1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic udelay 165 */ 166 #ifndef dmub_udelay 167 #define dmub_udelay(microseconds) udelay(microseconds) 168 #endif 169 170 #pragma pack(push, 1) 171 #define ABM_NUM_OF_ACE_SEGMENTS 5 172 173 /** 174 * Debug FW state offset 175 */ 176 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 177 178 union abm_flags { 179 struct { 180 /** 181 * @abm_enabled: Indicates if ABM is enabled. 182 */ 183 unsigned int abm_enabled : 1; 184 185 /** 186 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 187 */ 188 unsigned int disable_abm_requested : 1; 189 190 /** 191 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 192 */ 193 unsigned int disable_abm_immediately : 1; 194 195 /** 196 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 197 * to be disabled immediately and keep gain. 198 */ 199 unsigned int disable_abm_immediate_keep_gain : 1; 200 201 /** 202 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 203 */ 204 unsigned int fractional_pwm : 1; 205 206 /** 207 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 208 * of user backlight level. 209 */ 210 unsigned int abm_gradual_bl_change : 1; 211 212 /** 213 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 214 */ 215 unsigned int abm_new_frame : 1; 216 217 /** 218 * @vb_scaling_enabled: Indicates variBright Scaling Enable 219 */ 220 unsigned int vb_scaling_enabled : 1; 221 } bitfields; 222 223 unsigned int u32All; 224 }; 225 226 struct abm_save_restore { 227 /** 228 * @flags: Misc. ABM flags. 229 */ 230 union abm_flags flags; 231 232 /** 233 * @pause: true: pause ABM and get state 234 * false: unpause ABM after setting state 235 */ 236 uint32_t pause; 237 238 /** 239 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 240 */ 241 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 242 243 /** 244 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 245 */ 246 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 247 248 /** 249 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 250 */ 251 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 252 253 254 /** 255 * @knee_threshold: Current x-position of ACE knee (u0.16). 256 */ 257 uint32_t knee_threshold; 258 /** 259 * @current_gain: Current backlight reduction (u16.16). 260 */ 261 uint32_t current_gain; 262 /** 263 * @curr_bl_level: Current actual backlight level converging to target backlight level. 264 */ 265 uint16_t curr_bl_level; 266 267 /** 268 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 269 */ 270 uint16_t curr_user_bl_level; 271 272 }; 273 274 /** 275 * union dmub_addr - DMUB physical/virtual 64-bit address. 276 */ 277 union dmub_addr { 278 struct { 279 uint32_t low_part; /**< Lower 32 bits */ 280 uint32_t high_part; /**< Upper 32 bits */ 281 } u; /*<< Low/high bit access */ 282 uint64_t quad_part; /*<< 64 bit address */ 283 }; 284 #pragma pack(pop) 285 286 /** 287 * Dirty rect definition. 288 */ 289 struct dmub_rect { 290 /** 291 * Dirty rect x offset. 292 */ 293 uint32_t x; 294 295 /** 296 * Dirty rect y offset. 297 */ 298 uint32_t y; 299 300 /** 301 * Dirty rect width. 302 */ 303 uint32_t width; 304 305 /** 306 * Dirty rect height. 307 */ 308 uint32_t height; 309 }; 310 311 /** 312 * Flags that can be set by driver to change some PSR behaviour. 313 */ 314 union dmub_psr_debug_flags { 315 /** 316 * Debug flags. 317 */ 318 struct { 319 /** 320 * Enable visual confirm in FW. 321 */ 322 uint32_t visual_confirm : 1; 323 324 /** 325 * Force all selective updates to bw full frame updates. 326 */ 327 uint32_t force_full_frame_update : 1; 328 329 /** 330 * Use HW Lock Mgr object to do HW locking in FW. 331 */ 332 uint32_t use_hw_lock_mgr : 1; 333 334 /** 335 * Use TPS3 signal when restore main link. 336 */ 337 uint32_t force_wakeup_by_tps3 : 1; 338 339 /** 340 * Back to back flip, therefore cannot power down PHY 341 */ 342 uint32_t back_to_back_flip : 1; 343 344 /** 345 * Enable visual confirm for IPS 346 */ 347 uint32_t enable_ips_visual_confirm : 1; 348 } bitfields; 349 350 /** 351 * Union for debug flags. 352 */ 353 uint32_t u32All; 354 }; 355 356 /** 357 * Flags that can be set by driver to change some Replay behaviour. 358 */ 359 union replay_debug_flags { 360 struct { 361 /** 362 * 0x1 (bit 0) 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * 0x2 (bit 1) 369 * @skip_crc: Set if need to skip CRC. 370 */ 371 uint32_t skip_crc : 1; 372 373 /** 374 * 0x4 (bit 2) 375 * @force_link_power_on: Force disable ALPM control 376 */ 377 uint32_t force_link_power_on : 1; 378 379 /** 380 * 0x8 (bit 3) 381 * @force_phy_power_on: Force phy power on 382 */ 383 uint32_t force_phy_power_on : 1; 384 385 /** 386 * 0x10 (bit 4) 387 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 388 */ 389 uint32_t timing_resync_disabled : 1; 390 391 /** 392 * 0x20 (bit 5) 393 * @skip_crtc_disabled: CRTC disable skipped 394 */ 395 uint32_t skip_crtc_disabled : 1; 396 397 /** 398 * 0x40 (bit 6) 399 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 400 */ 401 uint32_t force_defer_one_frame_update : 1; 402 403 /** 404 * 0x80 (bit 7) 405 * @disable_delay_alpm_on: Force disable delay alpm on 406 */ 407 uint32_t disable_delay_alpm_on : 1; 408 409 /** 410 * 0x100 (bit 8) 411 * @disable_desync_error_check: Force disable desync error check 412 */ 413 uint32_t disable_desync_error_check : 1; 414 415 /** 416 * 0x200 (bit 9) 417 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 418 */ 419 uint32_t force_self_update_when_abm_non_steady : 1; 420 421 /** 422 * 0x400 (bit 10) 423 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 424 * If we enter IPS2, the Visual confirm bar will change to yellow 425 */ 426 uint32_t enable_ips_visual_confirm : 1; 427 428 /** 429 * 0x800 (bit 11) 430 * @enable_ips_residency_profiling: Enable IPS residency profiling 431 */ 432 uint32_t enable_ips_residency_profiling : 1; 433 434 uint32_t reserved : 20; 435 } bitfields; 436 437 uint32_t u32All; 438 }; 439 440 union replay_hw_flags { 441 struct { 442 /** 443 * @allow_alpm_fw_standby_mode: To indicate whether the 444 * ALPM FW standby mode is allowed 445 */ 446 uint32_t allow_alpm_fw_standby_mode : 1; 447 448 /* 449 * @dsc_enable_status: DSC enable status in driver 450 */ 451 uint32_t dsc_enable_status : 1; 452 453 /** 454 * @fec_enable_status: receive fec enable/disable status from driver 455 */ 456 uint32_t fec_enable_status : 1; 457 458 /* 459 * @smu_optimizations_en: SMU power optimization. 460 * Only when active display is Replay capable and display enters Replay. 461 * Trigger interrupt to SMU to powerup/down. 462 */ 463 uint32_t smu_optimizations_en : 1; 464 465 /** 466 * @phy_power_state: Indicates current phy power state 467 */ 468 uint32_t phy_power_state : 1; 469 470 /** 471 * @link_power_state: Indicates current link power state 472 */ 473 uint32_t link_power_state : 1; 474 /** 475 * Use TPS3 signal when restore main link. 476 */ 477 uint32_t force_wakeup_by_tps3 : 1; 478 /** 479 * @is_alpm_initialized: Indicates whether ALPM is initialized 480 */ 481 uint32_t is_alpm_initialized : 1; 482 } bitfields; 483 484 uint32_t u32All; 485 }; 486 487 union fw_assisted_mclk_switch_version { 488 struct { 489 uint8_t minor : 5; 490 uint8_t major : 3; 491 }; 492 uint8_t ver; 493 }; 494 495 /** 496 * DMUB feature capabilities. 497 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 498 */ 499 struct dmub_feature_caps { 500 /** 501 * Max PSR version supported by FW. 502 */ 503 uint8_t psr; 504 uint8_t fw_assisted_mclk_switch_ver; 505 uint8_t reserved[4]; 506 uint8_t subvp_psr_support; 507 uint8_t gecc_enable; 508 uint8_t replay_supported; 509 uint8_t replay_reserved[3]; 510 uint8_t abm_aux_backlight_support; 511 }; 512 513 struct dmub_visual_confirm_color { 514 /** 515 * Maximum 10 bits color value 516 */ 517 uint16_t color_r_cr; 518 uint16_t color_g_y; 519 uint16_t color_b_cb; 520 uint16_t panel_inst; 521 }; 522 523 //============================================================================== 524 //</DMUB_TYPES>================================================================= 525 //============================================================================== 526 //< DMUB_META>================================================================== 527 //============================================================================== 528 #pragma pack(push, 1) 529 530 /* Magic value for identifying dmub_fw_meta_info */ 531 #define DMUB_FW_META_MAGIC 0x444D5542 532 533 /* Offset from the end of the file to the dmub_fw_meta_info */ 534 #define DMUB_FW_META_OFFSET 0x24 535 536 /** 537 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 538 */ 539 union dmub_fw_meta_feature_bits { 540 struct { 541 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 542 uint32_t reserved : 31; 543 } bits; /**< status bits */ 544 uint32_t all; /**< 32-bit access to status bits */ 545 }; 546 547 /** 548 * struct dmub_fw_meta_info - metadata associated with fw binary 549 * 550 * NOTE: This should be considered a stable API. Fields should 551 * not be repurposed or reordered. New fields should be 552 * added instead to extend the structure. 553 * 554 * @magic_value: magic value identifying DMUB firmware meta info 555 * @fw_region_size: size of the firmware state region 556 * @trace_buffer_size: size of the tracebuffer region 557 * @fw_version: the firmware version information 558 * @dal_fw: 1 if the firmware is DAL 559 * @shared_state_size: size of the shared state region in bytes 560 * @shared_state_features: number of shared state features 561 */ 562 struct dmub_fw_meta_info { 563 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 564 uint32_t fw_region_size; /**< size of the firmware state region */ 565 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 566 uint32_t fw_version; /**< the firmware version information */ 567 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 568 uint8_t reserved[3]; /**< padding bits */ 569 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 570 uint16_t shared_state_features; /**< number of shared state features */ 571 uint16_t reserved2; /**< padding bytes */ 572 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 573 }; 574 575 /** 576 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 577 */ 578 union dmub_fw_meta { 579 struct dmub_fw_meta_info info; /**< metadata info */ 580 uint8_t reserved[64]; /**< padding bits */ 581 }; 582 583 #pragma pack(pop) 584 585 //============================================================================== 586 //< DMUB Trace Buffer>================================================================ 587 //============================================================================== 588 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 589 /** 590 * dmub_trace_code_t - firmware trace code, 32-bits 591 */ 592 typedef uint32_t dmub_trace_code_t; 593 594 /** 595 * struct dmcub_trace_buf_entry - Firmware trace entry 596 */ 597 struct dmcub_trace_buf_entry { 598 dmub_trace_code_t trace_code; /**< trace code for the event */ 599 uint32_t tick_count; /**< the tick count at time of trace */ 600 uint32_t param0; /**< trace defined parameter 0 */ 601 uint32_t param1; /**< trace defined parameter 1 */ 602 }; 603 #endif 604 605 //============================================================================== 606 //< DMUB_STATUS>================================================================ 607 //============================================================================== 608 609 /** 610 * DMCUB scratch registers can be used to determine firmware status. 611 * Current scratch register usage is as follows: 612 * 613 * SCRATCH0: FW Boot Status register 614 * SCRATCH5: LVTMA Status Register 615 * SCRATCH15: FW Boot Options register 616 */ 617 618 /** 619 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 620 */ 621 union dmub_fw_boot_status { 622 struct { 623 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 624 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 625 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 626 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 627 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 628 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 629 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 630 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 631 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 632 } bits; /**< status bits */ 633 uint32_t all; /**< 32-bit access to status bits */ 634 }; 635 636 /** 637 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 638 */ 639 enum dmub_fw_boot_status_bit { 640 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 641 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 642 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 643 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 644 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 645 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 646 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 647 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 648 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 649 }; 650 651 /* Register bit definition for SCRATCH5 */ 652 union dmub_lvtma_status { 653 struct { 654 uint32_t psp_ok : 1; 655 uint32_t edp_on : 1; 656 uint32_t reserved : 30; 657 } bits; 658 uint32_t all; 659 }; 660 661 enum dmub_lvtma_status_bit { 662 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 663 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 664 }; 665 666 enum dmub_ips_disable_type { 667 DMUB_IPS_ENABLE = 0, 668 DMUB_IPS_DISABLE_ALL = 1, 669 DMUB_IPS_DISABLE_IPS1 = 2, 670 DMUB_IPS_DISABLE_IPS2 = 3, 671 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 672 DMUB_IPS_DISABLE_DYNAMIC = 5, 673 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 674 }; 675 676 #define DMUB_IPS1_ALLOW_MASK 0x00000001 677 #define DMUB_IPS2_ALLOW_MASK 0x00000002 678 #define DMUB_IPS1_COMMIT_MASK 0x00000004 679 #define DMUB_IPS2_COMMIT_MASK 0x00000008 680 681 /** 682 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 683 */ 684 union dmub_fw_boot_options { 685 struct { 686 uint32_t pemu_env : 1; /**< 1 if PEMU */ 687 uint32_t fpga_env : 1; /**< 1 if FPGA */ 688 uint32_t optimized_init : 1; /**< 1 if optimized init */ 689 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 690 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 691 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 692 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 693 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 694 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 695 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 696 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 697 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 698 uint32_t power_optimization: 1; 699 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 700 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 701 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 702 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 703 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 704 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 705 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 706 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 707 uint32_t ips_disable: 3; /* options to disable ips support*/ 708 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 709 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 710 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 711 uint32_t reserved : 6; /**< reserved */ 712 } bits; /**< boot bits */ 713 uint32_t all; /**< 32-bit access to bits */ 714 }; 715 716 enum dmub_fw_boot_options_bit { 717 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 718 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 719 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 720 }; 721 722 //============================================================================== 723 //< DMUB_SHARED_STATE>========================================================== 724 //============================================================================== 725 726 /** 727 * Shared firmware state between driver and firmware for lockless communication 728 * in situations where the inbox/outbox may be unavailable. 729 * 730 * Each structure *must* be at most 256-bytes in size. The layout allocation is 731 * described below: 732 * 733 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 734 */ 735 736 /** 737 * enum dmub_shared_state_feature_id - List of shared state features. 738 */ 739 enum dmub_shared_state_feature_id { 740 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 741 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 742 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 743 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 744 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 745 }; 746 747 /** 748 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 749 */ 750 union dmub_shared_state_ips_fw_signals { 751 struct { 752 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 753 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 754 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 755 uint32_t detection_required : 1; /**< 1 if detection is required */ 756 uint32_t reserved_bits : 28; /**< Reversed */ 757 } bits; 758 uint32_t all; 759 }; 760 761 /** 762 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 763 */ 764 union dmub_shared_state_ips_driver_signals { 765 struct { 766 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 767 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 768 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 769 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 770 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 771 uint32_t reserved_bits : 27; /**< Reversed bits */ 772 } bits; 773 uint32_t all; 774 }; 775 776 /** 777 * IPS FW Version 778 */ 779 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 780 781 struct dmub_shared_state_debug_setup { 782 union { 783 struct { 784 uint32_t exclude_points[62]; 785 } profile_mode; 786 }; 787 }; 788 789 /** 790 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 791 */ 792 struct dmub_shared_state_ips_fw { 793 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 794 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 795 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 796 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 797 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 798 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 799 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 800 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 801 }; /* 248-bytes, fixed */ 802 803 /** 804 * IPS Driver Version 805 */ 806 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 807 808 /** 809 * struct dmub_shared_state_ips_driver - Driver state for IPS. 810 */ 811 struct dmub_shared_state_ips_driver { 812 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 813 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 814 }; /* 248-bytes, fixed */ 815 816 /** 817 * enum dmub_shared_state_feature_common - Generic payload. 818 */ 819 struct dmub_shared_state_feature_common { 820 uint32_t padding[62]; 821 }; /* 248-bytes, fixed */ 822 823 /** 824 * enum dmub_shared_state_feature_header - Feature description. 825 */ 826 struct dmub_shared_state_feature_header { 827 uint16_t id; /**< Feature ID */ 828 uint16_t version; /**< Feature version */ 829 uint32_t reserved; /**< Reserved bytes. */ 830 }; /* 8 bytes, fixed */ 831 832 /** 833 * struct dmub_shared_state_feature_block - Feature block. 834 */ 835 struct dmub_shared_state_feature_block { 836 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 837 union dmub_shared_feature_state_union { 838 struct dmub_shared_state_feature_common common; /**< Generic data */ 839 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 840 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 841 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 842 } data; /**< Shared state data. */ 843 }; /* 256-bytes, fixed */ 844 845 /** 846 * Shared state size in bytes. 847 */ 848 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 849 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 850 851 //============================================================================== 852 //</DMUB_STATUS>================================================================ 853 //============================================================================== 854 //< DMUB_VBIOS>================================================================= 855 //============================================================================== 856 857 /* 858 * enum dmub_cmd_vbios_type - VBIOS commands. 859 * 860 * Command IDs should be treated as stable ABI. 861 * Do not reuse or modify IDs. 862 */ 863 enum dmub_cmd_vbios_type { 864 /** 865 * Configures the DIG encoder. 866 */ 867 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 868 /** 869 * Controls the PHY. 870 */ 871 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 872 /** 873 * Sets the pixel clock/symbol clock. 874 */ 875 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 876 /** 877 * Enables or disables power gating. 878 */ 879 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 880 /** 881 * Controls embedded panels. 882 */ 883 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 884 /** 885 * Query DP alt status on a transmitter. 886 */ 887 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 888 /** 889 * Control PHY FSM 890 */ 891 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 892 /** 893 * Controls domain power gating 894 */ 895 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 896 }; 897 898 //============================================================================== 899 //</DMUB_VBIOS>================================================================= 900 //============================================================================== 901 //< DMUB_GPINT>================================================================= 902 //============================================================================== 903 904 /** 905 * The shifts and masks below may alternatively be used to format and read 906 * the command register bits. 907 */ 908 909 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 910 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 911 912 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 913 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 914 915 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 916 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 917 918 /** 919 * Command responses. 920 */ 921 922 /** 923 * Return response for DMUB_GPINT__STOP_FW command. 924 */ 925 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 926 927 /** 928 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 929 */ 930 union dmub_gpint_data_register { 931 struct { 932 uint32_t param : 16; /**< 16-bit parameter */ 933 uint32_t command_code : 12; /**< GPINT command */ 934 uint32_t status : 4; /**< Command status bit */ 935 } bits; /**< GPINT bit access */ 936 uint32_t all; /**< GPINT 32-bit access */ 937 }; 938 939 /* 940 * enum dmub_gpint_command - GPINT command to DMCUB FW 941 * 942 * Command IDs should be treated as stable ABI. 943 * Do not reuse or modify IDs. 944 */ 945 enum dmub_gpint_command { 946 /** 947 * Invalid command, ignored. 948 */ 949 DMUB_GPINT__INVALID_COMMAND = 0, 950 /** 951 * DESC: Queries the firmware version. 952 * RETURN: Firmware version. 953 */ 954 DMUB_GPINT__GET_FW_VERSION = 1, 955 /** 956 * DESC: Halts the firmware. 957 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 958 */ 959 DMUB_GPINT__STOP_FW = 2, 960 /** 961 * DESC: Get PSR state from FW. 962 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 963 */ 964 DMUB_GPINT__GET_PSR_STATE = 7, 965 /** 966 * DESC: Notifies DMCUB of the currently active streams. 967 * ARGS: Stream mask, 1 bit per active stream index. 968 */ 969 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 970 /** 971 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 972 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 973 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 974 * RETURN: PSR residency in milli-percent. 975 */ 976 DMUB_GPINT__PSR_RESIDENCY = 9, 977 978 /** 979 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 980 */ 981 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 982 983 /** 984 * DESC: Get REPLAY state from FW. 985 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 986 */ 987 DMUB_GPINT__GET_REPLAY_STATE = 13, 988 989 /** 990 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 991 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 992 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 993 * RETURN: REPLAY residency in milli-percent. 994 */ 995 DMUB_GPINT__REPLAY_RESIDENCY = 14, 996 997 /** 998 * DESC: Copy bounding box to the host. 999 * ARGS: Version of bounding box to copy 1000 * RETURN: Result of copying bounding box 1001 */ 1002 DMUB_GPINT__BB_COPY = 96, 1003 1004 /** 1005 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1006 * ARGS: The word3 for the 64 bit address 1007 */ 1008 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1009 1010 /** 1011 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1012 * ARGS: The word2 for the 64 bit address 1013 */ 1014 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1015 1016 /** 1017 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1018 * ARGS: The word1 for the 64 bit address 1019 */ 1020 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1021 1022 /** 1023 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1024 * ARGS: The word0 for the 64 bit address 1025 */ 1026 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1027 1028 /** 1029 * DESC: Updates the trace buffer lower 32-bit mask. 1030 * ARGS: The new mask 1031 * RETURN: Lower 32-bit mask. 1032 */ 1033 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1034 1035 /** 1036 * DESC: Updates the trace buffer mask bit0~bit15. 1037 * ARGS: The new mask 1038 * RETURN: Lower 32-bit mask. 1039 */ 1040 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1041 1042 /** 1043 * DESC: Updates the trace buffer mask bit16~bit31. 1044 * ARGS: The new mask 1045 * RETURN: Lower 32-bit mask. 1046 */ 1047 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1048 1049 /** 1050 * DESC: Updates the trace buffer mask bit32~bit47. 1051 * ARGS: The new mask 1052 * RETURN: Lower 32-bit mask. 1053 */ 1054 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1055 1056 /** 1057 * DESC: Updates the trace buffer mask bit48~bit63. 1058 * ARGS: The new mask 1059 * RETURN: Lower 32-bit mask. 1060 */ 1061 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1062 1063 /** 1064 * DESC: Read the trace buffer mask bi0~bit15. 1065 */ 1066 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1067 1068 /** 1069 * DESC: Read the trace buffer mask bit16~bit31. 1070 */ 1071 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1072 1073 /** 1074 * DESC: Read the trace buffer mask bi32~bit47. 1075 */ 1076 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1077 1078 /** 1079 * DESC: Updates the trace buffer mask bit32~bit63. 1080 */ 1081 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1082 1083 /** 1084 * DESC: Set IPS residency measurement 1085 * ARGS: 0 - Disable ips measurement 1086 * 1 - Enable ips measurement 1087 */ 1088 DMUB_GPINT__IPS_RESIDENCY = 121, 1089 1090 /** 1091 * DESC: Enable measurements for various task duration 1092 * ARGS: 0 - Disable measurement 1093 * 1 - Enable measurement 1094 */ 1095 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1096 1097 /** 1098 * DESC: Gets IPS residency in microseconds 1099 * ARGS: 0 - Return IPS1 residency 1100 * 1 - Return IPS2 residency 1101 * 2 - Return IPS1_RCG residency 1102 * 3 - Return IPS1_ONO2_ON residency 1103 * RETURN: Total residency in microseconds - lower 32 bits 1104 */ 1105 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1106 1107 /** 1108 * DESC: Gets IPS1 histogram counts 1109 * ARGS: Bucket index 1110 * RETURN: Total count for the bucket 1111 */ 1112 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1113 1114 /** 1115 * DESC: Gets IPS2 histogram counts 1116 * ARGS: Bucket index 1117 * RETURN: Total count for the bucket 1118 */ 1119 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1120 1121 /** 1122 * DESC: Gets IPS residency 1123 * ARGS: 0 - Return IPS1 residency 1124 * 1 - Return IPS2 residency 1125 * 2 - Return IPS1_RCG residency 1126 * 3 - Return IPS1_ONO2_ON residency 1127 * RETURN: Total residency in milli-percent. 1128 */ 1129 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1130 1131 /** 1132 * DESC: Gets IPS1_RCG histogram counts 1133 * ARGS: Bucket index 1134 * RETURN: Total count for the bucket 1135 */ 1136 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1137 1138 /** 1139 * DESC: Gets IPS1_ONO2_ON histogram counts 1140 * ARGS: Bucket index 1141 * RETURN: Total count for the bucket 1142 */ 1143 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1144 1145 /** 1146 * DESC: Gets IPS entry counter during residency measurement 1147 * ARGS: 0 - Return IPS1 entry counts 1148 * 1 - Return IPS2 entry counts 1149 * 2 - Return IPS1_RCG entry counts 1150 * 3 - Return IPS2_ONO2_ON entry counts 1151 * RETURN: Entry counter for selected IPS mode 1152 */ 1153 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1154 1155 /** 1156 * DESC: Gets IPS inactive residency in microseconds 1157 * ARGS: 0 - Return IPS1_MAX residency 1158 * 1 - Return IPS2 residency 1159 * 2 - Return IPS1_RCG residency 1160 * 3 - Return IPS1_ONO2_ON residency 1161 * RETURN: Total inactive residency in microseconds - lower 32 bits 1162 */ 1163 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1164 1165 /** 1166 * DESC: Gets IPS inactive residency in microseconds 1167 * ARGS: 0 - Return IPS1_MAX residency 1168 * 1 - Return IPS2 residency 1169 * 2 - Return IPS1_RCG residency 1170 * 3 - Return IPS1_ONO2_ON residency 1171 * RETURN: Total inactive residency in microseconds - upper 32 bits 1172 */ 1173 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1174 1175 /** 1176 * DESC: Gets IPS residency in microseconds 1177 * ARGS: 0 - Return IPS1 residency 1178 * 1 - Return IPS2 residency 1179 * 2 - Return IPS1_RCG residency 1180 * 3 - Return IPS1_ONO2_ON residency 1181 * RETURN: Total residency in microseconds - upper 32 bits 1182 */ 1183 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1184 /** 1185 * DESC: Setup debug configs. 1186 */ 1187 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1188 }; 1189 1190 /** 1191 * INBOX0 generic command definition 1192 */ 1193 union dmub_inbox0_cmd_common { 1194 struct { 1195 uint32_t command_code: 8; /**< INBOX0 command code */ 1196 uint32_t param: 24; /**< 24-bit parameter */ 1197 } bits; 1198 uint32_t all; 1199 }; 1200 1201 /** 1202 * INBOX0 hw_lock command definition 1203 */ 1204 union dmub_inbox0_cmd_lock_hw { 1205 struct { 1206 uint32_t command_code: 8; 1207 1208 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1209 uint32_t hw_lock_client: 2; 1210 1211 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1212 uint32_t otg_inst: 3; 1213 uint32_t opp_inst: 3; 1214 uint32_t dig_inst: 3; 1215 1216 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1217 uint32_t lock_pipe: 1; 1218 uint32_t lock_cursor: 1; 1219 uint32_t lock_dig: 1; 1220 uint32_t triple_buffer_lock: 1; 1221 1222 uint32_t lock: 1; /**< Lock */ 1223 uint32_t should_release: 1; /**< Release */ 1224 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1225 } bits; 1226 uint32_t all; 1227 }; 1228 1229 union dmub_inbox0_data_register { 1230 union dmub_inbox0_cmd_common inbox0_cmd_common; 1231 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1232 }; 1233 1234 enum dmub_inbox0_command { 1235 /** 1236 * DESC: Invalid command, ignored. 1237 */ 1238 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1239 /** 1240 * DESC: Notification to acquire/release HW lock 1241 * ARGS: 1242 */ 1243 DMUB_INBOX0_CMD__HW_LOCK = 1, 1244 }; 1245 //============================================================================== 1246 //</DMUB_GPINT>================================================================= 1247 //============================================================================== 1248 //< DMUB_CMD>=================================================================== 1249 //============================================================================== 1250 1251 /** 1252 * Size in bytes of each DMUB command. 1253 */ 1254 #define DMUB_RB_CMD_SIZE 64 1255 1256 /** 1257 * Maximum number of items in the DMUB ringbuffer. 1258 */ 1259 #define DMUB_RB_MAX_ENTRY 128 1260 1261 /** 1262 * Ringbuffer size in bytes. 1263 */ 1264 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1265 1266 /** 1267 * REG_SET mask for reg offload. 1268 */ 1269 #define REG_SET_MASK 0xFFFF 1270 1271 /* 1272 * enum dmub_cmd_type - DMUB inbox command. 1273 * 1274 * Command IDs should be treated as stable ABI. 1275 * Do not reuse or modify IDs. 1276 */ 1277 enum dmub_cmd_type { 1278 /** 1279 * Invalid command. 1280 */ 1281 DMUB_CMD__NULL = 0, 1282 /** 1283 * Read modify write register sequence offload. 1284 */ 1285 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1286 /** 1287 * Field update register sequence offload. 1288 */ 1289 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1290 /** 1291 * Burst write sequence offload. 1292 */ 1293 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1294 /** 1295 * Reg wait sequence offload. 1296 */ 1297 DMUB_CMD__REG_REG_WAIT = 4, 1298 /** 1299 * Workaround to avoid HUBP underflow during NV12 playback. 1300 */ 1301 DMUB_CMD__PLAT_54186_WA = 5, 1302 /** 1303 * Command type used to query FW feature caps. 1304 */ 1305 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1306 /** 1307 * Command type used to get visual confirm color. 1308 */ 1309 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1310 /** 1311 * Command type used for all PSR commands. 1312 */ 1313 DMUB_CMD__PSR = 64, 1314 /** 1315 * Command type used for all MALL commands. 1316 */ 1317 DMUB_CMD__MALL = 65, 1318 /** 1319 * Command type used for all ABM commands. 1320 */ 1321 DMUB_CMD__ABM = 66, 1322 /** 1323 * Command type used to update dirty rects in FW. 1324 */ 1325 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1326 /** 1327 * Command type used to update cursor info in FW. 1328 */ 1329 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1330 /** 1331 * Command type used for HW locking in FW. 1332 */ 1333 DMUB_CMD__HW_LOCK = 69, 1334 /** 1335 * Command type used to access DP AUX. 1336 */ 1337 DMUB_CMD__DP_AUX_ACCESS = 70, 1338 /** 1339 * Command type used for OUTBOX1 notification enable 1340 */ 1341 DMUB_CMD__OUTBOX1_ENABLE = 71, 1342 1343 /** 1344 * Command type used for all idle optimization commands. 1345 */ 1346 DMUB_CMD__IDLE_OPT = 72, 1347 /** 1348 * Command type used for all clock manager commands. 1349 */ 1350 DMUB_CMD__CLK_MGR = 73, 1351 /** 1352 * Command type used for all panel control commands. 1353 */ 1354 DMUB_CMD__PANEL_CNTL = 74, 1355 1356 /** 1357 * Command type used for all CAB commands. 1358 */ 1359 DMUB_CMD__CAB_FOR_SS = 75, 1360 1361 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1362 1363 /** 1364 * Command type used for interfacing with DPIA. 1365 */ 1366 DMUB_CMD__DPIA = 77, 1367 /** 1368 * Command type used for EDID CEA parsing 1369 */ 1370 DMUB_CMD__EDID_CEA = 79, 1371 /** 1372 * Command type used for getting usbc cable ID 1373 */ 1374 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1375 /** 1376 * Command type used to query HPD state. 1377 */ 1378 DMUB_CMD__QUERY_HPD_STATE = 82, 1379 /** 1380 * Command type used for all VBIOS interface commands. 1381 */ 1382 /** 1383 * Command type used for all REPLAY commands. 1384 */ 1385 DMUB_CMD__REPLAY = 83, 1386 1387 /** 1388 * Command type used for all SECURE_DISPLAY commands. 1389 */ 1390 DMUB_CMD__SECURE_DISPLAY = 85, 1391 1392 /** 1393 * Command type used to set DPIA HPD interrupt state 1394 */ 1395 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1396 1397 /** 1398 * Command type used for all PSP commands. 1399 */ 1400 DMUB_CMD__PSP = 88, 1401 1402 DMUB_CMD__VBIOS = 128, 1403 }; 1404 1405 /** 1406 * enum dmub_out_cmd_type - DMUB outbox commands. 1407 */ 1408 enum dmub_out_cmd_type { 1409 /** 1410 * Invalid outbox command, ignored. 1411 */ 1412 DMUB_OUT_CMD__NULL = 0, 1413 /** 1414 * Command type used for DP AUX Reply data notification 1415 */ 1416 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1417 /** 1418 * Command type used for DP HPD event notification 1419 */ 1420 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1421 /** 1422 * Command type used for SET_CONFIG Reply notification 1423 */ 1424 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1425 /** 1426 * Command type used for USB4 DPIA notification 1427 */ 1428 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1429 /** 1430 * Command type used for HPD redetect notification 1431 */ 1432 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1433 }; 1434 1435 /* DMUB_CMD__DPIA command sub-types. */ 1436 enum dmub_cmd_dpia_type { 1437 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1438 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1439 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1440 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1441 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1442 }; 1443 1444 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1445 enum dmub_cmd_dpia_notification_type { 1446 DPIA_NOTIFY__BW_ALLOCATION = 0, 1447 }; 1448 1449 #pragma pack(push, 1) 1450 1451 /** 1452 * struct dmub_cmd_header - Common command header fields. 1453 */ 1454 struct dmub_cmd_header { 1455 unsigned int type : 8; /**< command type */ 1456 unsigned int sub_type : 8; /**< command sub type */ 1457 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1458 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1459 unsigned int reserved0 : 6; /**< reserved bits */ 1460 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1461 unsigned int reserved1 : 2; /**< reserved bits */ 1462 }; 1463 1464 /* 1465 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1466 * 1467 * 60 payload bytes can hold up to 5 sets of read modify writes, 1468 * each take 3 dwords. 1469 * 1470 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1471 * 1472 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1473 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1474 */ 1475 struct dmub_cmd_read_modify_write_sequence { 1476 uint32_t addr; /**< register address */ 1477 uint32_t modify_mask; /**< modify mask */ 1478 uint32_t modify_value; /**< modify value */ 1479 }; 1480 1481 /** 1482 * Maximum number of ops in read modify write sequence. 1483 */ 1484 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1485 1486 /** 1487 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1488 */ 1489 struct dmub_rb_cmd_read_modify_write { 1490 struct dmub_cmd_header header; /**< command header */ 1491 /** 1492 * Read modify write sequence. 1493 */ 1494 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1495 }; 1496 1497 /* 1498 * Update a register with specified masks and values sequeunce 1499 * 1500 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1501 * 1502 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1503 * 1504 * 1505 * USE CASE: 1506 * 1. auto-increment register where additional read would update pointer and produce wrong result 1507 * 2. toggle a bit without read in the middle 1508 */ 1509 1510 struct dmub_cmd_reg_field_update_sequence { 1511 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1512 uint32_t modify_value; /**< value to update with */ 1513 }; 1514 1515 /** 1516 * Maximum number of ops in field update sequence. 1517 */ 1518 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1519 1520 /** 1521 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1522 */ 1523 struct dmub_rb_cmd_reg_field_update_sequence { 1524 struct dmub_cmd_header header; /**< command header */ 1525 uint32_t addr; /**< register address */ 1526 /** 1527 * Field update sequence. 1528 */ 1529 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1530 }; 1531 1532 1533 /** 1534 * Maximum number of burst write values. 1535 */ 1536 #define DMUB_BURST_WRITE_VALUES__MAX 14 1537 1538 /* 1539 * struct dmub_rb_cmd_burst_write - Burst write 1540 * 1541 * support use case such as writing out LUTs. 1542 * 1543 * 60 payload bytes can hold up to 14 values to write to given address 1544 * 1545 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1546 */ 1547 struct dmub_rb_cmd_burst_write { 1548 struct dmub_cmd_header header; /**< command header */ 1549 uint32_t addr; /**< register start address */ 1550 /** 1551 * Burst write register values. 1552 */ 1553 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1554 }; 1555 1556 /** 1557 * struct dmub_rb_cmd_common - Common command header 1558 */ 1559 struct dmub_rb_cmd_common { 1560 struct dmub_cmd_header header; /**< command header */ 1561 /** 1562 * Padding to RB_CMD_SIZE 1563 */ 1564 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1565 }; 1566 1567 /** 1568 * struct dmub_cmd_reg_wait_data - Register wait data 1569 */ 1570 struct dmub_cmd_reg_wait_data { 1571 uint32_t addr; /**< Register address */ 1572 uint32_t mask; /**< Mask for register bits */ 1573 uint32_t condition_field_value; /**< Value to wait for */ 1574 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1575 }; 1576 1577 /** 1578 * struct dmub_rb_cmd_reg_wait - Register wait command 1579 */ 1580 struct dmub_rb_cmd_reg_wait { 1581 struct dmub_cmd_header header; /**< Command header */ 1582 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1583 }; 1584 1585 /** 1586 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1587 * 1588 * Reprograms surface parameters to avoid underflow. 1589 */ 1590 struct dmub_cmd_PLAT_54186_wa { 1591 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1592 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1593 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1594 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1595 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1596 struct { 1597 uint32_t hubp_inst : 4; /**< HUBP instance */ 1598 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1599 uint32_t immediate :1; /**< Immediate flip */ 1600 uint32_t vmid : 4; /**< VMID */ 1601 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1602 uint32_t reserved : 21; /**< Reserved */ 1603 } flip_params; /**< Pageflip parameters */ 1604 uint32_t reserved[9]; /**< Reserved bits */ 1605 }; 1606 1607 /** 1608 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1609 */ 1610 struct dmub_rb_cmd_PLAT_54186_wa { 1611 struct dmub_cmd_header header; /**< Command header */ 1612 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1613 }; 1614 1615 /** 1616 * enum dmub_cmd_mall_type - MALL commands 1617 */ 1618 enum dmub_cmd_mall_type { 1619 /** 1620 * Allows display refresh from MALL. 1621 */ 1622 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1623 /** 1624 * Disallows display refresh from MALL. 1625 */ 1626 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1627 /** 1628 * Cursor copy for MALL. 1629 */ 1630 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1631 /** 1632 * Controls DF requests. 1633 */ 1634 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1635 }; 1636 1637 /** 1638 * struct dmub_rb_cmd_mall - MALL command data. 1639 */ 1640 struct dmub_rb_cmd_mall { 1641 struct dmub_cmd_header header; /**< Common command header */ 1642 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1643 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1644 uint32_t tmr_delay; /**< Timer delay */ 1645 uint32_t tmr_scale; /**< Timer scale */ 1646 uint16_t cursor_width; /**< Cursor width in pixels */ 1647 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1648 uint16_t cursor_height; /**< Cursor height in pixels */ 1649 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1650 uint8_t debug_bits; /**< Debug bits */ 1651 1652 uint8_t reserved1; /**< Reserved bits */ 1653 uint8_t reserved2; /**< Reserved bits */ 1654 }; 1655 1656 /** 1657 * enum dmub_cmd_cab_type - CAB command data. 1658 */ 1659 enum dmub_cmd_cab_type { 1660 /** 1661 * No idle optimizations (i.e. no CAB) 1662 */ 1663 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1664 /** 1665 * No DCN requests for memory 1666 */ 1667 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1668 /** 1669 * Fit surfaces in CAB (i.e. CAB enable) 1670 */ 1671 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1672 /** 1673 * Do not fit surfaces in CAB (i.e. no CAB) 1674 */ 1675 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1676 }; 1677 1678 /** 1679 * struct dmub_rb_cmd_cab - CAB command data. 1680 */ 1681 struct dmub_rb_cmd_cab_for_ss { 1682 struct dmub_cmd_header header; 1683 uint8_t cab_alloc_ways; /* total number of ways */ 1684 uint8_t debug_bits; /* debug bits */ 1685 }; 1686 1687 /** 1688 * Enum for indicating which MCLK switch mode per pipe 1689 */ 1690 enum mclk_switch_mode { 1691 NONE = 0, 1692 FPO = 1, 1693 SUBVP = 2, 1694 VBLANK = 3, 1695 }; 1696 1697 /* Per pipe struct which stores the MCLK switch mode 1698 * data to be sent to DMUB. 1699 * Named "v2" for now -- once FPO and SUBVP are fully merged 1700 * the type name can be updated 1701 */ 1702 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1703 union { 1704 struct { 1705 uint32_t pix_clk_100hz; 1706 uint16_t main_vblank_start; 1707 uint16_t main_vblank_end; 1708 uint16_t mall_region_lines; 1709 uint16_t prefetch_lines; 1710 uint16_t prefetch_to_mall_start_lines; 1711 uint16_t processing_delay_lines; 1712 uint16_t htotal; // required to calculate line time for multi-display cases 1713 uint16_t vtotal; 1714 uint8_t main_pipe_index; 1715 uint8_t phantom_pipe_index; 1716 /* Since the microschedule is calculated in terms of OTG lines, 1717 * include any scaling factors to make sure when we get accurate 1718 * conversion when programming MALL_START_LINE (which is in terms 1719 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1720 * is 1/2 (numerator = 1, denominator = 2). 1721 */ 1722 uint8_t scale_factor_numerator; 1723 uint8_t scale_factor_denominator; 1724 uint8_t is_drr; 1725 uint8_t main_split_pipe_index; 1726 uint8_t phantom_split_pipe_index; 1727 } subvp_data; 1728 1729 struct { 1730 uint32_t pix_clk_100hz; 1731 uint16_t vblank_start; 1732 uint16_t vblank_end; 1733 uint16_t vstartup_start; 1734 uint16_t vtotal; 1735 uint16_t htotal; 1736 uint8_t vblank_pipe_index; 1737 uint8_t padding[1]; 1738 struct { 1739 uint8_t drr_in_use; 1740 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1741 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1742 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1743 uint8_t use_ramping; // Use ramping or not 1744 uint8_t drr_vblank_start_margin; 1745 } drr_info; // DRR considered as part of SubVP + VBLANK case 1746 } vblank_data; 1747 } pipe_config; 1748 1749 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1750 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1751 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1752 */ 1753 uint8_t mode; // enum mclk_switch_mode 1754 }; 1755 1756 /** 1757 * Config data for Sub-VP and FPO 1758 * Named "v2" for now -- once FPO and SUBVP are fully merged 1759 * the type name can be updated 1760 */ 1761 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1762 uint16_t watermark_a_cache; 1763 uint8_t vertical_int_margin_us; 1764 uint8_t pstate_allow_width_us; 1765 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1766 }; 1767 1768 /** 1769 * DMUB rb command definition for Sub-VP and FPO 1770 * Named "v2" for now -- once FPO and SUBVP are fully merged 1771 * the type name can be updated 1772 */ 1773 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1774 struct dmub_cmd_header header; 1775 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1776 }; 1777 1778 struct dmub_flip_addr_info { 1779 uint32_t surf_addr_lo; 1780 uint32_t surf_addr_c_lo; 1781 uint32_t meta_addr_lo; 1782 uint32_t meta_addr_c_lo; 1783 uint16_t surf_addr_hi; 1784 uint16_t surf_addr_c_hi; 1785 uint16_t meta_addr_hi; 1786 uint16_t meta_addr_c_hi; 1787 }; 1788 1789 struct dmub_fams2_flip_info { 1790 union { 1791 struct { 1792 uint8_t is_immediate: 1; 1793 } bits; 1794 uint8_t all; 1795 } config; 1796 uint8_t otg_inst; 1797 uint8_t pipe_mask; 1798 uint8_t pad; 1799 struct dmub_flip_addr_info addr_info; 1800 }; 1801 1802 struct dmub_rb_cmd_fams2_flip { 1803 struct dmub_cmd_header header; 1804 struct dmub_fams2_flip_info flip_info; 1805 }; 1806 1807 struct dmub_optc_state_v2 { 1808 uint32_t v_total_min; 1809 uint32_t v_total_max; 1810 uint32_t v_total_mid; 1811 uint32_t v_total_mid_frame_num; 1812 uint8_t program_manual_trigger; 1813 uint8_t tg_inst; 1814 uint8_t pad[2]; 1815 }; 1816 1817 struct dmub_optc_position { 1818 uint32_t vpos; 1819 uint32_t hpos; 1820 uint32_t frame; 1821 }; 1822 1823 struct dmub_rb_cmd_fams2_drr_update { 1824 struct dmub_cmd_header header; 1825 struct dmub_optc_state_v2 dmub_optc_state_req; 1826 }; 1827 1828 /* HW and FW global configuration data for FAMS2 */ 1829 /* FAMS2 types and structs */ 1830 enum fams2_stream_type { 1831 FAMS2_STREAM_TYPE_NONE = 0, 1832 FAMS2_STREAM_TYPE_VBLANK = 1, 1833 FAMS2_STREAM_TYPE_VACTIVE = 2, 1834 FAMS2_STREAM_TYPE_DRR = 3, 1835 FAMS2_STREAM_TYPE_SUBVP = 4, 1836 }; 1837 1838 /* static stream state */ 1839 struct dmub_fams2_legacy_stream_static_state { 1840 uint8_t vactive_det_fill_delay_otg_vlines; 1841 uint8_t programming_delay_otg_vlines; 1842 }; //v0 1843 1844 struct dmub_fams2_subvp_stream_static_state { 1845 uint16_t vratio_numerator; 1846 uint16_t vratio_denominator; 1847 uint16_t phantom_vtotal; 1848 uint16_t phantom_vactive; 1849 union { 1850 struct { 1851 uint8_t is_multi_planar : 1; 1852 uint8_t is_yuv420 : 1; 1853 } bits; 1854 uint8_t all; 1855 } config; 1856 uint8_t programming_delay_otg_vlines; 1857 uint8_t prefetch_to_mall_otg_vlines; 1858 uint8_t phantom_otg_inst; 1859 uint8_t phantom_pipe_mask; 1860 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1861 }; //v0 1862 1863 struct dmub_fams2_drr_stream_static_state { 1864 uint16_t nom_stretched_vtotal; 1865 uint8_t programming_delay_otg_vlines; 1866 uint8_t only_stretch_if_required; 1867 uint8_t pad[2]; 1868 }; //v0 1869 1870 struct dmub_fams2_cmd_legacy_stream_static_state { 1871 uint16_t vactive_det_fill_delay_otg_vlines; 1872 uint16_t programming_delay_otg_vlines; 1873 }; //v1 1874 1875 struct dmub_fams2_cmd_subvp_stream_static_state { 1876 uint16_t vratio_numerator; 1877 uint16_t vratio_denominator; 1878 uint16_t phantom_vtotal; 1879 uint16_t phantom_vactive; 1880 uint16_t programming_delay_otg_vlines; 1881 uint16_t prefetch_to_mall_otg_vlines; 1882 union { 1883 struct { 1884 uint8_t is_multi_planar : 1; 1885 uint8_t is_yuv420 : 1; 1886 } bits; 1887 uint8_t all; 1888 } config; 1889 uint8_t phantom_otg_inst; 1890 uint8_t phantom_pipe_mask; 1891 uint8_t pad0; 1892 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1893 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 1894 }; //v1 1895 1896 struct dmub_fams2_cmd_drr_stream_static_state { 1897 uint16_t nom_stretched_vtotal; 1898 uint16_t programming_delay_otg_vlines; 1899 uint8_t only_stretch_if_required; 1900 uint8_t pad[3]; 1901 }; //v1 1902 1903 union dmub_fams2_stream_static_sub_state { 1904 struct dmub_fams2_legacy_stream_static_state legacy; 1905 struct dmub_fams2_subvp_stream_static_state subvp; 1906 struct dmub_fams2_drr_stream_static_state drr; 1907 }; //v0 1908 1909 union dmub_fams2_cmd_stream_static_sub_state { 1910 struct dmub_fams2_cmd_legacy_stream_static_state legacy; 1911 struct dmub_fams2_cmd_subvp_stream_static_state subvp; 1912 struct dmub_fams2_cmd_drr_stream_static_state drr; 1913 }; //v1 1914 1915 struct dmub_fams2_stream_static_state { 1916 enum fams2_stream_type type; 1917 uint32_t otg_vline_time_ns; 1918 uint32_t otg_vline_time_ticks; 1919 uint16_t htotal; 1920 uint16_t vtotal; // nominal vtotal 1921 uint16_t vblank_start; 1922 uint16_t vblank_end; 1923 uint16_t max_vtotal; 1924 uint16_t allow_start_otg_vline; 1925 uint16_t allow_end_otg_vline; 1926 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1927 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1928 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 1929 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1930 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1931 union { 1932 struct { 1933 uint8_t is_drr: 1; // stream is DRR enabled 1934 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 1935 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1936 } bits; 1937 uint8_t all; 1938 } config; 1939 uint8_t otg_inst; 1940 uint8_t pipe_mask; // pipe mask for the whole config 1941 uint8_t num_planes; 1942 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1943 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 1944 union dmub_fams2_stream_static_sub_state sub_state; 1945 }; //v0 1946 1947 struct dmub_fams2_cmd_stream_static_base_state { 1948 enum fams2_stream_type type; 1949 uint32_t otg_vline_time_ns; 1950 uint32_t otg_vline_time_ticks; 1951 uint16_t htotal; 1952 uint16_t vtotal; // nominal vtotal 1953 uint16_t vblank_start; 1954 uint16_t vblank_end; 1955 uint16_t max_vtotal; 1956 uint16_t allow_start_otg_vline; 1957 uint16_t allow_end_otg_vline; 1958 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1959 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1960 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 1961 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1962 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1963 union { 1964 struct { 1965 uint8_t is_drr : 1; // stream is DRR enabled 1966 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 1967 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1968 } bits; 1969 uint8_t all; 1970 } config; 1971 uint8_t otg_inst; 1972 uint8_t pipe_mask; // pipe mask for the whole config 1973 uint8_t num_planes; 1974 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1975 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 1976 }; //v1 1977 1978 struct dmub_fams2_stream_static_state_v1 { 1979 struct dmub_fams2_cmd_stream_static_base_state base; 1980 union dmub_fams2_cmd_stream_static_sub_state sub_state; 1981 }; //v1 1982 1983 /** 1984 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 1985 * p-state request to allow latency 1986 */ 1987 enum dmub_fams2_allow_delay_check_mode { 1988 /* No check for request to allow delay */ 1989 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 1990 /* Check for request to allow delay */ 1991 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 1992 /* Check for prepare to allow delay */ 1993 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 1994 }; 1995 1996 union dmub_fams2_global_feature_config { 1997 struct { 1998 uint32_t enable: 1; 1999 uint32_t enable_ppt_check: 1; 2000 uint32_t enable_stall_recovery: 1; 2001 uint32_t enable_debug: 1; 2002 uint32_t enable_offload_flip: 1; 2003 uint32_t enable_visual_confirm: 1; 2004 uint32_t allow_delay_check_mode: 2; 2005 uint32_t reserved: 24; 2006 } bits; 2007 uint32_t all; 2008 }; 2009 2010 struct dmub_cmd_fams2_global_config { 2011 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2012 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2013 uint32_t num_streams; 2014 union dmub_fams2_global_feature_config features; 2015 uint32_t recovery_timeout_us; 2016 uint32_t hwfq_flip_programming_delay_us; 2017 }; 2018 2019 union dmub_cmd_fams2_config { 2020 struct dmub_cmd_fams2_global_config global; 2021 struct dmub_fams2_stream_static_state stream; //v0 2022 union { 2023 struct dmub_fams2_cmd_stream_static_base_state base; 2024 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2025 } stream_v1; //v1 2026 }; 2027 2028 /** 2029 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2030 */ 2031 struct dmub_rb_cmd_fams2 { 2032 struct dmub_cmd_header header; 2033 union dmub_cmd_fams2_config config; 2034 }; 2035 2036 /** 2037 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2038 */ 2039 enum dmub_cmd_idle_opt_type { 2040 /** 2041 * DCN hardware restore. 2042 */ 2043 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2044 2045 /** 2046 * DCN hardware save. 2047 */ 2048 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2049 2050 /** 2051 * DCN hardware notify idle. 2052 */ 2053 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2054 2055 /** 2056 * DCN hardware notify power state. 2057 */ 2058 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2059 }; 2060 2061 /** 2062 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2063 */ 2064 struct dmub_rb_cmd_idle_opt_dcn_restore { 2065 struct dmub_cmd_header header; /**< header */ 2066 }; 2067 2068 /** 2069 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2070 */ 2071 struct dmub_dcn_notify_idle_cntl_data { 2072 uint8_t driver_idle; 2073 uint8_t skip_otg_disable; 2074 uint8_t reserved[58]; 2075 }; 2076 2077 /** 2078 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2079 */ 2080 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2081 struct dmub_cmd_header header; /**< header */ 2082 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2083 }; 2084 2085 /** 2086 * enum dmub_idle_opt_dc_power_state - DC power states. 2087 */ 2088 enum dmub_idle_opt_dc_power_state { 2089 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2090 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2091 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2092 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2093 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2094 }; 2095 2096 /** 2097 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2098 */ 2099 struct dmub_idle_opt_set_dc_power_state_data { 2100 uint8_t power_state; /**< power state */ 2101 uint8_t pad[3]; /**< padding */ 2102 }; 2103 2104 /** 2105 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2106 */ 2107 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2108 struct dmub_cmd_header header; /**< header */ 2109 struct dmub_idle_opt_set_dc_power_state_data data; 2110 }; 2111 2112 /** 2113 * struct dmub_clocks - Clock update notification. 2114 */ 2115 struct dmub_clocks { 2116 uint32_t dispclk_khz; /**< dispclk kHz */ 2117 uint32_t dppclk_khz; /**< dppclk kHz */ 2118 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2119 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2120 }; 2121 2122 /** 2123 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2124 */ 2125 enum dmub_cmd_clk_mgr_type { 2126 /** 2127 * Notify DMCUB of clock update. 2128 */ 2129 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2130 }; 2131 2132 /** 2133 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2134 */ 2135 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2136 struct dmub_cmd_header header; /**< header */ 2137 struct dmub_clocks clocks; /**< clock data */ 2138 }; 2139 2140 /** 2141 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2142 */ 2143 struct dmub_cmd_digx_encoder_control_data { 2144 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2145 }; 2146 2147 /** 2148 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2149 */ 2150 struct dmub_rb_cmd_digx_encoder_control { 2151 struct dmub_cmd_header header; /**< header */ 2152 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2153 }; 2154 2155 /** 2156 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2157 */ 2158 struct dmub_cmd_set_pixel_clock_data { 2159 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2160 }; 2161 2162 /** 2163 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2164 */ 2165 struct dmub_rb_cmd_set_pixel_clock { 2166 struct dmub_cmd_header header; /**< header */ 2167 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2168 }; 2169 2170 /** 2171 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2172 */ 2173 struct dmub_cmd_enable_disp_power_gating_data { 2174 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2175 }; 2176 2177 /** 2178 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2179 */ 2180 struct dmub_rb_cmd_enable_disp_power_gating { 2181 struct dmub_cmd_header header; /**< header */ 2182 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2183 }; 2184 2185 /** 2186 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2187 */ 2188 struct dmub_dig_transmitter_control_data_v1_7 { 2189 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2190 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2191 union { 2192 uint8_t digmode; /**< enum atom_encode_mode_def */ 2193 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2194 } mode_laneset; 2195 uint8_t lanenum; /**< Number of lanes */ 2196 union { 2197 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2198 } symclk_units; 2199 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2200 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2201 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2202 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2203 uint8_t reserved1; /**< For future use */ 2204 uint8_t reserved2[3]; /**< For future use */ 2205 uint32_t reserved3[11]; /**< For future use */ 2206 }; 2207 2208 /** 2209 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2210 */ 2211 union dmub_cmd_dig1_transmitter_control_data { 2212 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2213 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2214 }; 2215 2216 /** 2217 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2218 */ 2219 struct dmub_rb_cmd_dig1_transmitter_control { 2220 struct dmub_cmd_header header; /**< header */ 2221 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2222 }; 2223 2224 /** 2225 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2226 */ 2227 struct dmub_rb_cmd_domain_control_data { 2228 uint8_t inst : 6; /**< DOMAIN instance to control */ 2229 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2230 uint8_t reserved[3]; /**< Reserved for future use */ 2231 }; 2232 2233 /** 2234 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2235 */ 2236 struct dmub_rb_cmd_domain_control { 2237 struct dmub_cmd_header header; /**< header */ 2238 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2239 }; 2240 2241 /** 2242 * DPIA tunnel command parameters. 2243 */ 2244 struct dmub_cmd_dig_dpia_control_data { 2245 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2246 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2247 union { 2248 uint8_t digmode; /** enum atom_encode_mode_def */ 2249 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2250 } mode_laneset; 2251 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2252 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2253 uint8_t hpdsel; /** =0: HPD is not assigned */ 2254 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2255 uint8_t dpia_id; /** Index of DPIA */ 2256 uint8_t fec_rdy : 1; 2257 uint8_t reserved : 7; 2258 uint32_t reserved1; 2259 }; 2260 2261 /** 2262 * DMUB command for DPIA tunnel control. 2263 */ 2264 struct dmub_rb_cmd_dig1_dpia_control { 2265 struct dmub_cmd_header header; 2266 struct dmub_cmd_dig_dpia_control_data dpia_control; 2267 }; 2268 2269 /** 2270 * SET_CONFIG Command Payload (deprecated) 2271 */ 2272 struct set_config_cmd_payload { 2273 uint8_t msg_type; /* set config message type */ 2274 uint8_t msg_data; /* set config message data */ 2275 }; 2276 2277 /** 2278 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2279 */ 2280 struct dmub_cmd_set_config_control_data { 2281 struct set_config_cmd_payload cmd_pkt; 2282 uint8_t instance; /* DPIA instance */ 2283 uint8_t immed_status; /* Immediate status returned in case of error */ 2284 }; 2285 2286 /** 2287 * SET_CONFIG Request Command Payload 2288 */ 2289 struct set_config_request_cmd_payload { 2290 uint8_t instance; /* DPIA instance */ 2291 uint8_t immed_status; /* Immediate status returned in case of error */ 2292 uint8_t msg_type; /* set config message type */ 2293 uint8_t reserved; 2294 uint32_t msg_data; /* set config message data */ 2295 }; 2296 2297 /** 2298 * DMUB command structure for SET_CONFIG command. 2299 */ 2300 struct dmub_rb_cmd_set_config_access { 2301 struct dmub_cmd_header header; /* header */ 2302 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2303 }; 2304 2305 /** 2306 * DMUB command structure for SET_CONFIG request command. 2307 */ 2308 struct dmub_rb_cmd_set_config_request { 2309 struct dmub_cmd_header header; /* header */ 2310 struct set_config_request_cmd_payload payload; /* set config request payload */ 2311 }; 2312 2313 /** 2314 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2315 */ 2316 struct dmub_cmd_mst_alloc_slots_control_data { 2317 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2318 uint8_t instance; /* DPIA instance */ 2319 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2320 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2321 }; 2322 2323 /** 2324 * DMUB command structure for SET_ command. 2325 */ 2326 struct dmub_rb_cmd_set_mst_alloc_slots { 2327 struct dmub_cmd_header header; /* header */ 2328 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2329 }; 2330 2331 /** 2332 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2333 */ 2334 struct dmub_cmd_tps_notification_data { 2335 uint8_t instance; /* DPIA instance */ 2336 uint8_t tps; /* requested training pattern */ 2337 uint8_t reserved1; 2338 uint8_t reserved2; 2339 }; 2340 2341 /** 2342 * DMUB command structure for SET_TPS_NOTIFICATION command. 2343 */ 2344 struct dmub_rb_cmd_set_tps_notification { 2345 struct dmub_cmd_header header; /* header */ 2346 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2347 }; 2348 2349 /** 2350 * DMUB command structure for DPIA HPD int enable control. 2351 */ 2352 struct dmub_rb_cmd_dpia_hpd_int_enable { 2353 struct dmub_cmd_header header; /* header */ 2354 uint32_t enable; /* dpia hpd interrupt enable */ 2355 }; 2356 2357 /** 2358 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2359 */ 2360 struct dmub_rb_cmd_dpphy_init { 2361 struct dmub_cmd_header header; /**< header */ 2362 uint8_t reserved[60]; /**< reserved bits */ 2363 }; 2364 2365 /** 2366 * enum dp_aux_request_action - DP AUX request command listing. 2367 * 2368 * 4 AUX request command bits are shifted to high nibble. 2369 */ 2370 enum dp_aux_request_action { 2371 /** I2C-over-AUX write request */ 2372 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2373 /** I2C-over-AUX read request */ 2374 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2375 /** I2C-over-AUX write status request */ 2376 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2377 /** I2C-over-AUX write request with MOT=1 */ 2378 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2379 /** I2C-over-AUX read request with MOT=1 */ 2380 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2381 /** I2C-over-AUX write status request with MOT=1 */ 2382 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2383 /** Native AUX write request */ 2384 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2385 /** Native AUX read request */ 2386 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2387 }; 2388 2389 /** 2390 * enum aux_return_code_type - DP AUX process return code listing. 2391 */ 2392 enum aux_return_code_type { 2393 /** AUX process succeeded */ 2394 AUX_RET_SUCCESS = 0, 2395 /** AUX process failed with unknown reason */ 2396 AUX_RET_ERROR_UNKNOWN, 2397 /** AUX process completed with invalid reply */ 2398 AUX_RET_ERROR_INVALID_REPLY, 2399 /** AUX process timed out */ 2400 AUX_RET_ERROR_TIMEOUT, 2401 /** HPD was low during AUX process */ 2402 AUX_RET_ERROR_HPD_DISCON, 2403 /** Failed to acquire AUX engine */ 2404 AUX_RET_ERROR_ENGINE_ACQUIRE, 2405 /** AUX request not supported */ 2406 AUX_RET_ERROR_INVALID_OPERATION, 2407 /** AUX process not available */ 2408 AUX_RET_ERROR_PROTOCOL_ERROR, 2409 }; 2410 2411 /** 2412 * enum aux_channel_type - DP AUX channel type listing. 2413 */ 2414 enum aux_channel_type { 2415 /** AUX thru Legacy DP AUX */ 2416 AUX_CHANNEL_LEGACY_DDC, 2417 /** AUX thru DPIA DP tunneling */ 2418 AUX_CHANNEL_DPIA 2419 }; 2420 2421 /** 2422 * struct aux_transaction_parameters - DP AUX request transaction data 2423 */ 2424 struct aux_transaction_parameters { 2425 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2426 uint8_t action; /**< enum dp_aux_request_action */ 2427 uint8_t length; /**< DP AUX request data length */ 2428 uint8_t reserved; /**< For future use */ 2429 uint32_t address; /**< DP AUX address */ 2430 uint8_t data[16]; /**< DP AUX write data */ 2431 }; 2432 2433 /** 2434 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2435 */ 2436 struct dmub_cmd_dp_aux_control_data { 2437 uint8_t instance; /**< AUX instance or DPIA instance */ 2438 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2439 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2440 uint8_t reserved0; /**< For future use */ 2441 uint16_t timeout; /**< timeout time in us */ 2442 uint16_t reserved1; /**< For future use */ 2443 enum aux_channel_type type; /**< enum aux_channel_type */ 2444 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2445 }; 2446 2447 /** 2448 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2449 */ 2450 struct dmub_rb_cmd_dp_aux_access { 2451 /** 2452 * Command header. 2453 */ 2454 struct dmub_cmd_header header; 2455 /** 2456 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2457 */ 2458 struct dmub_cmd_dp_aux_control_data aux_control; 2459 }; 2460 2461 /** 2462 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2463 */ 2464 struct dmub_rb_cmd_outbox1_enable { 2465 /** 2466 * Command header. 2467 */ 2468 struct dmub_cmd_header header; 2469 /** 2470 * enable: 0x0 -> disable outbox1 notification (default value) 2471 * 0x1 -> enable outbox1 notification 2472 */ 2473 uint32_t enable; 2474 }; 2475 2476 /* DP AUX Reply command - OutBox Cmd */ 2477 /** 2478 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2479 */ 2480 struct aux_reply_data { 2481 /** 2482 * Aux cmd 2483 */ 2484 uint8_t command; 2485 /** 2486 * Aux reply data length (max: 16 bytes) 2487 */ 2488 uint8_t length; 2489 /** 2490 * Alignment only 2491 */ 2492 uint8_t pad[2]; 2493 /** 2494 * Aux reply data 2495 */ 2496 uint8_t data[16]; 2497 }; 2498 2499 /** 2500 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2501 */ 2502 struct aux_reply_control_data { 2503 /** 2504 * Reserved for future use 2505 */ 2506 uint32_t handle; 2507 /** 2508 * Aux Instance 2509 */ 2510 uint8_t instance; 2511 /** 2512 * Aux transaction result: definition in enum aux_return_code_type 2513 */ 2514 uint8_t result; 2515 /** 2516 * Alignment only 2517 */ 2518 uint16_t pad; 2519 }; 2520 2521 /** 2522 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2523 */ 2524 struct dmub_rb_cmd_dp_aux_reply { 2525 /** 2526 * Command header. 2527 */ 2528 struct dmub_cmd_header header; 2529 /** 2530 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2531 */ 2532 struct aux_reply_control_data control; 2533 /** 2534 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2535 */ 2536 struct aux_reply_data reply_data; 2537 }; 2538 2539 /* DP HPD Notify command - OutBox Cmd */ 2540 /** 2541 * DP HPD Type 2542 */ 2543 enum dp_hpd_type { 2544 /** 2545 * Normal DP HPD 2546 */ 2547 DP_HPD = 0, 2548 /** 2549 * DP HPD short pulse 2550 */ 2551 DP_IRQ 2552 }; 2553 2554 /** 2555 * DP HPD Status 2556 */ 2557 enum dp_hpd_status { 2558 /** 2559 * DP_HPD status low 2560 */ 2561 DP_HPD_UNPLUG = 0, 2562 /** 2563 * DP_HPD status high 2564 */ 2565 DP_HPD_PLUG 2566 }; 2567 2568 /** 2569 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2570 */ 2571 struct dp_hpd_data { 2572 /** 2573 * DP HPD instance 2574 */ 2575 uint8_t instance; 2576 /** 2577 * HPD type 2578 */ 2579 uint8_t hpd_type; 2580 /** 2581 * HPD status: only for type: DP_HPD to indicate status 2582 */ 2583 uint8_t hpd_status; 2584 /** 2585 * Alignment only 2586 */ 2587 uint8_t pad; 2588 }; 2589 2590 /** 2591 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2592 */ 2593 struct dmub_rb_cmd_dp_hpd_notify { 2594 /** 2595 * Command header. 2596 */ 2597 struct dmub_cmd_header header; 2598 /** 2599 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2600 */ 2601 struct dp_hpd_data hpd_data; 2602 }; 2603 2604 /** 2605 * Definition of a SET_CONFIG reply from DPOA. 2606 */ 2607 enum set_config_status { 2608 SET_CONFIG_PENDING = 0, 2609 SET_CONFIG_ACK_RECEIVED, 2610 SET_CONFIG_RX_TIMEOUT, 2611 SET_CONFIG_UNKNOWN_ERROR, 2612 }; 2613 2614 /** 2615 * Definition of a set_config reply 2616 */ 2617 struct set_config_reply_control_data { 2618 uint8_t instance; /* DPIA Instance */ 2619 uint8_t status; /* Set Config reply */ 2620 uint16_t pad; /* Alignment */ 2621 }; 2622 2623 /** 2624 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2625 */ 2626 struct dmub_rb_cmd_dp_set_config_reply { 2627 struct dmub_cmd_header header; 2628 struct set_config_reply_control_data set_config_reply_control; 2629 }; 2630 2631 /** 2632 * Definition of a DPIA notification header 2633 */ 2634 struct dpia_notification_header { 2635 uint8_t instance; /**< DPIA Instance */ 2636 uint8_t reserved[3]; 2637 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2638 }; 2639 2640 /** 2641 * Definition of the common data struct of DPIA notification 2642 */ 2643 struct dpia_notification_common { 2644 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2645 - sizeof(struct dpia_notification_header)]; 2646 }; 2647 2648 /** 2649 * Definition of a DPIA notification data 2650 */ 2651 struct dpia_bw_allocation_notify_data { 2652 union { 2653 struct { 2654 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2655 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2656 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2657 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2658 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2659 uint16_t reserved: 11; /**< Reserved */ 2660 } bits; 2661 2662 uint16_t flags; 2663 }; 2664 2665 uint8_t cm_id; /**< CM ID */ 2666 uint8_t group_id; /**< Group ID */ 2667 uint8_t granularity; /**< BW Allocation Granularity */ 2668 uint8_t estimated_bw; /**< Estimated_BW */ 2669 uint8_t allocated_bw; /**< Allocated_BW */ 2670 uint8_t reserved; 2671 }; 2672 2673 /** 2674 * union dpia_notify_data_type - DPIA Notification in Outbox command 2675 */ 2676 union dpia_notification_data { 2677 /** 2678 * DPIA Notification for common data struct 2679 */ 2680 struct dpia_notification_common common_data; 2681 2682 /** 2683 * DPIA Notification for DP BW Allocation support 2684 */ 2685 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2686 }; 2687 2688 /** 2689 * Definition of a DPIA notification payload 2690 */ 2691 struct dpia_notification_payload { 2692 struct dpia_notification_header header; 2693 union dpia_notification_data data; /**< DPIA notification payload data */ 2694 }; 2695 2696 /** 2697 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2698 */ 2699 struct dmub_rb_cmd_dpia_notification { 2700 struct dmub_cmd_header header; /**< DPIA notification header */ 2701 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2702 }; 2703 2704 /** 2705 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2706 */ 2707 struct dmub_cmd_hpd_state_query_data { 2708 uint8_t instance; /**< HPD instance or DPIA instance */ 2709 uint8_t result; /**< For returning HPD state */ 2710 uint16_t pad; /** < Alignment */ 2711 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2712 enum aux_return_code_type status; /**< for returning the status of command */ 2713 }; 2714 2715 /** 2716 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2717 */ 2718 struct dmub_rb_cmd_query_hpd_state { 2719 /** 2720 * Command header. 2721 */ 2722 struct dmub_cmd_header header; 2723 /** 2724 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2725 */ 2726 struct dmub_cmd_hpd_state_query_data data; 2727 }; 2728 2729 /** 2730 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2731 */ 2732 struct dmub_rb_cmd_hpd_sense_notify_data { 2733 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2734 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2735 }; 2736 2737 /** 2738 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2739 */ 2740 struct dmub_rb_cmd_hpd_sense_notify { 2741 struct dmub_cmd_header header; /**< header */ 2742 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2743 }; 2744 2745 /* 2746 * Command IDs should be treated as stable ABI. 2747 * Do not reuse or modify IDs. 2748 */ 2749 2750 /** 2751 * PSR command sub-types. 2752 */ 2753 enum dmub_cmd_psr_type { 2754 /** 2755 * Set PSR version support. 2756 */ 2757 DMUB_CMD__PSR_SET_VERSION = 0, 2758 /** 2759 * Copy driver-calculated parameters to PSR state. 2760 */ 2761 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2762 /** 2763 * Enable PSR. 2764 */ 2765 DMUB_CMD__PSR_ENABLE = 2, 2766 2767 /** 2768 * Disable PSR. 2769 */ 2770 DMUB_CMD__PSR_DISABLE = 3, 2771 2772 /** 2773 * Set PSR level. 2774 * PSR level is a 16-bit value dicated by driver that 2775 * will enable/disable different functionality. 2776 */ 2777 DMUB_CMD__PSR_SET_LEVEL = 4, 2778 2779 /** 2780 * Forces PSR enabled until an explicit PSR disable call. 2781 */ 2782 DMUB_CMD__PSR_FORCE_STATIC = 5, 2783 /** 2784 * Set vtotal in psr active for FreeSync PSR. 2785 */ 2786 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2787 /** 2788 * Set PSR power option 2789 */ 2790 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2791 }; 2792 2793 /** 2794 * Different PSR residency modes. 2795 * Different modes change the definition of PSR residency. 2796 */ 2797 enum psr_residency_mode { 2798 PSR_RESIDENCY_MODE_PHY = 0, 2799 PSR_RESIDENCY_MODE_ALPM, 2800 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2801 /* Do not add below. */ 2802 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2803 }; 2804 2805 enum dmub_cmd_fams_type { 2806 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2807 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2808 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2809 /** 2810 * For SubVP set manual trigger in FW because it 2811 * triggers DRR_UPDATE_PENDING which SubVP relies 2812 * on (for any SubVP cases that use a DRR display) 2813 */ 2814 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2815 DMUB_CMD__FAMS2_CONFIG = 4, 2816 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2817 DMUB_CMD__FAMS2_FLIP = 6, 2818 }; 2819 2820 /** 2821 * PSR versions. 2822 */ 2823 enum psr_version { 2824 /** 2825 * PSR version 1. 2826 */ 2827 PSR_VERSION_1 = 0, 2828 /** 2829 * Freesync PSR SU. 2830 */ 2831 PSR_VERSION_SU_1 = 1, 2832 /** 2833 * PSR not supported. 2834 */ 2835 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2836 }; 2837 2838 /** 2839 * PHY Link rate for DP. 2840 */ 2841 enum phy_link_rate { 2842 /** 2843 * not supported. 2844 */ 2845 PHY_RATE_UNKNOWN = 0, 2846 /** 2847 * Rate_1 (RBR) - 1.62 Gbps/Lane 2848 */ 2849 PHY_RATE_162 = 1, 2850 /** 2851 * Rate_2 - 2.16 Gbps/Lane 2852 */ 2853 PHY_RATE_216 = 2, 2854 /** 2855 * Rate_3 - 2.43 Gbps/Lane 2856 */ 2857 PHY_RATE_243 = 3, 2858 /** 2859 * Rate_4 (HBR) - 2.70 Gbps/Lane 2860 */ 2861 PHY_RATE_270 = 4, 2862 /** 2863 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2864 */ 2865 PHY_RATE_324 = 5, 2866 /** 2867 * Rate_6 - 4.32 Gbps/Lane 2868 */ 2869 PHY_RATE_432 = 6, 2870 /** 2871 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2872 */ 2873 PHY_RATE_540 = 7, 2874 /** 2875 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2876 */ 2877 PHY_RATE_810 = 8, 2878 /** 2879 * UHBR10 - 10.0 Gbps/Lane 2880 */ 2881 PHY_RATE_1000 = 9, 2882 /** 2883 * UHBR13.5 - 13.5 Gbps/Lane 2884 */ 2885 PHY_RATE_1350 = 10, 2886 /** 2887 * UHBR10 - 20.0 Gbps/Lane 2888 */ 2889 PHY_RATE_2000 = 11, 2890 2891 PHY_RATE_675 = 12, 2892 /** 2893 * Rate 12 - 6.75 Gbps/Lane 2894 */ 2895 }; 2896 2897 /** 2898 * enum dmub_phy_fsm_state - PHY FSM states. 2899 * PHY FSM state to transit to during PSR enable/disable. 2900 */ 2901 enum dmub_phy_fsm_state { 2902 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2903 DMUB_PHY_FSM_RESET, 2904 DMUB_PHY_FSM_RESET_RELEASED, 2905 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2906 DMUB_PHY_FSM_INITIALIZED, 2907 DMUB_PHY_FSM_CALIBRATED, 2908 DMUB_PHY_FSM_CALIBRATED_LP, 2909 DMUB_PHY_FSM_CALIBRATED_PG, 2910 DMUB_PHY_FSM_POWER_DOWN, 2911 DMUB_PHY_FSM_PLL_EN, 2912 DMUB_PHY_FSM_TX_EN, 2913 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2914 DMUB_PHY_FSM_FAST_LP, 2915 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2916 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2917 DMUB_PHY_FSM_P2_PLL_OFF, 2918 DMUB_PHY_FSM_P2_PLL_ON, 2919 }; 2920 2921 /** 2922 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2923 */ 2924 struct dmub_cmd_psr_copy_settings_data { 2925 /** 2926 * Flags that can be set by driver to change some PSR behaviour. 2927 */ 2928 union dmub_psr_debug_flags debug; 2929 /** 2930 * 16-bit value dicated by driver that will enable/disable different functionality. 2931 */ 2932 uint16_t psr_level; 2933 /** 2934 * DPP HW instance. 2935 */ 2936 uint8_t dpp_inst; 2937 /** 2938 * MPCC HW instance. 2939 * Not used in dmub fw, 2940 * dmub fw will get active opp by reading odm registers. 2941 */ 2942 uint8_t mpcc_inst; 2943 /** 2944 * OPP HW instance. 2945 * Not used in dmub fw, 2946 * dmub fw will get active opp by reading odm registers. 2947 */ 2948 uint8_t opp_inst; 2949 /** 2950 * OTG HW instance. 2951 */ 2952 uint8_t otg_inst; 2953 /** 2954 * DIG FE HW instance. 2955 */ 2956 uint8_t digfe_inst; 2957 /** 2958 * DIG BE HW instance. 2959 */ 2960 uint8_t digbe_inst; 2961 /** 2962 * DP PHY HW instance. 2963 */ 2964 uint8_t dpphy_inst; 2965 /** 2966 * AUX HW instance. 2967 */ 2968 uint8_t aux_inst; 2969 /** 2970 * Determines if SMU optimzations are enabled/disabled. 2971 */ 2972 uint8_t smu_optimizations_en; 2973 /** 2974 * Unused. 2975 * TODO: Remove. 2976 */ 2977 uint8_t frame_delay; 2978 /** 2979 * If RFB setup time is greater than the total VBLANK time, 2980 * it is not possible for the sink to capture the video frame 2981 * in the same frame the SDP is sent. In this case, 2982 * the frame capture indication bit should be set and an extra 2983 * static frame should be transmitted to the sink. 2984 */ 2985 uint8_t frame_cap_ind; 2986 /** 2987 * Granularity of Y offset supported by sink. 2988 */ 2989 uint8_t su_y_granularity; 2990 /** 2991 * Indicates whether sink should start capturing 2992 * immediately following active scan line, 2993 * or starting with the 2nd active scan line. 2994 */ 2995 uint8_t line_capture_indication; 2996 /** 2997 * Multi-display optimizations are implemented on certain ASICs. 2998 */ 2999 uint8_t multi_disp_optimizations_en; 3000 /** 3001 * The last possible line SDP may be transmitted without violating 3002 * the RFB setup time or entering the active video frame. 3003 */ 3004 uint16_t init_sdp_deadline; 3005 /** 3006 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3007 */ 3008 uint8_t rate_control_caps ; 3009 /* 3010 * Force PSRSU always doing full frame update 3011 */ 3012 uint8_t force_ffu_mode; 3013 /** 3014 * Length of each horizontal line in us. 3015 */ 3016 uint32_t line_time_in_us; 3017 /** 3018 * FEC enable status in driver 3019 */ 3020 uint8_t fec_enable_status; 3021 /** 3022 * FEC re-enable delay when PSR exit. 3023 * unit is 100us, range form 0~255(0xFF). 3024 */ 3025 uint8_t fec_enable_delay_in100us; 3026 /** 3027 * PSR control version. 3028 */ 3029 uint8_t cmd_version; 3030 /** 3031 * Panel Instance. 3032 * Panel instance to identify which psr_state to use 3033 * Currently the support is only for 0 or 1 3034 */ 3035 uint8_t panel_inst; 3036 /* 3037 * DSC enable status in driver 3038 */ 3039 uint8_t dsc_enable_status; 3040 /* 3041 * Use FSM state for PSR power up/down 3042 */ 3043 uint8_t use_phy_fsm; 3044 /** 3045 * frame delay for frame re-lock 3046 */ 3047 uint8_t relock_delay_frame_cnt; 3048 /** 3049 * esd recovery indicate. 3050 */ 3051 uint8_t esd_recovery; 3052 /** 3053 * DSC Slice height. 3054 */ 3055 uint16_t dsc_slice_height; 3056 /** 3057 * Some panels request main link off before xth vertical line 3058 */ 3059 uint16_t poweroff_before_vertical_line; 3060 }; 3061 3062 /** 3063 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3064 */ 3065 struct dmub_rb_cmd_psr_copy_settings { 3066 /** 3067 * Command header. 3068 */ 3069 struct dmub_cmd_header header; 3070 /** 3071 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3072 */ 3073 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3074 }; 3075 3076 /** 3077 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3078 */ 3079 struct dmub_cmd_psr_set_level_data { 3080 /** 3081 * 16-bit value dicated by driver that will enable/disable different functionality. 3082 */ 3083 uint16_t psr_level; 3084 /** 3085 * PSR control version. 3086 */ 3087 uint8_t cmd_version; 3088 /** 3089 * Panel Instance. 3090 * Panel instance to identify which psr_state to use 3091 * Currently the support is only for 0 or 1 3092 */ 3093 uint8_t panel_inst; 3094 }; 3095 3096 /** 3097 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3098 */ 3099 struct dmub_rb_cmd_psr_set_level { 3100 /** 3101 * Command header. 3102 */ 3103 struct dmub_cmd_header header; 3104 /** 3105 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3106 */ 3107 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3108 }; 3109 3110 struct dmub_rb_cmd_psr_enable_data { 3111 /** 3112 * PSR control version. 3113 */ 3114 uint8_t cmd_version; 3115 /** 3116 * Panel Instance. 3117 * Panel instance to identify which psr_state to use 3118 * Currently the support is only for 0 or 1 3119 */ 3120 uint8_t panel_inst; 3121 /** 3122 * Phy state to enter. 3123 * Values to use are defined in dmub_phy_fsm_state 3124 */ 3125 uint8_t phy_fsm_state; 3126 /** 3127 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3128 * Set this using enum phy_link_rate. 3129 * This does not support HDMI/DP2 for now. 3130 */ 3131 uint8_t phy_rate; 3132 }; 3133 3134 /** 3135 * Definition of a DMUB_CMD__PSR_ENABLE command. 3136 * PSR enable/disable is controlled using the sub_type. 3137 */ 3138 struct dmub_rb_cmd_psr_enable { 3139 /** 3140 * Command header. 3141 */ 3142 struct dmub_cmd_header header; 3143 3144 struct dmub_rb_cmd_psr_enable_data data; 3145 }; 3146 3147 /** 3148 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3149 */ 3150 struct dmub_cmd_psr_set_version_data { 3151 /** 3152 * PSR version that FW should implement. 3153 */ 3154 enum psr_version version; 3155 /** 3156 * PSR control version. 3157 */ 3158 uint8_t cmd_version; 3159 /** 3160 * Panel Instance. 3161 * Panel instance to identify which psr_state to use 3162 * Currently the support is only for 0 or 1 3163 */ 3164 uint8_t panel_inst; 3165 /** 3166 * Explicit padding to 4 byte boundary. 3167 */ 3168 uint8_t pad[2]; 3169 }; 3170 3171 /** 3172 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3173 */ 3174 struct dmub_rb_cmd_psr_set_version { 3175 /** 3176 * Command header. 3177 */ 3178 struct dmub_cmd_header header; 3179 /** 3180 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3181 */ 3182 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3183 }; 3184 3185 struct dmub_cmd_psr_force_static_data { 3186 /** 3187 * PSR control version. 3188 */ 3189 uint8_t cmd_version; 3190 /** 3191 * Panel Instance. 3192 * Panel instance to identify which psr_state to use 3193 * Currently the support is only for 0 or 1 3194 */ 3195 uint8_t panel_inst; 3196 /** 3197 * Explicit padding to 4 byte boundary. 3198 */ 3199 uint8_t pad[2]; 3200 }; 3201 3202 /** 3203 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3204 */ 3205 struct dmub_rb_cmd_psr_force_static { 3206 /** 3207 * Command header. 3208 */ 3209 struct dmub_cmd_header header; 3210 /** 3211 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3212 */ 3213 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3214 }; 3215 3216 /** 3217 * PSR SU debug flags. 3218 */ 3219 union dmub_psr_su_debug_flags { 3220 /** 3221 * PSR SU debug flags. 3222 */ 3223 struct { 3224 /** 3225 * Update dirty rect in SW only. 3226 */ 3227 uint8_t update_dirty_rect_only : 1; 3228 /** 3229 * Reset the cursor/plane state before processing the call. 3230 */ 3231 uint8_t reset_state : 1; 3232 } bitfields; 3233 3234 /** 3235 * Union for debug flags. 3236 */ 3237 uint32_t u32All; 3238 }; 3239 3240 /** 3241 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3242 * This triggers a selective update for PSR SU. 3243 */ 3244 struct dmub_cmd_update_dirty_rect_data { 3245 /** 3246 * Dirty rects from OS. 3247 */ 3248 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3249 /** 3250 * PSR SU debug flags. 3251 */ 3252 union dmub_psr_su_debug_flags debug_flags; 3253 /** 3254 * OTG HW instance. 3255 */ 3256 uint8_t pipe_idx; 3257 /** 3258 * Number of dirty rects. 3259 */ 3260 uint8_t dirty_rect_count; 3261 /** 3262 * PSR control version. 3263 */ 3264 uint8_t cmd_version; 3265 /** 3266 * Panel Instance. 3267 * Panel instance to identify which psr_state to use 3268 * Currently the support is only for 0 or 1 3269 */ 3270 uint8_t panel_inst; 3271 }; 3272 3273 /** 3274 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3275 */ 3276 struct dmub_rb_cmd_update_dirty_rect { 3277 /** 3278 * Command header. 3279 */ 3280 struct dmub_cmd_header header; 3281 /** 3282 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3283 */ 3284 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3285 }; 3286 3287 /** 3288 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3289 */ 3290 union dmub_reg_cursor_control_cfg { 3291 struct { 3292 uint32_t cur_enable: 1; 3293 uint32_t reser0: 3; 3294 uint32_t cur_2x_magnify: 1; 3295 uint32_t reser1: 3; 3296 uint32_t mode: 3; 3297 uint32_t reser2: 5; 3298 uint32_t pitch: 2; 3299 uint32_t reser3: 6; 3300 uint32_t line_per_chunk: 5; 3301 uint32_t reser4: 3; 3302 } bits; 3303 uint32_t raw; 3304 }; 3305 struct dmub_cursor_position_cache_hubp { 3306 union dmub_reg_cursor_control_cfg cur_ctl; 3307 union dmub_reg_position_cfg { 3308 struct { 3309 uint32_t cur_x_pos: 16; 3310 uint32_t cur_y_pos: 16; 3311 } bits; 3312 uint32_t raw; 3313 } position; 3314 union dmub_reg_hot_spot_cfg { 3315 struct { 3316 uint32_t hot_x: 16; 3317 uint32_t hot_y: 16; 3318 } bits; 3319 uint32_t raw; 3320 } hot_spot; 3321 union dmub_reg_dst_offset_cfg { 3322 struct { 3323 uint32_t dst_x_offset: 13; 3324 uint32_t reserved: 19; 3325 } bits; 3326 uint32_t raw; 3327 } dst_offset; 3328 }; 3329 3330 union dmub_reg_cur0_control_cfg { 3331 struct { 3332 uint32_t cur0_enable: 1; 3333 uint32_t expansion_mode: 1; 3334 uint32_t reser0: 1; 3335 uint32_t cur0_rom_en: 1; 3336 uint32_t mode: 3; 3337 uint32_t reserved: 25; 3338 } bits; 3339 uint32_t raw; 3340 }; 3341 struct dmub_cursor_position_cache_dpp { 3342 union dmub_reg_cur0_control_cfg cur0_ctl; 3343 }; 3344 struct dmub_cursor_position_cfg { 3345 struct dmub_cursor_position_cache_hubp pHubp; 3346 struct dmub_cursor_position_cache_dpp pDpp; 3347 uint8_t pipe_idx; 3348 /* 3349 * Padding is required. To be 4 Bytes Aligned. 3350 */ 3351 uint8_t padding[3]; 3352 }; 3353 3354 struct dmub_cursor_attribute_cache_hubp { 3355 uint32_t SURFACE_ADDR_HIGH; 3356 uint32_t SURFACE_ADDR; 3357 union dmub_reg_cursor_control_cfg cur_ctl; 3358 union dmub_reg_cursor_size_cfg { 3359 struct { 3360 uint32_t width: 16; 3361 uint32_t height: 16; 3362 } bits; 3363 uint32_t raw; 3364 } size; 3365 union dmub_reg_cursor_settings_cfg { 3366 struct { 3367 uint32_t dst_y_offset: 8; 3368 uint32_t chunk_hdl_adjust: 2; 3369 uint32_t reserved: 22; 3370 } bits; 3371 uint32_t raw; 3372 } settings; 3373 }; 3374 struct dmub_cursor_attribute_cache_dpp { 3375 union dmub_reg_cur0_control_cfg cur0_ctl; 3376 }; 3377 struct dmub_cursor_attributes_cfg { 3378 struct dmub_cursor_attribute_cache_hubp aHubp; 3379 struct dmub_cursor_attribute_cache_dpp aDpp; 3380 }; 3381 3382 struct dmub_cmd_update_cursor_payload0 { 3383 /** 3384 * Cursor dirty rects. 3385 */ 3386 struct dmub_rect cursor_rect; 3387 /** 3388 * PSR SU debug flags. 3389 */ 3390 union dmub_psr_su_debug_flags debug_flags; 3391 /** 3392 * Cursor enable/disable. 3393 */ 3394 uint8_t enable; 3395 /** 3396 * OTG HW instance. 3397 */ 3398 uint8_t pipe_idx; 3399 /** 3400 * PSR control version. 3401 */ 3402 uint8_t cmd_version; 3403 /** 3404 * Panel Instance. 3405 * Panel instance to identify which psr_state to use 3406 * Currently the support is only for 0 or 1 3407 */ 3408 uint8_t panel_inst; 3409 /** 3410 * Cursor Position Register. 3411 * Registers contains Hubp & Dpp modules 3412 */ 3413 struct dmub_cursor_position_cfg position_cfg; 3414 }; 3415 3416 struct dmub_cmd_update_cursor_payload1 { 3417 struct dmub_cursor_attributes_cfg attribute_cfg; 3418 }; 3419 3420 union dmub_cmd_update_cursor_info_data { 3421 struct dmub_cmd_update_cursor_payload0 payload0; 3422 struct dmub_cmd_update_cursor_payload1 payload1; 3423 }; 3424 /** 3425 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3426 */ 3427 struct dmub_rb_cmd_update_cursor_info { 3428 /** 3429 * Command header. 3430 */ 3431 struct dmub_cmd_header header; 3432 /** 3433 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3434 */ 3435 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3436 }; 3437 3438 /** 3439 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3440 */ 3441 struct dmub_cmd_psr_set_vtotal_data { 3442 /** 3443 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3444 */ 3445 uint16_t psr_vtotal_idle; 3446 /** 3447 * PSR control version. 3448 */ 3449 uint8_t cmd_version; 3450 /** 3451 * Panel Instance. 3452 * Panel instance to identify which psr_state to use 3453 * Currently the support is only for 0 or 1 3454 */ 3455 uint8_t panel_inst; 3456 /* 3457 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3458 */ 3459 uint16_t psr_vtotal_su; 3460 /** 3461 * Explicit padding to 4 byte boundary. 3462 */ 3463 uint8_t pad2[2]; 3464 }; 3465 3466 /** 3467 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3468 */ 3469 struct dmub_rb_cmd_psr_set_vtotal { 3470 /** 3471 * Command header. 3472 */ 3473 struct dmub_cmd_header header; 3474 /** 3475 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3476 */ 3477 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3478 }; 3479 3480 /** 3481 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3482 */ 3483 struct dmub_cmd_psr_set_power_opt_data { 3484 /** 3485 * PSR control version. 3486 */ 3487 uint8_t cmd_version; 3488 /** 3489 * Panel Instance. 3490 * Panel instance to identify which psr_state to use 3491 * Currently the support is only for 0 or 1 3492 */ 3493 uint8_t panel_inst; 3494 /** 3495 * Explicit padding to 4 byte boundary. 3496 */ 3497 uint8_t pad[2]; 3498 /** 3499 * PSR power option 3500 */ 3501 uint32_t power_opt; 3502 }; 3503 3504 /** 3505 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3506 */ 3507 struct dmub_rb_cmd_psr_set_power_opt { 3508 /** 3509 * Command header. 3510 */ 3511 struct dmub_cmd_header header; 3512 /** 3513 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3514 */ 3515 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3516 }; 3517 3518 /** 3519 * Definition of Replay Residency GPINT command. 3520 * Bit[0] - Residency mode for Revision 0 3521 * Bit[1] - Enable/Disable state 3522 * Bit[2-3] - Revision number 3523 * Bit[4-7] - Residency mode for Revision 1 3524 * Bit[8] - Panel instance 3525 * Bit[9-15] - Reserved 3526 */ 3527 3528 enum pr_residency_mode { 3529 PR_RESIDENCY_MODE_PHY = 0x0, 3530 PR_RESIDENCY_MODE_ALPM, 3531 PR_RESIDENCY_MODE_IPS2, 3532 PR_RESIDENCY_MODE_FRAME_CNT, 3533 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3534 }; 3535 3536 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3537 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3538 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3539 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3540 3541 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3542 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3543 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3544 3545 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3546 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3547 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3548 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3549 3550 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3551 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3552 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3553 3554 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3555 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3556 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3557 3558 /** 3559 * Definition of a replay_state. 3560 */ 3561 enum replay_state { 3562 REPLAY_STATE_0 = 0x0, 3563 REPLAY_STATE_1 = 0x10, 3564 REPLAY_STATE_1A = 0x11, 3565 REPLAY_STATE_2 = 0x20, 3566 REPLAY_STATE_2A = 0x21, 3567 REPLAY_STATE_3 = 0x30, 3568 REPLAY_STATE_3INIT = 0x31, 3569 REPLAY_STATE_4 = 0x40, 3570 REPLAY_STATE_4A = 0x41, 3571 REPLAY_STATE_4B = 0x42, 3572 REPLAY_STATE_4C = 0x43, 3573 REPLAY_STATE_4D = 0x44, 3574 REPLAY_STATE_4E = 0x45, 3575 REPLAY_STATE_4B_LOCKED = 0x4A, 3576 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3577 REPLAY_STATE_5 = 0x50, 3578 REPLAY_STATE_5A = 0x51, 3579 REPLAY_STATE_5B = 0x52, 3580 REPLAY_STATE_5A_LOCKED = 0x5A, 3581 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3582 REPLAY_STATE_6 = 0x60, 3583 REPLAY_STATE_6A = 0x61, 3584 REPLAY_STATE_6B = 0x62, 3585 REPLAY_STATE_INVALID = 0xFF, 3586 }; 3587 3588 /** 3589 * Replay command sub-types. 3590 */ 3591 enum dmub_cmd_replay_type { 3592 /** 3593 * Copy driver-calculated parameters to REPLAY state. 3594 */ 3595 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3596 /** 3597 * Enable REPLAY. 3598 */ 3599 DMUB_CMD__REPLAY_ENABLE = 1, 3600 /** 3601 * Set Replay power option. 3602 */ 3603 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3604 /** 3605 * Set coasting vtotal. 3606 */ 3607 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3608 /** 3609 * Set power opt and coasting vtotal. 3610 */ 3611 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3612 /** 3613 * Set disabled iiming sync. 3614 */ 3615 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3616 /** 3617 * Set Residency Frameupdate Timer. 3618 */ 3619 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3620 /** 3621 * Set pseudo vtotal 3622 */ 3623 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3624 /** 3625 * Set adaptive sync sdp enabled 3626 */ 3627 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3628 /** 3629 * Set Replay General command. 3630 */ 3631 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3632 }; 3633 3634 /** 3635 * Replay general command sub-types. 3636 */ 3637 enum dmub_cmd_replay_general_subtype { 3638 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3639 /** 3640 * TODO: For backward compatible, allow new command only. 3641 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3642 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3643 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3644 */ 3645 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3646 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3647 }; 3648 3649 /** 3650 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3651 */ 3652 struct dmub_cmd_replay_copy_settings_data { 3653 /** 3654 * Flags that can be set by driver to change some replay behaviour. 3655 */ 3656 union replay_debug_flags debug; 3657 3658 /** 3659 * @flags: Flags used to determine feature functionality. 3660 */ 3661 union replay_hw_flags flags; 3662 3663 /** 3664 * DPP HW instance. 3665 */ 3666 uint8_t dpp_inst; 3667 /** 3668 * OTG HW instance. 3669 */ 3670 uint8_t otg_inst; 3671 /** 3672 * DIG FE HW instance. 3673 */ 3674 uint8_t digfe_inst; 3675 /** 3676 * DIG BE HW instance. 3677 */ 3678 uint8_t digbe_inst; 3679 /** 3680 * AUX HW instance. 3681 */ 3682 uint8_t aux_inst; 3683 /** 3684 * Panel Instance. 3685 * Panel isntance to identify which psr_state to use 3686 * Currently the support is only for 0 or 1 3687 */ 3688 uint8_t panel_inst; 3689 /** 3690 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3691 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3692 */ 3693 uint8_t pixel_deviation_per_line; 3694 /** 3695 * @max_deviation_line: The max number of deviation line that can keep the timing 3696 * synchronized between the Source and Sink during Replay normal sleep mode. 3697 */ 3698 uint8_t max_deviation_line; 3699 /** 3700 * Length of each horizontal line in ns. 3701 */ 3702 uint32_t line_time_in_ns; 3703 /** 3704 * PHY instance. 3705 */ 3706 uint8_t dpphy_inst; 3707 /** 3708 * Determines if SMU optimzations are enabled/disabled. 3709 */ 3710 uint8_t smu_optimizations_en; 3711 /** 3712 * Determines if timing sync are enabled/disabled. 3713 */ 3714 uint8_t replay_timing_sync_supported; 3715 /* 3716 * Use FSM state for Replay power up/down 3717 */ 3718 uint8_t use_phy_fsm; 3719 }; 3720 3721 /** 3722 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3723 */ 3724 struct dmub_rb_cmd_replay_copy_settings { 3725 /** 3726 * Command header. 3727 */ 3728 struct dmub_cmd_header header; 3729 /** 3730 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3731 */ 3732 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3733 }; 3734 3735 /** 3736 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3737 */ 3738 enum replay_enable { 3739 /** 3740 * Disable REPLAY. 3741 */ 3742 REPLAY_DISABLE = 0, 3743 /** 3744 * Enable REPLAY. 3745 */ 3746 REPLAY_ENABLE = 1, 3747 }; 3748 3749 /** 3750 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3751 */ 3752 struct dmub_rb_cmd_replay_enable_data { 3753 /** 3754 * Replay enable or disable. 3755 */ 3756 uint8_t enable; 3757 /** 3758 * Panel Instance. 3759 * Panel isntance to identify which replay_state to use 3760 * Currently the support is only for 0 or 1 3761 */ 3762 uint8_t panel_inst; 3763 /** 3764 * Phy state to enter. 3765 * Values to use are defined in dmub_phy_fsm_state 3766 */ 3767 uint8_t phy_fsm_state; 3768 /** 3769 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3770 * Set this using enum phy_link_rate. 3771 * This does not support HDMI/DP2 for now. 3772 */ 3773 uint8_t phy_rate; 3774 }; 3775 3776 /** 3777 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3778 * Replay enable/disable is controlled using action in data. 3779 */ 3780 struct dmub_rb_cmd_replay_enable { 3781 /** 3782 * Command header. 3783 */ 3784 struct dmub_cmd_header header; 3785 3786 struct dmub_rb_cmd_replay_enable_data data; 3787 }; 3788 3789 /** 3790 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3791 */ 3792 struct dmub_cmd_replay_set_power_opt_data { 3793 /** 3794 * Panel Instance. 3795 * Panel isntance to identify which replay_state to use 3796 * Currently the support is only for 0 or 1 3797 */ 3798 uint8_t panel_inst; 3799 /** 3800 * Explicit padding to 4 byte boundary. 3801 */ 3802 uint8_t pad[3]; 3803 /** 3804 * REPLAY power option 3805 */ 3806 uint32_t power_opt; 3807 }; 3808 3809 /** 3810 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3811 */ 3812 struct dmub_cmd_replay_set_timing_sync_data { 3813 /** 3814 * Panel Instance. 3815 * Panel isntance to identify which replay_state to use 3816 * Currently the support is only for 0 or 1 3817 */ 3818 uint8_t panel_inst; 3819 /** 3820 * REPLAY set_timing_sync 3821 */ 3822 uint8_t timing_sync_supported; 3823 /** 3824 * Explicit padding to 4 byte boundary. 3825 */ 3826 uint8_t pad[2]; 3827 }; 3828 3829 /** 3830 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3831 */ 3832 struct dmub_cmd_replay_set_pseudo_vtotal { 3833 /** 3834 * Panel Instance. 3835 * Panel isntance to identify which replay_state to use 3836 * Currently the support is only for 0 or 1 3837 */ 3838 uint8_t panel_inst; 3839 /** 3840 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3841 */ 3842 uint16_t vtotal; 3843 /** 3844 * Explicit padding to 4 byte boundary. 3845 */ 3846 uint8_t pad; 3847 }; 3848 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3849 /** 3850 * Panel Instance. 3851 * Panel isntance to identify which replay_state to use 3852 * Currently the support is only for 0 or 1 3853 */ 3854 uint8_t panel_inst; 3855 /** 3856 * enabled: set adaptive sync sdp enabled 3857 */ 3858 uint8_t force_disabled; 3859 3860 uint8_t pad[2]; 3861 }; 3862 struct dmub_cmd_replay_set_general_cmd_data { 3863 /** 3864 * Panel Instance. 3865 * Panel isntance to identify which replay_state to use 3866 * Currently the support is only for 0 or 1 3867 */ 3868 uint8_t panel_inst; 3869 /** 3870 * subtype: replay general cmd sub type 3871 */ 3872 uint8_t subtype; 3873 3874 uint8_t pad[2]; 3875 /** 3876 * config data with param1 and param2 3877 */ 3878 uint32_t param1; 3879 3880 uint32_t param2; 3881 }; 3882 3883 /** 3884 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3885 */ 3886 struct dmub_rb_cmd_replay_set_power_opt { 3887 /** 3888 * Command header. 3889 */ 3890 struct dmub_cmd_header header; 3891 /** 3892 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3893 */ 3894 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3895 }; 3896 3897 /** 3898 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3899 */ 3900 struct dmub_cmd_replay_set_coasting_vtotal_data { 3901 /** 3902 * 16-bit value dicated by driver that indicates the coasting vtotal. 3903 */ 3904 uint16_t coasting_vtotal; 3905 /** 3906 * REPLAY control version. 3907 */ 3908 uint8_t cmd_version; 3909 /** 3910 * Panel Instance. 3911 * Panel isntance to identify which replay_state to use 3912 * Currently the support is only for 0 or 1 3913 */ 3914 uint8_t panel_inst; 3915 /** 3916 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3917 */ 3918 uint16_t coasting_vtotal_high; 3919 /** 3920 * Explicit padding to 4 byte boundary. 3921 */ 3922 uint8_t pad[2]; 3923 }; 3924 3925 /** 3926 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3927 */ 3928 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3929 /** 3930 * Command header. 3931 */ 3932 struct dmub_cmd_header header; 3933 /** 3934 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3935 */ 3936 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3937 }; 3938 3939 /** 3940 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3941 */ 3942 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3943 /** 3944 * Command header. 3945 */ 3946 struct dmub_cmd_header header; 3947 /** 3948 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3949 */ 3950 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3951 /** 3952 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3953 */ 3954 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3955 }; 3956 3957 /** 3958 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3959 */ 3960 struct dmub_rb_cmd_replay_set_timing_sync { 3961 /** 3962 * Command header. 3963 */ 3964 struct dmub_cmd_header header; 3965 /** 3966 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3967 */ 3968 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3969 }; 3970 3971 /** 3972 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3973 */ 3974 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3975 /** 3976 * Command header. 3977 */ 3978 struct dmub_cmd_header header; 3979 /** 3980 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3981 */ 3982 struct dmub_cmd_replay_set_pseudo_vtotal data; 3983 }; 3984 3985 /** 3986 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3987 */ 3988 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3989 /** 3990 * Command header. 3991 */ 3992 struct dmub_cmd_header header; 3993 /** 3994 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3995 */ 3996 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3997 }; 3998 3999 /** 4000 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4001 */ 4002 struct dmub_rb_cmd_replay_set_general_cmd { 4003 /** 4004 * Command header. 4005 */ 4006 struct dmub_cmd_header header; 4007 /** 4008 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4009 */ 4010 struct dmub_cmd_replay_set_general_cmd_data data; 4011 }; 4012 4013 /** 4014 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4015 */ 4016 struct dmub_cmd_replay_frameupdate_timer_data { 4017 /** 4018 * Panel Instance. 4019 * Panel isntance to identify which replay_state to use 4020 * Currently the support is only for 0 or 1 4021 */ 4022 uint8_t panel_inst; 4023 /** 4024 * Replay Frameupdate Timer Enable or not 4025 */ 4026 uint8_t enable; 4027 /** 4028 * REPLAY force reflash frame update number 4029 */ 4030 uint16_t frameupdate_count; 4031 }; 4032 /** 4033 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4034 */ 4035 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4036 /** 4037 * Command header. 4038 */ 4039 struct dmub_cmd_header header; 4040 /** 4041 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4042 */ 4043 struct dmub_cmd_replay_frameupdate_timer_data data; 4044 }; 4045 4046 /** 4047 * Definition union of replay command set 4048 */ 4049 union dmub_replay_cmd_set { 4050 /** 4051 * Panel Instance. 4052 * Panel isntance to identify which replay_state to use 4053 * Currently the support is only for 0 or 1 4054 */ 4055 uint8_t panel_inst; 4056 /** 4057 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4058 */ 4059 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4060 /** 4061 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4062 */ 4063 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4064 /** 4065 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4066 */ 4067 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4068 /** 4069 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4070 */ 4071 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4072 /** 4073 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4074 */ 4075 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4076 }; 4077 4078 /** 4079 * Set of HW components that can be locked. 4080 * 4081 * Note: If updating with more HW components, fields 4082 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4083 */ 4084 union dmub_hw_lock_flags { 4085 /** 4086 * Set of HW components that can be locked. 4087 */ 4088 struct { 4089 /** 4090 * Lock/unlock OTG master update lock. 4091 */ 4092 uint8_t lock_pipe : 1; 4093 /** 4094 * Lock/unlock cursor. 4095 */ 4096 uint8_t lock_cursor : 1; 4097 /** 4098 * Lock/unlock global update lock. 4099 */ 4100 uint8_t lock_dig : 1; 4101 /** 4102 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4103 */ 4104 uint8_t triple_buffer_lock : 1; 4105 } bits; 4106 4107 /** 4108 * Union for HW Lock flags. 4109 */ 4110 uint8_t u8All; 4111 }; 4112 4113 /** 4114 * Instances of HW to be locked. 4115 * 4116 * Note: If updating with more HW components, fields 4117 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4118 */ 4119 struct dmub_hw_lock_inst_flags { 4120 /** 4121 * OTG HW instance for OTG master update lock. 4122 */ 4123 uint8_t otg_inst; 4124 /** 4125 * OPP instance for cursor lock. 4126 */ 4127 uint8_t opp_inst; 4128 /** 4129 * OTG HW instance for global update lock. 4130 * TODO: Remove, and re-use otg_inst. 4131 */ 4132 uint8_t dig_inst; 4133 /** 4134 * Explicit pad to 4 byte boundary. 4135 */ 4136 uint8_t pad; 4137 }; 4138 4139 /** 4140 * Clients that can acquire the HW Lock Manager. 4141 * 4142 * Note: If updating with more clients, fields in 4143 * dmub_inbox0_cmd_lock_hw must be updated to match. 4144 */ 4145 enum hw_lock_client { 4146 /** 4147 * Driver is the client of HW Lock Manager. 4148 */ 4149 HW_LOCK_CLIENT_DRIVER = 0, 4150 /** 4151 * PSR SU is the client of HW Lock Manager. 4152 */ 4153 HW_LOCK_CLIENT_PSR_SU = 1, 4154 HW_LOCK_CLIENT_SUBVP = 3, 4155 /** 4156 * Replay is the client of HW Lock Manager. 4157 */ 4158 HW_LOCK_CLIENT_REPLAY = 4, 4159 HW_LOCK_CLIENT_FAMS2 = 5, 4160 /** 4161 * Invalid client. 4162 */ 4163 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4164 }; 4165 4166 /** 4167 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4168 */ 4169 struct dmub_cmd_lock_hw_data { 4170 /** 4171 * Specifies the client accessing HW Lock Manager. 4172 */ 4173 enum hw_lock_client client; 4174 /** 4175 * HW instances to be locked. 4176 */ 4177 struct dmub_hw_lock_inst_flags inst_flags; 4178 /** 4179 * Which components to be locked. 4180 */ 4181 union dmub_hw_lock_flags hw_locks; 4182 /** 4183 * Specifies lock/unlock. 4184 */ 4185 uint8_t lock; 4186 /** 4187 * HW can be unlocked separately from releasing the HW Lock Mgr. 4188 * This flag is set if the client wishes to release the object. 4189 */ 4190 uint8_t should_release; 4191 /** 4192 * Explicit padding to 4 byte boundary. 4193 */ 4194 uint8_t pad; 4195 }; 4196 4197 /** 4198 * Definition of a DMUB_CMD__HW_LOCK command. 4199 * Command is used by driver and FW. 4200 */ 4201 struct dmub_rb_cmd_lock_hw { 4202 /** 4203 * Command header. 4204 */ 4205 struct dmub_cmd_header header; 4206 /** 4207 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4208 */ 4209 struct dmub_cmd_lock_hw_data lock_hw_data; 4210 }; 4211 4212 /** 4213 * ABM command sub-types. 4214 */ 4215 enum dmub_cmd_abm_type { 4216 /** 4217 * Initialize parameters for ABM algorithm. 4218 * Data is passed through an indirect buffer. 4219 */ 4220 DMUB_CMD__ABM_INIT_CONFIG = 0, 4221 /** 4222 * Set OTG and panel HW instance. 4223 */ 4224 DMUB_CMD__ABM_SET_PIPE = 1, 4225 /** 4226 * Set user requested backklight level. 4227 */ 4228 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4229 /** 4230 * Set ABM operating/aggression level. 4231 */ 4232 DMUB_CMD__ABM_SET_LEVEL = 3, 4233 /** 4234 * Set ambient light level. 4235 */ 4236 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4237 /** 4238 * Enable/disable fractional duty cycle for backlight PWM. 4239 */ 4240 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4241 4242 /** 4243 * unregister vertical interrupt after steady state is reached 4244 */ 4245 DMUB_CMD__ABM_PAUSE = 6, 4246 4247 /** 4248 * Save and Restore ABM state. On save we save parameters, and 4249 * on restore we update state with passed in data. 4250 */ 4251 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4252 4253 /** 4254 * Query ABM caps. 4255 */ 4256 DMUB_CMD__ABM_QUERY_CAPS = 8, 4257 4258 /** 4259 * Set ABM Events 4260 */ 4261 DMUB_CMD__ABM_SET_EVENT = 9, 4262 4263 /** 4264 * Get the current ACE curve. 4265 */ 4266 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4267 }; 4268 4269 struct abm_ace_curve { 4270 /** 4271 * @offsets: ACE curve offsets. 4272 */ 4273 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4274 4275 /** 4276 * @thresholds: ACE curve thresholds. 4277 */ 4278 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4279 4280 /** 4281 * @slopes: ACE curve slopes. 4282 */ 4283 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4284 }; 4285 4286 struct fixed_pt_format { 4287 /** 4288 * @sign_bit: Indicates whether one bit is reserved for the sign. 4289 */ 4290 bool sign_bit; 4291 4292 /** 4293 * @num_int_bits: Number of bits used for integer part. 4294 */ 4295 uint8_t num_int_bits; 4296 4297 /** 4298 * @num_frac_bits: Number of bits used for fractional part. 4299 */ 4300 uint8_t num_frac_bits; 4301 4302 /** 4303 * @pad: Explicit padding to 4 byte boundary. 4304 */ 4305 uint8_t pad; 4306 }; 4307 4308 struct abm_caps { 4309 /** 4310 * @num_hg_bins: Number of histogram bins. 4311 */ 4312 uint8_t num_hg_bins; 4313 4314 /** 4315 * @num_ace_segments: Number of ACE curve segments. 4316 */ 4317 uint8_t num_ace_segments; 4318 4319 /** 4320 * @pad: Explicit padding to 4 byte boundary. 4321 */ 4322 uint8_t pad[2]; 4323 4324 /** 4325 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4326 */ 4327 struct fixed_pt_format ace_thresholds_format; 4328 4329 /** 4330 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4331 */ 4332 struct fixed_pt_format ace_offsets_format; 4333 4334 /** 4335 * @ace_slopes_format: Format of the ACE slopes. 4336 */ 4337 struct fixed_pt_format ace_slopes_format; 4338 }; 4339 4340 /** 4341 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4342 * Requirements: 4343 * - Padded explicitly to 32-bit boundary. 4344 * - Must ensure this structure matches the one on driver-side, 4345 * otherwise it won't be aligned. 4346 */ 4347 struct abm_config_table { 4348 /** 4349 * Gamma curve thresholds, used for crgb conversion. 4350 */ 4351 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4352 /** 4353 * Gamma curve offsets, used for crgb conversion. 4354 */ 4355 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4356 /** 4357 * Gamma curve slopes, used for crgb conversion. 4358 */ 4359 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4360 /** 4361 * Custom backlight curve thresholds. 4362 */ 4363 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4364 /** 4365 * Custom backlight curve offsets. 4366 */ 4367 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4368 /** 4369 * Ambient light thresholds. 4370 */ 4371 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4372 /** 4373 * Minimum programmable backlight. 4374 */ 4375 uint16_t min_abm_backlight; // 122B 4376 /** 4377 * Minimum reduction values. 4378 */ 4379 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4380 /** 4381 * Maximum reduction values. 4382 */ 4383 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4384 /** 4385 * Bright positive gain. 4386 */ 4387 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4388 /** 4389 * Dark negative gain. 4390 */ 4391 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4392 /** 4393 * Hybrid factor. 4394 */ 4395 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4396 /** 4397 * Contrast factor. 4398 */ 4399 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4400 /** 4401 * Deviation gain. 4402 */ 4403 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4404 /** 4405 * Minimum knee. 4406 */ 4407 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4408 /** 4409 * Maximum knee. 4410 */ 4411 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4412 /** 4413 * Unused. 4414 */ 4415 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4416 /** 4417 * Explicit padding to 4 byte boundary. 4418 */ 4419 uint8_t pad3[3]; // 229B 4420 /** 4421 * Backlight ramp reduction. 4422 */ 4423 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4424 /** 4425 * Backlight ramp start. 4426 */ 4427 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4428 }; 4429 4430 /** 4431 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4432 */ 4433 struct dmub_cmd_abm_set_pipe_data { 4434 /** 4435 * OTG HW instance. 4436 */ 4437 uint8_t otg_inst; 4438 4439 /** 4440 * Panel Control HW instance. 4441 */ 4442 uint8_t panel_inst; 4443 4444 /** 4445 * Controls how ABM will interpret a set pipe or set level command. 4446 */ 4447 uint8_t set_pipe_option; 4448 4449 /** 4450 * Unused. 4451 * TODO: Remove. 4452 */ 4453 uint8_t ramping_boundary; 4454 4455 /** 4456 * PwrSeq HW Instance. 4457 */ 4458 uint8_t pwrseq_inst; 4459 4460 /** 4461 * Explicit padding to 4 byte boundary. 4462 */ 4463 uint8_t pad[3]; 4464 }; 4465 4466 /** 4467 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4468 */ 4469 struct dmub_rb_cmd_abm_set_pipe { 4470 /** 4471 * Command header. 4472 */ 4473 struct dmub_cmd_header header; 4474 4475 /** 4476 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4477 */ 4478 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4479 }; 4480 4481 /** 4482 * Type of backlight control method to be used by ABM module 4483 */ 4484 enum dmub_backlight_control_type { 4485 /** 4486 * PWM Backlight control 4487 */ 4488 DMU_BACKLIGHT_CONTROL_PWM = 0, 4489 /** 4490 * VESA Aux-based backlight control 4491 */ 4492 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4493 /** 4494 * AMD DPCD Aux-based backlight control 4495 */ 4496 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4497 }; 4498 4499 /** 4500 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4501 */ 4502 struct dmub_cmd_abm_set_backlight_data { 4503 /** 4504 * Number of frames to ramp to backlight user level. 4505 */ 4506 uint32_t frame_ramp; 4507 4508 /** 4509 * Requested backlight level from user. 4510 */ 4511 uint32_t backlight_user_level; 4512 4513 /** 4514 * ABM control version. 4515 */ 4516 uint8_t version; 4517 4518 /** 4519 * Panel Control HW instance mask. 4520 * Bit 0 is Panel Control HW instance 0. 4521 * Bit 1 is Panel Control HW instance 1. 4522 */ 4523 uint8_t panel_mask; 4524 4525 /** 4526 * AUX HW Instance. 4527 */ 4528 uint8_t aux_inst; 4529 4530 /** 4531 * Explicit padding to 4 byte boundary. 4532 */ 4533 uint8_t pad[1]; 4534 4535 /** 4536 * Backlight control type. 4537 * Value 0 is PWM backlight control. 4538 * Value 1 is VAUX backlight control. 4539 * Value 2 is AMD DPCD AUX backlight control. 4540 */ 4541 enum dmub_backlight_control_type backlight_control_type; 4542 4543 /** 4544 * Minimum luminance in nits. 4545 */ 4546 uint32_t min_luminance; 4547 4548 /** 4549 * Maximum luminance in nits. 4550 */ 4551 uint32_t max_luminance; 4552 4553 /** 4554 * Minimum backlight in pwm. 4555 */ 4556 uint32_t min_backlight_pwm; 4557 4558 /** 4559 * Maximum backlight in pwm. 4560 */ 4561 uint32_t max_backlight_pwm; 4562 }; 4563 4564 /** 4565 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4566 */ 4567 struct dmub_rb_cmd_abm_set_backlight { 4568 /** 4569 * Command header. 4570 */ 4571 struct dmub_cmd_header header; 4572 4573 /** 4574 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4575 */ 4576 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4577 }; 4578 4579 /** 4580 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4581 */ 4582 struct dmub_cmd_abm_set_level_data { 4583 /** 4584 * Set current ABM operating/aggression level. 4585 */ 4586 uint32_t level; 4587 4588 /** 4589 * ABM control version. 4590 */ 4591 uint8_t version; 4592 4593 /** 4594 * Panel Control HW instance mask. 4595 * Bit 0 is Panel Control HW instance 0. 4596 * Bit 1 is Panel Control HW instance 1. 4597 */ 4598 uint8_t panel_mask; 4599 4600 /** 4601 * Explicit padding to 4 byte boundary. 4602 */ 4603 uint8_t pad[2]; 4604 }; 4605 4606 /** 4607 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4608 */ 4609 struct dmub_rb_cmd_abm_set_level { 4610 /** 4611 * Command header. 4612 */ 4613 struct dmub_cmd_header header; 4614 4615 /** 4616 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4617 */ 4618 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4619 }; 4620 4621 /** 4622 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4623 */ 4624 struct dmub_cmd_abm_set_ambient_level_data { 4625 /** 4626 * Ambient light sensor reading from OS. 4627 */ 4628 uint32_t ambient_lux; 4629 4630 /** 4631 * ABM control version. 4632 */ 4633 uint8_t version; 4634 4635 /** 4636 * Panel Control HW instance mask. 4637 * Bit 0 is Panel Control HW instance 0. 4638 * Bit 1 is Panel Control HW instance 1. 4639 */ 4640 uint8_t panel_mask; 4641 4642 /** 4643 * Explicit padding to 4 byte boundary. 4644 */ 4645 uint8_t pad[2]; 4646 }; 4647 4648 /** 4649 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4650 */ 4651 struct dmub_rb_cmd_abm_set_ambient_level { 4652 /** 4653 * Command header. 4654 */ 4655 struct dmub_cmd_header header; 4656 4657 /** 4658 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4659 */ 4660 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4661 }; 4662 4663 /** 4664 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4665 */ 4666 struct dmub_cmd_abm_set_pwm_frac_data { 4667 /** 4668 * Enable/disable fractional duty cycle for backlight PWM. 4669 * TODO: Convert to uint8_t. 4670 */ 4671 uint32_t fractional_pwm; 4672 4673 /** 4674 * ABM control version. 4675 */ 4676 uint8_t version; 4677 4678 /** 4679 * Panel Control HW instance mask. 4680 * Bit 0 is Panel Control HW instance 0. 4681 * Bit 1 is Panel Control HW instance 1. 4682 */ 4683 uint8_t panel_mask; 4684 4685 /** 4686 * Explicit padding to 4 byte boundary. 4687 */ 4688 uint8_t pad[2]; 4689 }; 4690 4691 /** 4692 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4693 */ 4694 struct dmub_rb_cmd_abm_set_pwm_frac { 4695 /** 4696 * Command header. 4697 */ 4698 struct dmub_cmd_header header; 4699 4700 /** 4701 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4702 */ 4703 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4704 }; 4705 4706 /** 4707 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4708 */ 4709 struct dmub_cmd_abm_init_config_data { 4710 /** 4711 * Location of indirect buffer used to pass init data to ABM. 4712 */ 4713 union dmub_addr src; 4714 4715 /** 4716 * Indirect buffer length. 4717 */ 4718 uint16_t bytes; 4719 4720 4721 /** 4722 * ABM control version. 4723 */ 4724 uint8_t version; 4725 4726 /** 4727 * Panel Control HW instance mask. 4728 * Bit 0 is Panel Control HW instance 0. 4729 * Bit 1 is Panel Control HW instance 1. 4730 */ 4731 uint8_t panel_mask; 4732 4733 /** 4734 * Explicit padding to 4 byte boundary. 4735 */ 4736 uint8_t pad[2]; 4737 }; 4738 4739 /** 4740 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4741 */ 4742 struct dmub_rb_cmd_abm_init_config { 4743 /** 4744 * Command header. 4745 */ 4746 struct dmub_cmd_header header; 4747 4748 /** 4749 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4750 */ 4751 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4752 }; 4753 4754 /** 4755 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4756 */ 4757 4758 struct dmub_cmd_abm_pause_data { 4759 4760 /** 4761 * Panel Control HW instance mask. 4762 * Bit 0 is Panel Control HW instance 0. 4763 * Bit 1 is Panel Control HW instance 1. 4764 */ 4765 uint8_t panel_mask; 4766 4767 /** 4768 * OTG hw instance 4769 */ 4770 uint8_t otg_inst; 4771 4772 /** 4773 * Enable or disable ABM pause 4774 */ 4775 uint8_t enable; 4776 4777 /** 4778 * Explicit padding to 4 byte boundary. 4779 */ 4780 uint8_t pad[1]; 4781 }; 4782 4783 /** 4784 * Definition of a DMUB_CMD__ABM_PAUSE command. 4785 */ 4786 struct dmub_rb_cmd_abm_pause { 4787 /** 4788 * Command header. 4789 */ 4790 struct dmub_cmd_header header; 4791 4792 /** 4793 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4794 */ 4795 struct dmub_cmd_abm_pause_data abm_pause_data; 4796 }; 4797 4798 /** 4799 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4800 */ 4801 struct dmub_cmd_abm_query_caps_in { 4802 /** 4803 * Panel instance. 4804 */ 4805 uint8_t panel_inst; 4806 4807 /** 4808 * Explicit padding to 4 byte boundary. 4809 */ 4810 uint8_t pad[3]; 4811 }; 4812 4813 /** 4814 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4815 */ 4816 struct dmub_cmd_abm_query_caps_out { 4817 /** 4818 * SW Algorithm caps. 4819 */ 4820 struct abm_caps sw_caps; 4821 4822 /** 4823 * ABM HW caps. 4824 */ 4825 struct abm_caps hw_caps; 4826 }; 4827 4828 /** 4829 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4830 */ 4831 struct dmub_rb_cmd_abm_query_caps { 4832 /** 4833 * Command header. 4834 */ 4835 struct dmub_cmd_header header; 4836 4837 /** 4838 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4839 */ 4840 union { 4841 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4842 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4843 } data; 4844 }; 4845 4846 /** 4847 * enum dmub_abm_ace_curve_type - ACE curve type. 4848 */ 4849 enum dmub_abm_ace_curve_type { 4850 /** 4851 * ACE curve as defined by the SW layer. 4852 */ 4853 ABM_ACE_CURVE_TYPE__SW = 0, 4854 /** 4855 * ACE curve as defined by the SW to HW translation interface layer. 4856 */ 4857 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4858 }; 4859 4860 /** 4861 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4862 */ 4863 struct dmub_rb_cmd_abm_get_ace_curve { 4864 /** 4865 * Command header. 4866 */ 4867 struct dmub_cmd_header header; 4868 4869 /** 4870 * Address where ACE curve should be copied. 4871 */ 4872 union dmub_addr dest; 4873 4874 /** 4875 * Type of ACE curve being queried. 4876 */ 4877 enum dmub_abm_ace_curve_type ace_type; 4878 4879 /** 4880 * Indirect buffer length. 4881 */ 4882 uint16_t bytes; 4883 4884 /** 4885 * eDP panel instance. 4886 */ 4887 uint8_t panel_inst; 4888 4889 /** 4890 * Explicit padding to 4 byte boundary. 4891 */ 4892 uint8_t pad; 4893 }; 4894 4895 /** 4896 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4897 */ 4898 struct dmub_rb_cmd_abm_save_restore { 4899 /** 4900 * Command header. 4901 */ 4902 struct dmub_cmd_header header; 4903 4904 /** 4905 * OTG hw instance 4906 */ 4907 uint8_t otg_inst; 4908 4909 /** 4910 * Enable or disable ABM pause 4911 */ 4912 uint8_t freeze; 4913 4914 /** 4915 * Explicit padding to 4 byte boundary. 4916 */ 4917 uint8_t debug; 4918 4919 /** 4920 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4921 */ 4922 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4923 }; 4924 4925 /** 4926 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4927 */ 4928 4929 struct dmub_cmd_abm_set_event_data { 4930 4931 /** 4932 * VB Scaling Init. Strength Mapping 4933 * Byte 0: 0~255 for VB level 0 4934 * Byte 1: 0~255 for VB level 1 4935 * Byte 2: 0~255 for VB level 2 4936 * Byte 3: 0~255 for VB level 3 4937 */ 4938 uint32_t vb_scaling_strength_mapping; 4939 /** 4940 * VariBright Scaling Enable 4941 */ 4942 uint8_t vb_scaling_enable; 4943 /** 4944 * Panel Control HW instance mask. 4945 * Bit 0 is Panel Control HW instance 0. 4946 * Bit 1 is Panel Control HW instance 1. 4947 */ 4948 uint8_t panel_mask; 4949 4950 /** 4951 * Explicit padding to 4 byte boundary. 4952 */ 4953 uint8_t pad[2]; 4954 }; 4955 4956 /** 4957 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 4958 */ 4959 struct dmub_rb_cmd_abm_set_event { 4960 /** 4961 * Command header. 4962 */ 4963 struct dmub_cmd_header header; 4964 4965 /** 4966 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4967 */ 4968 struct dmub_cmd_abm_set_event_data abm_set_event_data; 4969 }; 4970 4971 /** 4972 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4973 */ 4974 struct dmub_cmd_query_feature_caps_data { 4975 /** 4976 * DMUB feature capabilities. 4977 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4978 */ 4979 struct dmub_feature_caps feature_caps; 4980 }; 4981 4982 /** 4983 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4984 */ 4985 struct dmub_rb_cmd_query_feature_caps { 4986 /** 4987 * Command header. 4988 */ 4989 struct dmub_cmd_header header; 4990 /** 4991 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4992 */ 4993 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4994 }; 4995 4996 /** 4997 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4998 */ 4999 struct dmub_cmd_visual_confirm_color_data { 5000 /** 5001 * DMUB visual confirm color 5002 */ 5003 struct dmub_visual_confirm_color visual_confirm_color; 5004 }; 5005 5006 /** 5007 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5008 */ 5009 struct dmub_rb_cmd_get_visual_confirm_color { 5010 /** 5011 * Command header. 5012 */ 5013 struct dmub_cmd_header header; 5014 /** 5015 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5016 */ 5017 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5018 }; 5019 5020 /** 5021 * enum dmub_cmd_panel_cntl_type - Panel control command. 5022 */ 5023 enum dmub_cmd_panel_cntl_type { 5024 /** 5025 * Initializes embedded panel hardware blocks. 5026 */ 5027 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5028 /** 5029 * Queries backlight info for the embedded panel. 5030 */ 5031 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5032 /** 5033 * Sets the PWM Freq as per user's requirement. 5034 */ 5035 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5036 }; 5037 5038 /** 5039 * struct dmub_cmd_panel_cntl_data - Panel control data. 5040 */ 5041 struct dmub_cmd_panel_cntl_data { 5042 uint32_t pwrseq_inst; /**< pwrseq instance */ 5043 uint32_t current_backlight; /* in/out */ 5044 uint32_t bl_pwm_cntl; /* in/out */ 5045 uint32_t bl_pwm_period_cntl; /* in/out */ 5046 uint32_t bl_pwm_ref_div1; /* in/out */ 5047 uint8_t is_backlight_on : 1; /* in/out */ 5048 uint8_t is_powered_on : 1; /* in/out */ 5049 uint8_t padding[3]; 5050 uint32_t bl_pwm_ref_div2; /* in/out */ 5051 uint8_t reserved[4]; 5052 }; 5053 5054 /** 5055 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5056 */ 5057 struct dmub_rb_cmd_panel_cntl { 5058 struct dmub_cmd_header header; /**< header */ 5059 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5060 }; 5061 5062 struct dmub_optc_state { 5063 uint32_t v_total_max; 5064 uint32_t v_total_min; 5065 uint32_t tg_inst; 5066 }; 5067 5068 struct dmub_rb_cmd_drr_update { 5069 struct dmub_cmd_header header; 5070 struct dmub_optc_state dmub_optc_state_req; 5071 }; 5072 5073 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5074 uint32_t pix_clk_100hz; 5075 uint8_t max_ramp_step; 5076 uint8_t pipes; 5077 uint8_t min_refresh_in_hz; 5078 uint8_t pipe_count; 5079 uint8_t pipe_index[4]; 5080 }; 5081 5082 struct dmub_cmd_fw_assisted_mclk_switch_config { 5083 uint8_t fams_enabled; 5084 uint8_t visual_confirm_enabled; 5085 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5086 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5087 }; 5088 5089 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5090 struct dmub_cmd_header header; 5091 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5092 }; 5093 5094 /** 5095 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5096 */ 5097 struct dmub_cmd_lvtma_control_data { 5098 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5099 uint8_t bypass_panel_control_wait; 5100 uint8_t reserved_0[2]; /**< For future use */ 5101 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5102 uint8_t reserved_1[3]; /**< For future use */ 5103 }; 5104 5105 /** 5106 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5107 */ 5108 struct dmub_rb_cmd_lvtma_control { 5109 /** 5110 * Command header. 5111 */ 5112 struct dmub_cmd_header header; 5113 /** 5114 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5115 */ 5116 struct dmub_cmd_lvtma_control_data data; 5117 }; 5118 5119 /** 5120 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5121 */ 5122 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5123 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5124 uint8_t is_usb; /**< is phy is usb */ 5125 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5126 uint8_t is_dp4; /**< is dp in 4 lane */ 5127 }; 5128 5129 /** 5130 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5131 */ 5132 struct dmub_rb_cmd_transmitter_query_dp_alt { 5133 struct dmub_cmd_header header; /**< header */ 5134 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5135 }; 5136 5137 struct phy_test_mode { 5138 uint8_t mode; 5139 uint8_t pat0; 5140 uint8_t pad[2]; 5141 }; 5142 5143 /** 5144 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5145 */ 5146 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5147 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5148 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5149 uint8_t lane_num; /**< Number of lanes */ 5150 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5151 struct phy_test_mode test_mode; 5152 enum dmub_phy_fsm_state state; 5153 uint32_t status; 5154 uint8_t pad; 5155 }; 5156 5157 /** 5158 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5159 */ 5160 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5161 struct dmub_cmd_header header; /**< header */ 5162 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5163 }; 5164 5165 /** 5166 * Maximum number of bytes a chunk sent to DMUB for parsing 5167 */ 5168 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5169 5170 /** 5171 * Represent a chunk of CEA blocks sent to DMUB for parsing 5172 */ 5173 struct dmub_cmd_send_edid_cea { 5174 uint16_t offset; /**< offset into the CEA block */ 5175 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5176 uint16_t cea_total_length; /**< total length of the CEA block */ 5177 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5178 uint8_t pad[3]; /**< padding and for future expansion */ 5179 }; 5180 5181 /** 5182 * Result of VSDB parsing from CEA block 5183 */ 5184 struct dmub_cmd_edid_cea_amd_vsdb { 5185 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5186 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5187 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5188 uint16_t min_frame_rate; /**< Maximum frame rate */ 5189 uint16_t max_frame_rate; /**< Minimum frame rate */ 5190 }; 5191 5192 /** 5193 * Result of sending a CEA chunk 5194 */ 5195 struct dmub_cmd_edid_cea_ack { 5196 uint16_t offset; /**< offset of the chunk into the CEA block */ 5197 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5198 uint8_t pad; /**< padding and for future expansion */ 5199 }; 5200 5201 /** 5202 * Specify whether the result is an ACK/NACK or the parsing has finished 5203 */ 5204 enum dmub_cmd_edid_cea_reply_type { 5205 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5206 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5207 }; 5208 5209 /** 5210 * Definition of a DMUB_CMD__EDID_CEA command. 5211 */ 5212 struct dmub_rb_cmd_edid_cea { 5213 struct dmub_cmd_header header; /**< Command header */ 5214 union dmub_cmd_edid_cea_data { 5215 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5216 struct dmub_cmd_edid_cea_output { /**< output with results */ 5217 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5218 union { 5219 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5220 struct dmub_cmd_edid_cea_ack ack; 5221 }; 5222 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5223 } data; /**< Command data */ 5224 5225 }; 5226 5227 /** 5228 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5229 */ 5230 struct dmub_cmd_cable_id_input { 5231 uint8_t phy_inst; /**< phy inst for cable id data */ 5232 }; 5233 5234 /** 5235 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5236 */ 5237 struct dmub_cmd_cable_id_output { 5238 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5239 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5240 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5241 uint8_t RESERVED :2; /**< reserved means not defined */ 5242 }; 5243 5244 /** 5245 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5246 */ 5247 struct dmub_rb_cmd_get_usbc_cable_id { 5248 struct dmub_cmd_header header; /**< Command header */ 5249 /** 5250 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5251 */ 5252 union dmub_cmd_cable_id_data { 5253 struct dmub_cmd_cable_id_input input; /**< Input */ 5254 struct dmub_cmd_cable_id_output output; /**< Output */ 5255 uint8_t output_raw; /**< Raw data output */ 5256 } data; 5257 }; 5258 5259 /** 5260 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5261 */ 5262 enum dmub_cmd_secure_display_type { 5263 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5264 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5265 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5266 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5267 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5268 }; 5269 5270 #define MAX_ROI_NUM 2 5271 5272 struct dmub_cmd_roi_info { 5273 uint16_t x_start; 5274 uint16_t x_end; 5275 uint16_t y_start; 5276 uint16_t y_end; 5277 uint8_t otg_id; 5278 uint8_t phy_id; 5279 }; 5280 5281 struct dmub_cmd_roi_window_ctl { 5282 uint16_t x_start; 5283 uint16_t x_end; 5284 uint16_t y_start; 5285 uint16_t y_end; 5286 bool enable; 5287 }; 5288 5289 struct dmub_cmd_roi_ctl_info { 5290 uint8_t otg_id; 5291 uint8_t phy_id; 5292 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5293 }; 5294 5295 /** 5296 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5297 */ 5298 struct dmub_rb_cmd_secure_display { 5299 struct dmub_cmd_header header; 5300 /** 5301 * Data passed from driver to dmub firmware. 5302 */ 5303 struct dmub_cmd_roi_info roi_info; 5304 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5305 }; 5306 5307 /** 5308 * Command type of a DMUB_CMD__PSP command 5309 */ 5310 enum dmub_cmd_psp_type { 5311 DMUB_CMD__PSP_ASSR_ENABLE = 0 5312 }; 5313 5314 /** 5315 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5316 */ 5317 struct dmub_cmd_assr_enable_data { 5318 /** 5319 * ASSR enable or disable. 5320 */ 5321 uint8_t enable; 5322 /** 5323 * PHY port type. 5324 * Indicates eDP / non-eDP port type 5325 */ 5326 uint8_t phy_port_type; 5327 /** 5328 * PHY port ID. 5329 */ 5330 uint8_t phy_port_id; 5331 /** 5332 * Link encoder index. 5333 */ 5334 uint8_t link_enc_index; 5335 /** 5336 * HPO mode. 5337 */ 5338 uint8_t hpo_mode; 5339 5340 /** 5341 * Reserved field. 5342 */ 5343 uint8_t reserved[7]; 5344 }; 5345 5346 /** 5347 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5348 */ 5349 struct dmub_rb_cmd_assr_enable { 5350 /** 5351 * Command header. 5352 */ 5353 struct dmub_cmd_header header; 5354 5355 /** 5356 * Assr data. 5357 */ 5358 struct dmub_cmd_assr_enable_data assr_data; 5359 5360 /** 5361 * Reserved field. 5362 */ 5363 uint32_t reserved[3]; 5364 }; 5365 5366 /** 5367 * union dmub_rb_cmd - DMUB inbox command. 5368 */ 5369 union dmub_rb_cmd { 5370 /** 5371 * Elements shared with all commands. 5372 */ 5373 struct dmub_rb_cmd_common cmd_common; 5374 /** 5375 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5376 */ 5377 struct dmub_rb_cmd_read_modify_write read_modify_write; 5378 /** 5379 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5380 */ 5381 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5382 /** 5383 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5384 */ 5385 struct dmub_rb_cmd_burst_write burst_write; 5386 /** 5387 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5388 */ 5389 struct dmub_rb_cmd_reg_wait reg_wait; 5390 /** 5391 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5392 */ 5393 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5394 /** 5395 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5396 */ 5397 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5398 /** 5399 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5400 */ 5401 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5402 /** 5403 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5404 */ 5405 struct dmub_rb_cmd_dpphy_init dpphy_init; 5406 /** 5407 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5408 */ 5409 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5410 /** 5411 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5412 */ 5413 struct dmub_rb_cmd_domain_control domain_control; 5414 /** 5415 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5416 */ 5417 struct dmub_rb_cmd_psr_set_version psr_set_version; 5418 /** 5419 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5420 */ 5421 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5422 /** 5423 * Definition of a DMUB_CMD__PSR_ENABLE command. 5424 */ 5425 struct dmub_rb_cmd_psr_enable psr_enable; 5426 /** 5427 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5428 */ 5429 struct dmub_rb_cmd_psr_set_level psr_set_level; 5430 /** 5431 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5432 */ 5433 struct dmub_rb_cmd_psr_force_static psr_force_static; 5434 /** 5435 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5436 */ 5437 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5438 /** 5439 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5440 */ 5441 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5442 /** 5443 * Definition of a DMUB_CMD__HW_LOCK command. 5444 * Command is used by driver and FW. 5445 */ 5446 struct dmub_rb_cmd_lock_hw lock_hw; 5447 /** 5448 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5449 */ 5450 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5451 /** 5452 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5453 */ 5454 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5455 /** 5456 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5457 */ 5458 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5459 /** 5460 * Definition of a DMUB_CMD__MALL command. 5461 */ 5462 struct dmub_rb_cmd_mall mall; 5463 5464 /** 5465 * Definition of a DMUB_CMD__CAB command. 5466 */ 5467 struct dmub_rb_cmd_cab_for_ss cab; 5468 5469 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5470 5471 /** 5472 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5473 */ 5474 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5475 5476 /** 5477 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5478 */ 5479 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5480 5481 /** 5482 * Definition of DMUB_CMD__PANEL_CNTL commands. 5483 */ 5484 struct dmub_rb_cmd_panel_cntl panel_cntl; 5485 5486 /** 5487 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5488 */ 5489 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5490 5491 /** 5492 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5493 */ 5494 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5495 5496 /** 5497 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5498 */ 5499 struct dmub_rb_cmd_abm_set_level abm_set_level; 5500 5501 /** 5502 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5503 */ 5504 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5505 5506 /** 5507 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5508 */ 5509 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5510 5511 /** 5512 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5513 */ 5514 struct dmub_rb_cmd_abm_init_config abm_init_config; 5515 5516 /** 5517 * Definition of a DMUB_CMD__ABM_PAUSE command. 5518 */ 5519 struct dmub_rb_cmd_abm_pause abm_pause; 5520 5521 /** 5522 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5523 */ 5524 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5525 5526 /** 5527 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5528 */ 5529 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5530 5531 /** 5532 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5533 */ 5534 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5535 5536 /** 5537 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5538 */ 5539 struct dmub_rb_cmd_abm_set_event abm_set_event; 5540 5541 /** 5542 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5543 */ 5544 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5545 5546 /** 5547 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5548 */ 5549 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5550 5551 /** 5552 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5553 */ 5554 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5555 5556 /** 5557 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5558 */ 5559 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5560 struct dmub_rb_cmd_drr_update drr_update; 5561 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5562 5563 /** 5564 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5565 */ 5566 struct dmub_rb_cmd_lvtma_control lvtma_control; 5567 /** 5568 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5569 */ 5570 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5571 /** 5572 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5573 */ 5574 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5575 /** 5576 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5577 */ 5578 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5579 /** 5580 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5581 */ 5582 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 5583 /** 5584 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5585 */ 5586 struct dmub_rb_cmd_set_config_request set_config_request; 5587 /** 5588 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5589 */ 5590 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5591 /** 5592 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 5593 */ 5594 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 5595 /** 5596 * Definition of a DMUB_CMD__EDID_CEA command. 5597 */ 5598 struct dmub_rb_cmd_edid_cea edid_cea; 5599 /** 5600 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5601 */ 5602 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5603 5604 /** 5605 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5606 */ 5607 struct dmub_rb_cmd_query_hpd_state query_hpd; 5608 /** 5609 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5610 */ 5611 struct dmub_rb_cmd_secure_display secure_display; 5612 5613 /** 5614 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5615 */ 5616 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5617 /** 5618 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5619 */ 5620 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5621 /** 5622 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 5623 */ 5624 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 5625 /* 5626 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5627 */ 5628 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5629 /** 5630 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5631 */ 5632 struct dmub_rb_cmd_replay_enable replay_enable; 5633 /** 5634 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5635 */ 5636 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5637 /** 5638 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5639 */ 5640 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5641 /** 5642 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5643 */ 5644 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5645 5646 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5647 /** 5648 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5649 */ 5650 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5651 /** 5652 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5653 */ 5654 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5655 /** 5656 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5657 */ 5658 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5659 /** 5660 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5661 */ 5662 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5663 /** 5664 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5665 */ 5666 struct dmub_rb_cmd_assr_enable assr_enable; 5667 struct dmub_rb_cmd_fams2 fams2_config; 5668 5669 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5670 5671 struct dmub_rb_cmd_fams2_flip fams2_flip; 5672 }; 5673 5674 /** 5675 * union dmub_rb_out_cmd - Outbox command 5676 */ 5677 union dmub_rb_out_cmd { 5678 /** 5679 * Parameters common to every command. 5680 */ 5681 struct dmub_rb_cmd_common cmd_common; 5682 /** 5683 * AUX reply command. 5684 */ 5685 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5686 /** 5687 * HPD notify command. 5688 */ 5689 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5690 /** 5691 * SET_CONFIG reply command. 5692 */ 5693 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5694 /** 5695 * DPIA notification command. 5696 */ 5697 struct dmub_rb_cmd_dpia_notification dpia_notification; 5698 /** 5699 * HPD sense notification command. 5700 */ 5701 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5702 }; 5703 #pragma pack(pop) 5704 5705 5706 //============================================================================== 5707 //</DMUB_CMD>=================================================================== 5708 //============================================================================== 5709 //< DMUB_RB>==================================================================== 5710 //============================================================================== 5711 5712 /** 5713 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5714 */ 5715 struct dmub_rb_init_params { 5716 void *ctx; /**< Caller provided context pointer */ 5717 void *base_address; /**< CPU base address for ring's data */ 5718 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5719 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5720 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5721 }; 5722 5723 /** 5724 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5725 */ 5726 struct dmub_rb { 5727 void *base_address; /**< CPU address for the ring's data */ 5728 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5729 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5730 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5731 5732 void *ctx; /**< Caller provided context pointer */ 5733 void *dmub; /**< Pointer to the DMUB interface */ 5734 }; 5735 5736 /** 5737 * @brief Checks if the ringbuffer is empty. 5738 * 5739 * @param rb DMUB Ringbuffer 5740 * @return true if empty 5741 * @return false otherwise 5742 */ 5743 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5744 { 5745 return (rb->wrpt == rb->rptr); 5746 } 5747 5748 /** 5749 * @brief Checks if the ringbuffer is full 5750 * 5751 * @param rb DMUB Ringbuffer 5752 * @return true if full 5753 * @return false otherwise 5754 */ 5755 static inline bool dmub_rb_full(struct dmub_rb *rb) 5756 { 5757 uint32_t data_count; 5758 5759 if (rb->wrpt >= rb->rptr) 5760 data_count = rb->wrpt - rb->rptr; 5761 else 5762 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5763 5764 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5765 } 5766 5767 /** 5768 * @brief Pushes a command into the ringbuffer 5769 * 5770 * @param rb DMUB ringbuffer 5771 * @param cmd The command to push 5772 * @return true if the ringbuffer was not full 5773 * @return false otherwise 5774 */ 5775 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5776 const union dmub_rb_cmd *cmd) 5777 { 5778 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5779 const uint64_t *src = (const uint64_t *)cmd; 5780 uint8_t i; 5781 5782 if (dmub_rb_full(rb)) 5783 return false; 5784 5785 // copying data 5786 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5787 *dst++ = *src++; 5788 5789 rb->wrpt += DMUB_RB_CMD_SIZE; 5790 5791 if (rb->wrpt >= rb->capacity) 5792 rb->wrpt %= rb->capacity; 5793 5794 return true; 5795 } 5796 5797 /** 5798 * @brief Pushes a command into the DMUB outbox ringbuffer 5799 * 5800 * @param rb DMUB outbox ringbuffer 5801 * @param cmd Outbox command 5802 * @return true if not full 5803 * @return false otherwise 5804 */ 5805 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5806 const union dmub_rb_out_cmd *cmd) 5807 { 5808 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 5809 const uint8_t *src = (const uint8_t *)cmd; 5810 5811 if (dmub_rb_full(rb)) 5812 return false; 5813 5814 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 5815 5816 rb->wrpt += DMUB_RB_CMD_SIZE; 5817 5818 if (rb->wrpt >= rb->capacity) 5819 rb->wrpt %= rb->capacity; 5820 5821 return true; 5822 } 5823 5824 /** 5825 * @brief Returns the next unprocessed command in the ringbuffer. 5826 * 5827 * @param rb DMUB ringbuffer 5828 * @param cmd The command to return 5829 * @return true if not empty 5830 * @return false otherwise 5831 */ 5832 static inline bool dmub_rb_front(struct dmub_rb *rb, 5833 union dmub_rb_cmd **cmd) 5834 { 5835 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 5836 5837 if (dmub_rb_empty(rb)) 5838 return false; 5839 5840 *cmd = (union dmub_rb_cmd *)rb_cmd; 5841 5842 return true; 5843 } 5844 5845 /** 5846 * @brief Determines the next ringbuffer offset. 5847 * 5848 * @param rb DMUB inbox ringbuffer 5849 * @param num_cmds Number of commands 5850 * @param next_rptr The next offset in the ringbuffer 5851 */ 5852 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 5853 uint32_t num_cmds, 5854 uint32_t *next_rptr) 5855 { 5856 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 5857 5858 if (*next_rptr >= rb->capacity) 5859 *next_rptr %= rb->capacity; 5860 } 5861 5862 /** 5863 * @brief Returns a pointer to a command in the inbox. 5864 * 5865 * @param rb DMUB inbox ringbuffer 5866 * @param cmd The inbox command to return 5867 * @param rptr The ringbuffer offset 5868 * @return true if not empty 5869 * @return false otherwise 5870 */ 5871 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 5872 union dmub_rb_cmd **cmd, 5873 uint32_t rptr) 5874 { 5875 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 5876 5877 if (dmub_rb_empty(rb)) 5878 return false; 5879 5880 *cmd = (union dmub_rb_cmd *)rb_cmd; 5881 5882 return true; 5883 } 5884 5885 /** 5886 * @brief Returns the next unprocessed command in the outbox. 5887 * 5888 * @param rb DMUB outbox ringbuffer 5889 * @param cmd The outbox command to return 5890 * @return true if not empty 5891 * @return false otherwise 5892 */ 5893 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 5894 union dmub_rb_out_cmd *cmd) 5895 { 5896 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 5897 uint64_t *dst = (uint64_t *)cmd; 5898 uint8_t i; 5899 5900 if (dmub_rb_empty(rb)) 5901 return false; 5902 5903 // copying data 5904 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5905 *dst++ = *src++; 5906 5907 return true; 5908 } 5909 5910 /** 5911 * @brief Removes the front entry in the ringbuffer. 5912 * 5913 * @param rb DMUB ringbuffer 5914 * @return true if the command was removed 5915 * @return false if there were no commands 5916 */ 5917 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 5918 { 5919 if (dmub_rb_empty(rb)) 5920 return false; 5921 5922 rb->rptr += DMUB_RB_CMD_SIZE; 5923 5924 if (rb->rptr >= rb->capacity) 5925 rb->rptr %= rb->capacity; 5926 5927 return true; 5928 } 5929 5930 /** 5931 * @brief Flushes commands in the ringbuffer to framebuffer memory. 5932 * 5933 * Avoids a race condition where DMCUB accesses memory while 5934 * there are still writes in flight to framebuffer. 5935 * 5936 * @param rb DMUB ringbuffer 5937 */ 5938 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 5939 { 5940 uint32_t rptr = rb->rptr; 5941 uint32_t wptr = rb->wrpt; 5942 5943 while (rptr != wptr) { 5944 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 5945 uint8_t i; 5946 5947 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5948 (void)READ_ONCE(*data++); 5949 5950 rptr += DMUB_RB_CMD_SIZE; 5951 if (rptr >= rb->capacity) 5952 rptr %= rb->capacity; 5953 } 5954 } 5955 5956 /** 5957 * @brief Initializes a DMCUB ringbuffer 5958 * 5959 * @param rb DMUB ringbuffer 5960 * @param init_params initial configuration for the ringbuffer 5961 */ 5962 static inline void dmub_rb_init(struct dmub_rb *rb, 5963 struct dmub_rb_init_params *init_params) 5964 { 5965 rb->base_address = init_params->base_address; 5966 rb->capacity = init_params->capacity; 5967 rb->rptr = init_params->read_ptr; 5968 rb->wrpt = init_params->write_ptr; 5969 } 5970 5971 /** 5972 * @brief Copies output data from in/out commands into the given command. 5973 * 5974 * @param rb DMUB ringbuffer 5975 * @param cmd Command to copy data into 5976 */ 5977 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5978 union dmub_rb_cmd *cmd) 5979 { 5980 // Copy rb entry back into command 5981 uint8_t *rd_ptr = (rb->rptr == 0) ? 5982 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5983 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5984 5985 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5986 } 5987 5988 //============================================================================== 5989 //</DMUB_RB>==================================================================== 5990 //============================================================================== 5991 #endif /* _DMUB_CMD_H_ */ 5992