1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0x992f4893d 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 66 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 #define DMUB_MAX_SUBVP_STREAMS 2 121 122 /* Trace buffer offset for entry */ 123 #define TRACE_BUFFER_ENTRY_OFFSET 16 124 125 /** 126 * ABM control version legacy 127 */ 128 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 129 130 /** 131 * ABM control version with multi edp support 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 134 135 /** 136 * Physical framebuffer address location, 64-bit. 137 */ 138 #ifndef PHYSICAL_ADDRESS_LOC 139 #define PHYSICAL_ADDRESS_LOC union large_integer 140 #endif 141 142 /** 143 * OS/FW agnostic memcpy 144 */ 145 #ifndef dmub_memcpy 146 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 147 #endif 148 149 /** 150 * OS/FW agnostic memset 151 */ 152 #ifndef dmub_memset 153 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 154 #endif 155 156 #if defined(__cplusplus) 157 extern "C" { 158 #endif 159 160 /** 161 * OS/FW agnostic udelay 162 */ 163 #ifndef dmub_udelay 164 #define dmub_udelay(microseconds) udelay(microseconds) 165 #endif 166 167 /** 168 * Number of nanoseconds per DMUB tick. 169 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 170 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 171 */ 172 #define NS_PER_DMUB_TICK 10 173 174 /** 175 * union dmub_addr - DMUB physical/virtual 64-bit address. 176 */ 177 union dmub_addr { 178 struct { 179 uint32_t low_part; /**< Lower 32 bits */ 180 uint32_t high_part; /**< Upper 32 bits */ 181 } u; /*<< Low/high bit access */ 182 uint64_t quad_part; /*<< 64 bit address */ 183 }; 184 185 /** 186 * Flags that can be set by driver to change some PSR behaviour. 187 */ 188 union dmub_psr_debug_flags { 189 /** 190 * Debug flags. 191 */ 192 struct { 193 /** 194 * Enable visual confirm in FW. 195 */ 196 uint32_t visual_confirm : 1; 197 /** 198 * Use HW Lock Mgr object to do HW locking in FW. 199 */ 200 uint32_t use_hw_lock_mgr : 1; 201 202 /** 203 * Unused. 204 * TODO: Remove. 205 */ 206 uint32_t log_line_nums : 1; 207 } bitfields; 208 209 /** 210 * Union for debug flags. 211 */ 212 uint32_t u32All; 213 }; 214 215 /** 216 * DMUB feature capabilities. 217 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 218 */ 219 struct dmub_feature_caps { 220 /** 221 * Max PSR version supported by FW. 222 */ 223 uint8_t psr; 224 uint8_t reserved[7]; 225 }; 226 227 #if defined(__cplusplus) 228 } 229 #endif 230 231 //============================================================================== 232 //</DMUB_TYPES>================================================================= 233 //============================================================================== 234 //< DMUB_META>================================================================== 235 //============================================================================== 236 #pragma pack(push, 1) 237 238 /* Magic value for identifying dmub_fw_meta_info */ 239 #define DMUB_FW_META_MAGIC 0x444D5542 240 241 /* Offset from the end of the file to the dmub_fw_meta_info */ 242 #define DMUB_FW_META_OFFSET 0x24 243 244 /** 245 * struct dmub_fw_meta_info - metadata associated with fw binary 246 * 247 * NOTE: This should be considered a stable API. Fields should 248 * not be repurposed or reordered. New fields should be 249 * added instead to extend the structure. 250 * 251 * @magic_value: magic value identifying DMUB firmware meta info 252 * @fw_region_size: size of the firmware state region 253 * @trace_buffer_size: size of the tracebuffer region 254 * @fw_version: the firmware version information 255 * @dal_fw: 1 if the firmware is DAL 256 */ 257 struct dmub_fw_meta_info { 258 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 259 uint32_t fw_region_size; /**< size of the firmware state region */ 260 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 261 uint32_t fw_version; /**< the firmware version information */ 262 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 263 uint8_t reserved[3]; /**< padding bits */ 264 }; 265 266 /** 267 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 268 */ 269 union dmub_fw_meta { 270 struct dmub_fw_meta_info info; /**< metadata info */ 271 uint8_t reserved[64]; /**< padding bits */ 272 }; 273 274 #pragma pack(pop) 275 276 //============================================================================== 277 //< DMUB Trace Buffer>================================================================ 278 //============================================================================== 279 /** 280 * dmub_trace_code_t - firmware trace code, 32-bits 281 */ 282 typedef uint32_t dmub_trace_code_t; 283 284 /** 285 * struct dmcub_trace_buf_entry - Firmware trace entry 286 */ 287 struct dmcub_trace_buf_entry { 288 dmub_trace_code_t trace_code; /**< trace code for the event */ 289 uint32_t tick_count; /**< the tick count at time of trace */ 290 uint32_t param0; /**< trace defined parameter 0 */ 291 uint32_t param1; /**< trace defined parameter 1 */ 292 }; 293 294 //============================================================================== 295 //< DMUB_STATUS>================================================================ 296 //============================================================================== 297 298 /** 299 * DMCUB scratch registers can be used to determine firmware status. 300 * Current scratch register usage is as follows: 301 * 302 * SCRATCH0: FW Boot Status register 303 * SCRATCH15: FW Boot Options register 304 */ 305 306 /** 307 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 308 */ 309 union dmub_fw_boot_status { 310 struct { 311 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 312 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 313 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 314 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 315 } bits; /**< status bits */ 316 uint32_t all; /**< 32-bit access to status bits */ 317 }; 318 319 /** 320 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 321 */ 322 enum dmub_fw_boot_status_bit { 323 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 324 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 325 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 326 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 327 }; 328 329 /** 330 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 331 */ 332 union dmub_fw_boot_options { 333 struct { 334 uint32_t pemu_env : 1; /**< 1 if PEMU */ 335 uint32_t fpga_env : 1; /**< 1 if FPGA */ 336 uint32_t optimized_init : 1; /**< 1 if optimized init */ 337 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 338 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 339 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 340 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 341 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 342 #else 343 uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */ 344 #endif 345 uint32_t reserved : 25; /**< reserved */ 346 } bits; /**< boot bits */ 347 uint32_t all; /**< 32-bit access to bits */ 348 }; 349 350 enum dmub_fw_boot_options_bit { 351 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 352 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 353 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 354 }; 355 356 //============================================================================== 357 //</DMUB_STATUS>================================================================ 358 //============================================================================== 359 //< DMUB_VBIOS>================================================================= 360 //============================================================================== 361 362 /* 363 * enum dmub_cmd_vbios_type - VBIOS commands. 364 * 365 * Command IDs should be treated as stable ABI. 366 * Do not reuse or modify IDs. 367 */ 368 enum dmub_cmd_vbios_type { 369 /** 370 * Configures the DIG encoder. 371 */ 372 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 373 /** 374 * Controls the PHY. 375 */ 376 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 377 /** 378 * Sets the pixel clock/symbol clock. 379 */ 380 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 381 /** 382 * Enables or disables power gating. 383 */ 384 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 385 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 386 }; 387 388 //============================================================================== 389 //</DMUB_VBIOS>================================================================= 390 //============================================================================== 391 //< DMUB_GPINT>================================================================= 392 //============================================================================== 393 394 /** 395 * The shifts and masks below may alternatively be used to format and read 396 * the command register bits. 397 */ 398 399 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 400 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 401 402 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 403 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 404 405 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 406 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 407 408 /** 409 * Command responses. 410 */ 411 412 /** 413 * Return response for DMUB_GPINT__STOP_FW command. 414 */ 415 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 416 417 /** 418 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 419 */ 420 union dmub_gpint_data_register { 421 struct { 422 uint32_t param : 16; /**< 16-bit parameter */ 423 uint32_t command_code : 12; /**< GPINT command */ 424 uint32_t status : 4; /**< Command status bit */ 425 } bits; /**< GPINT bit access */ 426 uint32_t all; /**< GPINT 32-bit access */ 427 }; 428 429 /* 430 * enum dmub_gpint_command - GPINT command to DMCUB FW 431 * 432 * Command IDs should be treated as stable ABI. 433 * Do not reuse or modify IDs. 434 */ 435 enum dmub_gpint_command { 436 /** 437 * Invalid command, ignored. 438 */ 439 DMUB_GPINT__INVALID_COMMAND = 0, 440 /** 441 * DESC: Queries the firmware version. 442 * RETURN: Firmware version. 443 */ 444 DMUB_GPINT__GET_FW_VERSION = 1, 445 /** 446 * DESC: Halts the firmware. 447 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 448 */ 449 DMUB_GPINT__STOP_FW = 2, 450 /** 451 * DESC: Get PSR state from FW. 452 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 453 */ 454 DMUB_GPINT__GET_PSR_STATE = 7, 455 /** 456 * DESC: Notifies DMCUB of the currently active streams. 457 * ARGS: Stream mask, 1 bit per active stream index. 458 */ 459 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 460 /** 461 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 462 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 463 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 464 * RETURN: PSR residency in milli-percent. 465 */ 466 DMUB_GPINT__PSR_RESIDENCY = 9, 467 }; 468 469 /** 470 * INBOX0 generic command definition 471 */ 472 union dmub_inbox0_cmd_common { 473 struct { 474 uint32_t command_code: 8; /**< INBOX0 command code */ 475 uint32_t param: 24; /**< 24-bit parameter */ 476 } bits; 477 uint32_t all; 478 }; 479 480 /** 481 * INBOX0 hw_lock command definition 482 */ 483 union dmub_inbox0_cmd_lock_hw { 484 struct { 485 uint32_t command_code: 8; 486 487 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 488 uint32_t hw_lock_client: 1; 489 490 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 491 uint32_t otg_inst: 3; 492 uint32_t opp_inst: 3; 493 uint32_t dig_inst: 3; 494 495 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 496 uint32_t lock_pipe: 1; 497 uint32_t lock_cursor: 1; 498 uint32_t lock_dig: 1; 499 uint32_t triple_buffer_lock: 1; 500 501 uint32_t lock: 1; /**< Lock */ 502 uint32_t should_release: 1; /**< Release */ 503 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 504 } bits; 505 uint32_t all; 506 }; 507 508 union dmub_inbox0_data_register { 509 union dmub_inbox0_cmd_common inbox0_cmd_common; 510 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 511 }; 512 513 enum dmub_inbox0_command { 514 /** 515 * DESC: Invalid command, ignored. 516 */ 517 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 518 /** 519 * DESC: Notification to acquire/release HW lock 520 * ARGS: 521 */ 522 DMUB_INBOX0_CMD__HW_LOCK = 1, 523 }; 524 //============================================================================== 525 //</DMUB_GPINT>================================================================= 526 //============================================================================== 527 //< DMUB_CMD>=================================================================== 528 //============================================================================== 529 530 /** 531 * Size in bytes of each DMUB command. 532 */ 533 #define DMUB_RB_CMD_SIZE 64 534 535 /** 536 * Maximum number of items in the DMUB ringbuffer. 537 */ 538 #define DMUB_RB_MAX_ENTRY 128 539 540 /** 541 * Ringbuffer size in bytes. 542 */ 543 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 544 545 /** 546 * REG_SET mask for reg offload. 547 */ 548 #define REG_SET_MASK 0xFFFF 549 550 /* 551 * enum dmub_cmd_type - DMUB inbox command. 552 * 553 * Command IDs should be treated as stable ABI. 554 * Do not reuse or modify IDs. 555 */ 556 enum dmub_cmd_type { 557 /** 558 * Invalid command. 559 */ 560 DMUB_CMD__NULL = 0, 561 /** 562 * Read modify write register sequence offload. 563 */ 564 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 565 /** 566 * Field update register sequence offload. 567 */ 568 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 569 /** 570 * Burst write sequence offload. 571 */ 572 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 573 /** 574 * Reg wait sequence offload. 575 */ 576 DMUB_CMD__REG_REG_WAIT = 4, 577 /** 578 * Workaround to avoid HUBP underflow during NV12 playback. 579 */ 580 DMUB_CMD__PLAT_54186_WA = 5, 581 /** 582 * Command type used to query FW feature caps. 583 */ 584 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 585 /** 586 * Command type used for all PSR commands. 587 */ 588 DMUB_CMD__PSR = 64, 589 /** 590 * Command type used for all MALL commands. 591 */ 592 DMUB_CMD__MALL = 65, 593 /** 594 * Command type used for all ABM commands. 595 */ 596 DMUB_CMD__ABM = 66, 597 /** 598 * Command type used for HW locking in FW. 599 */ 600 DMUB_CMD__HW_LOCK = 69, 601 /** 602 * Command type used to access DP AUX. 603 */ 604 DMUB_CMD__DP_AUX_ACCESS = 70, 605 /** 606 * Command type used for OUTBOX1 notification enable 607 */ 608 DMUB_CMD__OUTBOX1_ENABLE = 71, 609 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 610 /** 611 * Command type used for all idle optimization commands. 612 */ 613 DMUB_CMD__IDLE_OPT = 72, 614 /** 615 * Command type used for all clock manager commands. 616 */ 617 DMUB_CMD__CLK_MGR = 73, 618 /** 619 * Command type used for all panel control commands. 620 */ 621 DMUB_CMD__PANEL_CNTL = 74, 622 #endif 623 /** 624 * Command type used for all VBIOS interface commands. 625 */ 626 DMUB_CMD__VBIOS = 128, 627 }; 628 629 /** 630 * enum dmub_out_cmd_type - DMUB outbox commands. 631 */ 632 enum dmub_out_cmd_type { 633 /** 634 * Invalid outbox command, ignored. 635 */ 636 DMUB_OUT_CMD__NULL = 0, 637 /** 638 * Command type used for DP AUX Reply data notification 639 */ 640 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 641 /** 642 * Command type used for DP HPD event notification 643 */ 644 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 645 }; 646 647 #pragma pack(push, 1) 648 649 /** 650 * struct dmub_cmd_header - Common command header fields. 651 */ 652 struct dmub_cmd_header { 653 unsigned int type : 8; /**< command type */ 654 unsigned int sub_type : 8; /**< command sub type */ 655 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 656 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 657 unsigned int reserved0 : 6; /**< reserved bits */ 658 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 659 unsigned int reserved1 : 2; /**< reserved bits */ 660 }; 661 662 /* 663 * struct dmub_cmd_read_modify_write_sequence - Read modify write 664 * 665 * 60 payload bytes can hold up to 5 sets of read modify writes, 666 * each take 3 dwords. 667 * 668 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 669 * 670 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 671 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 672 */ 673 struct dmub_cmd_read_modify_write_sequence { 674 uint32_t addr; /**< register address */ 675 uint32_t modify_mask; /**< modify mask */ 676 uint32_t modify_value; /**< modify value */ 677 }; 678 679 /** 680 * Maximum number of ops in read modify write sequence. 681 */ 682 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 683 684 /** 685 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 686 */ 687 struct dmub_rb_cmd_read_modify_write { 688 struct dmub_cmd_header header; /**< command header */ 689 /** 690 * Read modify write sequence. 691 */ 692 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 693 }; 694 695 /* 696 * Update a register with specified masks and values sequeunce 697 * 698 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 699 * 700 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 701 * 702 * 703 * USE CASE: 704 * 1. auto-increment register where additional read would update pointer and produce wrong result 705 * 2. toggle a bit without read in the middle 706 */ 707 708 struct dmub_cmd_reg_field_update_sequence { 709 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 710 uint32_t modify_value; /**< value to update with */ 711 }; 712 713 /** 714 * Maximum number of ops in field update sequence. 715 */ 716 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 717 718 /** 719 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 720 */ 721 struct dmub_rb_cmd_reg_field_update_sequence { 722 struct dmub_cmd_header header; /**< command header */ 723 uint32_t addr; /**< register address */ 724 /** 725 * Field update sequence. 726 */ 727 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 728 }; 729 730 731 /** 732 * Maximum number of burst write values. 733 */ 734 #define DMUB_BURST_WRITE_VALUES__MAX 14 735 736 /* 737 * struct dmub_rb_cmd_burst_write - Burst write 738 * 739 * support use case such as writing out LUTs. 740 * 741 * 60 payload bytes can hold up to 14 values to write to given address 742 * 743 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 744 */ 745 struct dmub_rb_cmd_burst_write { 746 struct dmub_cmd_header header; /**< command header */ 747 uint32_t addr; /**< register start address */ 748 /** 749 * Burst write register values. 750 */ 751 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 752 }; 753 754 /** 755 * struct dmub_rb_cmd_common - Common command header 756 */ 757 struct dmub_rb_cmd_common { 758 struct dmub_cmd_header header; /**< command header */ 759 /** 760 * Padding to RB_CMD_SIZE 761 */ 762 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 763 }; 764 765 /** 766 * struct dmub_cmd_reg_wait_data - Register wait data 767 */ 768 struct dmub_cmd_reg_wait_data { 769 uint32_t addr; /**< Register address */ 770 uint32_t mask; /**< Mask for register bits */ 771 uint32_t condition_field_value; /**< Value to wait for */ 772 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 773 }; 774 775 /** 776 * struct dmub_rb_cmd_reg_wait - Register wait command 777 */ 778 struct dmub_rb_cmd_reg_wait { 779 struct dmub_cmd_header header; /**< Command header */ 780 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 781 }; 782 783 /** 784 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 785 * 786 * Reprograms surface parameters to avoid underflow. 787 */ 788 struct dmub_cmd_PLAT_54186_wa { 789 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 790 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 791 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 792 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 793 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 794 struct { 795 uint8_t hubp_inst : 4; /**< HUBP instance */ 796 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 797 uint8_t immediate :1; /**< Immediate flip */ 798 uint8_t vmid : 4; /**< VMID */ 799 uint8_t grph_stereo : 1; /**< 1 if stereo */ 800 uint32_t reserved : 21; /**< Reserved */ 801 } flip_params; /**< Pageflip parameters */ 802 uint32_t reserved[9]; /**< Reserved bits */ 803 }; 804 805 /** 806 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 807 */ 808 struct dmub_rb_cmd_PLAT_54186_wa { 809 struct dmub_cmd_header header; /**< Command header */ 810 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 811 }; 812 813 /** 814 * struct dmub_rb_cmd_mall - MALL command data. 815 */ 816 struct dmub_rb_cmd_mall { 817 struct dmub_cmd_header header; /**< Common command header */ 818 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 819 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 820 uint32_t tmr_delay; /**< Timer delay */ 821 uint32_t tmr_scale; /**< Timer scale */ 822 uint16_t cursor_width; /**< Cursor width in pixels */ 823 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 824 uint16_t cursor_height; /**< Cursor height in pixels */ 825 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 826 uint8_t debug_bits; /**< Debug bits */ 827 828 uint8_t reserved1; /**< Reserved bits */ 829 uint8_t reserved2; /**< Reserved bits */ 830 }; 831 832 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 833 834 /** 835 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 836 */ 837 enum dmub_cmd_idle_opt_type { 838 /** 839 * DCN hardware restore. 840 */ 841 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 842 }; 843 844 /** 845 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 846 */ 847 struct dmub_rb_cmd_idle_opt_dcn_restore { 848 struct dmub_cmd_header header; /**< header */ 849 }; 850 851 /** 852 * struct dmub_clocks - Clock update notification. 853 */ 854 struct dmub_clocks { 855 uint32_t dispclk_khz; /**< dispclk kHz */ 856 uint32_t dppclk_khz; /**< dppclk kHz */ 857 uint32_t dcfclk_khz; /**< dcfclk kHz */ 858 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 859 }; 860 861 /** 862 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 863 */ 864 enum dmub_cmd_clk_mgr_type { 865 /** 866 * Notify DMCUB of clock update. 867 */ 868 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 869 }; 870 871 /** 872 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 873 */ 874 struct dmub_rb_cmd_clk_mgr_notify_clocks { 875 struct dmub_cmd_header header; /**< header */ 876 struct dmub_clocks clocks; /**< clock data */ 877 }; 878 #endif 879 /** 880 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 881 */ 882 struct dmub_cmd_digx_encoder_control_data { 883 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 884 }; 885 886 /** 887 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 888 */ 889 struct dmub_rb_cmd_digx_encoder_control { 890 struct dmub_cmd_header header; /**< header */ 891 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 892 }; 893 894 /** 895 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 896 */ 897 struct dmub_cmd_set_pixel_clock_data { 898 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 899 }; 900 901 /** 902 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 903 */ 904 struct dmub_rb_cmd_set_pixel_clock { 905 struct dmub_cmd_header header; /**< header */ 906 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 907 }; 908 909 /** 910 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 911 */ 912 struct dmub_cmd_enable_disp_power_gating_data { 913 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 914 }; 915 916 /** 917 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 918 */ 919 struct dmub_rb_cmd_enable_disp_power_gating { 920 struct dmub_cmd_header header; /**< header */ 921 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 922 }; 923 924 /** 925 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 926 */ 927 struct dmub_dig_transmitter_control_data_v1_7 { 928 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 929 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 930 union { 931 uint8_t digmode; /**< enum atom_encode_mode_def */ 932 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 933 } mode_laneset; 934 uint8_t lanenum; /**< Number of lanes */ 935 union { 936 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 937 } symclk_units; 938 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 939 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 940 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 941 uint8_t reserved0; /**< For future use */ 942 uint8_t reserved1; /**< For future use */ 943 uint8_t reserved2[3]; /**< For future use */ 944 uint32_t reserved3[11]; /**< For future use */ 945 }; 946 947 /** 948 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 949 */ 950 union dmub_cmd_dig1_transmitter_control_data { 951 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 952 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 953 }; 954 955 /** 956 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 957 */ 958 struct dmub_rb_cmd_dig1_transmitter_control { 959 struct dmub_cmd_header header; /**< header */ 960 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 961 }; 962 963 /** 964 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 965 */ 966 struct dmub_rb_cmd_dpphy_init { 967 struct dmub_cmd_header header; /**< header */ 968 uint8_t reserved[60]; /**< reserved bits */ 969 }; 970 971 /** 972 * enum dp_aux_request_action - DP AUX request command listing. 973 * 974 * 4 AUX request command bits are shifted to high nibble. 975 */ 976 enum dp_aux_request_action { 977 /** I2C-over-AUX write request */ 978 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 979 /** I2C-over-AUX read request */ 980 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 981 /** I2C-over-AUX write status request */ 982 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 983 /** I2C-over-AUX write request with MOT=1 */ 984 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 985 /** I2C-over-AUX read request with MOT=1 */ 986 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 987 /** I2C-over-AUX write status request with MOT=1 */ 988 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 989 /** Native AUX write request */ 990 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 991 /** Native AUX read request */ 992 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 993 }; 994 995 /** 996 * enum aux_return_code_type - DP AUX process return code listing. 997 */ 998 enum aux_return_code_type { 999 /** AUX process succeeded */ 1000 AUX_RET_SUCCESS = 0, 1001 /** AUX process failed with unknown reason */ 1002 AUX_RET_ERROR_UNKNOWN, 1003 /** AUX process completed with invalid reply */ 1004 AUX_RET_ERROR_INVALID_REPLY, 1005 /** AUX process timed out */ 1006 AUX_RET_ERROR_TIMEOUT, 1007 /** HPD was low during AUX process */ 1008 AUX_RET_ERROR_HPD_DISCON, 1009 /** Failed to acquire AUX engine */ 1010 AUX_RET_ERROR_ENGINE_ACQUIRE, 1011 /** AUX request not supported */ 1012 AUX_RET_ERROR_INVALID_OPERATION, 1013 /** AUX process not available */ 1014 AUX_RET_ERROR_PROTOCOL_ERROR, 1015 }; 1016 1017 /** 1018 * enum aux_channel_type - DP AUX channel type listing. 1019 */ 1020 enum aux_channel_type { 1021 /** AUX thru Legacy DP AUX */ 1022 AUX_CHANNEL_LEGACY_DDC, 1023 /** AUX thru DPIA DP tunneling */ 1024 AUX_CHANNEL_DPIA 1025 }; 1026 1027 /** 1028 * struct aux_transaction_parameters - DP AUX request transaction data 1029 */ 1030 struct aux_transaction_parameters { 1031 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1032 uint8_t action; /**< enum dp_aux_request_action */ 1033 uint8_t length; /**< DP AUX request data length */ 1034 uint8_t reserved; /**< For future use */ 1035 uint32_t address; /**< DP AUX address */ 1036 uint8_t data[16]; /**< DP AUX write data */ 1037 }; 1038 1039 /** 1040 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1041 */ 1042 struct dmub_cmd_dp_aux_control_data { 1043 uint8_t instance; /**< AUX instance or DPIA instance */ 1044 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1045 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1046 uint8_t reserved0; /**< For future use */ 1047 uint16_t timeout; /**< timeout time in us */ 1048 uint16_t reserved1; /**< For future use */ 1049 enum aux_channel_type type; /**< enum aux_channel_type */ 1050 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1051 }; 1052 1053 /** 1054 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1055 */ 1056 struct dmub_rb_cmd_dp_aux_access { 1057 /** 1058 * Command header. 1059 */ 1060 struct dmub_cmd_header header; 1061 /** 1062 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1063 */ 1064 struct dmub_cmd_dp_aux_control_data aux_control; 1065 }; 1066 1067 /** 1068 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1069 */ 1070 struct dmub_rb_cmd_outbox1_enable { 1071 /** 1072 * Command header. 1073 */ 1074 struct dmub_cmd_header header; 1075 /** 1076 * enable: 0x0 -> disable outbox1 notification (default value) 1077 * 0x1 -> enable outbox1 notification 1078 */ 1079 uint32_t enable; 1080 }; 1081 1082 /* DP AUX Reply command - OutBox Cmd */ 1083 /** 1084 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1085 */ 1086 struct aux_reply_data { 1087 /** 1088 * Aux cmd 1089 */ 1090 uint8_t command; 1091 /** 1092 * Aux reply data length (max: 16 bytes) 1093 */ 1094 uint8_t length; 1095 /** 1096 * Alignment only 1097 */ 1098 uint8_t pad[2]; 1099 /** 1100 * Aux reply data 1101 */ 1102 uint8_t data[16]; 1103 }; 1104 1105 /** 1106 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1107 */ 1108 struct aux_reply_control_data { 1109 /** 1110 * Reserved for future use 1111 */ 1112 uint32_t handle; 1113 /** 1114 * Aux Instance 1115 */ 1116 uint8_t instance; 1117 /** 1118 * Aux transaction result: definition in enum aux_return_code_type 1119 */ 1120 uint8_t result; 1121 /** 1122 * Alignment only 1123 */ 1124 uint16_t pad; 1125 }; 1126 1127 /** 1128 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1129 */ 1130 struct dmub_rb_cmd_dp_aux_reply { 1131 /** 1132 * Command header. 1133 */ 1134 struct dmub_cmd_header header; 1135 /** 1136 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1137 */ 1138 struct aux_reply_control_data control; 1139 /** 1140 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1141 */ 1142 struct aux_reply_data reply_data; 1143 }; 1144 1145 /* DP HPD Notify command - OutBox Cmd */ 1146 /** 1147 * DP HPD Type 1148 */ 1149 enum dp_hpd_type { 1150 /** 1151 * Normal DP HPD 1152 */ 1153 DP_HPD = 0, 1154 /** 1155 * DP HPD short pulse 1156 */ 1157 DP_IRQ 1158 }; 1159 1160 /** 1161 * DP HPD Status 1162 */ 1163 enum dp_hpd_status { 1164 /** 1165 * DP_HPD status low 1166 */ 1167 DP_HPD_UNPLUG = 0, 1168 /** 1169 * DP_HPD status high 1170 */ 1171 DP_HPD_PLUG 1172 }; 1173 1174 /** 1175 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1176 */ 1177 struct dp_hpd_data { 1178 /** 1179 * DP HPD instance 1180 */ 1181 uint8_t instance; 1182 /** 1183 * HPD type 1184 */ 1185 uint8_t hpd_type; 1186 /** 1187 * HPD status: only for type: DP_HPD to indicate status 1188 */ 1189 uint8_t hpd_status; 1190 /** 1191 * Alignment only 1192 */ 1193 uint8_t pad; 1194 }; 1195 1196 /** 1197 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1198 */ 1199 struct dmub_rb_cmd_dp_hpd_notify { 1200 /** 1201 * Command header. 1202 */ 1203 struct dmub_cmd_header header; 1204 /** 1205 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1206 */ 1207 struct dp_hpd_data hpd_data; 1208 }; 1209 1210 /* 1211 * Command IDs should be treated as stable ABI. 1212 * Do not reuse or modify IDs. 1213 */ 1214 1215 /** 1216 * PSR command sub-types. 1217 */ 1218 enum dmub_cmd_psr_type { 1219 /** 1220 * Set PSR version support. 1221 */ 1222 DMUB_CMD__PSR_SET_VERSION = 0, 1223 /** 1224 * Copy driver-calculated parameters to PSR state. 1225 */ 1226 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1227 /** 1228 * Enable PSR. 1229 */ 1230 DMUB_CMD__PSR_ENABLE = 2, 1231 1232 /** 1233 * Disable PSR. 1234 */ 1235 DMUB_CMD__PSR_DISABLE = 3, 1236 1237 /** 1238 * Set PSR level. 1239 * PSR level is a 16-bit value dicated by driver that 1240 * will enable/disable different functionality. 1241 */ 1242 DMUB_CMD__PSR_SET_LEVEL = 4, 1243 1244 /** 1245 * Forces PSR enabled until an explicit PSR disable call. 1246 */ 1247 DMUB_CMD__PSR_FORCE_STATIC = 5, 1248 }; 1249 1250 /** 1251 * PSR versions. 1252 */ 1253 enum psr_version { 1254 /** 1255 * PSR version 1. 1256 */ 1257 PSR_VERSION_1 = 0, 1258 /** 1259 * PSR not supported. 1260 */ 1261 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1262 }; 1263 1264 /** 1265 * enum dmub_cmd_mall_type - MALL commands 1266 */ 1267 enum dmub_cmd_mall_type { 1268 /** 1269 * Allows display refresh from MALL. 1270 */ 1271 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1272 /** 1273 * Disallows display refresh from MALL. 1274 */ 1275 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1276 /** 1277 * Cursor copy for MALL. 1278 */ 1279 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1280 /** 1281 * Controls DF requests. 1282 */ 1283 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1284 }; 1285 1286 1287 /** 1288 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1289 */ 1290 struct dmub_cmd_psr_copy_settings_data { 1291 /** 1292 * Flags that can be set by driver to change some PSR behaviour. 1293 */ 1294 union dmub_psr_debug_flags debug; 1295 /** 1296 * 16-bit value dicated by driver that will enable/disable different functionality. 1297 */ 1298 uint16_t psr_level; 1299 /** 1300 * DPP HW instance. 1301 */ 1302 uint8_t dpp_inst; 1303 /** 1304 * MPCC HW instance. 1305 * Not used in dmub fw, 1306 * dmub fw will get active opp by reading odm registers. 1307 */ 1308 uint8_t mpcc_inst; 1309 /** 1310 * OPP HW instance. 1311 * Not used in dmub fw, 1312 * dmub fw will get active opp by reading odm registers. 1313 */ 1314 uint8_t opp_inst; 1315 /** 1316 * OTG HW instance. 1317 */ 1318 uint8_t otg_inst; 1319 /** 1320 * DIG FE HW instance. 1321 */ 1322 uint8_t digfe_inst; 1323 /** 1324 * DIG BE HW instance. 1325 */ 1326 uint8_t digbe_inst; 1327 /** 1328 * DP PHY HW instance. 1329 */ 1330 uint8_t dpphy_inst; 1331 /** 1332 * AUX HW instance. 1333 */ 1334 uint8_t aux_inst; 1335 /** 1336 * Determines if SMU optimzations are enabled/disabled. 1337 */ 1338 uint8_t smu_optimizations_en; 1339 /** 1340 * Unused. 1341 * TODO: Remove. 1342 */ 1343 uint8_t frame_delay; 1344 /** 1345 * If RFB setup time is greater than the total VBLANK time, 1346 * it is not possible for the sink to capture the video frame 1347 * in the same frame the SDP is sent. In this case, 1348 * the frame capture indication bit should be set and an extra 1349 * static frame should be transmitted to the sink. 1350 */ 1351 uint8_t frame_cap_ind; 1352 /** 1353 * Explicit padding to 4 byte boundary. 1354 */ 1355 uint8_t pad[2]; 1356 /** 1357 * Multi-display optimizations are implemented on certain ASICs. 1358 */ 1359 uint8_t multi_disp_optimizations_en; 1360 /** 1361 * The last possible line SDP may be transmitted without violating 1362 * the RFB setup time or entering the active video frame. 1363 */ 1364 uint16_t init_sdp_deadline; 1365 /** 1366 * Explicit padding to 4 byte boundary. 1367 */ 1368 uint16_t pad2; 1369 /** 1370 * Length of each horizontal line in us. 1371 */ 1372 uint32_t line_time_in_us; 1373 /** 1374 * FEC enable status in driver 1375 */ 1376 uint8_t fec_enable_status; 1377 /** 1378 * FEC re-enable delay when PSR exit. 1379 * unit is 100us, range form 0~255(0xFF). 1380 */ 1381 uint8_t fec_enable_delay_in100us; 1382 /** 1383 * Explicit padding to 4 byte boundary. 1384 */ 1385 uint8_t pad3[2]; 1386 }; 1387 1388 /** 1389 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1390 */ 1391 struct dmub_rb_cmd_psr_copy_settings { 1392 /** 1393 * Command header. 1394 */ 1395 struct dmub_cmd_header header; 1396 /** 1397 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1398 */ 1399 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1400 }; 1401 1402 /** 1403 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1404 */ 1405 struct dmub_cmd_psr_set_level_data { 1406 /** 1407 * 16-bit value dicated by driver that will enable/disable different functionality. 1408 */ 1409 uint16_t psr_level; 1410 /** 1411 * Explicit padding to 4 byte boundary. 1412 */ 1413 uint8_t pad[2]; 1414 }; 1415 1416 /** 1417 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1418 */ 1419 struct dmub_rb_cmd_psr_set_level { 1420 /** 1421 * Command header. 1422 */ 1423 struct dmub_cmd_header header; 1424 /** 1425 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1426 */ 1427 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1428 }; 1429 1430 /** 1431 * Definition of a DMUB_CMD__PSR_ENABLE command. 1432 * PSR enable/disable is controlled using the sub_type. 1433 */ 1434 struct dmub_rb_cmd_psr_enable { 1435 /** 1436 * Command header. 1437 */ 1438 struct dmub_cmd_header header; 1439 }; 1440 1441 /** 1442 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1443 */ 1444 struct dmub_cmd_psr_set_version_data { 1445 /** 1446 * PSR version that FW should implement. 1447 */ 1448 enum psr_version version; 1449 }; 1450 1451 /** 1452 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1453 */ 1454 struct dmub_rb_cmd_psr_set_version { 1455 /** 1456 * Command header. 1457 */ 1458 struct dmub_cmd_header header; 1459 /** 1460 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1461 */ 1462 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1463 }; 1464 1465 /** 1466 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1467 */ 1468 struct dmub_rb_cmd_psr_force_static { 1469 /** 1470 * Command header. 1471 */ 1472 struct dmub_cmd_header header; 1473 }; 1474 1475 /** 1476 * Set of HW components that can be locked. 1477 * 1478 * Note: If updating with more HW components, fields 1479 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1480 */ 1481 union dmub_hw_lock_flags { 1482 /** 1483 * Set of HW components that can be locked. 1484 */ 1485 struct { 1486 /** 1487 * Lock/unlock OTG master update lock. 1488 */ 1489 uint8_t lock_pipe : 1; 1490 /** 1491 * Lock/unlock cursor. 1492 */ 1493 uint8_t lock_cursor : 1; 1494 /** 1495 * Lock/unlock global update lock. 1496 */ 1497 uint8_t lock_dig : 1; 1498 /** 1499 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1500 */ 1501 uint8_t triple_buffer_lock : 1; 1502 } bits; 1503 1504 /** 1505 * Union for HW Lock flags. 1506 */ 1507 uint8_t u8All; 1508 }; 1509 1510 /** 1511 * Instances of HW to be locked. 1512 * 1513 * Note: If updating with more HW components, fields 1514 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1515 */ 1516 struct dmub_hw_lock_inst_flags { 1517 /** 1518 * OTG HW instance for OTG master update lock. 1519 */ 1520 uint8_t otg_inst; 1521 /** 1522 * OPP instance for cursor lock. 1523 */ 1524 uint8_t opp_inst; 1525 /** 1526 * OTG HW instance for global update lock. 1527 * TODO: Remove, and re-use otg_inst. 1528 */ 1529 uint8_t dig_inst; 1530 /** 1531 * Explicit pad to 4 byte boundary. 1532 */ 1533 uint8_t pad; 1534 }; 1535 1536 /** 1537 * Clients that can acquire the HW Lock Manager. 1538 * 1539 * Note: If updating with more clients, fields in 1540 * dmub_inbox0_cmd_lock_hw must be updated to match. 1541 */ 1542 enum hw_lock_client { 1543 /** 1544 * Driver is the client of HW Lock Manager. 1545 */ 1546 HW_LOCK_CLIENT_DRIVER = 0, 1547 HW_LOCK_CLIENT_SUBVP = 3, 1548 /** 1549 * Invalid client. 1550 */ 1551 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1552 }; 1553 1554 /** 1555 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1556 */ 1557 struct dmub_cmd_lock_hw_data { 1558 /** 1559 * Specifies the client accessing HW Lock Manager. 1560 */ 1561 enum hw_lock_client client; 1562 /** 1563 * HW instances to be locked. 1564 */ 1565 struct dmub_hw_lock_inst_flags inst_flags; 1566 /** 1567 * Which components to be locked. 1568 */ 1569 union dmub_hw_lock_flags hw_locks; 1570 /** 1571 * Specifies lock/unlock. 1572 */ 1573 uint8_t lock; 1574 /** 1575 * HW can be unlocked separately from releasing the HW Lock Mgr. 1576 * This flag is set if the client wishes to release the object. 1577 */ 1578 uint8_t should_release; 1579 /** 1580 * Explicit padding to 4 byte boundary. 1581 */ 1582 uint8_t pad; 1583 }; 1584 1585 /** 1586 * Definition of a DMUB_CMD__HW_LOCK command. 1587 * Command is used by driver and FW. 1588 */ 1589 struct dmub_rb_cmd_lock_hw { 1590 /** 1591 * Command header. 1592 */ 1593 struct dmub_cmd_header header; 1594 /** 1595 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1596 */ 1597 struct dmub_cmd_lock_hw_data lock_hw_data; 1598 }; 1599 1600 /** 1601 * ABM command sub-types. 1602 */ 1603 enum dmub_cmd_abm_type { 1604 /** 1605 * Initialize parameters for ABM algorithm. 1606 * Data is passed through an indirect buffer. 1607 */ 1608 DMUB_CMD__ABM_INIT_CONFIG = 0, 1609 /** 1610 * Set OTG and panel HW instance. 1611 */ 1612 DMUB_CMD__ABM_SET_PIPE = 1, 1613 /** 1614 * Set user requested backklight level. 1615 */ 1616 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1617 /** 1618 * Set ABM operating/aggression level. 1619 */ 1620 DMUB_CMD__ABM_SET_LEVEL = 3, 1621 /** 1622 * Set ambient light level. 1623 */ 1624 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1625 /** 1626 * Enable/disable fractional duty cycle for backlight PWM. 1627 */ 1628 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1629 }; 1630 1631 /** 1632 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1633 * Requirements: 1634 * - Padded explicitly to 32-bit boundary. 1635 * - Must ensure this structure matches the one on driver-side, 1636 * otherwise it won't be aligned. 1637 */ 1638 struct abm_config_table { 1639 /** 1640 * Gamma curve thresholds, used for crgb conversion. 1641 */ 1642 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1643 /** 1644 * Gamma curve offsets, used for crgb conversion. 1645 */ 1646 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1647 /** 1648 * Gamma curve slopes, used for crgb conversion. 1649 */ 1650 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1651 /** 1652 * Custom backlight curve thresholds. 1653 */ 1654 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1655 /** 1656 * Custom backlight curve offsets. 1657 */ 1658 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1659 /** 1660 * Ambient light thresholds. 1661 */ 1662 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1663 /** 1664 * Minimum programmable backlight. 1665 */ 1666 uint16_t min_abm_backlight; // 122B 1667 /** 1668 * Minimum reduction values. 1669 */ 1670 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1671 /** 1672 * Maximum reduction values. 1673 */ 1674 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1675 /** 1676 * Bright positive gain. 1677 */ 1678 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1679 /** 1680 * Dark negative gain. 1681 */ 1682 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1683 /** 1684 * Hybrid factor. 1685 */ 1686 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1687 /** 1688 * Contrast factor. 1689 */ 1690 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1691 /** 1692 * Deviation gain. 1693 */ 1694 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1695 /** 1696 * Minimum knee. 1697 */ 1698 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1699 /** 1700 * Maximum knee. 1701 */ 1702 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1703 /** 1704 * Unused. 1705 */ 1706 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1707 /** 1708 * Explicit padding to 4 byte boundary. 1709 */ 1710 uint8_t pad3[3]; // 229B 1711 /** 1712 * Backlight ramp reduction. 1713 */ 1714 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1715 /** 1716 * Backlight ramp start. 1717 */ 1718 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1719 }; 1720 1721 /** 1722 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1723 */ 1724 struct dmub_cmd_abm_set_pipe_data { 1725 /** 1726 * OTG HW instance. 1727 */ 1728 uint8_t otg_inst; 1729 1730 /** 1731 * Panel Control HW instance. 1732 */ 1733 uint8_t panel_inst; 1734 1735 /** 1736 * Controls how ABM will interpret a set pipe or set level command. 1737 */ 1738 uint8_t set_pipe_option; 1739 1740 /** 1741 * Unused. 1742 * TODO: Remove. 1743 */ 1744 uint8_t ramping_boundary; 1745 }; 1746 1747 /** 1748 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1749 */ 1750 struct dmub_rb_cmd_abm_set_pipe { 1751 /** 1752 * Command header. 1753 */ 1754 struct dmub_cmd_header header; 1755 1756 /** 1757 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1758 */ 1759 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1760 }; 1761 1762 /** 1763 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1764 */ 1765 struct dmub_cmd_abm_set_backlight_data { 1766 /** 1767 * Number of frames to ramp to backlight user level. 1768 */ 1769 uint32_t frame_ramp; 1770 1771 /** 1772 * Requested backlight level from user. 1773 */ 1774 uint32_t backlight_user_level; 1775 1776 /** 1777 * ABM control version. 1778 */ 1779 uint8_t version; 1780 1781 /** 1782 * Panel Control HW instance mask. 1783 * Bit 0 is Panel Control HW instance 0. 1784 * Bit 1 is Panel Control HW instance 1. 1785 */ 1786 uint8_t panel_mask; 1787 1788 /** 1789 * Explicit padding to 4 byte boundary. 1790 */ 1791 uint8_t pad[2]; 1792 }; 1793 1794 /** 1795 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1796 */ 1797 struct dmub_rb_cmd_abm_set_backlight { 1798 /** 1799 * Command header. 1800 */ 1801 struct dmub_cmd_header header; 1802 1803 /** 1804 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1805 */ 1806 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1807 }; 1808 1809 /** 1810 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1811 */ 1812 struct dmub_cmd_abm_set_level_data { 1813 /** 1814 * Set current ABM operating/aggression level. 1815 */ 1816 uint32_t level; 1817 1818 /** 1819 * ABM control version. 1820 */ 1821 uint8_t version; 1822 1823 /** 1824 * Panel Control HW instance mask. 1825 * Bit 0 is Panel Control HW instance 0. 1826 * Bit 1 is Panel Control HW instance 1. 1827 */ 1828 uint8_t panel_mask; 1829 1830 /** 1831 * Explicit padding to 4 byte boundary. 1832 */ 1833 uint8_t pad[2]; 1834 }; 1835 1836 /** 1837 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1838 */ 1839 struct dmub_rb_cmd_abm_set_level { 1840 /** 1841 * Command header. 1842 */ 1843 struct dmub_cmd_header header; 1844 1845 /** 1846 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1847 */ 1848 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1849 }; 1850 1851 /** 1852 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1853 */ 1854 struct dmub_cmd_abm_set_ambient_level_data { 1855 /** 1856 * Ambient light sensor reading from OS. 1857 */ 1858 uint32_t ambient_lux; 1859 1860 /** 1861 * ABM control version. 1862 */ 1863 uint8_t version; 1864 1865 /** 1866 * Panel Control HW instance mask. 1867 * Bit 0 is Panel Control HW instance 0. 1868 * Bit 1 is Panel Control HW instance 1. 1869 */ 1870 uint8_t panel_mask; 1871 1872 /** 1873 * Explicit padding to 4 byte boundary. 1874 */ 1875 uint8_t pad[2]; 1876 }; 1877 1878 /** 1879 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1880 */ 1881 struct dmub_rb_cmd_abm_set_ambient_level { 1882 /** 1883 * Command header. 1884 */ 1885 struct dmub_cmd_header header; 1886 1887 /** 1888 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1889 */ 1890 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1891 }; 1892 1893 /** 1894 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1895 */ 1896 struct dmub_cmd_abm_set_pwm_frac_data { 1897 /** 1898 * Enable/disable fractional duty cycle for backlight PWM. 1899 * TODO: Convert to uint8_t. 1900 */ 1901 uint32_t fractional_pwm; 1902 1903 /** 1904 * ABM control version. 1905 */ 1906 uint8_t version; 1907 1908 /** 1909 * Panel Control HW instance mask. 1910 * Bit 0 is Panel Control HW instance 0. 1911 * Bit 1 is Panel Control HW instance 1. 1912 */ 1913 uint8_t panel_mask; 1914 1915 /** 1916 * Explicit padding to 4 byte boundary. 1917 */ 1918 uint8_t pad[2]; 1919 }; 1920 1921 /** 1922 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 1923 */ 1924 struct dmub_rb_cmd_abm_set_pwm_frac { 1925 /** 1926 * Command header. 1927 */ 1928 struct dmub_cmd_header header; 1929 1930 /** 1931 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1932 */ 1933 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 1934 }; 1935 1936 /** 1937 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1938 */ 1939 struct dmub_cmd_abm_init_config_data { 1940 /** 1941 * Location of indirect buffer used to pass init data to ABM. 1942 */ 1943 union dmub_addr src; 1944 1945 /** 1946 * Indirect buffer length. 1947 */ 1948 uint16_t bytes; 1949 1950 1951 /** 1952 * ABM control version. 1953 */ 1954 uint8_t version; 1955 1956 /** 1957 * Panel Control HW instance mask. 1958 * Bit 0 is Panel Control HW instance 0. 1959 * Bit 1 is Panel Control HW instance 1. 1960 */ 1961 uint8_t panel_mask; 1962 1963 /** 1964 * Explicit padding to 4 byte boundary. 1965 */ 1966 uint8_t pad[2]; 1967 }; 1968 1969 /** 1970 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 1971 */ 1972 struct dmub_rb_cmd_abm_init_config { 1973 /** 1974 * Command header. 1975 */ 1976 struct dmub_cmd_header header; 1977 1978 /** 1979 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1980 */ 1981 struct dmub_cmd_abm_init_config_data abm_init_config_data; 1982 }; 1983 1984 /** 1985 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1986 */ 1987 struct dmub_cmd_query_feature_caps_data { 1988 /** 1989 * DMUB feature capabilities. 1990 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 1991 */ 1992 struct dmub_feature_caps feature_caps; 1993 }; 1994 1995 /** 1996 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 1997 */ 1998 struct dmub_rb_cmd_query_feature_caps { 1999 /** 2000 * Command header. 2001 */ 2002 struct dmub_cmd_header header; 2003 /** 2004 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2005 */ 2006 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2007 }; 2008 2009 struct dmub_optc_state { 2010 uint32_t v_total_max; 2011 uint32_t v_total_min; 2012 uint32_t v_total_mid; 2013 uint32_t v_total_mid_frame_num; 2014 uint32_t tg_inst; 2015 uint32_t enable_manual_trigger; 2016 uint32_t clear_force_vsync; 2017 }; 2018 2019 struct dmub_rb_cmd_drr_update { 2020 struct dmub_cmd_header header; 2021 struct dmub_optc_state dmub_optc_state_req; 2022 }; 2023 2024 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 2025 /** 2026 * enum dmub_cmd_panel_cntl_type - Panel control command. 2027 */ 2028 enum dmub_cmd_panel_cntl_type { 2029 /** 2030 * Initializes embedded panel hardware blocks. 2031 */ 2032 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2033 /** 2034 * Queries backlight info for the embedded panel. 2035 */ 2036 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2037 }; 2038 2039 /** 2040 * struct dmub_cmd_panel_cntl_data - Panel control data. 2041 */ 2042 struct dmub_cmd_panel_cntl_data { 2043 uint32_t inst; /**< panel instance */ 2044 uint32_t current_backlight; /* in/out */ 2045 uint32_t bl_pwm_cntl; /* in/out */ 2046 uint32_t bl_pwm_period_cntl; /* in/out */ 2047 uint32_t bl_pwm_ref_div1; /* in/out */ 2048 uint8_t is_backlight_on : 1; /* in/out */ 2049 uint8_t is_powered_on : 1; /* in/out */ 2050 }; 2051 2052 /** 2053 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2054 */ 2055 struct dmub_rb_cmd_panel_cntl { 2056 struct dmub_cmd_header header; /**< header */ 2057 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2058 }; 2059 #endif 2060 2061 /** 2062 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2063 */ 2064 struct dmub_cmd_lvtma_control_data { 2065 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2066 uint8_t reserved_0[3]; /**< For future use */ 2067 uint8_t panel_inst; /**< LVTMA control instance */ 2068 uint8_t reserved_1[3]; /**< For future use */ 2069 }; 2070 2071 /** 2072 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2073 */ 2074 struct dmub_rb_cmd_lvtma_control { 2075 /** 2076 * Command header. 2077 */ 2078 struct dmub_cmd_header header; 2079 /** 2080 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2081 */ 2082 struct dmub_cmd_lvtma_control_data data; 2083 }; 2084 2085 /** 2086 * union dmub_rb_cmd - DMUB inbox command. 2087 */ 2088 union dmub_rb_cmd { 2089 struct dmub_rb_cmd_lock_hw lock_hw; 2090 /** 2091 * Elements shared with all commands. 2092 */ 2093 struct dmub_rb_cmd_common cmd_common; 2094 /** 2095 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2096 */ 2097 struct dmub_rb_cmd_read_modify_write read_modify_write; 2098 /** 2099 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2100 */ 2101 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2102 /** 2103 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2104 */ 2105 struct dmub_rb_cmd_burst_write burst_write; 2106 /** 2107 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2108 */ 2109 struct dmub_rb_cmd_reg_wait reg_wait; 2110 /** 2111 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2112 */ 2113 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2114 /** 2115 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2116 */ 2117 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2118 /** 2119 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2120 */ 2121 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2122 /** 2123 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2124 */ 2125 struct dmub_rb_cmd_dpphy_init dpphy_init; 2126 /** 2127 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2128 */ 2129 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2130 /** 2131 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2132 */ 2133 struct dmub_rb_cmd_psr_set_version psr_set_version; 2134 /** 2135 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2136 */ 2137 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2138 /** 2139 * Definition of a DMUB_CMD__PSR_ENABLE command. 2140 */ 2141 struct dmub_rb_cmd_psr_enable psr_enable; 2142 /** 2143 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2144 */ 2145 struct dmub_rb_cmd_psr_set_level psr_set_level; 2146 /** 2147 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2148 */ 2149 struct dmub_rb_cmd_psr_force_static psr_force_static; 2150 /** 2151 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2152 */ 2153 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2154 /** 2155 * Definition of a DMUB_CMD__MALL command. 2156 */ 2157 struct dmub_rb_cmd_mall mall; 2158 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 2159 /** 2160 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2161 */ 2162 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2163 2164 /** 2165 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2166 */ 2167 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2168 2169 /** 2170 * Definition of DMUB_CMD__PANEL_CNTL commands. 2171 */ 2172 struct dmub_rb_cmd_panel_cntl panel_cntl; 2173 #endif 2174 /** 2175 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2176 */ 2177 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2178 2179 /** 2180 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2181 */ 2182 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2183 2184 /** 2185 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2186 */ 2187 struct dmub_rb_cmd_abm_set_level abm_set_level; 2188 2189 /** 2190 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2191 */ 2192 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2193 2194 /** 2195 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2196 */ 2197 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2198 2199 /** 2200 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2201 */ 2202 struct dmub_rb_cmd_abm_init_config abm_init_config; 2203 2204 /** 2205 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2206 */ 2207 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2208 2209 /** 2210 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2211 */ 2212 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2213 2214 /** 2215 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2216 */ 2217 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2218 struct dmub_rb_cmd_drr_update drr_update; 2219 /** 2220 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2221 */ 2222 struct dmub_rb_cmd_lvtma_control lvtma_control; 2223 }; 2224 2225 /** 2226 * union dmub_rb_out_cmd - Outbox command 2227 */ 2228 union dmub_rb_out_cmd { 2229 /** 2230 * Parameters common to every command. 2231 */ 2232 struct dmub_rb_cmd_common cmd_common; 2233 /** 2234 * AUX reply command. 2235 */ 2236 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2237 /** 2238 * HPD notify command. 2239 */ 2240 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2241 }; 2242 #pragma pack(pop) 2243 2244 2245 //============================================================================== 2246 //</DMUB_CMD>=================================================================== 2247 //============================================================================== 2248 //< DMUB_RB>==================================================================== 2249 //============================================================================== 2250 2251 #if defined(__cplusplus) 2252 extern "C" { 2253 #endif 2254 2255 /** 2256 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2257 */ 2258 struct dmub_rb_init_params { 2259 void *ctx; /**< Caller provided context pointer */ 2260 void *base_address; /**< CPU base address for ring's data */ 2261 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2262 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2263 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2264 }; 2265 2266 /** 2267 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2268 */ 2269 struct dmub_rb { 2270 void *base_address; /**< CPU address for the ring's data */ 2271 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2272 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2273 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2274 2275 void *ctx; /**< Caller provided context pointer */ 2276 void *dmub; /**< Pointer to the DMUB interface */ 2277 }; 2278 2279 /** 2280 * @brief Checks if the ringbuffer is empty. 2281 * 2282 * @param rb DMUB Ringbuffer 2283 * @return true if empty 2284 * @return false otherwise 2285 */ 2286 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2287 { 2288 return (rb->wrpt == rb->rptr); 2289 } 2290 2291 /** 2292 * @brief Checks if the ringbuffer is full 2293 * 2294 * @param rb DMUB Ringbuffer 2295 * @return true if full 2296 * @return false otherwise 2297 */ 2298 static inline bool dmub_rb_full(struct dmub_rb *rb) 2299 { 2300 uint32_t data_count; 2301 2302 if (rb->wrpt >= rb->rptr) 2303 data_count = rb->wrpt - rb->rptr; 2304 else 2305 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2306 2307 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2308 } 2309 2310 /** 2311 * @brief Pushes a command into the ringbuffer 2312 * 2313 * @param rb DMUB ringbuffer 2314 * @param cmd The command to push 2315 * @return true if the ringbuffer was not full 2316 * @return false otherwise 2317 */ 2318 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2319 const union dmub_rb_cmd *cmd) 2320 { 2321 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2322 const uint64_t *src = (const uint64_t *)cmd; 2323 uint8_t i; 2324 2325 if (dmub_rb_full(rb)) 2326 return false; 2327 2328 // copying data 2329 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2330 *dst++ = *src++; 2331 2332 rb->wrpt += DMUB_RB_CMD_SIZE; 2333 2334 if (rb->wrpt >= rb->capacity) 2335 rb->wrpt %= rb->capacity; 2336 2337 return true; 2338 } 2339 2340 /** 2341 * @brief Pushes a command into the DMUB outbox ringbuffer 2342 * 2343 * @param rb DMUB outbox ringbuffer 2344 * @param cmd Outbox command 2345 * @return true if not full 2346 * @return false otherwise 2347 */ 2348 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2349 const union dmub_rb_out_cmd *cmd) 2350 { 2351 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2352 const uint8_t *src = (uint8_t *)cmd; 2353 2354 if (dmub_rb_full(rb)) 2355 return false; 2356 2357 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2358 2359 rb->wrpt += DMUB_RB_CMD_SIZE; 2360 2361 if (rb->wrpt >= rb->capacity) 2362 rb->wrpt %= rb->capacity; 2363 2364 return true; 2365 } 2366 2367 /** 2368 * @brief Returns the next unprocessed command in the ringbuffer. 2369 * 2370 * @param rb DMUB ringbuffer 2371 * @param cmd The command to return 2372 * @return true if not empty 2373 * @return false otherwise 2374 */ 2375 static inline bool dmub_rb_front(struct dmub_rb *rb, 2376 union dmub_rb_cmd **cmd) 2377 { 2378 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2379 2380 if (dmub_rb_empty(rb)) 2381 return false; 2382 2383 *cmd = (union dmub_rb_cmd *)rb_cmd; 2384 2385 return true; 2386 } 2387 2388 /** 2389 * @brief Determines the next ringbuffer offset. 2390 * 2391 * @param rb DMUB inbox ringbuffer 2392 * @param num_cmds Number of commands 2393 * @param next_rptr The next offset in the ringbuffer 2394 */ 2395 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2396 uint32_t num_cmds, 2397 uint32_t *next_rptr) 2398 { 2399 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2400 2401 if (*next_rptr >= rb->capacity) 2402 *next_rptr %= rb->capacity; 2403 } 2404 2405 /** 2406 * @brief Returns a pointer to a command in the inbox. 2407 * 2408 * @param rb DMUB inbox ringbuffer 2409 * @param cmd The inbox command to return 2410 * @param rptr The ringbuffer offset 2411 * @return true if not empty 2412 * @return false otherwise 2413 */ 2414 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2415 union dmub_rb_cmd **cmd, 2416 uint32_t rptr) 2417 { 2418 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2419 2420 if (dmub_rb_empty(rb)) 2421 return false; 2422 2423 *cmd = (union dmub_rb_cmd *)rb_cmd; 2424 2425 return true; 2426 } 2427 2428 /** 2429 * @brief Returns the next unprocessed command in the outbox. 2430 * 2431 * @param rb DMUB outbox ringbuffer 2432 * @param cmd The outbox command to return 2433 * @return true if not empty 2434 * @return false otherwise 2435 */ 2436 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2437 union dmub_rb_out_cmd *cmd) 2438 { 2439 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2440 uint64_t *dst = (uint64_t *)cmd; 2441 uint8_t i; 2442 2443 if (dmub_rb_empty(rb)) 2444 return false; 2445 2446 // copying data 2447 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2448 *dst++ = *src++; 2449 2450 return true; 2451 } 2452 2453 /** 2454 * @brief Removes the front entry in the ringbuffer. 2455 * 2456 * @param rb DMUB ringbuffer 2457 * @return true if the command was removed 2458 * @return false if there were no commands 2459 */ 2460 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2461 { 2462 if (dmub_rb_empty(rb)) 2463 return false; 2464 2465 rb->rptr += DMUB_RB_CMD_SIZE; 2466 2467 if (rb->rptr >= rb->capacity) 2468 rb->rptr %= rb->capacity; 2469 2470 return true; 2471 } 2472 2473 /** 2474 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2475 * 2476 * Avoids a race condition where DMCUB accesses memory while 2477 * there are still writes in flight to framebuffer. 2478 * 2479 * @param rb DMUB ringbuffer 2480 */ 2481 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2482 { 2483 uint32_t rptr = rb->rptr; 2484 uint32_t wptr = rb->wrpt; 2485 2486 while (rptr != wptr) { 2487 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2488 uint8_t i; 2489 2490 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2491 *data++; 2492 2493 rptr += DMUB_RB_CMD_SIZE; 2494 if (rptr >= rb->capacity) 2495 rptr %= rb->capacity; 2496 } 2497 } 2498 2499 /** 2500 * @brief Initializes a DMCUB ringbuffer 2501 * 2502 * @param rb DMUB ringbuffer 2503 * @param init_params initial configuration for the ringbuffer 2504 */ 2505 static inline void dmub_rb_init(struct dmub_rb *rb, 2506 struct dmub_rb_init_params *init_params) 2507 { 2508 rb->base_address = init_params->base_address; 2509 rb->capacity = init_params->capacity; 2510 rb->rptr = init_params->read_ptr; 2511 rb->wrpt = init_params->write_ptr; 2512 } 2513 2514 /** 2515 * @brief Copies output data from in/out commands into the given command. 2516 * 2517 * @param rb DMUB ringbuffer 2518 * @param cmd Command to copy data into 2519 */ 2520 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2521 union dmub_rb_cmd *cmd) 2522 { 2523 // Copy rb entry back into command 2524 uint8_t *rd_ptr = (rb->rptr == 0) ? 2525 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2526 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2527 2528 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2529 } 2530 2531 #if defined(__cplusplus) 2532 } 2533 #endif 2534 2535 //============================================================================== 2536 //</DMUB_RB>==================================================================== 2537 //============================================================================== 2538 2539 #endif /* _DMUB_CMD_H_ */ 2540