1 /* 2 * Note: This header is the authoritative source for the DMUB firmware 3 * command interface. In the Linux kernel, it is maintained as an 4 * auto-generated copy from an AMD internal repository. 5 * 6 * This file follows Doxygen formatting for firmware standards and 7 * is NOT intended to be kernel-doc compliant. 8 */ 9 10 /* 11 * Copyright 2019 Advanced Micro Devices, Inc. 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 * 31 * Authors: AMD 32 * 33 */ 34 35 #ifndef DMUB_CMD_H 36 #define DMUB_CMD_H 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 //<DMUB_TYPES>================================================================== 46 /* Basic type definitions. */ 47 48 #ifdef __forceinline 49 #undef __forceinline 50 #endif 51 #define __forceinline inline 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled gradually 55 * by slowly reversing all backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 58 59 /** 60 * Flag from driver to indicate that ABM should be disabled immediately 61 * and undo all backlight programming and pixel compensation. 62 */ 63 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 64 65 /** 66 * Flag from driver to indicate that ABM should be disabled immediately 67 * and keep the current backlight programming and pixel compensation. 68 */ 69 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 70 71 /** 72 * Flag from driver to set the current ABM pipe index or ABM operating level. 73 */ 74 #define SET_ABM_PIPE_NORMAL 1 75 76 /** 77 * Number of ambient light levels in ABM algorithm. 78 */ 79 #define NUM_AMBI_LEVEL 5 80 81 /** 82 * Number of operating/aggression levels in ABM algorithm. 83 */ 84 #define NUM_AGGR_LEVEL 4 85 86 /** 87 * Number of segments in the gamma curve. 88 */ 89 #define NUM_POWER_FN_SEGS 8 90 91 /** 92 * Number of segments in the backlight curve. 93 */ 94 #define NUM_BL_CURVE_SEGS 16 95 96 /** 97 * Maximum number of segments in ABM ACE curve. 98 */ 99 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 100 101 /** 102 * Maximum number of bins in ABM histogram. 103 */ 104 #define ABM_MAX_NUM_OF_HG_BINS 64 105 106 /** 107 * Flag from driver to indicate that CACP should be disabled gradually 108 * by slowly reversing all programming and pixel compensation. 109 */ 110 #define SET_CACP_PIPE_GRADUALLY_DISABLE 0 111 112 /** 113 * Flag from driver to indicate that CACP should be disabled immediately 114 * and undo all programming and pixel compensation. 115 */ 116 #define SET_CACP_PIPE_IMMEDIATELY_DISABLE 255 117 118 /** 119 * Flag from driver to indicate that CACP should be disabled immediately 120 * and keep the current programming and pixel compensation. 121 */ 122 #define SET_CACP_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 123 124 /** 125 * Flag from driver to indicate that CACP should be disabled immediately 126 * on the next abm vertical interrupt 127 */ 128 #define SET_CACP_PIPE_IMMEDIATE_ON_NEXT_DISABLE 253 129 130 /** 131 * Flag from driver to set the current CACP pipe index or CACP operating level. 132 */ 133 #define SET_CACP_PIPE_NORMAL 1 134 135 /* Maximum number of SubVP streams */ 136 #define DMUB_MAX_SUBVP_STREAMS 2 137 138 /* Define max FPO streams as 4 for now. Current implementation today 139 * only supports 1, but could be more in the future. Reduce array 140 * size to ensure the command size remains less than 64 bytes if 141 * adding new fields. 142 */ 143 #define DMUB_MAX_FPO_STREAMS 4 144 145 /* Define to ensure that the "common" members always appear in the same 146 * order in different structs for back compat purposes 147 */ 148 #define COMMON_STREAM_STATIC_SUB_STATE \ 149 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 150 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 151 struct dmub_fams2_cmd_drr_stream_static_state drr; 152 153 /* Maximum number of streams on any ASIC. */ 154 #define DMUB_MAX_STREAMS 6 155 156 /* Maximum number of planes on any ASIC. */ 157 #define DMUB_MAX_PLANES 6 158 159 /* Maximum number of phantom planes on any ASIC */ 160 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 161 162 /* Trace buffer offset for entry */ 163 #define TRACE_BUFFER_ENTRY_OFFSET 16 164 165 /** 166 * Maximum number of dirty rects supported by FW. 167 */ 168 #define DMUB_MAX_DIRTY_RECTS 3 169 170 /** 171 * 172 * PSR control version legacy 173 */ 174 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 175 /** 176 * PSR control version with multi edp support 177 */ 178 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 179 180 /** 181 * 182 * dirty rect cmd version legacy 183 */ 184 #define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0 185 /** 186 * dirty rect cmd version with multi edp support 187 */ 188 #define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1 189 /** 190 * dirty rect cmd version with external monitor support 191 */ 192 #define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2 193 194 /** 195 * 196 * Cursor update cmd version legacy 197 */ 198 #define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0 199 /** 200 * Cursor update cmd version with multi edp support 201 */ 202 #define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1 203 /** 204 * Cursor update cmd version with external monitor support 205 */ 206 #define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2 207 208 /** 209 * ABM control version legacy 210 */ 211 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 212 213 /** 214 * ABM control version with multi edp support 215 */ 216 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 217 218 /** 219 * CACP control version legacy 220 */ 221 #define DMUB_CMD_CACP_CONTROL_VERSION_UNKNOWN 0x0 222 223 /** 224 * CACP control version with multi edp support 225 */ 226 #define DMUB_CMD_CACP_CONTROL_VERSION_1 0x1 227 228 /** 229 * CACP control mode with dynamic switch between v1 and v2 230 */ 231 #define DMUB_CMD_CACP_CONTROL_MODE_0 0x0 232 233 /** 234 * CACP control version with forced configure to v1 on new ABM HW 235 */ 236 #define DMUB_CMD_CACP_CONTROL_MODE_1 0x1 237 238 /** 239 * Physical framebuffer address location, 64-bit. 240 */ 241 #ifndef PHYSICAL_ADDRESS_LOC 242 #define PHYSICAL_ADDRESS_LOC union large_integer 243 #endif 244 245 /** 246 * OS/FW agnostic memcpy 247 */ 248 #ifndef dmub_memcpy 249 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 250 #endif 251 252 /** 253 * OS/FW agnostic memset 254 */ 255 #ifndef dmub_memset 256 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 257 #endif 258 259 /** 260 * OS/FW agnostic memcmp 261 */ 262 #ifndef dmub_memcmp 263 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 264 #endif 265 266 /** 267 * OS/FW agnostic udelay 268 */ 269 #ifndef dmub_udelay 270 #define dmub_udelay(microseconds) udelay(microseconds) 271 #endif 272 273 #pragma pack(push, 1) 274 #define ABM_NUM_OF_ACE_SEGMENTS 5 275 276 /** 277 * Debug FW state offset 278 */ 279 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 280 281 union abm_flags { 282 struct { 283 /** 284 * @abm_enabled: Indicates if ABM is enabled. 285 */ 286 unsigned int abm_enabled : 1; 287 288 /** 289 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 290 */ 291 unsigned int disable_abm_requested : 1; 292 293 /** 294 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 295 */ 296 unsigned int disable_abm_immediately : 1; 297 298 /** 299 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 300 * to be disabled immediately and keep gain. 301 */ 302 unsigned int disable_abm_immediate_keep_gain : 1; 303 304 /** 305 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 306 */ 307 unsigned int fractional_pwm : 1; 308 309 /** 310 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 311 * of user backlight level. 312 */ 313 unsigned int abm_gradual_bl_change : 1; 314 315 /** 316 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 317 */ 318 unsigned int abm_new_frame : 1; 319 320 /** 321 * @vb_scaling_enabled: Indicates variBright Scaling Enable 322 */ 323 unsigned int vb_scaling_enabled : 1; 324 } bitfields; 325 326 unsigned int u32All; 327 }; 328 329 struct abm_save_restore { 330 /** 331 * @flags: Misc. ABM flags. 332 */ 333 union abm_flags flags; 334 335 /** 336 * @pause: true: pause ABM and get state 337 * false: unpause ABM after setting state 338 */ 339 uint32_t pause; 340 341 /** 342 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 343 */ 344 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 345 346 /** 347 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 348 */ 349 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 350 351 /** 352 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 353 */ 354 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 355 356 357 /** 358 * @knee_threshold: Current x-position of ACE knee (u0.16). 359 */ 360 uint32_t knee_threshold; 361 /** 362 * @current_gain: Current backlight reduction (u16.16). 363 */ 364 uint32_t current_gain; 365 /** 366 * @curr_bl_level: Current actual backlight level converging to target backlight level. 367 */ 368 uint16_t curr_bl_level; 369 370 /** 371 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 372 */ 373 uint16_t curr_user_bl_level; 374 375 }; 376 377 /** 378 * union dmub_addr - DMUB physical/virtual 64-bit address. 379 */ 380 union dmub_addr { 381 struct { 382 uint32_t low_part; /**< Lower 32 bits */ 383 uint32_t high_part; /**< Upper 32 bits */ 384 } u; /*<< Low/high bit access */ 385 uint64_t quad_part; /*<< 64 bit address */ 386 }; 387 388 /* Flattened structure containing SOC BB parameters stored in the VBIOS 389 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 390 * This also prevents alighment issues when new parameters are added to the SoC BB. 391 * The following parameters should be added since these values can't be obtained elsewhere: 392 * -dml2_soc_power_management_parameters 393 * -dml2_soc_vmin_clock_limits 394 */ 395 struct dmub_soc_bb_params { 396 uint32_t dram_clk_change_blackout_ns; 397 uint32_t dram_clk_change_read_only_ns; 398 uint32_t dram_clk_change_write_only_ns; 399 uint32_t fclk_change_blackout_ns; 400 uint32_t g7_ppt_blackout_ns; 401 uint32_t stutter_enter_plus_exit_latency_ns; 402 uint32_t stutter_exit_latency_ns; 403 uint32_t z8_stutter_enter_plus_exit_latency_ns; 404 uint32_t z8_stutter_exit_latency_ns; 405 uint32_t z8_min_idle_time_ns; 406 uint32_t type_b_dram_clk_change_blackout_ns; 407 uint32_t type_b_ppt_blackout_ns; 408 uint32_t vmin_limit_dispclk_khz; 409 uint32_t vmin_limit_dcfclk_khz; 410 uint32_t g7_temperature_read_blackout_ns; 411 }; 412 #pragma pack(pop) 413 414 /** 415 * Dirty rect definition. 416 */ 417 struct dmub_rect { 418 /** 419 * Dirty rect x offset. 420 */ 421 uint32_t x; 422 423 /** 424 * Dirty rect y offset. 425 */ 426 uint32_t y; 427 428 /** 429 * Dirty rect width. 430 */ 431 uint32_t width; 432 433 /** 434 * Dirty rect height. 435 */ 436 uint32_t height; 437 }; 438 439 /** 440 * Flags that can be set by driver to change some PSR behaviour. 441 */ 442 union dmub_psr_debug_flags { 443 /** 444 * Debug flags. 445 */ 446 struct { 447 /** 448 * Enable visual confirm in FW. 449 */ 450 uint32_t visual_confirm : 1; 451 452 /** 453 * Force all selective updates to bw full frame updates. 454 */ 455 uint32_t force_full_frame_update : 1; 456 457 /** 458 * Use HW Lock Mgr object to do HW locking in FW. 459 */ 460 uint32_t use_hw_lock_mgr : 1; 461 462 /** 463 * Use TPS3 signal when restore main link. 464 */ 465 uint32_t force_wakeup_by_tps3 : 1; 466 467 /** 468 * Back to back flip, therefore cannot power down PHY 469 */ 470 uint32_t back_to_back_flip : 1; 471 472 /** 473 * Enable visual confirm for IPS 474 */ 475 uint32_t enable_ips_visual_confirm : 1; 476 } bitfields; 477 478 /** 479 * Union for debug flags. 480 */ 481 uint32_t u32All; 482 }; 483 484 /** 485 * Flags that can be set by driver to change some Replay behaviour. 486 */ 487 union replay_debug_flags { 488 struct { 489 /** 490 * 0x1 (bit 0) 491 * Enable visual confirm in FW. 492 */ 493 uint32_t visual_confirm : 1; 494 495 /** 496 * 0x2 (bit 1) 497 * @skip_crc: Set if need to skip CRC. 498 */ 499 uint32_t skip_crc : 1; 500 501 /** 502 * 0x4 (bit 2) 503 * @force_link_power_on: Force disable ALPM control 504 */ 505 uint32_t force_link_power_on : 1; 506 507 /** 508 * 0x8 (bit 3) 509 * @force_phy_power_on: Force phy power on 510 */ 511 uint32_t force_phy_power_on : 1; 512 513 /** 514 * 0x10 (bit 4) 515 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 516 */ 517 uint32_t timing_resync_disabled : 1; 518 519 /** 520 * 0x20 (bit 5) 521 * @skip_crtc_disabled: CRTC disable skipped 522 */ 523 uint32_t skip_crtc_disabled : 1; 524 525 /** 526 * 0x40 (bit 6) 527 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 528 */ 529 uint32_t force_defer_one_frame_update : 1; 530 531 /** 532 * 0x80 (bit 7) 533 * @disable_delay_alpm_on: Force disable delay alpm on 534 */ 535 uint32_t disable_delay_alpm_on : 1; 536 537 /** 538 * 0x100 (bit 8) 539 * @disable_desync_error_check: Force disable desync error check 540 */ 541 uint32_t disable_desync_error_check : 1; 542 543 /** 544 * 0x200 (bit 9) 545 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 546 */ 547 uint32_t force_self_update_when_abm_non_steady : 1; 548 549 /** 550 * 0x400 (bit 10) 551 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 552 * If we enter IPS2, the Visual confirm bar will change to yellow 553 */ 554 uint32_t enable_ips_visual_confirm : 1; 555 556 /** 557 * 0x800 (bit 11) 558 * @enable_ips_residency_profiling: Enable IPS residency profiling 559 */ 560 uint32_t enable_ips_residency_profiling : 1; 561 562 /** 563 * 0x1000 (bit 12) 564 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 565 */ 566 uint32_t enable_coasting_vtotal_check : 1; 567 /** 568 * 0x2000 (bit 13) 569 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 570 */ 571 uint32_t enable_visual_confirm_debug : 1; 572 573 /** 574 * 0x4000 (bit 14) 575 * @debug_log_enabled: Debug Log Enabled 576 */ 577 uint32_t debug_log_enabled : 1; 578 579 /** 580 * 0x8000 (bit 15) 581 * @enable_sub_feature_visual_confirm: Enable Sub Feature Visual Confirm 582 */ 583 uint32_t enable_sub_feature_visual_confirm : 1; 584 585 uint32_t reserved : 16; 586 } bitfields; 587 588 uint32_t u32All; 589 }; 590 591 /** 592 * Flags record error state. 593 */ 594 union replay_visual_confirm_error_state_flags { 595 struct { 596 /** 597 * 0x1 (bit 0) - Desync Error flag. 598 */ 599 uint32_t desync_error : 1; 600 601 /** 602 * 0x2 (bit 1) - State Transition Error flag. 603 */ 604 uint32_t state_transition_error : 1; 605 606 /** 607 * 0x4 (bit 2) - Crc Error flag 608 */ 609 uint32_t crc_error : 1; 610 611 /** 612 * 0x8 (bit 3) - Reserved 613 */ 614 uint32_t reserved_3 : 1; 615 616 /** 617 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 618 * Added new debug flag to control DPCD. 619 */ 620 uint32_t incorrect_vtotal_in_static_screen : 1; 621 622 /** 623 * 0x20 (bit 5) - No doubled Refresh Rate. 624 */ 625 uint32_t no_double_rr : 1; 626 627 /** 628 * Reserved bit 6-7 629 */ 630 uint32_t reserved_6_7 : 2; 631 632 /** 633 * Reserved bit 9-31 634 */ 635 uint32_t reserved_9_31 : 24; 636 } bitfields; 637 638 uint32_t u32All; 639 }; 640 641 union replay_hw_flags { 642 struct { 643 /** 644 * @allow_alpm_fw_standby_mode: To indicate whether the 645 * ALPM FW standby mode is allowed 646 */ 647 uint32_t allow_alpm_fw_standby_mode : 1; 648 649 /* 650 * @dsc_enable_status: DSC enable status in driver 651 */ 652 uint32_t dsc_enable_status : 1; 653 654 /** 655 * @fec_enable_status: receive fec enable/disable status from driver 656 */ 657 uint32_t fec_enable_status : 1; 658 659 /* 660 * @smu_optimizations_en: SMU power optimization. 661 * Only when active display is Replay capable and display enters Replay. 662 * Trigger interrupt to SMU to powerup/down. 663 */ 664 uint32_t smu_optimizations_en : 1; 665 666 /** 667 * @phy_power_state: Indicates current phy power state 668 */ 669 uint32_t phy_power_state : 1; 670 671 /** 672 * @link_power_state: Indicates current link power state 673 */ 674 uint32_t link_power_state : 1; 675 /** 676 * Use TPS3 signal when restore main link. 677 */ 678 uint32_t force_wakeup_by_tps3 : 1; 679 /** 680 * @is_alpm_initialized: Indicates whether ALPM is initialized 681 */ 682 uint32_t is_alpm_initialized : 1; 683 684 /** 685 * @alpm_mode: Indicates ALPM mode selected 686 */ 687 uint32_t alpm_mode : 2; 688 } bitfields; 689 690 uint32_t u32All; 691 }; 692 693 /** 694 * Flags that can be set by driver to change some Panel Replay behaviour. 695 */ 696 union pr_debug_flags { 697 struct { 698 /** 699 * 0x1 (bit 0) 700 * Enable visual confirm in FW. 701 */ 702 uint32_t visual_confirm : 1; 703 704 /** 705 * 0x2 (bit 1) 706 * @skip_crc: Set if need to skip CRC. 707 */ 708 uint32_t skip_crc : 1; 709 710 /** 711 * 0x4 (bit 2) 712 * @force_link_power_on: Force disable ALPM control 713 */ 714 uint32_t force_link_power_on : 1; 715 716 /** 717 * 0x8 (bit 3) 718 * @force_phy_power_on: Force phy power on 719 */ 720 uint32_t force_phy_power_on : 1; 721 722 /** 723 * 0x10 (bit 4) 724 * @visual_confirm_rate_control: Enable Visual Confirm rate control detection 725 */ 726 uint32_t visual_confirm_rate_control : 1; 727 728 /** 729 * 0x20 (bit 5) 730 * @force_full_frame_update: Force all selective updates to be full frame updates 731 */ 732 uint32_t force_full_frame_update : 1; 733 734 /** 735 * 0x40 (bit 6) 736 * @force_dpg_on: Force DPG on 737 */ 738 uint32_t force_dpg_on : 1; 739 740 /** 741 * 0x80 (bit 7) 742 * @force_hubp_on: Force Hubp on 743 */ 744 uint32_t force_hubp_on : 1; 745 746 uint32_t reserved : 24; 747 } bitfields; 748 749 uint32_t u32All; 750 }; 751 752 union pr_hw_flags { 753 struct { 754 /** 755 * @allow_alpm_fw_standby_mode: To indicate whether the 756 * ALPM FW standby mode is allowed 757 */ 758 uint32_t allow_alpm_fw_standby_mode : 1; 759 760 /* 761 * @dsc_enable_status: DSC enable status in driver 762 */ 763 uint32_t dsc_enable_status : 1; 764 765 /** 766 * @fec_enable_status: receive fec enable/disable status from driver 767 */ 768 uint32_t fec_enable_status : 1; 769 /* 770 * @smu_optimizations_en: SMU power optimization. 771 * Only when active display is Replay capable and display enters Replay. 772 * Trigger interrupt to SMU to powerup/down. 773 */ 774 uint32_t smu_optimizations_en : 1; 775 /** 776 * @link_power_state: Indicates current link power state 777 */ 778 uint32_t link_power_state : 1; 779 /** 780 * Use TPS3 signal when restore main link. 781 */ 782 uint32_t force_wakeup_by_tps3 : 1; 783 /** 784 * @is_alpm_initialized: Indicates whether ALPM is initialized 785 */ 786 uint32_t is_alpm_initialized : 1; 787 /** 788 * @alpm_mode: Indicates ALPM mode selected 789 */ 790 uint32_t alpm_mode : 2; 791 uint32_t reserved : 23; 792 } bitfields; 793 794 uint32_t u32All; 795 }; 796 797 /** 798 * Definition of Panel Replay ML Activity Options 799 */ 800 enum pr_ml_activity_option { 801 OPTION_DEFAULT = 0x00, // VESA Option Default (1C) 802 OPTION_1A = 0x01, // VESA Option 1A 803 OPTION_1B = 0x02, // VESA Option 1B 804 OPTION_1C = 0x03, // VESA Option 1C 805 }; 806 807 union fw_assisted_mclk_switch_version { 808 struct { 809 uint8_t minor : 5; 810 uint8_t major : 3; 811 }; 812 uint8_t ver; 813 }; 814 815 /** 816 * DMUB feature capabilities. 817 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 818 */ 819 struct dmub_feature_caps { 820 /** 821 * Max PSR version supported by FW. 822 */ 823 uint8_t psr; 824 uint8_t fw_assisted_mclk_switch_ver; 825 uint8_t reserved[4]; 826 uint8_t subvp_psr_support; 827 uint8_t gecc_enable; 828 uint8_t replay_supported; 829 uint8_t replay_reserved[3]; 830 uint8_t abm_aux_backlight_support; 831 uint8_t lsdma_support_in_dmu; 832 }; 833 834 struct dmub_visual_confirm_color { 835 /** 836 * Maximum 10 bits color value 837 */ 838 uint16_t color_r_cr; 839 uint16_t color_g_y; 840 uint16_t color_b_cb; 841 uint16_t panel_inst; 842 }; 843 844 /** 845 * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data. 846 */ 847 struct dmub_cursor_offload_pipe_data_dcn30_v1 { 848 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 849 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 850 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 851 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 852 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 853 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 854 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 855 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 856 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 857 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 858 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 859 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 860 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 861 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 862 uint32_t reserved0[4]; 863 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 864 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 865 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 866 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 867 uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 868 uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 869 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16; 870 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16; 871 uint32_t reserved1[5]; 872 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 873 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 874 uint32_t reserved2[3]; 875 }; 876 877 /** 878 * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data. 879 */ 880 struct dmub_cursor_offload_pipe_data_dcn401_v1 { 881 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 882 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 883 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 884 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 885 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 886 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 887 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 888 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 889 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 890 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 891 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 892 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 893 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 894 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 895 uint32_t reserved0[4]; 896 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 897 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 898 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 899 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 900 uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 901 uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 902 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16; 903 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16; 904 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16; 905 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16; 906 uint32_t reserved1[4]; 907 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 908 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 909 uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1; 910 uint32_t reserved2[3]; 911 }; 912 913 /** 914 * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload. 915 */ 916 struct dmub_cursor_offload_pipe_data_v1 { 917 union { 918 struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */ 919 struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */ 920 uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */ 921 }; 922 }; 923 924 /** 925 * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data. 926 */ 927 struct dmub_cursor_offload_payload_data_v1 { 928 uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */ 929 uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */ 930 uint32_t pipe_mask; /**< Mask of pipes to update. */ 931 uint32_t reserved; /**< Reserved for future use. */ 932 struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */ 933 }; 934 935 /** 936 * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload. 937 */ 938 struct dmub_cursor_offload_stream_v1 { 939 struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */ 940 uint32_t write_idx; /**< The index of the last written payload. */ 941 }; 942 943 /** 944 * struct dmub_cursor_offload_v1 - Cursor offload feature state. 945 */ 946 struct dmub_cursor_offload_v1 { 947 struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */ 948 }; 949 950 //============================================================================== 951 //</DMUB_TYPES>================================================================= 952 //============================================================================== 953 //< DMUB_META>================================================================== 954 //============================================================================== 955 #pragma pack(push, 1) 956 957 /* Magic value for identifying dmub_fw_meta_info */ 958 #define DMUB_FW_META_MAGIC 0x444D5542 959 960 /* Offset from the end of the file to the dmub_fw_meta_info */ 961 #define DMUB_FW_META_OFFSET 0x24 962 963 /** 964 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 965 */ 966 union dmub_fw_meta_feature_bits { 967 struct { 968 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 969 uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ 970 uint32_t inbox0_lock_support: 1; /**< 1 supports inbox0 lock mechanism */ 971 uint32_t reserved : 29; 972 } bits; /**< status bits */ 973 uint32_t all; /**< 32-bit access to status bits */ 974 }; 975 976 /** 977 * struct dmub_fw_meta_info - metadata associated with fw binary 978 * 979 * NOTE: This should be considered a stable API. Fields should 980 * not be repurposed or reordered. New fields should be 981 * added instead to extend the structure. 982 * 983 * @magic_value: magic value identifying DMUB firmware meta info 984 * @fw_region_size: size of the firmware state region 985 * @trace_buffer_size: size of the tracebuffer region 986 * @fw_version: the firmware version information 987 * @dal_fw: 1 if the firmware is DAL 988 * @shared_state_size: size of the shared state region in bytes 989 * @shared_state_features: number of shared state features 990 */ 991 struct dmub_fw_meta_info { 992 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 993 uint32_t fw_region_size; /**< size of the firmware state region */ 994 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 995 uint32_t fw_version; /**< the firmware version information */ 996 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 997 uint8_t reserved[3]; /**< padding bits */ 998 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 999 uint16_t shared_state_features; /**< number of shared state features */ 1000 uint16_t reserved2; /**< padding bytes */ 1001 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 1002 }; 1003 1004 /** 1005 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 1006 */ 1007 union dmub_fw_meta { 1008 struct dmub_fw_meta_info info; /**< metadata info */ 1009 uint8_t reserved[64]; /**< padding bits */ 1010 }; 1011 1012 #pragma pack(pop) 1013 1014 //============================================================================== 1015 //< DMUB Trace Buffer>================================================================ 1016 //============================================================================== 1017 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 1018 /** 1019 * dmub_trace_code_t - firmware trace code, 32-bits 1020 */ 1021 typedef uint32_t dmub_trace_code_t; 1022 1023 /** 1024 * struct dmcub_trace_buf_entry - Firmware trace entry 1025 */ 1026 struct dmcub_trace_buf_entry { 1027 dmub_trace_code_t trace_code; /**< trace code for the event */ 1028 uint32_t tick_count; /**< the tick count at time of trace */ 1029 uint32_t param0; /**< trace defined parameter 0 */ 1030 uint32_t param1; /**< trace defined parameter 1 */ 1031 }; 1032 #endif 1033 1034 //============================================================================== 1035 //< DMUB_STATUS>================================================================ 1036 //============================================================================== 1037 1038 /** 1039 * DMCUB scratch registers can be used to determine firmware status. 1040 * Current scratch register usage is as follows: 1041 * 1042 * SCRATCH0: FW Boot Status register 1043 * SCRATCH5: LVTMA Status Register 1044 * SCRATCH15: FW Boot Options register 1045 */ 1046 1047 /** 1048 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 1049 */ 1050 union dmub_fw_boot_status { 1051 struct { 1052 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 1053 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 1054 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 1055 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 1056 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 1057 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 1058 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 1059 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 1060 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 1061 } bits; /**< status bits */ 1062 uint32_t all; /**< 32-bit access to status bits */ 1063 }; 1064 1065 /** 1066 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 1067 */ 1068 enum dmub_fw_boot_status_bit { 1069 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 1070 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 1071 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 1072 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 1073 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 1074 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 1075 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 1076 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 1077 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 1078 }; 1079 1080 /* Register bit definition for SCRATCH5 */ 1081 union dmub_lvtma_status { 1082 struct { 1083 uint32_t psp_ok : 1; 1084 uint32_t edp_on : 1; 1085 uint32_t reserved : 30; 1086 } bits; 1087 uint32_t all; 1088 }; 1089 1090 enum dmub_lvtma_status_bit { 1091 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 1092 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 1093 }; 1094 1095 enum dmub_ips_disable_type { 1096 DMUB_IPS_ENABLE = 0, 1097 DMUB_IPS_DISABLE_ALL = 1, 1098 DMUB_IPS_DISABLE_IPS1 = 2, 1099 DMUB_IPS_DISABLE_IPS2 = 3, 1100 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 1101 DMUB_IPS_DISABLE_DYNAMIC = 5, 1102 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 1103 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 1104 }; 1105 1106 enum dmub_ips_rcg_disable_type { 1107 DMUB_IPS_RCG_ENABLE = 0, 1108 DMUB_IPS0_RCG_DISABLE = 1, 1109 DMUB_IPS1_RCG_DISABLE = 2, 1110 DMUB_IPS_RCG_DISABLE = 3 1111 }; 1112 1113 enum dmub_ips_in_vpb_disable_type { 1114 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 1115 DMUB_IPS_VPB_DISABLE_ALL = 1, 1116 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 1117 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 1118 }; 1119 1120 #define DMUB_IPS1_ALLOW_MASK 0x00000001 1121 #define DMUB_IPS2_ALLOW_MASK 0x00000002 1122 #define DMUB_IPS1_COMMIT_MASK 0x00000004 1123 #define DMUB_IPS2_COMMIT_MASK 0x00000008 1124 1125 enum dmub_ips_comand_type { 1126 /** 1127 * Start/stop IPS residency measurements for a given IPS mode 1128 */ 1129 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 1130 /** 1131 * Query IPS residency information for a given IPS mode 1132 */ 1133 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 1134 }; 1135 1136 /** 1137 * enum dmub_cursor_offload_comand_type - Cursor offload subcommands. 1138 */ 1139 enum dmub_cursor_offload_comand_type { 1140 /** 1141 * Initializes the cursor offload feature. 1142 */ 1143 DMUB_CMD__CURSOR_OFFLOAD_INIT = 0, 1144 /** 1145 * Enables cursor offloading for a stream and updates the timing parameters. 1146 */ 1147 DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1, 1148 /** 1149 * Disables cursor offloading for a given stream. 1150 */ 1151 DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2, 1152 /** 1153 * Programs the latest data for a given stream. 1154 */ 1155 DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3, 1156 }; 1157 1158 /** 1159 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 1160 */ 1161 union dmub_fw_boot_options { 1162 struct { 1163 uint32_t pemu_env : 1; /**< 1 if PEMU */ 1164 uint32_t fpga_env : 1; /**< 1 if FPGA */ 1165 uint32_t optimized_init : 1; /**< 1 if optimized init */ 1166 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 1167 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 1168 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 1169 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 1170 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 1171 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 1172 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 1173 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 1174 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 1175 uint32_t power_optimization: 1; 1176 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 1177 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 1178 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 1179 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 1180 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 1181 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 1182 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 1183 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 1184 uint32_t ips_disable: 3; /* options to disable ips support*/ 1185 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 1186 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 1187 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 1188 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 1189 uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */ 1190 uint32_t bootcrc_en_at_preos: 1; /**< 1 to run the boot time crc during warm/cold boot*/ 1191 uint32_t bootcrc_en_at_S0i3: 1; /**< 1 to run the boot time crc during S0i3 boot*/ 1192 uint32_t bootcrc_boot_mode: 1; /**< 1 for S0i3 resume and 0 for Warm/cold boot*/ 1193 uint32_t reserved : 1; /**< reserved */ 1194 } bits; /**< boot bits */ 1195 uint32_t all; /**< 32-bit access to bits */ 1196 }; 1197 1198 enum dmub_fw_boot_options_bit { 1199 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 1200 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 1201 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 1202 }; 1203 1204 //============================================================================== 1205 //< DMUB_SHARED_STATE>========================================================== 1206 //============================================================================== 1207 1208 /** 1209 * Shared firmware state between driver and firmware for lockless communication 1210 * in situations where the inbox/outbox may be unavailable. 1211 * 1212 * Each structure *must* be at most 256-bytes in size. The layout allocation is 1213 * described below: 1214 * 1215 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 1216 */ 1217 1218 /** 1219 * enum dmub_shared_state_feature_id - List of shared state features. 1220 */ 1221 enum dmub_shared_state_feature_id { 1222 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 1223 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 1224 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 1225 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 1226 DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4, 1227 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 1228 }; 1229 1230 /** 1231 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 1232 */ 1233 union dmub_shared_state_ips_fw_signals { 1234 struct { 1235 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 1236 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 1237 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 1238 uint32_t detection_required : 1; /**< 1 if detection is required */ 1239 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 1240 uint32_t reserved_bits : 27; /**< Reversed */ 1241 } bits; 1242 uint32_t all; 1243 }; 1244 1245 /** 1246 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 1247 */ 1248 union dmub_shared_state_ips_driver_signals { 1249 struct { 1250 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 1251 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 1252 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 1253 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 1254 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 1255 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 1256 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 1257 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 1258 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 1259 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 1260 uint32_t reserved_bits : 22; /**< Reversed bits */ 1261 } bits; 1262 uint32_t all; 1263 }; 1264 1265 /** 1266 * IPS FW Version 1267 */ 1268 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 1269 1270 struct dmub_shared_state_debug_setup { 1271 union { 1272 struct { 1273 uint32_t exclude_points[62]; 1274 } profile_mode; 1275 }; 1276 }; 1277 1278 /** 1279 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 1280 */ 1281 struct dmub_shared_state_ips_fw { 1282 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 1283 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 1284 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 1285 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 1286 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 1287 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 1288 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 1289 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 1290 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 1291 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 1292 }; /* 248-bytes, fixed */ 1293 1294 /** 1295 * IPS Driver Version 1296 */ 1297 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 1298 1299 /** 1300 * struct dmub_shared_state_ips_driver - Driver state for IPS. 1301 */ 1302 struct dmub_shared_state_ips_driver { 1303 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 1304 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 1305 }; /* 248-bytes, fixed */ 1306 1307 /** 1308 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1309 */ 1310 struct dmub_shared_state_cursor_offload_stream_v1 { 1311 uint32_t last_write_idx; /**< Last write index */ 1312 uint8_t reserved[28]; /**< Reserved bytes. */ 1313 }; /* 32-bytes, fixed */ 1314 1315 /** 1316 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1317 */ 1318 struct dmub_shared_state_cursor_offload_v1 { 1319 struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */ 1320 uint8_t reserved[56]; /**< reserved for future use */ 1321 }; /* 248-bytes, fixed */ 1322 1323 /** 1324 * enum dmub_shared_state_feature_common - Generic payload. 1325 */ 1326 struct dmub_shared_state_feature_common { 1327 uint32_t padding[62]; 1328 }; /* 248-bytes, fixed */ 1329 1330 /** 1331 * enum dmub_shared_state_feature_header - Feature description. 1332 */ 1333 struct dmub_shared_state_feature_header { 1334 uint16_t id; /**< Feature ID */ 1335 uint16_t version; /**< Feature version */ 1336 uint32_t reserved; /**< Reserved bytes. */ 1337 }; /* 8 bytes, fixed */ 1338 1339 /** 1340 * struct dmub_shared_state_feature_block - Feature block. 1341 */ 1342 struct dmub_shared_state_feature_block { 1343 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 1344 union dmub_shared_feature_state_union { 1345 struct dmub_shared_state_feature_common common; /**< Generic data */ 1346 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 1347 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 1348 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 1349 struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */ 1350 } data; /**< Shared state data. */ 1351 }; /* 256-bytes, fixed */ 1352 1353 /** 1354 * Shared state size in bytes. 1355 */ 1356 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 1357 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 1358 1359 //============================================================================== 1360 //</DMUB_STATUS>================================================================ 1361 //============================================================================== 1362 //< DMUB_VBIOS>================================================================= 1363 //============================================================================== 1364 1365 /* 1366 * enum dmub_cmd_vbios_type - VBIOS commands. 1367 * 1368 * Command IDs should be treated as stable ABI. 1369 * Do not reuse or modify IDs. 1370 */ 1371 enum dmub_cmd_vbios_type { 1372 /** 1373 * Configures the DIG encoder. 1374 */ 1375 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1376 /** 1377 * Controls the PHY. 1378 */ 1379 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1380 /** 1381 * Sets the pixel clock/symbol clock. 1382 */ 1383 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1384 /** 1385 * Enables or disables power gating. 1386 */ 1387 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1388 /** 1389 * Controls embedded panels. 1390 */ 1391 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1392 /** 1393 * Query DP alt status on a transmitter. 1394 */ 1395 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1396 /** 1397 * Control PHY FSM 1398 */ 1399 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1400 /** 1401 * Controls domain power gating 1402 */ 1403 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1404 }; 1405 1406 //============================================================================== 1407 //</DMUB_VBIOS>================================================================= 1408 //============================================================================== 1409 //< DMUB_GPINT>================================================================= 1410 //============================================================================== 1411 1412 /** 1413 * The shifts and masks below may alternatively be used to format and read 1414 * the command register bits. 1415 */ 1416 1417 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1418 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1419 1420 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1421 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1422 1423 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1424 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1425 1426 /** 1427 * Command responses. 1428 */ 1429 1430 /** 1431 * Return response for DMUB_GPINT__STOP_FW command. 1432 */ 1433 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1434 1435 /** 1436 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1437 */ 1438 union dmub_gpint_data_register { 1439 struct { 1440 uint32_t param : 16; /**< 16-bit parameter */ 1441 uint32_t command_code : 12; /**< GPINT command */ 1442 uint32_t status : 4; /**< Command status bit */ 1443 } bits; /**< GPINT bit access */ 1444 uint32_t all; /**< GPINT 32-bit access */ 1445 }; 1446 1447 /* 1448 * enum dmub_gpint_command - GPINT command to DMCUB FW 1449 * 1450 * Command IDs should be treated as stable ABI. 1451 * Do not reuse or modify IDs. 1452 */ 1453 enum dmub_gpint_command { 1454 /** 1455 * Invalid command, ignored. 1456 */ 1457 DMUB_GPINT__INVALID_COMMAND = 0, 1458 /** 1459 * DESC: Queries the firmware version. 1460 * RETURN: Firmware version. 1461 */ 1462 DMUB_GPINT__GET_FW_VERSION = 1, 1463 /** 1464 * DESC: Halts the firmware. 1465 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1466 */ 1467 DMUB_GPINT__STOP_FW = 2, 1468 /** 1469 * DESC: Get PSR state from FW. 1470 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1471 */ 1472 DMUB_GPINT__GET_PSR_STATE = 7, 1473 /** 1474 * DESC: Notifies DMCUB of the currently active streams. 1475 * ARGS: Stream mask, 1 bit per active stream index. 1476 */ 1477 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1478 /** 1479 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1480 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1481 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1482 * RETURN: PSR residency in milli-percent. 1483 */ 1484 DMUB_GPINT__PSR_RESIDENCY = 9, 1485 1486 /** 1487 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1488 */ 1489 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1490 1491 /** 1492 * DESC: Get REPLAY state from FW. 1493 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1494 */ 1495 DMUB_GPINT__GET_REPLAY_STATE = 13, 1496 1497 /** 1498 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1499 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1500 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1501 * RETURN: REPLAY residency in milli-percent. 1502 */ 1503 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1504 1505 /** 1506 * DESC: Set CACP internal core configuration 1507 */ 1508 DMUB_GPINT__TRIGGER_CACP = 18, 1509 1510 /** 1511 * DESC: Copy bounding box to the host. 1512 * ARGS: Version of bounding box to copy 1513 * RETURN: Result of copying bounding box 1514 */ 1515 DMUB_GPINT__BB_COPY = 96, 1516 1517 /** 1518 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1519 * ARGS: The word3 for the 64 bit address 1520 */ 1521 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1522 1523 /** 1524 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1525 * ARGS: The word2 for the 64 bit address 1526 */ 1527 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1528 1529 /** 1530 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1531 * ARGS: The word1 for the 64 bit address 1532 */ 1533 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1534 1535 /** 1536 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1537 * ARGS: The word0 for the 64 bit address 1538 */ 1539 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1540 1541 /** 1542 * DESC: Updates the trace buffer lower 32-bit mask. 1543 * ARGS: The new mask 1544 * RETURN: Lower 32-bit mask. 1545 */ 1546 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1547 1548 /** 1549 * DESC: Updates the trace buffer mask bit0~bit15. 1550 * ARGS: The new mask 1551 * RETURN: Lower 32-bit mask. 1552 */ 1553 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1554 1555 /** 1556 * DESC: Updates the trace buffer mask bit16~bit31. 1557 * ARGS: The new mask 1558 * RETURN: Lower 32-bit mask. 1559 */ 1560 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1561 1562 /** 1563 * DESC: Updates the trace buffer mask bit32~bit47. 1564 * ARGS: The new mask 1565 * RETURN: Lower 32-bit mask. 1566 */ 1567 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1568 1569 /** 1570 * DESC: Updates the trace buffer mask bit48~bit63. 1571 * ARGS: The new mask 1572 * RETURN: Lower 32-bit mask. 1573 */ 1574 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1575 1576 /** 1577 * DESC: Read the trace buffer mask bi0~bit15. 1578 */ 1579 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1580 1581 /** 1582 * DESC: Read the trace buffer mask bit16~bit31. 1583 */ 1584 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1585 1586 /** 1587 * DESC: Read the trace buffer mask bi32~bit47. 1588 */ 1589 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1590 1591 /** 1592 * DESC: Updates the trace buffer mask bit32~bit63. 1593 */ 1594 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1595 1596 /** 1597 * DESC: Set IPS residency measurement 1598 * ARGS: 0 - Disable ips measurement 1599 * 1 - Enable ips measurement 1600 */ 1601 DMUB_GPINT__IPS_RESIDENCY = 121, 1602 /** 1603 * DESC: Enable measurements for various task duration 1604 * ARGS: 0 - Disable measurement 1605 * 1 - Enable measurement 1606 */ 1607 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1608 /** 1609 * DESC: Gets IPS residency in microseconds 1610 * ARGS: 0 - Return IPS1 residency 1611 * 1 - Return IPS2 residency 1612 * 2 - Return IPS0_RCG residency 1613 * 3 - Return IPS1_ONO2_ON residency 1614 * 4 - Return IPS1_Z8_RETENTION residency 1615 * RETURN: Total residency in microseconds - lower 32 bits 1616 */ 1617 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1618 /** 1619 * DESC: Gets IPS1 histogram counts 1620 * ARGS: Bucket index 1621 * RETURN: Total count for the bucket 1622 */ 1623 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1624 /** 1625 * DESC: Gets IPS2 histogram counts 1626 * ARGS: Bucket index 1627 * RETURN: Total count for the bucket 1628 */ 1629 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1630 /** 1631 * DESC: Gets IPS residency 1632 * ARGS: 0 - Return IPS1 residency 1633 * 1 - Return IPS2 residency 1634 * 2 - Return IPS0_RCG residency 1635 * 3 - Return IPS1_ONO2_ON residency 1636 * 4 - Return IPS1_Z8_RETENTION residency 1637 * RETURN: Total residency in milli-percent. 1638 */ 1639 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1640 /** 1641 * DESC: Gets IPS0_RCG histogram counts 1642 * ARGS: Bucket index 1643 * RETURN: Total count for the bucket 1644 */ 1645 DMUB_GPINT__GET_IPS0_RCG_HISTOGRAM_COUNTER = 128, 1646 /** 1647 * DESC: Gets IPS1_ONO2_ON histogram counts 1648 * ARGS: Bucket index 1649 * RETURN: Total count for the bucket 1650 */ 1651 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1652 /** 1653 * DESC: Gets IPS entry counter during residency measurement 1654 * ARGS: 0 - Return IPS1 entry counts 1655 * 1 - Return IPS2 entry counts 1656 * 2 - Return IPS0_RCG entry counts 1657 * 3 - Return IPS1_ONO2_ON entry counts 1658 * 4 - Return IPS1_Z8_RETENTION entry counts 1659 * RETURN: Entry counter for selected IPS mode 1660 */ 1661 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1662 /** 1663 * DESC: Gets IPS inactive residency in microseconds 1664 * ARGS: 0 - Return IPS1_MAX residency 1665 * 1 - Return IPS2 residency 1666 * 2 - Return IPS0_RCG residency 1667 * 3 - Return IPS1_ONO2_ON residency 1668 * 4 - Return IPS1_Z8_RETENTION residency 1669 * RETURN: Total inactive residency in microseconds - lower 32 bits 1670 */ 1671 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1672 /** 1673 * DESC: Gets IPS inactive residency in microseconds 1674 * ARGS: 0 - Return IPS1_MAX residency 1675 * 1 - Return IPS2 residency 1676 * 2 - Return IPS0_RCG residency 1677 * 3 - Return IPS1_ONO2_ON residency 1678 * 4 - Return IPS1_Z8_RETENTION residency 1679 * RETURN: Total inactive residency in microseconds - upper 32 bits 1680 */ 1681 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1682 /** 1683 * DESC: Gets IPS residency in microseconds 1684 * ARGS: 0 - Return IPS1 residency 1685 * 1 - Return IPS2 residency 1686 * 2 - Return IPS0_RCG residency 1687 * 3 - Return IPS1_ONO2_ON residency 1688 * 4 - Return IPS1_Z8_RETENTION residency 1689 * RETURN: Total residency in microseconds - upper 32 bits 1690 */ 1691 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1692 /** 1693 * DESC: Setup debug configs. 1694 */ 1695 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1696 /** 1697 * DESC: Initiates IPS wake sequence. 1698 */ 1699 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1700 /** 1701 * DESC: Do panel power off sequence 1702 * ARGS: 1 - Power off 1703 */ 1704 DMUB_GPINT__PANEL_POWER_OFF_SEQ = 138, 1705 }; 1706 1707 /** 1708 * INBOX0 generic command definition 1709 */ 1710 union dmub_inbox0_cmd_common { 1711 struct { 1712 uint32_t command_code: 8; /**< INBOX0 command code */ 1713 uint32_t param: 24; /**< 24-bit parameter */ 1714 } bits; 1715 uint32_t all; 1716 }; 1717 1718 /** 1719 * INBOX0 hw_lock command definition 1720 */ 1721 union dmub_inbox0_cmd_lock_hw { 1722 struct { 1723 uint32_t command_code: 8; 1724 1725 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1726 uint32_t hw_lock_client: 2; 1727 1728 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1729 uint32_t otg_inst: 3; 1730 uint32_t opp_inst: 3; 1731 uint32_t dig_inst: 3; 1732 1733 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1734 uint32_t lock_pipe: 1; 1735 uint32_t lock_cursor: 1; 1736 uint32_t lock_dig: 1; 1737 uint32_t triple_buffer_lock: 1; 1738 1739 uint32_t lock: 1; /**< Lock */ 1740 uint32_t should_release: 1; /**< Release */ 1741 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1742 } bits; 1743 uint32_t all; 1744 }; 1745 1746 union dmub_inbox0_data_register { 1747 union dmub_inbox0_cmd_common inbox0_cmd_common; 1748 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1749 }; 1750 1751 enum dmub_inbox0_command { 1752 /** 1753 * DESC: Invalid command, ignored. 1754 */ 1755 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1756 /** 1757 * DESC: Notification to acquire/release HW lock 1758 * ARGS: 1759 */ 1760 DMUB_INBOX0_CMD__HW_LOCK = 1, 1761 }; 1762 //============================================================================== 1763 //</DMUB_GPINT>================================================================= 1764 //============================================================================== 1765 //< DMUB_CMD>=================================================================== 1766 //============================================================================== 1767 1768 /** 1769 * Size in bytes of each DMUB command. 1770 */ 1771 #define DMUB_RB_CMD_SIZE 64 1772 1773 /** 1774 * Maximum number of items in the DMUB ringbuffer. 1775 */ 1776 #define DMUB_RB_MAX_ENTRY 128 1777 1778 /** 1779 * Ringbuffer size in bytes. 1780 */ 1781 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1782 1783 /** 1784 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1785 */ 1786 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1787 1788 /** 1789 * Ringbuffer size in bytes. 1790 */ 1791 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1792 1793 /** 1794 * REG_SET mask for reg offload. 1795 */ 1796 #define REG_SET_MASK 0xFFFF 1797 1798 /* 1799 * enum dmub_cmd_type - DMUB inbox command. 1800 * 1801 * Command IDs should be treated as stable ABI. 1802 * Do not reuse or modify IDs. 1803 */ 1804 enum dmub_cmd_type { 1805 /** 1806 * Invalid command. 1807 */ 1808 DMUB_CMD__NULL = 0, 1809 /** 1810 * Read modify write register sequence offload. 1811 */ 1812 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1813 /** 1814 * Field update register sequence offload. 1815 */ 1816 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1817 /** 1818 * Burst write sequence offload. 1819 */ 1820 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1821 /** 1822 * Reg wait sequence offload. 1823 */ 1824 DMUB_CMD__REG_REG_WAIT = 4, 1825 /** 1826 * Workaround to avoid HUBP underflow during NV12 playback. 1827 */ 1828 DMUB_CMD__PLAT_54186_WA = 5, 1829 /** 1830 * Command type used to query FW feature caps. 1831 */ 1832 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1833 /** 1834 * Command type used to get visual confirm color. 1835 */ 1836 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1837 /** 1838 * Command type used for all PSR commands. 1839 */ 1840 DMUB_CMD__PSR = 64, 1841 /** 1842 * Command type used for all MALL commands. 1843 */ 1844 DMUB_CMD__MALL = 65, 1845 /** 1846 * Command type used for all ABM commands. 1847 */ 1848 DMUB_CMD__ABM = 66, 1849 /** 1850 * Command type used to update dirty rects in FW. 1851 */ 1852 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1853 /** 1854 * Command type used to update cursor info in FW. 1855 */ 1856 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1857 /** 1858 * Command type used for HW locking in FW. 1859 */ 1860 DMUB_CMD__HW_LOCK = 69, 1861 /** 1862 * Command type used to access DP AUX. 1863 */ 1864 DMUB_CMD__DP_AUX_ACCESS = 70, 1865 /** 1866 * Command type used for OUTBOX1 notification enable 1867 */ 1868 DMUB_CMD__OUTBOX1_ENABLE = 71, 1869 1870 /** 1871 * Command type used for all idle optimization commands. 1872 */ 1873 DMUB_CMD__IDLE_OPT = 72, 1874 /** 1875 * Command type used for all clock manager commands. 1876 */ 1877 DMUB_CMD__CLK_MGR = 73, 1878 /** 1879 * Command type used for all panel control commands. 1880 */ 1881 DMUB_CMD__PANEL_CNTL = 74, 1882 1883 /** 1884 * Command type used for all CAB commands. 1885 */ 1886 DMUB_CMD__CAB_FOR_SS = 75, 1887 1888 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1889 1890 /** 1891 * Command type used for interfacing with DPIA. 1892 */ 1893 DMUB_CMD__DPIA = 77, 1894 /** 1895 * Command type used for EDID CEA parsing 1896 */ 1897 DMUB_CMD__EDID_CEA = 79, 1898 /** 1899 * Command type used for getting usbc cable ID 1900 */ 1901 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1902 /** 1903 * Command type used to query HPD state. 1904 */ 1905 DMUB_CMD__QUERY_HPD_STATE = 82, 1906 /** 1907 * Command type used for all VBIOS interface commands. 1908 */ 1909 /** 1910 * Command type used for all REPLAY commands. 1911 */ 1912 DMUB_CMD__REPLAY = 83, 1913 1914 /** 1915 * Command type used for all SECURE_DISPLAY commands. 1916 */ 1917 DMUB_CMD__SECURE_DISPLAY = 85, 1918 1919 /** 1920 * Command type used to set DPIA HPD interrupt state 1921 */ 1922 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1923 1924 /** 1925 * Command type used for all CACP commands. 1926 */ 1927 DMUB_CMD__CACP = 87, 1928 1929 /** 1930 * Command type used for all PSP commands. 1931 */ 1932 DMUB_CMD__PSP = 88, 1933 1934 /** 1935 * Command type used for all Fused IO commands. 1936 */ 1937 DMUB_CMD__FUSED_IO = 89, 1938 1939 /** 1940 * Command type used for all LSDMA commands. 1941 */ 1942 DMUB_CMD__LSDMA = 90, 1943 1944 /** 1945 * Command type use for all IPS commands. 1946 */ 1947 DMUB_CMD__IPS = 91, 1948 1949 /** 1950 * Command type use for Cursor offload. 1951 */ 1952 DMUB_CMD__CURSOR_OFFLOAD = 92, 1953 1954 /** 1955 * Command type used for all SMART_POWER_OLED commands. 1956 */ 1957 DMUB_CMD__SMART_POWER_OLED = 93, 1958 1959 /** 1960 * Command type use for all Panel Replay commands. 1961 */ 1962 DMUB_CMD__PR = 94, 1963 1964 /** 1965 * Command type used for all IHC commands. 1966 */ 1967 DMUB_CMD__IHC = 95, 1968 1969 /** 1970 * Command type use for boot time crc commands. 1971 */ 1972 DMUB_CMD__BOOT_TIME_CRC = 96, 1973 1974 /** 1975 * Command type use for VBIOS shared commands. 1976 */ 1977 DMUB_CMD__VBIOS = 128, 1978 }; 1979 1980 /** 1981 * enum dmub_out_cmd_type - DMUB outbox commands. 1982 */ 1983 enum dmub_out_cmd_type { 1984 /** 1985 * Invalid outbox command, ignored. 1986 */ 1987 DMUB_OUT_CMD__NULL = 0, 1988 /** 1989 * Command type used for DP AUX Reply data notification 1990 */ 1991 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1992 /** 1993 * Command type used for DP HPD event notification 1994 */ 1995 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1996 /** 1997 * Command type used for SET_CONFIG Reply notification 1998 */ 1999 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 2000 /** 2001 * Command type used for USB4 DPIA notification 2002 */ 2003 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 2004 /** 2005 * Command type used for HPD redetect notification 2006 */ 2007 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 2008 /** 2009 * Command type used for Fused IO notification 2010 */ 2011 DMUB_OUT_CMD__FUSED_IO = 7, 2012 }; 2013 2014 /* DMUB_CMD__DPIA command sub-types. */ 2015 enum dmub_cmd_dpia_type { 2016 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 2017 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 2018 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 2019 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 2020 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 2021 }; 2022 2023 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 2024 enum dmub_cmd_dpia_notification_type { 2025 DPIA_NOTIFY__BW_ALLOCATION = 0, 2026 }; 2027 2028 #pragma pack(push, 1) 2029 2030 /** 2031 * struct dmub_cmd_header - Common command header fields. 2032 */ 2033 struct dmub_cmd_header { 2034 unsigned int type : 8; /**< command type */ 2035 unsigned int sub_type : 8; /**< command sub type */ 2036 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 2037 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 2038 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 2039 unsigned int reserved0 : 5; /**< reserved bits */ 2040 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 2041 unsigned int reserved1 : 2; /**< reserved bits */ 2042 }; 2043 2044 /* 2045 * struct dmub_cmd_read_modify_write_sequence - Read modify write 2046 * 2047 * 60 payload bytes can hold up to 5 sets of read modify writes, 2048 * each take 3 dwords. 2049 * 2050 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 2051 * 2052 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 2053 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 2054 */ 2055 struct dmub_cmd_read_modify_write_sequence { 2056 uint32_t addr; /**< register address */ 2057 uint32_t modify_mask; /**< modify mask */ 2058 uint32_t modify_value; /**< modify value */ 2059 }; 2060 2061 /** 2062 * Maximum number of ops in read modify write sequence. 2063 */ 2064 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 2065 2066 /** 2067 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 2068 */ 2069 struct dmub_rb_cmd_read_modify_write { 2070 struct dmub_cmd_header header; /**< command header */ 2071 /** 2072 * Read modify write sequence. 2073 */ 2074 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 2075 }; 2076 2077 /* 2078 * Update a register with specified masks and values sequeunce 2079 * 2080 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 2081 * 2082 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 2083 * 2084 * 2085 * USE CASE: 2086 * 1. auto-increment register where additional read would update pointer and produce wrong result 2087 * 2. toggle a bit without read in the middle 2088 */ 2089 2090 struct dmub_cmd_reg_field_update_sequence { 2091 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 2092 uint32_t modify_value; /**< value to update with */ 2093 }; 2094 2095 /** 2096 * Maximum number of ops in field update sequence. 2097 */ 2098 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 2099 2100 /** 2101 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 2102 */ 2103 struct dmub_rb_cmd_reg_field_update_sequence { 2104 struct dmub_cmd_header header; /**< command header */ 2105 uint32_t addr; /**< register address */ 2106 /** 2107 * Field update sequence. 2108 */ 2109 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 2110 }; 2111 2112 2113 /** 2114 * Maximum number of burst write values. 2115 */ 2116 #define DMUB_BURST_WRITE_VALUES__MAX 14 2117 2118 /* 2119 * struct dmub_rb_cmd_burst_write - Burst write 2120 * 2121 * support use case such as writing out LUTs. 2122 * 2123 * 60 payload bytes can hold up to 14 values to write to given address 2124 * 2125 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 2126 */ 2127 struct dmub_rb_cmd_burst_write { 2128 struct dmub_cmd_header header; /**< command header */ 2129 uint32_t addr; /**< register start address */ 2130 /** 2131 * Burst write register values. 2132 */ 2133 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 2134 }; 2135 2136 /** 2137 * struct dmub_rb_cmd_common - Common command header 2138 */ 2139 struct dmub_rb_cmd_common { 2140 struct dmub_cmd_header header; /**< command header */ 2141 /** 2142 * Padding to RB_CMD_SIZE 2143 */ 2144 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 2145 }; 2146 2147 /** 2148 * struct dmub_cmd_reg_wait_data - Register wait data 2149 */ 2150 struct dmub_cmd_reg_wait_data { 2151 uint32_t addr; /**< Register address */ 2152 uint32_t mask; /**< Mask for register bits */ 2153 uint32_t condition_field_value; /**< Value to wait for */ 2154 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 2155 }; 2156 2157 /** 2158 * struct dmub_rb_cmd_reg_wait - Register wait command 2159 */ 2160 struct dmub_rb_cmd_reg_wait { 2161 struct dmub_cmd_header header; /**< Command header */ 2162 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 2163 }; 2164 2165 /** 2166 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 2167 * 2168 * Reprograms surface parameters to avoid underflow. 2169 */ 2170 struct dmub_cmd_PLAT_54186_wa { 2171 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 2172 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 2173 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 2174 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 2175 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 2176 struct { 2177 uint32_t hubp_inst : 4; /**< HUBP instance */ 2178 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 2179 uint32_t immediate :1; /**< Immediate flip */ 2180 uint32_t vmid : 4; /**< VMID */ 2181 uint32_t grph_stereo : 1; /**< 1 if stereo */ 2182 uint32_t reserved : 21; /**< Reserved */ 2183 } flip_params; /**< Pageflip parameters */ 2184 uint32_t reserved[9]; /**< Reserved bits */ 2185 }; 2186 2187 /** 2188 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 2189 */ 2190 struct dmub_rb_cmd_PLAT_54186_wa { 2191 struct dmub_cmd_header header; /**< Command header */ 2192 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 2193 }; 2194 2195 /** 2196 * enum dmub_cmd_mall_type - MALL commands 2197 */ 2198 enum dmub_cmd_mall_type { 2199 /** 2200 * Allows display refresh from MALL. 2201 */ 2202 DMUB_CMD__MALL_ACTION_ALLOW = 0, 2203 /** 2204 * Disallows display refresh from MALL. 2205 */ 2206 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 2207 /** 2208 * Cursor copy for MALL. 2209 */ 2210 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 2211 /** 2212 * Controls DF requests. 2213 */ 2214 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 2215 }; 2216 2217 /** 2218 * struct dmub_rb_cmd_mall - MALL command data. 2219 */ 2220 struct dmub_rb_cmd_mall { 2221 struct dmub_cmd_header header; /**< Common command header */ 2222 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 2223 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 2224 uint32_t tmr_delay; /**< Timer delay */ 2225 uint32_t tmr_scale; /**< Timer scale */ 2226 uint16_t cursor_width; /**< Cursor width in pixels */ 2227 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 2228 uint16_t cursor_height; /**< Cursor height in pixels */ 2229 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 2230 uint8_t debug_bits; /**< Debug bits */ 2231 2232 uint8_t reserved1; /**< Reserved bits */ 2233 uint8_t reserved2; /**< Reserved bits */ 2234 }; 2235 2236 /** 2237 * enum dmub_cmd_cab_type - CAB command data. 2238 */ 2239 enum dmub_cmd_cab_type { 2240 /** 2241 * No idle optimizations (i.e. no CAB) 2242 */ 2243 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 2244 /** 2245 * No DCN requests for memory 2246 */ 2247 DMUB_CMD__CAB_NO_DCN_REQ = 1, 2248 /** 2249 * Fit surfaces in CAB (i.e. CAB enable) 2250 */ 2251 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 2252 /** 2253 * Do not fit surfaces in CAB (i.e. no CAB) 2254 */ 2255 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 2256 }; 2257 2258 /** 2259 * struct dmub_rb_cmd_cab_for_ss - CAB command data. 2260 */ 2261 struct dmub_rb_cmd_cab_for_ss { 2262 struct dmub_cmd_header header; 2263 uint8_t cab_alloc_ways; /* total number of ways */ 2264 uint8_t debug_bits; /* debug bits */ 2265 }; 2266 2267 /** 2268 * Enum for indicating which MCLK switch mode per pipe 2269 */ 2270 enum mclk_switch_mode { 2271 NONE = 0, 2272 FPO = 1, 2273 SUBVP = 2, 2274 VBLANK = 3, 2275 }; 2276 2277 /* Per pipe struct which stores the MCLK switch mode 2278 * data to be sent to DMUB. 2279 * Named "v2" for now -- once FPO and SUBVP are fully merged 2280 * the type name can be updated 2281 */ 2282 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 2283 union { 2284 struct { 2285 uint32_t pix_clk_100hz; 2286 uint16_t main_vblank_start; 2287 uint16_t main_vblank_end; 2288 uint16_t mall_region_lines; 2289 uint16_t prefetch_lines; 2290 uint16_t prefetch_to_mall_start_lines; 2291 uint16_t processing_delay_lines; 2292 uint16_t htotal; // required to calculate line time for multi-display cases 2293 uint16_t vtotal; 2294 uint8_t main_pipe_index; 2295 uint8_t phantom_pipe_index; 2296 /* Since the microschedule is calculated in terms of OTG lines, 2297 * include any scaling factors to make sure when we get accurate 2298 * conversion when programming MALL_START_LINE (which is in terms 2299 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 2300 * is 1/2 (numerator = 1, denominator = 2). 2301 */ 2302 uint8_t scale_factor_numerator; 2303 uint8_t scale_factor_denominator; 2304 uint8_t is_drr; 2305 uint8_t main_split_pipe_index; 2306 uint8_t phantom_split_pipe_index; 2307 } subvp_data; 2308 2309 struct { 2310 uint32_t pix_clk_100hz; 2311 uint16_t vblank_start; 2312 uint16_t vblank_end; 2313 uint16_t vstartup_start; 2314 uint16_t vtotal; 2315 uint16_t htotal; 2316 uint8_t vblank_pipe_index; 2317 uint8_t padding[1]; 2318 struct { 2319 uint8_t drr_in_use; 2320 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 2321 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 2322 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 2323 uint8_t use_ramping; // Use ramping or not 2324 uint8_t drr_vblank_start_margin; 2325 } drr_info; // DRR considered as part of SubVP + VBLANK case 2326 } vblank_data; 2327 } pipe_config; 2328 2329 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 2330 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 2331 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 2332 */ 2333 uint8_t mode; // enum mclk_switch_mode 2334 }; 2335 2336 /** 2337 * Config data for Sub-VP and FPO 2338 * Named "v2" for now -- once FPO and SUBVP are fully merged 2339 * the type name can be updated 2340 */ 2341 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 2342 uint16_t watermark_a_cache; 2343 uint8_t vertical_int_margin_us; 2344 uint8_t pstate_allow_width_us; 2345 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 2346 }; 2347 2348 /** 2349 * DMUB rb command definition for Sub-VP and FPO 2350 * Named "v2" for now -- once FPO and SUBVP are fully merged 2351 * the type name can be updated 2352 */ 2353 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 2354 struct dmub_cmd_header header; 2355 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 2356 }; 2357 2358 struct dmub_flip_addr_info { 2359 uint32_t surf_addr_lo; 2360 uint32_t surf_addr_c_lo; 2361 uint32_t meta_addr_lo; 2362 uint32_t meta_addr_c_lo; 2363 uint16_t surf_addr_hi; 2364 uint16_t surf_addr_c_hi; 2365 uint16_t meta_addr_hi; 2366 uint16_t meta_addr_c_hi; 2367 }; 2368 2369 struct dmub_fams2_flip_info { 2370 union { 2371 struct { 2372 uint8_t is_immediate: 1; 2373 } bits; 2374 uint8_t all; 2375 } config; 2376 uint8_t otg_inst; 2377 uint8_t pipe_mask; 2378 uint8_t pad; 2379 struct dmub_flip_addr_info addr_info; 2380 }; 2381 2382 struct dmub_rb_cmd_fams2_flip { 2383 struct dmub_cmd_header header; 2384 struct dmub_fams2_flip_info flip_info; 2385 }; 2386 2387 struct dmub_cmd_lsdma_data { 2388 union { 2389 struct lsdma_init_data { 2390 union dmub_addr gpu_addr_base; 2391 uint32_t ring_size; 2392 } init_data; 2393 struct lsdma_tiled_copy_data { 2394 uint32_t src_addr_lo; 2395 uint32_t src_addr_hi; 2396 2397 uint32_t dst_addr_lo; 2398 uint32_t dst_addr_hi; 2399 2400 uint32_t src_x : 16; 2401 uint32_t src_y : 16; 2402 2403 uint32_t dst_x : 16; 2404 uint32_t dst_y : 16; 2405 2406 uint32_t src_width : 16; 2407 uint32_t src_height : 16; 2408 2409 uint32_t dst_width : 16; 2410 uint32_t dst_height : 16; 2411 2412 uint32_t rect_x : 16; 2413 uint32_t rect_y : 16; 2414 2415 uint32_t src_swizzle_mode : 5; 2416 uint32_t src_mip_max : 5; 2417 uint32_t src_mip_id : 5; 2418 uint32_t dst_mip_max : 5; 2419 uint32_t dst_swizzle_mode : 5; 2420 uint32_t dst_mip_id : 5; 2421 uint32_t dcc : 1; 2422 uint32_t padding1 : 1; 2423 2424 uint32_t data_format : 6; 2425 uint32_t tmz : 4; 2426 uint32_t dst_element_size : 3; 2427 uint32_t num_type : 3; 2428 uint32_t src_element_size : 3; 2429 uint32_t write_compress : 2; 2430 uint32_t cache_policy_dst : 3; 2431 uint32_t cache_policy_src : 3; 2432 uint32_t read_compress : 2; 2433 uint32_t max_com : 2; 2434 uint32_t max_uncom : 1; 2435 2436 uint32_t dst_dim : 2; 2437 uint32_t src_dim : 2; 2438 uint32_t padding : 28; 2439 } tiled_copy_data; 2440 struct lsdma_linear_copy_data { 2441 uint32_t src_lo; 2442 uint32_t src_hi; 2443 2444 uint32_t dst_lo; 2445 uint32_t dst_hi; 2446 2447 uint32_t count : 30; 2448 uint32_t pad0 : 2; 2449 2450 uint32_t tmz : 4; 2451 uint32_t cache_policy_src : 3; 2452 uint32_t cache_policy_dst : 3; 2453 uint32_t data_format : 6; 2454 uint32_t num_type : 3; 2455 uint32_t read_compress : 2; 2456 uint32_t write_compress : 2; 2457 uint32_t max_com : 2; 2458 uint32_t max_uncom : 1; 2459 uint32_t pad1 : 6; 2460 } linear_copy_data; 2461 struct lsdma_linear_sub_window_copy_data { 2462 uint32_t src_lo; 2463 uint32_t src_hi; 2464 2465 uint32_t dst_lo; 2466 uint32_t dst_hi; 2467 2468 uint32_t src_x : 16; 2469 uint32_t src_y : 16; 2470 2471 uint32_t dst_x : 16; 2472 uint32_t dst_y : 16; 2473 2474 uint32_t rect_x : 16; 2475 uint32_t rect_y : 16; 2476 2477 uint32_t src_pitch : 16; 2478 uint32_t dst_pitch : 16; 2479 2480 uint32_t src_slice_pitch; 2481 uint32_t dst_slice_pitch; 2482 2483 uint32_t tmz : 4; 2484 uint32_t element_size : 3; 2485 uint32_t src_cache_policy : 3; 2486 uint32_t dst_cache_policy : 3; 2487 uint32_t data_format : 6; 2488 uint32_t num_type : 3; 2489 uint32_t read_compress : 2; 2490 uint32_t write_compress : 2; 2491 uint32_t max_com : 2; 2492 uint32_t max_uncom : 1; 2493 uint32_t reserved0 : 3; 2494 } linear_sub_window_copy_data; 2495 struct lsdma_reg_write_data { 2496 uint32_t reg_addr; 2497 uint32_t reg_data; 2498 } reg_write_data; 2499 struct lsdma_pio_copy_data { 2500 uint32_t src_lo; 2501 uint32_t src_hi; 2502 2503 uint32_t dst_lo; 2504 uint32_t dst_hi; 2505 2506 union { 2507 struct { 2508 uint32_t byte_count : 26; 2509 uint32_t src_loc : 1; 2510 uint32_t dst_loc : 1; 2511 uint32_t src_addr_inc : 1; 2512 uint32_t dst_addr_inc : 1; 2513 uint32_t overlap_disable : 1; 2514 uint32_t constant_fill : 1; 2515 } fields; 2516 uint32_t raw; 2517 } packet; 2518 } pio_copy_data; 2519 struct lsdma_pio_constfill_data { 2520 uint32_t dst_lo; 2521 uint32_t dst_hi; 2522 2523 union { 2524 struct { 2525 uint32_t byte_count : 26; 2526 uint32_t src_loc : 1; 2527 uint32_t dst_loc : 1; 2528 uint32_t src_addr_inc : 1; 2529 uint32_t dst_addr_inc : 1; 2530 uint32_t overlap_disable : 1; 2531 uint32_t constant_fill : 1; 2532 } fields; 2533 uint32_t raw; 2534 } packet; 2535 2536 uint32_t data; 2537 } pio_constfill_data; 2538 2539 uint32_t all[14]; 2540 } u; 2541 }; 2542 2543 struct dmub_rb_cmd_lsdma { 2544 struct dmub_cmd_header header; 2545 struct dmub_cmd_lsdma_data lsdma_data; 2546 }; 2547 2548 struct dmub_optc_state_v2 { 2549 uint32_t v_total_min; 2550 uint32_t v_total_max; 2551 uint32_t v_total_mid; 2552 uint32_t v_total_mid_frame_num; 2553 uint8_t program_manual_trigger; 2554 uint8_t tg_inst; 2555 uint8_t pad[2]; 2556 }; 2557 2558 struct dmub_optc_position { 2559 uint32_t vpos; 2560 uint32_t hpos; 2561 uint32_t frame; 2562 }; 2563 2564 struct dmub_rb_cmd_fams2_drr_update { 2565 struct dmub_cmd_header header; 2566 struct dmub_optc_state_v2 dmub_optc_state_req; 2567 }; 2568 2569 /* HW and FW global configuration data for FAMS2 */ 2570 /* FAMS2 types and structs */ 2571 enum fams2_stream_type { 2572 FAMS2_STREAM_TYPE_NONE = 0, 2573 FAMS2_STREAM_TYPE_VBLANK = 1, 2574 FAMS2_STREAM_TYPE_VACTIVE = 2, 2575 FAMS2_STREAM_TYPE_DRR = 3, 2576 FAMS2_STREAM_TYPE_SUBVP = 4, 2577 }; 2578 2579 struct dmub_rect16 { 2580 /** 2581 * Dirty rect x offset. 2582 */ 2583 uint16_t x; 2584 2585 /** 2586 * Dirty rect y offset. 2587 */ 2588 uint16_t y; 2589 2590 /** 2591 * Dirty rect width. 2592 */ 2593 uint16_t width; 2594 2595 /** 2596 * Dirty rect height. 2597 */ 2598 uint16_t height; 2599 }; 2600 2601 /* static stream state */ 2602 struct dmub_fams2_legacy_stream_static_state { 2603 uint8_t vactive_det_fill_delay_otg_vlines; 2604 uint8_t programming_delay_otg_vlines; 2605 }; //v0 2606 2607 struct dmub_fams2_subvp_stream_static_state { 2608 uint16_t vratio_numerator; 2609 uint16_t vratio_denominator; 2610 uint16_t phantom_vtotal; 2611 uint16_t phantom_vactive; 2612 union { 2613 struct { 2614 uint8_t is_multi_planar : 1; 2615 uint8_t is_yuv420 : 1; 2616 } bits; 2617 uint8_t all; 2618 } config; 2619 uint8_t programming_delay_otg_vlines; 2620 uint8_t prefetch_to_mall_otg_vlines; 2621 uint8_t phantom_otg_inst; 2622 uint8_t phantom_pipe_mask; 2623 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2624 }; //v0 2625 2626 struct dmub_fams2_drr_stream_static_state { 2627 uint16_t nom_stretched_vtotal; 2628 uint8_t programming_delay_otg_vlines; 2629 uint8_t only_stretch_if_required; 2630 uint8_t pad[2]; 2631 }; //v0 2632 2633 struct dmub_fams2_cmd_legacy_stream_static_state { 2634 uint16_t vactive_det_fill_delay_otg_vlines; 2635 uint16_t programming_delay_otg_vlines; 2636 uint32_t disallow_time_us; 2637 }; //v1 2638 2639 struct dmub_fams2_cmd_subvp_stream_static_state { 2640 uint16_t vratio_numerator; 2641 uint16_t vratio_denominator; 2642 uint16_t phantom_vtotal; 2643 uint16_t phantom_vactive; 2644 uint16_t programming_delay_otg_vlines; 2645 uint16_t prefetch_to_mall_otg_vlines; 2646 union { 2647 struct { 2648 uint8_t is_multi_planar : 1; 2649 uint8_t is_yuv420 : 1; 2650 } bits; 2651 uint8_t all; 2652 } config; 2653 uint8_t phantom_otg_inst; 2654 uint8_t phantom_pipe_mask; 2655 uint8_t pad0; 2656 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2657 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2658 }; //v1 2659 2660 struct dmub_fams2_cmd_drr_stream_static_state { 2661 uint16_t nom_stretched_vtotal; 2662 uint16_t programming_delay_otg_vlines; 2663 uint8_t only_stretch_if_required; 2664 uint8_t pad[3]; 2665 }; //v1 2666 2667 union dmub_fams2_stream_static_sub_state { 2668 struct dmub_fams2_legacy_stream_static_state legacy; 2669 struct dmub_fams2_subvp_stream_static_state subvp; 2670 struct dmub_fams2_drr_stream_static_state drr; 2671 }; //v0 2672 2673 union dmub_fams2_cmd_stream_static_sub_state { 2674 COMMON_STREAM_STATIC_SUB_STATE 2675 }; //v1 2676 2677 union dmub_fams2_stream_static_sub_state_v2 { 2678 COMMON_STREAM_STATIC_SUB_STATE 2679 }; //v2 2680 2681 struct dmub_fams2_stream_static_state { 2682 enum fams2_stream_type type; 2683 uint32_t otg_vline_time_ns; 2684 uint32_t otg_vline_time_ticks; 2685 uint16_t htotal; 2686 uint16_t vtotal; // nominal vtotal 2687 uint16_t vblank_start; 2688 uint16_t vblank_end; 2689 uint16_t max_vtotal; 2690 uint16_t allow_start_otg_vline; 2691 uint16_t allow_end_otg_vline; 2692 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2693 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2694 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2695 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2696 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2697 union { 2698 struct { 2699 uint8_t is_drr : 1; // stream is DRR enabled 2700 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2701 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2702 } bits; 2703 uint8_t all; 2704 } config; 2705 uint8_t otg_inst; 2706 uint8_t pipe_mask; // pipe mask for the whole config 2707 uint8_t num_planes; 2708 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2709 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2710 union dmub_fams2_stream_static_sub_state sub_state; 2711 }; //v0 2712 2713 struct dmub_fams2_cmd_stream_static_base_state { 2714 enum fams2_stream_type type; 2715 uint32_t otg_vline_time_ns; 2716 uint32_t otg_vline_time_ticks; 2717 uint16_t htotal; 2718 uint16_t vtotal; // nominal vtotal 2719 uint16_t vblank_start; 2720 uint16_t vblank_end; 2721 uint16_t max_vtotal; 2722 uint16_t allow_start_otg_vline; 2723 uint16_t allow_end_otg_vline; 2724 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2725 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2726 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2727 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2728 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2729 union { 2730 struct { 2731 uint8_t is_drr : 1; // stream is DRR enabled 2732 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2733 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2734 } bits; 2735 uint8_t all; 2736 } config; 2737 uint8_t otg_inst; 2738 uint8_t pipe_mask; // pipe mask for the whole config 2739 uint8_t num_planes; 2740 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2741 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2742 }; //v1 2743 2744 struct dmub_fams2_stream_static_state_v1 { 2745 struct dmub_fams2_cmd_stream_static_base_state base; 2746 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2747 }; //v1 2748 2749 /** 2750 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2751 * p-state request to allow latency 2752 */ 2753 enum dmub_fams2_allow_delay_check_mode { 2754 /* No check for request to allow delay */ 2755 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2756 /* Check for request to allow delay */ 2757 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2758 /* Check for prepare to allow delay */ 2759 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2760 }; 2761 2762 union dmub_fams2_global_feature_config { 2763 struct { 2764 uint32_t enable: 1; 2765 uint32_t enable_ppt_check: 1; 2766 uint32_t enable_stall_recovery: 1; 2767 uint32_t enable_debug: 1; 2768 uint32_t enable_offload_flip: 1; 2769 uint32_t enable_visual_confirm: 1; 2770 uint32_t allow_delay_check_mode: 2; 2771 uint32_t legacy_method_no_fams2 : 1; 2772 uint32_t reserved : 23; 2773 } bits; 2774 uint32_t all; 2775 }; 2776 2777 struct dmub_cmd_fams2_global_config { 2778 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2779 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2780 uint32_t num_streams; 2781 union dmub_fams2_global_feature_config features; 2782 uint32_t recovery_timeout_us; 2783 uint32_t hwfq_flip_programming_delay_us; 2784 uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target 2785 }; 2786 2787 union dmub_cmd_fams2_config { 2788 struct dmub_cmd_fams2_global_config global; 2789 struct dmub_fams2_stream_static_state stream; //v0 2790 union { 2791 struct dmub_fams2_cmd_stream_static_base_state base; 2792 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2793 } stream_v1; //v1 2794 }; 2795 2796 struct dmub_fams2_config_v2 { 2797 struct dmub_cmd_fams2_global_config global; 2798 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2799 }; 2800 2801 /** 2802 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2803 */ 2804 struct dmub_rb_cmd_fams2 { 2805 struct dmub_cmd_header header; 2806 union dmub_cmd_fams2_config config; 2807 }; 2808 2809 /** 2810 * Indirect buffer descriptor 2811 */ 2812 struct dmub_ib_data { 2813 union dmub_addr src; // location of indirect buffer in memory 2814 uint16_t size; // indirect buffer size in bytes 2815 }; 2816 2817 /** 2818 * DMUB rb command definition for commands passed over indirect buffer 2819 */ 2820 struct dmub_rb_cmd_ib { 2821 struct dmub_cmd_header header; 2822 struct dmub_ib_data ib_data; 2823 }; 2824 2825 /** 2826 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2827 */ 2828 enum dmub_cmd_idle_opt_type { 2829 /** 2830 * DCN hardware restore. 2831 */ 2832 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2833 2834 /** 2835 * DCN hardware save. 2836 */ 2837 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2838 2839 /** 2840 * DCN hardware notify idle. 2841 */ 2842 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2843 2844 /** 2845 * DCN hardware notify power state. 2846 */ 2847 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2848 2849 /** 2850 * DCN notify to release HW. 2851 */ 2852 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2853 }; 2854 2855 /** 2856 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2857 */ 2858 struct dmub_rb_cmd_idle_opt_dcn_restore { 2859 struct dmub_cmd_header header; /**< header */ 2860 }; 2861 2862 /** 2863 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2864 */ 2865 struct dmub_dcn_notify_idle_cntl_data { 2866 uint8_t driver_idle; 2867 uint8_t skip_otg_disable; 2868 uint8_t reserved[58]; 2869 }; 2870 2871 /** 2872 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2873 */ 2874 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2875 struct dmub_cmd_header header; /**< header */ 2876 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2877 }; 2878 2879 /** 2880 * enum dmub_idle_opt_dc_power_state - DC power states. 2881 */ 2882 enum dmub_idle_opt_dc_power_state { 2883 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2884 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2885 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2886 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2887 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2888 }; 2889 2890 /** 2891 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2892 */ 2893 struct dmub_idle_opt_set_dc_power_state_data { 2894 uint8_t power_state; /**< power state */ 2895 uint8_t pad[3]; /**< padding */ 2896 }; 2897 2898 /** 2899 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2900 */ 2901 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2902 struct dmub_cmd_header header; /**< header */ 2903 struct dmub_idle_opt_set_dc_power_state_data data; 2904 }; 2905 2906 /** 2907 * struct dmub_clocks - Clock update notification. 2908 */ 2909 struct dmub_clocks { 2910 uint32_t dispclk_khz; /**< dispclk kHz */ 2911 uint32_t dppclk_khz; /**< dppclk kHz */ 2912 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2913 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2914 }; 2915 2916 /** 2917 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2918 */ 2919 enum dmub_cmd_clk_mgr_type { 2920 /** 2921 * Notify DMCUB of clock update. 2922 */ 2923 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2924 }; 2925 2926 /** 2927 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2928 */ 2929 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2930 struct dmub_cmd_header header; /**< header */ 2931 struct dmub_clocks clocks; /**< clock data */ 2932 }; 2933 2934 /** 2935 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2936 */ 2937 struct dmub_cmd_digx_encoder_control_data { 2938 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2939 }; 2940 2941 /** 2942 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2943 */ 2944 struct dmub_rb_cmd_digx_encoder_control { 2945 struct dmub_cmd_header header; /**< header */ 2946 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2947 }; 2948 2949 /** 2950 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2951 */ 2952 struct dmub_cmd_set_pixel_clock_data { 2953 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2954 }; 2955 2956 /** 2957 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2958 */ 2959 struct dmub_rb_cmd_set_pixel_clock { 2960 struct dmub_cmd_header header; /**< header */ 2961 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2962 }; 2963 2964 /** 2965 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2966 */ 2967 struct dmub_cmd_enable_disp_power_gating_data { 2968 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2969 }; 2970 2971 /** 2972 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2973 */ 2974 struct dmub_rb_cmd_enable_disp_power_gating { 2975 struct dmub_cmd_header header; /**< header */ 2976 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2977 }; 2978 2979 /** 2980 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2981 */ 2982 struct dmub_dig_transmitter_control_data_v1_7 { 2983 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2984 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2985 union { 2986 uint8_t digmode; /**< enum atom_encode_mode_def */ 2987 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2988 uint8_t txffe; /**< TxFFE settings for HDMI 2.1 */ 2989 } mode_laneset; 2990 uint8_t lanenum; /**< Number of lanes */ 2991 union { 2992 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2993 uint32_t symclk_Hz; /**< Symbol clock in Hz for FRL */ 2994 } symclk_units; 2995 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2996 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2997 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2998 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2999 uint8_t TxFFELaneSel; /**< TxFFE lane select [3:0] 3000 (bit0: lane0, bit1: lane1, bit2: lane3, bit3: lane3) */ 3001 uint8_t skip_phy_ssc_reduction; 3002 uint8_t reserved2[2]; /**< For future use */ 3003 uint32_t reserved3[11]; /**< For future use */ 3004 }; 3005 3006 /** 3007 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 3008 */ 3009 union dmub_cmd_dig1_transmitter_control_data { 3010 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 3011 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 3012 }; 3013 3014 /** 3015 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 3016 */ 3017 struct dmub_rb_cmd_dig1_transmitter_control { 3018 struct dmub_cmd_header header; /**< header */ 3019 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 3020 }; 3021 3022 /** 3023 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 3024 */ 3025 struct dmub_rb_cmd_domain_control_data { 3026 uint8_t inst : 6; /**< DOMAIN instance to control */ 3027 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 3028 uint8_t reserved[3]; /**< Reserved for future use */ 3029 }; 3030 3031 /** 3032 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 3033 */ 3034 struct dmub_rb_cmd_domain_control { 3035 struct dmub_cmd_header header; /**< header */ 3036 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 3037 }; 3038 3039 /** 3040 * DPIA tunnel command parameters. 3041 */ 3042 struct dmub_cmd_dig_dpia_control_data { 3043 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 3044 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 3045 union { 3046 uint8_t digmode; /** enum atom_encode_mode_def */ 3047 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 3048 } mode_laneset; 3049 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 3050 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 3051 uint8_t hpdsel; /** =0: HPD is not assigned */ 3052 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 3053 uint8_t dpia_id; /** Index of DPIA */ 3054 uint8_t fec_rdy : 1; 3055 uint8_t reserved : 7; 3056 uint32_t reserved1; 3057 }; 3058 3059 /** 3060 * DMUB command for DPIA tunnel control. 3061 */ 3062 struct dmub_rb_cmd_dig1_dpia_control { 3063 struct dmub_cmd_header header; 3064 struct dmub_cmd_dig_dpia_control_data dpia_control; 3065 }; 3066 3067 /** 3068 * SET_CONFIG Command Payload (deprecated) 3069 */ 3070 struct set_config_cmd_payload { 3071 uint8_t msg_type; /* set config message type */ 3072 uint8_t msg_data; /* set config message data */ 3073 }; 3074 3075 /** 3076 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 3077 */ 3078 struct dmub_cmd_set_config_control_data { 3079 struct set_config_cmd_payload cmd_pkt; 3080 uint8_t instance; /* DPIA instance */ 3081 uint8_t immed_status; /* Immediate status returned in case of error */ 3082 }; 3083 3084 /** 3085 * SET_CONFIG Request Command Payload 3086 */ 3087 struct set_config_request_cmd_payload { 3088 uint8_t instance; /* DPIA instance */ 3089 uint8_t immed_status; /* Immediate status returned in case of error */ 3090 uint8_t msg_type; /* set config message type */ 3091 uint8_t reserved; 3092 uint32_t msg_data; /* set config message data */ 3093 }; 3094 3095 /** 3096 * DMUB command structure for SET_CONFIG command. 3097 */ 3098 struct dmub_rb_cmd_set_config_access { 3099 struct dmub_cmd_header header; /* header */ 3100 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 3101 }; 3102 3103 /** 3104 * DMUB command structure for SET_CONFIG request command. 3105 */ 3106 struct dmub_rb_cmd_set_config_request { 3107 struct dmub_cmd_header header; /* header */ 3108 struct set_config_request_cmd_payload payload; /* set config request payload */ 3109 }; 3110 3111 /** 3112 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3113 */ 3114 struct dmub_cmd_mst_alloc_slots_control_data { 3115 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 3116 uint8_t instance; /* DPIA instance */ 3117 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 3118 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 3119 }; 3120 3121 /** 3122 * DMUB command structure for SET_ command. 3123 */ 3124 struct dmub_rb_cmd_set_mst_alloc_slots { 3125 struct dmub_cmd_header header; /* header */ 3126 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 3127 }; 3128 3129 /** 3130 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 3131 */ 3132 struct dmub_cmd_tps_notification_data { 3133 uint8_t instance; /* DPIA instance */ 3134 uint8_t tps; /* requested training pattern */ 3135 uint8_t reserved1; 3136 uint8_t reserved2; 3137 }; 3138 3139 /** 3140 * DMUB command structure for SET_TPS_NOTIFICATION command. 3141 */ 3142 struct dmub_rb_cmd_set_tps_notification { 3143 struct dmub_cmd_header header; /* header */ 3144 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 3145 }; 3146 3147 /** 3148 * DMUB command structure for DPIA HPD int enable control. 3149 */ 3150 struct dmub_rb_cmd_dpia_hpd_int_enable { 3151 struct dmub_cmd_header header; /* header */ 3152 uint32_t enable; /* dpia hpd interrupt enable */ 3153 }; 3154 3155 /** 3156 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 3157 */ 3158 struct dmub_rb_cmd_dpphy_init { 3159 struct dmub_cmd_header header; /**< header */ 3160 uint8_t reserved[60]; /**< reserved bits */ 3161 }; 3162 3163 /** 3164 * enum dp_aux_request_action - DP AUX request command listing. 3165 * 3166 * 4 AUX request command bits are shifted to high nibble. 3167 */ 3168 enum dp_aux_request_action { 3169 /** I2C-over-AUX write request */ 3170 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 3171 /** I2C-over-AUX read request */ 3172 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 3173 /** I2C-over-AUX write status request */ 3174 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 3175 /** I2C-over-AUX write request with MOT=1 */ 3176 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 3177 /** I2C-over-AUX read request with MOT=1 */ 3178 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 3179 /** I2C-over-AUX write status request with MOT=1 */ 3180 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 3181 /** Native AUX write request */ 3182 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 3183 /** Native AUX read request */ 3184 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 3185 }; 3186 3187 /** 3188 * enum aux_return_code_type - DP AUX process return code listing. 3189 */ 3190 enum aux_return_code_type { 3191 /** AUX process succeeded */ 3192 AUX_RET_SUCCESS = 0, 3193 /** AUX process failed with unknown reason */ 3194 AUX_RET_ERROR_UNKNOWN, 3195 /** AUX process completed with invalid reply */ 3196 AUX_RET_ERROR_INVALID_REPLY, 3197 /** AUX process timed out */ 3198 AUX_RET_ERROR_TIMEOUT, 3199 /** HPD was low during AUX process */ 3200 AUX_RET_ERROR_HPD_DISCON, 3201 /** Failed to acquire AUX engine */ 3202 AUX_RET_ERROR_ENGINE_ACQUIRE, 3203 /** AUX request not supported */ 3204 AUX_RET_ERROR_INVALID_OPERATION, 3205 /** AUX process not available */ 3206 AUX_RET_ERROR_PROTOCOL_ERROR, 3207 }; 3208 3209 /** 3210 * enum aux_channel_type - DP AUX channel type listing. 3211 */ 3212 enum aux_channel_type { 3213 /** AUX thru Legacy DP AUX */ 3214 AUX_CHANNEL_LEGACY_DDC, 3215 /** AUX thru DPIA DP tunneling */ 3216 AUX_CHANNEL_DPIA 3217 }; 3218 3219 /** 3220 * struct aux_transaction_parameters - DP AUX request transaction data 3221 */ 3222 struct aux_transaction_parameters { 3223 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 3224 uint8_t action; /**< enum dp_aux_request_action */ 3225 uint8_t length; /**< DP AUX request data length */ 3226 uint8_t reserved; /**< For future use */ 3227 uint32_t address; /**< DP AUX address */ 3228 uint8_t data[16]; /**< DP AUX write data */ 3229 }; 3230 3231 /** 3232 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3233 */ 3234 struct dmub_cmd_dp_aux_control_data { 3235 uint8_t instance; /**< AUX instance or DPIA instance */ 3236 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 3237 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 3238 uint8_t reserved0; /**< For future use */ 3239 uint16_t timeout; /**< timeout time in us */ 3240 uint16_t reserved1; /**< For future use */ 3241 enum aux_channel_type type; /**< enum aux_channel_type */ 3242 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 3243 }; 3244 3245 /** 3246 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3247 */ 3248 struct dmub_rb_cmd_dp_aux_access { 3249 /** 3250 * Command header. 3251 */ 3252 struct dmub_cmd_header header; 3253 /** 3254 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3255 */ 3256 struct dmub_cmd_dp_aux_control_data aux_control; 3257 }; 3258 3259 /** 3260 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3261 */ 3262 struct dmub_rb_cmd_outbox1_enable { 3263 /** 3264 * Command header. 3265 */ 3266 struct dmub_cmd_header header; 3267 /** 3268 * enable: 0x0 -> disable outbox1 notification (default value) 3269 * 0x1 -> enable outbox1 notification 3270 */ 3271 uint32_t enable; 3272 }; 3273 3274 /* DP AUX Reply command - OutBox Cmd */ 3275 /** 3276 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3277 */ 3278 struct aux_reply_data { 3279 /** 3280 * Aux cmd 3281 */ 3282 uint8_t command; 3283 /** 3284 * Aux reply data length (max: 16 bytes) 3285 */ 3286 uint8_t length; 3287 /** 3288 * Alignment only 3289 */ 3290 uint8_t pad[2]; 3291 /** 3292 * Aux reply data 3293 */ 3294 uint8_t data[16]; 3295 }; 3296 3297 /** 3298 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3299 */ 3300 struct aux_reply_control_data { 3301 /** 3302 * Reserved for future use 3303 */ 3304 uint32_t handle; 3305 /** 3306 * Aux Instance 3307 */ 3308 uint8_t instance; 3309 /** 3310 * Aux transaction result: definition in enum aux_return_code_type 3311 */ 3312 uint8_t result; 3313 /** 3314 * Alignment only 3315 */ 3316 uint16_t pad; 3317 }; 3318 3319 /** 3320 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 3321 */ 3322 struct dmub_rb_cmd_dp_aux_reply { 3323 /** 3324 * Command header. 3325 */ 3326 struct dmub_cmd_header header; 3327 /** 3328 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3329 */ 3330 struct aux_reply_control_data control; 3331 /** 3332 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3333 */ 3334 struct aux_reply_data reply_data; 3335 }; 3336 3337 /* DP HPD Notify command - OutBox Cmd */ 3338 /** 3339 * DP HPD Type 3340 */ 3341 enum dp_hpd_type { 3342 /** 3343 * Normal DP HPD 3344 */ 3345 DP_HPD = 0, 3346 /** 3347 * DP HPD short pulse 3348 */ 3349 DP_IRQ = 1, 3350 /** 3351 * Failure to acquire DP HPD state 3352 */ 3353 DP_NONE_HPD = 2 3354 }; 3355 3356 /** 3357 * DP HPD Status 3358 */ 3359 enum dp_hpd_status { 3360 /** 3361 * DP_HPD status low 3362 */ 3363 DP_HPD_UNPLUG = 0, 3364 /** 3365 * DP_HPD status high 3366 */ 3367 DP_HPD_PLUG 3368 }; 3369 3370 /** 3371 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3372 */ 3373 struct dp_hpd_data { 3374 /** 3375 * DP HPD instance 3376 */ 3377 uint8_t instance; 3378 /** 3379 * HPD type 3380 */ 3381 uint8_t hpd_type; 3382 /** 3383 * HPD status: only for type: DP_HPD to indicate status 3384 */ 3385 uint8_t hpd_status; 3386 /** 3387 * Alignment only 3388 */ 3389 uint8_t pad; 3390 }; 3391 3392 /** 3393 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3394 */ 3395 struct dmub_rb_cmd_dp_hpd_notify { 3396 /** 3397 * Command header. 3398 */ 3399 struct dmub_cmd_header header; 3400 /** 3401 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3402 */ 3403 struct dp_hpd_data hpd_data; 3404 }; 3405 3406 /** 3407 * Definition of a SET_CONFIG reply from DPOA. 3408 */ 3409 enum set_config_status { 3410 SET_CONFIG_PENDING = 0, 3411 SET_CONFIG_ACK_RECEIVED, 3412 SET_CONFIG_RX_TIMEOUT, 3413 SET_CONFIG_UNKNOWN_ERROR, 3414 }; 3415 3416 /** 3417 * Definition of a set_config reply 3418 */ 3419 struct set_config_reply_control_data { 3420 uint8_t instance; /* DPIA Instance */ 3421 uint8_t status; /* Set Config reply */ 3422 uint16_t pad; /* Alignment */ 3423 }; 3424 3425 /** 3426 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 3427 */ 3428 struct dmub_rb_cmd_dp_set_config_reply { 3429 struct dmub_cmd_header header; 3430 struct set_config_reply_control_data set_config_reply_control; 3431 }; 3432 3433 /** 3434 * Definition of a DPIA notification header 3435 */ 3436 struct dpia_notification_header { 3437 uint8_t instance; /**< DPIA Instance */ 3438 uint8_t reserved[3]; 3439 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 3440 }; 3441 3442 /** 3443 * Definition of the common data struct of DPIA notification 3444 */ 3445 struct dpia_notification_common { 3446 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 3447 - sizeof(struct dpia_notification_header)]; 3448 }; 3449 3450 /** 3451 * Definition of a DPIA notification data 3452 */ 3453 struct dpia_bw_allocation_notify_data { 3454 union { 3455 struct { 3456 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3457 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3458 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3459 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3460 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3461 uint16_t reserved: 11; /**< Reserved */ 3462 } bits; 3463 3464 uint16_t flags; 3465 }; 3466 3467 uint8_t cm_id; /**< CM ID */ 3468 uint8_t group_id; /**< Group ID */ 3469 uint8_t granularity; /**< BW Allocation Granularity */ 3470 uint8_t estimated_bw; /**< Estimated_BW */ 3471 uint8_t allocated_bw; /**< Allocated_BW */ 3472 uint8_t reserved; 3473 }; 3474 3475 /** 3476 * union dpia_notify_data_type - DPIA Notification in Outbox command 3477 */ 3478 union dpia_notification_data { 3479 /** 3480 * DPIA Notification for common data struct 3481 */ 3482 struct dpia_notification_common common_data; 3483 3484 /** 3485 * DPIA Notification for DP BW Allocation support 3486 */ 3487 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3488 }; 3489 3490 /** 3491 * Definition of a DPIA notification payload 3492 */ 3493 struct dpia_notification_payload { 3494 struct dpia_notification_header header; 3495 union dpia_notification_data data; /**< DPIA notification payload data */ 3496 }; 3497 3498 /** 3499 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3500 */ 3501 struct dmub_rb_cmd_dpia_notification { 3502 struct dmub_cmd_header header; /**< DPIA notification header */ 3503 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3504 }; 3505 3506 /** 3507 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3508 */ 3509 struct dmub_cmd_hpd_state_query_data { 3510 uint8_t instance; /**< HPD instance or DPIA instance */ 3511 uint8_t result; /**< For returning HPD state */ 3512 uint16_t pad; /** < Alignment */ 3513 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3514 enum aux_return_code_type status; /**< for returning the status of command */ 3515 }; 3516 3517 /** 3518 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3519 */ 3520 struct dmub_rb_cmd_query_hpd_state { 3521 /** 3522 * Command header. 3523 */ 3524 struct dmub_cmd_header header; 3525 /** 3526 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3527 */ 3528 struct dmub_cmd_hpd_state_query_data data; 3529 }; 3530 3531 /** 3532 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3533 */ 3534 struct dmub_rb_cmd_hpd_sense_notify_data { 3535 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3536 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3537 }; 3538 3539 /** 3540 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3541 */ 3542 struct dmub_rb_cmd_hpd_sense_notify { 3543 struct dmub_cmd_header header; /**< header */ 3544 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3545 }; 3546 3547 /* 3548 * Command IDs should be treated as stable ABI. 3549 * Do not reuse or modify IDs. 3550 */ 3551 3552 /** 3553 * PSR command sub-types. 3554 */ 3555 enum dmub_cmd_psr_type { 3556 /** 3557 * Set PSR version support. 3558 */ 3559 DMUB_CMD__PSR_SET_VERSION = 0, 3560 /** 3561 * Copy driver-calculated parameters to PSR state. 3562 */ 3563 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3564 /** 3565 * Enable PSR. 3566 */ 3567 DMUB_CMD__PSR_ENABLE = 2, 3568 3569 /** 3570 * Disable PSR. 3571 */ 3572 DMUB_CMD__PSR_DISABLE = 3, 3573 3574 /** 3575 * Set PSR level. 3576 * PSR level is a 16-bit value dicated by driver that 3577 * will enable/disable different functionality. 3578 */ 3579 DMUB_CMD__PSR_SET_LEVEL = 4, 3580 3581 /** 3582 * Forces PSR enabled until an explicit PSR disable call. 3583 */ 3584 DMUB_CMD__PSR_FORCE_STATIC = 5, 3585 /** 3586 * Set vtotal in psr active for FreeSync PSR. 3587 */ 3588 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3589 /** 3590 * Set PSR power option 3591 */ 3592 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3593 }; 3594 3595 /** 3596 * Different PSR residency modes. 3597 * Different modes change the definition of PSR residency. 3598 */ 3599 enum psr_residency_mode { 3600 PSR_RESIDENCY_MODE_PHY = 0, 3601 PSR_RESIDENCY_MODE_ALPM, 3602 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3603 /* Do not add below. */ 3604 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3605 }; 3606 3607 enum dmub_cmd_fams_type { 3608 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3609 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3610 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3611 /** 3612 * For SubVP set manual trigger in FW because it 3613 * triggers DRR_UPDATE_PENDING which SubVP relies 3614 * on (for any SubVP cases that use a DRR display) 3615 */ 3616 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3617 DMUB_CMD__FAMS2_CONFIG = 4, 3618 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3619 DMUB_CMD__FAMS2_FLIP = 6, 3620 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3621 DMUB_CMD__FAMS2_IB_DEBUG_META = 8, 3622 }; 3623 3624 /** 3625 * PSR versions. 3626 */ 3627 enum psr_version { 3628 /** 3629 * PSR version 1. 3630 */ 3631 PSR_VERSION_1 = 0, 3632 /** 3633 * Freesync PSR SU. 3634 */ 3635 PSR_VERSION_SU_1 = 1, 3636 /** 3637 * PSR not supported. 3638 */ 3639 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3640 }; 3641 3642 /** 3643 * PHY Link rate for DP. 3644 */ 3645 enum phy_link_rate { 3646 /** 3647 * not supported. 3648 */ 3649 PHY_RATE_UNKNOWN = 0, 3650 /** 3651 * Rate_1 (RBR) - 1.62 Gbps/Lane 3652 */ 3653 PHY_RATE_162 = 1, 3654 /** 3655 * Rate_2 - 2.16 Gbps/Lane 3656 */ 3657 PHY_RATE_216 = 2, 3658 /** 3659 * Rate_3 - 2.43 Gbps/Lane 3660 */ 3661 PHY_RATE_243 = 3, 3662 /** 3663 * Rate_4 (HBR) - 2.70 Gbps/Lane 3664 */ 3665 PHY_RATE_270 = 4, 3666 /** 3667 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3668 */ 3669 PHY_RATE_324 = 5, 3670 /** 3671 * Rate_6 - 4.32 Gbps/Lane 3672 */ 3673 PHY_RATE_432 = 6, 3674 /** 3675 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3676 */ 3677 PHY_RATE_540 = 7, 3678 /** 3679 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3680 */ 3681 PHY_RATE_810 = 8, 3682 /** 3683 * UHBR10 - 10.0 Gbps/Lane 3684 */ 3685 PHY_RATE_1000 = 9, 3686 /** 3687 * UHBR13.5 - 13.5 Gbps/Lane 3688 */ 3689 PHY_RATE_1350 = 10, 3690 /** 3691 * UHBR10 - 20.0 Gbps/Lane 3692 */ 3693 PHY_RATE_2000 = 11, 3694 3695 PHY_RATE_675 = 12, 3696 /** 3697 * Rate 12 - 6.75 Gbps/Lane 3698 */ 3699 }; 3700 3701 /** 3702 * enum dmub_phy_fsm_state - PHY FSM states. 3703 * PHY FSM state to transit to during PSR enable/disable. 3704 */ 3705 enum dmub_phy_fsm_state { 3706 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3707 DMUB_PHY_FSM_RESET, 3708 DMUB_PHY_FSM_RESET_RELEASED, 3709 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3710 DMUB_PHY_FSM_INITIALIZED, 3711 DMUB_PHY_FSM_CALIBRATED, 3712 DMUB_PHY_FSM_CALIBRATED_LP, 3713 DMUB_PHY_FSM_CALIBRATED_PG, 3714 DMUB_PHY_FSM_POWER_DOWN, 3715 DMUB_PHY_FSM_PLL_EN, 3716 DMUB_PHY_FSM_TX_EN, 3717 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3718 DMUB_PHY_FSM_FAST_LP, 3719 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3720 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3721 DMUB_PHY_FSM_P2_PLL_OFF, 3722 DMUB_PHY_FSM_P2_PLL_ON, 3723 }; 3724 3725 /** 3726 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3727 */ 3728 struct dmub_cmd_psr_copy_settings_data { 3729 /** 3730 * Flags that can be set by driver to change some PSR behaviour. 3731 */ 3732 union dmub_psr_debug_flags debug; 3733 /** 3734 * 16-bit value dicated by driver that will enable/disable different functionality. 3735 */ 3736 uint16_t psr_level; 3737 /** 3738 * DPP HW instance. 3739 */ 3740 uint8_t dpp_inst; 3741 /** 3742 * MPCC HW instance. 3743 * Not used in dmub fw, 3744 * dmub fw will get active opp by reading odm registers. 3745 */ 3746 uint8_t mpcc_inst; 3747 /** 3748 * OPP HW instance. 3749 * Not used in dmub fw, 3750 * dmub fw will get active opp by reading odm registers. 3751 */ 3752 uint8_t opp_inst; 3753 /** 3754 * OTG HW instance. 3755 */ 3756 uint8_t otg_inst; 3757 /** 3758 * DIG FE HW instance. 3759 */ 3760 uint8_t digfe_inst; 3761 /** 3762 * DIG BE HW instance. 3763 */ 3764 uint8_t digbe_inst; 3765 /** 3766 * DP PHY HW instance. 3767 */ 3768 uint8_t dpphy_inst; 3769 /** 3770 * AUX HW instance. 3771 */ 3772 uint8_t aux_inst; 3773 /** 3774 * Determines if SMU optimzations are enabled/disabled. 3775 */ 3776 uint8_t smu_optimizations_en; 3777 /** 3778 * Unused. 3779 * TODO: Remove. 3780 */ 3781 uint8_t frame_delay; 3782 /** 3783 * If RFB setup time is greater than the total VBLANK time, 3784 * it is not possible for the sink to capture the video frame 3785 * in the same frame the SDP is sent. In this case, 3786 * the frame capture indication bit should be set and an extra 3787 * static frame should be transmitted to the sink. 3788 */ 3789 uint8_t frame_cap_ind; 3790 /** 3791 * Granularity of Y offset supported by sink. 3792 */ 3793 uint8_t su_y_granularity; 3794 /** 3795 * Indicates whether sink should start capturing 3796 * immediately following active scan line, 3797 * or starting with the 2nd active scan line. 3798 */ 3799 uint8_t line_capture_indication; 3800 /** 3801 * Multi-display optimizations are implemented on certain ASICs. 3802 */ 3803 uint8_t multi_disp_optimizations_en; 3804 /** 3805 * The last possible line SDP may be transmitted without violating 3806 * the RFB setup time or entering the active video frame. 3807 */ 3808 uint16_t init_sdp_deadline; 3809 /** 3810 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3811 */ 3812 uint8_t rate_control_caps; 3813 /* 3814 * Force PSRSU always doing full frame update 3815 */ 3816 uint8_t force_ffu_mode; 3817 /** 3818 * Length of each horizontal line in us. 3819 */ 3820 uint32_t line_time_in_us; 3821 /** 3822 * FEC enable status in driver 3823 */ 3824 uint8_t fec_enable_status; 3825 /** 3826 * FEC re-enable delay when PSR exit. 3827 * unit is 100us, range form 0~255(0xFF). 3828 */ 3829 uint8_t fec_enable_delay_in100us; 3830 /** 3831 * PSR control version. 3832 */ 3833 uint8_t cmd_version; 3834 /** 3835 * Panel Instance. 3836 * Panel instance to identify which psr_state to use 3837 * Currently the support is only for 0 or 1 3838 */ 3839 uint8_t panel_inst; 3840 /* 3841 * DSC enable status in driver 3842 */ 3843 uint8_t dsc_enable_status; 3844 /* 3845 * Use FSM state for PSR power up/down 3846 */ 3847 uint8_t use_phy_fsm; 3848 /** 3849 * frame delay for frame re-lock 3850 */ 3851 uint8_t relock_delay_frame_cnt; 3852 /** 3853 * esd recovery indicate. 3854 */ 3855 uint8_t esd_recovery; 3856 /** 3857 * DSC Slice height. 3858 */ 3859 uint16_t dsc_slice_height; 3860 /** 3861 * Some panels request main link off before xth vertical line 3862 */ 3863 uint16_t poweroff_before_vertical_line; 3864 /** 3865 * Some panels cannot handle idle pattern during PSR entry. 3866 * To power down phy before disable stream to avoid sending 3867 * idle pattern. 3868 */ 3869 uint8_t power_down_phy_before_disable_stream; 3870 }; 3871 3872 /** 3873 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3874 */ 3875 struct dmub_rb_cmd_psr_copy_settings { 3876 /** 3877 * Command header. 3878 */ 3879 struct dmub_cmd_header header; 3880 /** 3881 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3882 */ 3883 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3884 }; 3885 3886 /** 3887 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3888 */ 3889 struct dmub_cmd_psr_set_level_data { 3890 /** 3891 * 16-bit value dicated by driver that will enable/disable different functionality. 3892 */ 3893 uint16_t psr_level; 3894 /** 3895 * PSR control version. 3896 */ 3897 uint8_t cmd_version; 3898 /** 3899 * Panel Instance. 3900 * Panel instance to identify which psr_state to use 3901 * Currently the support is only for 0 or 1 3902 */ 3903 uint8_t panel_inst; 3904 }; 3905 3906 /** 3907 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3908 */ 3909 struct dmub_rb_cmd_psr_set_level { 3910 /** 3911 * Command header. 3912 */ 3913 struct dmub_cmd_header header; 3914 /** 3915 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3916 */ 3917 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3918 }; 3919 3920 struct dmub_rb_cmd_psr_enable_data { 3921 /** 3922 * PSR control version. 3923 */ 3924 uint8_t cmd_version; 3925 /** 3926 * Panel Instance. 3927 * Panel instance to identify which psr_state to use 3928 * Currently the support is only for 0 or 1 3929 */ 3930 uint8_t panel_inst; 3931 /** 3932 * Phy state to enter. 3933 * Values to use are defined in dmub_phy_fsm_state 3934 */ 3935 uint8_t phy_fsm_state; 3936 /** 3937 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3938 * Set this using enum phy_link_rate. 3939 * This does not support HDMI/DP2 for now. 3940 */ 3941 uint8_t phy_rate; 3942 }; 3943 3944 /** 3945 * Definition of a DMUB_CMD__PSR_ENABLE command. 3946 * PSR enable/disable is controlled using the sub_type. 3947 */ 3948 struct dmub_rb_cmd_psr_enable { 3949 /** 3950 * Command header. 3951 */ 3952 struct dmub_cmd_header header; 3953 3954 struct dmub_rb_cmd_psr_enable_data data; 3955 }; 3956 3957 /** 3958 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3959 */ 3960 struct dmub_cmd_psr_set_version_data { 3961 /** 3962 * PSR version that FW should implement. 3963 */ 3964 enum psr_version version; 3965 /** 3966 * PSR control version. 3967 */ 3968 uint8_t cmd_version; 3969 /** 3970 * Panel Instance. 3971 * Panel instance to identify which psr_state to use 3972 * Currently the support is only for 0 or 1 3973 */ 3974 uint8_t panel_inst; 3975 /** 3976 * Explicit padding to 4 byte boundary. 3977 */ 3978 uint8_t pad[2]; 3979 }; 3980 3981 /** 3982 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3983 */ 3984 struct dmub_rb_cmd_psr_set_version { 3985 /** 3986 * Command header. 3987 */ 3988 struct dmub_cmd_header header; 3989 /** 3990 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3991 */ 3992 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3993 }; 3994 3995 struct dmub_cmd_psr_force_static_data { 3996 /** 3997 * PSR control version. 3998 */ 3999 uint8_t cmd_version; 4000 /** 4001 * Panel Instance. 4002 * Panel instance to identify which psr_state to use 4003 * Currently the support is only for 0 or 1 4004 */ 4005 uint8_t panel_inst; 4006 /** 4007 * Explicit padding to 4 byte boundary. 4008 */ 4009 uint8_t pad[2]; 4010 }; 4011 4012 /** 4013 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 4014 */ 4015 struct dmub_rb_cmd_psr_force_static { 4016 /** 4017 * Command header. 4018 */ 4019 struct dmub_cmd_header header; 4020 /** 4021 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 4022 */ 4023 struct dmub_cmd_psr_force_static_data psr_force_static_data; 4024 }; 4025 4026 /** 4027 * PSR SU debug flags. 4028 */ 4029 union dmub_psr_su_debug_flags { 4030 /** 4031 * PSR SU debug flags. 4032 */ 4033 struct { 4034 /** 4035 * Update dirty rect in SW only. 4036 */ 4037 uint8_t update_dirty_rect_only : 1; 4038 /** 4039 * Reset the cursor/plane state before processing the call. 4040 */ 4041 uint8_t reset_state : 1; 4042 } bitfields; 4043 4044 /** 4045 * Union for debug flags. 4046 */ 4047 uint32_t u32All; 4048 }; 4049 4050 /** 4051 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 4052 * This triggers a selective update for PSR SU. 4053 */ 4054 struct dmub_cmd_update_dirty_rect_data { 4055 /** 4056 * Dirty rects from OS. 4057 */ 4058 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 4059 /** 4060 * PSR SU debug flags. 4061 */ 4062 union dmub_psr_su_debug_flags debug_flags; 4063 /** 4064 * Pipe index. 4065 */ 4066 uint8_t pipe_idx; 4067 /** 4068 * Number of dirty rects. 4069 */ 4070 uint8_t dirty_rect_count; 4071 /** 4072 * dirty rects cmd version. 4073 */ 4074 uint8_t cmd_version; 4075 /** 4076 * Panel Instance. 4077 * Panel instance to identify which psr_state to use 4078 * Currently the support is only for 0 or 1 4079 */ 4080 uint8_t panel_inst; 4081 /** 4082 * OTG HW instance 4083 */ 4084 uint8_t otg_inst; 4085 /** 4086 * Padding for 4 byte alignment 4087 */ 4088 uint8_t padding[3]; 4089 }; 4090 4091 /** 4092 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 4093 */ 4094 struct dmub_rb_cmd_update_dirty_rect { 4095 /** 4096 * Command header. 4097 */ 4098 struct dmub_cmd_header header; 4099 /** 4100 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 4101 */ 4102 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 4103 }; 4104 4105 /** 4106 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 4107 */ 4108 union dmub_reg_cursor_control_cfg { 4109 struct { 4110 uint32_t cur_enable: 1; 4111 uint32_t reser0: 3; 4112 uint32_t cur_2x_magnify: 1; 4113 uint32_t reser1: 3; 4114 uint32_t mode: 3; 4115 uint32_t reser2: 5; 4116 uint32_t pitch: 2; 4117 uint32_t reser3: 6; 4118 uint32_t line_per_chunk: 5; 4119 uint32_t reser4: 3; 4120 } bits; 4121 uint32_t raw; 4122 }; 4123 struct dmub_cursor_position_cache_hubp { 4124 union dmub_reg_cursor_control_cfg cur_ctl; 4125 union dmub_reg_position_cfg { 4126 struct { 4127 uint32_t cur_x_pos: 16; 4128 uint32_t cur_y_pos: 16; 4129 } bits; 4130 uint32_t raw; 4131 } position; 4132 union dmub_reg_hot_spot_cfg { 4133 struct { 4134 uint32_t hot_x: 16; 4135 uint32_t hot_y: 16; 4136 } bits; 4137 uint32_t raw; 4138 } hot_spot; 4139 union dmub_reg_dst_offset_cfg { 4140 struct { 4141 uint32_t dst_x_offset: 13; 4142 uint32_t reserved: 19; 4143 } bits; 4144 uint32_t raw; 4145 } dst_offset; 4146 }; 4147 4148 union dmub_reg_cur0_control_cfg { 4149 struct { 4150 uint32_t cur0_enable: 1; 4151 uint32_t expansion_mode: 1; 4152 uint32_t reser0: 1; 4153 uint32_t cur0_rom_en: 1; 4154 uint32_t mode: 3; 4155 uint32_t reserved: 25; 4156 } bits; 4157 uint32_t raw; 4158 }; 4159 struct dmub_cursor_position_cache_dpp { 4160 union dmub_reg_cur0_control_cfg cur0_ctl; 4161 }; 4162 struct dmub_cursor_position_cfg { 4163 struct dmub_cursor_position_cache_hubp pHubp; 4164 struct dmub_cursor_position_cache_dpp pDpp; 4165 uint8_t pipe_idx; 4166 /* 4167 * Padding is required. To be 4 Bytes Aligned. 4168 */ 4169 uint8_t padding[3]; 4170 }; 4171 4172 struct dmub_cursor_attribute_cache_hubp { 4173 uint32_t SURFACE_ADDR_HIGH; 4174 uint32_t SURFACE_ADDR; 4175 union dmub_reg_cursor_control_cfg cur_ctl; 4176 union dmub_reg_cursor_size_cfg { 4177 struct { 4178 uint32_t width: 16; 4179 uint32_t height: 16; 4180 } bits; 4181 uint32_t raw; 4182 } size; 4183 union dmub_reg_cursor_settings_cfg { 4184 struct { 4185 uint32_t dst_y_offset: 8; 4186 uint32_t chunk_hdl_adjust: 2; 4187 uint32_t reserved: 22; 4188 } bits; 4189 uint32_t raw; 4190 } settings; 4191 }; 4192 struct dmub_cursor_attribute_cache_dpp { 4193 union dmub_reg_cur0_control_cfg cur0_ctl; 4194 }; 4195 struct dmub_cursor_attributes_cfg { 4196 struct dmub_cursor_attribute_cache_hubp aHubp; 4197 struct dmub_cursor_attribute_cache_dpp aDpp; 4198 }; 4199 4200 struct dmub_cmd_update_cursor_payload0 { 4201 /** 4202 * Cursor dirty rects. 4203 */ 4204 struct dmub_rect cursor_rect; 4205 /** 4206 * PSR SU debug flags. 4207 */ 4208 union dmub_psr_su_debug_flags debug_flags; 4209 /** 4210 * Cursor enable/disable. 4211 */ 4212 uint8_t enable; 4213 /** 4214 * Pipe index. 4215 */ 4216 uint8_t pipe_idx; 4217 /** 4218 * Cursor update cmd version. 4219 */ 4220 uint8_t cmd_version; 4221 /** 4222 * Panel Instance. 4223 * Panel instance to identify which psr_state to use 4224 * Currently the support is only for 0 or 1 4225 */ 4226 uint8_t panel_inst; 4227 /** 4228 * Cursor Position Register. 4229 * Registers contains Hubp & Dpp modules 4230 */ 4231 struct dmub_cursor_position_cfg position_cfg; 4232 /** 4233 * OTG HW instance 4234 */ 4235 uint8_t otg_inst; 4236 /** 4237 * Padding for 4 byte alignment 4238 */ 4239 uint8_t padding[3]; 4240 }; 4241 4242 struct dmub_cmd_update_cursor_payload1 { 4243 struct dmub_cursor_attributes_cfg attribute_cfg; 4244 }; 4245 4246 union dmub_cmd_update_cursor_info_data { 4247 struct dmub_cmd_update_cursor_payload0 payload0; 4248 struct dmub_cmd_update_cursor_payload1 payload1; 4249 }; 4250 /** 4251 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4252 */ 4253 struct dmub_rb_cmd_update_cursor_info { 4254 /** 4255 * Command header. 4256 */ 4257 struct dmub_cmd_header header; 4258 /** 4259 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 4260 */ 4261 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 4262 }; 4263 4264 /** 4265 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4266 */ 4267 struct dmub_cmd_psr_set_vtotal_data { 4268 /** 4269 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 4270 */ 4271 uint16_t psr_vtotal_idle; 4272 /** 4273 * PSR control version. 4274 */ 4275 uint8_t cmd_version; 4276 /** 4277 * Panel Instance. 4278 * Panel instance to identify which psr_state to use 4279 * Currently the support is only for 0 or 1 4280 */ 4281 uint8_t panel_inst; 4282 /* 4283 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 4284 */ 4285 uint16_t psr_vtotal_su; 4286 /** 4287 * Explicit padding to 4 byte boundary. 4288 */ 4289 uint8_t pad2[2]; 4290 }; 4291 4292 /** 4293 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4294 */ 4295 struct dmub_rb_cmd_psr_set_vtotal { 4296 /** 4297 * Command header. 4298 */ 4299 struct dmub_cmd_header header; 4300 /** 4301 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4302 */ 4303 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 4304 }; 4305 4306 /** 4307 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 4308 */ 4309 struct dmub_cmd_psr_set_power_opt_data { 4310 /** 4311 * PSR control version. 4312 */ 4313 uint8_t cmd_version; 4314 /** 4315 * Panel Instance. 4316 * Panel instance to identify which psr_state to use 4317 * Currently the support is only for 0 or 1 4318 */ 4319 uint8_t panel_inst; 4320 /** 4321 * Explicit padding to 4 byte boundary. 4322 */ 4323 uint8_t pad[2]; 4324 /** 4325 * PSR power option 4326 */ 4327 uint32_t power_opt; 4328 }; 4329 4330 /** 4331 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4332 */ 4333 struct dmub_rb_cmd_psr_set_power_opt { 4334 /** 4335 * Command header. 4336 */ 4337 struct dmub_cmd_header header; 4338 /** 4339 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4340 */ 4341 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 4342 }; 4343 4344 enum dmub_alpm_mode { 4345 ALPM_AUXWAKE = 0, 4346 ALPM_AUXLESS = 1, 4347 ALPM_UNSUPPORTED = 2, 4348 }; 4349 4350 /** 4351 * Definition of Replay Residency GPINT command. 4352 * Bit[0] - Residency mode for Revision 0 4353 * Bit[1] - Enable/Disable state 4354 * Bit[2-3] - Revision number 4355 * Bit[4-7] - Residency mode for Revision 1 4356 * Bit[8] - Panel instance 4357 * Bit[9-15] - Reserved 4358 */ 4359 4360 enum pr_residency_mode { 4361 PR_RESIDENCY_MODE_PHY = 0x0, 4362 PR_RESIDENCY_MODE_ALPM, 4363 PR_RESIDENCY_MODE_IPS2, 4364 PR_RESIDENCY_MODE_FRAME_CNT, 4365 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 4366 }; 4367 4368 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 4369 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 4370 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 4371 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 4372 4373 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4374 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 4375 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4376 4377 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 4378 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 4379 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 4380 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 4381 4382 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4383 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4384 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4385 4386 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 4387 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 4388 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 4389 4390 /** 4391 * Definition of a replay_state. 4392 */ 4393 enum replay_state { 4394 REPLAY_STATE_0 = 0x0, 4395 REPLAY_STATE_1 = 0x10, 4396 REPLAY_STATE_1A = 0x11, 4397 REPLAY_STATE_2 = 0x20, 4398 REPLAY_STATE_2A = 0x21, 4399 REPLAY_STATE_3 = 0x30, 4400 REPLAY_STATE_3INIT = 0x31, 4401 REPLAY_STATE_4 = 0x40, 4402 REPLAY_STATE_4A = 0x41, 4403 REPLAY_STATE_4B = 0x42, 4404 REPLAY_STATE_4C = 0x43, 4405 REPLAY_STATE_4D = 0x44, 4406 REPLAY_STATE_4E = 0x45, 4407 REPLAY_STATE_4B_LOCKED = 0x4A, 4408 REPLAY_STATE_4C_UNLOCKED = 0x4B, 4409 REPLAY_STATE_5 = 0x50, 4410 REPLAY_STATE_5A = 0x51, 4411 REPLAY_STATE_5B = 0x52, 4412 REPLAY_STATE_5A_LOCKED = 0x5A, 4413 REPLAY_STATE_5B_UNLOCKED = 0x5B, 4414 REPLAY_STATE_6 = 0x60, 4415 REPLAY_STATE_6A = 0x61, 4416 REPLAY_STATE_6B = 0x62, 4417 REPLAY_STATE_INVALID = 0xFF, 4418 }; 4419 4420 /** 4421 * Definition of a panel replay state 4422 */ 4423 enum pr_state { 4424 PR_STATE_0 = 0x00, // State 0 steady state 4425 // Pending SDP and Unlock before back to State 0 4426 PR_STATE_0_PENDING_SDP_AND_UNLOCK = 0x01, 4427 PR_STATE_1 = 0x10, // State 1 4428 PR_STATE_2 = 0x20, // State 2 steady state 4429 // Pending frame transmission before transition to State 2 4430 PR_STATE_2_PENDING_FRAME_TRANSMISSION = 0x30, 4431 // Active and Powered Up 4432 PR_STATE_2_POWERED = 0x31, 4433 // Active and Powered Down, but need to blank HUBP after DPG_EN latch 4434 PR_STATE_2_PENDING_HUBP_BLANK = 0x32, 4435 // Active and Pending Power Up 4436 PR_STATE_2_PENDING_POWER_UP = 0x33, 4437 // Active and Powered Up, Pending DPG latch 4438 PR_STATE_2_PENDING_LOCK = 0x34, 4439 // Active and Powered Up, Pending SDP and Unlock 4440 PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35, 4441 // Pending transmission of AS SDP for timing sync, but no rfb update 4442 PR_STATE_2_PENDING_AS_SDP = 0x36, 4443 // Invalid 4444 PR_STATE_INVALID = 0xFF, 4445 }; 4446 4447 /** 4448 * Replay command sub-types. 4449 */ 4450 enum dmub_cmd_replay_type { 4451 /** 4452 * Copy driver-calculated parameters to REPLAY state. 4453 */ 4454 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 4455 /** 4456 * Enable REPLAY. 4457 */ 4458 DMUB_CMD__REPLAY_ENABLE = 1, 4459 /** 4460 * Set Replay power option. 4461 */ 4462 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 4463 /** 4464 * Set coasting vtotal. 4465 */ 4466 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 4467 /** 4468 * Set power opt and coasting vtotal. 4469 */ 4470 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 4471 /** 4472 * Set disabled iiming sync. 4473 */ 4474 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 4475 /** 4476 * Set Residency Frameupdate Timer. 4477 */ 4478 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 4479 /** 4480 * Set pseudo vtotal 4481 */ 4482 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 4483 /** 4484 * Set adaptive sync sdp enabled 4485 */ 4486 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4487 /** 4488 * Set Replay General command. 4489 */ 4490 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4491 }; 4492 4493 /* 4494 * Panel Replay sub-types 4495 */ 4496 enum dmub_cmd_panel_replay_type { 4497 DMUB_CMD__PR_ENABLE = 0, 4498 DMUB_CMD__PR_COPY_SETTINGS = 1, 4499 DMUB_CMD__PR_UPDATE_STATE = 2, 4500 DMUB_CMD__PR_GENERAL_CMD = 3, 4501 }; 4502 4503 enum dmub_cmd_panel_replay_state_update_subtype { 4504 PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, 4505 PR_STATE_UPDATE_SYNC_MODE = 0x2, 4506 PR_STATE_UPDATE_RUNTIME_FLAGS = 0x3, 4507 PR_STATE_UPDATE_PSEUDO_VTOTAL = 0x4, 4508 }; 4509 4510 enum dmub_cmd_panel_replay_general_subtype { 4511 PR_GENERAL_CMD_DEBUG_OPTION = 0x1, 4512 }; 4513 4514 /** 4515 * Replay general command sub-types. 4516 */ 4517 enum dmub_cmd_replay_general_subtype { 4518 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 4519 /** 4520 * TODO: For backward compatible, allow new command only. 4521 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4522 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4523 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4524 */ 4525 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4526 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4527 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4528 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4529 REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, 4530 REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, 4531 REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE, 4532 REPLAY_GENERAL_CMD_LIVE_CAPTURE_WITH_CVT, 4533 }; 4534 4535 struct dmub_alpm_auxless_data { 4536 uint16_t lfps_setup_ns; 4537 uint16_t lfps_period_ns; 4538 uint16_t lfps_silence_ns; 4539 uint16_t lfps_t1_t2_override_us; 4540 short lfps_t1_t2_offset_us; 4541 uint8_t lttpr_count; 4542 /* 4543 * Padding to align structure to 4 byte boundary. 4544 */ 4545 uint8_t pad[1]; 4546 }; 4547 4548 /** 4549 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4550 */ 4551 struct dmub_cmd_replay_copy_settings_data { 4552 /** 4553 * Flags that can be set by driver to change some replay behaviour. 4554 */ 4555 union replay_debug_flags debug; 4556 4557 /** 4558 * @flags: Flags used to determine feature functionality. 4559 */ 4560 union replay_hw_flags flags; 4561 4562 /** 4563 * DPP HW instance. 4564 */ 4565 uint8_t dpp_inst; 4566 /** 4567 * OTG HW instance. 4568 */ 4569 uint8_t otg_inst; 4570 /** 4571 * DIG FE HW instance. 4572 */ 4573 uint8_t digfe_inst; 4574 /** 4575 * DIG BE HW instance. 4576 */ 4577 uint8_t digbe_inst; 4578 /** 4579 * AUX HW instance. 4580 */ 4581 uint8_t aux_inst; 4582 /** 4583 * Panel Instance. 4584 * Panel isntance to identify which psr_state to use 4585 * Currently the support is only for 0 or 1 4586 */ 4587 uint8_t panel_inst; 4588 /** 4589 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4590 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4591 */ 4592 uint8_t pixel_deviation_per_line; 4593 /** 4594 * @max_deviation_line: The max number of deviation line that can keep the timing 4595 * synchronized between the Source and Sink during Replay normal sleep mode. 4596 */ 4597 uint8_t max_deviation_line; 4598 /** 4599 * Length of each horizontal line in ns. 4600 */ 4601 uint32_t line_time_in_ns; 4602 /** 4603 * PHY instance. 4604 */ 4605 uint8_t dpphy_inst; 4606 /** 4607 * Determines if SMU optimzations are enabled/disabled. 4608 */ 4609 uint8_t smu_optimizations_en; 4610 /** 4611 * Determines if timing sync are enabled/disabled. 4612 */ 4613 uint8_t replay_timing_sync_supported; 4614 /* 4615 * Use FSM state for Replay power up/down 4616 */ 4617 uint8_t use_phy_fsm; 4618 /** 4619 * Use for AUX-less ALPM LFPS wake operation 4620 */ 4621 struct dmub_alpm_auxless_data auxless_alpm_data; 4622 /** 4623 * @hpo_stream_enc_inst: HPO stream encoder instance 4624 */ 4625 uint8_t hpo_stream_enc_inst; 4626 /** 4627 * @hpo_link_enc_inst: HPO link encoder instance 4628 */ 4629 uint8_t hpo_link_enc_inst; 4630 /** 4631 * Determines if fast resync in ultra sleep mode is enabled/disabled. 4632 */ 4633 uint8_t replay_support_fast_resync_in_ultra_sleep_mode; 4634 /** 4635 * @pad: Align structure to 4 byte boundary. 4636 */ 4637 uint8_t pad[1]; 4638 }; 4639 4640 4641 /** 4642 * Replay versions. 4643 */ 4644 enum replay_version { 4645 /** 4646 * FreeSync Replay 4647 */ 4648 REPLAY_VERSION_FREESYNC_REPLAY = 0, 4649 /** 4650 * Panel Replay 4651 */ 4652 REPLAY_VERSION_PANEL_REPLAY = 1, 4653 /** 4654 * Replay not supported. 4655 */ 4656 REPLAY_VERSION_UNSUPPORTED = 0xFF, 4657 }; 4658 4659 /** 4660 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4661 */ 4662 struct dmub_rb_cmd_replay_copy_settings { 4663 /** 4664 * Command header. 4665 */ 4666 struct dmub_cmd_header header; 4667 /** 4668 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4669 */ 4670 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4671 }; 4672 4673 /** 4674 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4675 */ 4676 enum replay_enable { 4677 /** 4678 * Disable REPLAY. 4679 */ 4680 REPLAY_DISABLE = 0, 4681 /** 4682 * Enable REPLAY. 4683 */ 4684 REPLAY_ENABLE = 1, 4685 }; 4686 4687 /** 4688 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 4689 */ 4690 struct dmub_rb_cmd_smart_power_oled_enable_data { 4691 /** 4692 * SMART_POWER_OLED enable or disable. 4693 */ 4694 uint8_t enable; 4695 /** 4696 * Panel Instance. 4697 * Panel isntance to identify which replay_state to use 4698 * Currently the support is only for 0 or 1 4699 */ 4700 uint8_t panel_inst; 4701 4702 uint16_t peak_nits; 4703 /** 4704 * OTG HW instance. 4705 */ 4706 uint8_t otg_inst; 4707 /** 4708 * DIG FE HW instance. 4709 */ 4710 uint8_t digfe_inst; 4711 /** 4712 * DIG BE HW instance. 4713 */ 4714 uint8_t digbe_inst; 4715 uint8_t debugcontrol; 4716 /* 4717 * vertical interrupt trigger line 4718 */ 4719 uint32_t triggerline; 4720 4721 uint16_t fixed_max_cll; 4722 4723 uint8_t pad[2]; 4724 }; 4725 4726 /** 4727 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4728 */ 4729 struct dmub_rb_cmd_replay_enable_data { 4730 /** 4731 * Replay enable or disable. 4732 */ 4733 uint8_t enable; 4734 /** 4735 * Panel Instance. 4736 * Panel isntance to identify which replay_state to use 4737 * Currently the support is only for 0 or 1 4738 */ 4739 uint8_t panel_inst; 4740 /** 4741 * Phy state to enter. 4742 * Values to use are defined in dmub_phy_fsm_state 4743 */ 4744 uint8_t phy_fsm_state; 4745 /** 4746 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4747 * Set this using enum phy_link_rate. 4748 * This does not support HDMI/DP2 for now. 4749 */ 4750 uint8_t phy_rate; 4751 /** 4752 * @hpo_stream_enc_inst: HPO stream encoder instance 4753 */ 4754 uint8_t hpo_stream_enc_inst; 4755 /** 4756 * @hpo_link_enc_inst: HPO link encoder instance 4757 */ 4758 uint8_t hpo_link_enc_inst; 4759 /** 4760 * @pad: Align structure to 4 byte boundary. 4761 */ 4762 uint8_t pad[2]; 4763 }; 4764 4765 /** 4766 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4767 * Replay enable/disable is controlled using action in data. 4768 */ 4769 struct dmub_rb_cmd_replay_enable { 4770 /** 4771 * Command header. 4772 */ 4773 struct dmub_cmd_header header; 4774 4775 struct dmub_rb_cmd_replay_enable_data data; 4776 }; 4777 4778 /** 4779 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4780 */ 4781 struct dmub_cmd_replay_set_power_opt_data { 4782 /** 4783 * Panel Instance. 4784 * Panel isntance to identify which replay_state to use 4785 * Currently the support is only for 0 or 1 4786 */ 4787 uint8_t panel_inst; 4788 /** 4789 * Explicit padding to 4 byte boundary. 4790 */ 4791 uint8_t pad[3]; 4792 /** 4793 * REPLAY power option 4794 */ 4795 uint32_t power_opt; 4796 }; 4797 4798 /** 4799 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4800 */ 4801 struct dmub_cmd_replay_set_timing_sync_data { 4802 /** 4803 * Panel Instance. 4804 * Panel isntance to identify which replay_state to use 4805 * Currently the support is only for 0 or 1 4806 */ 4807 uint8_t panel_inst; 4808 /** 4809 * REPLAY set_timing_sync 4810 */ 4811 uint8_t timing_sync_supported; 4812 /** 4813 * Explicit padding to 4 byte boundary. 4814 */ 4815 uint8_t pad[2]; 4816 }; 4817 4818 /** 4819 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4820 */ 4821 struct dmub_cmd_replay_set_pseudo_vtotal { 4822 /** 4823 * Panel Instance. 4824 * Panel isntance to identify which replay_state to use 4825 * Currently the support is only for 0 or 1 4826 */ 4827 uint8_t panel_inst; 4828 /** 4829 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4830 */ 4831 uint16_t vtotal; 4832 /** 4833 * Explicit padding to 4 byte boundary. 4834 */ 4835 uint8_t pad; 4836 }; 4837 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4838 /** 4839 * Panel Instance. 4840 * Panel isntance to identify which replay_state to use 4841 * Currently the support is only for 0 or 1 4842 */ 4843 uint8_t panel_inst; 4844 /** 4845 * enabled: set adaptive sync sdp enabled 4846 */ 4847 uint8_t force_disabled; 4848 4849 uint8_t pad[2]; 4850 }; 4851 struct dmub_cmd_replay_set_general_cmd_data { 4852 /** 4853 * Panel Instance. 4854 * Panel isntance to identify which replay_state to use 4855 * Currently the support is only for 0 or 1 4856 */ 4857 uint8_t panel_inst; 4858 /** 4859 * subtype: replay general cmd sub type 4860 */ 4861 uint8_t subtype; 4862 4863 uint8_t pad[2]; 4864 /** 4865 * config data with param1 and param2 4866 */ 4867 uint32_t param1; 4868 4869 uint32_t param2; 4870 }; 4871 4872 /** 4873 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4874 */ 4875 struct dmub_rb_cmd_replay_set_power_opt { 4876 /** 4877 * Command header. 4878 */ 4879 struct dmub_cmd_header header; 4880 /** 4881 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4882 */ 4883 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4884 }; 4885 4886 /** 4887 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4888 */ 4889 struct dmub_cmd_replay_set_coasting_vtotal_data { 4890 /** 4891 * 16-bit value dicated by driver that indicates the coasting vtotal. 4892 */ 4893 uint16_t coasting_vtotal; 4894 /** 4895 * REPLAY control version. 4896 */ 4897 uint8_t cmd_version; 4898 /** 4899 * Panel Instance. 4900 * Panel isntance to identify which replay_state to use 4901 * Currently the support is only for 0 or 1 4902 */ 4903 uint8_t panel_inst; 4904 /** 4905 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4906 */ 4907 uint16_t coasting_vtotal_high; 4908 /** 4909 * frame skip number. 4910 */ 4911 uint16_t frame_skip_number; 4912 }; 4913 4914 /** 4915 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4916 */ 4917 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4918 /** 4919 * Command header. 4920 */ 4921 struct dmub_cmd_header header; 4922 /** 4923 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4924 */ 4925 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4926 }; 4927 4928 /** 4929 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4930 */ 4931 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4932 /** 4933 * Command header. 4934 */ 4935 struct dmub_cmd_header header; 4936 /** 4937 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4938 */ 4939 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4940 /** 4941 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4942 */ 4943 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4944 }; 4945 4946 /** 4947 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4948 */ 4949 struct dmub_rb_cmd_replay_set_timing_sync { 4950 /** 4951 * Command header. 4952 */ 4953 struct dmub_cmd_header header; 4954 /** 4955 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4956 */ 4957 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4958 }; 4959 4960 /** 4961 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4962 */ 4963 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4964 /** 4965 * Command header. 4966 */ 4967 struct dmub_cmd_header header; 4968 /** 4969 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4970 */ 4971 struct dmub_cmd_replay_set_pseudo_vtotal data; 4972 }; 4973 4974 /** 4975 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4976 */ 4977 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4978 /** 4979 * Command header. 4980 */ 4981 struct dmub_cmd_header header; 4982 /** 4983 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4984 */ 4985 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4986 }; 4987 4988 /** 4989 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4990 */ 4991 struct dmub_rb_cmd_replay_set_general_cmd { 4992 /** 4993 * Command header. 4994 */ 4995 struct dmub_cmd_header header; 4996 /** 4997 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4998 */ 4999 struct dmub_cmd_replay_set_general_cmd_data data; 5000 }; 5001 5002 /** 5003 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5004 */ 5005 struct dmub_cmd_replay_frameupdate_timer_data { 5006 /** 5007 * Panel Instance. 5008 * Panel isntance to identify which replay_state to use 5009 * Currently the support is only for 0 or 1 5010 */ 5011 uint8_t panel_inst; 5012 /** 5013 * Replay Frameupdate Timer Enable or not 5014 */ 5015 uint8_t enable; 5016 /** 5017 * REPLAY force reflash frame update number 5018 */ 5019 uint16_t frameupdate_count; 5020 }; 5021 /** 5022 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 5023 */ 5024 struct dmub_rb_cmd_replay_set_frameupdate_timer { 5025 /** 5026 * Command header. 5027 */ 5028 struct dmub_cmd_header header; 5029 /** 5030 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5031 */ 5032 struct dmub_cmd_replay_frameupdate_timer_data data; 5033 }; 5034 5035 /** 5036 * Definition union of replay command set 5037 */ 5038 union dmub_replay_cmd_set { 5039 /** 5040 * Panel Instance. 5041 * Panel isntance to identify which replay_state to use 5042 * Currently the support is only for 0 or 1 5043 */ 5044 uint8_t panel_inst; 5045 /** 5046 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 5047 */ 5048 struct dmub_cmd_replay_set_timing_sync_data sync_data; 5049 /** 5050 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 5051 */ 5052 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 5053 /** 5054 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 5055 */ 5056 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 5057 /** 5058 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 5059 */ 5060 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 5061 /** 5062 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 5063 */ 5064 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 5065 }; 5066 5067 /** 5068 * IHC command sub-types. 5069 */ 5070 enum dmub_cmd_ihc_type { 5071 /** 5072 * Set DIG HDCP interrupt destination. 5073 */ 5074 DMUB_CMD__IHC_SET_DIG_HDCP_INTERRUPT_DEST = 0, 5075 }; 5076 5077 /** 5078 * Data passed from driver to FW in a DMUB_CMD__IHC command. 5079 */ 5080 struct dmub_cmd_ihc_data { 5081 /** 5082 * DIG engine ID (0-3). 5083 */ 5084 uint8_t dig_id; 5085 /** 5086 * 1 = route to DMU, 0 = route to CPU. 5087 */ 5088 uint8_t to_dmu : 1; 5089 /** 5090 * Reserved bits. 5091 */ 5092 uint8_t reserved : 7; 5093 /** 5094 * Padding. 5095 */ 5096 uint8_t pad[2]; 5097 }; 5098 5099 /** 5100 * Definition of a DMUB_CMD__IHC command. 5101 */ 5102 struct dmub_rb_cmd_ihc { 5103 /** 5104 * Command header. 5105 */ 5106 struct dmub_cmd_header header; 5107 /** 5108 * IHC command data. 5109 */ 5110 struct dmub_cmd_ihc_data data; 5111 }; 5112 5113 /** 5114 * SMART POWER OLED command sub-types. 5115 */ 5116 enum dmub_cmd_smart_power_oled_type { 5117 5118 /** 5119 * Enable/Disable SMART_POWER_OLED. 5120 */ 5121 DMUB_CMD__SMART_POWER_OLED_ENABLE = 1, 5122 /** 5123 * Get current MaxCLL value if SMART POWER OLED is enabled. 5124 */ 5125 DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2, 5126 }; 5127 5128 /** 5129 * Definition of a DMUB_CMD__SMART_POWER_OLED command. 5130 */ 5131 struct dmub_rb_cmd_smart_power_oled_enable { 5132 /** 5133 * Command header. 5134 */ 5135 struct dmub_cmd_header header; 5136 5137 struct dmub_rb_cmd_smart_power_oled_enable_data data; 5138 }; 5139 5140 struct dmub_cmd_smart_power_oled_getmaxcll_input { 5141 uint8_t panel_inst; 5142 uint8_t pad[3]; 5143 }; 5144 5145 struct dmub_cmd_smart_power_oled_getmaxcll_output { 5146 uint16_t current_max_cll; 5147 uint8_t pad[2]; 5148 }; 5149 5150 /** 5151 * Definition of a DMUB_CMD__SMART_POWER_OLED command. 5152 */ 5153 struct dmub_rb_cmd_smart_power_oled_getmaxcll { 5154 struct dmub_cmd_header header; /**< Command header */ 5155 /** 5156 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 5157 */ 5158 union dmub_cmd_smart_power_oled_getmaxcll_data { 5159 struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */ 5160 struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */ 5161 uint32_t output_raw; /**< Raw data output */ 5162 } data; 5163 }; 5164 5165 /** 5166 * Set of HW components that can be locked. 5167 * 5168 * Note: If updating with more HW components, fields 5169 * in dmub_inbox0_cmd_lock_hw must be updated to match. 5170 */ 5171 union dmub_hw_lock_flags { 5172 /** 5173 * Set of HW components that can be locked. 5174 */ 5175 struct { 5176 /** 5177 * Lock/unlock OTG master update lock. 5178 */ 5179 uint8_t lock_pipe : 1; 5180 /** 5181 * Lock/unlock cursor. 5182 */ 5183 uint8_t lock_cursor : 1; 5184 /** 5185 * Lock/unlock global update lock. 5186 */ 5187 uint8_t lock_dig : 1; 5188 /** 5189 * Triple buffer lock requires additional hw programming to usual OTG master lock. 5190 */ 5191 uint8_t triple_buffer_lock : 1; 5192 } bits; 5193 5194 /** 5195 * Union for HW Lock flags. 5196 */ 5197 uint8_t u8All; 5198 }; 5199 5200 /** 5201 * Instances of HW to be locked. 5202 * 5203 * Note: If updating with more HW components, fields 5204 * in dmub_inbox0_cmd_lock_hw must be updated to match. 5205 */ 5206 struct dmub_hw_lock_inst_flags { 5207 /** 5208 * OTG HW instance for OTG master update lock. 5209 */ 5210 uint8_t otg_inst; 5211 /** 5212 * OPP instance for cursor lock. 5213 */ 5214 uint8_t opp_inst; 5215 /** 5216 * OTG HW instance for global update lock. 5217 * TODO: Remove, and re-use otg_inst. 5218 */ 5219 uint8_t dig_inst; 5220 /** 5221 * Explicit pad to 4 byte boundary. 5222 */ 5223 uint8_t pad; 5224 }; 5225 5226 /** 5227 * Clients that can acquire the HW Lock Manager. 5228 * 5229 * Note: If updating with more clients, fields in 5230 * dmub_inbox0_cmd_lock_hw must be updated to match. 5231 */ 5232 enum hw_lock_client { 5233 /** 5234 * Driver is the client of HW Lock Manager. 5235 */ 5236 HW_LOCK_CLIENT_DRIVER = 0, 5237 /** 5238 * PSR SU is the client of HW Lock Manager. 5239 */ 5240 HW_LOCK_CLIENT_PSR_SU = 1, 5241 HW_LOCK_CLIENT_SUBVP = 3, 5242 /** 5243 * Replay is the client of HW Lock Manager. 5244 */ 5245 HW_LOCK_CLIENT_REPLAY = 4, 5246 HW_LOCK_CLIENT_FAMS2 = 5, 5247 HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6, 5248 /** 5249 * Invalid client. 5250 */ 5251 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 5252 }; 5253 5254 /** 5255 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 5256 */ 5257 struct dmub_cmd_lock_hw_data { 5258 /** 5259 * Specifies the client accessing HW Lock Manager. 5260 */ 5261 enum hw_lock_client client; 5262 /** 5263 * HW instances to be locked. 5264 */ 5265 struct dmub_hw_lock_inst_flags inst_flags; 5266 /** 5267 * Which components to be locked. 5268 */ 5269 union dmub_hw_lock_flags hw_locks; 5270 /** 5271 * Specifies lock/unlock. 5272 */ 5273 uint8_t lock; 5274 /** 5275 * HW can be unlocked separately from releasing the HW Lock Mgr. 5276 * This flag is set if the client wishes to release the object. 5277 */ 5278 uint8_t should_release; 5279 /** 5280 * Explicit padding to 4 byte boundary. 5281 */ 5282 uint8_t pad; 5283 }; 5284 5285 /** 5286 * Definition of a DMUB_CMD__HW_LOCK command. 5287 * Command is used by driver and FW. 5288 */ 5289 struct dmub_rb_cmd_lock_hw { 5290 /** 5291 * Command header. 5292 */ 5293 struct dmub_cmd_header header; 5294 /** 5295 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 5296 */ 5297 struct dmub_cmd_lock_hw_data lock_hw_data; 5298 }; 5299 5300 /** 5301 * ABM command sub-types. 5302 */ 5303 enum dmub_cmd_abm_type { 5304 /** 5305 * Initialize parameters for ABM algorithm. 5306 * Data is passed through an indirect buffer. 5307 */ 5308 DMUB_CMD__ABM_INIT_CONFIG = 0, 5309 /** 5310 * Set OTG and panel HW instance. 5311 */ 5312 DMUB_CMD__ABM_SET_PIPE = 1, 5313 /** 5314 * Set user requested backklight level. 5315 */ 5316 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 5317 /** 5318 * Set ABM operating/aggression level. 5319 */ 5320 DMUB_CMD__ABM_SET_LEVEL = 3, 5321 /** 5322 * Set ambient light level. 5323 */ 5324 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 5325 /** 5326 * Enable/disable fractional duty cycle for backlight PWM. 5327 */ 5328 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 5329 5330 /** 5331 * unregister vertical interrupt after steady state is reached 5332 */ 5333 DMUB_CMD__ABM_PAUSE = 6, 5334 5335 /** 5336 * Save and Restore ABM state. On save we save parameters, and 5337 * on restore we update state with passed in data. 5338 */ 5339 DMUB_CMD__ABM_SAVE_RESTORE = 7, 5340 5341 /** 5342 * Query ABM caps. 5343 */ 5344 DMUB_CMD__ABM_QUERY_CAPS = 8, 5345 5346 /** 5347 * Set ABM Events 5348 */ 5349 DMUB_CMD__ABM_SET_EVENT = 9, 5350 5351 /** 5352 * Get the current ACE curve. 5353 */ 5354 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 5355 5356 /** 5357 * Get current histogram data 5358 */ 5359 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 5360 }; 5361 5362 /** 5363 * LSDMA command sub-types. 5364 */ 5365 enum dmub_cmd_lsdma_type { 5366 /** 5367 * Initialize parameters for LSDMA. 5368 * Ring buffer is mapped to the ring buffer 5369 */ 5370 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 5371 /** 5372 * LSDMA copies data from source to destination linearly 5373 */ 5374 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 5375 /** 5376 * LSDMA copies data from source to destination linearly in sub window 5377 */ 5378 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, 5379 /** 5380 * Send the tiled-to-tiled copy command 5381 */ 5382 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, 5383 /** 5384 * Send the poll reg write command 5385 */ 5386 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, 5387 /** 5388 * Send the pio copy command 5389 */ 5390 DMUB_CMD__LSDMA_PIO_COPY = 5, 5391 /** 5392 * Send the pio constfill command 5393 */ 5394 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, 5395 }; 5396 5397 struct abm_ace_curve { 5398 /** 5399 * @offsets: ACE curve offsets. 5400 */ 5401 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5402 5403 /** 5404 * @thresholds: ACE curve thresholds. 5405 */ 5406 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5407 5408 /** 5409 * @slopes: ACE curve slopes. 5410 */ 5411 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5412 }; 5413 5414 struct fixed_pt_format { 5415 /** 5416 * @sign_bit: Indicates whether one bit is reserved for the sign. 5417 */ 5418 bool sign_bit; 5419 5420 /** 5421 * @num_int_bits: Number of bits used for integer part. 5422 */ 5423 uint8_t num_int_bits; 5424 5425 /** 5426 * @num_frac_bits: Number of bits used for fractional part. 5427 */ 5428 uint8_t num_frac_bits; 5429 5430 /** 5431 * @pad: Explicit padding to 4 byte boundary. 5432 */ 5433 uint8_t pad; 5434 }; 5435 5436 struct abm_caps { 5437 /** 5438 * @num_hg_bins: Number of histogram bins. 5439 */ 5440 uint8_t num_hg_bins; 5441 5442 /** 5443 * @num_ace_segments: Number of ACE curve segments. 5444 */ 5445 uint8_t num_ace_segments; 5446 5447 /** 5448 * @pad: Explicit padding to 4 byte boundary. 5449 */ 5450 uint8_t pad[2]; 5451 5452 /** 5453 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 5454 */ 5455 struct fixed_pt_format ace_thresholds_format; 5456 5457 /** 5458 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 5459 */ 5460 struct fixed_pt_format ace_offsets_format; 5461 5462 /** 5463 * @ace_slopes_format: Format of the ACE slopes. 5464 */ 5465 struct fixed_pt_format ace_slopes_format; 5466 }; 5467 5468 /** 5469 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 5470 * Requirements: 5471 * - Padded explicitly to 32-bit boundary. 5472 * - Must ensure this structure matches the one on driver-side, 5473 * otherwise it won't be aligned. 5474 */ 5475 struct abm_config_table { 5476 /** 5477 * Gamma curve thresholds, used for crgb conversion. 5478 */ 5479 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 5480 /** 5481 * Gamma curve offsets, used for crgb conversion. 5482 */ 5483 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 5484 /** 5485 * Gamma curve slopes, used for crgb conversion. 5486 */ 5487 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 5488 /** 5489 * Custom backlight curve thresholds. 5490 */ 5491 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 5492 /** 5493 * Custom backlight curve offsets. 5494 */ 5495 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 5496 /** 5497 * Ambient light thresholds. 5498 */ 5499 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 5500 /** 5501 * Minimum programmable backlight. 5502 */ 5503 uint16_t min_abm_backlight; // 122B 5504 /** 5505 * Minimum reduction values. 5506 */ 5507 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 5508 /** 5509 * Maximum reduction values. 5510 */ 5511 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 5512 /** 5513 * Bright positive gain. 5514 */ 5515 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 5516 /** 5517 * Dark negative gain. 5518 */ 5519 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 5520 /** 5521 * Hybrid factor. 5522 */ 5523 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 5524 /** 5525 * Contrast factor. 5526 */ 5527 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 5528 /** 5529 * Deviation gain. 5530 */ 5531 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 5532 /** 5533 * Minimum knee. 5534 */ 5535 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 5536 /** 5537 * Maximum knee. 5538 */ 5539 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 5540 /** 5541 * Unused. 5542 */ 5543 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 5544 /** 5545 * Explicit padding to 4 byte boundary. 5546 */ 5547 uint8_t pad3[3]; // 229B 5548 /** 5549 * Backlight ramp reduction. 5550 */ 5551 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 5552 /** 5553 * Backlight ramp start. 5554 */ 5555 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 5556 }; 5557 5558 /** 5559 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5560 */ 5561 struct dmub_cmd_abm_set_pipe_data { 5562 /** 5563 * OTG HW instance. 5564 */ 5565 uint8_t otg_inst; 5566 5567 /** 5568 * Panel Control HW instance. 5569 */ 5570 uint8_t panel_inst; 5571 5572 /** 5573 * Controls how ABM will interpret a set pipe or set level command. 5574 */ 5575 uint8_t set_pipe_option; 5576 5577 /** 5578 * Unused. 5579 * TODO: Remove. 5580 */ 5581 uint8_t ramping_boundary; 5582 5583 /** 5584 * PwrSeq HW Instance. 5585 */ 5586 uint8_t pwrseq_inst; 5587 5588 /** 5589 * Explicit padding to 4 byte boundary. 5590 */ 5591 uint8_t pad[3]; 5592 }; 5593 5594 /** 5595 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5596 */ 5597 struct dmub_rb_cmd_abm_set_pipe { 5598 /** 5599 * Command header. 5600 */ 5601 struct dmub_cmd_header header; 5602 5603 /** 5604 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5605 */ 5606 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 5607 }; 5608 5609 /** 5610 * Type of backlight control method to be used by ABM module 5611 */ 5612 enum dmub_backlight_control_type { 5613 /** 5614 * PWM Backlight control 5615 */ 5616 DMU_BACKLIGHT_CONTROL_PWM = 0, 5617 /** 5618 * VESA Aux-based backlight control 5619 */ 5620 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 5621 /** 5622 * AMD DPCD Aux-based backlight control 5623 */ 5624 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 5625 }; 5626 5627 /** 5628 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5629 */ 5630 struct dmub_cmd_abm_set_backlight_data { 5631 /** 5632 * Number of frames to ramp to backlight user level. 5633 */ 5634 uint32_t frame_ramp; 5635 5636 /** 5637 * Requested backlight level from user. 5638 */ 5639 uint32_t backlight_user_level; 5640 5641 /** 5642 * ABM control version. 5643 */ 5644 uint8_t version; 5645 5646 /** 5647 * Panel Control HW instance mask. 5648 * Bit 0 is Panel Control HW instance 0. 5649 * Bit 1 is Panel Control HW instance 1. 5650 */ 5651 uint8_t panel_mask; 5652 5653 /** 5654 * AUX HW Instance. 5655 */ 5656 uint8_t aux_inst; 5657 5658 /** 5659 * Explicit padding to 4 byte boundary. 5660 */ 5661 uint8_t pad[1]; 5662 5663 /** 5664 * Backlight control type. 5665 * Value 0 is PWM backlight control. 5666 * Value 1 is VAUX backlight control. 5667 * Value 2 is AMD DPCD AUX backlight control. 5668 */ 5669 enum dmub_backlight_control_type backlight_control_type; 5670 5671 /** 5672 * Minimum luminance in nits. 5673 */ 5674 uint32_t min_luminance; 5675 5676 /** 5677 * Maximum luminance in nits. 5678 */ 5679 uint32_t max_luminance; 5680 5681 /** 5682 * Minimum backlight in pwm. 5683 */ 5684 uint32_t min_backlight_pwm; 5685 5686 /** 5687 * Maximum backlight in pwm. 5688 */ 5689 uint32_t max_backlight_pwm; 5690 }; 5691 5692 /** 5693 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5694 */ 5695 struct dmub_rb_cmd_abm_set_backlight { 5696 /** 5697 * Command header. 5698 */ 5699 struct dmub_cmd_header header; 5700 5701 /** 5702 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5703 */ 5704 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 5705 }; 5706 5707 /** 5708 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5709 */ 5710 struct dmub_cmd_abm_set_level_data { 5711 /** 5712 * Set current ABM operating/aggression level. 5713 */ 5714 uint32_t level; 5715 5716 /** 5717 * ABM control version. 5718 */ 5719 uint8_t version; 5720 5721 /** 5722 * Panel Control HW instance mask. 5723 * Bit 0 is Panel Control HW instance 0. 5724 * Bit 1 is Panel Control HW instance 1. 5725 */ 5726 uint8_t panel_mask; 5727 5728 /** 5729 * Explicit padding to 4 byte boundary. 5730 */ 5731 uint8_t pad[2]; 5732 }; 5733 5734 /** 5735 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5736 */ 5737 struct dmub_rb_cmd_abm_set_level { 5738 /** 5739 * Command header. 5740 */ 5741 struct dmub_cmd_header header; 5742 5743 /** 5744 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5745 */ 5746 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5747 }; 5748 5749 /** 5750 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5751 */ 5752 struct dmub_cmd_abm_set_ambient_level_data { 5753 /** 5754 * Ambient light sensor reading from OS. 5755 */ 5756 uint32_t ambient_lux; 5757 5758 /** 5759 * ABM control version. 5760 */ 5761 uint8_t version; 5762 5763 /** 5764 * Panel Control HW instance mask. 5765 * Bit 0 is Panel Control HW instance 0. 5766 * Bit 1 is Panel Control HW instance 1. 5767 */ 5768 uint8_t panel_mask; 5769 5770 /** 5771 * Explicit padding to 4 byte boundary. 5772 */ 5773 uint8_t pad[2]; 5774 }; 5775 5776 /** 5777 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5778 */ 5779 struct dmub_rb_cmd_abm_set_ambient_level { 5780 /** 5781 * Command header. 5782 */ 5783 struct dmub_cmd_header header; 5784 5785 /** 5786 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5787 */ 5788 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5789 }; 5790 5791 /** 5792 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5793 */ 5794 struct dmub_cmd_abm_set_pwm_frac_data { 5795 /** 5796 * Enable/disable fractional duty cycle for backlight PWM. 5797 * TODO: Convert to uint8_t. 5798 */ 5799 uint32_t fractional_pwm; 5800 5801 /** 5802 * ABM control version. 5803 */ 5804 uint8_t version; 5805 5806 /** 5807 * Panel Control HW instance mask. 5808 * Bit 0 is Panel Control HW instance 0. 5809 * Bit 1 is Panel Control HW instance 1. 5810 */ 5811 uint8_t panel_mask; 5812 5813 /** 5814 * Explicit padding to 4 byte boundary. 5815 */ 5816 uint8_t pad[2]; 5817 }; 5818 5819 /** 5820 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5821 */ 5822 struct dmub_rb_cmd_abm_set_pwm_frac { 5823 /** 5824 * Command header. 5825 */ 5826 struct dmub_cmd_header header; 5827 5828 /** 5829 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5830 */ 5831 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5832 }; 5833 5834 /** 5835 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5836 */ 5837 struct dmub_cmd_abm_init_config_data { 5838 /** 5839 * Location of indirect buffer used to pass init data to ABM. 5840 */ 5841 union dmub_addr src; 5842 5843 /** 5844 * Indirect buffer length. 5845 */ 5846 uint16_t bytes; 5847 5848 5849 /** 5850 * ABM control version. 5851 */ 5852 uint8_t version; 5853 5854 /** 5855 * Panel Control HW instance mask. 5856 * Bit 0 is Panel Control HW instance 0. 5857 * Bit 1 is Panel Control HW instance 1. 5858 */ 5859 uint8_t panel_mask; 5860 5861 /** 5862 * Explicit padding to 4 byte boundary. 5863 */ 5864 uint8_t pad[2]; 5865 }; 5866 5867 /** 5868 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5869 */ 5870 struct dmub_rb_cmd_abm_init_config { 5871 /** 5872 * Command header. 5873 */ 5874 struct dmub_cmd_header header; 5875 5876 /** 5877 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5878 */ 5879 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5880 }; 5881 5882 /** 5883 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5884 */ 5885 5886 struct dmub_cmd_abm_pause_data { 5887 5888 /** 5889 * Panel Control HW instance mask. 5890 * Bit 0 is Panel Control HW instance 0. 5891 * Bit 1 is Panel Control HW instance 1. 5892 */ 5893 uint8_t panel_mask; 5894 5895 /** 5896 * OTG hw instance 5897 */ 5898 uint8_t otg_inst; 5899 5900 /** 5901 * Enable or disable ABM pause 5902 */ 5903 uint8_t enable; 5904 5905 /** 5906 * Explicit padding to 4 byte boundary. 5907 */ 5908 uint8_t pad[1]; 5909 }; 5910 5911 /** 5912 * Definition of a DMUB_CMD__ABM_PAUSE command. 5913 */ 5914 struct dmub_rb_cmd_abm_pause { 5915 /** 5916 * Command header. 5917 */ 5918 struct dmub_cmd_header header; 5919 5920 /** 5921 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5922 */ 5923 struct dmub_cmd_abm_pause_data abm_pause_data; 5924 }; 5925 5926 /** 5927 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5928 */ 5929 struct dmub_cmd_abm_query_caps_in { 5930 /** 5931 * Panel instance. 5932 */ 5933 uint8_t panel_inst; 5934 5935 /** 5936 * Explicit padding to 4 byte boundary. 5937 */ 5938 uint8_t pad[3]; 5939 }; 5940 5941 /** 5942 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5943 */ 5944 struct dmub_cmd_abm_query_caps_out { 5945 /** 5946 * SW Algorithm caps. 5947 */ 5948 struct abm_caps sw_caps; 5949 5950 /** 5951 * ABM HW caps. 5952 */ 5953 struct abm_caps hw_caps; 5954 }; 5955 5956 /** 5957 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5958 */ 5959 struct dmub_rb_cmd_abm_query_caps { 5960 /** 5961 * Command header. 5962 */ 5963 struct dmub_cmd_header header; 5964 5965 /** 5966 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5967 */ 5968 union { 5969 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5970 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5971 } data; 5972 }; 5973 5974 /** 5975 * enum dmub_abm_ace_curve_type - ACE curve type. 5976 */ 5977 enum dmub_abm_ace_curve_type { 5978 /** 5979 * ACE curve as defined by the SW layer. 5980 */ 5981 ABM_ACE_CURVE_TYPE__SW = 0, 5982 /** 5983 * ACE curve as defined by the SW to HW translation interface layer. 5984 */ 5985 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5986 }; 5987 5988 /** 5989 * enum dmub_abm_histogram_type - Histogram type. 5990 */ 5991 enum dmub_abm_histogram_type { 5992 /** 5993 * ACE curve as defined by the SW layer. 5994 */ 5995 ABM_HISTOGRAM_TYPE__SW = 0, 5996 /** 5997 * ACE curve as defined by the SW to HW translation interface layer. 5998 */ 5999 ABM_HISTOGRAM_TYPE__SW_IF = 1, 6000 }; 6001 6002 /** 6003 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6004 */ 6005 struct dmub_rb_cmd_abm_get_ace_curve { 6006 /** 6007 * Command header. 6008 */ 6009 struct dmub_cmd_header header; 6010 6011 /** 6012 * Address where ACE curve should be copied. 6013 */ 6014 union dmub_addr dest; 6015 6016 /** 6017 * Type of ACE curve being queried. 6018 */ 6019 enum dmub_abm_ace_curve_type ace_type; 6020 6021 /** 6022 * Indirect buffer length. 6023 */ 6024 uint16_t bytes; 6025 6026 /** 6027 * eDP panel instance. 6028 */ 6029 uint8_t panel_inst; 6030 6031 /** 6032 * Explicit padding to 4 byte boundary. 6033 */ 6034 uint8_t pad; 6035 }; 6036 6037 /** 6038 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6039 */ 6040 struct dmub_rb_cmd_abm_get_histogram { 6041 /** 6042 * Command header. 6043 */ 6044 struct dmub_cmd_header header; 6045 6046 /** 6047 * Address where Histogram should be copied. 6048 */ 6049 union dmub_addr dest; 6050 6051 /** 6052 * Type of Histogram being queried. 6053 */ 6054 enum dmub_abm_histogram_type histogram_type; 6055 6056 /** 6057 * Indirect buffer length. 6058 */ 6059 uint16_t bytes; 6060 6061 /** 6062 * eDP panel instance. 6063 */ 6064 uint8_t panel_inst; 6065 6066 /** 6067 * Explicit padding to 4 byte boundary. 6068 */ 6069 uint8_t pad; 6070 }; 6071 6072 /** 6073 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6074 */ 6075 struct dmub_rb_cmd_abm_save_restore { 6076 /** 6077 * Command header. 6078 */ 6079 struct dmub_cmd_header header; 6080 6081 /** 6082 * OTG hw instance 6083 */ 6084 uint8_t otg_inst; 6085 6086 /** 6087 * Enable or disable ABM pause 6088 */ 6089 uint8_t freeze; 6090 6091 /** 6092 * Explicit padding to 4 byte boundary. 6093 */ 6094 uint8_t debug; 6095 6096 /** 6097 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 6098 */ 6099 struct dmub_cmd_abm_init_config_data abm_init_config_data; 6100 }; 6101 6102 /** 6103 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 6104 */ 6105 6106 struct dmub_cmd_abm_set_event_data { 6107 6108 /** 6109 * VB Scaling Init. Strength Mapping 6110 * Byte 0: 0~255 for VB level 0 6111 * Byte 1: 0~255 for VB level 1 6112 * Byte 2: 0~255 for VB level 2 6113 * Byte 3: 0~255 for VB level 3 6114 */ 6115 uint32_t vb_scaling_strength_mapping; 6116 /** 6117 * VariBright Scaling Enable 6118 */ 6119 uint8_t vb_scaling_enable; 6120 /** 6121 * Panel Control HW instance mask. 6122 * Bit 0 is Panel Control HW instance 0. 6123 * Bit 1 is Panel Control HW instance 1. 6124 */ 6125 uint8_t panel_mask; 6126 6127 /** 6128 * Explicit padding to 4 byte boundary. 6129 */ 6130 uint8_t pad[2]; 6131 }; 6132 6133 /** 6134 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6135 */ 6136 struct dmub_rb_cmd_abm_set_event { 6137 /** 6138 * Command header. 6139 */ 6140 struct dmub_cmd_header header; 6141 6142 /** 6143 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 6144 */ 6145 struct dmub_cmd_abm_set_event_data abm_set_event_data; 6146 }; 6147 6148 /** 6149 * CACP command sub-types. 6150 */ 6151 enum dmub_cmd_cacp_type { 6152 /** 6153 * Initialize parameters for CACP algorithm. 6154 * Data is passed through an indirect buffer. 6155 */ 6156 DMUB_CMD__CACP_INIT_CONFIG = 0, 6157 /** 6158 * Set OTG and panel HW instance. 6159 */ 6160 DMUB_CMD__CACP_SET_PIPE = 1, 6161 /** 6162 * Set CACP operating/aggression level. 6163 */ 6164 DMUB_CMD__CACP_SET_LEVEL = 2, 6165 /** 6166 * Set event: full-screen/video mode/Hdr mode 6167 */ 6168 DMUB_CMD__CACP_SET_EVENT = 3, 6169 6170 /** 6171 * unregister vertical interrupt after steady state is reached 6172 */ 6173 DMUB_CMD__CACP_PAUSE = 4, 6174 /** 6175 * Set backlight: only for miniLED 6176 */ 6177 DMUB_CMD__CACP_SET_BACKLIGHT = 5, 6178 /** 6179 * Enable/disable fractional duty cycle for backlight PWM. 6180 */ 6181 DMUB_CMD__CACP_SET_PWM_FRAC = 6, 6182 /** 6183 * Get CACP Histogram 6184 */ 6185 DMUB_CMD__CACP_GET_HISTOGRAM = 7, 6186 }; 6187 6188 /** 6189 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PIPE command. 6190 */ 6191 struct dmub_cmd_cacp_set_pipe_data { 6192 /** 6193 * OTG HW instance. 6194 */ 6195 uint8_t otg_inst; 6196 6197 /** 6198 * Panel Control HW instance. 6199 */ 6200 uint8_t panel_inst; 6201 6202 /** 6203 * Controls how CACP will interpret a set pipe or set level command. 6204 */ 6205 uint8_t set_pipe_option; 6206 6207 /** 6208 * PwrSeq HW Instance. 6209 */ 6210 uint8_t pwrseq_inst; 6211 }; 6212 6213 /** 6214 * Definition of a DMUB_CMD__CACP_SET_PIPE command. 6215 */ 6216 struct dmub_rb_cmd_cacp_set_pipe { 6217 /** 6218 * Command header. 6219 */ 6220 struct dmub_cmd_header header; 6221 6222 /** 6223 * Data passed from driver to FW in a DMUB_CMD__CACP_PIPE command. 6224 */ 6225 struct dmub_cmd_cacp_set_pipe_data cacp_set_pipe_data; 6226 }; 6227 6228 /** 6229 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_LEVEL command. 6230 */ 6231 struct dmub_cmd_cacp_set_level_data { 6232 /** 6233 * Set current cacp operating/aggression level. 6234 */ 6235 uint32_t level; 6236 6237 /** 6238 * CACP control version. 6239 */ 6240 uint8_t version; 6241 6242 /** 6243 * Panel Control HW instance mask. 6244 * Bit 0 is Panel Control HW instance 0. 6245 * Bit 1 is Panel Control HW instance 1. 6246 */ 6247 uint8_t panel_mask; 6248 6249 /** 6250 * Explicit padding to 4 byte boundary. 6251 */ 6252 uint8_t pad[2]; 6253 }; 6254 6255 /** 6256 * Definition of a DMUB_CMD__CACP_SET_LEVEL command. 6257 */ 6258 struct dmub_rb_cmd_cacp_set_level { 6259 /** 6260 * Command header. 6261 */ 6262 struct dmub_cmd_header header; 6263 6264 /** 6265 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_LEVEL command. 6266 */ 6267 struct dmub_cmd_cacp_set_level_data cacp_set_level_data; 6268 }; 6269 6270 /** 6271 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_EVENT command. 6272 */ 6273 struct dmub_cmd_cacp_set_event_data { 6274 /** 6275 * Full screen mode 6276 */ 6277 uint8_t full_screen_mode; 6278 6279 /** 6280 * VariBright Scaling Enable 6281 */ 6282 uint8_t vb_scaling_enable; 6283 6284 /** 6285 * HDR mode 6286 */ 6287 uint8_t hdr_mode; 6288 6289 /** 6290 * Panel Control HW instance mask. 6291 * Bit 0 is Panel Control HW instance 0. 6292 * Bit 1 is Panel Control HW instance 1. 6293 */ 6294 uint8_t panel_mask; 6295 6296 /** 6297 * Transition time info 6298 */ 6299 uint32_t trans_info; 6300 }; 6301 6302 /** 6303 * Definition of a DMUB_CMD__CACP_SET_EVENT command. 6304 */ 6305 struct dmub_rb_cmd_cacp_set_event { 6306 /** 6307 * Command header. 6308 */ 6309 struct dmub_cmd_header header; 6310 6311 /** 6312 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_EVENT command. 6313 */ 6314 struct dmub_cmd_cacp_set_event_data cacp_set_event_data; 6315 }; 6316 6317 /** 6318 * Data passed from driver to FW in a DMUB_CMD__CACP_INIT_CONFIG command. 6319 */ 6320 struct dmub_cmd_cacp_init_config_data { 6321 /** 6322 * Location of indirect buffer used to pass init data to CACP. 6323 */ 6324 union dmub_addr src; 6325 6326 /** 6327 * Indirect buffer length. 6328 */ 6329 uint16_t bytes; 6330 6331 /** 6332 * CACP control version. 6333 */ 6334 uint8_t mode; 6335 6336 /** 6337 * Panel Control HW instance mask. 6338 * Bit 0 is Panel Control HW instance 0. 6339 * Bit 1 is Panel Control HW instance 1. 6340 */ 6341 uint8_t panel_mask; 6342 6343 /** 6344 * CACP visual_confirm debug 6345 */ 6346 uint32_t visual_confirm; 6347 6348 /** 6349 * CACP customized str_scl params 6350 */ 6351 uint8_t strscl_valid; 6352 uint8_t pad[3]; 6353 uint8_t strscl_sdr[4]; 6354 uint8_t strscl_hdr[4]; 6355 }; 6356 6357 /** 6358 * Definition of a DMUB_CMD__CACP_INIT_CONFIG command. 6359 */ 6360 struct dmub_rb_cmd_cacp_init_config { 6361 /** 6362 * Command header. 6363 */ 6364 struct dmub_cmd_header header; 6365 6366 /** 6367 * Data passed from driver to FW in a DMUB_CMD__CACP_INIT_CONFIG command. 6368 */ 6369 struct dmub_cmd_cacp_init_config_data cacp_init_config_data; 6370 }; 6371 6372 /** 6373 * Data passed from driver to FW in a DMUB_CMD__CACP_PAUSE command. 6374 */ 6375 6376 struct dmub_cmd_cacp_pause_data { 6377 6378 /** 6379 * Panel Control HW instance mask. 6380 * Bit 0 is Panel Control HW instance 0. 6381 * Bit 1 is Panel Control HW instance 1. 6382 */ 6383 uint8_t panel_mask; 6384 6385 /** 6386 * OTG hw instance 6387 */ 6388 uint8_t otg_inst; 6389 6390 /** 6391 * Enable or disable CACP pause 6392 */ 6393 uint8_t enable; 6394 6395 /** 6396 * Explicit padding to 4 byte boundary. 6397 */ 6398 uint8_t pad; 6399 }; 6400 6401 /** 6402 * Definition of a DMUB_CMD__CACP_PAUSE command. 6403 */ 6404 struct dmub_rb_cmd_cacp_pause { 6405 /** 6406 * Command header. 6407 */ 6408 struct dmub_cmd_header header; 6409 6410 /** 6411 * Data passed from driver to FW in a DMUB_CMD__CACP_PAUSE command. 6412 */ 6413 struct dmub_cmd_cacp_pause_data cacp_pause_data; 6414 }; 6415 6416 /** 6417 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_BACKLIGHT command. 6418 */ 6419 struct dmub_cmd_cacp_set_backlight_data { 6420 /** 6421 * Number of frames to ramp to backlight user level. 6422 */ 6423 uint32_t frame_ramp; 6424 6425 /** 6426 * Requested backlight level from user. 6427 */ 6428 uint32_t backlight_user_level; 6429 6430 /** 6431 * ABM control version. 6432 */ 6433 uint8_t version; 6434 6435 /** 6436 * Panel Control HW instance mask. 6437 * Bit 0 is Panel Control HW instance 0. 6438 * Bit 1 is Panel Control HW instance 1. 6439 */ 6440 uint8_t panel_mask; 6441 6442 /** 6443 * Explicit padding to 4 byte boundary. 6444 */ 6445 uint8_t pad[2]; 6446 }; 6447 6448 /** 6449 * Definition of a DMUB_CMD__CACP_SET_BACKLIGHT command. 6450 */ 6451 struct dmub_rb_cmd_cacp_set_backlight { 6452 /** 6453 * Command header. 6454 */ 6455 struct dmub_cmd_header header; 6456 6457 /** 6458 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_BACKLIGHT command. 6459 */ 6460 struct dmub_cmd_cacp_set_backlight_data cacp_set_backlight_data; 6461 }; 6462 6463 /** 6464 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PWM_FRAC command. 6465 */ 6466 struct dmub_cmd_cacp_set_pwm_frac_data { 6467 /** 6468 * Enable/disable fractional duty cycle for backlight PWM. 6469 * TODO: Convert to uint8_t. 6470 */ 6471 uint32_t fractional_pwm; 6472 6473 /** 6474 * CACP control version. 6475 */ 6476 uint8_t version; 6477 6478 /** 6479 * Panel Control HW instance mask. 6480 * Bit 0 is Panel Control HW instance 0. 6481 * Bit 1 is Panel Control HW instance 1. 6482 */ 6483 uint8_t panel_mask; 6484 6485 /** 6486 * Explicit padding to 4 byte boundary. 6487 */ 6488 uint8_t pad[2]; 6489 }; 6490 6491 /** 6492 * Definition of a DMUB_CMD__CACP_SET_PWM_FRAC command. 6493 */ 6494 struct dmub_rb_cmd_cacp_set_pwm_frac { 6495 /** 6496 * Command header. 6497 */ 6498 struct dmub_cmd_header header; 6499 6500 /** 6501 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PWM_FRAC command. 6502 */ 6503 struct dmub_cmd_cacp_set_pwm_frac_data cacp_set_pwm_frac_data; 6504 }; 6505 6506 /** 6507 * Definition of a DMUB_CMD__CACP_GET_HISTOGRAM command. 6508 */ 6509 struct dmub_rb_cmd_cacp_get_histogram { 6510 /** 6511 * Command header. 6512 */ 6513 struct dmub_cmd_header header; 6514 6515 /** 6516 * Address where Histogram should be copied. 6517 */ 6518 union dmub_addr dest; 6519 6520 /** 6521 * Type of Histogram being queried. 6522 */ 6523 enum dmub_abm_histogram_type histogram_type; 6524 6525 /** 6526 * Indirect buffer length. 6527 */ 6528 uint16_t bytes; 6529 6530 /** 6531 * eDP panel instance. 6532 */ 6533 uint8_t panel_inst; 6534 6535 /** 6536 * Explicit padding to 4 byte boundary. 6537 */ 6538 uint8_t pad; 6539 }; 6540 6541 /** 6542 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 6543 */ 6544 struct dmub_cmd_query_feature_caps_data { 6545 /** 6546 * DMUB feature capabilities. 6547 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 6548 */ 6549 struct dmub_feature_caps feature_caps; 6550 }; 6551 6552 /** 6553 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6554 */ 6555 struct dmub_rb_cmd_query_feature_caps { 6556 /** 6557 * Command header. 6558 */ 6559 struct dmub_cmd_header header; 6560 /** 6561 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 6562 */ 6563 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 6564 }; 6565 6566 /** 6567 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6568 */ 6569 struct dmub_cmd_visual_confirm_color_data { 6570 /** 6571 * DMUB visual confirm color 6572 */ 6573 struct dmub_visual_confirm_color visual_confirm_color; 6574 }; 6575 6576 /** 6577 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6578 */ 6579 struct dmub_rb_cmd_get_visual_confirm_color { 6580 /** 6581 * Command header. 6582 */ 6583 struct dmub_cmd_header header; 6584 /** 6585 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6586 */ 6587 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 6588 }; 6589 6590 /** 6591 * enum dmub_cmd_panel_cntl_type - Panel control command. 6592 */ 6593 enum dmub_cmd_panel_cntl_type { 6594 /** 6595 * Initializes embedded panel hardware blocks. 6596 */ 6597 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 6598 /** 6599 * Queries backlight info for the embedded panel. 6600 */ 6601 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 6602 /** 6603 * Sets the PWM Freq as per user's requirement. 6604 */ 6605 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 6606 }; 6607 6608 /** 6609 * struct dmub_cmd_panel_cntl_data - Panel control data. 6610 */ 6611 struct dmub_cmd_panel_cntl_data { 6612 uint32_t pwrseq_inst; /**< pwrseq instance */ 6613 uint32_t current_backlight; /* in/out */ 6614 uint32_t bl_pwm_cntl; /* in/out */ 6615 uint32_t bl_pwm_period_cntl; /* in/out */ 6616 uint32_t bl_pwm_ref_div1; /* in/out */ 6617 uint8_t is_backlight_on : 1; /* in/out */ 6618 uint8_t is_powered_on : 1; /* in/out */ 6619 uint8_t padding[3]; 6620 uint32_t bl_pwm_ref_div2; /* in/out */ 6621 uint8_t reserved[4]; 6622 }; 6623 6624 /** 6625 * struct dmub_rb_cmd_panel_cntl - Panel control command. 6626 */ 6627 struct dmub_rb_cmd_panel_cntl { 6628 struct dmub_cmd_header header; /**< header */ 6629 struct dmub_cmd_panel_cntl_data data; /**< payload */ 6630 }; 6631 6632 struct dmub_optc_state { 6633 uint32_t v_total_max; 6634 uint32_t v_total_min; 6635 uint32_t tg_inst; 6636 }; 6637 6638 struct dmub_rb_cmd_drr_update { 6639 struct dmub_cmd_header header; 6640 struct dmub_optc_state dmub_optc_state_req; 6641 }; 6642 6643 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 6644 uint32_t pix_clk_100hz; 6645 uint8_t max_ramp_step; 6646 uint8_t pipes; 6647 uint8_t min_refresh_in_hz; 6648 uint8_t pipe_count; 6649 uint8_t pipe_index[4]; 6650 }; 6651 6652 struct dmub_cmd_fw_assisted_mclk_switch_config { 6653 uint8_t fams_enabled; 6654 uint8_t visual_confirm_enabled; 6655 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 6656 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 6657 }; 6658 6659 struct dmub_rb_cmd_fw_assisted_mclk_switch { 6660 struct dmub_cmd_header header; 6661 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 6662 }; 6663 6664 /** 6665 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6666 */ 6667 struct dmub_cmd_lvtma_control_data { 6668 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 6669 uint8_t bypass_panel_control_wait; 6670 uint8_t reserved_0[2]; /**< For future use */ 6671 uint8_t pwrseq_inst; /**< LVTMA control instance */ 6672 uint8_t reserved_1[3]; /**< For future use */ 6673 }; 6674 6675 /** 6676 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6677 */ 6678 struct dmub_rb_cmd_lvtma_control { 6679 /** 6680 * Command header. 6681 */ 6682 struct dmub_cmd_header header; 6683 /** 6684 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6685 */ 6686 struct dmub_cmd_lvtma_control_data data; 6687 }; 6688 6689 /** 6690 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6691 */ 6692 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 6693 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 6694 uint8_t is_usb; /**< is phy is usb */ 6695 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 6696 uint8_t is_dp4; /**< is dp in 4 lane */ 6697 }; 6698 6699 /** 6700 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6701 */ 6702 struct dmub_rb_cmd_transmitter_query_dp_alt { 6703 struct dmub_cmd_header header; /**< header */ 6704 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 6705 }; 6706 6707 struct phy_test_mode { 6708 uint8_t mode; 6709 uint8_t pat0; 6710 uint8_t pad[2]; 6711 }; 6712 6713 /** 6714 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6715 */ 6716 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 6717 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 6718 uint8_t mode; /**< HDMI/DP/DP2 etc */ 6719 uint8_t lane_num; /**< Number of lanes */ 6720 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 6721 struct phy_test_mode test_mode; 6722 enum dmub_phy_fsm_state state; 6723 uint32_t status; 6724 uint8_t pad; 6725 }; 6726 6727 /** 6728 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6729 */ 6730 struct dmub_rb_cmd_transmitter_set_phy_fsm { 6731 struct dmub_cmd_header header; /**< header */ 6732 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 6733 }; 6734 6735 /** 6736 * Maximum number of bytes a chunk sent to DMUB for parsing 6737 */ 6738 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 6739 6740 /** 6741 * Represent a chunk of CEA blocks sent to DMUB for parsing 6742 */ 6743 struct dmub_cmd_send_edid_cea { 6744 uint16_t offset; /**< offset into the CEA block */ 6745 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 6746 uint16_t cea_total_length; /**< total length of the CEA block */ 6747 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 6748 uint8_t pad[3]; /**< padding and for future expansion */ 6749 }; 6750 6751 /** 6752 * Result of VSDB parsing from CEA block 6753 */ 6754 struct dmub_cmd_edid_cea_amd_vsdb { 6755 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 6756 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 6757 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 6758 uint16_t min_frame_rate; /**< Maximum frame rate */ 6759 uint16_t max_frame_rate; /**< Minimum frame rate */ 6760 uint8_t freesync_mccs_vcp_code; /**< Freesync MCCS VCP code */ 6761 }; 6762 6763 /** 6764 * Result of sending a CEA chunk 6765 */ 6766 struct dmub_cmd_edid_cea_ack { 6767 uint16_t offset; /**< offset of the chunk into the CEA block */ 6768 uint8_t success; /**< 1 if this sending of chunk succeeded */ 6769 uint8_t pad; /**< padding and for future expansion */ 6770 }; 6771 6772 /** 6773 * Specify whether the result is an ACK/NACK or the parsing has finished 6774 */ 6775 enum dmub_cmd_edid_cea_reply_type { 6776 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 6777 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 6778 }; 6779 6780 /** 6781 * Definition of a DMUB_CMD__EDID_CEA command. 6782 */ 6783 struct dmub_rb_cmd_edid_cea { 6784 struct dmub_cmd_header header; /**< Command header */ 6785 union dmub_cmd_edid_cea_data { 6786 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 6787 struct dmub_cmd_edid_cea_output { /**< output with results */ 6788 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 6789 union { 6790 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 6791 struct dmub_cmd_edid_cea_ack ack; 6792 }; 6793 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 6794 } data; /**< Command data */ 6795 6796 }; 6797 6798 /** 6799 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 6800 */ 6801 struct dmub_cmd_cable_id_input { 6802 uint8_t phy_inst; /**< phy inst for cable id data */ 6803 }; 6804 6805 /** 6806 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 6807 */ 6808 struct dmub_cmd_cable_id_output { 6809 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 6810 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 6811 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 6812 uint8_t RESERVED :2; /**< reserved means not defined */ 6813 }; 6814 6815 /** 6816 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 6817 */ 6818 struct dmub_rb_cmd_get_usbc_cable_id { 6819 struct dmub_cmd_header header; /**< Command header */ 6820 /** 6821 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 6822 */ 6823 union dmub_cmd_cable_id_data { 6824 struct dmub_cmd_cable_id_input input; /**< Input */ 6825 struct dmub_cmd_cable_id_output output; /**< Output */ 6826 uint8_t output_raw; /**< Raw data output */ 6827 } data; 6828 }; 6829 6830 enum dmub_cmd_fused_io_sub_type { 6831 DMUB_CMD__FUSED_IO_EXECUTE = 0, 6832 DMUB_CMD__FUSED_IO_ABORT = 1, 6833 }; 6834 6835 enum dmub_cmd_fused_request_type { 6836 FUSED_REQUEST_READ, 6837 FUSED_REQUEST_WRITE, 6838 FUSED_REQUEST_POLL, 6839 }; 6840 6841 enum dmub_cmd_fused_request_status { 6842 FUSED_REQUEST_STATUS_SUCCESS, 6843 FUSED_REQUEST_STATUS_BEGIN, 6844 FUSED_REQUEST_STATUS_SUBMIT, 6845 FUSED_REQUEST_STATUS_REPLY, 6846 FUSED_REQUEST_STATUS_POLL, 6847 FUSED_REQUEST_STATUS_ABORTED, 6848 FUSED_REQUEST_STATUS_FAILED = 0x80, 6849 FUSED_REQUEST_STATUS_INVALID, 6850 FUSED_REQUEST_STATUS_BUSY, 6851 FUSED_REQUEST_STATUS_TIMEOUT, 6852 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 6853 }; 6854 6855 struct dmub_cmd_fused_request { 6856 uint8_t status; 6857 uint8_t type : 2; 6858 uint8_t _reserved0 : 3; 6859 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 6860 uint8_t identifier; 6861 uint8_t _reserved1; 6862 uint32_t timeout_us; 6863 union dmub_cmd_fused_request_location { 6864 struct dmub_cmd_fused_request_location_i2c { 6865 uint8_t is_aux : 1; // False 6866 uint8_t ddc_line : 3; 6867 uint8_t over_aux : 1; 6868 uint8_t _reserved0 : 3; 6869 uint8_t address; 6870 uint8_t offset; 6871 uint8_t length; 6872 } i2c; 6873 struct dmub_cmd_fused_request_location_aux { 6874 uint32_t is_aux : 1; // True 6875 uint32_t ddc_line : 3; 6876 uint32_t address : 20; 6877 uint32_t length : 8; // Automatically split into 16B transactions 6878 } aux; 6879 } u; 6880 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 6881 }; 6882 6883 struct dmub_rb_cmd_fused_io { 6884 struct dmub_cmd_header header; 6885 struct dmub_cmd_fused_request request; 6886 }; 6887 6888 /** 6889 * Command type of a DMUB_CMD__SECURE_DISPLAY command 6890 */ 6891 enum dmub_cmd_secure_display_type { 6892 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 6893 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 6894 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 6895 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 6896 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 6897 }; 6898 6899 #define MAX_ROI_NUM 2 6900 6901 struct dmub_cmd_roi_info { 6902 uint16_t x_start; 6903 uint16_t x_end; 6904 uint16_t y_start; 6905 uint16_t y_end; 6906 uint8_t otg_id; 6907 uint8_t phy_id; 6908 }; 6909 6910 struct dmub_cmd_roi_window_ctl { 6911 uint16_t x_start; 6912 uint16_t x_end; 6913 uint16_t y_start; 6914 uint16_t y_end; 6915 bool enable; 6916 }; 6917 6918 struct dmub_cmd_roi_ctl_info { 6919 uint8_t otg_id; 6920 uint8_t phy_id; 6921 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 6922 }; 6923 6924 /** 6925 * Definition of a DMUB_CMD__SECURE_DISPLAY command 6926 */ 6927 struct dmub_rb_cmd_secure_display { 6928 struct dmub_cmd_header header; 6929 /** 6930 * Data passed from driver to dmub firmware. 6931 */ 6932 struct dmub_cmd_roi_info roi_info; 6933 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 6934 }; 6935 6936 /** 6937 * Command type of a DMUB_CMD__PSP command 6938 */ 6939 enum dmub_cmd_psp_type { 6940 DMUB_CMD__PSP_ASSR_ENABLE = 0 6941 }; 6942 6943 /** 6944 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 6945 */ 6946 struct dmub_cmd_assr_enable_data { 6947 /** 6948 * ASSR enable or disable. 6949 */ 6950 uint8_t enable; 6951 /** 6952 * PHY port type. 6953 * Indicates eDP / non-eDP port type 6954 */ 6955 uint8_t phy_port_type; 6956 /** 6957 * PHY port ID. 6958 */ 6959 uint8_t phy_port_id; 6960 /** 6961 * Link encoder index. 6962 */ 6963 uint8_t link_enc_index; 6964 /** 6965 * HPO mode. 6966 */ 6967 uint8_t hpo_mode; 6968 6969 /** 6970 * Reserved field. 6971 */ 6972 uint8_t reserved[7]; 6973 }; 6974 6975 /** 6976 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6977 */ 6978 struct dmub_rb_cmd_assr_enable { 6979 /** 6980 * Command header. 6981 */ 6982 struct dmub_cmd_header header; 6983 6984 /** 6985 * Assr data. 6986 */ 6987 struct dmub_cmd_assr_enable_data assr_data; 6988 6989 /** 6990 * Reserved field. 6991 */ 6992 uint32_t reserved[3]; 6993 }; 6994 6995 /** 6996 * Current definition of "ips_mode" from driver 6997 */ 6998 enum ips_residency_mode { 6999 IPS_RESIDENCY__IPS1_MAX, 7000 IPS_RESIDENCY__IPS2, 7001 IPS_RESIDENCY__IPS1_RCG, // refers to IPS0 + RCG 7002 IPS_RESIDENCY__IPS1_ONO2_ON, 7003 IPS_RESIDENCY__IPS1_Z8_RETENTION, 7004 IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, 7005 IPS_RESIDENCY__PG_ONO_CURRENT_STATE 7006 }; 7007 7008 #define NUM_IPS_HISTOGRAM_BUCKETS 16 7009 7010 /** 7011 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 7012 */ 7013 struct dmub_ips_residency_info { 7014 uint32_t residency_millipercent; 7015 uint32_t entry_counter; 7016 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 7017 uint64_t total_time_us; 7018 uint64_t total_inactive_time_us; 7019 uint32_t ono_pg_state_at_collection; 7020 uint32_t ono_pg_state_last_seen_in_ips; 7021 }; 7022 7023 /** 7024 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 7025 */ 7026 struct dmub_cmd_ips_residency_cntl_data { 7027 uint8_t panel_inst; 7028 uint8_t start_measurement; 7029 uint8_t padding[2]; // align to 4-byte boundary 7030 }; 7031 7032 struct dmub_rb_cmd_ips_residency_cntl { 7033 struct dmub_cmd_header header; 7034 struct dmub_cmd_ips_residency_cntl_data cntl_data; 7035 }; 7036 7037 /** 7038 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 7039 */ 7040 struct dmub_cmd_ips_query_residency_info_data { 7041 union dmub_addr dest; 7042 uint32_t size; 7043 uint32_t ips_mode; 7044 uint8_t panel_inst; 7045 uint8_t padding[3]; // align to 4-byte boundary 7046 }; 7047 7048 struct dmub_rb_cmd_ips_query_residency_info { 7049 struct dmub_cmd_header header; 7050 struct dmub_cmd_ips_query_residency_info_data info_data; 7051 }; 7052 7053 /** 7054 * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command. 7055 */ 7056 struct dmub_cmd_cursor_offload_init_data { 7057 union dmub_addr state_addr; /**< State address for dmub_cursor_offload */ 7058 uint32_t state_size; /**< State size for dmub_cursor_offload */ 7059 }; 7060 7061 /** 7062 * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload. 7063 */ 7064 struct dmub_rb_cmd_cursor_offload_init { 7065 struct dmub_cmd_header header; 7066 struct dmub_cmd_cursor_offload_init_data init_data; 7067 }; 7068 7069 /** 7070 * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command. 7071 */ 7072 struct dmub_cmd_cursor_offload_stream_data { 7073 uint32_t otg_inst: 4; /**< OTG instance to control */ 7074 uint32_t reserved: 28; /**< Reserved for future use */ 7075 uint32_t line_time_in_ns; /**< Line time in ns for the OTG */ 7076 uint32_t v_total_max; /**< OTG v_total_max */ 7077 }; 7078 7079 /** 7080 * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload. 7081 */ 7082 struct dmub_rb_cmd_cursor_offload_stream_cntl { 7083 struct dmub_cmd_header header; 7084 struct dmub_cmd_cursor_offload_stream_data data; 7085 }; 7086 7087 /** 7088 * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command. 7089 */ 7090 struct dmub_cmd_pr_enable_data { 7091 /** 7092 * Panel Replay enable or disable. 7093 */ 7094 uint8_t enable; 7095 /** 7096 * Panel Instance. 7097 * Panel isntance to identify which replay_state to use 7098 * Currently the support is only for 0 or 1 7099 */ 7100 uint8_t panel_inst; 7101 /** 7102 * Phy state to enter. 7103 * Values to use are defined in dmub_phy_fsm_state 7104 */ 7105 uint8_t phy_fsm_state; 7106 /** 7107 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 7108 * Set this using enum phy_link_rate. 7109 * This does not support HDMI/DP2 for now. 7110 */ 7111 uint8_t phy_rate; 7112 /** 7113 * @hpo_stream_enc_inst: HPO stream encoder instance 7114 */ 7115 uint8_t hpo_stream_enc_inst; 7116 /** 7117 * @hpo_link_enc_inst: HPO link encoder instance 7118 */ 7119 uint8_t hpo_link_enc_inst; 7120 /** 7121 * @pad: Align structure to 4 byte boundary. 7122 */ 7123 uint8_t pad[2]; 7124 }; 7125 7126 /** 7127 * Definition of a DMUB_CMD__PR_ENABLE command. 7128 * Panel Replay enable/disable is controlled using action in data. 7129 */ 7130 struct dmub_rb_cmd_pr_enable { 7131 /** 7132 * Command header. 7133 */ 7134 struct dmub_cmd_header header; 7135 7136 struct dmub_cmd_pr_enable_data data; 7137 }; 7138 7139 /** 7140 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 7141 */ 7142 struct dmub_cmd_pr_copy_settings_data { 7143 /** 7144 * Flags that can be set by driver to change some replay behaviour. 7145 */ 7146 union pr_debug_flags debug; 7147 7148 /** 7149 * @flags: Flags used to determine feature functionality. 7150 */ 7151 union pr_hw_flags flags; 7152 7153 /** 7154 * DPP HW instance. 7155 */ 7156 uint8_t dpp_inst; 7157 /** 7158 * OTG HW instance. 7159 */ 7160 uint8_t otg_inst; 7161 /** 7162 * DIG FE HW instance. 7163 */ 7164 uint8_t digfe_inst; 7165 /** 7166 * DIG BE HW instance. 7167 */ 7168 uint8_t digbe_inst; 7169 /** 7170 * AUX HW instance. 7171 */ 7172 uint8_t aux_inst; 7173 /** 7174 * Panel Instance. 7175 * Panel isntance to identify which psr_state to use 7176 * Currently the support is only for 0 or 1 7177 */ 7178 uint8_t panel_inst; 7179 /** 7180 * PHY instance. 7181 */ 7182 uint8_t dpphy_inst; 7183 /** 7184 * Determines if SMU optimzations are enabled/disabled. 7185 */ 7186 uint8_t smu_optimizations_en; 7187 /** 7188 * Length of each horizontal line in ns. 7189 */ 7190 uint32_t line_time_in_ns; 7191 /* 7192 * Use FSFT afftet pixel clk 7193 */ 7194 uint32_t pix_clk_100hz; 7195 /* 7196 * Use Original pixel clock 7197 */ 7198 uint32_t sink_pix_clk_100hz; 7199 /** 7200 * Use for AUX-less ALPM LFPS wake operation 7201 */ 7202 struct dmub_alpm_auxless_data auxless_alpm_data; 7203 /** 7204 * DSC Slice height. 7205 */ 7206 uint16_t dsc_slice_height; 7207 /* 7208 * Use FSM state for Replay power up/down 7209 */ 7210 uint8_t use_phy_fsm; 7211 /** 7212 * @hpo_stream_enc_inst: HPO stream encoder instance 7213 */ 7214 uint8_t hpo_stream_enc_inst; 7215 /** 7216 * @hpo_link_enc_inst: HPO link encoder instance 7217 */ 7218 uint8_t hpo_link_enc_inst; 7219 /* 7220 * Selective Update granularity needed. 7221 */ 7222 uint8_t su_granularity_needed; 7223 /* 7224 * Horizontal granularity for Selective Update. 7225 */ 7226 uint16_t su_x_granularity; 7227 /* 7228 * Extended caps of vertical granularity for Selective Update. 7229 */ 7230 uint16_t su_y_granularity_extended_caps; 7231 /* 7232 * Vertical granularity for Selective Update. 7233 */ 7234 uint8_t su_y_granularity; 7235 /** 7236 * @main_link_activity_option: Indicates main link activity option selected 7237 */ 7238 uint8_t main_link_activity_option; 7239 }; 7240 7241 /** 7242 * Definition of a DMUB_CMD__PR_COPY_SETTINGS command. 7243 */ 7244 struct dmub_rb_cmd_pr_copy_settings { 7245 /** 7246 * Command header. 7247 */ 7248 struct dmub_cmd_header header; 7249 /** 7250 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 7251 */ 7252 struct dmub_cmd_pr_copy_settings_data data; 7253 }; 7254 7255 union dmub_pr_runtime_flags { 7256 struct { 7257 uint32_t disable_abm_optimization : 1; // Disable ABM optimization for PR 7258 } bitfields; 7259 uint32_t u32All; 7260 }; 7261 7262 struct dmub_cmd_pr_update_state_data { 7263 /** 7264 * Panel Instance. 7265 * Panel isntance to identify which psr_state to use 7266 * Currently the support is only for 0 or 1 7267 */ 7268 uint8_t panel_inst; 7269 7270 uint8_t pad[3]; // align to 4-byte boundary 7271 /* 7272 * Update flags to control the update behavior. 7273 */ 7274 uint32_t update_flag; 7275 /** 7276 * state/data to set. 7277 */ 7278 uint32_t coasting_vtotal; 7279 uint32_t sync_mode; 7280 uint32_t pseudo_vtotal; 7281 7282 union dmub_pr_runtime_flags pr_runtime_flags; 7283 }; 7284 7285 struct dmub_cmd_pr_general_cmd_data { 7286 /** 7287 * Panel Instance. 7288 * Panel isntance to identify which psr_state to use 7289 * Currently the support is only for 0 or 1 7290 */ 7291 uint8_t panel_inst; 7292 /** 7293 * subtype: PR general cmd sub type 7294 */ 7295 uint8_t subtype; 7296 7297 uint8_t pad[2]; 7298 /** 7299 * config data by different subtypes 7300 */ 7301 union { 7302 uint32_t u32All; 7303 } data; 7304 }; 7305 7306 /** 7307 * Definition of a DMUB_CMD__PR_UPDATE_STATE command. 7308 */ 7309 struct dmub_rb_cmd_pr_update_state { 7310 /** 7311 * Command header. 7312 */ 7313 struct dmub_cmd_header header; 7314 /** 7315 * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command. 7316 */ 7317 struct dmub_cmd_pr_update_state_data data; 7318 }; 7319 7320 /** 7321 * Definition of a DMUB_CMD__PR_GENERAL_CMD command. 7322 */ 7323 struct dmub_rb_cmd_pr_general_cmd { 7324 /** 7325 * Command header. 7326 */ 7327 struct dmub_cmd_header header; 7328 /** 7329 * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command. 7330 */ 7331 struct dmub_cmd_pr_general_cmd_data data; 7332 }; 7333 7334 /** 7335 * Command type of a DMUB_CMD__BOOT_TIME_CRC command 7336 */ 7337 enum dmub_cmd_boot_time_crc_type { 7338 DMUB_CMD__BOOT_TIME_CRC_INIT_MEM = 0 7339 }; 7340 7341 /** 7342 * Data passed from driver to FW in a DMUB_CMD__BOOT_TIME_CRC_INIT command. 7343 */ 7344 struct dmub_cmd_boot_time_crc_init_data { 7345 union dmub_addr buffer_addr; 7346 uint32_t buffer_size; 7347 }; 7348 7349 /** 7350 * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command. 7351 */ 7352 struct dmub_rb_cmd_boot_time_crc_init { 7353 struct dmub_cmd_header header; 7354 struct dmub_cmd_boot_time_crc_init_data data; 7355 }; 7356 7357 /** 7358 * union dmub_rb_cmd - DMUB inbox command. 7359 */ 7360 union dmub_rb_cmd { 7361 /** 7362 * Elements shared with all commands. 7363 */ 7364 struct dmub_rb_cmd_common cmd_common; 7365 /** 7366 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 7367 */ 7368 struct dmub_rb_cmd_read_modify_write read_modify_write; 7369 /** 7370 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 7371 */ 7372 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 7373 /** 7374 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 7375 */ 7376 struct dmub_rb_cmd_burst_write burst_write; 7377 /** 7378 * Definition of a DMUB_CMD__REG_REG_WAIT command. 7379 */ 7380 struct dmub_rb_cmd_reg_wait reg_wait; 7381 /** 7382 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 7383 */ 7384 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 7385 /** 7386 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 7387 */ 7388 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 7389 /** 7390 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 7391 */ 7392 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 7393 /** 7394 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 7395 */ 7396 struct dmub_rb_cmd_dpphy_init dpphy_init; 7397 /** 7398 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 7399 */ 7400 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 7401 /** 7402 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 7403 */ 7404 struct dmub_rb_cmd_domain_control domain_control; 7405 /** 7406 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 7407 */ 7408 struct dmub_rb_cmd_psr_set_version psr_set_version; 7409 /** 7410 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 7411 */ 7412 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 7413 /** 7414 * Definition of a DMUB_CMD__PSR_ENABLE command. 7415 */ 7416 struct dmub_rb_cmd_psr_enable psr_enable; 7417 /** 7418 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 7419 */ 7420 struct dmub_rb_cmd_psr_set_level psr_set_level; 7421 /** 7422 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 7423 */ 7424 struct dmub_rb_cmd_psr_force_static psr_force_static; 7425 /** 7426 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 7427 */ 7428 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 7429 /** 7430 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 7431 */ 7432 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 7433 /** 7434 * Definition of a DMUB_CMD__HW_LOCK command. 7435 * Command is used by driver and FW. 7436 */ 7437 struct dmub_rb_cmd_lock_hw lock_hw; 7438 /** 7439 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 7440 */ 7441 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 7442 /** 7443 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 7444 */ 7445 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 7446 /** 7447 * Definition of a DMUB_CMD__PLAT_54186_WA command. 7448 */ 7449 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 7450 /** 7451 * Definition of a DMUB_CMD__MALL command. 7452 */ 7453 struct dmub_rb_cmd_mall mall; 7454 7455 /** 7456 * Definition of a DMUB_CMD__CAB command. 7457 */ 7458 struct dmub_rb_cmd_cab_for_ss cab; 7459 7460 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 7461 7462 /** 7463 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 7464 */ 7465 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 7466 7467 /** 7468 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 7469 */ 7470 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 7471 7472 /** 7473 * Definition of DMUB_CMD__PANEL_CNTL commands. 7474 */ 7475 struct dmub_rb_cmd_panel_cntl panel_cntl; 7476 7477 /** 7478 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 7479 */ 7480 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 7481 7482 /** 7483 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 7484 */ 7485 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 7486 7487 /** 7488 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 7489 */ 7490 struct dmub_rb_cmd_abm_set_level abm_set_level; 7491 7492 /** 7493 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 7494 */ 7495 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 7496 7497 /** 7498 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 7499 */ 7500 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 7501 7502 /** 7503 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 7504 */ 7505 struct dmub_rb_cmd_abm_init_config abm_init_config; 7506 7507 /** 7508 * Definition of a DMUB_CMD__ABM_PAUSE command. 7509 */ 7510 struct dmub_rb_cmd_abm_pause abm_pause; 7511 7512 /** 7513 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 7514 */ 7515 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 7516 7517 /** 7518 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 7519 */ 7520 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 7521 7522 /** 7523 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 7524 */ 7525 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 7526 7527 /** 7528 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 7529 */ 7530 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 7531 7532 /** 7533 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 7534 */ 7535 struct dmub_rb_cmd_abm_set_event abm_set_event; 7536 7537 /** 7538 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 7539 */ 7540 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 7541 7542 /** 7543 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 7544 */ 7545 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 7546 7547 /** 7548 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 7549 */ 7550 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 7551 7552 /** 7553 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 7554 */ 7555 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 7556 struct dmub_rb_cmd_drr_update drr_update; 7557 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 7558 7559 /** 7560 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 7561 */ 7562 struct dmub_rb_cmd_lvtma_control lvtma_control; 7563 /** 7564 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 7565 */ 7566 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 7567 /** 7568 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 7569 */ 7570 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 7571 /** 7572 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 7573 */ 7574 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 7575 /** 7576 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 7577 */ 7578 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 7579 /** 7580 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 7581 */ 7582 struct dmub_rb_cmd_set_config_request set_config_request; 7583 /** 7584 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 7585 */ 7586 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 7587 /** 7588 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 7589 */ 7590 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 7591 /** 7592 * Definition of a DMUB_CMD__EDID_CEA command. 7593 */ 7594 struct dmub_rb_cmd_edid_cea edid_cea; 7595 /** 7596 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 7597 */ 7598 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 7599 7600 /** 7601 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 7602 */ 7603 struct dmub_rb_cmd_query_hpd_state query_hpd; 7604 /** 7605 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 7606 */ 7607 struct dmub_rb_cmd_secure_display secure_display; 7608 7609 /** 7610 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 7611 */ 7612 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 7613 7614 /** 7615 * Definition of a DMUB_CMD__CACP_SET_PIPE command. 7616 */ 7617 struct dmub_rb_cmd_cacp_set_pipe cacp_set_pipe; 7618 7619 /** 7620 * Definition of a DMUB_CMD__CACP_SET_LEVEL command. 7621 */ 7622 struct dmub_rb_cmd_cacp_set_level cacp_set_level; 7623 7624 /** 7625 * Definition of a DMUB_CMD__CACP_SET_EVENT command. 7626 */ 7627 struct dmub_rb_cmd_cacp_set_event cacp_set_event; 7628 7629 /** 7630 * Definition of a DMUB_CMD__CACP_INIT_CONFIG command. 7631 */ 7632 struct dmub_rb_cmd_cacp_init_config cacp_init_config; 7633 7634 /** 7635 * Definition of a DMUB_CMD__CACP_PAUSE command. 7636 */ 7637 struct dmub_rb_cmd_cacp_pause cacp_pause; 7638 7639 /** 7640 * Definition of a DMUB_CMD__CACP_SET_BACKLIGHT command. 7641 */ 7642 struct dmub_rb_cmd_cacp_set_backlight cacp_set_backlight; 7643 7644 /** 7645 * Definition of a DMUB_CMD__CACP_SET_PWM_FRAC command. 7646 */ 7647 struct dmub_rb_cmd_cacp_set_pwm_frac cacp_set_pwm_frac; 7648 7649 /** 7650 * Definition of a DMUB_CMD__CACP_GET_HISTOGRAM command. 7651 */ 7652 struct dmub_rb_cmd_cacp_get_histogram cacp_get_histogram; 7653 7654 /** 7655 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 7656 */ 7657 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 7658 /** 7659 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 7660 */ 7661 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 7662 /* 7663 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 7664 */ 7665 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 7666 /** 7667 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 7668 */ 7669 struct dmub_rb_cmd_replay_enable replay_enable; 7670 /** 7671 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 7672 */ 7673 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 7674 /** 7675 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 7676 */ 7677 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 7678 /** 7679 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 7680 */ 7681 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 7682 7683 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 7684 /** 7685 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 7686 */ 7687 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 7688 /** 7689 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 7690 */ 7691 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 7692 /** 7693 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 7694 */ 7695 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 7696 /** 7697 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 7698 */ 7699 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 7700 /** 7701 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 7702 */ 7703 struct dmub_rb_cmd_assr_enable assr_enable; 7704 7705 struct dmub_rb_cmd_fams2 fams2_config; 7706 7707 struct dmub_rb_cmd_ib ib_fams2_config; 7708 7709 struct dmub_rb_cmd_ib ib_fams2_debug_meta; 7710 7711 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 7712 7713 struct dmub_rb_cmd_fams2_flip fams2_flip; 7714 7715 struct dmub_rb_cmd_fused_io fused_io; 7716 7717 /** 7718 * Definition of a DMUB_CMD__LSDMA command. 7719 */ 7720 struct dmub_rb_cmd_lsdma lsdma; 7721 7722 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 7723 7724 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 7725 /** 7726 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command. 7727 */ 7728 struct dmub_rb_cmd_cursor_offload_init cursor_offload_init; 7729 /** 7730 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands. 7731 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE 7732 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE 7733 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM 7734 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR 7735 */ 7736 struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; 7737 /** 7738 * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 7739 */ 7740 struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable; 7741 /** 7742 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 7743 */ 7744 struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll; 7745 /* 7746 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 7747 */ 7748 struct dmub_rb_cmd_pr_copy_settings pr_copy_settings; 7749 /** 7750 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 7751 */ 7752 struct dmub_rb_cmd_pr_enable pr_enable; 7753 7754 struct dmub_rb_cmd_pr_update_state pr_update_state; 7755 7756 struct dmub_rb_cmd_pr_general_cmd pr_general_cmd; 7757 /** 7758 * Definition of a DMUB_CMD__IHC command. 7759 */ 7760 struct dmub_rb_cmd_ihc ihc; 7761 /** 7762 * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command. 7763 */ 7764 struct dmub_rb_cmd_boot_time_crc_init boot_time_crc_init; 7765 }; 7766 7767 /** 7768 * union dmub_rb_out_cmd - Outbox command 7769 */ 7770 union dmub_rb_out_cmd { 7771 /** 7772 * Parameters common to every command. 7773 */ 7774 struct dmub_rb_cmd_common cmd_common; 7775 /** 7776 * AUX reply command. 7777 */ 7778 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 7779 /** 7780 * HPD notify command. 7781 */ 7782 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 7783 /** 7784 * SET_CONFIG reply command. 7785 */ 7786 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 7787 /** 7788 * DPIA notification command. 7789 */ 7790 struct dmub_rb_cmd_dpia_notification dpia_notification; 7791 /** 7792 * HPD sense notification command. 7793 */ 7794 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 7795 struct dmub_rb_cmd_fused_io fused_io; 7796 }; 7797 #pragma pack(pop) 7798 7799 7800 //============================================================================== 7801 //</DMUB_CMD>=================================================================== 7802 //============================================================================== 7803 //< DMUB_RB>==================================================================== 7804 //============================================================================== 7805 7806 /** 7807 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 7808 */ 7809 struct dmub_rb_init_params { 7810 void *ctx; /**< Caller provided context pointer */ 7811 void *base_address; /**< CPU base address for ring's data */ 7812 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 7813 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 7814 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 7815 }; 7816 7817 /** 7818 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 7819 */ 7820 struct dmub_rb { 7821 void *base_address; /**< CPU address for the ring's data */ 7822 uint32_t rptr; /**< Read pointer for consumer in bytes */ 7823 uint32_t wrpt; /**< Write pointer for producer in bytes */ 7824 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 7825 7826 void *ctx; /**< Caller provided context pointer */ 7827 void *dmub; /**< Pointer to the DMUB interface */ 7828 }; 7829 7830 /** 7831 * @brief Checks if the ringbuffer is empty. 7832 * 7833 * @param rb DMUB Ringbuffer 7834 * @return true if empty 7835 * @return false otherwise 7836 */ 7837 static inline bool dmub_rb_empty(struct dmub_rb *rb) 7838 { 7839 return (rb->wrpt == rb->rptr); 7840 } 7841 7842 /** 7843 * @brief gets number of outstanding requests in the RB 7844 * 7845 * @param rb DMUB Ringbuffer 7846 * @return true if full 7847 */ 7848 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 7849 { 7850 uint32_t data_count; 7851 7852 if (rb->wrpt >= rb->rptr) 7853 data_count = rb->wrpt - rb->rptr; 7854 else 7855 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7856 7857 return data_count / DMUB_RB_CMD_SIZE; 7858 } 7859 7860 /** 7861 * @brief gets number of free buffers in the RB 7862 * 7863 * @param rb DMUB Ringbuffer 7864 * @return true if full 7865 */ 7866 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 7867 { 7868 uint32_t data_count; 7869 7870 if (rb->wrpt >= rb->rptr) 7871 data_count = rb->wrpt - rb->rptr; 7872 else 7873 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7874 7875 /* +1 because 1 entry is always unusable */ 7876 data_count += DMUB_RB_CMD_SIZE; 7877 7878 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 7879 } 7880 7881 /** 7882 * @brief Checks if the ringbuffer is full 7883 * 7884 * @param rb DMUB Ringbuffer 7885 * @return true if full 7886 * @return false otherwise 7887 */ 7888 static inline bool dmub_rb_full(struct dmub_rb *rb) 7889 { 7890 uint32_t data_count; 7891 7892 if (rb->wrpt >= rb->rptr) 7893 data_count = rb->wrpt - rb->rptr; 7894 else 7895 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7896 7897 /* -1 because 1 entry is always unusable */ 7898 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 7899 } 7900 7901 /** 7902 * @brief Pushes a command into the ringbuffer 7903 * 7904 * @param rb DMUB ringbuffer 7905 * @param cmd The command to push 7906 * @return true if the ringbuffer was not full 7907 * @return false otherwise 7908 */ 7909 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 7910 const union dmub_rb_cmd *cmd) 7911 { 7912 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 7913 const uint8_t *src = (const uint8_t *)cmd; 7914 uint8_t i; 7915 7916 if (rb->capacity == 0) 7917 return false; 7918 7919 if (dmub_rb_full(rb)) 7920 return false; 7921 7922 // copying data 7923 for (i = 0; i < DMUB_RB_CMD_SIZE; i++) 7924 *dst++ = *src++; 7925 7926 rb->wrpt += DMUB_RB_CMD_SIZE; 7927 7928 if (rb->wrpt >= rb->capacity) 7929 rb->wrpt %= rb->capacity; 7930 7931 return true; 7932 } 7933 7934 /** 7935 * @brief Pushes a command into the DMUB outbox ringbuffer 7936 * 7937 * @param rb DMUB outbox ringbuffer 7938 * @param cmd Outbox command 7939 * @return true if not full 7940 * @return false otherwise 7941 */ 7942 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 7943 const union dmub_rb_out_cmd *cmd) 7944 { 7945 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 7946 const uint8_t *src = (const uint8_t *)cmd; 7947 7948 if (rb->capacity == 0) 7949 return false; 7950 7951 if (dmub_rb_full(rb)) 7952 return false; 7953 7954 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 7955 7956 rb->wrpt += DMUB_RB_CMD_SIZE; 7957 7958 if (rb->wrpt >= rb->capacity) 7959 rb->wrpt %= rb->capacity; 7960 7961 return true; 7962 } 7963 7964 /** 7965 * @brief Returns the next unprocessed command in the ringbuffer. 7966 * 7967 * @param rb DMUB ringbuffer 7968 * @param cmd The command to return 7969 * @return true if not empty 7970 * @return false otherwise 7971 */ 7972 static inline bool dmub_rb_front(struct dmub_rb *rb, 7973 union dmub_rb_cmd **cmd) 7974 { 7975 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 7976 7977 if (dmub_rb_empty(rb)) 7978 return false; 7979 7980 *cmd = (union dmub_rb_cmd *)rb_cmd; 7981 7982 return true; 7983 } 7984 7985 /** 7986 * @brief Determines the next ringbuffer offset. 7987 * 7988 * @param rb DMUB inbox ringbuffer 7989 * @param num_cmds Number of commands 7990 * @param next_rptr The next offset in the ringbuffer 7991 */ 7992 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 7993 uint32_t num_cmds, 7994 uint32_t *next_rptr) 7995 { 7996 if (rb->capacity == 0) 7997 return; 7998 7999 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 8000 8001 if (*next_rptr >= rb->capacity) 8002 *next_rptr %= rb->capacity; 8003 } 8004 8005 /** 8006 * @brief Returns a pointer to a command in the inbox. 8007 * 8008 * @param rb DMUB inbox ringbuffer 8009 * @param cmd The inbox command to return 8010 * @param rptr The ringbuffer offset 8011 * @return true if not empty 8012 * @return false otherwise 8013 */ 8014 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 8015 union dmub_rb_cmd **cmd, 8016 uint32_t rptr) 8017 { 8018 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 8019 8020 if (dmub_rb_empty(rb)) 8021 return false; 8022 8023 *cmd = (union dmub_rb_cmd *)rb_cmd; 8024 8025 return true; 8026 } 8027 8028 /** 8029 * @brief Returns the next unprocessed command in the outbox. 8030 * 8031 * @param rb DMUB outbox ringbuffer 8032 * @param cmd The outbox command to return 8033 * @return true if not empty 8034 * @return false otherwise 8035 */ 8036 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 8037 union dmub_rb_out_cmd *cmd) 8038 { 8039 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 8040 uint64_t *dst = (uint64_t *)cmd; 8041 uint8_t i; 8042 8043 if (dmub_rb_empty(rb)) 8044 return false; 8045 8046 // copying data 8047 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 8048 *dst++ = *src++; 8049 8050 return true; 8051 } 8052 8053 /** 8054 * @brief Removes the front entry in the ringbuffer. 8055 * 8056 * @param rb DMUB ringbuffer 8057 * @return true if the command was removed 8058 * @return false if there were no commands 8059 */ 8060 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 8061 { 8062 if (rb->capacity == 0) 8063 return false; 8064 8065 if (dmub_rb_empty(rb)) 8066 return false; 8067 8068 rb->rptr += DMUB_RB_CMD_SIZE; 8069 8070 if (rb->rptr >= rb->capacity) 8071 rb->rptr %= rb->capacity; 8072 8073 return true; 8074 } 8075 8076 /** 8077 * @brief Flushes commands in the ringbuffer to framebuffer memory. 8078 * 8079 * Avoids a race condition where DMCUB accesses memory while 8080 * there are still writes in flight to framebuffer. 8081 * 8082 * @param rb DMUB ringbuffer 8083 */ 8084 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 8085 { 8086 uint32_t rptr = rb->rptr; 8087 uint32_t wptr = rb->wrpt; 8088 8089 if (rb->capacity == 0) 8090 return; 8091 8092 while (rptr != wptr) { 8093 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 8094 uint8_t i; 8095 8096 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 8097 (void)READ_ONCE(*data++); 8098 8099 rptr += DMUB_RB_CMD_SIZE; 8100 if (rptr >= rb->capacity) 8101 rptr %= rb->capacity; 8102 } 8103 } 8104 8105 /** 8106 * @brief Initializes a DMCUB ringbuffer 8107 * 8108 * @param rb DMUB ringbuffer 8109 * @param init_params initial configuration for the ringbuffer 8110 */ 8111 static inline void dmub_rb_init(struct dmub_rb *rb, 8112 struct dmub_rb_init_params *init_params) 8113 { 8114 rb->base_address = init_params->base_address; 8115 rb->capacity = init_params->capacity; 8116 rb->rptr = init_params->read_ptr; 8117 rb->wrpt = init_params->write_ptr; 8118 } 8119 8120 /** 8121 * @brief Copies output data from in/out commands into the given command. 8122 * 8123 * @param rb DMUB ringbuffer 8124 * @param cmd Command to copy data into 8125 */ 8126 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 8127 union dmub_rb_cmd *cmd) 8128 { 8129 // Copy rb entry back into command 8130 uint8_t *rd_ptr = (rb->rptr == 0) ? 8131 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 8132 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 8133 8134 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 8135 } 8136 8137 //============================================================================== 8138 //</DMUB_RB>==================================================================== 8139 //============================================================================== 8140 #endif /* _DMUB_CMD_H_ */ 8141