1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 #pragma pack(pop) 303 304 /** 305 * Dirty rect definition. 306 */ 307 struct dmub_rect { 308 /** 309 * Dirty rect x offset. 310 */ 311 uint32_t x; 312 313 /** 314 * Dirty rect y offset. 315 */ 316 uint32_t y; 317 318 /** 319 * Dirty rect width. 320 */ 321 uint32_t width; 322 323 /** 324 * Dirty rect height. 325 */ 326 uint32_t height; 327 }; 328 329 /** 330 * Flags that can be set by driver to change some PSR behaviour. 331 */ 332 union dmub_psr_debug_flags { 333 /** 334 * Debug flags. 335 */ 336 struct { 337 /** 338 * Enable visual confirm in FW. 339 */ 340 uint32_t visual_confirm : 1; 341 342 /** 343 * Force all selective updates to bw full frame updates. 344 */ 345 uint32_t force_full_frame_update : 1; 346 347 /** 348 * Use HW Lock Mgr object to do HW locking in FW. 349 */ 350 uint32_t use_hw_lock_mgr : 1; 351 352 /** 353 * Use TPS3 signal when restore main link. 354 */ 355 uint32_t force_wakeup_by_tps3 : 1; 356 357 /** 358 * Back to back flip, therefore cannot power down PHY 359 */ 360 uint32_t back_to_back_flip : 1; 361 362 /** 363 * Enable visual confirm for IPS 364 */ 365 uint32_t enable_ips_visual_confirm : 1; 366 } bitfields; 367 368 /** 369 * Union for debug flags. 370 */ 371 uint32_t u32All; 372 }; 373 374 /** 375 * Flags that can be set by driver to change some Replay behaviour. 376 */ 377 union replay_debug_flags { 378 struct { 379 /** 380 * 0x1 (bit 0) 381 * Enable visual confirm in FW. 382 */ 383 uint32_t visual_confirm : 1; 384 385 /** 386 * 0x2 (bit 1) 387 * @skip_crc: Set if need to skip CRC. 388 */ 389 uint32_t skip_crc : 1; 390 391 /** 392 * 0x4 (bit 2) 393 * @force_link_power_on: Force disable ALPM control 394 */ 395 uint32_t force_link_power_on : 1; 396 397 /** 398 * 0x8 (bit 3) 399 * @force_phy_power_on: Force phy power on 400 */ 401 uint32_t force_phy_power_on : 1; 402 403 /** 404 * 0x10 (bit 4) 405 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 406 */ 407 uint32_t timing_resync_disabled : 1; 408 409 /** 410 * 0x20 (bit 5) 411 * @skip_crtc_disabled: CRTC disable skipped 412 */ 413 uint32_t skip_crtc_disabled : 1; 414 415 /** 416 * 0x40 (bit 6) 417 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 418 */ 419 uint32_t force_defer_one_frame_update : 1; 420 421 /** 422 * 0x80 (bit 7) 423 * @disable_delay_alpm_on: Force disable delay alpm on 424 */ 425 uint32_t disable_delay_alpm_on : 1; 426 427 /** 428 * 0x100 (bit 8) 429 * @disable_desync_error_check: Force disable desync error check 430 */ 431 uint32_t disable_desync_error_check : 1; 432 433 /** 434 * 0x200 (bit 9) 435 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 436 */ 437 uint32_t force_self_update_when_abm_non_steady : 1; 438 439 /** 440 * 0x400 (bit 10) 441 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 442 * If we enter IPS2, the Visual confirm bar will change to yellow 443 */ 444 uint32_t enable_ips_visual_confirm : 1; 445 446 /** 447 * 0x800 (bit 11) 448 * @enable_ips_residency_profiling: Enable IPS residency profiling 449 */ 450 uint32_t enable_ips_residency_profiling : 1; 451 452 /** 453 * 0x1000 (bit 12) 454 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 455 */ 456 uint32_t enable_coasting_vtotal_check : 1; 457 /** 458 * 0x2000 (bit 13) 459 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 460 */ 461 uint32_t enable_visual_confirm_debug : 1; 462 463 uint32_t reserved : 18; 464 } bitfields; 465 466 uint32_t u32All; 467 }; 468 469 /** 470 * Flags record error state. 471 */ 472 union replay_visual_confirm_error_state_flags { 473 struct { 474 /** 475 * 0x1 (bit 0) - Desync Error flag. 476 */ 477 uint32_t desync_error : 1; 478 479 /** 480 * 0x2 (bit 1) - State Transition Error flag. 481 */ 482 uint32_t state_transition_error : 1; 483 484 /** 485 * 0x4 (bit 2) - Crc Error flag 486 */ 487 uint32_t crc_error : 1; 488 489 /** 490 * 0x8 (bit 3) - Reserved 491 */ 492 uint32_t reserved_3 : 1; 493 494 /** 495 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 496 * Added new debug flag to control DPCD. 497 */ 498 uint32_t incorrect_vtotal_in_static_screen : 1; 499 500 /** 501 * 0x20 (bit 5) - No doubled Refresh Rate. 502 */ 503 uint32_t no_double_rr : 1; 504 505 /** 506 * Reserved bit 6-7 507 */ 508 uint32_t reserved_6_7 : 2; 509 510 /** 511 * Reserved bit 9-31 512 */ 513 uint32_t reserved_9_31 : 24; 514 } bitfields; 515 516 uint32_t u32All; 517 }; 518 519 union replay_hw_flags { 520 struct { 521 /** 522 * @allow_alpm_fw_standby_mode: To indicate whether the 523 * ALPM FW standby mode is allowed 524 */ 525 uint32_t allow_alpm_fw_standby_mode : 1; 526 527 /* 528 * @dsc_enable_status: DSC enable status in driver 529 */ 530 uint32_t dsc_enable_status : 1; 531 532 /** 533 * @fec_enable_status: receive fec enable/disable status from driver 534 */ 535 uint32_t fec_enable_status : 1; 536 537 /* 538 * @smu_optimizations_en: SMU power optimization. 539 * Only when active display is Replay capable and display enters Replay. 540 * Trigger interrupt to SMU to powerup/down. 541 */ 542 uint32_t smu_optimizations_en : 1; 543 544 /** 545 * @phy_power_state: Indicates current phy power state 546 */ 547 uint32_t phy_power_state : 1; 548 549 /** 550 * @link_power_state: Indicates current link power state 551 */ 552 uint32_t link_power_state : 1; 553 /** 554 * Use TPS3 signal when restore main link. 555 */ 556 uint32_t force_wakeup_by_tps3 : 1; 557 /** 558 * @is_alpm_initialized: Indicates whether ALPM is initialized 559 */ 560 uint32_t is_alpm_initialized : 1; 561 562 /** 563 * @alpm_mode: Indicates ALPM mode selected 564 */ 565 uint32_t alpm_mode : 2; 566 } bitfields; 567 568 uint32_t u32All; 569 }; 570 571 union fw_assisted_mclk_switch_version { 572 struct { 573 uint8_t minor : 5; 574 uint8_t major : 3; 575 }; 576 uint8_t ver; 577 }; 578 579 /** 580 * DMUB feature capabilities. 581 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 582 */ 583 struct dmub_feature_caps { 584 /** 585 * Max PSR version supported by FW. 586 */ 587 uint8_t psr; 588 uint8_t fw_assisted_mclk_switch_ver; 589 uint8_t reserved[4]; 590 uint8_t subvp_psr_support; 591 uint8_t gecc_enable; 592 uint8_t replay_supported; 593 uint8_t replay_reserved[3]; 594 uint8_t abm_aux_backlight_support; 595 }; 596 597 struct dmub_visual_confirm_color { 598 /** 599 * Maximum 10 bits color value 600 */ 601 uint16_t color_r_cr; 602 uint16_t color_g_y; 603 uint16_t color_b_cb; 604 uint16_t panel_inst; 605 }; 606 607 //============================================================================== 608 //</DMUB_TYPES>================================================================= 609 //============================================================================== 610 //< DMUB_META>================================================================== 611 //============================================================================== 612 #pragma pack(push, 1) 613 614 /* Magic value for identifying dmub_fw_meta_info */ 615 #define DMUB_FW_META_MAGIC 0x444D5542 616 617 /* Offset from the end of the file to the dmub_fw_meta_info */ 618 #define DMUB_FW_META_OFFSET 0x24 619 620 /** 621 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 622 */ 623 union dmub_fw_meta_feature_bits { 624 struct { 625 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 626 uint32_t reserved : 31; 627 } bits; /**< status bits */ 628 uint32_t all; /**< 32-bit access to status bits */ 629 }; 630 631 /** 632 * struct dmub_fw_meta_info - metadata associated with fw binary 633 * 634 * NOTE: This should be considered a stable API. Fields should 635 * not be repurposed or reordered. New fields should be 636 * added instead to extend the structure. 637 * 638 * @magic_value: magic value identifying DMUB firmware meta info 639 * @fw_region_size: size of the firmware state region 640 * @trace_buffer_size: size of the tracebuffer region 641 * @fw_version: the firmware version information 642 * @dal_fw: 1 if the firmware is DAL 643 * @shared_state_size: size of the shared state region in bytes 644 * @shared_state_features: number of shared state features 645 */ 646 struct dmub_fw_meta_info { 647 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 648 uint32_t fw_region_size; /**< size of the firmware state region */ 649 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 650 uint32_t fw_version; /**< the firmware version information */ 651 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 652 uint8_t reserved[3]; /**< padding bits */ 653 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 654 uint16_t shared_state_features; /**< number of shared state features */ 655 uint16_t reserved2; /**< padding bytes */ 656 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 657 }; 658 659 /** 660 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 661 */ 662 union dmub_fw_meta { 663 struct dmub_fw_meta_info info; /**< metadata info */ 664 uint8_t reserved[64]; /**< padding bits */ 665 }; 666 667 #pragma pack(pop) 668 669 //============================================================================== 670 //< DMUB Trace Buffer>================================================================ 671 //============================================================================== 672 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 673 /** 674 * dmub_trace_code_t - firmware trace code, 32-bits 675 */ 676 typedef uint32_t dmub_trace_code_t; 677 678 /** 679 * struct dmcub_trace_buf_entry - Firmware trace entry 680 */ 681 struct dmcub_trace_buf_entry { 682 dmub_trace_code_t trace_code; /**< trace code for the event */ 683 uint32_t tick_count; /**< the tick count at time of trace */ 684 uint32_t param0; /**< trace defined parameter 0 */ 685 uint32_t param1; /**< trace defined parameter 1 */ 686 }; 687 #endif 688 689 //============================================================================== 690 //< DMUB_STATUS>================================================================ 691 //============================================================================== 692 693 /** 694 * DMCUB scratch registers can be used to determine firmware status. 695 * Current scratch register usage is as follows: 696 * 697 * SCRATCH0: FW Boot Status register 698 * SCRATCH5: LVTMA Status Register 699 * SCRATCH15: FW Boot Options register 700 */ 701 702 /** 703 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 704 */ 705 union dmub_fw_boot_status { 706 struct { 707 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 708 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 709 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 710 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 711 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 712 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 713 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 714 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 715 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 716 } bits; /**< status bits */ 717 uint32_t all; /**< 32-bit access to status bits */ 718 }; 719 720 /** 721 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 722 */ 723 enum dmub_fw_boot_status_bit { 724 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 725 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 726 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 727 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 728 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 729 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 730 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 731 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 732 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 733 }; 734 735 /* Register bit definition for SCRATCH5 */ 736 union dmub_lvtma_status { 737 struct { 738 uint32_t psp_ok : 1; 739 uint32_t edp_on : 1; 740 uint32_t reserved : 30; 741 } bits; 742 uint32_t all; 743 }; 744 745 enum dmub_lvtma_status_bit { 746 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 747 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 748 }; 749 750 enum dmub_ips_disable_type { 751 DMUB_IPS_ENABLE = 0, 752 DMUB_IPS_DISABLE_ALL = 1, 753 DMUB_IPS_DISABLE_IPS1 = 2, 754 DMUB_IPS_DISABLE_IPS2 = 3, 755 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 756 DMUB_IPS_DISABLE_DYNAMIC = 5, 757 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 758 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 759 }; 760 761 enum dmub_ips_rcg_disable_type { 762 DMUB_IPS_RCG_ENABLE = 0, 763 DMUB_IPS0_RCG_DISABLE = 1, 764 DMUB_IPS1_RCG_DISABLE = 2, 765 DMUB_IPS_RCG_DISABLE = 3 766 }; 767 768 #define DMUB_IPS1_ALLOW_MASK 0x00000001 769 #define DMUB_IPS2_ALLOW_MASK 0x00000002 770 #define DMUB_IPS1_COMMIT_MASK 0x00000004 771 #define DMUB_IPS2_COMMIT_MASK 0x00000008 772 773 /** 774 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 775 */ 776 union dmub_fw_boot_options { 777 struct { 778 uint32_t pemu_env : 1; /**< 1 if PEMU */ 779 uint32_t fpga_env : 1; /**< 1 if FPGA */ 780 uint32_t optimized_init : 1; /**< 1 if optimized init */ 781 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 782 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 783 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 784 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 785 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 786 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 787 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 788 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 789 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 790 uint32_t power_optimization: 1; 791 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 792 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 793 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 794 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 795 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 796 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 797 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 798 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 799 uint32_t ips_disable: 3; /* options to disable ips support*/ 800 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 801 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 802 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 803 uint32_t reserved : 6; /**< reserved */ 804 } bits; /**< boot bits */ 805 uint32_t all; /**< 32-bit access to bits */ 806 }; 807 808 enum dmub_fw_boot_options_bit { 809 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 810 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 811 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 812 }; 813 814 //============================================================================== 815 //< DMUB_SHARED_STATE>========================================================== 816 //============================================================================== 817 818 /** 819 * Shared firmware state between driver and firmware for lockless communication 820 * in situations where the inbox/outbox may be unavailable. 821 * 822 * Each structure *must* be at most 256-bytes in size. The layout allocation is 823 * described below: 824 * 825 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 826 */ 827 828 /** 829 * enum dmub_shared_state_feature_id - List of shared state features. 830 */ 831 enum dmub_shared_state_feature_id { 832 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 833 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 834 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 835 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 836 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 837 }; 838 839 /** 840 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 841 */ 842 union dmub_shared_state_ips_fw_signals { 843 struct { 844 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 845 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 846 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 847 uint32_t detection_required : 1; /**< 1 if detection is required */ 848 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 849 uint32_t reserved_bits : 27; /**< Reversed */ 850 } bits; 851 uint32_t all; 852 }; 853 854 /** 855 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 856 */ 857 union dmub_shared_state_ips_driver_signals { 858 struct { 859 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 860 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 861 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 862 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 863 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 864 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 865 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 866 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 867 uint32_t reserved_bits : 24; /**< Reversed bits */ 868 } bits; 869 uint32_t all; 870 }; 871 872 /** 873 * IPS FW Version 874 */ 875 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 876 877 struct dmub_shared_state_debug_setup { 878 union { 879 struct { 880 uint32_t exclude_points[62]; 881 } profile_mode; 882 }; 883 }; 884 885 /** 886 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 887 */ 888 struct dmub_shared_state_ips_fw { 889 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 890 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 891 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 892 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 893 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 894 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 895 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 896 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 897 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 898 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 899 }; /* 248-bytes, fixed */ 900 901 /** 902 * IPS Driver Version 903 */ 904 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 905 906 /** 907 * struct dmub_shared_state_ips_driver - Driver state for IPS. 908 */ 909 struct dmub_shared_state_ips_driver { 910 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 911 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 912 }; /* 248-bytes, fixed */ 913 914 /** 915 * enum dmub_shared_state_feature_common - Generic payload. 916 */ 917 struct dmub_shared_state_feature_common { 918 uint32_t padding[62]; 919 }; /* 248-bytes, fixed */ 920 921 /** 922 * enum dmub_shared_state_feature_header - Feature description. 923 */ 924 struct dmub_shared_state_feature_header { 925 uint16_t id; /**< Feature ID */ 926 uint16_t version; /**< Feature version */ 927 uint32_t reserved; /**< Reserved bytes. */ 928 }; /* 8 bytes, fixed */ 929 930 /** 931 * struct dmub_shared_state_feature_block - Feature block. 932 */ 933 struct dmub_shared_state_feature_block { 934 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 935 union dmub_shared_feature_state_union { 936 struct dmub_shared_state_feature_common common; /**< Generic data */ 937 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 938 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 939 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 940 } data; /**< Shared state data. */ 941 }; /* 256-bytes, fixed */ 942 943 /** 944 * Shared state size in bytes. 945 */ 946 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 947 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 948 949 //============================================================================== 950 //</DMUB_STATUS>================================================================ 951 //============================================================================== 952 //< DMUB_VBIOS>================================================================= 953 //============================================================================== 954 955 /* 956 * enum dmub_cmd_vbios_type - VBIOS commands. 957 * 958 * Command IDs should be treated as stable ABI. 959 * Do not reuse or modify IDs. 960 */ 961 enum dmub_cmd_vbios_type { 962 /** 963 * Configures the DIG encoder. 964 */ 965 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 966 /** 967 * Controls the PHY. 968 */ 969 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 970 /** 971 * Sets the pixel clock/symbol clock. 972 */ 973 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 974 /** 975 * Enables or disables power gating. 976 */ 977 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 978 /** 979 * Controls embedded panels. 980 */ 981 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 982 /** 983 * Query DP alt status on a transmitter. 984 */ 985 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 986 /** 987 * Control PHY FSM 988 */ 989 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 990 /** 991 * Controls domain power gating 992 */ 993 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 994 }; 995 996 //============================================================================== 997 //</DMUB_VBIOS>================================================================= 998 //============================================================================== 999 //< DMUB_GPINT>================================================================= 1000 //============================================================================== 1001 1002 /** 1003 * The shifts and masks below may alternatively be used to format and read 1004 * the command register bits. 1005 */ 1006 1007 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1008 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1009 1010 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1011 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1012 1013 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1014 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1015 1016 /** 1017 * Command responses. 1018 */ 1019 1020 /** 1021 * Return response for DMUB_GPINT__STOP_FW command. 1022 */ 1023 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1024 1025 /** 1026 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1027 */ 1028 union dmub_gpint_data_register { 1029 struct { 1030 uint32_t param : 16; /**< 16-bit parameter */ 1031 uint32_t command_code : 12; /**< GPINT command */ 1032 uint32_t status : 4; /**< Command status bit */ 1033 } bits; /**< GPINT bit access */ 1034 uint32_t all; /**< GPINT 32-bit access */ 1035 }; 1036 1037 /* 1038 * enum dmub_gpint_command - GPINT command to DMCUB FW 1039 * 1040 * Command IDs should be treated as stable ABI. 1041 * Do not reuse or modify IDs. 1042 */ 1043 enum dmub_gpint_command { 1044 /** 1045 * Invalid command, ignored. 1046 */ 1047 DMUB_GPINT__INVALID_COMMAND = 0, 1048 /** 1049 * DESC: Queries the firmware version. 1050 * RETURN: Firmware version. 1051 */ 1052 DMUB_GPINT__GET_FW_VERSION = 1, 1053 /** 1054 * DESC: Halts the firmware. 1055 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1056 */ 1057 DMUB_GPINT__STOP_FW = 2, 1058 /** 1059 * DESC: Get PSR state from FW. 1060 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1061 */ 1062 DMUB_GPINT__GET_PSR_STATE = 7, 1063 /** 1064 * DESC: Notifies DMCUB of the currently active streams. 1065 * ARGS: Stream mask, 1 bit per active stream index. 1066 */ 1067 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1068 /** 1069 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1070 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1071 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1072 * RETURN: PSR residency in milli-percent. 1073 */ 1074 DMUB_GPINT__PSR_RESIDENCY = 9, 1075 1076 /** 1077 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1078 */ 1079 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1080 1081 /** 1082 * DESC: Get REPLAY state from FW. 1083 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1084 */ 1085 DMUB_GPINT__GET_REPLAY_STATE = 13, 1086 1087 /** 1088 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1089 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1090 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1091 * RETURN: REPLAY residency in milli-percent. 1092 */ 1093 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1094 1095 /** 1096 * DESC: Copy bounding box to the host. 1097 * ARGS: Version of bounding box to copy 1098 * RETURN: Result of copying bounding box 1099 */ 1100 DMUB_GPINT__BB_COPY = 96, 1101 1102 /** 1103 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1104 * ARGS: The word3 for the 64 bit address 1105 */ 1106 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1107 1108 /** 1109 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1110 * ARGS: The word2 for the 64 bit address 1111 */ 1112 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1113 1114 /** 1115 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1116 * ARGS: The word1 for the 64 bit address 1117 */ 1118 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1119 1120 /** 1121 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1122 * ARGS: The word0 for the 64 bit address 1123 */ 1124 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1125 1126 /** 1127 * DESC: Updates the trace buffer lower 32-bit mask. 1128 * ARGS: The new mask 1129 * RETURN: Lower 32-bit mask. 1130 */ 1131 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1132 1133 /** 1134 * DESC: Updates the trace buffer mask bit0~bit15. 1135 * ARGS: The new mask 1136 * RETURN: Lower 32-bit mask. 1137 */ 1138 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1139 1140 /** 1141 * DESC: Updates the trace buffer mask bit16~bit31. 1142 * ARGS: The new mask 1143 * RETURN: Lower 32-bit mask. 1144 */ 1145 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1146 1147 /** 1148 * DESC: Updates the trace buffer mask bit32~bit47. 1149 * ARGS: The new mask 1150 * RETURN: Lower 32-bit mask. 1151 */ 1152 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1153 1154 /** 1155 * DESC: Updates the trace buffer mask bit48~bit63. 1156 * ARGS: The new mask 1157 * RETURN: Lower 32-bit mask. 1158 */ 1159 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1160 1161 /** 1162 * DESC: Read the trace buffer mask bi0~bit15. 1163 */ 1164 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1165 1166 /** 1167 * DESC: Read the trace buffer mask bit16~bit31. 1168 */ 1169 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1170 1171 /** 1172 * DESC: Read the trace buffer mask bi32~bit47. 1173 */ 1174 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1175 1176 /** 1177 * DESC: Updates the trace buffer mask bit32~bit63. 1178 */ 1179 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1180 1181 /** 1182 * DESC: Set IPS residency measurement 1183 * ARGS: 0 - Disable ips measurement 1184 * 1 - Enable ips measurement 1185 */ 1186 DMUB_GPINT__IPS_RESIDENCY = 121, 1187 1188 /** 1189 * DESC: Enable measurements for various task duration 1190 * ARGS: 0 - Disable measurement 1191 * 1 - Enable measurement 1192 */ 1193 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1194 1195 /** 1196 * DESC: Gets IPS residency in microseconds 1197 * ARGS: 0 - Return IPS1 residency 1198 * 1 - Return IPS2 residency 1199 * 2 - Return IPS1_RCG residency 1200 * 3 - Return IPS1_ONO2_ON residency 1201 * RETURN: Total residency in microseconds - lower 32 bits 1202 */ 1203 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1204 1205 /** 1206 * DESC: Gets IPS1 histogram counts 1207 * ARGS: Bucket index 1208 * RETURN: Total count for the bucket 1209 */ 1210 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1211 1212 /** 1213 * DESC: Gets IPS2 histogram counts 1214 * ARGS: Bucket index 1215 * RETURN: Total count for the bucket 1216 */ 1217 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1218 1219 /** 1220 * DESC: Gets IPS residency 1221 * ARGS: 0 - Return IPS1 residency 1222 * 1 - Return IPS2 residency 1223 * 2 - Return IPS1_RCG residency 1224 * 3 - Return IPS1_ONO2_ON residency 1225 * RETURN: Total residency in milli-percent. 1226 */ 1227 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1228 1229 /** 1230 * DESC: Gets IPS1_RCG histogram counts 1231 * ARGS: Bucket index 1232 * RETURN: Total count for the bucket 1233 */ 1234 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1235 1236 /** 1237 * DESC: Gets IPS1_ONO2_ON histogram counts 1238 * ARGS: Bucket index 1239 * RETURN: Total count for the bucket 1240 */ 1241 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1242 1243 /** 1244 * DESC: Gets IPS entry counter during residency measurement 1245 * ARGS: 0 - Return IPS1 entry counts 1246 * 1 - Return IPS2 entry counts 1247 * 2 - Return IPS1_RCG entry counts 1248 * 3 - Return IPS2_ONO2_ON entry counts 1249 * RETURN: Entry counter for selected IPS mode 1250 */ 1251 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1252 1253 /** 1254 * DESC: Gets IPS inactive residency in microseconds 1255 * ARGS: 0 - Return IPS1_MAX residency 1256 * 1 - Return IPS2 residency 1257 * 2 - Return IPS1_RCG residency 1258 * 3 - Return IPS1_ONO2_ON residency 1259 * RETURN: Total inactive residency in microseconds - lower 32 bits 1260 */ 1261 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1262 1263 /** 1264 * DESC: Gets IPS inactive residency in microseconds 1265 * ARGS: 0 - Return IPS1_MAX residency 1266 * 1 - Return IPS2 residency 1267 * 2 - Return IPS1_RCG residency 1268 * 3 - Return IPS1_ONO2_ON residency 1269 * RETURN: Total inactive residency in microseconds - upper 32 bits 1270 */ 1271 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1272 1273 /** 1274 * DESC: Gets IPS residency in microseconds 1275 * ARGS: 0 - Return IPS1 residency 1276 * 1 - Return IPS2 residency 1277 * 2 - Return IPS1_RCG residency 1278 * 3 - Return IPS1_ONO2_ON residency 1279 * RETURN: Total residency in microseconds - upper 32 bits 1280 */ 1281 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1282 /** 1283 * DESC: Setup debug configs. 1284 */ 1285 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1286 /** 1287 * DESC: Initiates IPS wake sequence. 1288 */ 1289 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1290 }; 1291 1292 /** 1293 * INBOX0 generic command definition 1294 */ 1295 union dmub_inbox0_cmd_common { 1296 struct { 1297 uint32_t command_code: 8; /**< INBOX0 command code */ 1298 uint32_t param: 24; /**< 24-bit parameter */ 1299 } bits; 1300 uint32_t all; 1301 }; 1302 1303 /** 1304 * INBOX0 hw_lock command definition 1305 */ 1306 union dmub_inbox0_cmd_lock_hw { 1307 struct { 1308 uint32_t command_code: 8; 1309 1310 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1311 uint32_t hw_lock_client: 2; 1312 1313 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1314 uint32_t otg_inst: 3; 1315 uint32_t opp_inst: 3; 1316 uint32_t dig_inst: 3; 1317 1318 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1319 uint32_t lock_pipe: 1; 1320 uint32_t lock_cursor: 1; 1321 uint32_t lock_dig: 1; 1322 uint32_t triple_buffer_lock: 1; 1323 1324 uint32_t lock: 1; /**< Lock */ 1325 uint32_t should_release: 1; /**< Release */ 1326 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1327 } bits; 1328 uint32_t all; 1329 }; 1330 1331 union dmub_inbox0_data_register { 1332 union dmub_inbox0_cmd_common inbox0_cmd_common; 1333 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1334 }; 1335 1336 enum dmub_inbox0_command { 1337 /** 1338 * DESC: Invalid command, ignored. 1339 */ 1340 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1341 /** 1342 * DESC: Notification to acquire/release HW lock 1343 * ARGS: 1344 */ 1345 DMUB_INBOX0_CMD__HW_LOCK = 1, 1346 }; 1347 //============================================================================== 1348 //</DMUB_GPINT>================================================================= 1349 //============================================================================== 1350 //< DMUB_CMD>=================================================================== 1351 //============================================================================== 1352 1353 /** 1354 * Size in bytes of each DMUB command. 1355 */ 1356 #define DMUB_RB_CMD_SIZE 64 1357 1358 /** 1359 * Maximum number of items in the DMUB ringbuffer. 1360 */ 1361 #define DMUB_RB_MAX_ENTRY 128 1362 1363 /** 1364 * Ringbuffer size in bytes. 1365 */ 1366 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1367 1368 /** 1369 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1370 */ 1371 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1372 1373 /** 1374 * Ringbuffer size in bytes. 1375 */ 1376 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1377 1378 /** 1379 * REG_SET mask for reg offload. 1380 */ 1381 #define REG_SET_MASK 0xFFFF 1382 1383 /* 1384 * enum dmub_cmd_type - DMUB inbox command. 1385 * 1386 * Command IDs should be treated as stable ABI. 1387 * Do not reuse or modify IDs. 1388 */ 1389 enum dmub_cmd_type { 1390 /** 1391 * Invalid command. 1392 */ 1393 DMUB_CMD__NULL = 0, 1394 /** 1395 * Read modify write register sequence offload. 1396 */ 1397 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1398 /** 1399 * Field update register sequence offload. 1400 */ 1401 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1402 /** 1403 * Burst write sequence offload. 1404 */ 1405 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1406 /** 1407 * Reg wait sequence offload. 1408 */ 1409 DMUB_CMD__REG_REG_WAIT = 4, 1410 /** 1411 * Workaround to avoid HUBP underflow during NV12 playback. 1412 */ 1413 DMUB_CMD__PLAT_54186_WA = 5, 1414 /** 1415 * Command type used to query FW feature caps. 1416 */ 1417 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1418 /** 1419 * Command type used to get visual confirm color. 1420 */ 1421 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1422 /** 1423 * Command type used for all PSR commands. 1424 */ 1425 DMUB_CMD__PSR = 64, 1426 /** 1427 * Command type used for all MALL commands. 1428 */ 1429 DMUB_CMD__MALL = 65, 1430 /** 1431 * Command type used for all ABM commands. 1432 */ 1433 DMUB_CMD__ABM = 66, 1434 /** 1435 * Command type used to update dirty rects in FW. 1436 */ 1437 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1438 /** 1439 * Command type used to update cursor info in FW. 1440 */ 1441 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1442 /** 1443 * Command type used for HW locking in FW. 1444 */ 1445 DMUB_CMD__HW_LOCK = 69, 1446 /** 1447 * Command type used to access DP AUX. 1448 */ 1449 DMUB_CMD__DP_AUX_ACCESS = 70, 1450 /** 1451 * Command type used for OUTBOX1 notification enable 1452 */ 1453 DMUB_CMD__OUTBOX1_ENABLE = 71, 1454 1455 /** 1456 * Command type used for all idle optimization commands. 1457 */ 1458 DMUB_CMD__IDLE_OPT = 72, 1459 /** 1460 * Command type used for all clock manager commands. 1461 */ 1462 DMUB_CMD__CLK_MGR = 73, 1463 /** 1464 * Command type used for all panel control commands. 1465 */ 1466 DMUB_CMD__PANEL_CNTL = 74, 1467 1468 /** 1469 * Command type used for all CAB commands. 1470 */ 1471 DMUB_CMD__CAB_FOR_SS = 75, 1472 1473 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1474 1475 /** 1476 * Command type used for interfacing with DPIA. 1477 */ 1478 DMUB_CMD__DPIA = 77, 1479 /** 1480 * Command type used for EDID CEA parsing 1481 */ 1482 DMUB_CMD__EDID_CEA = 79, 1483 /** 1484 * Command type used for getting usbc cable ID 1485 */ 1486 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1487 /** 1488 * Command type used to query HPD state. 1489 */ 1490 DMUB_CMD__QUERY_HPD_STATE = 82, 1491 /** 1492 * Command type used for all VBIOS interface commands. 1493 */ 1494 /** 1495 * Command type used for all REPLAY commands. 1496 */ 1497 DMUB_CMD__REPLAY = 83, 1498 1499 /** 1500 * Command type used for all SECURE_DISPLAY commands. 1501 */ 1502 DMUB_CMD__SECURE_DISPLAY = 85, 1503 1504 /** 1505 * Command type used to set DPIA HPD interrupt state 1506 */ 1507 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1508 1509 /** 1510 * Command type used for all PSP commands. 1511 */ 1512 DMUB_CMD__PSP = 88, 1513 1514 /** 1515 * Command type used for all Fused IO commands. 1516 */ 1517 DMUB_CMD__FUSED_IO = 89, 1518 1519 DMUB_CMD__VBIOS = 128, 1520 }; 1521 1522 /** 1523 * enum dmub_out_cmd_type - DMUB outbox commands. 1524 */ 1525 enum dmub_out_cmd_type { 1526 /** 1527 * Invalid outbox command, ignored. 1528 */ 1529 DMUB_OUT_CMD__NULL = 0, 1530 /** 1531 * Command type used for DP AUX Reply data notification 1532 */ 1533 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1534 /** 1535 * Command type used for DP HPD event notification 1536 */ 1537 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1538 /** 1539 * Command type used for SET_CONFIG Reply notification 1540 */ 1541 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1542 /** 1543 * Command type used for USB4 DPIA notification 1544 */ 1545 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1546 /** 1547 * Command type used for HPD redetect notification 1548 */ 1549 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1550 /** 1551 * Command type used for Fused IO notification 1552 */ 1553 DMUB_OUT_CMD__FUSED_IO = 7, 1554 }; 1555 1556 /* DMUB_CMD__DPIA command sub-types. */ 1557 enum dmub_cmd_dpia_type { 1558 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1559 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1560 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1561 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1562 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1563 }; 1564 1565 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1566 enum dmub_cmd_dpia_notification_type { 1567 DPIA_NOTIFY__BW_ALLOCATION = 0, 1568 }; 1569 1570 #pragma pack(push, 1) 1571 1572 /** 1573 * struct dmub_cmd_header - Common command header fields. 1574 */ 1575 struct dmub_cmd_header { 1576 unsigned int type : 8; /**< command type */ 1577 unsigned int sub_type : 8; /**< command sub type */ 1578 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1579 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1580 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1581 unsigned int reserved0 : 5; /**< reserved bits */ 1582 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1583 unsigned int reserved1 : 2; /**< reserved bits */ 1584 }; 1585 1586 /* 1587 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1588 * 1589 * 60 payload bytes can hold up to 5 sets of read modify writes, 1590 * each take 3 dwords. 1591 * 1592 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1593 * 1594 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1595 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1596 */ 1597 struct dmub_cmd_read_modify_write_sequence { 1598 uint32_t addr; /**< register address */ 1599 uint32_t modify_mask; /**< modify mask */ 1600 uint32_t modify_value; /**< modify value */ 1601 }; 1602 1603 /** 1604 * Maximum number of ops in read modify write sequence. 1605 */ 1606 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1607 1608 /** 1609 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1610 */ 1611 struct dmub_rb_cmd_read_modify_write { 1612 struct dmub_cmd_header header; /**< command header */ 1613 /** 1614 * Read modify write sequence. 1615 */ 1616 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1617 }; 1618 1619 /* 1620 * Update a register with specified masks and values sequeunce 1621 * 1622 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1623 * 1624 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1625 * 1626 * 1627 * USE CASE: 1628 * 1. auto-increment register where additional read would update pointer and produce wrong result 1629 * 2. toggle a bit without read in the middle 1630 */ 1631 1632 struct dmub_cmd_reg_field_update_sequence { 1633 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1634 uint32_t modify_value; /**< value to update with */ 1635 }; 1636 1637 /** 1638 * Maximum number of ops in field update sequence. 1639 */ 1640 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1641 1642 /** 1643 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1644 */ 1645 struct dmub_rb_cmd_reg_field_update_sequence { 1646 struct dmub_cmd_header header; /**< command header */ 1647 uint32_t addr; /**< register address */ 1648 /** 1649 * Field update sequence. 1650 */ 1651 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1652 }; 1653 1654 1655 /** 1656 * Maximum number of burst write values. 1657 */ 1658 #define DMUB_BURST_WRITE_VALUES__MAX 14 1659 1660 /* 1661 * struct dmub_rb_cmd_burst_write - Burst write 1662 * 1663 * support use case such as writing out LUTs. 1664 * 1665 * 60 payload bytes can hold up to 14 values to write to given address 1666 * 1667 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1668 */ 1669 struct dmub_rb_cmd_burst_write { 1670 struct dmub_cmd_header header; /**< command header */ 1671 uint32_t addr; /**< register start address */ 1672 /** 1673 * Burst write register values. 1674 */ 1675 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1676 }; 1677 1678 /** 1679 * struct dmub_rb_cmd_common - Common command header 1680 */ 1681 struct dmub_rb_cmd_common { 1682 struct dmub_cmd_header header; /**< command header */ 1683 /** 1684 * Padding to RB_CMD_SIZE 1685 */ 1686 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1687 }; 1688 1689 /** 1690 * struct dmub_cmd_reg_wait_data - Register wait data 1691 */ 1692 struct dmub_cmd_reg_wait_data { 1693 uint32_t addr; /**< Register address */ 1694 uint32_t mask; /**< Mask for register bits */ 1695 uint32_t condition_field_value; /**< Value to wait for */ 1696 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1697 }; 1698 1699 /** 1700 * struct dmub_rb_cmd_reg_wait - Register wait command 1701 */ 1702 struct dmub_rb_cmd_reg_wait { 1703 struct dmub_cmd_header header; /**< Command header */ 1704 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1705 }; 1706 1707 /** 1708 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1709 * 1710 * Reprograms surface parameters to avoid underflow. 1711 */ 1712 struct dmub_cmd_PLAT_54186_wa { 1713 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1714 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1715 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1716 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1717 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1718 struct { 1719 uint32_t hubp_inst : 4; /**< HUBP instance */ 1720 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1721 uint32_t immediate :1; /**< Immediate flip */ 1722 uint32_t vmid : 4; /**< VMID */ 1723 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1724 uint32_t reserved : 21; /**< Reserved */ 1725 } flip_params; /**< Pageflip parameters */ 1726 uint32_t reserved[9]; /**< Reserved bits */ 1727 }; 1728 1729 /** 1730 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1731 */ 1732 struct dmub_rb_cmd_PLAT_54186_wa { 1733 struct dmub_cmd_header header; /**< Command header */ 1734 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1735 }; 1736 1737 /** 1738 * enum dmub_cmd_mall_type - MALL commands 1739 */ 1740 enum dmub_cmd_mall_type { 1741 /** 1742 * Allows display refresh from MALL. 1743 */ 1744 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1745 /** 1746 * Disallows display refresh from MALL. 1747 */ 1748 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1749 /** 1750 * Cursor copy for MALL. 1751 */ 1752 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1753 /** 1754 * Controls DF requests. 1755 */ 1756 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1757 }; 1758 1759 /** 1760 * struct dmub_rb_cmd_mall - MALL command data. 1761 */ 1762 struct dmub_rb_cmd_mall { 1763 struct dmub_cmd_header header; /**< Common command header */ 1764 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1765 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1766 uint32_t tmr_delay; /**< Timer delay */ 1767 uint32_t tmr_scale; /**< Timer scale */ 1768 uint16_t cursor_width; /**< Cursor width in pixels */ 1769 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1770 uint16_t cursor_height; /**< Cursor height in pixels */ 1771 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1772 uint8_t debug_bits; /**< Debug bits */ 1773 1774 uint8_t reserved1; /**< Reserved bits */ 1775 uint8_t reserved2; /**< Reserved bits */ 1776 }; 1777 1778 /** 1779 * enum dmub_cmd_cab_type - CAB command data. 1780 */ 1781 enum dmub_cmd_cab_type { 1782 /** 1783 * No idle optimizations (i.e. no CAB) 1784 */ 1785 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1786 /** 1787 * No DCN requests for memory 1788 */ 1789 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1790 /** 1791 * Fit surfaces in CAB (i.e. CAB enable) 1792 */ 1793 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1794 /** 1795 * Do not fit surfaces in CAB (i.e. no CAB) 1796 */ 1797 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1798 }; 1799 1800 /** 1801 * struct dmub_rb_cmd_cab - CAB command data. 1802 */ 1803 struct dmub_rb_cmd_cab_for_ss { 1804 struct dmub_cmd_header header; 1805 uint8_t cab_alloc_ways; /* total number of ways */ 1806 uint8_t debug_bits; /* debug bits */ 1807 }; 1808 1809 /** 1810 * Enum for indicating which MCLK switch mode per pipe 1811 */ 1812 enum mclk_switch_mode { 1813 NONE = 0, 1814 FPO = 1, 1815 SUBVP = 2, 1816 VBLANK = 3, 1817 }; 1818 1819 /* Per pipe struct which stores the MCLK switch mode 1820 * data to be sent to DMUB. 1821 * Named "v2" for now -- once FPO and SUBVP are fully merged 1822 * the type name can be updated 1823 */ 1824 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1825 union { 1826 struct { 1827 uint32_t pix_clk_100hz; 1828 uint16_t main_vblank_start; 1829 uint16_t main_vblank_end; 1830 uint16_t mall_region_lines; 1831 uint16_t prefetch_lines; 1832 uint16_t prefetch_to_mall_start_lines; 1833 uint16_t processing_delay_lines; 1834 uint16_t htotal; // required to calculate line time for multi-display cases 1835 uint16_t vtotal; 1836 uint8_t main_pipe_index; 1837 uint8_t phantom_pipe_index; 1838 /* Since the microschedule is calculated in terms of OTG lines, 1839 * include any scaling factors to make sure when we get accurate 1840 * conversion when programming MALL_START_LINE (which is in terms 1841 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1842 * is 1/2 (numerator = 1, denominator = 2). 1843 */ 1844 uint8_t scale_factor_numerator; 1845 uint8_t scale_factor_denominator; 1846 uint8_t is_drr; 1847 uint8_t main_split_pipe_index; 1848 uint8_t phantom_split_pipe_index; 1849 } subvp_data; 1850 1851 struct { 1852 uint32_t pix_clk_100hz; 1853 uint16_t vblank_start; 1854 uint16_t vblank_end; 1855 uint16_t vstartup_start; 1856 uint16_t vtotal; 1857 uint16_t htotal; 1858 uint8_t vblank_pipe_index; 1859 uint8_t padding[1]; 1860 struct { 1861 uint8_t drr_in_use; 1862 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1863 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1864 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1865 uint8_t use_ramping; // Use ramping or not 1866 uint8_t drr_vblank_start_margin; 1867 } drr_info; // DRR considered as part of SubVP + VBLANK case 1868 } vblank_data; 1869 } pipe_config; 1870 1871 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1872 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1873 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1874 */ 1875 uint8_t mode; // enum mclk_switch_mode 1876 }; 1877 1878 /** 1879 * Config data for Sub-VP and FPO 1880 * Named "v2" for now -- once FPO and SUBVP are fully merged 1881 * the type name can be updated 1882 */ 1883 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1884 uint16_t watermark_a_cache; 1885 uint8_t vertical_int_margin_us; 1886 uint8_t pstate_allow_width_us; 1887 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1888 }; 1889 1890 /** 1891 * DMUB rb command definition for Sub-VP and FPO 1892 * Named "v2" for now -- once FPO and SUBVP are fully merged 1893 * the type name can be updated 1894 */ 1895 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1896 struct dmub_cmd_header header; 1897 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1898 }; 1899 1900 struct dmub_flip_addr_info { 1901 uint32_t surf_addr_lo; 1902 uint32_t surf_addr_c_lo; 1903 uint32_t meta_addr_lo; 1904 uint32_t meta_addr_c_lo; 1905 uint16_t surf_addr_hi; 1906 uint16_t surf_addr_c_hi; 1907 uint16_t meta_addr_hi; 1908 uint16_t meta_addr_c_hi; 1909 }; 1910 1911 struct dmub_fams2_flip_info { 1912 union { 1913 struct { 1914 uint8_t is_immediate: 1; 1915 } bits; 1916 uint8_t all; 1917 } config; 1918 uint8_t otg_inst; 1919 uint8_t pipe_mask; 1920 uint8_t pad; 1921 struct dmub_flip_addr_info addr_info; 1922 }; 1923 1924 struct dmub_rb_cmd_fams2_flip { 1925 struct dmub_cmd_header header; 1926 struct dmub_fams2_flip_info flip_info; 1927 }; 1928 1929 struct dmub_optc_state_v2 { 1930 uint32_t v_total_min; 1931 uint32_t v_total_max; 1932 uint32_t v_total_mid; 1933 uint32_t v_total_mid_frame_num; 1934 uint8_t program_manual_trigger; 1935 uint8_t tg_inst; 1936 uint8_t pad[2]; 1937 }; 1938 1939 struct dmub_optc_position { 1940 uint32_t vpos; 1941 uint32_t hpos; 1942 uint32_t frame; 1943 }; 1944 1945 struct dmub_rb_cmd_fams2_drr_update { 1946 struct dmub_cmd_header header; 1947 struct dmub_optc_state_v2 dmub_optc_state_req; 1948 }; 1949 1950 /* HW and FW global configuration data for FAMS2 */ 1951 /* FAMS2 types and structs */ 1952 enum fams2_stream_type { 1953 FAMS2_STREAM_TYPE_NONE = 0, 1954 FAMS2_STREAM_TYPE_VBLANK = 1, 1955 FAMS2_STREAM_TYPE_VACTIVE = 2, 1956 FAMS2_STREAM_TYPE_DRR = 3, 1957 FAMS2_STREAM_TYPE_SUBVP = 4, 1958 }; 1959 1960 /* static stream state */ 1961 struct dmub_fams2_legacy_stream_static_state { 1962 uint8_t vactive_det_fill_delay_otg_vlines; 1963 uint8_t programming_delay_otg_vlines; 1964 }; //v0 1965 1966 struct dmub_fams2_subvp_stream_static_state { 1967 uint16_t vratio_numerator; 1968 uint16_t vratio_denominator; 1969 uint16_t phantom_vtotal; 1970 uint16_t phantom_vactive; 1971 union { 1972 struct { 1973 uint8_t is_multi_planar : 1; 1974 uint8_t is_yuv420 : 1; 1975 } bits; 1976 uint8_t all; 1977 } config; 1978 uint8_t programming_delay_otg_vlines; 1979 uint8_t prefetch_to_mall_otg_vlines; 1980 uint8_t phantom_otg_inst; 1981 uint8_t phantom_pipe_mask; 1982 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1983 }; //v0 1984 1985 struct dmub_fams2_drr_stream_static_state { 1986 uint16_t nom_stretched_vtotal; 1987 uint8_t programming_delay_otg_vlines; 1988 uint8_t only_stretch_if_required; 1989 uint8_t pad[2]; 1990 }; //v0 1991 1992 struct dmub_fams2_cmd_legacy_stream_static_state { 1993 uint16_t vactive_det_fill_delay_otg_vlines; 1994 uint16_t programming_delay_otg_vlines; 1995 }; //v1 1996 1997 struct dmub_fams2_cmd_subvp_stream_static_state { 1998 uint16_t vratio_numerator; 1999 uint16_t vratio_denominator; 2000 uint16_t phantom_vtotal; 2001 uint16_t phantom_vactive; 2002 uint16_t programming_delay_otg_vlines; 2003 uint16_t prefetch_to_mall_otg_vlines; 2004 union { 2005 struct { 2006 uint8_t is_multi_planar : 1; 2007 uint8_t is_yuv420 : 1; 2008 } bits; 2009 uint8_t all; 2010 } config; 2011 uint8_t phantom_otg_inst; 2012 uint8_t phantom_pipe_mask; 2013 uint8_t pad0; 2014 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2015 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2016 }; //v1 2017 2018 struct dmub_fams2_cmd_drr_stream_static_state { 2019 uint16_t nom_stretched_vtotal; 2020 uint16_t programming_delay_otg_vlines; 2021 uint8_t only_stretch_if_required; 2022 uint8_t pad[3]; 2023 }; //v1 2024 2025 union dmub_fams2_stream_static_sub_state { 2026 struct dmub_fams2_legacy_stream_static_state legacy; 2027 struct dmub_fams2_subvp_stream_static_state subvp; 2028 struct dmub_fams2_drr_stream_static_state drr; 2029 }; //v0 2030 2031 union dmub_fams2_cmd_stream_static_sub_state { 2032 COMMON_STREAM_STATIC_SUB_STATE 2033 }; //v1 2034 2035 union dmub_fams2_stream_static_sub_state_v2 { 2036 COMMON_STREAM_STATIC_SUB_STATE 2037 }; //v2 2038 2039 struct dmub_fams2_stream_static_state { 2040 enum fams2_stream_type type; 2041 uint32_t otg_vline_time_ns; 2042 uint32_t otg_vline_time_ticks; 2043 uint16_t htotal; 2044 uint16_t vtotal; // nominal vtotal 2045 uint16_t vblank_start; 2046 uint16_t vblank_end; 2047 uint16_t max_vtotal; 2048 uint16_t allow_start_otg_vline; 2049 uint16_t allow_end_otg_vline; 2050 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2051 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2052 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2053 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2054 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2055 union { 2056 struct { 2057 uint8_t is_drr: 1; // stream is DRR enabled 2058 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2059 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2060 } bits; 2061 uint8_t all; 2062 } config; 2063 uint8_t otg_inst; 2064 uint8_t pipe_mask; // pipe mask for the whole config 2065 uint8_t num_planes; 2066 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2067 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2068 union dmub_fams2_stream_static_sub_state sub_state; 2069 }; //v0 2070 2071 struct dmub_fams2_cmd_stream_static_base_state { 2072 enum fams2_stream_type type; 2073 uint32_t otg_vline_time_ns; 2074 uint32_t otg_vline_time_ticks; 2075 uint16_t htotal; 2076 uint16_t vtotal; // nominal vtotal 2077 uint16_t vblank_start; 2078 uint16_t vblank_end; 2079 uint16_t max_vtotal; 2080 uint16_t allow_start_otg_vline; 2081 uint16_t allow_end_otg_vline; 2082 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2083 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2084 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2085 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2086 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2087 union { 2088 struct { 2089 uint8_t is_drr : 1; // stream is DRR enabled 2090 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2091 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2092 } bits; 2093 uint8_t all; 2094 } config; 2095 uint8_t otg_inst; 2096 uint8_t pipe_mask; // pipe mask for the whole config 2097 uint8_t num_planes; 2098 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2099 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2100 }; //v1 2101 2102 struct dmub_fams2_stream_static_state_v1 { 2103 struct dmub_fams2_cmd_stream_static_base_state base; 2104 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2105 }; //v1 2106 2107 /** 2108 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2109 * p-state request to allow latency 2110 */ 2111 enum dmub_fams2_allow_delay_check_mode { 2112 /* No check for request to allow delay */ 2113 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2114 /* Check for request to allow delay */ 2115 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2116 /* Check for prepare to allow delay */ 2117 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2118 }; 2119 2120 union dmub_fams2_global_feature_config { 2121 struct { 2122 uint32_t enable: 1; 2123 uint32_t enable_ppt_check: 1; 2124 uint32_t enable_stall_recovery: 1; 2125 uint32_t enable_debug: 1; 2126 uint32_t enable_offload_flip: 1; 2127 uint32_t enable_visual_confirm: 1; 2128 uint32_t allow_delay_check_mode: 2; 2129 uint32_t reserved: 24; 2130 } bits; 2131 uint32_t all; 2132 }; 2133 2134 struct dmub_cmd_fams2_global_config { 2135 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2136 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2137 uint32_t num_streams; 2138 union dmub_fams2_global_feature_config features; 2139 uint32_t recovery_timeout_us; 2140 uint32_t hwfq_flip_programming_delay_us; 2141 }; 2142 2143 union dmub_cmd_fams2_config { 2144 struct dmub_cmd_fams2_global_config global; 2145 struct dmub_fams2_stream_static_state stream; //v0 2146 union { 2147 struct dmub_fams2_cmd_stream_static_base_state base; 2148 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2149 } stream_v1; //v1 2150 }; 2151 2152 struct dmub_fams2_config_v2 { 2153 struct dmub_cmd_fams2_global_config global; 2154 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2155 }; 2156 2157 /** 2158 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2159 */ 2160 struct dmub_rb_cmd_fams2 { 2161 struct dmub_cmd_header header; 2162 union dmub_cmd_fams2_config config; 2163 }; 2164 2165 /** 2166 * Indirect buffer descriptor 2167 */ 2168 struct dmub_ib_data { 2169 union dmub_addr src; // location of indirect buffer in memory 2170 uint16_t size; // indirect buffer size in bytes 2171 }; 2172 2173 /** 2174 * DMUB rb command definition for commands passed over indirect buffer 2175 */ 2176 struct dmub_rb_cmd_ib { 2177 struct dmub_cmd_header header; 2178 struct dmub_ib_data ib_data; 2179 }; 2180 2181 /** 2182 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2183 */ 2184 enum dmub_cmd_idle_opt_type { 2185 /** 2186 * DCN hardware restore. 2187 */ 2188 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2189 2190 /** 2191 * DCN hardware save. 2192 */ 2193 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2194 2195 /** 2196 * DCN hardware notify idle. 2197 */ 2198 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2199 2200 /** 2201 * DCN hardware notify power state. 2202 */ 2203 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2204 2205 /** 2206 * DCN notify to release HW. 2207 */ 2208 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2209 }; 2210 2211 /** 2212 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2213 */ 2214 struct dmub_rb_cmd_idle_opt_dcn_restore { 2215 struct dmub_cmd_header header; /**< header */ 2216 }; 2217 2218 /** 2219 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2220 */ 2221 struct dmub_dcn_notify_idle_cntl_data { 2222 uint8_t driver_idle; 2223 uint8_t skip_otg_disable; 2224 uint8_t reserved[58]; 2225 }; 2226 2227 /** 2228 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2229 */ 2230 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2231 struct dmub_cmd_header header; /**< header */ 2232 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2233 }; 2234 2235 /** 2236 * enum dmub_idle_opt_dc_power_state - DC power states. 2237 */ 2238 enum dmub_idle_opt_dc_power_state { 2239 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2240 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2241 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2242 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2243 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2244 }; 2245 2246 /** 2247 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2248 */ 2249 struct dmub_idle_opt_set_dc_power_state_data { 2250 uint8_t power_state; /**< power state */ 2251 uint8_t pad[3]; /**< padding */ 2252 }; 2253 2254 /** 2255 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2256 */ 2257 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2258 struct dmub_cmd_header header; /**< header */ 2259 struct dmub_idle_opt_set_dc_power_state_data data; 2260 }; 2261 2262 /** 2263 * struct dmub_clocks - Clock update notification. 2264 */ 2265 struct dmub_clocks { 2266 uint32_t dispclk_khz; /**< dispclk kHz */ 2267 uint32_t dppclk_khz; /**< dppclk kHz */ 2268 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2269 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2270 }; 2271 2272 /** 2273 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2274 */ 2275 enum dmub_cmd_clk_mgr_type { 2276 /** 2277 * Notify DMCUB of clock update. 2278 */ 2279 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2280 }; 2281 2282 /** 2283 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2284 */ 2285 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2286 struct dmub_cmd_header header; /**< header */ 2287 struct dmub_clocks clocks; /**< clock data */ 2288 }; 2289 2290 /** 2291 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2292 */ 2293 struct dmub_cmd_digx_encoder_control_data { 2294 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2295 }; 2296 2297 /** 2298 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2299 */ 2300 struct dmub_rb_cmd_digx_encoder_control { 2301 struct dmub_cmd_header header; /**< header */ 2302 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2303 }; 2304 2305 /** 2306 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2307 */ 2308 struct dmub_cmd_set_pixel_clock_data { 2309 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2310 }; 2311 2312 /** 2313 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2314 */ 2315 struct dmub_rb_cmd_set_pixel_clock { 2316 struct dmub_cmd_header header; /**< header */ 2317 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2318 }; 2319 2320 /** 2321 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2322 */ 2323 struct dmub_cmd_enable_disp_power_gating_data { 2324 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2325 }; 2326 2327 /** 2328 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2329 */ 2330 struct dmub_rb_cmd_enable_disp_power_gating { 2331 struct dmub_cmd_header header; /**< header */ 2332 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2333 }; 2334 2335 /** 2336 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2337 */ 2338 struct dmub_dig_transmitter_control_data_v1_7 { 2339 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2340 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2341 union { 2342 uint8_t digmode; /**< enum atom_encode_mode_def */ 2343 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2344 } mode_laneset; 2345 uint8_t lanenum; /**< Number of lanes */ 2346 union { 2347 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2348 } symclk_units; 2349 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2350 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2351 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2352 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2353 uint8_t reserved1; /**< For future use */ 2354 uint8_t reserved2[3]; /**< For future use */ 2355 uint32_t reserved3[11]; /**< For future use */ 2356 }; 2357 2358 /** 2359 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2360 */ 2361 union dmub_cmd_dig1_transmitter_control_data { 2362 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2363 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2364 }; 2365 2366 /** 2367 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2368 */ 2369 struct dmub_rb_cmd_dig1_transmitter_control { 2370 struct dmub_cmd_header header; /**< header */ 2371 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2372 }; 2373 2374 /** 2375 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2376 */ 2377 struct dmub_rb_cmd_domain_control_data { 2378 uint8_t inst : 6; /**< DOMAIN instance to control */ 2379 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2380 uint8_t reserved[3]; /**< Reserved for future use */ 2381 }; 2382 2383 /** 2384 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2385 */ 2386 struct dmub_rb_cmd_domain_control { 2387 struct dmub_cmd_header header; /**< header */ 2388 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2389 }; 2390 2391 /** 2392 * DPIA tunnel command parameters. 2393 */ 2394 struct dmub_cmd_dig_dpia_control_data { 2395 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2396 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2397 union { 2398 uint8_t digmode; /** enum atom_encode_mode_def */ 2399 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2400 } mode_laneset; 2401 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2402 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2403 uint8_t hpdsel; /** =0: HPD is not assigned */ 2404 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2405 uint8_t dpia_id; /** Index of DPIA */ 2406 uint8_t fec_rdy : 1; 2407 uint8_t reserved : 7; 2408 uint32_t reserved1; 2409 }; 2410 2411 /** 2412 * DMUB command for DPIA tunnel control. 2413 */ 2414 struct dmub_rb_cmd_dig1_dpia_control { 2415 struct dmub_cmd_header header; 2416 struct dmub_cmd_dig_dpia_control_data dpia_control; 2417 }; 2418 2419 /** 2420 * SET_CONFIG Command Payload (deprecated) 2421 */ 2422 struct set_config_cmd_payload { 2423 uint8_t msg_type; /* set config message type */ 2424 uint8_t msg_data; /* set config message data */ 2425 }; 2426 2427 /** 2428 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2429 */ 2430 struct dmub_cmd_set_config_control_data { 2431 struct set_config_cmd_payload cmd_pkt; 2432 uint8_t instance; /* DPIA instance */ 2433 uint8_t immed_status; /* Immediate status returned in case of error */ 2434 }; 2435 2436 /** 2437 * SET_CONFIG Request Command Payload 2438 */ 2439 struct set_config_request_cmd_payload { 2440 uint8_t instance; /* DPIA instance */ 2441 uint8_t immed_status; /* Immediate status returned in case of error */ 2442 uint8_t msg_type; /* set config message type */ 2443 uint8_t reserved; 2444 uint32_t msg_data; /* set config message data */ 2445 }; 2446 2447 /** 2448 * DMUB command structure for SET_CONFIG command. 2449 */ 2450 struct dmub_rb_cmd_set_config_access { 2451 struct dmub_cmd_header header; /* header */ 2452 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2453 }; 2454 2455 /** 2456 * DMUB command structure for SET_CONFIG request command. 2457 */ 2458 struct dmub_rb_cmd_set_config_request { 2459 struct dmub_cmd_header header; /* header */ 2460 struct set_config_request_cmd_payload payload; /* set config request payload */ 2461 }; 2462 2463 /** 2464 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2465 */ 2466 struct dmub_cmd_mst_alloc_slots_control_data { 2467 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2468 uint8_t instance; /* DPIA instance */ 2469 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2470 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2471 }; 2472 2473 /** 2474 * DMUB command structure for SET_ command. 2475 */ 2476 struct dmub_rb_cmd_set_mst_alloc_slots { 2477 struct dmub_cmd_header header; /* header */ 2478 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2479 }; 2480 2481 /** 2482 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2483 */ 2484 struct dmub_cmd_tps_notification_data { 2485 uint8_t instance; /* DPIA instance */ 2486 uint8_t tps; /* requested training pattern */ 2487 uint8_t reserved1; 2488 uint8_t reserved2; 2489 }; 2490 2491 /** 2492 * DMUB command structure for SET_TPS_NOTIFICATION command. 2493 */ 2494 struct dmub_rb_cmd_set_tps_notification { 2495 struct dmub_cmd_header header; /* header */ 2496 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2497 }; 2498 2499 /** 2500 * DMUB command structure for DPIA HPD int enable control. 2501 */ 2502 struct dmub_rb_cmd_dpia_hpd_int_enable { 2503 struct dmub_cmd_header header; /* header */ 2504 uint32_t enable; /* dpia hpd interrupt enable */ 2505 }; 2506 2507 /** 2508 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2509 */ 2510 struct dmub_rb_cmd_dpphy_init { 2511 struct dmub_cmd_header header; /**< header */ 2512 uint8_t reserved[60]; /**< reserved bits */ 2513 }; 2514 2515 /** 2516 * enum dp_aux_request_action - DP AUX request command listing. 2517 * 2518 * 4 AUX request command bits are shifted to high nibble. 2519 */ 2520 enum dp_aux_request_action { 2521 /** I2C-over-AUX write request */ 2522 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2523 /** I2C-over-AUX read request */ 2524 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2525 /** I2C-over-AUX write status request */ 2526 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2527 /** I2C-over-AUX write request with MOT=1 */ 2528 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2529 /** I2C-over-AUX read request with MOT=1 */ 2530 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2531 /** I2C-over-AUX write status request with MOT=1 */ 2532 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2533 /** Native AUX write request */ 2534 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2535 /** Native AUX read request */ 2536 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2537 }; 2538 2539 /** 2540 * enum aux_return_code_type - DP AUX process return code listing. 2541 */ 2542 enum aux_return_code_type { 2543 /** AUX process succeeded */ 2544 AUX_RET_SUCCESS = 0, 2545 /** AUX process failed with unknown reason */ 2546 AUX_RET_ERROR_UNKNOWN, 2547 /** AUX process completed with invalid reply */ 2548 AUX_RET_ERROR_INVALID_REPLY, 2549 /** AUX process timed out */ 2550 AUX_RET_ERROR_TIMEOUT, 2551 /** HPD was low during AUX process */ 2552 AUX_RET_ERROR_HPD_DISCON, 2553 /** Failed to acquire AUX engine */ 2554 AUX_RET_ERROR_ENGINE_ACQUIRE, 2555 /** AUX request not supported */ 2556 AUX_RET_ERROR_INVALID_OPERATION, 2557 /** AUX process not available */ 2558 AUX_RET_ERROR_PROTOCOL_ERROR, 2559 }; 2560 2561 /** 2562 * enum aux_channel_type - DP AUX channel type listing. 2563 */ 2564 enum aux_channel_type { 2565 /** AUX thru Legacy DP AUX */ 2566 AUX_CHANNEL_LEGACY_DDC, 2567 /** AUX thru DPIA DP tunneling */ 2568 AUX_CHANNEL_DPIA 2569 }; 2570 2571 /** 2572 * struct aux_transaction_parameters - DP AUX request transaction data 2573 */ 2574 struct aux_transaction_parameters { 2575 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2576 uint8_t action; /**< enum dp_aux_request_action */ 2577 uint8_t length; /**< DP AUX request data length */ 2578 uint8_t reserved; /**< For future use */ 2579 uint32_t address; /**< DP AUX address */ 2580 uint8_t data[16]; /**< DP AUX write data */ 2581 }; 2582 2583 /** 2584 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2585 */ 2586 struct dmub_cmd_dp_aux_control_data { 2587 uint8_t instance; /**< AUX instance or DPIA instance */ 2588 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2589 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2590 uint8_t reserved0; /**< For future use */ 2591 uint16_t timeout; /**< timeout time in us */ 2592 uint16_t reserved1; /**< For future use */ 2593 enum aux_channel_type type; /**< enum aux_channel_type */ 2594 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2595 }; 2596 2597 /** 2598 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2599 */ 2600 struct dmub_rb_cmd_dp_aux_access { 2601 /** 2602 * Command header. 2603 */ 2604 struct dmub_cmd_header header; 2605 /** 2606 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2607 */ 2608 struct dmub_cmd_dp_aux_control_data aux_control; 2609 }; 2610 2611 /** 2612 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2613 */ 2614 struct dmub_rb_cmd_outbox1_enable { 2615 /** 2616 * Command header. 2617 */ 2618 struct dmub_cmd_header header; 2619 /** 2620 * enable: 0x0 -> disable outbox1 notification (default value) 2621 * 0x1 -> enable outbox1 notification 2622 */ 2623 uint32_t enable; 2624 }; 2625 2626 /* DP AUX Reply command - OutBox Cmd */ 2627 /** 2628 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2629 */ 2630 struct aux_reply_data { 2631 /** 2632 * Aux cmd 2633 */ 2634 uint8_t command; 2635 /** 2636 * Aux reply data length (max: 16 bytes) 2637 */ 2638 uint8_t length; 2639 /** 2640 * Alignment only 2641 */ 2642 uint8_t pad[2]; 2643 /** 2644 * Aux reply data 2645 */ 2646 uint8_t data[16]; 2647 }; 2648 2649 /** 2650 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2651 */ 2652 struct aux_reply_control_data { 2653 /** 2654 * Reserved for future use 2655 */ 2656 uint32_t handle; 2657 /** 2658 * Aux Instance 2659 */ 2660 uint8_t instance; 2661 /** 2662 * Aux transaction result: definition in enum aux_return_code_type 2663 */ 2664 uint8_t result; 2665 /** 2666 * Alignment only 2667 */ 2668 uint16_t pad; 2669 }; 2670 2671 /** 2672 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2673 */ 2674 struct dmub_rb_cmd_dp_aux_reply { 2675 /** 2676 * Command header. 2677 */ 2678 struct dmub_cmd_header header; 2679 /** 2680 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2681 */ 2682 struct aux_reply_control_data control; 2683 /** 2684 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2685 */ 2686 struct aux_reply_data reply_data; 2687 }; 2688 2689 /* DP HPD Notify command - OutBox Cmd */ 2690 /** 2691 * DP HPD Type 2692 */ 2693 enum dp_hpd_type { 2694 /** 2695 * Normal DP HPD 2696 */ 2697 DP_HPD = 0, 2698 /** 2699 * DP HPD short pulse 2700 */ 2701 DP_IRQ = 1, 2702 /** 2703 * Failure to acquire DP HPD state 2704 */ 2705 DP_NONE_HPD = 2 2706 }; 2707 2708 /** 2709 * DP HPD Status 2710 */ 2711 enum dp_hpd_status { 2712 /** 2713 * DP_HPD status low 2714 */ 2715 DP_HPD_UNPLUG = 0, 2716 /** 2717 * DP_HPD status high 2718 */ 2719 DP_HPD_PLUG 2720 }; 2721 2722 /** 2723 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2724 */ 2725 struct dp_hpd_data { 2726 /** 2727 * DP HPD instance 2728 */ 2729 uint8_t instance; 2730 /** 2731 * HPD type 2732 */ 2733 uint8_t hpd_type; 2734 /** 2735 * HPD status: only for type: DP_HPD to indicate status 2736 */ 2737 uint8_t hpd_status; 2738 /** 2739 * Alignment only 2740 */ 2741 uint8_t pad; 2742 }; 2743 2744 /** 2745 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2746 */ 2747 struct dmub_rb_cmd_dp_hpd_notify { 2748 /** 2749 * Command header. 2750 */ 2751 struct dmub_cmd_header header; 2752 /** 2753 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2754 */ 2755 struct dp_hpd_data hpd_data; 2756 }; 2757 2758 /** 2759 * Definition of a SET_CONFIG reply from DPOA. 2760 */ 2761 enum set_config_status { 2762 SET_CONFIG_PENDING = 0, 2763 SET_CONFIG_ACK_RECEIVED, 2764 SET_CONFIG_RX_TIMEOUT, 2765 SET_CONFIG_UNKNOWN_ERROR, 2766 }; 2767 2768 /** 2769 * Definition of a set_config reply 2770 */ 2771 struct set_config_reply_control_data { 2772 uint8_t instance; /* DPIA Instance */ 2773 uint8_t status; /* Set Config reply */ 2774 uint16_t pad; /* Alignment */ 2775 }; 2776 2777 /** 2778 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2779 */ 2780 struct dmub_rb_cmd_dp_set_config_reply { 2781 struct dmub_cmd_header header; 2782 struct set_config_reply_control_data set_config_reply_control; 2783 }; 2784 2785 /** 2786 * Definition of a DPIA notification header 2787 */ 2788 struct dpia_notification_header { 2789 uint8_t instance; /**< DPIA Instance */ 2790 uint8_t reserved[3]; 2791 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2792 }; 2793 2794 /** 2795 * Definition of the common data struct of DPIA notification 2796 */ 2797 struct dpia_notification_common { 2798 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2799 - sizeof(struct dpia_notification_header)]; 2800 }; 2801 2802 /** 2803 * Definition of a DPIA notification data 2804 */ 2805 struct dpia_bw_allocation_notify_data { 2806 union { 2807 struct { 2808 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2809 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2810 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2811 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2812 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2813 uint16_t reserved: 11; /**< Reserved */ 2814 } bits; 2815 2816 uint16_t flags; 2817 }; 2818 2819 uint8_t cm_id; /**< CM ID */ 2820 uint8_t group_id; /**< Group ID */ 2821 uint8_t granularity; /**< BW Allocation Granularity */ 2822 uint8_t estimated_bw; /**< Estimated_BW */ 2823 uint8_t allocated_bw; /**< Allocated_BW */ 2824 uint8_t reserved; 2825 }; 2826 2827 /** 2828 * union dpia_notify_data_type - DPIA Notification in Outbox command 2829 */ 2830 union dpia_notification_data { 2831 /** 2832 * DPIA Notification for common data struct 2833 */ 2834 struct dpia_notification_common common_data; 2835 2836 /** 2837 * DPIA Notification for DP BW Allocation support 2838 */ 2839 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2840 }; 2841 2842 /** 2843 * Definition of a DPIA notification payload 2844 */ 2845 struct dpia_notification_payload { 2846 struct dpia_notification_header header; 2847 union dpia_notification_data data; /**< DPIA notification payload data */ 2848 }; 2849 2850 /** 2851 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2852 */ 2853 struct dmub_rb_cmd_dpia_notification { 2854 struct dmub_cmd_header header; /**< DPIA notification header */ 2855 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2856 }; 2857 2858 /** 2859 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2860 */ 2861 struct dmub_cmd_hpd_state_query_data { 2862 uint8_t instance; /**< HPD instance or DPIA instance */ 2863 uint8_t result; /**< For returning HPD state */ 2864 uint16_t pad; /** < Alignment */ 2865 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2866 enum aux_return_code_type status; /**< for returning the status of command */ 2867 }; 2868 2869 /** 2870 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2871 */ 2872 struct dmub_rb_cmd_query_hpd_state { 2873 /** 2874 * Command header. 2875 */ 2876 struct dmub_cmd_header header; 2877 /** 2878 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2879 */ 2880 struct dmub_cmd_hpd_state_query_data data; 2881 }; 2882 2883 /** 2884 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2885 */ 2886 struct dmub_rb_cmd_hpd_sense_notify_data { 2887 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2888 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2889 }; 2890 2891 /** 2892 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2893 */ 2894 struct dmub_rb_cmd_hpd_sense_notify { 2895 struct dmub_cmd_header header; /**< header */ 2896 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2897 }; 2898 2899 /* 2900 * Command IDs should be treated as stable ABI. 2901 * Do not reuse or modify IDs. 2902 */ 2903 2904 /** 2905 * PSR command sub-types. 2906 */ 2907 enum dmub_cmd_psr_type { 2908 /** 2909 * Set PSR version support. 2910 */ 2911 DMUB_CMD__PSR_SET_VERSION = 0, 2912 /** 2913 * Copy driver-calculated parameters to PSR state. 2914 */ 2915 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2916 /** 2917 * Enable PSR. 2918 */ 2919 DMUB_CMD__PSR_ENABLE = 2, 2920 2921 /** 2922 * Disable PSR. 2923 */ 2924 DMUB_CMD__PSR_DISABLE = 3, 2925 2926 /** 2927 * Set PSR level. 2928 * PSR level is a 16-bit value dicated by driver that 2929 * will enable/disable different functionality. 2930 */ 2931 DMUB_CMD__PSR_SET_LEVEL = 4, 2932 2933 /** 2934 * Forces PSR enabled until an explicit PSR disable call. 2935 */ 2936 DMUB_CMD__PSR_FORCE_STATIC = 5, 2937 /** 2938 * Set vtotal in psr active for FreeSync PSR. 2939 */ 2940 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2941 /** 2942 * Set PSR power option 2943 */ 2944 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2945 }; 2946 2947 /** 2948 * Different PSR residency modes. 2949 * Different modes change the definition of PSR residency. 2950 */ 2951 enum psr_residency_mode { 2952 PSR_RESIDENCY_MODE_PHY = 0, 2953 PSR_RESIDENCY_MODE_ALPM, 2954 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2955 /* Do not add below. */ 2956 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2957 }; 2958 2959 enum dmub_cmd_fams_type { 2960 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2961 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2962 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2963 /** 2964 * For SubVP set manual trigger in FW because it 2965 * triggers DRR_UPDATE_PENDING which SubVP relies 2966 * on (for any SubVP cases that use a DRR display) 2967 */ 2968 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2969 DMUB_CMD__FAMS2_CONFIG = 4, 2970 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2971 DMUB_CMD__FAMS2_FLIP = 6, 2972 DMUB_CMD__FAMS2_IB_CONFIG = 7, 2973 }; 2974 2975 /** 2976 * PSR versions. 2977 */ 2978 enum psr_version { 2979 /** 2980 * PSR version 1. 2981 */ 2982 PSR_VERSION_1 = 0, 2983 /** 2984 * Freesync PSR SU. 2985 */ 2986 PSR_VERSION_SU_1 = 1, 2987 /** 2988 * PSR not supported. 2989 */ 2990 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2991 }; 2992 2993 /** 2994 * PHY Link rate for DP. 2995 */ 2996 enum phy_link_rate { 2997 /** 2998 * not supported. 2999 */ 3000 PHY_RATE_UNKNOWN = 0, 3001 /** 3002 * Rate_1 (RBR) - 1.62 Gbps/Lane 3003 */ 3004 PHY_RATE_162 = 1, 3005 /** 3006 * Rate_2 - 2.16 Gbps/Lane 3007 */ 3008 PHY_RATE_216 = 2, 3009 /** 3010 * Rate_3 - 2.43 Gbps/Lane 3011 */ 3012 PHY_RATE_243 = 3, 3013 /** 3014 * Rate_4 (HBR) - 2.70 Gbps/Lane 3015 */ 3016 PHY_RATE_270 = 4, 3017 /** 3018 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3019 */ 3020 PHY_RATE_324 = 5, 3021 /** 3022 * Rate_6 - 4.32 Gbps/Lane 3023 */ 3024 PHY_RATE_432 = 6, 3025 /** 3026 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3027 */ 3028 PHY_RATE_540 = 7, 3029 /** 3030 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3031 */ 3032 PHY_RATE_810 = 8, 3033 /** 3034 * UHBR10 - 10.0 Gbps/Lane 3035 */ 3036 PHY_RATE_1000 = 9, 3037 /** 3038 * UHBR13.5 - 13.5 Gbps/Lane 3039 */ 3040 PHY_RATE_1350 = 10, 3041 /** 3042 * UHBR10 - 20.0 Gbps/Lane 3043 */ 3044 PHY_RATE_2000 = 11, 3045 3046 PHY_RATE_675 = 12, 3047 /** 3048 * Rate 12 - 6.75 Gbps/Lane 3049 */ 3050 }; 3051 3052 /** 3053 * enum dmub_phy_fsm_state - PHY FSM states. 3054 * PHY FSM state to transit to during PSR enable/disable. 3055 */ 3056 enum dmub_phy_fsm_state { 3057 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3058 DMUB_PHY_FSM_RESET, 3059 DMUB_PHY_FSM_RESET_RELEASED, 3060 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3061 DMUB_PHY_FSM_INITIALIZED, 3062 DMUB_PHY_FSM_CALIBRATED, 3063 DMUB_PHY_FSM_CALIBRATED_LP, 3064 DMUB_PHY_FSM_CALIBRATED_PG, 3065 DMUB_PHY_FSM_POWER_DOWN, 3066 DMUB_PHY_FSM_PLL_EN, 3067 DMUB_PHY_FSM_TX_EN, 3068 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3069 DMUB_PHY_FSM_FAST_LP, 3070 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3071 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3072 DMUB_PHY_FSM_P2_PLL_OFF, 3073 DMUB_PHY_FSM_P2_PLL_ON, 3074 }; 3075 3076 /** 3077 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3078 */ 3079 struct dmub_cmd_psr_copy_settings_data { 3080 /** 3081 * Flags that can be set by driver to change some PSR behaviour. 3082 */ 3083 union dmub_psr_debug_flags debug; 3084 /** 3085 * 16-bit value dicated by driver that will enable/disable different functionality. 3086 */ 3087 uint16_t psr_level; 3088 /** 3089 * DPP HW instance. 3090 */ 3091 uint8_t dpp_inst; 3092 /** 3093 * MPCC HW instance. 3094 * Not used in dmub fw, 3095 * dmub fw will get active opp by reading odm registers. 3096 */ 3097 uint8_t mpcc_inst; 3098 /** 3099 * OPP HW instance. 3100 * Not used in dmub fw, 3101 * dmub fw will get active opp by reading odm registers. 3102 */ 3103 uint8_t opp_inst; 3104 /** 3105 * OTG HW instance. 3106 */ 3107 uint8_t otg_inst; 3108 /** 3109 * DIG FE HW instance. 3110 */ 3111 uint8_t digfe_inst; 3112 /** 3113 * DIG BE HW instance. 3114 */ 3115 uint8_t digbe_inst; 3116 /** 3117 * DP PHY HW instance. 3118 */ 3119 uint8_t dpphy_inst; 3120 /** 3121 * AUX HW instance. 3122 */ 3123 uint8_t aux_inst; 3124 /** 3125 * Determines if SMU optimzations are enabled/disabled. 3126 */ 3127 uint8_t smu_optimizations_en; 3128 /** 3129 * Unused. 3130 * TODO: Remove. 3131 */ 3132 uint8_t frame_delay; 3133 /** 3134 * If RFB setup time is greater than the total VBLANK time, 3135 * it is not possible for the sink to capture the video frame 3136 * in the same frame the SDP is sent. In this case, 3137 * the frame capture indication bit should be set and an extra 3138 * static frame should be transmitted to the sink. 3139 */ 3140 uint8_t frame_cap_ind; 3141 /** 3142 * Granularity of Y offset supported by sink. 3143 */ 3144 uint8_t su_y_granularity; 3145 /** 3146 * Indicates whether sink should start capturing 3147 * immediately following active scan line, 3148 * or starting with the 2nd active scan line. 3149 */ 3150 uint8_t line_capture_indication; 3151 /** 3152 * Multi-display optimizations are implemented on certain ASICs. 3153 */ 3154 uint8_t multi_disp_optimizations_en; 3155 /** 3156 * The last possible line SDP may be transmitted without violating 3157 * the RFB setup time or entering the active video frame. 3158 */ 3159 uint16_t init_sdp_deadline; 3160 /** 3161 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3162 */ 3163 uint8_t rate_control_caps ; 3164 /* 3165 * Force PSRSU always doing full frame update 3166 */ 3167 uint8_t force_ffu_mode; 3168 /** 3169 * Length of each horizontal line in us. 3170 */ 3171 uint32_t line_time_in_us; 3172 /** 3173 * FEC enable status in driver 3174 */ 3175 uint8_t fec_enable_status; 3176 /** 3177 * FEC re-enable delay when PSR exit. 3178 * unit is 100us, range form 0~255(0xFF). 3179 */ 3180 uint8_t fec_enable_delay_in100us; 3181 /** 3182 * PSR control version. 3183 */ 3184 uint8_t cmd_version; 3185 /** 3186 * Panel Instance. 3187 * Panel instance to identify which psr_state to use 3188 * Currently the support is only for 0 or 1 3189 */ 3190 uint8_t panel_inst; 3191 /* 3192 * DSC enable status in driver 3193 */ 3194 uint8_t dsc_enable_status; 3195 /* 3196 * Use FSM state for PSR power up/down 3197 */ 3198 uint8_t use_phy_fsm; 3199 /** 3200 * frame delay for frame re-lock 3201 */ 3202 uint8_t relock_delay_frame_cnt; 3203 /** 3204 * esd recovery indicate. 3205 */ 3206 uint8_t esd_recovery; 3207 /** 3208 * DSC Slice height. 3209 */ 3210 uint16_t dsc_slice_height; 3211 /** 3212 * Some panels request main link off before xth vertical line 3213 */ 3214 uint16_t poweroff_before_vertical_line; 3215 /** 3216 * Some panels cannot handle idle pattern during PSR entry. 3217 * To power down phy before disable stream to avoid sending 3218 * idle pattern. 3219 */ 3220 uint8_t power_down_phy_before_disable_stream; 3221 }; 3222 3223 /** 3224 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3225 */ 3226 struct dmub_rb_cmd_psr_copy_settings { 3227 /** 3228 * Command header. 3229 */ 3230 struct dmub_cmd_header header; 3231 /** 3232 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3233 */ 3234 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3235 }; 3236 3237 /** 3238 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3239 */ 3240 struct dmub_cmd_psr_set_level_data { 3241 /** 3242 * 16-bit value dicated by driver that will enable/disable different functionality. 3243 */ 3244 uint16_t psr_level; 3245 /** 3246 * PSR control version. 3247 */ 3248 uint8_t cmd_version; 3249 /** 3250 * Panel Instance. 3251 * Panel instance to identify which psr_state to use 3252 * Currently the support is only for 0 or 1 3253 */ 3254 uint8_t panel_inst; 3255 }; 3256 3257 /** 3258 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3259 */ 3260 struct dmub_rb_cmd_psr_set_level { 3261 /** 3262 * Command header. 3263 */ 3264 struct dmub_cmd_header header; 3265 /** 3266 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3267 */ 3268 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3269 }; 3270 3271 struct dmub_rb_cmd_psr_enable_data { 3272 /** 3273 * PSR control version. 3274 */ 3275 uint8_t cmd_version; 3276 /** 3277 * Panel Instance. 3278 * Panel instance to identify which psr_state to use 3279 * Currently the support is only for 0 or 1 3280 */ 3281 uint8_t panel_inst; 3282 /** 3283 * Phy state to enter. 3284 * Values to use are defined in dmub_phy_fsm_state 3285 */ 3286 uint8_t phy_fsm_state; 3287 /** 3288 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3289 * Set this using enum phy_link_rate. 3290 * This does not support HDMI/DP2 for now. 3291 */ 3292 uint8_t phy_rate; 3293 }; 3294 3295 /** 3296 * Definition of a DMUB_CMD__PSR_ENABLE command. 3297 * PSR enable/disable is controlled using the sub_type. 3298 */ 3299 struct dmub_rb_cmd_psr_enable { 3300 /** 3301 * Command header. 3302 */ 3303 struct dmub_cmd_header header; 3304 3305 struct dmub_rb_cmd_psr_enable_data data; 3306 }; 3307 3308 /** 3309 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3310 */ 3311 struct dmub_cmd_psr_set_version_data { 3312 /** 3313 * PSR version that FW should implement. 3314 */ 3315 enum psr_version version; 3316 /** 3317 * PSR control version. 3318 */ 3319 uint8_t cmd_version; 3320 /** 3321 * Panel Instance. 3322 * Panel instance to identify which psr_state to use 3323 * Currently the support is only for 0 or 1 3324 */ 3325 uint8_t panel_inst; 3326 /** 3327 * Explicit padding to 4 byte boundary. 3328 */ 3329 uint8_t pad[2]; 3330 }; 3331 3332 /** 3333 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3334 */ 3335 struct dmub_rb_cmd_psr_set_version { 3336 /** 3337 * Command header. 3338 */ 3339 struct dmub_cmd_header header; 3340 /** 3341 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3342 */ 3343 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3344 }; 3345 3346 struct dmub_cmd_psr_force_static_data { 3347 /** 3348 * PSR control version. 3349 */ 3350 uint8_t cmd_version; 3351 /** 3352 * Panel Instance. 3353 * Panel instance to identify which psr_state to use 3354 * Currently the support is only for 0 or 1 3355 */ 3356 uint8_t panel_inst; 3357 /** 3358 * Explicit padding to 4 byte boundary. 3359 */ 3360 uint8_t pad[2]; 3361 }; 3362 3363 /** 3364 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3365 */ 3366 struct dmub_rb_cmd_psr_force_static { 3367 /** 3368 * Command header. 3369 */ 3370 struct dmub_cmd_header header; 3371 /** 3372 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3373 */ 3374 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3375 }; 3376 3377 /** 3378 * PSR SU debug flags. 3379 */ 3380 union dmub_psr_su_debug_flags { 3381 /** 3382 * PSR SU debug flags. 3383 */ 3384 struct { 3385 /** 3386 * Update dirty rect in SW only. 3387 */ 3388 uint8_t update_dirty_rect_only : 1; 3389 /** 3390 * Reset the cursor/plane state before processing the call. 3391 */ 3392 uint8_t reset_state : 1; 3393 } bitfields; 3394 3395 /** 3396 * Union for debug flags. 3397 */ 3398 uint32_t u32All; 3399 }; 3400 3401 /** 3402 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3403 * This triggers a selective update for PSR SU. 3404 */ 3405 struct dmub_cmd_update_dirty_rect_data { 3406 /** 3407 * Dirty rects from OS. 3408 */ 3409 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3410 /** 3411 * PSR SU debug flags. 3412 */ 3413 union dmub_psr_su_debug_flags debug_flags; 3414 /** 3415 * OTG HW instance. 3416 */ 3417 uint8_t pipe_idx; 3418 /** 3419 * Number of dirty rects. 3420 */ 3421 uint8_t dirty_rect_count; 3422 /** 3423 * PSR control version. 3424 */ 3425 uint8_t cmd_version; 3426 /** 3427 * Panel Instance. 3428 * Panel instance to identify which psr_state to use 3429 * Currently the support is only for 0 or 1 3430 */ 3431 uint8_t panel_inst; 3432 }; 3433 3434 /** 3435 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3436 */ 3437 struct dmub_rb_cmd_update_dirty_rect { 3438 /** 3439 * Command header. 3440 */ 3441 struct dmub_cmd_header header; 3442 /** 3443 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3444 */ 3445 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3446 }; 3447 3448 /** 3449 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3450 */ 3451 union dmub_reg_cursor_control_cfg { 3452 struct { 3453 uint32_t cur_enable: 1; 3454 uint32_t reser0: 3; 3455 uint32_t cur_2x_magnify: 1; 3456 uint32_t reser1: 3; 3457 uint32_t mode: 3; 3458 uint32_t reser2: 5; 3459 uint32_t pitch: 2; 3460 uint32_t reser3: 6; 3461 uint32_t line_per_chunk: 5; 3462 uint32_t reser4: 3; 3463 } bits; 3464 uint32_t raw; 3465 }; 3466 struct dmub_cursor_position_cache_hubp { 3467 union dmub_reg_cursor_control_cfg cur_ctl; 3468 union dmub_reg_position_cfg { 3469 struct { 3470 uint32_t cur_x_pos: 16; 3471 uint32_t cur_y_pos: 16; 3472 } bits; 3473 uint32_t raw; 3474 } position; 3475 union dmub_reg_hot_spot_cfg { 3476 struct { 3477 uint32_t hot_x: 16; 3478 uint32_t hot_y: 16; 3479 } bits; 3480 uint32_t raw; 3481 } hot_spot; 3482 union dmub_reg_dst_offset_cfg { 3483 struct { 3484 uint32_t dst_x_offset: 13; 3485 uint32_t reserved: 19; 3486 } bits; 3487 uint32_t raw; 3488 } dst_offset; 3489 }; 3490 3491 union dmub_reg_cur0_control_cfg { 3492 struct { 3493 uint32_t cur0_enable: 1; 3494 uint32_t expansion_mode: 1; 3495 uint32_t reser0: 1; 3496 uint32_t cur0_rom_en: 1; 3497 uint32_t mode: 3; 3498 uint32_t reserved: 25; 3499 } bits; 3500 uint32_t raw; 3501 }; 3502 struct dmub_cursor_position_cache_dpp { 3503 union dmub_reg_cur0_control_cfg cur0_ctl; 3504 }; 3505 struct dmub_cursor_position_cfg { 3506 struct dmub_cursor_position_cache_hubp pHubp; 3507 struct dmub_cursor_position_cache_dpp pDpp; 3508 uint8_t pipe_idx; 3509 /* 3510 * Padding is required. To be 4 Bytes Aligned. 3511 */ 3512 uint8_t padding[3]; 3513 }; 3514 3515 struct dmub_cursor_attribute_cache_hubp { 3516 uint32_t SURFACE_ADDR_HIGH; 3517 uint32_t SURFACE_ADDR; 3518 union dmub_reg_cursor_control_cfg cur_ctl; 3519 union dmub_reg_cursor_size_cfg { 3520 struct { 3521 uint32_t width: 16; 3522 uint32_t height: 16; 3523 } bits; 3524 uint32_t raw; 3525 } size; 3526 union dmub_reg_cursor_settings_cfg { 3527 struct { 3528 uint32_t dst_y_offset: 8; 3529 uint32_t chunk_hdl_adjust: 2; 3530 uint32_t reserved: 22; 3531 } bits; 3532 uint32_t raw; 3533 } settings; 3534 }; 3535 struct dmub_cursor_attribute_cache_dpp { 3536 union dmub_reg_cur0_control_cfg cur0_ctl; 3537 }; 3538 struct dmub_cursor_attributes_cfg { 3539 struct dmub_cursor_attribute_cache_hubp aHubp; 3540 struct dmub_cursor_attribute_cache_dpp aDpp; 3541 }; 3542 3543 struct dmub_cmd_update_cursor_payload0 { 3544 /** 3545 * Cursor dirty rects. 3546 */ 3547 struct dmub_rect cursor_rect; 3548 /** 3549 * PSR SU debug flags. 3550 */ 3551 union dmub_psr_su_debug_flags debug_flags; 3552 /** 3553 * Cursor enable/disable. 3554 */ 3555 uint8_t enable; 3556 /** 3557 * OTG HW instance. 3558 */ 3559 uint8_t pipe_idx; 3560 /** 3561 * PSR control version. 3562 */ 3563 uint8_t cmd_version; 3564 /** 3565 * Panel Instance. 3566 * Panel instance to identify which psr_state to use 3567 * Currently the support is only for 0 or 1 3568 */ 3569 uint8_t panel_inst; 3570 /** 3571 * Cursor Position Register. 3572 * Registers contains Hubp & Dpp modules 3573 */ 3574 struct dmub_cursor_position_cfg position_cfg; 3575 }; 3576 3577 struct dmub_cmd_update_cursor_payload1 { 3578 struct dmub_cursor_attributes_cfg attribute_cfg; 3579 }; 3580 3581 union dmub_cmd_update_cursor_info_data { 3582 struct dmub_cmd_update_cursor_payload0 payload0; 3583 struct dmub_cmd_update_cursor_payload1 payload1; 3584 }; 3585 /** 3586 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3587 */ 3588 struct dmub_rb_cmd_update_cursor_info { 3589 /** 3590 * Command header. 3591 */ 3592 struct dmub_cmd_header header; 3593 /** 3594 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3595 */ 3596 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3597 }; 3598 3599 /** 3600 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3601 */ 3602 struct dmub_cmd_psr_set_vtotal_data { 3603 /** 3604 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3605 */ 3606 uint16_t psr_vtotal_idle; 3607 /** 3608 * PSR control version. 3609 */ 3610 uint8_t cmd_version; 3611 /** 3612 * Panel Instance. 3613 * Panel instance to identify which psr_state to use 3614 * Currently the support is only for 0 or 1 3615 */ 3616 uint8_t panel_inst; 3617 /* 3618 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3619 */ 3620 uint16_t psr_vtotal_su; 3621 /** 3622 * Explicit padding to 4 byte boundary. 3623 */ 3624 uint8_t pad2[2]; 3625 }; 3626 3627 /** 3628 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3629 */ 3630 struct dmub_rb_cmd_psr_set_vtotal { 3631 /** 3632 * Command header. 3633 */ 3634 struct dmub_cmd_header header; 3635 /** 3636 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3637 */ 3638 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3639 }; 3640 3641 /** 3642 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3643 */ 3644 struct dmub_cmd_psr_set_power_opt_data { 3645 /** 3646 * PSR control version. 3647 */ 3648 uint8_t cmd_version; 3649 /** 3650 * Panel Instance. 3651 * Panel instance to identify which psr_state to use 3652 * Currently the support is only for 0 or 1 3653 */ 3654 uint8_t panel_inst; 3655 /** 3656 * Explicit padding to 4 byte boundary. 3657 */ 3658 uint8_t pad[2]; 3659 /** 3660 * PSR power option 3661 */ 3662 uint32_t power_opt; 3663 }; 3664 3665 /** 3666 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3667 */ 3668 struct dmub_rb_cmd_psr_set_power_opt { 3669 /** 3670 * Command header. 3671 */ 3672 struct dmub_cmd_header header; 3673 /** 3674 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3675 */ 3676 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3677 }; 3678 3679 enum dmub_alpm_mode { 3680 ALPM_AUXWAKE = 0, 3681 ALPM_AUXLESS = 1, 3682 ALPM_UNSUPPORTED = 2, 3683 }; 3684 3685 /** 3686 * Definition of Replay Residency GPINT command. 3687 * Bit[0] - Residency mode for Revision 0 3688 * Bit[1] - Enable/Disable state 3689 * Bit[2-3] - Revision number 3690 * Bit[4-7] - Residency mode for Revision 1 3691 * Bit[8] - Panel instance 3692 * Bit[9-15] - Reserved 3693 */ 3694 3695 enum pr_residency_mode { 3696 PR_RESIDENCY_MODE_PHY = 0x0, 3697 PR_RESIDENCY_MODE_ALPM, 3698 PR_RESIDENCY_MODE_IPS2, 3699 PR_RESIDENCY_MODE_FRAME_CNT, 3700 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3701 }; 3702 3703 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3704 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3705 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3706 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3707 3708 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3709 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3710 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3711 3712 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3713 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3714 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3715 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3716 3717 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3718 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3719 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3720 3721 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3722 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3723 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3724 3725 /** 3726 * Definition of a replay_state. 3727 */ 3728 enum replay_state { 3729 REPLAY_STATE_0 = 0x0, 3730 REPLAY_STATE_1 = 0x10, 3731 REPLAY_STATE_1A = 0x11, 3732 REPLAY_STATE_2 = 0x20, 3733 REPLAY_STATE_2A = 0x21, 3734 REPLAY_STATE_3 = 0x30, 3735 REPLAY_STATE_3INIT = 0x31, 3736 REPLAY_STATE_4 = 0x40, 3737 REPLAY_STATE_4A = 0x41, 3738 REPLAY_STATE_4B = 0x42, 3739 REPLAY_STATE_4C = 0x43, 3740 REPLAY_STATE_4D = 0x44, 3741 REPLAY_STATE_4E = 0x45, 3742 REPLAY_STATE_4B_LOCKED = 0x4A, 3743 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3744 REPLAY_STATE_5 = 0x50, 3745 REPLAY_STATE_5A = 0x51, 3746 REPLAY_STATE_5B = 0x52, 3747 REPLAY_STATE_5A_LOCKED = 0x5A, 3748 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3749 REPLAY_STATE_6 = 0x60, 3750 REPLAY_STATE_6A = 0x61, 3751 REPLAY_STATE_6B = 0x62, 3752 REPLAY_STATE_INVALID = 0xFF, 3753 }; 3754 3755 /** 3756 * Replay command sub-types. 3757 */ 3758 enum dmub_cmd_replay_type { 3759 /** 3760 * Copy driver-calculated parameters to REPLAY state. 3761 */ 3762 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3763 /** 3764 * Enable REPLAY. 3765 */ 3766 DMUB_CMD__REPLAY_ENABLE = 1, 3767 /** 3768 * Set Replay power option. 3769 */ 3770 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3771 /** 3772 * Set coasting vtotal. 3773 */ 3774 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3775 /** 3776 * Set power opt and coasting vtotal. 3777 */ 3778 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3779 /** 3780 * Set disabled iiming sync. 3781 */ 3782 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3783 /** 3784 * Set Residency Frameupdate Timer. 3785 */ 3786 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3787 /** 3788 * Set pseudo vtotal 3789 */ 3790 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3791 /** 3792 * Set adaptive sync sdp enabled 3793 */ 3794 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3795 /** 3796 * Set Replay General command. 3797 */ 3798 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3799 }; 3800 3801 /** 3802 * Replay general command sub-types. 3803 */ 3804 enum dmub_cmd_replay_general_subtype { 3805 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3806 /** 3807 * TODO: For backward compatible, allow new command only. 3808 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3809 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3810 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3811 */ 3812 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3813 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3814 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 3815 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 3816 }; 3817 3818 struct dmub_alpm_auxless_data { 3819 uint16_t lfps_setup_ns; 3820 uint16_t lfps_period_ns; 3821 uint16_t lfps_silence_ns; 3822 uint16_t lfps_t1_t2_override_us; 3823 short lfps_t1_t2_offset_us; 3824 uint8_t lttpr_count; 3825 }; 3826 3827 /** 3828 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3829 */ 3830 struct dmub_cmd_replay_copy_settings_data { 3831 /** 3832 * Flags that can be set by driver to change some replay behaviour. 3833 */ 3834 union replay_debug_flags debug; 3835 3836 /** 3837 * @flags: Flags used to determine feature functionality. 3838 */ 3839 union replay_hw_flags flags; 3840 3841 /** 3842 * DPP HW instance. 3843 */ 3844 uint8_t dpp_inst; 3845 /** 3846 * OTG HW instance. 3847 */ 3848 uint8_t otg_inst; 3849 /** 3850 * DIG FE HW instance. 3851 */ 3852 uint8_t digfe_inst; 3853 /** 3854 * DIG BE HW instance. 3855 */ 3856 uint8_t digbe_inst; 3857 /** 3858 * AUX HW instance. 3859 */ 3860 uint8_t aux_inst; 3861 /** 3862 * Panel Instance. 3863 * Panel isntance to identify which psr_state to use 3864 * Currently the support is only for 0 or 1 3865 */ 3866 uint8_t panel_inst; 3867 /** 3868 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3869 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3870 */ 3871 uint8_t pixel_deviation_per_line; 3872 /** 3873 * @max_deviation_line: The max number of deviation line that can keep the timing 3874 * synchronized between the Source and Sink during Replay normal sleep mode. 3875 */ 3876 uint8_t max_deviation_line; 3877 /** 3878 * Length of each horizontal line in ns. 3879 */ 3880 uint32_t line_time_in_ns; 3881 /** 3882 * PHY instance. 3883 */ 3884 uint8_t dpphy_inst; 3885 /** 3886 * Determines if SMU optimzations are enabled/disabled. 3887 */ 3888 uint8_t smu_optimizations_en; 3889 /** 3890 * Determines if timing sync are enabled/disabled. 3891 */ 3892 uint8_t replay_timing_sync_supported; 3893 /* 3894 * Use FSM state for Replay power up/down 3895 */ 3896 uint8_t use_phy_fsm; 3897 /** 3898 * Use for AUX-less ALPM LFPS wake operation 3899 */ 3900 struct dmub_alpm_auxless_data auxless_alpm_data; 3901 }; 3902 3903 /** 3904 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3905 */ 3906 struct dmub_rb_cmd_replay_copy_settings { 3907 /** 3908 * Command header. 3909 */ 3910 struct dmub_cmd_header header; 3911 /** 3912 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3913 */ 3914 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3915 }; 3916 3917 /** 3918 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3919 */ 3920 enum replay_enable { 3921 /** 3922 * Disable REPLAY. 3923 */ 3924 REPLAY_DISABLE = 0, 3925 /** 3926 * Enable REPLAY. 3927 */ 3928 REPLAY_ENABLE = 1, 3929 }; 3930 3931 /** 3932 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3933 */ 3934 struct dmub_rb_cmd_replay_enable_data { 3935 /** 3936 * Replay enable or disable. 3937 */ 3938 uint8_t enable; 3939 /** 3940 * Panel Instance. 3941 * Panel isntance to identify which replay_state to use 3942 * Currently the support is only for 0 or 1 3943 */ 3944 uint8_t panel_inst; 3945 /** 3946 * Phy state to enter. 3947 * Values to use are defined in dmub_phy_fsm_state 3948 */ 3949 uint8_t phy_fsm_state; 3950 /** 3951 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3952 * Set this using enum phy_link_rate. 3953 * This does not support HDMI/DP2 for now. 3954 */ 3955 uint8_t phy_rate; 3956 }; 3957 3958 /** 3959 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3960 * Replay enable/disable is controlled using action in data. 3961 */ 3962 struct dmub_rb_cmd_replay_enable { 3963 /** 3964 * Command header. 3965 */ 3966 struct dmub_cmd_header header; 3967 3968 struct dmub_rb_cmd_replay_enable_data data; 3969 }; 3970 3971 /** 3972 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3973 */ 3974 struct dmub_cmd_replay_set_power_opt_data { 3975 /** 3976 * Panel Instance. 3977 * Panel isntance to identify which replay_state to use 3978 * Currently the support is only for 0 or 1 3979 */ 3980 uint8_t panel_inst; 3981 /** 3982 * Explicit padding to 4 byte boundary. 3983 */ 3984 uint8_t pad[3]; 3985 /** 3986 * REPLAY power option 3987 */ 3988 uint32_t power_opt; 3989 }; 3990 3991 /** 3992 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3993 */ 3994 struct dmub_cmd_replay_set_timing_sync_data { 3995 /** 3996 * Panel Instance. 3997 * Panel isntance to identify which replay_state to use 3998 * Currently the support is only for 0 or 1 3999 */ 4000 uint8_t panel_inst; 4001 /** 4002 * REPLAY set_timing_sync 4003 */ 4004 uint8_t timing_sync_supported; 4005 /** 4006 * Explicit padding to 4 byte boundary. 4007 */ 4008 uint8_t pad[2]; 4009 }; 4010 4011 /** 4012 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4013 */ 4014 struct dmub_cmd_replay_set_pseudo_vtotal { 4015 /** 4016 * Panel Instance. 4017 * Panel isntance to identify which replay_state to use 4018 * Currently the support is only for 0 or 1 4019 */ 4020 uint8_t panel_inst; 4021 /** 4022 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4023 */ 4024 uint16_t vtotal; 4025 /** 4026 * Explicit padding to 4 byte boundary. 4027 */ 4028 uint8_t pad; 4029 }; 4030 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4031 /** 4032 * Panel Instance. 4033 * Panel isntance to identify which replay_state to use 4034 * Currently the support is only for 0 or 1 4035 */ 4036 uint8_t panel_inst; 4037 /** 4038 * enabled: set adaptive sync sdp enabled 4039 */ 4040 uint8_t force_disabled; 4041 4042 uint8_t pad[2]; 4043 }; 4044 struct dmub_cmd_replay_set_general_cmd_data { 4045 /** 4046 * Panel Instance. 4047 * Panel isntance to identify which replay_state to use 4048 * Currently the support is only for 0 or 1 4049 */ 4050 uint8_t panel_inst; 4051 /** 4052 * subtype: replay general cmd sub type 4053 */ 4054 uint8_t subtype; 4055 4056 uint8_t pad[2]; 4057 /** 4058 * config data with param1 and param2 4059 */ 4060 uint32_t param1; 4061 4062 uint32_t param2; 4063 }; 4064 4065 /** 4066 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4067 */ 4068 struct dmub_rb_cmd_replay_set_power_opt { 4069 /** 4070 * Command header. 4071 */ 4072 struct dmub_cmd_header header; 4073 /** 4074 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4075 */ 4076 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4077 }; 4078 4079 /** 4080 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4081 */ 4082 struct dmub_cmd_replay_set_coasting_vtotal_data { 4083 /** 4084 * 16-bit value dicated by driver that indicates the coasting vtotal. 4085 */ 4086 uint16_t coasting_vtotal; 4087 /** 4088 * REPLAY control version. 4089 */ 4090 uint8_t cmd_version; 4091 /** 4092 * Panel Instance. 4093 * Panel isntance to identify which replay_state to use 4094 * Currently the support is only for 0 or 1 4095 */ 4096 uint8_t panel_inst; 4097 /** 4098 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4099 */ 4100 uint16_t coasting_vtotal_high; 4101 /** 4102 * Explicit padding to 4 byte boundary. 4103 */ 4104 uint8_t pad[2]; 4105 }; 4106 4107 /** 4108 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4109 */ 4110 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4111 /** 4112 * Command header. 4113 */ 4114 struct dmub_cmd_header header; 4115 /** 4116 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4117 */ 4118 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4119 }; 4120 4121 /** 4122 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4123 */ 4124 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4125 /** 4126 * Command header. 4127 */ 4128 struct dmub_cmd_header header; 4129 /** 4130 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4131 */ 4132 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4133 /** 4134 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4135 */ 4136 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4137 }; 4138 4139 /** 4140 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4141 */ 4142 struct dmub_rb_cmd_replay_set_timing_sync { 4143 /** 4144 * Command header. 4145 */ 4146 struct dmub_cmd_header header; 4147 /** 4148 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4149 */ 4150 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4151 }; 4152 4153 /** 4154 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4155 */ 4156 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4157 /** 4158 * Command header. 4159 */ 4160 struct dmub_cmd_header header; 4161 /** 4162 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4163 */ 4164 struct dmub_cmd_replay_set_pseudo_vtotal data; 4165 }; 4166 4167 /** 4168 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4169 */ 4170 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4171 /** 4172 * Command header. 4173 */ 4174 struct dmub_cmd_header header; 4175 /** 4176 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4177 */ 4178 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4179 }; 4180 4181 /** 4182 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4183 */ 4184 struct dmub_rb_cmd_replay_set_general_cmd { 4185 /** 4186 * Command header. 4187 */ 4188 struct dmub_cmd_header header; 4189 /** 4190 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4191 */ 4192 struct dmub_cmd_replay_set_general_cmd_data data; 4193 }; 4194 4195 /** 4196 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4197 */ 4198 struct dmub_cmd_replay_frameupdate_timer_data { 4199 /** 4200 * Panel Instance. 4201 * Panel isntance to identify which replay_state to use 4202 * Currently the support is only for 0 or 1 4203 */ 4204 uint8_t panel_inst; 4205 /** 4206 * Replay Frameupdate Timer Enable or not 4207 */ 4208 uint8_t enable; 4209 /** 4210 * REPLAY force reflash frame update number 4211 */ 4212 uint16_t frameupdate_count; 4213 }; 4214 /** 4215 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4216 */ 4217 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4218 /** 4219 * Command header. 4220 */ 4221 struct dmub_cmd_header header; 4222 /** 4223 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4224 */ 4225 struct dmub_cmd_replay_frameupdate_timer_data data; 4226 }; 4227 4228 /** 4229 * Definition union of replay command set 4230 */ 4231 union dmub_replay_cmd_set { 4232 /** 4233 * Panel Instance. 4234 * Panel isntance to identify which replay_state to use 4235 * Currently the support is only for 0 or 1 4236 */ 4237 uint8_t panel_inst; 4238 /** 4239 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4240 */ 4241 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4242 /** 4243 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4244 */ 4245 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4246 /** 4247 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4248 */ 4249 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4250 /** 4251 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4252 */ 4253 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4254 /** 4255 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4256 */ 4257 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4258 }; 4259 4260 /** 4261 * Set of HW components that can be locked. 4262 * 4263 * Note: If updating with more HW components, fields 4264 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4265 */ 4266 union dmub_hw_lock_flags { 4267 /** 4268 * Set of HW components that can be locked. 4269 */ 4270 struct { 4271 /** 4272 * Lock/unlock OTG master update lock. 4273 */ 4274 uint8_t lock_pipe : 1; 4275 /** 4276 * Lock/unlock cursor. 4277 */ 4278 uint8_t lock_cursor : 1; 4279 /** 4280 * Lock/unlock global update lock. 4281 */ 4282 uint8_t lock_dig : 1; 4283 /** 4284 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4285 */ 4286 uint8_t triple_buffer_lock : 1; 4287 } bits; 4288 4289 /** 4290 * Union for HW Lock flags. 4291 */ 4292 uint8_t u8All; 4293 }; 4294 4295 /** 4296 * Instances of HW to be locked. 4297 * 4298 * Note: If updating with more HW components, fields 4299 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4300 */ 4301 struct dmub_hw_lock_inst_flags { 4302 /** 4303 * OTG HW instance for OTG master update lock. 4304 */ 4305 uint8_t otg_inst; 4306 /** 4307 * OPP instance for cursor lock. 4308 */ 4309 uint8_t opp_inst; 4310 /** 4311 * OTG HW instance for global update lock. 4312 * TODO: Remove, and re-use otg_inst. 4313 */ 4314 uint8_t dig_inst; 4315 /** 4316 * Explicit pad to 4 byte boundary. 4317 */ 4318 uint8_t pad; 4319 }; 4320 4321 /** 4322 * Clients that can acquire the HW Lock Manager. 4323 * 4324 * Note: If updating with more clients, fields in 4325 * dmub_inbox0_cmd_lock_hw must be updated to match. 4326 */ 4327 enum hw_lock_client { 4328 /** 4329 * Driver is the client of HW Lock Manager. 4330 */ 4331 HW_LOCK_CLIENT_DRIVER = 0, 4332 /** 4333 * PSR SU is the client of HW Lock Manager. 4334 */ 4335 HW_LOCK_CLIENT_PSR_SU = 1, 4336 HW_LOCK_CLIENT_SUBVP = 3, 4337 /** 4338 * Replay is the client of HW Lock Manager. 4339 */ 4340 HW_LOCK_CLIENT_REPLAY = 4, 4341 HW_LOCK_CLIENT_FAMS2 = 5, 4342 /** 4343 * Invalid client. 4344 */ 4345 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4346 }; 4347 4348 /** 4349 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4350 */ 4351 struct dmub_cmd_lock_hw_data { 4352 /** 4353 * Specifies the client accessing HW Lock Manager. 4354 */ 4355 enum hw_lock_client client; 4356 /** 4357 * HW instances to be locked. 4358 */ 4359 struct dmub_hw_lock_inst_flags inst_flags; 4360 /** 4361 * Which components to be locked. 4362 */ 4363 union dmub_hw_lock_flags hw_locks; 4364 /** 4365 * Specifies lock/unlock. 4366 */ 4367 uint8_t lock; 4368 /** 4369 * HW can be unlocked separately from releasing the HW Lock Mgr. 4370 * This flag is set if the client wishes to release the object. 4371 */ 4372 uint8_t should_release; 4373 /** 4374 * Explicit padding to 4 byte boundary. 4375 */ 4376 uint8_t pad; 4377 }; 4378 4379 /** 4380 * Definition of a DMUB_CMD__HW_LOCK command. 4381 * Command is used by driver and FW. 4382 */ 4383 struct dmub_rb_cmd_lock_hw { 4384 /** 4385 * Command header. 4386 */ 4387 struct dmub_cmd_header header; 4388 /** 4389 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4390 */ 4391 struct dmub_cmd_lock_hw_data lock_hw_data; 4392 }; 4393 4394 /** 4395 * ABM command sub-types. 4396 */ 4397 enum dmub_cmd_abm_type { 4398 /** 4399 * Initialize parameters for ABM algorithm. 4400 * Data is passed through an indirect buffer. 4401 */ 4402 DMUB_CMD__ABM_INIT_CONFIG = 0, 4403 /** 4404 * Set OTG and panel HW instance. 4405 */ 4406 DMUB_CMD__ABM_SET_PIPE = 1, 4407 /** 4408 * Set user requested backklight level. 4409 */ 4410 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4411 /** 4412 * Set ABM operating/aggression level. 4413 */ 4414 DMUB_CMD__ABM_SET_LEVEL = 3, 4415 /** 4416 * Set ambient light level. 4417 */ 4418 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4419 /** 4420 * Enable/disable fractional duty cycle for backlight PWM. 4421 */ 4422 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4423 4424 /** 4425 * unregister vertical interrupt after steady state is reached 4426 */ 4427 DMUB_CMD__ABM_PAUSE = 6, 4428 4429 /** 4430 * Save and Restore ABM state. On save we save parameters, and 4431 * on restore we update state with passed in data. 4432 */ 4433 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4434 4435 /** 4436 * Query ABM caps. 4437 */ 4438 DMUB_CMD__ABM_QUERY_CAPS = 8, 4439 4440 /** 4441 * Set ABM Events 4442 */ 4443 DMUB_CMD__ABM_SET_EVENT = 9, 4444 4445 /** 4446 * Get the current ACE curve. 4447 */ 4448 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4449 4450 /** 4451 * Get current histogram data 4452 */ 4453 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4454 }; 4455 4456 struct abm_ace_curve { 4457 /** 4458 * @offsets: ACE curve offsets. 4459 */ 4460 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4461 4462 /** 4463 * @thresholds: ACE curve thresholds. 4464 */ 4465 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4466 4467 /** 4468 * @slopes: ACE curve slopes. 4469 */ 4470 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4471 }; 4472 4473 struct fixed_pt_format { 4474 /** 4475 * @sign_bit: Indicates whether one bit is reserved for the sign. 4476 */ 4477 bool sign_bit; 4478 4479 /** 4480 * @num_int_bits: Number of bits used for integer part. 4481 */ 4482 uint8_t num_int_bits; 4483 4484 /** 4485 * @num_frac_bits: Number of bits used for fractional part. 4486 */ 4487 uint8_t num_frac_bits; 4488 4489 /** 4490 * @pad: Explicit padding to 4 byte boundary. 4491 */ 4492 uint8_t pad; 4493 }; 4494 4495 struct abm_caps { 4496 /** 4497 * @num_hg_bins: Number of histogram bins. 4498 */ 4499 uint8_t num_hg_bins; 4500 4501 /** 4502 * @num_ace_segments: Number of ACE curve segments. 4503 */ 4504 uint8_t num_ace_segments; 4505 4506 /** 4507 * @pad: Explicit padding to 4 byte boundary. 4508 */ 4509 uint8_t pad[2]; 4510 4511 /** 4512 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4513 */ 4514 struct fixed_pt_format ace_thresholds_format; 4515 4516 /** 4517 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4518 */ 4519 struct fixed_pt_format ace_offsets_format; 4520 4521 /** 4522 * @ace_slopes_format: Format of the ACE slopes. 4523 */ 4524 struct fixed_pt_format ace_slopes_format; 4525 }; 4526 4527 /** 4528 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4529 * Requirements: 4530 * - Padded explicitly to 32-bit boundary. 4531 * - Must ensure this structure matches the one on driver-side, 4532 * otherwise it won't be aligned. 4533 */ 4534 struct abm_config_table { 4535 /** 4536 * Gamma curve thresholds, used for crgb conversion. 4537 */ 4538 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4539 /** 4540 * Gamma curve offsets, used for crgb conversion. 4541 */ 4542 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4543 /** 4544 * Gamma curve slopes, used for crgb conversion. 4545 */ 4546 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4547 /** 4548 * Custom backlight curve thresholds. 4549 */ 4550 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4551 /** 4552 * Custom backlight curve offsets. 4553 */ 4554 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4555 /** 4556 * Ambient light thresholds. 4557 */ 4558 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4559 /** 4560 * Minimum programmable backlight. 4561 */ 4562 uint16_t min_abm_backlight; // 122B 4563 /** 4564 * Minimum reduction values. 4565 */ 4566 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4567 /** 4568 * Maximum reduction values. 4569 */ 4570 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4571 /** 4572 * Bright positive gain. 4573 */ 4574 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4575 /** 4576 * Dark negative gain. 4577 */ 4578 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4579 /** 4580 * Hybrid factor. 4581 */ 4582 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4583 /** 4584 * Contrast factor. 4585 */ 4586 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4587 /** 4588 * Deviation gain. 4589 */ 4590 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4591 /** 4592 * Minimum knee. 4593 */ 4594 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4595 /** 4596 * Maximum knee. 4597 */ 4598 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4599 /** 4600 * Unused. 4601 */ 4602 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4603 /** 4604 * Explicit padding to 4 byte boundary. 4605 */ 4606 uint8_t pad3[3]; // 229B 4607 /** 4608 * Backlight ramp reduction. 4609 */ 4610 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4611 /** 4612 * Backlight ramp start. 4613 */ 4614 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4615 }; 4616 4617 /** 4618 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4619 */ 4620 struct dmub_cmd_abm_set_pipe_data { 4621 /** 4622 * OTG HW instance. 4623 */ 4624 uint8_t otg_inst; 4625 4626 /** 4627 * Panel Control HW instance. 4628 */ 4629 uint8_t panel_inst; 4630 4631 /** 4632 * Controls how ABM will interpret a set pipe or set level command. 4633 */ 4634 uint8_t set_pipe_option; 4635 4636 /** 4637 * Unused. 4638 * TODO: Remove. 4639 */ 4640 uint8_t ramping_boundary; 4641 4642 /** 4643 * PwrSeq HW Instance. 4644 */ 4645 uint8_t pwrseq_inst; 4646 4647 /** 4648 * Explicit padding to 4 byte boundary. 4649 */ 4650 uint8_t pad[3]; 4651 }; 4652 4653 /** 4654 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4655 */ 4656 struct dmub_rb_cmd_abm_set_pipe { 4657 /** 4658 * Command header. 4659 */ 4660 struct dmub_cmd_header header; 4661 4662 /** 4663 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4664 */ 4665 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4666 }; 4667 4668 /** 4669 * Type of backlight control method to be used by ABM module 4670 */ 4671 enum dmub_backlight_control_type { 4672 /** 4673 * PWM Backlight control 4674 */ 4675 DMU_BACKLIGHT_CONTROL_PWM = 0, 4676 /** 4677 * VESA Aux-based backlight control 4678 */ 4679 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4680 /** 4681 * AMD DPCD Aux-based backlight control 4682 */ 4683 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4684 }; 4685 4686 /** 4687 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4688 */ 4689 struct dmub_cmd_abm_set_backlight_data { 4690 /** 4691 * Number of frames to ramp to backlight user level. 4692 */ 4693 uint32_t frame_ramp; 4694 4695 /** 4696 * Requested backlight level from user. 4697 */ 4698 uint32_t backlight_user_level; 4699 4700 /** 4701 * ABM control version. 4702 */ 4703 uint8_t version; 4704 4705 /** 4706 * Panel Control HW instance mask. 4707 * Bit 0 is Panel Control HW instance 0. 4708 * Bit 1 is Panel Control HW instance 1. 4709 */ 4710 uint8_t panel_mask; 4711 4712 /** 4713 * AUX HW Instance. 4714 */ 4715 uint8_t aux_inst; 4716 4717 /** 4718 * Explicit padding to 4 byte boundary. 4719 */ 4720 uint8_t pad[1]; 4721 4722 /** 4723 * Backlight control type. 4724 * Value 0 is PWM backlight control. 4725 * Value 1 is VAUX backlight control. 4726 * Value 2 is AMD DPCD AUX backlight control. 4727 */ 4728 enum dmub_backlight_control_type backlight_control_type; 4729 4730 /** 4731 * Minimum luminance in nits. 4732 */ 4733 uint32_t min_luminance; 4734 4735 /** 4736 * Maximum luminance in nits. 4737 */ 4738 uint32_t max_luminance; 4739 4740 /** 4741 * Minimum backlight in pwm. 4742 */ 4743 uint32_t min_backlight_pwm; 4744 4745 /** 4746 * Maximum backlight in pwm. 4747 */ 4748 uint32_t max_backlight_pwm; 4749 }; 4750 4751 /** 4752 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4753 */ 4754 struct dmub_rb_cmd_abm_set_backlight { 4755 /** 4756 * Command header. 4757 */ 4758 struct dmub_cmd_header header; 4759 4760 /** 4761 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4762 */ 4763 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4764 }; 4765 4766 /** 4767 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4768 */ 4769 struct dmub_cmd_abm_set_level_data { 4770 /** 4771 * Set current ABM operating/aggression level. 4772 */ 4773 uint32_t level; 4774 4775 /** 4776 * ABM control version. 4777 */ 4778 uint8_t version; 4779 4780 /** 4781 * Panel Control HW instance mask. 4782 * Bit 0 is Panel Control HW instance 0. 4783 * Bit 1 is Panel Control HW instance 1. 4784 */ 4785 uint8_t panel_mask; 4786 4787 /** 4788 * Explicit padding to 4 byte boundary. 4789 */ 4790 uint8_t pad[2]; 4791 }; 4792 4793 /** 4794 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4795 */ 4796 struct dmub_rb_cmd_abm_set_level { 4797 /** 4798 * Command header. 4799 */ 4800 struct dmub_cmd_header header; 4801 4802 /** 4803 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4804 */ 4805 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4806 }; 4807 4808 /** 4809 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4810 */ 4811 struct dmub_cmd_abm_set_ambient_level_data { 4812 /** 4813 * Ambient light sensor reading from OS. 4814 */ 4815 uint32_t ambient_lux; 4816 4817 /** 4818 * ABM control version. 4819 */ 4820 uint8_t version; 4821 4822 /** 4823 * Panel Control HW instance mask. 4824 * Bit 0 is Panel Control HW instance 0. 4825 * Bit 1 is Panel Control HW instance 1. 4826 */ 4827 uint8_t panel_mask; 4828 4829 /** 4830 * Explicit padding to 4 byte boundary. 4831 */ 4832 uint8_t pad[2]; 4833 }; 4834 4835 /** 4836 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4837 */ 4838 struct dmub_rb_cmd_abm_set_ambient_level { 4839 /** 4840 * Command header. 4841 */ 4842 struct dmub_cmd_header header; 4843 4844 /** 4845 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4846 */ 4847 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4848 }; 4849 4850 /** 4851 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4852 */ 4853 struct dmub_cmd_abm_set_pwm_frac_data { 4854 /** 4855 * Enable/disable fractional duty cycle for backlight PWM. 4856 * TODO: Convert to uint8_t. 4857 */ 4858 uint32_t fractional_pwm; 4859 4860 /** 4861 * ABM control version. 4862 */ 4863 uint8_t version; 4864 4865 /** 4866 * Panel Control HW instance mask. 4867 * Bit 0 is Panel Control HW instance 0. 4868 * Bit 1 is Panel Control HW instance 1. 4869 */ 4870 uint8_t panel_mask; 4871 4872 /** 4873 * Explicit padding to 4 byte boundary. 4874 */ 4875 uint8_t pad[2]; 4876 }; 4877 4878 /** 4879 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4880 */ 4881 struct dmub_rb_cmd_abm_set_pwm_frac { 4882 /** 4883 * Command header. 4884 */ 4885 struct dmub_cmd_header header; 4886 4887 /** 4888 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4889 */ 4890 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4891 }; 4892 4893 /** 4894 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4895 */ 4896 struct dmub_cmd_abm_init_config_data { 4897 /** 4898 * Location of indirect buffer used to pass init data to ABM. 4899 */ 4900 union dmub_addr src; 4901 4902 /** 4903 * Indirect buffer length. 4904 */ 4905 uint16_t bytes; 4906 4907 4908 /** 4909 * ABM control version. 4910 */ 4911 uint8_t version; 4912 4913 /** 4914 * Panel Control HW instance mask. 4915 * Bit 0 is Panel Control HW instance 0. 4916 * Bit 1 is Panel Control HW instance 1. 4917 */ 4918 uint8_t panel_mask; 4919 4920 /** 4921 * Explicit padding to 4 byte boundary. 4922 */ 4923 uint8_t pad[2]; 4924 }; 4925 4926 /** 4927 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4928 */ 4929 struct dmub_rb_cmd_abm_init_config { 4930 /** 4931 * Command header. 4932 */ 4933 struct dmub_cmd_header header; 4934 4935 /** 4936 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4937 */ 4938 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4939 }; 4940 4941 /** 4942 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4943 */ 4944 4945 struct dmub_cmd_abm_pause_data { 4946 4947 /** 4948 * Panel Control HW instance mask. 4949 * Bit 0 is Panel Control HW instance 0. 4950 * Bit 1 is Panel Control HW instance 1. 4951 */ 4952 uint8_t panel_mask; 4953 4954 /** 4955 * OTG hw instance 4956 */ 4957 uint8_t otg_inst; 4958 4959 /** 4960 * Enable or disable ABM pause 4961 */ 4962 uint8_t enable; 4963 4964 /** 4965 * Explicit padding to 4 byte boundary. 4966 */ 4967 uint8_t pad[1]; 4968 }; 4969 4970 /** 4971 * Definition of a DMUB_CMD__ABM_PAUSE command. 4972 */ 4973 struct dmub_rb_cmd_abm_pause { 4974 /** 4975 * Command header. 4976 */ 4977 struct dmub_cmd_header header; 4978 4979 /** 4980 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4981 */ 4982 struct dmub_cmd_abm_pause_data abm_pause_data; 4983 }; 4984 4985 /** 4986 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4987 */ 4988 struct dmub_cmd_abm_query_caps_in { 4989 /** 4990 * Panel instance. 4991 */ 4992 uint8_t panel_inst; 4993 4994 /** 4995 * Explicit padding to 4 byte boundary. 4996 */ 4997 uint8_t pad[3]; 4998 }; 4999 5000 /** 5001 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5002 */ 5003 struct dmub_cmd_abm_query_caps_out { 5004 /** 5005 * SW Algorithm caps. 5006 */ 5007 struct abm_caps sw_caps; 5008 5009 /** 5010 * ABM HW caps. 5011 */ 5012 struct abm_caps hw_caps; 5013 }; 5014 5015 /** 5016 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5017 */ 5018 struct dmub_rb_cmd_abm_query_caps { 5019 /** 5020 * Command header. 5021 */ 5022 struct dmub_cmd_header header; 5023 5024 /** 5025 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5026 */ 5027 union { 5028 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5029 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5030 } data; 5031 }; 5032 5033 /** 5034 * enum dmub_abm_ace_curve_type - ACE curve type. 5035 */ 5036 enum dmub_abm_ace_curve_type { 5037 /** 5038 * ACE curve as defined by the SW layer. 5039 */ 5040 ABM_ACE_CURVE_TYPE__SW = 0, 5041 /** 5042 * ACE curve as defined by the SW to HW translation interface layer. 5043 */ 5044 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5045 }; 5046 5047 /** 5048 * enum dmub_abm_histogram_type - Histogram type. 5049 */ 5050 enum dmub_abm_histogram_type { 5051 /** 5052 * ACE curve as defined by the SW layer. 5053 */ 5054 ABM_HISTOGRAM_TYPE__SW = 0, 5055 /** 5056 * ACE curve as defined by the SW to HW translation interface layer. 5057 */ 5058 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5059 }; 5060 5061 /** 5062 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5063 */ 5064 struct dmub_rb_cmd_abm_get_ace_curve { 5065 /** 5066 * Command header. 5067 */ 5068 struct dmub_cmd_header header; 5069 5070 /** 5071 * Address where ACE curve should be copied. 5072 */ 5073 union dmub_addr dest; 5074 5075 /** 5076 * Type of ACE curve being queried. 5077 */ 5078 enum dmub_abm_ace_curve_type ace_type; 5079 5080 /** 5081 * Indirect buffer length. 5082 */ 5083 uint16_t bytes; 5084 5085 /** 5086 * eDP panel instance. 5087 */ 5088 uint8_t panel_inst; 5089 5090 /** 5091 * Explicit padding to 4 byte boundary. 5092 */ 5093 uint8_t pad; 5094 }; 5095 5096 /** 5097 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5098 */ 5099 struct dmub_rb_cmd_abm_get_histogram { 5100 /** 5101 * Command header. 5102 */ 5103 struct dmub_cmd_header header; 5104 5105 /** 5106 * Address where Histogram should be copied. 5107 */ 5108 union dmub_addr dest; 5109 5110 /** 5111 * Type of Histogram being queried. 5112 */ 5113 enum dmub_abm_histogram_type histogram_type; 5114 5115 /** 5116 * Indirect buffer length. 5117 */ 5118 uint16_t bytes; 5119 5120 /** 5121 * eDP panel instance. 5122 */ 5123 uint8_t panel_inst; 5124 5125 /** 5126 * Explicit padding to 4 byte boundary. 5127 */ 5128 uint8_t pad; 5129 }; 5130 5131 /** 5132 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5133 */ 5134 struct dmub_rb_cmd_abm_save_restore { 5135 /** 5136 * Command header. 5137 */ 5138 struct dmub_cmd_header header; 5139 5140 /** 5141 * OTG hw instance 5142 */ 5143 uint8_t otg_inst; 5144 5145 /** 5146 * Enable or disable ABM pause 5147 */ 5148 uint8_t freeze; 5149 5150 /** 5151 * Explicit padding to 4 byte boundary. 5152 */ 5153 uint8_t debug; 5154 5155 /** 5156 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5157 */ 5158 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5159 }; 5160 5161 /** 5162 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5163 */ 5164 5165 struct dmub_cmd_abm_set_event_data { 5166 5167 /** 5168 * VB Scaling Init. Strength Mapping 5169 * Byte 0: 0~255 for VB level 0 5170 * Byte 1: 0~255 for VB level 1 5171 * Byte 2: 0~255 for VB level 2 5172 * Byte 3: 0~255 for VB level 3 5173 */ 5174 uint32_t vb_scaling_strength_mapping; 5175 /** 5176 * VariBright Scaling Enable 5177 */ 5178 uint8_t vb_scaling_enable; 5179 /** 5180 * Panel Control HW instance mask. 5181 * Bit 0 is Panel Control HW instance 0. 5182 * Bit 1 is Panel Control HW instance 1. 5183 */ 5184 uint8_t panel_mask; 5185 5186 /** 5187 * Explicit padding to 4 byte boundary. 5188 */ 5189 uint8_t pad[2]; 5190 }; 5191 5192 /** 5193 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5194 */ 5195 struct dmub_rb_cmd_abm_set_event { 5196 /** 5197 * Command header. 5198 */ 5199 struct dmub_cmd_header header; 5200 5201 /** 5202 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5203 */ 5204 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5205 }; 5206 5207 /** 5208 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5209 */ 5210 struct dmub_cmd_query_feature_caps_data { 5211 /** 5212 * DMUB feature capabilities. 5213 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5214 */ 5215 struct dmub_feature_caps feature_caps; 5216 }; 5217 5218 /** 5219 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5220 */ 5221 struct dmub_rb_cmd_query_feature_caps { 5222 /** 5223 * Command header. 5224 */ 5225 struct dmub_cmd_header header; 5226 /** 5227 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5228 */ 5229 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5230 }; 5231 5232 /** 5233 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5234 */ 5235 struct dmub_cmd_visual_confirm_color_data { 5236 /** 5237 * DMUB visual confirm color 5238 */ 5239 struct dmub_visual_confirm_color visual_confirm_color; 5240 }; 5241 5242 /** 5243 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5244 */ 5245 struct dmub_rb_cmd_get_visual_confirm_color { 5246 /** 5247 * Command header. 5248 */ 5249 struct dmub_cmd_header header; 5250 /** 5251 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5252 */ 5253 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5254 }; 5255 5256 /** 5257 * enum dmub_cmd_panel_cntl_type - Panel control command. 5258 */ 5259 enum dmub_cmd_panel_cntl_type { 5260 /** 5261 * Initializes embedded panel hardware blocks. 5262 */ 5263 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5264 /** 5265 * Queries backlight info for the embedded panel. 5266 */ 5267 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5268 /** 5269 * Sets the PWM Freq as per user's requirement. 5270 */ 5271 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5272 }; 5273 5274 /** 5275 * struct dmub_cmd_panel_cntl_data - Panel control data. 5276 */ 5277 struct dmub_cmd_panel_cntl_data { 5278 uint32_t pwrseq_inst; /**< pwrseq instance */ 5279 uint32_t current_backlight; /* in/out */ 5280 uint32_t bl_pwm_cntl; /* in/out */ 5281 uint32_t bl_pwm_period_cntl; /* in/out */ 5282 uint32_t bl_pwm_ref_div1; /* in/out */ 5283 uint8_t is_backlight_on : 1; /* in/out */ 5284 uint8_t is_powered_on : 1; /* in/out */ 5285 uint8_t padding[3]; 5286 uint32_t bl_pwm_ref_div2; /* in/out */ 5287 uint8_t reserved[4]; 5288 }; 5289 5290 /** 5291 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5292 */ 5293 struct dmub_rb_cmd_panel_cntl { 5294 struct dmub_cmd_header header; /**< header */ 5295 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5296 }; 5297 5298 struct dmub_optc_state { 5299 uint32_t v_total_max; 5300 uint32_t v_total_min; 5301 uint32_t tg_inst; 5302 }; 5303 5304 struct dmub_rb_cmd_drr_update { 5305 struct dmub_cmd_header header; 5306 struct dmub_optc_state dmub_optc_state_req; 5307 }; 5308 5309 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5310 uint32_t pix_clk_100hz; 5311 uint8_t max_ramp_step; 5312 uint8_t pipes; 5313 uint8_t min_refresh_in_hz; 5314 uint8_t pipe_count; 5315 uint8_t pipe_index[4]; 5316 }; 5317 5318 struct dmub_cmd_fw_assisted_mclk_switch_config { 5319 uint8_t fams_enabled; 5320 uint8_t visual_confirm_enabled; 5321 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5322 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5323 }; 5324 5325 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5326 struct dmub_cmd_header header; 5327 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5328 }; 5329 5330 /** 5331 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5332 */ 5333 struct dmub_cmd_lvtma_control_data { 5334 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5335 uint8_t bypass_panel_control_wait; 5336 uint8_t reserved_0[2]; /**< For future use */ 5337 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5338 uint8_t reserved_1[3]; /**< For future use */ 5339 }; 5340 5341 /** 5342 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5343 */ 5344 struct dmub_rb_cmd_lvtma_control { 5345 /** 5346 * Command header. 5347 */ 5348 struct dmub_cmd_header header; 5349 /** 5350 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5351 */ 5352 struct dmub_cmd_lvtma_control_data data; 5353 }; 5354 5355 /** 5356 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5357 */ 5358 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5359 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5360 uint8_t is_usb; /**< is phy is usb */ 5361 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5362 uint8_t is_dp4; /**< is dp in 4 lane */ 5363 }; 5364 5365 /** 5366 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5367 */ 5368 struct dmub_rb_cmd_transmitter_query_dp_alt { 5369 struct dmub_cmd_header header; /**< header */ 5370 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5371 }; 5372 5373 struct phy_test_mode { 5374 uint8_t mode; 5375 uint8_t pat0; 5376 uint8_t pad[2]; 5377 }; 5378 5379 /** 5380 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5381 */ 5382 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5383 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5384 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5385 uint8_t lane_num; /**< Number of lanes */ 5386 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5387 struct phy_test_mode test_mode; 5388 enum dmub_phy_fsm_state state; 5389 uint32_t status; 5390 uint8_t pad; 5391 }; 5392 5393 /** 5394 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5395 */ 5396 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5397 struct dmub_cmd_header header; /**< header */ 5398 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5399 }; 5400 5401 /** 5402 * Maximum number of bytes a chunk sent to DMUB for parsing 5403 */ 5404 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5405 5406 /** 5407 * Represent a chunk of CEA blocks sent to DMUB for parsing 5408 */ 5409 struct dmub_cmd_send_edid_cea { 5410 uint16_t offset; /**< offset into the CEA block */ 5411 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5412 uint16_t cea_total_length; /**< total length of the CEA block */ 5413 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5414 uint8_t pad[3]; /**< padding and for future expansion */ 5415 }; 5416 5417 /** 5418 * Result of VSDB parsing from CEA block 5419 */ 5420 struct dmub_cmd_edid_cea_amd_vsdb { 5421 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5422 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5423 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5424 uint16_t min_frame_rate; /**< Maximum frame rate */ 5425 uint16_t max_frame_rate; /**< Minimum frame rate */ 5426 }; 5427 5428 /** 5429 * Result of sending a CEA chunk 5430 */ 5431 struct dmub_cmd_edid_cea_ack { 5432 uint16_t offset; /**< offset of the chunk into the CEA block */ 5433 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5434 uint8_t pad; /**< padding and for future expansion */ 5435 }; 5436 5437 /** 5438 * Specify whether the result is an ACK/NACK or the parsing has finished 5439 */ 5440 enum dmub_cmd_edid_cea_reply_type { 5441 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5442 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5443 }; 5444 5445 /** 5446 * Definition of a DMUB_CMD__EDID_CEA command. 5447 */ 5448 struct dmub_rb_cmd_edid_cea { 5449 struct dmub_cmd_header header; /**< Command header */ 5450 union dmub_cmd_edid_cea_data { 5451 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5452 struct dmub_cmd_edid_cea_output { /**< output with results */ 5453 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5454 union { 5455 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5456 struct dmub_cmd_edid_cea_ack ack; 5457 }; 5458 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5459 } data; /**< Command data */ 5460 5461 }; 5462 5463 /** 5464 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5465 */ 5466 struct dmub_cmd_cable_id_input { 5467 uint8_t phy_inst; /**< phy inst for cable id data */ 5468 }; 5469 5470 /** 5471 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5472 */ 5473 struct dmub_cmd_cable_id_output { 5474 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5475 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5476 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5477 uint8_t RESERVED :2; /**< reserved means not defined */ 5478 }; 5479 5480 /** 5481 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5482 */ 5483 struct dmub_rb_cmd_get_usbc_cable_id { 5484 struct dmub_cmd_header header; /**< Command header */ 5485 /** 5486 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5487 */ 5488 union dmub_cmd_cable_id_data { 5489 struct dmub_cmd_cable_id_input input; /**< Input */ 5490 struct dmub_cmd_cable_id_output output; /**< Output */ 5491 uint8_t output_raw; /**< Raw data output */ 5492 } data; 5493 }; 5494 5495 enum dmub_cmd_fused_io_sub_type { 5496 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5497 DMUB_CMD__FUSED_IO_ABORT = 1, 5498 }; 5499 5500 enum dmub_cmd_fused_request_type { 5501 FUSED_REQUEST_READ, 5502 FUSED_REQUEST_WRITE, 5503 FUSED_REQUEST_POLL, 5504 }; 5505 5506 enum dmub_cmd_fused_request_status { 5507 FUSED_REQUEST_STATUS_SUCCESS, 5508 FUSED_REQUEST_STATUS_BEGIN, 5509 FUSED_REQUEST_STATUS_SUBMIT, 5510 FUSED_REQUEST_STATUS_REPLY, 5511 FUSED_REQUEST_STATUS_POLL, 5512 FUSED_REQUEST_STATUS_ABORTED, 5513 FUSED_REQUEST_STATUS_FAILED = 0x80, 5514 FUSED_REQUEST_STATUS_INVALID, 5515 FUSED_REQUEST_STATUS_BUSY, 5516 FUSED_REQUEST_STATUS_TIMEOUT, 5517 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5518 }; 5519 5520 struct dmub_cmd_fused_request { 5521 uint8_t status; 5522 uint8_t type : 2; 5523 uint8_t _reserved0 : 3; 5524 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5525 uint8_t identifier; 5526 uint8_t _reserved1; 5527 uint32_t timeout_us; 5528 union dmub_cmd_fused_request_location { 5529 struct dmub_cmd_fused_request_location_i2c { 5530 uint8_t is_aux : 1; // False 5531 uint8_t ddc_line : 3; 5532 uint8_t over_aux : 1; 5533 uint8_t _reserved0 : 3; 5534 uint8_t address; 5535 uint8_t offset; 5536 uint8_t length; 5537 } i2c; 5538 struct dmub_cmd_fused_request_location_aux { 5539 uint32_t is_aux : 1; // True 5540 uint32_t ddc_line : 3; 5541 uint32_t address : 20; 5542 uint32_t length : 8; // Automatically split into 16B transactions 5543 } aux; 5544 } u; 5545 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5546 }; 5547 5548 struct dmub_rb_cmd_fused_io { 5549 struct dmub_cmd_header header; 5550 struct dmub_cmd_fused_request request; 5551 }; 5552 5553 /** 5554 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5555 */ 5556 enum dmub_cmd_secure_display_type { 5557 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5558 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5559 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5560 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5561 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5562 }; 5563 5564 #define MAX_ROI_NUM 2 5565 5566 struct dmub_cmd_roi_info { 5567 uint16_t x_start; 5568 uint16_t x_end; 5569 uint16_t y_start; 5570 uint16_t y_end; 5571 uint8_t otg_id; 5572 uint8_t phy_id; 5573 }; 5574 5575 struct dmub_cmd_roi_window_ctl { 5576 uint16_t x_start; 5577 uint16_t x_end; 5578 uint16_t y_start; 5579 uint16_t y_end; 5580 bool enable; 5581 }; 5582 5583 struct dmub_cmd_roi_ctl_info { 5584 uint8_t otg_id; 5585 uint8_t phy_id; 5586 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5587 }; 5588 5589 /** 5590 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5591 */ 5592 struct dmub_rb_cmd_secure_display { 5593 struct dmub_cmd_header header; 5594 /** 5595 * Data passed from driver to dmub firmware. 5596 */ 5597 struct dmub_cmd_roi_info roi_info; 5598 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5599 }; 5600 5601 /** 5602 * Command type of a DMUB_CMD__PSP command 5603 */ 5604 enum dmub_cmd_psp_type { 5605 DMUB_CMD__PSP_ASSR_ENABLE = 0 5606 }; 5607 5608 /** 5609 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5610 */ 5611 struct dmub_cmd_assr_enable_data { 5612 /** 5613 * ASSR enable or disable. 5614 */ 5615 uint8_t enable; 5616 /** 5617 * PHY port type. 5618 * Indicates eDP / non-eDP port type 5619 */ 5620 uint8_t phy_port_type; 5621 /** 5622 * PHY port ID. 5623 */ 5624 uint8_t phy_port_id; 5625 /** 5626 * Link encoder index. 5627 */ 5628 uint8_t link_enc_index; 5629 /** 5630 * HPO mode. 5631 */ 5632 uint8_t hpo_mode; 5633 5634 /** 5635 * Reserved field. 5636 */ 5637 uint8_t reserved[7]; 5638 }; 5639 5640 /** 5641 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5642 */ 5643 struct dmub_rb_cmd_assr_enable { 5644 /** 5645 * Command header. 5646 */ 5647 struct dmub_cmd_header header; 5648 5649 /** 5650 * Assr data. 5651 */ 5652 struct dmub_cmd_assr_enable_data assr_data; 5653 5654 /** 5655 * Reserved field. 5656 */ 5657 uint32_t reserved[3]; 5658 }; 5659 5660 /** 5661 * union dmub_rb_cmd - DMUB inbox command. 5662 */ 5663 union dmub_rb_cmd { 5664 /** 5665 * Elements shared with all commands. 5666 */ 5667 struct dmub_rb_cmd_common cmd_common; 5668 /** 5669 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5670 */ 5671 struct dmub_rb_cmd_read_modify_write read_modify_write; 5672 /** 5673 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5674 */ 5675 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5676 /** 5677 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5678 */ 5679 struct dmub_rb_cmd_burst_write burst_write; 5680 /** 5681 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5682 */ 5683 struct dmub_rb_cmd_reg_wait reg_wait; 5684 /** 5685 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5686 */ 5687 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5688 /** 5689 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5690 */ 5691 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5692 /** 5693 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5694 */ 5695 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5696 /** 5697 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5698 */ 5699 struct dmub_rb_cmd_dpphy_init dpphy_init; 5700 /** 5701 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5702 */ 5703 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5704 /** 5705 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5706 */ 5707 struct dmub_rb_cmd_domain_control domain_control; 5708 /** 5709 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5710 */ 5711 struct dmub_rb_cmd_psr_set_version psr_set_version; 5712 /** 5713 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5714 */ 5715 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5716 /** 5717 * Definition of a DMUB_CMD__PSR_ENABLE command. 5718 */ 5719 struct dmub_rb_cmd_psr_enable psr_enable; 5720 /** 5721 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5722 */ 5723 struct dmub_rb_cmd_psr_set_level psr_set_level; 5724 /** 5725 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5726 */ 5727 struct dmub_rb_cmd_psr_force_static psr_force_static; 5728 /** 5729 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5730 */ 5731 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5732 /** 5733 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5734 */ 5735 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5736 /** 5737 * Definition of a DMUB_CMD__HW_LOCK command. 5738 * Command is used by driver and FW. 5739 */ 5740 struct dmub_rb_cmd_lock_hw lock_hw; 5741 /** 5742 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5743 */ 5744 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5745 /** 5746 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5747 */ 5748 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5749 /** 5750 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5751 */ 5752 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5753 /** 5754 * Definition of a DMUB_CMD__MALL command. 5755 */ 5756 struct dmub_rb_cmd_mall mall; 5757 5758 /** 5759 * Definition of a DMUB_CMD__CAB command. 5760 */ 5761 struct dmub_rb_cmd_cab_for_ss cab; 5762 5763 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5764 5765 /** 5766 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5767 */ 5768 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5769 5770 /** 5771 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5772 */ 5773 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5774 5775 /** 5776 * Definition of DMUB_CMD__PANEL_CNTL commands. 5777 */ 5778 struct dmub_rb_cmd_panel_cntl panel_cntl; 5779 5780 /** 5781 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5782 */ 5783 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5784 5785 /** 5786 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5787 */ 5788 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5789 5790 /** 5791 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5792 */ 5793 struct dmub_rb_cmd_abm_set_level abm_set_level; 5794 5795 /** 5796 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5797 */ 5798 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5799 5800 /** 5801 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5802 */ 5803 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5804 5805 /** 5806 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5807 */ 5808 struct dmub_rb_cmd_abm_init_config abm_init_config; 5809 5810 /** 5811 * Definition of a DMUB_CMD__ABM_PAUSE command. 5812 */ 5813 struct dmub_rb_cmd_abm_pause abm_pause; 5814 5815 /** 5816 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5817 */ 5818 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5819 5820 /** 5821 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5822 */ 5823 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5824 5825 /** 5826 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5827 */ 5828 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5829 5830 /** 5831 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5832 */ 5833 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 5834 5835 /** 5836 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5837 */ 5838 struct dmub_rb_cmd_abm_set_event abm_set_event; 5839 5840 /** 5841 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5842 */ 5843 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5844 5845 /** 5846 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5847 */ 5848 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5849 5850 /** 5851 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5852 */ 5853 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5854 5855 /** 5856 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5857 */ 5858 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5859 struct dmub_rb_cmd_drr_update drr_update; 5860 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5861 5862 /** 5863 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5864 */ 5865 struct dmub_rb_cmd_lvtma_control lvtma_control; 5866 /** 5867 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5868 */ 5869 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5870 /** 5871 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5872 */ 5873 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5874 /** 5875 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5876 */ 5877 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5878 /** 5879 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5880 */ 5881 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 5882 /** 5883 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5884 */ 5885 struct dmub_rb_cmd_set_config_request set_config_request; 5886 /** 5887 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5888 */ 5889 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5890 /** 5891 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 5892 */ 5893 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 5894 /** 5895 * Definition of a DMUB_CMD__EDID_CEA command. 5896 */ 5897 struct dmub_rb_cmd_edid_cea edid_cea; 5898 /** 5899 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5900 */ 5901 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5902 5903 /** 5904 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5905 */ 5906 struct dmub_rb_cmd_query_hpd_state query_hpd; 5907 /** 5908 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5909 */ 5910 struct dmub_rb_cmd_secure_display secure_display; 5911 5912 /** 5913 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5914 */ 5915 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5916 /** 5917 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5918 */ 5919 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5920 /** 5921 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 5922 */ 5923 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 5924 /* 5925 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5926 */ 5927 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5928 /** 5929 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5930 */ 5931 struct dmub_rb_cmd_replay_enable replay_enable; 5932 /** 5933 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5934 */ 5935 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5936 /** 5937 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5938 */ 5939 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5940 /** 5941 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5942 */ 5943 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5944 5945 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5946 /** 5947 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5948 */ 5949 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5950 /** 5951 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5952 */ 5953 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5954 /** 5955 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5956 */ 5957 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5958 /** 5959 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5960 */ 5961 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5962 /** 5963 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5964 */ 5965 struct dmub_rb_cmd_assr_enable assr_enable; 5966 5967 struct dmub_rb_cmd_fams2 fams2_config; 5968 5969 struct dmub_rb_cmd_ib ib_fams2_config; 5970 5971 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5972 5973 struct dmub_rb_cmd_fams2_flip fams2_flip; 5974 5975 struct dmub_rb_cmd_fused_io fused_io; 5976 }; 5977 5978 /** 5979 * union dmub_rb_out_cmd - Outbox command 5980 */ 5981 union dmub_rb_out_cmd { 5982 /** 5983 * Parameters common to every command. 5984 */ 5985 struct dmub_rb_cmd_common cmd_common; 5986 /** 5987 * AUX reply command. 5988 */ 5989 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5990 /** 5991 * HPD notify command. 5992 */ 5993 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5994 /** 5995 * SET_CONFIG reply command. 5996 */ 5997 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5998 /** 5999 * DPIA notification command. 6000 */ 6001 struct dmub_rb_cmd_dpia_notification dpia_notification; 6002 /** 6003 * HPD sense notification command. 6004 */ 6005 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6006 struct dmub_rb_cmd_fused_io fused_io; 6007 }; 6008 #pragma pack(pop) 6009 6010 6011 //============================================================================== 6012 //</DMUB_CMD>=================================================================== 6013 //============================================================================== 6014 //< DMUB_RB>==================================================================== 6015 //============================================================================== 6016 6017 /** 6018 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6019 */ 6020 struct dmub_rb_init_params { 6021 void *ctx; /**< Caller provided context pointer */ 6022 void *base_address; /**< CPU base address for ring's data */ 6023 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6024 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6025 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6026 }; 6027 6028 /** 6029 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6030 */ 6031 struct dmub_rb { 6032 void *base_address; /**< CPU address for the ring's data */ 6033 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6034 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6035 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6036 6037 void *ctx; /**< Caller provided context pointer */ 6038 void *dmub; /**< Pointer to the DMUB interface */ 6039 }; 6040 6041 /** 6042 * @brief Checks if the ringbuffer is empty. 6043 * 6044 * @param rb DMUB Ringbuffer 6045 * @return true if empty 6046 * @return false otherwise 6047 */ 6048 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6049 { 6050 return (rb->wrpt == rb->rptr); 6051 } 6052 6053 /** 6054 * @brief gets number of outstanding requests in the RB 6055 * 6056 * @param rb DMUB Ringbuffer 6057 * @return true if full 6058 */ 6059 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6060 { 6061 uint32_t data_count; 6062 6063 if (rb->wrpt >= rb->rptr) 6064 data_count = rb->wrpt - rb->rptr; 6065 else 6066 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6067 6068 return data_count / DMUB_RB_CMD_SIZE; 6069 } 6070 6071 /** 6072 * @brief gets number of free buffers in the RB 6073 * 6074 * @param rb DMUB Ringbuffer 6075 * @return true if full 6076 */ 6077 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6078 { 6079 uint32_t data_count; 6080 6081 if (rb->wrpt >= rb->rptr) 6082 data_count = rb->wrpt - rb->rptr; 6083 else 6084 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6085 6086 /* +1 because 1 entry is always unusable */ 6087 data_count += DMUB_RB_CMD_SIZE; 6088 6089 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6090 } 6091 6092 /** 6093 * @brief Checks if the ringbuffer is full 6094 * 6095 * @param rb DMUB Ringbuffer 6096 * @return true if full 6097 * @return false otherwise 6098 */ 6099 static inline bool dmub_rb_full(struct dmub_rb *rb) 6100 { 6101 uint32_t data_count; 6102 6103 if (rb->wrpt >= rb->rptr) 6104 data_count = rb->wrpt - rb->rptr; 6105 else 6106 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6107 6108 /* -1 because 1 entry is always unusable */ 6109 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6110 } 6111 6112 /** 6113 * @brief Pushes a command into the ringbuffer 6114 * 6115 * @param rb DMUB ringbuffer 6116 * @param cmd The command to push 6117 * @return true if the ringbuffer was not full 6118 * @return false otherwise 6119 */ 6120 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6121 const union dmub_rb_cmd *cmd) 6122 { 6123 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6124 const uint64_t *src = (const uint64_t *)cmd; 6125 uint8_t i; 6126 6127 if (dmub_rb_full(rb)) 6128 return false; 6129 6130 // copying data 6131 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6132 *dst++ = *src++; 6133 6134 rb->wrpt += DMUB_RB_CMD_SIZE; 6135 6136 if (rb->wrpt >= rb->capacity) 6137 rb->wrpt %= rb->capacity; 6138 6139 return true; 6140 } 6141 6142 /** 6143 * @brief Pushes a command into the DMUB outbox ringbuffer 6144 * 6145 * @param rb DMUB outbox ringbuffer 6146 * @param cmd Outbox command 6147 * @return true if not full 6148 * @return false otherwise 6149 */ 6150 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6151 const union dmub_rb_out_cmd *cmd) 6152 { 6153 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6154 const uint8_t *src = (const uint8_t *)cmd; 6155 6156 if (dmub_rb_full(rb)) 6157 return false; 6158 6159 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6160 6161 rb->wrpt += DMUB_RB_CMD_SIZE; 6162 6163 if (rb->wrpt >= rb->capacity) 6164 rb->wrpt %= rb->capacity; 6165 6166 return true; 6167 } 6168 6169 /** 6170 * @brief Returns the next unprocessed command in the ringbuffer. 6171 * 6172 * @param rb DMUB ringbuffer 6173 * @param cmd The command to return 6174 * @return true if not empty 6175 * @return false otherwise 6176 */ 6177 static inline bool dmub_rb_front(struct dmub_rb *rb, 6178 union dmub_rb_cmd **cmd) 6179 { 6180 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6181 6182 if (dmub_rb_empty(rb)) 6183 return false; 6184 6185 *cmd = (union dmub_rb_cmd *)rb_cmd; 6186 6187 return true; 6188 } 6189 6190 /** 6191 * @brief Determines the next ringbuffer offset. 6192 * 6193 * @param rb DMUB inbox ringbuffer 6194 * @param num_cmds Number of commands 6195 * @param next_rptr The next offset in the ringbuffer 6196 */ 6197 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6198 uint32_t num_cmds, 6199 uint32_t *next_rptr) 6200 { 6201 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6202 6203 if (*next_rptr >= rb->capacity) 6204 *next_rptr %= rb->capacity; 6205 } 6206 6207 /** 6208 * @brief Returns a pointer to a command in the inbox. 6209 * 6210 * @param rb DMUB inbox ringbuffer 6211 * @param cmd The inbox command to return 6212 * @param rptr The ringbuffer offset 6213 * @return true if not empty 6214 * @return false otherwise 6215 */ 6216 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6217 union dmub_rb_cmd **cmd, 6218 uint32_t rptr) 6219 { 6220 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6221 6222 if (dmub_rb_empty(rb)) 6223 return false; 6224 6225 *cmd = (union dmub_rb_cmd *)rb_cmd; 6226 6227 return true; 6228 } 6229 6230 /** 6231 * @brief Returns the next unprocessed command in the outbox. 6232 * 6233 * @param rb DMUB outbox ringbuffer 6234 * @param cmd The outbox command to return 6235 * @return true if not empty 6236 * @return false otherwise 6237 */ 6238 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6239 union dmub_rb_out_cmd *cmd) 6240 { 6241 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6242 uint64_t *dst = (uint64_t *)cmd; 6243 uint8_t i; 6244 6245 if (dmub_rb_empty(rb)) 6246 return false; 6247 6248 // copying data 6249 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6250 *dst++ = *src++; 6251 6252 return true; 6253 } 6254 6255 /** 6256 * @brief Removes the front entry in the ringbuffer. 6257 * 6258 * @param rb DMUB ringbuffer 6259 * @return true if the command was removed 6260 * @return false if there were no commands 6261 */ 6262 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6263 { 6264 if (dmub_rb_empty(rb)) 6265 return false; 6266 6267 rb->rptr += DMUB_RB_CMD_SIZE; 6268 6269 if (rb->rptr >= rb->capacity) 6270 rb->rptr %= rb->capacity; 6271 6272 return true; 6273 } 6274 6275 /** 6276 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6277 * 6278 * Avoids a race condition where DMCUB accesses memory while 6279 * there are still writes in flight to framebuffer. 6280 * 6281 * @param rb DMUB ringbuffer 6282 */ 6283 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6284 { 6285 uint32_t rptr = rb->rptr; 6286 uint32_t wptr = rb->wrpt; 6287 6288 while (rptr != wptr) { 6289 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6290 uint8_t i; 6291 6292 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6293 (void)READ_ONCE(*data++); 6294 6295 rptr += DMUB_RB_CMD_SIZE; 6296 if (rptr >= rb->capacity) 6297 rptr %= rb->capacity; 6298 } 6299 } 6300 6301 /** 6302 * @brief Initializes a DMCUB ringbuffer 6303 * 6304 * @param rb DMUB ringbuffer 6305 * @param init_params initial configuration for the ringbuffer 6306 */ 6307 static inline void dmub_rb_init(struct dmub_rb *rb, 6308 struct dmub_rb_init_params *init_params) 6309 { 6310 rb->base_address = init_params->base_address; 6311 rb->capacity = init_params->capacity; 6312 rb->rptr = init_params->read_ptr; 6313 rb->wrpt = init_params->write_ptr; 6314 } 6315 6316 /** 6317 * @brief Copies output data from in/out commands into the given command. 6318 * 6319 * @param rb DMUB ringbuffer 6320 * @param cmd Command to copy data into 6321 */ 6322 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6323 union dmub_rb_cmd *cmd) 6324 { 6325 // Copy rb entry back into command 6326 uint8_t *rd_ptr = (rb->rptr == 0) ? 6327 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6328 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6329 6330 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6331 } 6332 6333 //============================================================================== 6334 //</DMUB_RB>==================================================================== 6335 //============================================================================== 6336 #endif /* _DMUB_CMD_H_ */ 6337