1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic udelay 165 */ 166 #ifndef dmub_udelay 167 #define dmub_udelay(microseconds) udelay(microseconds) 168 #endif 169 170 #pragma pack(push, 1) 171 #define ABM_NUM_OF_ACE_SEGMENTS 5 172 173 union abm_flags { 174 struct { 175 /** 176 * @abm_enabled: Indicates if ABM is enabled. 177 */ 178 unsigned int abm_enabled : 1; 179 180 /** 181 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 182 */ 183 unsigned int disable_abm_requested : 1; 184 185 /** 186 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 187 */ 188 unsigned int disable_abm_immediately : 1; 189 190 /** 191 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 192 * to be disabled immediately and keep gain. 193 */ 194 unsigned int disable_abm_immediate_keep_gain : 1; 195 196 /** 197 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 198 */ 199 unsigned int fractional_pwm : 1; 200 201 /** 202 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 203 * of user backlight level. 204 */ 205 unsigned int abm_gradual_bl_change : 1; 206 207 /** 208 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 209 */ 210 unsigned int abm_new_frame : 1; 211 212 /** 213 * @vb_scaling_enabled: Indicates variBright Scaling Enable 214 */ 215 unsigned int vb_scaling_enabled : 1; 216 } bitfields; 217 218 unsigned int u32All; 219 }; 220 221 struct abm_save_restore { 222 /** 223 * @flags: Misc. ABM flags. 224 */ 225 union abm_flags flags; 226 227 /** 228 * @pause: true: pause ABM and get state 229 * false: unpause ABM after setting state 230 */ 231 uint32_t pause; 232 233 /** 234 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 235 */ 236 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 237 238 /** 239 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 240 */ 241 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 242 243 /** 244 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 245 */ 246 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 247 248 249 /** 250 * @knee_threshold: Current x-position of ACE knee (u0.16). 251 */ 252 uint32_t knee_threshold; 253 /** 254 * @current_gain: Current backlight reduction (u16.16). 255 */ 256 uint32_t current_gain; 257 /** 258 * @curr_bl_level: Current actual backlight level converging to target backlight level. 259 */ 260 uint16_t curr_bl_level; 261 262 /** 263 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 264 */ 265 uint16_t curr_user_bl_level; 266 267 }; 268 269 /** 270 * union dmub_addr - DMUB physical/virtual 64-bit address. 271 */ 272 union dmub_addr { 273 struct { 274 uint32_t low_part; /**< Lower 32 bits */ 275 uint32_t high_part; /**< Upper 32 bits */ 276 } u; /*<< Low/high bit access */ 277 uint64_t quad_part; /*<< 64 bit address */ 278 }; 279 #pragma pack(pop) 280 281 /** 282 * Dirty rect definition. 283 */ 284 struct dmub_rect { 285 /** 286 * Dirty rect x offset. 287 */ 288 uint32_t x; 289 290 /** 291 * Dirty rect y offset. 292 */ 293 uint32_t y; 294 295 /** 296 * Dirty rect width. 297 */ 298 uint32_t width; 299 300 /** 301 * Dirty rect height. 302 */ 303 uint32_t height; 304 }; 305 306 /** 307 * Flags that can be set by driver to change some PSR behaviour. 308 */ 309 union dmub_psr_debug_flags { 310 /** 311 * Debug flags. 312 */ 313 struct { 314 /** 315 * Enable visual confirm in FW. 316 */ 317 uint32_t visual_confirm : 1; 318 319 /** 320 * Force all selective updates to bw full frame updates. 321 */ 322 uint32_t force_full_frame_update : 1; 323 324 /** 325 * Use HW Lock Mgr object to do HW locking in FW. 326 */ 327 uint32_t use_hw_lock_mgr : 1; 328 329 /** 330 * Use TPS3 signal when restore main link. 331 */ 332 uint32_t force_wakeup_by_tps3 : 1; 333 334 /** 335 * Back to back flip, therefore cannot power down PHY 336 */ 337 uint32_t back_to_back_flip : 1; 338 339 } bitfields; 340 341 /** 342 * Union for debug flags. 343 */ 344 uint32_t u32All; 345 }; 346 347 /** 348 * Flags that can be set by driver to change some Replay behaviour. 349 */ 350 union replay_debug_flags { 351 struct { 352 /** 353 * 0x1 (bit 0) 354 * Enable visual confirm in FW. 355 */ 356 uint32_t visual_confirm : 1; 357 358 /** 359 * 0x2 (bit 1) 360 * @skip_crc: Set if need to skip CRC. 361 */ 362 uint32_t skip_crc : 1; 363 364 /** 365 * 0x4 (bit 2) 366 * @force_link_power_on: Force disable ALPM control 367 */ 368 uint32_t force_link_power_on : 1; 369 370 /** 371 * 0x8 (bit 3) 372 * @force_phy_power_on: Force phy power on 373 */ 374 uint32_t force_phy_power_on : 1; 375 376 /** 377 * 0x10 (bit 4) 378 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 379 */ 380 uint32_t timing_resync_disabled : 1; 381 382 /** 383 * 0x20 (bit 5) 384 * @skip_crtc_disabled: CRTC disable skipped 385 */ 386 uint32_t skip_crtc_disabled : 1; 387 388 /** 389 * 0x40 (bit 6) 390 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 391 */ 392 uint32_t force_defer_one_frame_update : 1; 393 394 /** 395 * 0x80 (bit 7) 396 * @disable_delay_alpm_on: Force disable delay alpm on 397 */ 398 uint32_t disable_delay_alpm_on : 1; 399 400 /** 401 * 0x100 (bit 8) 402 * @disable_desync_error_check: Force disable desync error check 403 */ 404 uint32_t disable_desync_error_check : 1; 405 406 /** 407 * 0x200 (bit 9) 408 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 409 */ 410 uint32_t force_self_update_when_abm_non_steady : 1; 411 412 /** 413 * 0x400 (bit 10) 414 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 415 * If we enter IPS2, the Visual confirm bar will change to yellow 416 */ 417 uint32_t enable_ips_visual_confirm : 1; 418 419 /** 420 * 0x800 (bit 11) 421 * @enable_ips_residency_profiling: Enable IPS residency profiling 422 */ 423 uint32_t enable_ips_residency_profiling : 1; 424 425 uint32_t reserved : 20; 426 } bitfields; 427 428 uint32_t u32All; 429 }; 430 431 union replay_hw_flags { 432 struct { 433 /** 434 * @allow_alpm_fw_standby_mode: To indicate whether the 435 * ALPM FW standby mode is allowed 436 */ 437 uint32_t allow_alpm_fw_standby_mode : 1; 438 439 /* 440 * @dsc_enable_status: DSC enable status in driver 441 */ 442 uint32_t dsc_enable_status : 1; 443 444 /** 445 * @fec_enable_status: receive fec enable/disable status from driver 446 */ 447 uint32_t fec_enable_status : 1; 448 449 /* 450 * @smu_optimizations_en: SMU power optimization. 451 * Only when active display is Replay capable and display enters Replay. 452 * Trigger interrupt to SMU to powerup/down. 453 */ 454 uint32_t smu_optimizations_en : 1; 455 456 /** 457 * @phy_power_state: Indicates current phy power state 458 */ 459 uint32_t phy_power_state : 1; 460 461 /** 462 * @link_power_state: Indicates current link power state 463 */ 464 uint32_t link_power_state : 1; 465 /** 466 * Use TPS3 signal when restore main link. 467 */ 468 uint32_t force_wakeup_by_tps3 : 1; 469 } bitfields; 470 471 uint32_t u32All; 472 }; 473 474 /** 475 * DMUB feature capabilities. 476 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 477 */ 478 struct dmub_feature_caps { 479 /** 480 * Max PSR version supported by FW. 481 */ 482 uint8_t psr; 483 uint8_t fw_assisted_mclk_switch_ver; 484 uint8_t reserved[4]; 485 uint8_t subvp_psr_support; 486 uint8_t gecc_enable; 487 uint8_t replay_supported; 488 uint8_t replay_reserved[3]; 489 }; 490 491 struct dmub_visual_confirm_color { 492 /** 493 * Maximum 10 bits color value 494 */ 495 uint16_t color_r_cr; 496 uint16_t color_g_y; 497 uint16_t color_b_cb; 498 uint16_t panel_inst; 499 }; 500 501 //============================================================================== 502 //</DMUB_TYPES>================================================================= 503 //============================================================================== 504 //< DMUB_META>================================================================== 505 //============================================================================== 506 #pragma pack(push, 1) 507 508 /* Magic value for identifying dmub_fw_meta_info */ 509 #define DMUB_FW_META_MAGIC 0x444D5542 510 511 /* Offset from the end of the file to the dmub_fw_meta_info */ 512 #define DMUB_FW_META_OFFSET 0x24 513 514 /** 515 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 516 */ 517 union dmub_fw_meta_feature_bits { 518 struct { 519 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 520 uint32_t reserved : 31; 521 } bits; /**< status bits */ 522 uint32_t all; /**< 32-bit access to status bits */ 523 }; 524 525 /** 526 * struct dmub_fw_meta_info - metadata associated with fw binary 527 * 528 * NOTE: This should be considered a stable API. Fields should 529 * not be repurposed or reordered. New fields should be 530 * added instead to extend the structure. 531 * 532 * @magic_value: magic value identifying DMUB firmware meta info 533 * @fw_region_size: size of the firmware state region 534 * @trace_buffer_size: size of the tracebuffer region 535 * @fw_version: the firmware version information 536 * @dal_fw: 1 if the firmware is DAL 537 * @shared_state_size: size of the shared state region in bytes 538 * @shared_state_features: number of shared state features 539 */ 540 struct dmub_fw_meta_info { 541 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 542 uint32_t fw_region_size; /**< size of the firmware state region */ 543 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 544 uint32_t fw_version; /**< the firmware version information */ 545 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 546 uint8_t reserved[3]; /**< padding bits */ 547 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 548 uint16_t shared_state_features; /**< number of shared state features */ 549 uint16_t reserved2; /**< padding bytes */ 550 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 551 }; 552 553 /** 554 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 555 */ 556 union dmub_fw_meta { 557 struct dmub_fw_meta_info info; /**< metadata info */ 558 uint8_t reserved[64]; /**< padding bits */ 559 }; 560 561 #pragma pack(pop) 562 563 //============================================================================== 564 //< DMUB Trace Buffer>================================================================ 565 //============================================================================== 566 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 567 /** 568 * dmub_trace_code_t - firmware trace code, 32-bits 569 */ 570 typedef uint32_t dmub_trace_code_t; 571 572 /** 573 * struct dmcub_trace_buf_entry - Firmware trace entry 574 */ 575 struct dmcub_trace_buf_entry { 576 dmub_trace_code_t trace_code; /**< trace code for the event */ 577 uint32_t tick_count; /**< the tick count at time of trace */ 578 uint32_t param0; /**< trace defined parameter 0 */ 579 uint32_t param1; /**< trace defined parameter 1 */ 580 }; 581 #endif 582 583 //============================================================================== 584 //< DMUB_STATUS>================================================================ 585 //============================================================================== 586 587 /** 588 * DMCUB scratch registers can be used to determine firmware status. 589 * Current scratch register usage is as follows: 590 * 591 * SCRATCH0: FW Boot Status register 592 * SCRATCH5: LVTMA Status Register 593 * SCRATCH15: FW Boot Options register 594 */ 595 596 /** 597 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 598 */ 599 union dmub_fw_boot_status { 600 struct { 601 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 602 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 603 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 604 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 605 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 606 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 607 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 608 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 609 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 610 } bits; /**< status bits */ 611 uint32_t all; /**< 32-bit access to status bits */ 612 }; 613 614 /** 615 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 616 */ 617 enum dmub_fw_boot_status_bit { 618 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 619 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 620 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 621 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 622 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 623 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 624 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 625 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 626 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 627 }; 628 629 /* Register bit definition for SCRATCH5 */ 630 union dmub_lvtma_status { 631 struct { 632 uint32_t psp_ok : 1; 633 uint32_t edp_on : 1; 634 uint32_t reserved : 30; 635 } bits; 636 uint32_t all; 637 }; 638 639 enum dmub_lvtma_status_bit { 640 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 641 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 642 }; 643 644 enum dmub_ips_disable_type { 645 DMUB_IPS_ENABLE = 0, 646 DMUB_IPS_DISABLE_ALL = 1, 647 DMUB_IPS_DISABLE_IPS1 = 2, 648 DMUB_IPS_DISABLE_IPS2 = 3, 649 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 650 DMUB_IPS_DISABLE_DYNAMIC = 5, 651 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 652 }; 653 654 #define DMUB_IPS1_ALLOW_MASK 0x00000001 655 #define DMUB_IPS2_ALLOW_MASK 0x00000002 656 #define DMUB_IPS1_COMMIT_MASK 0x00000004 657 #define DMUB_IPS2_COMMIT_MASK 0x00000008 658 659 /** 660 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 661 */ 662 union dmub_fw_boot_options { 663 struct { 664 uint32_t pemu_env : 1; /**< 1 if PEMU */ 665 uint32_t fpga_env : 1; /**< 1 if FPGA */ 666 uint32_t optimized_init : 1; /**< 1 if optimized init */ 667 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 668 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 669 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 670 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 671 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 672 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 673 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 674 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 675 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 676 uint32_t power_optimization: 1; 677 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 678 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 679 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 680 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 681 uint32_t reserved0: 1; 682 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 683 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 684 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 685 uint32_t ips_disable: 3; /* options to disable ips support*/ 686 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 687 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 688 uint32_t reserved : 7; /**< reserved */ 689 } bits; /**< boot bits */ 690 uint32_t all; /**< 32-bit access to bits */ 691 }; 692 693 enum dmub_fw_boot_options_bit { 694 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 695 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 696 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 697 }; 698 699 //============================================================================== 700 //< DMUB_SHARED_STATE>========================================================== 701 //============================================================================== 702 703 /** 704 * Shared firmware state between driver and firmware for lockless communication 705 * in situations where the inbox/outbox may be unavailable. 706 * 707 * Each structure *must* be at most 256-bytes in size. The layout allocation is 708 * described below: 709 * 710 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 711 */ 712 713 /** 714 * enum dmub_shared_state_feature_id - List of shared state features. 715 */ 716 enum dmub_shared_state_feature_id { 717 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 718 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 719 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 720 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 721 }; 722 723 /** 724 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 725 */ 726 union dmub_shared_state_ips_fw_signals { 727 struct { 728 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 729 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 730 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 731 uint32_t detection_required : 1; /**< 1 if detection is required */ 732 uint32_t reserved_bits : 28; /**< Reversed */ 733 } bits; 734 uint32_t all; 735 }; 736 737 /** 738 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 739 */ 740 union dmub_shared_state_ips_driver_signals { 741 struct { 742 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 743 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 744 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 745 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 746 uint32_t reserved_bits : 28; /**< Reversed bits */ 747 } bits; 748 uint32_t all; 749 }; 750 751 /** 752 * IPS FW Version 753 */ 754 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 755 756 /** 757 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 758 */ 759 struct dmub_shared_state_ips_fw { 760 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 761 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 762 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 763 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 764 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 765 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 766 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 767 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 768 }; /* 248-bytes, fixed */ 769 770 /** 771 * IPS Driver Version 772 */ 773 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 774 775 /** 776 * struct dmub_shared_state_ips_driver - Driver state for IPS. 777 */ 778 struct dmub_shared_state_ips_driver { 779 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 780 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 781 }; /* 248-bytes, fixed */ 782 783 /** 784 * enum dmub_shared_state_feature_common - Generic payload. 785 */ 786 struct dmub_shared_state_feature_common { 787 uint32_t padding[62]; 788 }; /* 248-bytes, fixed */ 789 790 /** 791 * enum dmub_shared_state_feature_header - Feature description. 792 */ 793 struct dmub_shared_state_feature_header { 794 uint16_t id; /**< Feature ID */ 795 uint16_t version; /**< Feature version */ 796 uint32_t reserved; /**< Reserved bytes. */ 797 }; /* 8 bytes, fixed */ 798 799 /** 800 * struct dmub_shared_state_feature_block - Feature block. 801 */ 802 struct dmub_shared_state_feature_block { 803 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 804 union dmub_shared_feature_state_union { 805 struct dmub_shared_state_feature_common common; /**< Generic data */ 806 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 807 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 808 } data; /**< Shared state data. */ 809 }; /* 256-bytes, fixed */ 810 811 /** 812 * Shared state size in bytes. 813 */ 814 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 815 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 816 817 //============================================================================== 818 //</DMUB_STATUS>================================================================ 819 //============================================================================== 820 //< DMUB_VBIOS>================================================================= 821 //============================================================================== 822 823 /* 824 * enum dmub_cmd_vbios_type - VBIOS commands. 825 * 826 * Command IDs should be treated as stable ABI. 827 * Do not reuse or modify IDs. 828 */ 829 enum dmub_cmd_vbios_type { 830 /** 831 * Configures the DIG encoder. 832 */ 833 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 834 /** 835 * Controls the PHY. 836 */ 837 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 838 /** 839 * Sets the pixel clock/symbol clock. 840 */ 841 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 842 /** 843 * Enables or disables power gating. 844 */ 845 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 846 /** 847 * Controls embedded panels. 848 */ 849 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 850 /** 851 * Query DP alt status on a transmitter. 852 */ 853 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 854 /** 855 * Control PHY FSM 856 */ 857 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 858 /** 859 * Controls domain power gating 860 */ 861 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 862 }; 863 864 //============================================================================== 865 //</DMUB_VBIOS>================================================================= 866 //============================================================================== 867 //< DMUB_GPINT>================================================================= 868 //============================================================================== 869 870 /** 871 * The shifts and masks below may alternatively be used to format and read 872 * the command register bits. 873 */ 874 875 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 876 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 877 878 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 879 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 880 881 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 882 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 883 884 /** 885 * Command responses. 886 */ 887 888 /** 889 * Return response for DMUB_GPINT__STOP_FW command. 890 */ 891 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 892 893 /** 894 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 895 */ 896 union dmub_gpint_data_register { 897 struct { 898 uint32_t param : 16; /**< 16-bit parameter */ 899 uint32_t command_code : 12; /**< GPINT command */ 900 uint32_t status : 4; /**< Command status bit */ 901 } bits; /**< GPINT bit access */ 902 uint32_t all; /**< GPINT 32-bit access */ 903 }; 904 905 /* 906 * enum dmub_gpint_command - GPINT command to DMCUB FW 907 * 908 * Command IDs should be treated as stable ABI. 909 * Do not reuse or modify IDs. 910 */ 911 enum dmub_gpint_command { 912 /** 913 * Invalid command, ignored. 914 */ 915 DMUB_GPINT__INVALID_COMMAND = 0, 916 /** 917 * DESC: Queries the firmware version. 918 * RETURN: Firmware version. 919 */ 920 DMUB_GPINT__GET_FW_VERSION = 1, 921 /** 922 * DESC: Halts the firmware. 923 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 924 */ 925 DMUB_GPINT__STOP_FW = 2, 926 /** 927 * DESC: Get PSR state from FW. 928 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 929 */ 930 DMUB_GPINT__GET_PSR_STATE = 7, 931 /** 932 * DESC: Notifies DMCUB of the currently active streams. 933 * ARGS: Stream mask, 1 bit per active stream index. 934 */ 935 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 936 /** 937 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 938 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 939 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 940 * RETURN: PSR residency in milli-percent. 941 */ 942 DMUB_GPINT__PSR_RESIDENCY = 9, 943 944 /** 945 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 946 */ 947 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 948 949 /** 950 * DESC: Get REPLAY state from FW. 951 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 952 */ 953 DMUB_GPINT__GET_REPLAY_STATE = 13, 954 955 /** 956 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 957 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 958 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 959 * RETURN: REPLAY residency in milli-percent. 960 */ 961 DMUB_GPINT__REPLAY_RESIDENCY = 14, 962 963 /** 964 * DESC: Copy bounding box to the host. 965 * ARGS: Version of bounding box to copy 966 * RETURN: Result of copying bounding box 967 */ 968 DMUB_GPINT__BB_COPY = 96, 969 970 /** 971 * DESC: Updates the host addresses bit48~bit63 for bounding box. 972 * ARGS: The word3 for the 64 bit address 973 */ 974 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 975 976 /** 977 * DESC: Updates the host addresses bit32~bit47 for bounding box. 978 * ARGS: The word2 for the 64 bit address 979 */ 980 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 981 982 /** 983 * DESC: Updates the host addresses bit16~bit31 for bounding box. 984 * ARGS: The word1 for the 64 bit address 985 */ 986 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 987 988 /** 989 * DESC: Updates the host addresses bit0~bit15 for bounding box. 990 * ARGS: The word0 for the 64 bit address 991 */ 992 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 993 994 /** 995 * DESC: Updates the trace buffer lower 32-bit mask. 996 * ARGS: The new mask 997 * RETURN: Lower 32-bit mask. 998 */ 999 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1000 1001 /** 1002 * DESC: Updates the trace buffer mask bit0~bit15. 1003 * ARGS: The new mask 1004 * RETURN: Lower 32-bit mask. 1005 */ 1006 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1007 1008 /** 1009 * DESC: Updates the trace buffer mask bit16~bit31. 1010 * ARGS: The new mask 1011 * RETURN: Lower 32-bit mask. 1012 */ 1013 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1014 1015 /** 1016 * DESC: Updates the trace buffer mask bit32~bit47. 1017 * ARGS: The new mask 1018 * RETURN: Lower 32-bit mask. 1019 */ 1020 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1021 1022 /** 1023 * DESC: Updates the trace buffer mask bit48~bit63. 1024 * ARGS: The new mask 1025 * RETURN: Lower 32-bit mask. 1026 */ 1027 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1028 1029 /** 1030 * DESC: Read the trace buffer mask bi0~bit15. 1031 */ 1032 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1033 1034 /** 1035 * DESC: Read the trace buffer mask bit16~bit31. 1036 */ 1037 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1038 1039 /** 1040 * DESC: Read the trace buffer mask bi32~bit47. 1041 */ 1042 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1043 1044 /** 1045 * DESC: Updates the trace buffer mask bit32~bit63. 1046 */ 1047 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1048 1049 /** 1050 * DESC: Enable measurements for various task duration 1051 * ARGS: 0 - Disable measurement 1052 * 1 - Enable measurement 1053 */ 1054 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1055 }; 1056 1057 /** 1058 * INBOX0 generic command definition 1059 */ 1060 union dmub_inbox0_cmd_common { 1061 struct { 1062 uint32_t command_code: 8; /**< INBOX0 command code */ 1063 uint32_t param: 24; /**< 24-bit parameter */ 1064 } bits; 1065 uint32_t all; 1066 }; 1067 1068 /** 1069 * INBOX0 hw_lock command definition 1070 */ 1071 union dmub_inbox0_cmd_lock_hw { 1072 struct { 1073 uint32_t command_code: 8; 1074 1075 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1076 uint32_t hw_lock_client: 2; 1077 1078 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1079 uint32_t otg_inst: 3; 1080 uint32_t opp_inst: 3; 1081 uint32_t dig_inst: 3; 1082 1083 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1084 uint32_t lock_pipe: 1; 1085 uint32_t lock_cursor: 1; 1086 uint32_t lock_dig: 1; 1087 uint32_t triple_buffer_lock: 1; 1088 1089 uint32_t lock: 1; /**< Lock */ 1090 uint32_t should_release: 1; /**< Release */ 1091 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1092 } bits; 1093 uint32_t all; 1094 }; 1095 1096 union dmub_inbox0_data_register { 1097 union dmub_inbox0_cmd_common inbox0_cmd_common; 1098 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1099 }; 1100 1101 enum dmub_inbox0_command { 1102 /** 1103 * DESC: Invalid command, ignored. 1104 */ 1105 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1106 /** 1107 * DESC: Notification to acquire/release HW lock 1108 * ARGS: 1109 */ 1110 DMUB_INBOX0_CMD__HW_LOCK = 1, 1111 }; 1112 //============================================================================== 1113 //</DMUB_GPINT>================================================================= 1114 //============================================================================== 1115 //< DMUB_CMD>=================================================================== 1116 //============================================================================== 1117 1118 /** 1119 * Size in bytes of each DMUB command. 1120 */ 1121 #define DMUB_RB_CMD_SIZE 64 1122 1123 /** 1124 * Maximum number of items in the DMUB ringbuffer. 1125 */ 1126 #define DMUB_RB_MAX_ENTRY 128 1127 1128 /** 1129 * Ringbuffer size in bytes. 1130 */ 1131 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1132 1133 /** 1134 * REG_SET mask for reg offload. 1135 */ 1136 #define REG_SET_MASK 0xFFFF 1137 1138 /* 1139 * enum dmub_cmd_type - DMUB inbox command. 1140 * 1141 * Command IDs should be treated as stable ABI. 1142 * Do not reuse or modify IDs. 1143 */ 1144 enum dmub_cmd_type { 1145 /** 1146 * Invalid command. 1147 */ 1148 DMUB_CMD__NULL = 0, 1149 /** 1150 * Read modify write register sequence offload. 1151 */ 1152 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1153 /** 1154 * Field update register sequence offload. 1155 */ 1156 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1157 /** 1158 * Burst write sequence offload. 1159 */ 1160 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1161 /** 1162 * Reg wait sequence offload. 1163 */ 1164 DMUB_CMD__REG_REG_WAIT = 4, 1165 /** 1166 * Workaround to avoid HUBP underflow during NV12 playback. 1167 */ 1168 DMUB_CMD__PLAT_54186_WA = 5, 1169 /** 1170 * Command type used to query FW feature caps. 1171 */ 1172 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1173 /** 1174 * Command type used to get visual confirm color. 1175 */ 1176 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1177 /** 1178 * Command type used for all PSR commands. 1179 */ 1180 DMUB_CMD__PSR = 64, 1181 /** 1182 * Command type used for all MALL commands. 1183 */ 1184 DMUB_CMD__MALL = 65, 1185 /** 1186 * Command type used for all ABM commands. 1187 */ 1188 DMUB_CMD__ABM = 66, 1189 /** 1190 * Command type used to update dirty rects in FW. 1191 */ 1192 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1193 /** 1194 * Command type used to update cursor info in FW. 1195 */ 1196 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1197 /** 1198 * Command type used for HW locking in FW. 1199 */ 1200 DMUB_CMD__HW_LOCK = 69, 1201 /** 1202 * Command type used to access DP AUX. 1203 */ 1204 DMUB_CMD__DP_AUX_ACCESS = 70, 1205 /** 1206 * Command type used for OUTBOX1 notification enable 1207 */ 1208 DMUB_CMD__OUTBOX1_ENABLE = 71, 1209 1210 /** 1211 * Command type used for all idle optimization commands. 1212 */ 1213 DMUB_CMD__IDLE_OPT = 72, 1214 /** 1215 * Command type used for all clock manager commands. 1216 */ 1217 DMUB_CMD__CLK_MGR = 73, 1218 /** 1219 * Command type used for all panel control commands. 1220 */ 1221 DMUB_CMD__PANEL_CNTL = 74, 1222 1223 /** 1224 * Command type used for all CAB commands. 1225 */ 1226 DMUB_CMD__CAB_FOR_SS = 75, 1227 1228 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1229 1230 /** 1231 * Command type used for interfacing with DPIA. 1232 */ 1233 DMUB_CMD__DPIA = 77, 1234 /** 1235 * Command type used for EDID CEA parsing 1236 */ 1237 DMUB_CMD__EDID_CEA = 79, 1238 /** 1239 * Command type used for getting usbc cable ID 1240 */ 1241 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1242 /** 1243 * Command type used to query HPD state. 1244 */ 1245 DMUB_CMD__QUERY_HPD_STATE = 82, 1246 /** 1247 * Command type used for all VBIOS interface commands. 1248 */ 1249 /** 1250 * Command type used for all REPLAY commands. 1251 */ 1252 DMUB_CMD__REPLAY = 83, 1253 1254 /** 1255 * Command type used for all SECURE_DISPLAY commands. 1256 */ 1257 DMUB_CMD__SECURE_DISPLAY = 85, 1258 1259 /** 1260 * Command type used to set DPIA HPD interrupt state 1261 */ 1262 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1263 1264 /** 1265 * Command type used for all PSP commands. 1266 */ 1267 DMUB_CMD__PSP = 88, 1268 1269 DMUB_CMD__VBIOS = 128, 1270 }; 1271 1272 /** 1273 * enum dmub_out_cmd_type - DMUB outbox commands. 1274 */ 1275 enum dmub_out_cmd_type { 1276 /** 1277 * Invalid outbox command, ignored. 1278 */ 1279 DMUB_OUT_CMD__NULL = 0, 1280 /** 1281 * Command type used for DP AUX Reply data notification 1282 */ 1283 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1284 /** 1285 * Command type used for DP HPD event notification 1286 */ 1287 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1288 /** 1289 * Command type used for SET_CONFIG Reply notification 1290 */ 1291 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1292 /** 1293 * Command type used for USB4 DPIA notification 1294 */ 1295 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1296 /** 1297 * Command type used for HPD redetect notification 1298 */ 1299 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1300 }; 1301 1302 /* DMUB_CMD__DPIA command sub-types. */ 1303 enum dmub_cmd_dpia_type { 1304 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1305 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1306 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1307 }; 1308 1309 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1310 enum dmub_cmd_dpia_notification_type { 1311 DPIA_NOTIFY__BW_ALLOCATION = 0, 1312 }; 1313 1314 #pragma pack(push, 1) 1315 1316 /** 1317 * struct dmub_cmd_header - Common command header fields. 1318 */ 1319 struct dmub_cmd_header { 1320 unsigned int type : 8; /**< command type */ 1321 unsigned int sub_type : 8; /**< command sub type */ 1322 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1323 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1324 unsigned int reserved0 : 6; /**< reserved bits */ 1325 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1326 unsigned int reserved1 : 2; /**< reserved bits */ 1327 }; 1328 1329 /* 1330 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1331 * 1332 * 60 payload bytes can hold up to 5 sets of read modify writes, 1333 * each take 3 dwords. 1334 * 1335 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1336 * 1337 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1338 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1339 */ 1340 struct dmub_cmd_read_modify_write_sequence { 1341 uint32_t addr; /**< register address */ 1342 uint32_t modify_mask; /**< modify mask */ 1343 uint32_t modify_value; /**< modify value */ 1344 }; 1345 1346 /** 1347 * Maximum number of ops in read modify write sequence. 1348 */ 1349 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1350 1351 /** 1352 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1353 */ 1354 struct dmub_rb_cmd_read_modify_write { 1355 struct dmub_cmd_header header; /**< command header */ 1356 /** 1357 * Read modify write sequence. 1358 */ 1359 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1360 }; 1361 1362 /* 1363 * Update a register with specified masks and values sequeunce 1364 * 1365 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1366 * 1367 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1368 * 1369 * 1370 * USE CASE: 1371 * 1. auto-increment register where additional read would update pointer and produce wrong result 1372 * 2. toggle a bit without read in the middle 1373 */ 1374 1375 struct dmub_cmd_reg_field_update_sequence { 1376 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1377 uint32_t modify_value; /**< value to update with */ 1378 }; 1379 1380 /** 1381 * Maximum number of ops in field update sequence. 1382 */ 1383 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1384 1385 /** 1386 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1387 */ 1388 struct dmub_rb_cmd_reg_field_update_sequence { 1389 struct dmub_cmd_header header; /**< command header */ 1390 uint32_t addr; /**< register address */ 1391 /** 1392 * Field update sequence. 1393 */ 1394 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1395 }; 1396 1397 1398 /** 1399 * Maximum number of burst write values. 1400 */ 1401 #define DMUB_BURST_WRITE_VALUES__MAX 14 1402 1403 /* 1404 * struct dmub_rb_cmd_burst_write - Burst write 1405 * 1406 * support use case such as writing out LUTs. 1407 * 1408 * 60 payload bytes can hold up to 14 values to write to given address 1409 * 1410 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1411 */ 1412 struct dmub_rb_cmd_burst_write { 1413 struct dmub_cmd_header header; /**< command header */ 1414 uint32_t addr; /**< register start address */ 1415 /** 1416 * Burst write register values. 1417 */ 1418 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1419 }; 1420 1421 /** 1422 * struct dmub_rb_cmd_common - Common command header 1423 */ 1424 struct dmub_rb_cmd_common { 1425 struct dmub_cmd_header header; /**< command header */ 1426 /** 1427 * Padding to RB_CMD_SIZE 1428 */ 1429 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1430 }; 1431 1432 /** 1433 * struct dmub_cmd_reg_wait_data - Register wait data 1434 */ 1435 struct dmub_cmd_reg_wait_data { 1436 uint32_t addr; /**< Register address */ 1437 uint32_t mask; /**< Mask for register bits */ 1438 uint32_t condition_field_value; /**< Value to wait for */ 1439 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1440 }; 1441 1442 /** 1443 * struct dmub_rb_cmd_reg_wait - Register wait command 1444 */ 1445 struct dmub_rb_cmd_reg_wait { 1446 struct dmub_cmd_header header; /**< Command header */ 1447 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1448 }; 1449 1450 /** 1451 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1452 * 1453 * Reprograms surface parameters to avoid underflow. 1454 */ 1455 struct dmub_cmd_PLAT_54186_wa { 1456 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1457 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1458 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1459 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1460 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1461 struct { 1462 uint32_t hubp_inst : 4; /**< HUBP instance */ 1463 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1464 uint32_t immediate :1; /**< Immediate flip */ 1465 uint32_t vmid : 4; /**< VMID */ 1466 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1467 uint32_t reserved : 21; /**< Reserved */ 1468 } flip_params; /**< Pageflip parameters */ 1469 uint32_t reserved[9]; /**< Reserved bits */ 1470 }; 1471 1472 /** 1473 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1474 */ 1475 struct dmub_rb_cmd_PLAT_54186_wa { 1476 struct dmub_cmd_header header; /**< Command header */ 1477 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1478 }; 1479 1480 /** 1481 * enum dmub_cmd_mall_type - MALL commands 1482 */ 1483 enum dmub_cmd_mall_type { 1484 /** 1485 * Allows display refresh from MALL. 1486 */ 1487 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1488 /** 1489 * Disallows display refresh from MALL. 1490 */ 1491 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1492 /** 1493 * Cursor copy for MALL. 1494 */ 1495 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1496 /** 1497 * Controls DF requests. 1498 */ 1499 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1500 }; 1501 1502 /** 1503 * struct dmub_rb_cmd_mall - MALL command data. 1504 */ 1505 struct dmub_rb_cmd_mall { 1506 struct dmub_cmd_header header; /**< Common command header */ 1507 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1508 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1509 uint32_t tmr_delay; /**< Timer delay */ 1510 uint32_t tmr_scale; /**< Timer scale */ 1511 uint16_t cursor_width; /**< Cursor width in pixels */ 1512 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1513 uint16_t cursor_height; /**< Cursor height in pixels */ 1514 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1515 uint8_t debug_bits; /**< Debug bits */ 1516 1517 uint8_t reserved1; /**< Reserved bits */ 1518 uint8_t reserved2; /**< Reserved bits */ 1519 }; 1520 1521 /** 1522 * enum dmub_cmd_cab_type - CAB command data. 1523 */ 1524 enum dmub_cmd_cab_type { 1525 /** 1526 * No idle optimizations (i.e. no CAB) 1527 */ 1528 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1529 /** 1530 * No DCN requests for memory 1531 */ 1532 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1533 /** 1534 * Fit surfaces in CAB (i.e. CAB enable) 1535 */ 1536 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1537 /** 1538 * Do not fit surfaces in CAB (i.e. no CAB) 1539 */ 1540 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1541 }; 1542 1543 /** 1544 * struct dmub_rb_cmd_cab - CAB command data. 1545 */ 1546 struct dmub_rb_cmd_cab_for_ss { 1547 struct dmub_cmd_header header; 1548 uint8_t cab_alloc_ways; /* total number of ways */ 1549 uint8_t debug_bits; /* debug bits */ 1550 }; 1551 1552 /** 1553 * Enum for indicating which MCLK switch mode per pipe 1554 */ 1555 enum mclk_switch_mode { 1556 NONE = 0, 1557 FPO = 1, 1558 SUBVP = 2, 1559 VBLANK = 3, 1560 }; 1561 1562 /* Per pipe struct which stores the MCLK switch mode 1563 * data to be sent to DMUB. 1564 * Named "v2" for now -- once FPO and SUBVP are fully merged 1565 * the type name can be updated 1566 */ 1567 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1568 union { 1569 struct { 1570 uint32_t pix_clk_100hz; 1571 uint16_t main_vblank_start; 1572 uint16_t main_vblank_end; 1573 uint16_t mall_region_lines; 1574 uint16_t prefetch_lines; 1575 uint16_t prefetch_to_mall_start_lines; 1576 uint16_t processing_delay_lines; 1577 uint16_t htotal; // required to calculate line time for multi-display cases 1578 uint16_t vtotal; 1579 uint8_t main_pipe_index; 1580 uint8_t phantom_pipe_index; 1581 /* Since the microschedule is calculated in terms of OTG lines, 1582 * include any scaling factors to make sure when we get accurate 1583 * conversion when programming MALL_START_LINE (which is in terms 1584 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1585 * is 1/2 (numerator = 1, denominator = 2). 1586 */ 1587 uint8_t scale_factor_numerator; 1588 uint8_t scale_factor_denominator; 1589 uint8_t is_drr; 1590 uint8_t main_split_pipe_index; 1591 uint8_t phantom_split_pipe_index; 1592 } subvp_data; 1593 1594 struct { 1595 uint32_t pix_clk_100hz; 1596 uint16_t vblank_start; 1597 uint16_t vblank_end; 1598 uint16_t vstartup_start; 1599 uint16_t vtotal; 1600 uint16_t htotal; 1601 uint8_t vblank_pipe_index; 1602 uint8_t padding[1]; 1603 struct { 1604 uint8_t drr_in_use; 1605 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1606 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1607 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1608 uint8_t use_ramping; // Use ramping or not 1609 uint8_t drr_vblank_start_margin; 1610 } drr_info; // DRR considered as part of SubVP + VBLANK case 1611 } vblank_data; 1612 } pipe_config; 1613 1614 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1615 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1616 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1617 */ 1618 uint8_t mode; // enum mclk_switch_mode 1619 }; 1620 1621 /** 1622 * Config data for Sub-VP and FPO 1623 * Named "v2" for now -- once FPO and SUBVP are fully merged 1624 * the type name can be updated 1625 */ 1626 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1627 uint16_t watermark_a_cache; 1628 uint8_t vertical_int_margin_us; 1629 uint8_t pstate_allow_width_us; 1630 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1631 }; 1632 1633 /** 1634 * DMUB rb command definition for Sub-VP and FPO 1635 * Named "v2" for now -- once FPO and SUBVP are fully merged 1636 * the type name can be updated 1637 */ 1638 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1639 struct dmub_cmd_header header; 1640 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1641 }; 1642 1643 struct dmub_flip_addr_info { 1644 uint32_t surf_addr_lo; 1645 uint32_t surf_addr_c_lo; 1646 uint32_t meta_addr_lo; 1647 uint32_t meta_addr_c_lo; 1648 uint16_t surf_addr_hi; 1649 uint16_t surf_addr_c_hi; 1650 uint16_t meta_addr_hi; 1651 uint16_t meta_addr_c_hi; 1652 }; 1653 1654 struct dmub_fams2_flip_info { 1655 union { 1656 struct { 1657 uint8_t is_immediate: 1; 1658 } bits; 1659 uint8_t all; 1660 } config; 1661 uint8_t otg_inst; 1662 uint8_t pipe_mask; 1663 uint8_t pad; 1664 struct dmub_flip_addr_info addr_info; 1665 }; 1666 1667 struct dmub_rb_cmd_fams2_flip { 1668 struct dmub_cmd_header header; 1669 struct dmub_fams2_flip_info flip_info; 1670 }; 1671 1672 struct dmub_optc_state_v2 { 1673 uint32_t v_total_min; 1674 uint32_t v_total_max; 1675 uint32_t v_total_mid; 1676 uint32_t v_total_mid_frame_num; 1677 uint8_t program_manual_trigger; 1678 uint8_t tg_inst; 1679 uint8_t pad[2]; 1680 }; 1681 1682 struct dmub_optc_position { 1683 uint32_t vpos; 1684 uint32_t hpos; 1685 uint32_t frame; 1686 }; 1687 1688 struct dmub_rb_cmd_fams2_drr_update { 1689 struct dmub_cmd_header header; 1690 struct dmub_optc_state_v2 dmub_optc_state_req; 1691 }; 1692 1693 /* HW and FW global configuration data for FAMS2 */ 1694 /* FAMS2 types and structs */ 1695 enum fams2_stream_type { 1696 FAMS2_STREAM_TYPE_NONE = 0, 1697 FAMS2_STREAM_TYPE_VBLANK = 1, 1698 FAMS2_STREAM_TYPE_VACTIVE = 2, 1699 FAMS2_STREAM_TYPE_DRR = 3, 1700 FAMS2_STREAM_TYPE_SUBVP = 4, 1701 }; 1702 1703 /* dynamic stream state */ 1704 struct dmub_fams2_legacy_stream_dynamic_state { 1705 uint8_t force_allow_at_vblank; 1706 uint8_t pad[3]; 1707 }; 1708 1709 struct dmub_fams2_subvp_stream_dynamic_state { 1710 uint16_t viewport_start_hubp_vline; 1711 uint16_t viewport_height_hubp_vlines; 1712 uint16_t viewport_start_c_hubp_vline; 1713 uint16_t viewport_height_c_hubp_vlines; 1714 uint16_t phantom_viewport_height_hubp_vlines; 1715 uint16_t phantom_viewport_height_c_hubp_vlines; 1716 uint16_t microschedule_start_otg_vline; 1717 uint16_t mall_start_otg_vline; 1718 uint16_t mall_start_hubp_vline; 1719 uint16_t mall_start_c_hubp_vline; 1720 uint8_t force_allow_at_vblank_only; 1721 uint8_t pad[3]; 1722 }; 1723 1724 struct dmub_fams2_drr_stream_dynamic_state { 1725 uint16_t stretched_vtotal; 1726 uint8_t use_cur_vtotal; 1727 uint8_t pad; 1728 }; 1729 1730 struct dmub_fams2_stream_dynamic_state { 1731 uint64_t ref_tick; 1732 uint32_t cur_vtotal; 1733 uint16_t adjusted_allow_end_otg_vline; 1734 uint8_t pad[2]; 1735 struct dmub_optc_position ref_otg_pos; 1736 struct dmub_optc_position target_otg_pos; 1737 union { 1738 struct dmub_fams2_legacy_stream_dynamic_state legacy; 1739 struct dmub_fams2_subvp_stream_dynamic_state subvp; 1740 struct dmub_fams2_drr_stream_dynamic_state drr; 1741 } sub_state; 1742 }; 1743 1744 /* static stream state */ 1745 struct dmub_fams2_legacy_stream_static_state { 1746 uint8_t vactive_det_fill_delay_otg_vlines; 1747 uint8_t programming_delay_otg_vlines; 1748 }; 1749 1750 struct dmub_fams2_subvp_stream_static_state { 1751 uint16_t vratio_numerator; 1752 uint16_t vratio_denominator; 1753 uint16_t phantom_vtotal; 1754 uint16_t phantom_vactive; 1755 union { 1756 struct { 1757 uint8_t is_multi_planar : 1; 1758 uint8_t is_yuv420 : 1; 1759 } bits; 1760 uint8_t all; 1761 } config; 1762 uint8_t programming_delay_otg_vlines; 1763 uint8_t prefetch_to_mall_otg_vlines; 1764 uint8_t phantom_otg_inst; 1765 uint8_t phantom_pipe_mask; 1766 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1767 }; 1768 1769 struct dmub_fams2_drr_stream_static_state { 1770 uint16_t nom_stretched_vtotal; 1771 uint8_t programming_delay_otg_vlines; 1772 uint8_t only_stretch_if_required; 1773 uint8_t pad[2]; 1774 }; 1775 1776 struct dmub_fams2_stream_static_state { 1777 enum fams2_stream_type type; 1778 uint32_t otg_vline_time_ns; 1779 uint32_t otg_vline_time_ticks; 1780 uint16_t htotal; 1781 uint16_t vtotal; // nominal vtotal 1782 uint16_t vblank_start; 1783 uint16_t vblank_end; 1784 uint16_t max_vtotal; 1785 uint16_t allow_start_otg_vline; 1786 uint16_t allow_end_otg_vline; 1787 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1788 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1789 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 1790 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1791 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1792 union { 1793 struct { 1794 uint8_t is_drr: 1; // stream is DRR enabled 1795 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 1796 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1797 } bits; 1798 uint8_t all; 1799 } config; 1800 uint8_t otg_inst; 1801 uint8_t pipe_mask; // pipe mask for the whole config 1802 uint8_t num_planes; 1803 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1804 uint8_t pad[DMUB_MAX_PLANES % 4]; 1805 union { 1806 struct dmub_fams2_legacy_stream_static_state legacy; 1807 struct dmub_fams2_subvp_stream_static_state subvp; 1808 struct dmub_fams2_drr_stream_static_state drr; 1809 } sub_state; 1810 }; 1811 1812 /** 1813 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 1814 * p-state request to allow latency 1815 */ 1816 enum dmub_fams2_allow_delay_check_mode { 1817 /* No check for request to allow delay */ 1818 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 1819 /* Check for request to allow delay */ 1820 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 1821 /* Check for prepare to allow delay */ 1822 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 1823 }; 1824 1825 union dmub_fams2_global_feature_config { 1826 struct { 1827 uint32_t enable: 1; 1828 uint32_t enable_ppt_check: 1; 1829 uint32_t enable_stall_recovery: 1; 1830 uint32_t enable_debug: 1; 1831 uint32_t enable_offload_flip: 1; 1832 uint32_t enable_visual_confirm: 1; 1833 uint32_t allow_delay_check_mode: 2; 1834 uint32_t reserved: 24; 1835 } bits; 1836 uint32_t all; 1837 }; 1838 1839 struct dmub_cmd_fams2_global_config { 1840 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 1841 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 1842 uint32_t num_streams; 1843 union dmub_fams2_global_feature_config features; 1844 uint32_t recovery_timeout_us; 1845 uint32_t hwfq_flip_programming_delay_us; 1846 }; 1847 1848 union dmub_cmd_fams2_config { 1849 struct dmub_cmd_fams2_global_config global; 1850 struct dmub_fams2_stream_static_state stream; 1851 }; 1852 1853 /** 1854 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 1855 */ 1856 struct dmub_rb_cmd_fams2 { 1857 struct dmub_cmd_header header; 1858 union dmub_cmd_fams2_config config; 1859 }; 1860 1861 /** 1862 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1863 */ 1864 enum dmub_cmd_idle_opt_type { 1865 /** 1866 * DCN hardware restore. 1867 */ 1868 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1869 1870 /** 1871 * DCN hardware save. 1872 */ 1873 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1874 1875 /** 1876 * DCN hardware notify idle. 1877 */ 1878 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1879 }; 1880 1881 /** 1882 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1883 */ 1884 struct dmub_rb_cmd_idle_opt_dcn_restore { 1885 struct dmub_cmd_header header; /**< header */ 1886 }; 1887 1888 /** 1889 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1890 */ 1891 struct dmub_dcn_notify_idle_cntl_data { 1892 uint8_t driver_idle; 1893 uint8_t skip_otg_disable; 1894 uint8_t reserved[58]; 1895 }; 1896 1897 /** 1898 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1899 */ 1900 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1901 struct dmub_cmd_header header; /**< header */ 1902 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1903 }; 1904 1905 /** 1906 * struct dmub_clocks - Clock update notification. 1907 */ 1908 struct dmub_clocks { 1909 uint32_t dispclk_khz; /**< dispclk kHz */ 1910 uint32_t dppclk_khz; /**< dppclk kHz */ 1911 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1912 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1913 }; 1914 1915 /** 1916 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1917 */ 1918 enum dmub_cmd_clk_mgr_type { 1919 /** 1920 * Notify DMCUB of clock update. 1921 */ 1922 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1923 }; 1924 1925 /** 1926 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1927 */ 1928 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1929 struct dmub_cmd_header header; /**< header */ 1930 struct dmub_clocks clocks; /**< clock data */ 1931 }; 1932 1933 /** 1934 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1935 */ 1936 struct dmub_cmd_digx_encoder_control_data { 1937 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1938 }; 1939 1940 /** 1941 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1942 */ 1943 struct dmub_rb_cmd_digx_encoder_control { 1944 struct dmub_cmd_header header; /**< header */ 1945 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1946 }; 1947 1948 /** 1949 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1950 */ 1951 struct dmub_cmd_set_pixel_clock_data { 1952 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1953 }; 1954 1955 /** 1956 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1957 */ 1958 struct dmub_rb_cmd_set_pixel_clock { 1959 struct dmub_cmd_header header; /**< header */ 1960 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1961 }; 1962 1963 /** 1964 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1965 */ 1966 struct dmub_cmd_enable_disp_power_gating_data { 1967 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1968 }; 1969 1970 /** 1971 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1972 */ 1973 struct dmub_rb_cmd_enable_disp_power_gating { 1974 struct dmub_cmd_header header; /**< header */ 1975 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1976 }; 1977 1978 /** 1979 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1980 */ 1981 struct dmub_dig_transmitter_control_data_v1_7 { 1982 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1983 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1984 union { 1985 uint8_t digmode; /**< enum atom_encode_mode_def */ 1986 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1987 } mode_laneset; 1988 uint8_t lanenum; /**< Number of lanes */ 1989 union { 1990 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1991 } symclk_units; 1992 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1993 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1994 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1995 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1996 uint8_t reserved1; /**< For future use */ 1997 uint8_t reserved2[3]; /**< For future use */ 1998 uint32_t reserved3[11]; /**< For future use */ 1999 }; 2000 2001 /** 2002 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2003 */ 2004 union dmub_cmd_dig1_transmitter_control_data { 2005 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2006 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2007 }; 2008 2009 /** 2010 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2011 */ 2012 struct dmub_rb_cmd_dig1_transmitter_control { 2013 struct dmub_cmd_header header; /**< header */ 2014 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2015 }; 2016 2017 /** 2018 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2019 */ 2020 struct dmub_rb_cmd_domain_control_data { 2021 uint8_t inst : 6; /**< DOMAIN instance to control */ 2022 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2023 uint8_t reserved[3]; /**< Reserved for future use */ 2024 }; 2025 2026 /** 2027 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2028 */ 2029 struct dmub_rb_cmd_domain_control { 2030 struct dmub_cmd_header header; /**< header */ 2031 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2032 }; 2033 2034 /** 2035 * DPIA tunnel command parameters. 2036 */ 2037 struct dmub_cmd_dig_dpia_control_data { 2038 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2039 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2040 union { 2041 uint8_t digmode; /** enum atom_encode_mode_def */ 2042 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2043 } mode_laneset; 2044 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2045 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2046 uint8_t hpdsel; /** =0: HPD is not assigned */ 2047 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2048 uint8_t dpia_id; /** Index of DPIA */ 2049 uint8_t fec_rdy : 1; 2050 uint8_t reserved : 7; 2051 uint32_t reserved1; 2052 }; 2053 2054 /** 2055 * DMUB command for DPIA tunnel control. 2056 */ 2057 struct dmub_rb_cmd_dig1_dpia_control { 2058 struct dmub_cmd_header header; 2059 struct dmub_cmd_dig_dpia_control_data dpia_control; 2060 }; 2061 2062 /** 2063 * SET_CONFIG Command Payload 2064 */ 2065 struct set_config_cmd_payload { 2066 uint8_t msg_type; /* set config message type */ 2067 uint8_t msg_data; /* set config message data */ 2068 }; 2069 2070 /** 2071 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2072 */ 2073 struct dmub_cmd_set_config_control_data { 2074 struct set_config_cmd_payload cmd_pkt; 2075 uint8_t instance; /* DPIA instance */ 2076 uint8_t immed_status; /* Immediate status returned in case of error */ 2077 }; 2078 2079 /** 2080 * DMUB command structure for SET_CONFIG command. 2081 */ 2082 struct dmub_rb_cmd_set_config_access { 2083 struct dmub_cmd_header header; /* header */ 2084 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2085 }; 2086 2087 /** 2088 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2089 */ 2090 struct dmub_cmd_mst_alloc_slots_control_data { 2091 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2092 uint8_t instance; /* DPIA instance */ 2093 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2094 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2095 }; 2096 2097 /** 2098 * DMUB command structure for SET_ command. 2099 */ 2100 struct dmub_rb_cmd_set_mst_alloc_slots { 2101 struct dmub_cmd_header header; /* header */ 2102 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2103 }; 2104 2105 /** 2106 * DMUB command structure for DPIA HPD int enable control. 2107 */ 2108 struct dmub_rb_cmd_dpia_hpd_int_enable { 2109 struct dmub_cmd_header header; /* header */ 2110 uint32_t enable; /* dpia hpd interrupt enable */ 2111 }; 2112 2113 /** 2114 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2115 */ 2116 struct dmub_rb_cmd_dpphy_init { 2117 struct dmub_cmd_header header; /**< header */ 2118 uint8_t reserved[60]; /**< reserved bits */ 2119 }; 2120 2121 /** 2122 * enum dp_aux_request_action - DP AUX request command listing. 2123 * 2124 * 4 AUX request command bits are shifted to high nibble. 2125 */ 2126 enum dp_aux_request_action { 2127 /** I2C-over-AUX write request */ 2128 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2129 /** I2C-over-AUX read request */ 2130 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2131 /** I2C-over-AUX write status request */ 2132 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2133 /** I2C-over-AUX write request with MOT=1 */ 2134 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2135 /** I2C-over-AUX read request with MOT=1 */ 2136 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2137 /** I2C-over-AUX write status request with MOT=1 */ 2138 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2139 /** Native AUX write request */ 2140 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2141 /** Native AUX read request */ 2142 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2143 }; 2144 2145 /** 2146 * enum aux_return_code_type - DP AUX process return code listing. 2147 */ 2148 enum aux_return_code_type { 2149 /** AUX process succeeded */ 2150 AUX_RET_SUCCESS = 0, 2151 /** AUX process failed with unknown reason */ 2152 AUX_RET_ERROR_UNKNOWN, 2153 /** AUX process completed with invalid reply */ 2154 AUX_RET_ERROR_INVALID_REPLY, 2155 /** AUX process timed out */ 2156 AUX_RET_ERROR_TIMEOUT, 2157 /** HPD was low during AUX process */ 2158 AUX_RET_ERROR_HPD_DISCON, 2159 /** Failed to acquire AUX engine */ 2160 AUX_RET_ERROR_ENGINE_ACQUIRE, 2161 /** AUX request not supported */ 2162 AUX_RET_ERROR_INVALID_OPERATION, 2163 /** AUX process not available */ 2164 AUX_RET_ERROR_PROTOCOL_ERROR, 2165 }; 2166 2167 /** 2168 * enum aux_channel_type - DP AUX channel type listing. 2169 */ 2170 enum aux_channel_type { 2171 /** AUX thru Legacy DP AUX */ 2172 AUX_CHANNEL_LEGACY_DDC, 2173 /** AUX thru DPIA DP tunneling */ 2174 AUX_CHANNEL_DPIA 2175 }; 2176 2177 /** 2178 * struct aux_transaction_parameters - DP AUX request transaction data 2179 */ 2180 struct aux_transaction_parameters { 2181 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2182 uint8_t action; /**< enum dp_aux_request_action */ 2183 uint8_t length; /**< DP AUX request data length */ 2184 uint8_t reserved; /**< For future use */ 2185 uint32_t address; /**< DP AUX address */ 2186 uint8_t data[16]; /**< DP AUX write data */ 2187 }; 2188 2189 /** 2190 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2191 */ 2192 struct dmub_cmd_dp_aux_control_data { 2193 uint8_t instance; /**< AUX instance or DPIA instance */ 2194 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2195 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2196 uint8_t reserved0; /**< For future use */ 2197 uint16_t timeout; /**< timeout time in us */ 2198 uint16_t reserved1; /**< For future use */ 2199 enum aux_channel_type type; /**< enum aux_channel_type */ 2200 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2201 }; 2202 2203 /** 2204 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2205 */ 2206 struct dmub_rb_cmd_dp_aux_access { 2207 /** 2208 * Command header. 2209 */ 2210 struct dmub_cmd_header header; 2211 /** 2212 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2213 */ 2214 struct dmub_cmd_dp_aux_control_data aux_control; 2215 }; 2216 2217 /** 2218 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2219 */ 2220 struct dmub_rb_cmd_outbox1_enable { 2221 /** 2222 * Command header. 2223 */ 2224 struct dmub_cmd_header header; 2225 /** 2226 * enable: 0x0 -> disable outbox1 notification (default value) 2227 * 0x1 -> enable outbox1 notification 2228 */ 2229 uint32_t enable; 2230 }; 2231 2232 /* DP AUX Reply command - OutBox Cmd */ 2233 /** 2234 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2235 */ 2236 struct aux_reply_data { 2237 /** 2238 * Aux cmd 2239 */ 2240 uint8_t command; 2241 /** 2242 * Aux reply data length (max: 16 bytes) 2243 */ 2244 uint8_t length; 2245 /** 2246 * Alignment only 2247 */ 2248 uint8_t pad[2]; 2249 /** 2250 * Aux reply data 2251 */ 2252 uint8_t data[16]; 2253 }; 2254 2255 /** 2256 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2257 */ 2258 struct aux_reply_control_data { 2259 /** 2260 * Reserved for future use 2261 */ 2262 uint32_t handle; 2263 /** 2264 * Aux Instance 2265 */ 2266 uint8_t instance; 2267 /** 2268 * Aux transaction result: definition in enum aux_return_code_type 2269 */ 2270 uint8_t result; 2271 /** 2272 * Alignment only 2273 */ 2274 uint16_t pad; 2275 }; 2276 2277 /** 2278 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2279 */ 2280 struct dmub_rb_cmd_dp_aux_reply { 2281 /** 2282 * Command header. 2283 */ 2284 struct dmub_cmd_header header; 2285 /** 2286 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2287 */ 2288 struct aux_reply_control_data control; 2289 /** 2290 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2291 */ 2292 struct aux_reply_data reply_data; 2293 }; 2294 2295 /* DP HPD Notify command - OutBox Cmd */ 2296 /** 2297 * DP HPD Type 2298 */ 2299 enum dp_hpd_type { 2300 /** 2301 * Normal DP HPD 2302 */ 2303 DP_HPD = 0, 2304 /** 2305 * DP HPD short pulse 2306 */ 2307 DP_IRQ 2308 }; 2309 2310 /** 2311 * DP HPD Status 2312 */ 2313 enum dp_hpd_status { 2314 /** 2315 * DP_HPD status low 2316 */ 2317 DP_HPD_UNPLUG = 0, 2318 /** 2319 * DP_HPD status high 2320 */ 2321 DP_HPD_PLUG 2322 }; 2323 2324 /** 2325 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2326 */ 2327 struct dp_hpd_data { 2328 /** 2329 * DP HPD instance 2330 */ 2331 uint8_t instance; 2332 /** 2333 * HPD type 2334 */ 2335 uint8_t hpd_type; 2336 /** 2337 * HPD status: only for type: DP_HPD to indicate status 2338 */ 2339 uint8_t hpd_status; 2340 /** 2341 * Alignment only 2342 */ 2343 uint8_t pad; 2344 }; 2345 2346 /** 2347 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2348 */ 2349 struct dmub_rb_cmd_dp_hpd_notify { 2350 /** 2351 * Command header. 2352 */ 2353 struct dmub_cmd_header header; 2354 /** 2355 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2356 */ 2357 struct dp_hpd_data hpd_data; 2358 }; 2359 2360 /** 2361 * Definition of a SET_CONFIG reply from DPOA. 2362 */ 2363 enum set_config_status { 2364 SET_CONFIG_PENDING = 0, 2365 SET_CONFIG_ACK_RECEIVED, 2366 SET_CONFIG_RX_TIMEOUT, 2367 SET_CONFIG_UNKNOWN_ERROR, 2368 }; 2369 2370 /** 2371 * Definition of a set_config reply 2372 */ 2373 struct set_config_reply_control_data { 2374 uint8_t instance; /* DPIA Instance */ 2375 uint8_t status; /* Set Config reply */ 2376 uint16_t pad; /* Alignment */ 2377 }; 2378 2379 /** 2380 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2381 */ 2382 struct dmub_rb_cmd_dp_set_config_reply { 2383 struct dmub_cmd_header header; 2384 struct set_config_reply_control_data set_config_reply_control; 2385 }; 2386 2387 /** 2388 * Definition of a DPIA notification header 2389 */ 2390 struct dpia_notification_header { 2391 uint8_t instance; /**< DPIA Instance */ 2392 uint8_t reserved[3]; 2393 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2394 }; 2395 2396 /** 2397 * Definition of the common data struct of DPIA notification 2398 */ 2399 struct dpia_notification_common { 2400 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2401 - sizeof(struct dpia_notification_header)]; 2402 }; 2403 2404 /** 2405 * Definition of a DPIA notification data 2406 */ 2407 struct dpia_bw_allocation_notify_data { 2408 union { 2409 struct { 2410 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2411 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2412 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2413 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2414 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2415 uint16_t reserved: 11; /**< Reserved */ 2416 } bits; 2417 2418 uint16_t flags; 2419 }; 2420 2421 uint8_t cm_id; /**< CM ID */ 2422 uint8_t group_id; /**< Group ID */ 2423 uint8_t granularity; /**< BW Allocation Granularity */ 2424 uint8_t estimated_bw; /**< Estimated_BW */ 2425 uint8_t allocated_bw; /**< Allocated_BW */ 2426 uint8_t reserved; 2427 }; 2428 2429 /** 2430 * union dpia_notify_data_type - DPIA Notification in Outbox command 2431 */ 2432 union dpia_notification_data { 2433 /** 2434 * DPIA Notification for common data struct 2435 */ 2436 struct dpia_notification_common common_data; 2437 2438 /** 2439 * DPIA Notification for DP BW Allocation support 2440 */ 2441 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2442 }; 2443 2444 /** 2445 * Definition of a DPIA notification payload 2446 */ 2447 struct dpia_notification_payload { 2448 struct dpia_notification_header header; 2449 union dpia_notification_data data; /**< DPIA notification payload data */ 2450 }; 2451 2452 /** 2453 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2454 */ 2455 struct dmub_rb_cmd_dpia_notification { 2456 struct dmub_cmd_header header; /**< DPIA notification header */ 2457 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2458 }; 2459 2460 /** 2461 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2462 */ 2463 struct dmub_cmd_hpd_state_query_data { 2464 uint8_t instance; /**< HPD instance or DPIA instance */ 2465 uint8_t result; /**< For returning HPD state */ 2466 uint16_t pad; /** < Alignment */ 2467 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2468 enum aux_return_code_type status; /**< for returning the status of command */ 2469 }; 2470 2471 /** 2472 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2473 */ 2474 struct dmub_rb_cmd_query_hpd_state { 2475 /** 2476 * Command header. 2477 */ 2478 struct dmub_cmd_header header; 2479 /** 2480 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2481 */ 2482 struct dmub_cmd_hpd_state_query_data data; 2483 }; 2484 2485 /** 2486 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2487 */ 2488 struct dmub_rb_cmd_hpd_sense_notify_data { 2489 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2490 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2491 }; 2492 2493 /** 2494 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2495 */ 2496 struct dmub_rb_cmd_hpd_sense_notify { 2497 struct dmub_cmd_header header; /**< header */ 2498 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2499 }; 2500 2501 /* 2502 * Command IDs should be treated as stable ABI. 2503 * Do not reuse or modify IDs. 2504 */ 2505 2506 /** 2507 * PSR command sub-types. 2508 */ 2509 enum dmub_cmd_psr_type { 2510 /** 2511 * Set PSR version support. 2512 */ 2513 DMUB_CMD__PSR_SET_VERSION = 0, 2514 /** 2515 * Copy driver-calculated parameters to PSR state. 2516 */ 2517 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2518 /** 2519 * Enable PSR. 2520 */ 2521 DMUB_CMD__PSR_ENABLE = 2, 2522 2523 /** 2524 * Disable PSR. 2525 */ 2526 DMUB_CMD__PSR_DISABLE = 3, 2527 2528 /** 2529 * Set PSR level. 2530 * PSR level is a 16-bit value dicated by driver that 2531 * will enable/disable different functionality. 2532 */ 2533 DMUB_CMD__PSR_SET_LEVEL = 4, 2534 2535 /** 2536 * Forces PSR enabled until an explicit PSR disable call. 2537 */ 2538 DMUB_CMD__PSR_FORCE_STATIC = 5, 2539 /** 2540 * Set vtotal in psr active for FreeSync PSR. 2541 */ 2542 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2543 /** 2544 * Set PSR power option 2545 */ 2546 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2547 }; 2548 2549 /** 2550 * Different PSR residency modes. 2551 * Different modes change the definition of PSR residency. 2552 */ 2553 enum psr_residency_mode { 2554 PSR_RESIDENCY_MODE_PHY = 0, 2555 PSR_RESIDENCY_MODE_ALPM, 2556 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2557 /* Do not add below. */ 2558 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2559 }; 2560 2561 enum dmub_cmd_fams_type { 2562 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2563 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2564 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2565 /** 2566 * For SubVP set manual trigger in FW because it 2567 * triggers DRR_UPDATE_PENDING which SubVP relies 2568 * on (for any SubVP cases that use a DRR display) 2569 */ 2570 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2571 DMUB_CMD__FAMS2_CONFIG = 4, 2572 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2573 DMUB_CMD__FAMS2_FLIP = 6, 2574 }; 2575 2576 /** 2577 * PSR versions. 2578 */ 2579 enum psr_version { 2580 /** 2581 * PSR version 1. 2582 */ 2583 PSR_VERSION_1 = 0, 2584 /** 2585 * Freesync PSR SU. 2586 */ 2587 PSR_VERSION_SU_1 = 1, 2588 /** 2589 * PSR not supported. 2590 */ 2591 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2592 }; 2593 2594 /** 2595 * PHY Link rate for DP. 2596 */ 2597 enum phy_link_rate { 2598 /** 2599 * not supported. 2600 */ 2601 PHY_RATE_UNKNOWN = 0, 2602 /** 2603 * Rate_1 (RBR) - 1.62 Gbps/Lane 2604 */ 2605 PHY_RATE_162 = 1, 2606 /** 2607 * Rate_2 - 2.16 Gbps/Lane 2608 */ 2609 PHY_RATE_216 = 2, 2610 /** 2611 * Rate_3 - 2.43 Gbps/Lane 2612 */ 2613 PHY_RATE_243 = 3, 2614 /** 2615 * Rate_4 (HBR) - 2.70 Gbps/Lane 2616 */ 2617 PHY_RATE_270 = 4, 2618 /** 2619 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2620 */ 2621 PHY_RATE_324 = 5, 2622 /** 2623 * Rate_6 - 4.32 Gbps/Lane 2624 */ 2625 PHY_RATE_432 = 6, 2626 /** 2627 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2628 */ 2629 PHY_RATE_540 = 7, 2630 /** 2631 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2632 */ 2633 PHY_RATE_810 = 8, 2634 /** 2635 * UHBR10 - 10.0 Gbps/Lane 2636 */ 2637 PHY_RATE_1000 = 9, 2638 /** 2639 * UHBR13.5 - 13.5 Gbps/Lane 2640 */ 2641 PHY_RATE_1350 = 10, 2642 /** 2643 * UHBR10 - 20.0 Gbps/Lane 2644 */ 2645 PHY_RATE_2000 = 11, 2646 2647 PHY_RATE_675 = 12, 2648 /** 2649 * Rate 12 - 6.75 Gbps/Lane 2650 */ 2651 }; 2652 2653 /** 2654 * enum dmub_phy_fsm_state - PHY FSM states. 2655 * PHY FSM state to transit to during PSR enable/disable. 2656 */ 2657 enum dmub_phy_fsm_state { 2658 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2659 DMUB_PHY_FSM_RESET, 2660 DMUB_PHY_FSM_RESET_RELEASED, 2661 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2662 DMUB_PHY_FSM_INITIALIZED, 2663 DMUB_PHY_FSM_CALIBRATED, 2664 DMUB_PHY_FSM_CALIBRATED_LP, 2665 DMUB_PHY_FSM_CALIBRATED_PG, 2666 DMUB_PHY_FSM_POWER_DOWN, 2667 DMUB_PHY_FSM_PLL_EN, 2668 DMUB_PHY_FSM_TX_EN, 2669 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2670 DMUB_PHY_FSM_FAST_LP, 2671 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2672 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2673 DMUB_PHY_FSM_P2_PLL_OFF, 2674 DMUB_PHY_FSM_P2_PLL_ON, 2675 }; 2676 2677 /** 2678 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2679 */ 2680 struct dmub_cmd_psr_copy_settings_data { 2681 /** 2682 * Flags that can be set by driver to change some PSR behaviour. 2683 */ 2684 union dmub_psr_debug_flags debug; 2685 /** 2686 * 16-bit value dicated by driver that will enable/disable different functionality. 2687 */ 2688 uint16_t psr_level; 2689 /** 2690 * DPP HW instance. 2691 */ 2692 uint8_t dpp_inst; 2693 /** 2694 * MPCC HW instance. 2695 * Not used in dmub fw, 2696 * dmub fw will get active opp by reading odm registers. 2697 */ 2698 uint8_t mpcc_inst; 2699 /** 2700 * OPP HW instance. 2701 * Not used in dmub fw, 2702 * dmub fw will get active opp by reading odm registers. 2703 */ 2704 uint8_t opp_inst; 2705 /** 2706 * OTG HW instance. 2707 */ 2708 uint8_t otg_inst; 2709 /** 2710 * DIG FE HW instance. 2711 */ 2712 uint8_t digfe_inst; 2713 /** 2714 * DIG BE HW instance. 2715 */ 2716 uint8_t digbe_inst; 2717 /** 2718 * DP PHY HW instance. 2719 */ 2720 uint8_t dpphy_inst; 2721 /** 2722 * AUX HW instance. 2723 */ 2724 uint8_t aux_inst; 2725 /** 2726 * Determines if SMU optimzations are enabled/disabled. 2727 */ 2728 uint8_t smu_optimizations_en; 2729 /** 2730 * Unused. 2731 * TODO: Remove. 2732 */ 2733 uint8_t frame_delay; 2734 /** 2735 * If RFB setup time is greater than the total VBLANK time, 2736 * it is not possible for the sink to capture the video frame 2737 * in the same frame the SDP is sent. In this case, 2738 * the frame capture indication bit should be set and an extra 2739 * static frame should be transmitted to the sink. 2740 */ 2741 uint8_t frame_cap_ind; 2742 /** 2743 * Granularity of Y offset supported by sink. 2744 */ 2745 uint8_t su_y_granularity; 2746 /** 2747 * Indicates whether sink should start capturing 2748 * immediately following active scan line, 2749 * or starting with the 2nd active scan line. 2750 */ 2751 uint8_t line_capture_indication; 2752 /** 2753 * Multi-display optimizations are implemented on certain ASICs. 2754 */ 2755 uint8_t multi_disp_optimizations_en; 2756 /** 2757 * The last possible line SDP may be transmitted without violating 2758 * the RFB setup time or entering the active video frame. 2759 */ 2760 uint16_t init_sdp_deadline; 2761 /** 2762 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2763 */ 2764 uint8_t rate_control_caps ; 2765 /* 2766 * Force PSRSU always doing full frame update 2767 */ 2768 uint8_t force_ffu_mode; 2769 /** 2770 * Length of each horizontal line in us. 2771 */ 2772 uint32_t line_time_in_us; 2773 /** 2774 * FEC enable status in driver 2775 */ 2776 uint8_t fec_enable_status; 2777 /** 2778 * FEC re-enable delay when PSR exit. 2779 * unit is 100us, range form 0~255(0xFF). 2780 */ 2781 uint8_t fec_enable_delay_in100us; 2782 /** 2783 * PSR control version. 2784 */ 2785 uint8_t cmd_version; 2786 /** 2787 * Panel Instance. 2788 * Panel instance to identify which psr_state to use 2789 * Currently the support is only for 0 or 1 2790 */ 2791 uint8_t panel_inst; 2792 /* 2793 * DSC enable status in driver 2794 */ 2795 uint8_t dsc_enable_status; 2796 /* 2797 * Use FSM state for PSR power up/down 2798 */ 2799 uint8_t use_phy_fsm; 2800 /** 2801 * frame delay for frame re-lock 2802 */ 2803 uint8_t relock_delay_frame_cnt; 2804 /** 2805 * esd recovery indicate. 2806 */ 2807 uint8_t esd_recovery; 2808 /** 2809 * DSC Slice height. 2810 */ 2811 uint16_t dsc_slice_height; 2812 /** 2813 * Some panels request main link off before xth vertical line 2814 */ 2815 uint16_t poweroff_before_vertical_line; 2816 }; 2817 2818 /** 2819 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2820 */ 2821 struct dmub_rb_cmd_psr_copy_settings { 2822 /** 2823 * Command header. 2824 */ 2825 struct dmub_cmd_header header; 2826 /** 2827 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2828 */ 2829 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2830 }; 2831 2832 /** 2833 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2834 */ 2835 struct dmub_cmd_psr_set_level_data { 2836 /** 2837 * 16-bit value dicated by driver that will enable/disable different functionality. 2838 */ 2839 uint16_t psr_level; 2840 /** 2841 * PSR control version. 2842 */ 2843 uint8_t cmd_version; 2844 /** 2845 * Panel Instance. 2846 * Panel instance to identify which psr_state to use 2847 * Currently the support is only for 0 or 1 2848 */ 2849 uint8_t panel_inst; 2850 }; 2851 2852 /** 2853 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2854 */ 2855 struct dmub_rb_cmd_psr_set_level { 2856 /** 2857 * Command header. 2858 */ 2859 struct dmub_cmd_header header; 2860 /** 2861 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2862 */ 2863 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2864 }; 2865 2866 struct dmub_rb_cmd_psr_enable_data { 2867 /** 2868 * PSR control version. 2869 */ 2870 uint8_t cmd_version; 2871 /** 2872 * Panel Instance. 2873 * Panel instance to identify which psr_state to use 2874 * Currently the support is only for 0 or 1 2875 */ 2876 uint8_t panel_inst; 2877 /** 2878 * Phy state to enter. 2879 * Values to use are defined in dmub_phy_fsm_state 2880 */ 2881 uint8_t phy_fsm_state; 2882 /** 2883 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2884 * Set this using enum phy_link_rate. 2885 * This does not support HDMI/DP2 for now. 2886 */ 2887 uint8_t phy_rate; 2888 }; 2889 2890 /** 2891 * Definition of a DMUB_CMD__PSR_ENABLE command. 2892 * PSR enable/disable is controlled using the sub_type. 2893 */ 2894 struct dmub_rb_cmd_psr_enable { 2895 /** 2896 * Command header. 2897 */ 2898 struct dmub_cmd_header header; 2899 2900 struct dmub_rb_cmd_psr_enable_data data; 2901 }; 2902 2903 /** 2904 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2905 */ 2906 struct dmub_cmd_psr_set_version_data { 2907 /** 2908 * PSR version that FW should implement. 2909 */ 2910 enum psr_version version; 2911 /** 2912 * PSR control version. 2913 */ 2914 uint8_t cmd_version; 2915 /** 2916 * Panel Instance. 2917 * Panel instance to identify which psr_state to use 2918 * Currently the support is only for 0 or 1 2919 */ 2920 uint8_t panel_inst; 2921 /** 2922 * Explicit padding to 4 byte boundary. 2923 */ 2924 uint8_t pad[2]; 2925 }; 2926 2927 /** 2928 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2929 */ 2930 struct dmub_rb_cmd_psr_set_version { 2931 /** 2932 * Command header. 2933 */ 2934 struct dmub_cmd_header header; 2935 /** 2936 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2937 */ 2938 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2939 }; 2940 2941 struct dmub_cmd_psr_force_static_data { 2942 /** 2943 * PSR control version. 2944 */ 2945 uint8_t cmd_version; 2946 /** 2947 * Panel Instance. 2948 * Panel instance to identify which psr_state to use 2949 * Currently the support is only for 0 or 1 2950 */ 2951 uint8_t panel_inst; 2952 /** 2953 * Explicit padding to 4 byte boundary. 2954 */ 2955 uint8_t pad[2]; 2956 }; 2957 2958 /** 2959 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2960 */ 2961 struct dmub_rb_cmd_psr_force_static { 2962 /** 2963 * Command header. 2964 */ 2965 struct dmub_cmd_header header; 2966 /** 2967 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2968 */ 2969 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2970 }; 2971 2972 /** 2973 * PSR SU debug flags. 2974 */ 2975 union dmub_psr_su_debug_flags { 2976 /** 2977 * PSR SU debug flags. 2978 */ 2979 struct { 2980 /** 2981 * Update dirty rect in SW only. 2982 */ 2983 uint8_t update_dirty_rect_only : 1; 2984 /** 2985 * Reset the cursor/plane state before processing the call. 2986 */ 2987 uint8_t reset_state : 1; 2988 } bitfields; 2989 2990 /** 2991 * Union for debug flags. 2992 */ 2993 uint32_t u32All; 2994 }; 2995 2996 /** 2997 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2998 * This triggers a selective update for PSR SU. 2999 */ 3000 struct dmub_cmd_update_dirty_rect_data { 3001 /** 3002 * Dirty rects from OS. 3003 */ 3004 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3005 /** 3006 * PSR SU debug flags. 3007 */ 3008 union dmub_psr_su_debug_flags debug_flags; 3009 /** 3010 * OTG HW instance. 3011 */ 3012 uint8_t pipe_idx; 3013 /** 3014 * Number of dirty rects. 3015 */ 3016 uint8_t dirty_rect_count; 3017 /** 3018 * PSR control version. 3019 */ 3020 uint8_t cmd_version; 3021 /** 3022 * Panel Instance. 3023 * Panel instance to identify which psr_state to use 3024 * Currently the support is only for 0 or 1 3025 */ 3026 uint8_t panel_inst; 3027 /** 3028 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3029 */ 3030 uint16_t coasting_vtotal_high; 3031 /** 3032 * Explicit padding to 4 byte boundary. 3033 */ 3034 uint8_t pad[2]; 3035 }; 3036 3037 /** 3038 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3039 */ 3040 struct dmub_rb_cmd_update_dirty_rect { 3041 /** 3042 * Command header. 3043 */ 3044 struct dmub_cmd_header header; 3045 /** 3046 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3047 */ 3048 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3049 }; 3050 3051 /** 3052 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3053 */ 3054 union dmub_reg_cursor_control_cfg { 3055 struct { 3056 uint32_t cur_enable: 1; 3057 uint32_t reser0: 3; 3058 uint32_t cur_2x_magnify: 1; 3059 uint32_t reser1: 3; 3060 uint32_t mode: 3; 3061 uint32_t reser2: 5; 3062 uint32_t pitch: 2; 3063 uint32_t reser3: 6; 3064 uint32_t line_per_chunk: 5; 3065 uint32_t reser4: 3; 3066 } bits; 3067 uint32_t raw; 3068 }; 3069 struct dmub_cursor_position_cache_hubp { 3070 union dmub_reg_cursor_control_cfg cur_ctl; 3071 union dmub_reg_position_cfg { 3072 struct { 3073 uint32_t cur_x_pos: 16; 3074 uint32_t cur_y_pos: 16; 3075 } bits; 3076 uint32_t raw; 3077 } position; 3078 union dmub_reg_hot_spot_cfg { 3079 struct { 3080 uint32_t hot_x: 16; 3081 uint32_t hot_y: 16; 3082 } bits; 3083 uint32_t raw; 3084 } hot_spot; 3085 union dmub_reg_dst_offset_cfg { 3086 struct { 3087 uint32_t dst_x_offset: 13; 3088 uint32_t reserved: 19; 3089 } bits; 3090 uint32_t raw; 3091 } dst_offset; 3092 }; 3093 3094 union dmub_reg_cur0_control_cfg { 3095 struct { 3096 uint32_t cur0_enable: 1; 3097 uint32_t expansion_mode: 1; 3098 uint32_t reser0: 1; 3099 uint32_t cur0_rom_en: 1; 3100 uint32_t mode: 3; 3101 uint32_t reserved: 25; 3102 } bits; 3103 uint32_t raw; 3104 }; 3105 struct dmub_cursor_position_cache_dpp { 3106 union dmub_reg_cur0_control_cfg cur0_ctl; 3107 }; 3108 struct dmub_cursor_position_cfg { 3109 struct dmub_cursor_position_cache_hubp pHubp; 3110 struct dmub_cursor_position_cache_dpp pDpp; 3111 uint8_t pipe_idx; 3112 /* 3113 * Padding is required. To be 4 Bytes Aligned. 3114 */ 3115 uint8_t padding[3]; 3116 }; 3117 3118 struct dmub_cursor_attribute_cache_hubp { 3119 uint32_t SURFACE_ADDR_HIGH; 3120 uint32_t SURFACE_ADDR; 3121 union dmub_reg_cursor_control_cfg cur_ctl; 3122 union dmub_reg_cursor_size_cfg { 3123 struct { 3124 uint32_t width: 16; 3125 uint32_t height: 16; 3126 } bits; 3127 uint32_t raw; 3128 } size; 3129 union dmub_reg_cursor_settings_cfg { 3130 struct { 3131 uint32_t dst_y_offset: 8; 3132 uint32_t chunk_hdl_adjust: 2; 3133 uint32_t reserved: 22; 3134 } bits; 3135 uint32_t raw; 3136 } settings; 3137 }; 3138 struct dmub_cursor_attribute_cache_dpp { 3139 union dmub_reg_cur0_control_cfg cur0_ctl; 3140 }; 3141 struct dmub_cursor_attributes_cfg { 3142 struct dmub_cursor_attribute_cache_hubp aHubp; 3143 struct dmub_cursor_attribute_cache_dpp aDpp; 3144 }; 3145 3146 struct dmub_cmd_update_cursor_payload0 { 3147 /** 3148 * Cursor dirty rects. 3149 */ 3150 struct dmub_rect cursor_rect; 3151 /** 3152 * PSR SU debug flags. 3153 */ 3154 union dmub_psr_su_debug_flags debug_flags; 3155 /** 3156 * Cursor enable/disable. 3157 */ 3158 uint8_t enable; 3159 /** 3160 * OTG HW instance. 3161 */ 3162 uint8_t pipe_idx; 3163 /** 3164 * PSR control version. 3165 */ 3166 uint8_t cmd_version; 3167 /** 3168 * Panel Instance. 3169 * Panel instance to identify which psr_state to use 3170 * Currently the support is only for 0 or 1 3171 */ 3172 uint8_t panel_inst; 3173 /** 3174 * Cursor Position Register. 3175 * Registers contains Hubp & Dpp modules 3176 */ 3177 struct dmub_cursor_position_cfg position_cfg; 3178 }; 3179 3180 struct dmub_cmd_update_cursor_payload1 { 3181 struct dmub_cursor_attributes_cfg attribute_cfg; 3182 }; 3183 3184 union dmub_cmd_update_cursor_info_data { 3185 struct dmub_cmd_update_cursor_payload0 payload0; 3186 struct dmub_cmd_update_cursor_payload1 payload1; 3187 }; 3188 /** 3189 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3190 */ 3191 struct dmub_rb_cmd_update_cursor_info { 3192 /** 3193 * Command header. 3194 */ 3195 struct dmub_cmd_header header; 3196 /** 3197 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3198 */ 3199 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3200 }; 3201 3202 /** 3203 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3204 */ 3205 struct dmub_cmd_psr_set_vtotal_data { 3206 /** 3207 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3208 */ 3209 uint16_t psr_vtotal_idle; 3210 /** 3211 * PSR control version. 3212 */ 3213 uint8_t cmd_version; 3214 /** 3215 * Panel Instance. 3216 * Panel instance to identify which psr_state to use 3217 * Currently the support is only for 0 or 1 3218 */ 3219 uint8_t panel_inst; 3220 /* 3221 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3222 */ 3223 uint16_t psr_vtotal_su; 3224 /** 3225 * Explicit padding to 4 byte boundary. 3226 */ 3227 uint8_t pad2[2]; 3228 }; 3229 3230 /** 3231 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3232 */ 3233 struct dmub_rb_cmd_psr_set_vtotal { 3234 /** 3235 * Command header. 3236 */ 3237 struct dmub_cmd_header header; 3238 /** 3239 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3240 */ 3241 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3242 }; 3243 3244 /** 3245 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3246 */ 3247 struct dmub_cmd_psr_set_power_opt_data { 3248 /** 3249 * PSR control version. 3250 */ 3251 uint8_t cmd_version; 3252 /** 3253 * Panel Instance. 3254 * Panel instance to identify which psr_state to use 3255 * Currently the support is only for 0 or 1 3256 */ 3257 uint8_t panel_inst; 3258 /** 3259 * Explicit padding to 4 byte boundary. 3260 */ 3261 uint8_t pad[2]; 3262 /** 3263 * PSR power option 3264 */ 3265 uint32_t power_opt; 3266 }; 3267 3268 /** 3269 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3270 */ 3271 struct dmub_rb_cmd_psr_set_power_opt { 3272 /** 3273 * Command header. 3274 */ 3275 struct dmub_cmd_header header; 3276 /** 3277 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3278 */ 3279 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3280 }; 3281 3282 /** 3283 * Definition of Replay Residency GPINT command. 3284 * Bit[0] - Residency mode for Revision 0 3285 * Bit[1] - Enable/Disable state 3286 * Bit[2-3] - Revision number 3287 * Bit[4-7] - Residency mode for Revision 1 3288 * Bit[8] - Panel instance 3289 * Bit[9-15] - Reserved 3290 */ 3291 3292 enum pr_residency_mode { 3293 PR_RESIDENCY_MODE_PHY = 0x0, 3294 PR_RESIDENCY_MODE_ALPM, 3295 PR_RESIDENCY_MODE_IPS2, 3296 PR_RESIDENCY_MODE_FRAME_CNT, 3297 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3298 }; 3299 3300 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3301 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3302 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3303 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3304 3305 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3306 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3307 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3308 3309 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3310 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3311 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3312 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3313 3314 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3315 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3316 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3317 3318 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3319 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3320 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3321 3322 /** 3323 * Definition of a replay_state. 3324 */ 3325 enum replay_state { 3326 REPLAY_STATE_0 = 0x0, 3327 REPLAY_STATE_1 = 0x10, 3328 REPLAY_STATE_1A = 0x11, 3329 REPLAY_STATE_2 = 0x20, 3330 REPLAY_STATE_2A = 0x21, 3331 REPLAY_STATE_3 = 0x30, 3332 REPLAY_STATE_3INIT = 0x31, 3333 REPLAY_STATE_4 = 0x40, 3334 REPLAY_STATE_4A = 0x41, 3335 REPLAY_STATE_4B = 0x42, 3336 REPLAY_STATE_4C = 0x43, 3337 REPLAY_STATE_4D = 0x44, 3338 REPLAY_STATE_4E = 0x45, 3339 REPLAY_STATE_4B_LOCKED = 0x4A, 3340 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3341 REPLAY_STATE_5 = 0x50, 3342 REPLAY_STATE_5A = 0x51, 3343 REPLAY_STATE_5B = 0x52, 3344 REPLAY_STATE_5A_LOCKED = 0x5A, 3345 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3346 REPLAY_STATE_6 = 0x60, 3347 REPLAY_STATE_6A = 0x61, 3348 REPLAY_STATE_6B = 0x62, 3349 REPLAY_STATE_INVALID = 0xFF, 3350 }; 3351 3352 /** 3353 * Replay command sub-types. 3354 */ 3355 enum dmub_cmd_replay_type { 3356 /** 3357 * Copy driver-calculated parameters to REPLAY state. 3358 */ 3359 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3360 /** 3361 * Enable REPLAY. 3362 */ 3363 DMUB_CMD__REPLAY_ENABLE = 1, 3364 /** 3365 * Set Replay power option. 3366 */ 3367 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3368 /** 3369 * Set coasting vtotal. 3370 */ 3371 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3372 /** 3373 * Set power opt and coasting vtotal. 3374 */ 3375 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3376 /** 3377 * Set disabled iiming sync. 3378 */ 3379 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3380 /** 3381 * Set Residency Frameupdate Timer. 3382 */ 3383 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3384 /** 3385 * Set pseudo vtotal 3386 */ 3387 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3388 /** 3389 * Set adaptive sync sdp enabled 3390 */ 3391 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3392 /** 3393 * Set Replay General command. 3394 */ 3395 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3396 }; 3397 3398 /** 3399 * Replay general command sub-types. 3400 */ 3401 enum dmub_cmd_replay_general_subtype { 3402 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3403 /** 3404 * TODO: For backward compatible, allow new command only. 3405 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3406 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3407 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3408 */ 3409 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3410 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3411 }; 3412 3413 /** 3414 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3415 */ 3416 struct dmub_cmd_replay_copy_settings_data { 3417 /** 3418 * Flags that can be set by driver to change some replay behaviour. 3419 */ 3420 union replay_debug_flags debug; 3421 3422 /** 3423 * @flags: Flags used to determine feature functionality. 3424 */ 3425 union replay_hw_flags flags; 3426 3427 /** 3428 * DPP HW instance. 3429 */ 3430 uint8_t dpp_inst; 3431 /** 3432 * OTG HW instance. 3433 */ 3434 uint8_t otg_inst; 3435 /** 3436 * DIG FE HW instance. 3437 */ 3438 uint8_t digfe_inst; 3439 /** 3440 * DIG BE HW instance. 3441 */ 3442 uint8_t digbe_inst; 3443 /** 3444 * AUX HW instance. 3445 */ 3446 uint8_t aux_inst; 3447 /** 3448 * Panel Instance. 3449 * Panel isntance to identify which psr_state to use 3450 * Currently the support is only for 0 or 1 3451 */ 3452 uint8_t panel_inst; 3453 /** 3454 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3455 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3456 */ 3457 uint8_t pixel_deviation_per_line; 3458 /** 3459 * @max_deviation_line: The max number of deviation line that can keep the timing 3460 * synchronized between the Source and Sink during Replay normal sleep mode. 3461 */ 3462 uint8_t max_deviation_line; 3463 /** 3464 * Length of each horizontal line in ns. 3465 */ 3466 uint32_t line_time_in_ns; 3467 /** 3468 * PHY instance. 3469 */ 3470 uint8_t dpphy_inst; 3471 /** 3472 * Determines if SMU optimzations are enabled/disabled. 3473 */ 3474 uint8_t smu_optimizations_en; 3475 /** 3476 * Determines if timing sync are enabled/disabled. 3477 */ 3478 uint8_t replay_timing_sync_supported; 3479 /* 3480 * Use FSM state for Replay power up/down 3481 */ 3482 uint8_t use_phy_fsm; 3483 }; 3484 3485 /** 3486 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3487 */ 3488 struct dmub_rb_cmd_replay_copy_settings { 3489 /** 3490 * Command header. 3491 */ 3492 struct dmub_cmd_header header; 3493 /** 3494 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3495 */ 3496 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3497 }; 3498 3499 /** 3500 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3501 */ 3502 enum replay_enable { 3503 /** 3504 * Disable REPLAY. 3505 */ 3506 REPLAY_DISABLE = 0, 3507 /** 3508 * Enable REPLAY. 3509 */ 3510 REPLAY_ENABLE = 1, 3511 }; 3512 3513 /** 3514 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3515 */ 3516 struct dmub_rb_cmd_replay_enable_data { 3517 /** 3518 * Replay enable or disable. 3519 */ 3520 uint8_t enable; 3521 /** 3522 * Panel Instance. 3523 * Panel isntance to identify which replay_state to use 3524 * Currently the support is only for 0 or 1 3525 */ 3526 uint8_t panel_inst; 3527 /** 3528 * Phy state to enter. 3529 * Values to use are defined in dmub_phy_fsm_state 3530 */ 3531 uint8_t phy_fsm_state; 3532 /** 3533 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3534 * Set this using enum phy_link_rate. 3535 * This does not support HDMI/DP2 for now. 3536 */ 3537 uint8_t phy_rate; 3538 }; 3539 3540 /** 3541 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3542 * Replay enable/disable is controlled using action in data. 3543 */ 3544 struct dmub_rb_cmd_replay_enable { 3545 /** 3546 * Command header. 3547 */ 3548 struct dmub_cmd_header header; 3549 3550 struct dmub_rb_cmd_replay_enable_data data; 3551 }; 3552 3553 /** 3554 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3555 */ 3556 struct dmub_cmd_replay_set_power_opt_data { 3557 /** 3558 * Panel Instance. 3559 * Panel isntance to identify which replay_state to use 3560 * Currently the support is only for 0 or 1 3561 */ 3562 uint8_t panel_inst; 3563 /** 3564 * Explicit padding to 4 byte boundary. 3565 */ 3566 uint8_t pad[3]; 3567 /** 3568 * REPLAY power option 3569 */ 3570 uint32_t power_opt; 3571 }; 3572 3573 /** 3574 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3575 */ 3576 struct dmub_cmd_replay_set_timing_sync_data { 3577 /** 3578 * Panel Instance. 3579 * Panel isntance to identify which replay_state to use 3580 * Currently the support is only for 0 or 1 3581 */ 3582 uint8_t panel_inst; 3583 /** 3584 * REPLAY set_timing_sync 3585 */ 3586 uint8_t timing_sync_supported; 3587 /** 3588 * Explicit padding to 4 byte boundary. 3589 */ 3590 uint8_t pad[2]; 3591 }; 3592 3593 /** 3594 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3595 */ 3596 struct dmub_cmd_replay_set_pseudo_vtotal { 3597 /** 3598 * Panel Instance. 3599 * Panel isntance to identify which replay_state to use 3600 * Currently the support is only for 0 or 1 3601 */ 3602 uint8_t panel_inst; 3603 /** 3604 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3605 */ 3606 uint16_t vtotal; 3607 /** 3608 * Explicit padding to 4 byte boundary. 3609 */ 3610 uint8_t pad; 3611 }; 3612 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3613 /** 3614 * Panel Instance. 3615 * Panel isntance to identify which replay_state to use 3616 * Currently the support is only for 0 or 1 3617 */ 3618 uint8_t panel_inst; 3619 /** 3620 * enabled: set adaptive sync sdp enabled 3621 */ 3622 uint8_t force_disabled; 3623 3624 uint8_t pad[2]; 3625 }; 3626 struct dmub_cmd_replay_set_general_cmd_data { 3627 /** 3628 * Panel Instance. 3629 * Panel isntance to identify which replay_state to use 3630 * Currently the support is only for 0 or 1 3631 */ 3632 uint8_t panel_inst; 3633 /** 3634 * subtype: replay general cmd sub type 3635 */ 3636 uint8_t subtype; 3637 3638 uint8_t pad[2]; 3639 /** 3640 * config data with param1 and param2 3641 */ 3642 uint32_t param1; 3643 3644 uint32_t param2; 3645 }; 3646 3647 /** 3648 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3649 */ 3650 struct dmub_rb_cmd_replay_set_power_opt { 3651 /** 3652 * Command header. 3653 */ 3654 struct dmub_cmd_header header; 3655 /** 3656 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3657 */ 3658 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3659 }; 3660 3661 /** 3662 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3663 */ 3664 struct dmub_cmd_replay_set_coasting_vtotal_data { 3665 /** 3666 * 16-bit value dicated by driver that indicates the coasting vtotal. 3667 */ 3668 uint16_t coasting_vtotal; 3669 /** 3670 * REPLAY control version. 3671 */ 3672 uint8_t cmd_version; 3673 /** 3674 * Panel Instance. 3675 * Panel isntance to identify which replay_state to use 3676 * Currently the support is only for 0 or 1 3677 */ 3678 uint8_t panel_inst; 3679 /** 3680 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3681 */ 3682 uint16_t coasting_vtotal_high; 3683 /** 3684 * Explicit padding to 4 byte boundary. 3685 */ 3686 uint8_t pad[2]; 3687 }; 3688 3689 /** 3690 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3691 */ 3692 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3693 /** 3694 * Command header. 3695 */ 3696 struct dmub_cmd_header header; 3697 /** 3698 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3699 */ 3700 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3701 }; 3702 3703 /** 3704 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3705 */ 3706 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3707 /** 3708 * Command header. 3709 */ 3710 struct dmub_cmd_header header; 3711 /** 3712 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3713 */ 3714 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3715 /** 3716 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3717 */ 3718 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3719 }; 3720 3721 /** 3722 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3723 */ 3724 struct dmub_rb_cmd_replay_set_timing_sync { 3725 /** 3726 * Command header. 3727 */ 3728 struct dmub_cmd_header header; 3729 /** 3730 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3731 */ 3732 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3733 }; 3734 3735 /** 3736 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3737 */ 3738 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3739 /** 3740 * Command header. 3741 */ 3742 struct dmub_cmd_header header; 3743 /** 3744 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3745 */ 3746 struct dmub_cmd_replay_set_pseudo_vtotal data; 3747 }; 3748 3749 /** 3750 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3751 */ 3752 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3753 /** 3754 * Command header. 3755 */ 3756 struct dmub_cmd_header header; 3757 /** 3758 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3759 */ 3760 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3761 }; 3762 3763 /** 3764 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3765 */ 3766 struct dmub_rb_cmd_replay_set_general_cmd { 3767 /** 3768 * Command header. 3769 */ 3770 struct dmub_cmd_header header; 3771 /** 3772 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3773 */ 3774 struct dmub_cmd_replay_set_general_cmd_data data; 3775 }; 3776 3777 /** 3778 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3779 */ 3780 struct dmub_cmd_replay_frameupdate_timer_data { 3781 /** 3782 * Panel Instance. 3783 * Panel isntance to identify which replay_state to use 3784 * Currently the support is only for 0 or 1 3785 */ 3786 uint8_t panel_inst; 3787 /** 3788 * Replay Frameupdate Timer Enable or not 3789 */ 3790 uint8_t enable; 3791 /** 3792 * REPLAY force reflash frame update number 3793 */ 3794 uint16_t frameupdate_count; 3795 }; 3796 /** 3797 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3798 */ 3799 struct dmub_rb_cmd_replay_set_frameupdate_timer { 3800 /** 3801 * Command header. 3802 */ 3803 struct dmub_cmd_header header; 3804 /** 3805 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3806 */ 3807 struct dmub_cmd_replay_frameupdate_timer_data data; 3808 }; 3809 3810 /** 3811 * Definition union of replay command set 3812 */ 3813 union dmub_replay_cmd_set { 3814 /** 3815 * Panel Instance. 3816 * Panel isntance to identify which replay_state to use 3817 * Currently the support is only for 0 or 1 3818 */ 3819 uint8_t panel_inst; 3820 /** 3821 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 3822 */ 3823 struct dmub_cmd_replay_set_timing_sync_data sync_data; 3824 /** 3825 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 3826 */ 3827 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 3828 /** 3829 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 3830 */ 3831 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 3832 /** 3833 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 3834 */ 3835 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 3836 /** 3837 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 3838 */ 3839 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 3840 }; 3841 3842 /** 3843 * Set of HW components that can be locked. 3844 * 3845 * Note: If updating with more HW components, fields 3846 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3847 */ 3848 union dmub_hw_lock_flags { 3849 /** 3850 * Set of HW components that can be locked. 3851 */ 3852 struct { 3853 /** 3854 * Lock/unlock OTG master update lock. 3855 */ 3856 uint8_t lock_pipe : 1; 3857 /** 3858 * Lock/unlock cursor. 3859 */ 3860 uint8_t lock_cursor : 1; 3861 /** 3862 * Lock/unlock global update lock. 3863 */ 3864 uint8_t lock_dig : 1; 3865 /** 3866 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3867 */ 3868 uint8_t triple_buffer_lock : 1; 3869 } bits; 3870 3871 /** 3872 * Union for HW Lock flags. 3873 */ 3874 uint8_t u8All; 3875 }; 3876 3877 /** 3878 * Instances of HW to be locked. 3879 * 3880 * Note: If updating with more HW components, fields 3881 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3882 */ 3883 struct dmub_hw_lock_inst_flags { 3884 /** 3885 * OTG HW instance for OTG master update lock. 3886 */ 3887 uint8_t otg_inst; 3888 /** 3889 * OPP instance for cursor lock. 3890 */ 3891 uint8_t opp_inst; 3892 /** 3893 * OTG HW instance for global update lock. 3894 * TODO: Remove, and re-use otg_inst. 3895 */ 3896 uint8_t dig_inst; 3897 /** 3898 * Explicit pad to 4 byte boundary. 3899 */ 3900 uint8_t pad; 3901 }; 3902 3903 /** 3904 * Clients that can acquire the HW Lock Manager. 3905 * 3906 * Note: If updating with more clients, fields in 3907 * dmub_inbox0_cmd_lock_hw must be updated to match. 3908 */ 3909 enum hw_lock_client { 3910 /** 3911 * Driver is the client of HW Lock Manager. 3912 */ 3913 HW_LOCK_CLIENT_DRIVER = 0, 3914 /** 3915 * PSR SU is the client of HW Lock Manager. 3916 */ 3917 HW_LOCK_CLIENT_PSR_SU = 1, 3918 HW_LOCK_CLIENT_SUBVP = 3, 3919 /** 3920 * Replay is the client of HW Lock Manager. 3921 */ 3922 HW_LOCK_CLIENT_REPLAY = 4, 3923 HW_LOCK_CLIENT_FAMS2 = 5, 3924 /** 3925 * Invalid client. 3926 */ 3927 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3928 }; 3929 3930 /** 3931 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3932 */ 3933 struct dmub_cmd_lock_hw_data { 3934 /** 3935 * Specifies the client accessing HW Lock Manager. 3936 */ 3937 enum hw_lock_client client; 3938 /** 3939 * HW instances to be locked. 3940 */ 3941 struct dmub_hw_lock_inst_flags inst_flags; 3942 /** 3943 * Which components to be locked. 3944 */ 3945 union dmub_hw_lock_flags hw_locks; 3946 /** 3947 * Specifies lock/unlock. 3948 */ 3949 uint8_t lock; 3950 /** 3951 * HW can be unlocked separately from releasing the HW Lock Mgr. 3952 * This flag is set if the client wishes to release the object. 3953 */ 3954 uint8_t should_release; 3955 /** 3956 * Explicit padding to 4 byte boundary. 3957 */ 3958 uint8_t pad; 3959 }; 3960 3961 /** 3962 * Definition of a DMUB_CMD__HW_LOCK command. 3963 * Command is used by driver and FW. 3964 */ 3965 struct dmub_rb_cmd_lock_hw { 3966 /** 3967 * Command header. 3968 */ 3969 struct dmub_cmd_header header; 3970 /** 3971 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3972 */ 3973 struct dmub_cmd_lock_hw_data lock_hw_data; 3974 }; 3975 3976 /** 3977 * ABM command sub-types. 3978 */ 3979 enum dmub_cmd_abm_type { 3980 /** 3981 * Initialize parameters for ABM algorithm. 3982 * Data is passed through an indirect buffer. 3983 */ 3984 DMUB_CMD__ABM_INIT_CONFIG = 0, 3985 /** 3986 * Set OTG and panel HW instance. 3987 */ 3988 DMUB_CMD__ABM_SET_PIPE = 1, 3989 /** 3990 * Set user requested backklight level. 3991 */ 3992 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3993 /** 3994 * Set ABM operating/aggression level. 3995 */ 3996 DMUB_CMD__ABM_SET_LEVEL = 3, 3997 /** 3998 * Set ambient light level. 3999 */ 4000 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4001 /** 4002 * Enable/disable fractional duty cycle for backlight PWM. 4003 */ 4004 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4005 4006 /** 4007 * unregister vertical interrupt after steady state is reached 4008 */ 4009 DMUB_CMD__ABM_PAUSE = 6, 4010 4011 /** 4012 * Save and Restore ABM state. On save we save parameters, and 4013 * on restore we update state with passed in data. 4014 */ 4015 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4016 4017 /** 4018 * Query ABM caps. 4019 */ 4020 DMUB_CMD__ABM_QUERY_CAPS = 8, 4021 4022 /** 4023 * Set ABM Events 4024 */ 4025 DMUB_CMD__ABM_SET_EVENT = 9, 4026 4027 /** 4028 * Get the current ACE curve. 4029 */ 4030 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4031 }; 4032 4033 struct abm_ace_curve { 4034 /** 4035 * @offsets: ACE curve offsets. 4036 */ 4037 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4038 4039 /** 4040 * @thresholds: ACE curve thresholds. 4041 */ 4042 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4043 4044 /** 4045 * @slopes: ACE curve slopes. 4046 */ 4047 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4048 }; 4049 4050 struct fixed_pt_format { 4051 /** 4052 * @sign_bit: Indicates whether one bit is reserved for the sign. 4053 */ 4054 bool sign_bit; 4055 4056 /** 4057 * @num_int_bits: Number of bits used for integer part. 4058 */ 4059 uint8_t num_int_bits; 4060 4061 /** 4062 * @num_frac_bits: Number of bits used for fractional part. 4063 */ 4064 uint8_t num_frac_bits; 4065 4066 /** 4067 * @pad: Explicit padding to 4 byte boundary. 4068 */ 4069 uint8_t pad; 4070 }; 4071 4072 struct abm_caps { 4073 /** 4074 * @num_hg_bins: Number of histogram bins. 4075 */ 4076 uint8_t num_hg_bins; 4077 4078 /** 4079 * @num_ace_segments: Number of ACE curve segments. 4080 */ 4081 uint8_t num_ace_segments; 4082 4083 /** 4084 * @pad: Explicit padding to 4 byte boundary. 4085 */ 4086 uint8_t pad[2]; 4087 4088 /** 4089 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4090 */ 4091 struct fixed_pt_format ace_thresholds_format; 4092 4093 /** 4094 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4095 */ 4096 struct fixed_pt_format ace_offsets_format; 4097 4098 /** 4099 * @ace_slopes_format: Format of the ACE slopes. 4100 */ 4101 struct fixed_pt_format ace_slopes_format; 4102 }; 4103 4104 /** 4105 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4106 * Requirements: 4107 * - Padded explicitly to 32-bit boundary. 4108 * - Must ensure this structure matches the one on driver-side, 4109 * otherwise it won't be aligned. 4110 */ 4111 struct abm_config_table { 4112 /** 4113 * Gamma curve thresholds, used for crgb conversion. 4114 */ 4115 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4116 /** 4117 * Gamma curve offsets, used for crgb conversion. 4118 */ 4119 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4120 /** 4121 * Gamma curve slopes, used for crgb conversion. 4122 */ 4123 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4124 /** 4125 * Custom backlight curve thresholds. 4126 */ 4127 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4128 /** 4129 * Custom backlight curve offsets. 4130 */ 4131 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4132 /** 4133 * Ambient light thresholds. 4134 */ 4135 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4136 /** 4137 * Minimum programmable backlight. 4138 */ 4139 uint16_t min_abm_backlight; // 122B 4140 /** 4141 * Minimum reduction values. 4142 */ 4143 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4144 /** 4145 * Maximum reduction values. 4146 */ 4147 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4148 /** 4149 * Bright positive gain. 4150 */ 4151 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4152 /** 4153 * Dark negative gain. 4154 */ 4155 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4156 /** 4157 * Hybrid factor. 4158 */ 4159 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4160 /** 4161 * Contrast factor. 4162 */ 4163 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4164 /** 4165 * Deviation gain. 4166 */ 4167 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4168 /** 4169 * Minimum knee. 4170 */ 4171 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4172 /** 4173 * Maximum knee. 4174 */ 4175 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4176 /** 4177 * Unused. 4178 */ 4179 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4180 /** 4181 * Explicit padding to 4 byte boundary. 4182 */ 4183 uint8_t pad3[3]; // 229B 4184 /** 4185 * Backlight ramp reduction. 4186 */ 4187 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4188 /** 4189 * Backlight ramp start. 4190 */ 4191 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4192 }; 4193 4194 /** 4195 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4196 */ 4197 struct dmub_cmd_abm_set_pipe_data { 4198 /** 4199 * OTG HW instance. 4200 */ 4201 uint8_t otg_inst; 4202 4203 /** 4204 * Panel Control HW instance. 4205 */ 4206 uint8_t panel_inst; 4207 4208 /** 4209 * Controls how ABM will interpret a set pipe or set level command. 4210 */ 4211 uint8_t set_pipe_option; 4212 4213 /** 4214 * Unused. 4215 * TODO: Remove. 4216 */ 4217 uint8_t ramping_boundary; 4218 4219 /** 4220 * PwrSeq HW Instance. 4221 */ 4222 uint8_t pwrseq_inst; 4223 4224 /** 4225 * Explicit padding to 4 byte boundary. 4226 */ 4227 uint8_t pad[3]; 4228 }; 4229 4230 /** 4231 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4232 */ 4233 struct dmub_rb_cmd_abm_set_pipe { 4234 /** 4235 * Command header. 4236 */ 4237 struct dmub_cmd_header header; 4238 4239 /** 4240 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4241 */ 4242 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4243 }; 4244 4245 /** 4246 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4247 */ 4248 struct dmub_cmd_abm_set_backlight_data { 4249 /** 4250 * Number of frames to ramp to backlight user level. 4251 */ 4252 uint32_t frame_ramp; 4253 4254 /** 4255 * Requested backlight level from user. 4256 */ 4257 uint32_t backlight_user_level; 4258 4259 /** 4260 * ABM control version. 4261 */ 4262 uint8_t version; 4263 4264 /** 4265 * Panel Control HW instance mask. 4266 * Bit 0 is Panel Control HW instance 0. 4267 * Bit 1 is Panel Control HW instance 1. 4268 */ 4269 uint8_t panel_mask; 4270 4271 /** 4272 * Explicit padding to 4 byte boundary. 4273 */ 4274 uint8_t pad[2]; 4275 }; 4276 4277 /** 4278 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4279 */ 4280 struct dmub_rb_cmd_abm_set_backlight { 4281 /** 4282 * Command header. 4283 */ 4284 struct dmub_cmd_header header; 4285 4286 /** 4287 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4288 */ 4289 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4290 }; 4291 4292 /** 4293 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4294 */ 4295 struct dmub_cmd_abm_set_level_data { 4296 /** 4297 * Set current ABM operating/aggression level. 4298 */ 4299 uint32_t level; 4300 4301 /** 4302 * ABM control version. 4303 */ 4304 uint8_t version; 4305 4306 /** 4307 * Panel Control HW instance mask. 4308 * Bit 0 is Panel Control HW instance 0. 4309 * Bit 1 is Panel Control HW instance 1. 4310 */ 4311 uint8_t panel_mask; 4312 4313 /** 4314 * Explicit padding to 4 byte boundary. 4315 */ 4316 uint8_t pad[2]; 4317 }; 4318 4319 /** 4320 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4321 */ 4322 struct dmub_rb_cmd_abm_set_level { 4323 /** 4324 * Command header. 4325 */ 4326 struct dmub_cmd_header header; 4327 4328 /** 4329 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4330 */ 4331 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4332 }; 4333 4334 /** 4335 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4336 */ 4337 struct dmub_cmd_abm_set_ambient_level_data { 4338 /** 4339 * Ambient light sensor reading from OS. 4340 */ 4341 uint32_t ambient_lux; 4342 4343 /** 4344 * ABM control version. 4345 */ 4346 uint8_t version; 4347 4348 /** 4349 * Panel Control HW instance mask. 4350 * Bit 0 is Panel Control HW instance 0. 4351 * Bit 1 is Panel Control HW instance 1. 4352 */ 4353 uint8_t panel_mask; 4354 4355 /** 4356 * Explicit padding to 4 byte boundary. 4357 */ 4358 uint8_t pad[2]; 4359 }; 4360 4361 /** 4362 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4363 */ 4364 struct dmub_rb_cmd_abm_set_ambient_level { 4365 /** 4366 * Command header. 4367 */ 4368 struct dmub_cmd_header header; 4369 4370 /** 4371 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4372 */ 4373 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4374 }; 4375 4376 /** 4377 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4378 */ 4379 struct dmub_cmd_abm_set_pwm_frac_data { 4380 /** 4381 * Enable/disable fractional duty cycle for backlight PWM. 4382 * TODO: Convert to uint8_t. 4383 */ 4384 uint32_t fractional_pwm; 4385 4386 /** 4387 * ABM control version. 4388 */ 4389 uint8_t version; 4390 4391 /** 4392 * Panel Control HW instance mask. 4393 * Bit 0 is Panel Control HW instance 0. 4394 * Bit 1 is Panel Control HW instance 1. 4395 */ 4396 uint8_t panel_mask; 4397 4398 /** 4399 * Explicit padding to 4 byte boundary. 4400 */ 4401 uint8_t pad[2]; 4402 }; 4403 4404 /** 4405 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4406 */ 4407 struct dmub_rb_cmd_abm_set_pwm_frac { 4408 /** 4409 * Command header. 4410 */ 4411 struct dmub_cmd_header header; 4412 4413 /** 4414 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4415 */ 4416 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4417 }; 4418 4419 /** 4420 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4421 */ 4422 struct dmub_cmd_abm_init_config_data { 4423 /** 4424 * Location of indirect buffer used to pass init data to ABM. 4425 */ 4426 union dmub_addr src; 4427 4428 /** 4429 * Indirect buffer length. 4430 */ 4431 uint16_t bytes; 4432 4433 4434 /** 4435 * ABM control version. 4436 */ 4437 uint8_t version; 4438 4439 /** 4440 * Panel Control HW instance mask. 4441 * Bit 0 is Panel Control HW instance 0. 4442 * Bit 1 is Panel Control HW instance 1. 4443 */ 4444 uint8_t panel_mask; 4445 4446 /** 4447 * Explicit padding to 4 byte boundary. 4448 */ 4449 uint8_t pad[2]; 4450 }; 4451 4452 /** 4453 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4454 */ 4455 struct dmub_rb_cmd_abm_init_config { 4456 /** 4457 * Command header. 4458 */ 4459 struct dmub_cmd_header header; 4460 4461 /** 4462 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4463 */ 4464 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4465 }; 4466 4467 /** 4468 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4469 */ 4470 4471 struct dmub_cmd_abm_pause_data { 4472 4473 /** 4474 * Panel Control HW instance mask. 4475 * Bit 0 is Panel Control HW instance 0. 4476 * Bit 1 is Panel Control HW instance 1. 4477 */ 4478 uint8_t panel_mask; 4479 4480 /** 4481 * OTG hw instance 4482 */ 4483 uint8_t otg_inst; 4484 4485 /** 4486 * Enable or disable ABM pause 4487 */ 4488 uint8_t enable; 4489 4490 /** 4491 * Explicit padding to 4 byte boundary. 4492 */ 4493 uint8_t pad[1]; 4494 }; 4495 4496 /** 4497 * Definition of a DMUB_CMD__ABM_PAUSE command. 4498 */ 4499 struct dmub_rb_cmd_abm_pause { 4500 /** 4501 * Command header. 4502 */ 4503 struct dmub_cmd_header header; 4504 4505 /** 4506 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4507 */ 4508 struct dmub_cmd_abm_pause_data abm_pause_data; 4509 }; 4510 4511 /** 4512 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4513 */ 4514 struct dmub_cmd_abm_query_caps_in { 4515 /** 4516 * Panel instance. 4517 */ 4518 uint8_t panel_inst; 4519 4520 /** 4521 * Explicit padding to 4 byte boundary. 4522 */ 4523 uint8_t pad[3]; 4524 }; 4525 4526 /** 4527 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4528 */ 4529 struct dmub_cmd_abm_query_caps_out { 4530 /** 4531 * SW Algorithm caps. 4532 */ 4533 struct abm_caps sw_caps; 4534 4535 /** 4536 * ABM HW caps. 4537 */ 4538 struct abm_caps hw_caps; 4539 }; 4540 4541 /** 4542 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4543 */ 4544 struct dmub_rb_cmd_abm_query_caps { 4545 /** 4546 * Command header. 4547 */ 4548 struct dmub_cmd_header header; 4549 4550 /** 4551 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4552 */ 4553 union { 4554 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4555 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4556 } data; 4557 }; 4558 4559 /** 4560 * enum dmub_abm_ace_curve_type - ACE curve type. 4561 */ 4562 enum dmub_abm_ace_curve_type { 4563 /** 4564 * ACE curve as defined by the SW layer. 4565 */ 4566 ABM_ACE_CURVE_TYPE__SW = 0, 4567 /** 4568 * ACE curve as defined by the SW to HW translation interface layer. 4569 */ 4570 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4571 }; 4572 4573 /** 4574 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4575 */ 4576 struct dmub_rb_cmd_abm_get_ace_curve { 4577 /** 4578 * Command header. 4579 */ 4580 struct dmub_cmd_header header; 4581 4582 /** 4583 * Address where ACE curve should be copied. 4584 */ 4585 union dmub_addr dest; 4586 4587 /** 4588 * Type of ACE curve being queried. 4589 */ 4590 enum dmub_abm_ace_curve_type ace_type; 4591 4592 /** 4593 * Indirect buffer length. 4594 */ 4595 uint16_t bytes; 4596 4597 /** 4598 * eDP panel instance. 4599 */ 4600 uint8_t panel_inst; 4601 4602 /** 4603 * Explicit padding to 4 byte boundary. 4604 */ 4605 uint8_t pad; 4606 }; 4607 4608 /** 4609 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4610 */ 4611 struct dmub_rb_cmd_abm_save_restore { 4612 /** 4613 * Command header. 4614 */ 4615 struct dmub_cmd_header header; 4616 4617 /** 4618 * OTG hw instance 4619 */ 4620 uint8_t otg_inst; 4621 4622 /** 4623 * Enable or disable ABM pause 4624 */ 4625 uint8_t freeze; 4626 4627 /** 4628 * Explicit padding to 4 byte boundary. 4629 */ 4630 uint8_t debug; 4631 4632 /** 4633 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4634 */ 4635 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4636 }; 4637 4638 /** 4639 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4640 */ 4641 4642 struct dmub_cmd_abm_set_event_data { 4643 4644 /** 4645 * VB Scaling Init. Strength Mapping 4646 * Byte 0: 0~255 for VB level 0 4647 * Byte 1: 0~255 for VB level 1 4648 * Byte 2: 0~255 for VB level 2 4649 * Byte 3: 0~255 for VB level 3 4650 */ 4651 uint32_t vb_scaling_strength_mapping; 4652 /** 4653 * VariBright Scaling Enable 4654 */ 4655 uint8_t vb_scaling_enable; 4656 /** 4657 * Panel Control HW instance mask. 4658 * Bit 0 is Panel Control HW instance 0. 4659 * Bit 1 is Panel Control HW instance 1. 4660 */ 4661 uint8_t panel_mask; 4662 4663 /** 4664 * Explicit padding to 4 byte boundary. 4665 */ 4666 uint8_t pad[2]; 4667 }; 4668 4669 /** 4670 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 4671 */ 4672 struct dmub_rb_cmd_abm_set_event { 4673 /** 4674 * Command header. 4675 */ 4676 struct dmub_cmd_header header; 4677 4678 /** 4679 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4680 */ 4681 struct dmub_cmd_abm_set_event_data abm_set_event_data; 4682 }; 4683 4684 /** 4685 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4686 */ 4687 struct dmub_cmd_query_feature_caps_data { 4688 /** 4689 * DMUB feature capabilities. 4690 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4691 */ 4692 struct dmub_feature_caps feature_caps; 4693 }; 4694 4695 /** 4696 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4697 */ 4698 struct dmub_rb_cmd_query_feature_caps { 4699 /** 4700 * Command header. 4701 */ 4702 struct dmub_cmd_header header; 4703 /** 4704 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4705 */ 4706 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4707 }; 4708 4709 /** 4710 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4711 */ 4712 struct dmub_cmd_visual_confirm_color_data { 4713 /** 4714 * DMUB visual confirm color 4715 */ 4716 struct dmub_visual_confirm_color visual_confirm_color; 4717 }; 4718 4719 /** 4720 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4721 */ 4722 struct dmub_rb_cmd_get_visual_confirm_color { 4723 /** 4724 * Command header. 4725 */ 4726 struct dmub_cmd_header header; 4727 /** 4728 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4729 */ 4730 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4731 }; 4732 4733 /** 4734 * enum dmub_cmd_panel_cntl_type - Panel control command. 4735 */ 4736 enum dmub_cmd_panel_cntl_type { 4737 /** 4738 * Initializes embedded panel hardware blocks. 4739 */ 4740 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4741 /** 4742 * Queries backlight info for the embedded panel. 4743 */ 4744 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4745 /** 4746 * Sets the PWM Freq as per user's requirement. 4747 */ 4748 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 4749 }; 4750 4751 /** 4752 * struct dmub_cmd_panel_cntl_data - Panel control data. 4753 */ 4754 struct dmub_cmd_panel_cntl_data { 4755 uint32_t pwrseq_inst; /**< pwrseq instance */ 4756 uint32_t current_backlight; /* in/out */ 4757 uint32_t bl_pwm_cntl; /* in/out */ 4758 uint32_t bl_pwm_period_cntl; /* in/out */ 4759 uint32_t bl_pwm_ref_div1; /* in/out */ 4760 uint8_t is_backlight_on : 1; /* in/out */ 4761 uint8_t is_powered_on : 1; /* in/out */ 4762 uint8_t padding[3]; 4763 uint32_t bl_pwm_ref_div2; /* in/out */ 4764 uint8_t reserved[4]; 4765 }; 4766 4767 /** 4768 * struct dmub_rb_cmd_panel_cntl - Panel control command. 4769 */ 4770 struct dmub_rb_cmd_panel_cntl { 4771 struct dmub_cmd_header header; /**< header */ 4772 struct dmub_cmd_panel_cntl_data data; /**< payload */ 4773 }; 4774 4775 struct dmub_optc_state { 4776 uint32_t v_total_max; 4777 uint32_t v_total_min; 4778 uint32_t tg_inst; 4779 }; 4780 4781 struct dmub_rb_cmd_drr_update { 4782 struct dmub_cmd_header header; 4783 struct dmub_optc_state dmub_optc_state_req; 4784 }; 4785 4786 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 4787 uint32_t pix_clk_100hz; 4788 uint8_t max_ramp_step; 4789 uint8_t pipes; 4790 uint8_t min_refresh_in_hz; 4791 uint8_t pipe_count; 4792 uint8_t pipe_index[4]; 4793 }; 4794 4795 struct dmub_cmd_fw_assisted_mclk_switch_config { 4796 uint8_t fams_enabled; 4797 uint8_t visual_confirm_enabled; 4798 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 4799 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 4800 }; 4801 4802 struct dmub_rb_cmd_fw_assisted_mclk_switch { 4803 struct dmub_cmd_header header; 4804 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 4805 }; 4806 4807 /** 4808 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4809 */ 4810 struct dmub_cmd_lvtma_control_data { 4811 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 4812 uint8_t bypass_panel_control_wait; 4813 uint8_t reserved_0[2]; /**< For future use */ 4814 uint8_t pwrseq_inst; /**< LVTMA control instance */ 4815 uint8_t reserved_1[3]; /**< For future use */ 4816 }; 4817 4818 /** 4819 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4820 */ 4821 struct dmub_rb_cmd_lvtma_control { 4822 /** 4823 * Command header. 4824 */ 4825 struct dmub_cmd_header header; 4826 /** 4827 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4828 */ 4829 struct dmub_cmd_lvtma_control_data data; 4830 }; 4831 4832 /** 4833 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4834 */ 4835 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 4836 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4837 uint8_t is_usb; /**< is phy is usb */ 4838 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 4839 uint8_t is_dp4; /**< is dp in 4 lane */ 4840 }; 4841 4842 /** 4843 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4844 */ 4845 struct dmub_rb_cmd_transmitter_query_dp_alt { 4846 struct dmub_cmd_header header; /**< header */ 4847 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 4848 }; 4849 4850 struct phy_test_mode { 4851 uint8_t mode; 4852 uint8_t pat0; 4853 uint8_t pad[2]; 4854 }; 4855 4856 /** 4857 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4858 */ 4859 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 4860 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4861 uint8_t mode; /**< HDMI/DP/DP2 etc */ 4862 uint8_t lane_num; /**< Number of lanes */ 4863 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 4864 struct phy_test_mode test_mode; 4865 enum dmub_phy_fsm_state state; 4866 uint32_t status; 4867 uint8_t pad; 4868 }; 4869 4870 /** 4871 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4872 */ 4873 struct dmub_rb_cmd_transmitter_set_phy_fsm { 4874 struct dmub_cmd_header header; /**< header */ 4875 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 4876 }; 4877 4878 /** 4879 * Maximum number of bytes a chunk sent to DMUB for parsing 4880 */ 4881 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 4882 4883 /** 4884 * Represent a chunk of CEA blocks sent to DMUB for parsing 4885 */ 4886 struct dmub_cmd_send_edid_cea { 4887 uint16_t offset; /**< offset into the CEA block */ 4888 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 4889 uint16_t cea_total_length; /**< total length of the CEA block */ 4890 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 4891 uint8_t pad[3]; /**< padding and for future expansion */ 4892 }; 4893 4894 /** 4895 * Result of VSDB parsing from CEA block 4896 */ 4897 struct dmub_cmd_edid_cea_amd_vsdb { 4898 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 4899 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 4900 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 4901 uint16_t min_frame_rate; /**< Maximum frame rate */ 4902 uint16_t max_frame_rate; /**< Minimum frame rate */ 4903 }; 4904 4905 /** 4906 * Result of sending a CEA chunk 4907 */ 4908 struct dmub_cmd_edid_cea_ack { 4909 uint16_t offset; /**< offset of the chunk into the CEA block */ 4910 uint8_t success; /**< 1 if this sending of chunk succeeded */ 4911 uint8_t pad; /**< padding and for future expansion */ 4912 }; 4913 4914 /** 4915 * Specify whether the result is an ACK/NACK or the parsing has finished 4916 */ 4917 enum dmub_cmd_edid_cea_reply_type { 4918 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 4919 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 4920 }; 4921 4922 /** 4923 * Definition of a DMUB_CMD__EDID_CEA command. 4924 */ 4925 struct dmub_rb_cmd_edid_cea { 4926 struct dmub_cmd_header header; /**< Command header */ 4927 union dmub_cmd_edid_cea_data { 4928 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 4929 struct dmub_cmd_edid_cea_output { /**< output with results */ 4930 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 4931 union { 4932 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 4933 struct dmub_cmd_edid_cea_ack ack; 4934 }; 4935 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 4936 } data; /**< Command data */ 4937 4938 }; 4939 4940 /** 4941 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 4942 */ 4943 struct dmub_cmd_cable_id_input { 4944 uint8_t phy_inst; /**< phy inst for cable id data */ 4945 }; 4946 4947 /** 4948 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 4949 */ 4950 struct dmub_cmd_cable_id_output { 4951 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 4952 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 4953 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 4954 uint8_t RESERVED :2; /**< reserved means not defined */ 4955 }; 4956 4957 /** 4958 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 4959 */ 4960 struct dmub_rb_cmd_get_usbc_cable_id { 4961 struct dmub_cmd_header header; /**< Command header */ 4962 /** 4963 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 4964 */ 4965 union dmub_cmd_cable_id_data { 4966 struct dmub_cmd_cable_id_input input; /**< Input */ 4967 struct dmub_cmd_cable_id_output output; /**< Output */ 4968 uint8_t output_raw; /**< Raw data output */ 4969 } data; 4970 }; 4971 4972 /** 4973 * Command type of a DMUB_CMD__SECURE_DISPLAY command 4974 */ 4975 enum dmub_cmd_secure_display_type { 4976 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 4977 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 4978 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 4979 }; 4980 4981 /** 4982 * Definition of a DMUB_CMD__SECURE_DISPLAY command 4983 */ 4984 struct dmub_rb_cmd_secure_display { 4985 struct dmub_cmd_header header; 4986 /** 4987 * Data passed from driver to dmub firmware. 4988 */ 4989 struct dmub_cmd_roi_info { 4990 uint16_t x_start; 4991 uint16_t x_end; 4992 uint16_t y_start; 4993 uint16_t y_end; 4994 uint8_t otg_id; 4995 uint8_t phy_id; 4996 } roi_info; 4997 }; 4998 4999 /** 5000 * Command type of a DMUB_CMD__PSP command 5001 */ 5002 enum dmub_cmd_psp_type { 5003 DMUB_CMD__PSP_ASSR_ENABLE = 0 5004 }; 5005 5006 /** 5007 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5008 */ 5009 struct dmub_cmd_assr_enable_data { 5010 /** 5011 * ASSR enable or disable. 5012 */ 5013 uint8_t enable; 5014 /** 5015 * PHY port type. 5016 * Indicates eDP / non-eDP port type 5017 */ 5018 uint8_t phy_port_type; 5019 /** 5020 * PHY port ID. 5021 */ 5022 uint8_t phy_port_id; 5023 /** 5024 * Link encoder index. 5025 */ 5026 uint8_t link_enc_index; 5027 /** 5028 * HPO mode. 5029 */ 5030 uint8_t hpo_mode; 5031 5032 /** 5033 * Reserved field. 5034 */ 5035 uint8_t reserved[7]; 5036 }; 5037 5038 /** 5039 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5040 */ 5041 struct dmub_rb_cmd_assr_enable { 5042 /** 5043 * Command header. 5044 */ 5045 struct dmub_cmd_header header; 5046 5047 /** 5048 * Assr data. 5049 */ 5050 struct dmub_cmd_assr_enable_data assr_data; 5051 5052 /** 5053 * Reserved field. 5054 */ 5055 uint32_t reserved[3]; 5056 }; 5057 5058 /** 5059 * union dmub_rb_cmd - DMUB inbox command. 5060 */ 5061 union dmub_rb_cmd { 5062 /** 5063 * Elements shared with all commands. 5064 */ 5065 struct dmub_rb_cmd_common cmd_common; 5066 /** 5067 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5068 */ 5069 struct dmub_rb_cmd_read_modify_write read_modify_write; 5070 /** 5071 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5072 */ 5073 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5074 /** 5075 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5076 */ 5077 struct dmub_rb_cmd_burst_write burst_write; 5078 /** 5079 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5080 */ 5081 struct dmub_rb_cmd_reg_wait reg_wait; 5082 /** 5083 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5084 */ 5085 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5086 /** 5087 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5088 */ 5089 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5090 /** 5091 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5092 */ 5093 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5094 /** 5095 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5096 */ 5097 struct dmub_rb_cmd_dpphy_init dpphy_init; 5098 /** 5099 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5100 */ 5101 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5102 /** 5103 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5104 */ 5105 struct dmub_rb_cmd_domain_control domain_control; 5106 /** 5107 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5108 */ 5109 struct dmub_rb_cmd_psr_set_version psr_set_version; 5110 /** 5111 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5112 */ 5113 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5114 /** 5115 * Definition of a DMUB_CMD__PSR_ENABLE command. 5116 */ 5117 struct dmub_rb_cmd_psr_enable psr_enable; 5118 /** 5119 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5120 */ 5121 struct dmub_rb_cmd_psr_set_level psr_set_level; 5122 /** 5123 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5124 */ 5125 struct dmub_rb_cmd_psr_force_static psr_force_static; 5126 /** 5127 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5128 */ 5129 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5130 /** 5131 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5132 */ 5133 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5134 /** 5135 * Definition of a DMUB_CMD__HW_LOCK command. 5136 * Command is used by driver and FW. 5137 */ 5138 struct dmub_rb_cmd_lock_hw lock_hw; 5139 /** 5140 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5141 */ 5142 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5143 /** 5144 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5145 */ 5146 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5147 /** 5148 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5149 */ 5150 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5151 /** 5152 * Definition of a DMUB_CMD__MALL command. 5153 */ 5154 struct dmub_rb_cmd_mall mall; 5155 5156 /** 5157 * Definition of a DMUB_CMD__CAB command. 5158 */ 5159 struct dmub_rb_cmd_cab_for_ss cab; 5160 5161 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5162 5163 /** 5164 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5165 */ 5166 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5167 5168 /** 5169 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5170 */ 5171 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5172 5173 /** 5174 * Definition of DMUB_CMD__PANEL_CNTL commands. 5175 */ 5176 struct dmub_rb_cmd_panel_cntl panel_cntl; 5177 5178 /** 5179 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5180 */ 5181 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5182 5183 /** 5184 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5185 */ 5186 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5187 5188 /** 5189 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5190 */ 5191 struct dmub_rb_cmd_abm_set_level abm_set_level; 5192 5193 /** 5194 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5195 */ 5196 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5197 5198 /** 5199 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5200 */ 5201 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5202 5203 /** 5204 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5205 */ 5206 struct dmub_rb_cmd_abm_init_config abm_init_config; 5207 5208 /** 5209 * Definition of a DMUB_CMD__ABM_PAUSE command. 5210 */ 5211 struct dmub_rb_cmd_abm_pause abm_pause; 5212 5213 /** 5214 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5215 */ 5216 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5217 5218 /** 5219 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5220 */ 5221 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5222 5223 /** 5224 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5225 */ 5226 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5227 5228 /** 5229 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5230 */ 5231 struct dmub_rb_cmd_abm_set_event abm_set_event; 5232 5233 /** 5234 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5235 */ 5236 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5237 5238 /** 5239 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5240 */ 5241 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5242 5243 /** 5244 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5245 */ 5246 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5247 5248 /** 5249 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5250 */ 5251 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5252 struct dmub_rb_cmd_drr_update drr_update; 5253 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5254 5255 /** 5256 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5257 */ 5258 struct dmub_rb_cmd_lvtma_control lvtma_control; 5259 /** 5260 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5261 */ 5262 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5263 /** 5264 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5265 */ 5266 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5267 /** 5268 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5269 */ 5270 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5271 /** 5272 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5273 */ 5274 struct dmub_rb_cmd_set_config_access set_config_access; 5275 /** 5276 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5277 */ 5278 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5279 /** 5280 * Definition of a DMUB_CMD__EDID_CEA command. 5281 */ 5282 struct dmub_rb_cmd_edid_cea edid_cea; 5283 /** 5284 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5285 */ 5286 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5287 5288 /** 5289 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5290 */ 5291 struct dmub_rb_cmd_query_hpd_state query_hpd; 5292 /** 5293 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5294 */ 5295 struct dmub_rb_cmd_secure_display secure_display; 5296 5297 /** 5298 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5299 */ 5300 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5301 /** 5302 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5303 */ 5304 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5305 /* 5306 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5307 */ 5308 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5309 /** 5310 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5311 */ 5312 struct dmub_rb_cmd_replay_enable replay_enable; 5313 /** 5314 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5315 */ 5316 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5317 /** 5318 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5319 */ 5320 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5321 /** 5322 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5323 */ 5324 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5325 5326 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5327 /** 5328 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5329 */ 5330 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5331 /** 5332 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5333 */ 5334 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5335 /** 5336 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5337 */ 5338 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5339 /** 5340 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5341 */ 5342 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5343 /** 5344 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5345 */ 5346 struct dmub_rb_cmd_assr_enable assr_enable; 5347 struct dmub_rb_cmd_fams2 fams2_config; 5348 5349 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5350 5351 struct dmub_rb_cmd_fams2_flip fams2_flip; 5352 }; 5353 5354 /** 5355 * union dmub_rb_out_cmd - Outbox command 5356 */ 5357 union dmub_rb_out_cmd { 5358 /** 5359 * Parameters common to every command. 5360 */ 5361 struct dmub_rb_cmd_common cmd_common; 5362 /** 5363 * AUX reply command. 5364 */ 5365 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5366 /** 5367 * HPD notify command. 5368 */ 5369 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5370 /** 5371 * SET_CONFIG reply command. 5372 */ 5373 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5374 /** 5375 * DPIA notification command. 5376 */ 5377 struct dmub_rb_cmd_dpia_notification dpia_notification; 5378 /** 5379 * HPD sense notification command. 5380 */ 5381 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5382 }; 5383 #pragma pack(pop) 5384 5385 5386 //============================================================================== 5387 //</DMUB_CMD>=================================================================== 5388 //============================================================================== 5389 //< DMUB_RB>==================================================================== 5390 //============================================================================== 5391 5392 /** 5393 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5394 */ 5395 struct dmub_rb_init_params { 5396 void *ctx; /**< Caller provided context pointer */ 5397 void *base_address; /**< CPU base address for ring's data */ 5398 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5399 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5400 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5401 }; 5402 5403 /** 5404 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5405 */ 5406 struct dmub_rb { 5407 void *base_address; /**< CPU address for the ring's data */ 5408 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5409 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5410 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5411 5412 void *ctx; /**< Caller provided context pointer */ 5413 void *dmub; /**< Pointer to the DMUB interface */ 5414 }; 5415 5416 /** 5417 * @brief Checks if the ringbuffer is empty. 5418 * 5419 * @param rb DMUB Ringbuffer 5420 * @return true if empty 5421 * @return false otherwise 5422 */ 5423 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5424 { 5425 return (rb->wrpt == rb->rptr); 5426 } 5427 5428 /** 5429 * @brief Checks if the ringbuffer is full 5430 * 5431 * @param rb DMUB Ringbuffer 5432 * @return true if full 5433 * @return false otherwise 5434 */ 5435 static inline bool dmub_rb_full(struct dmub_rb *rb) 5436 { 5437 uint32_t data_count; 5438 5439 if (rb->wrpt >= rb->rptr) 5440 data_count = rb->wrpt - rb->rptr; 5441 else 5442 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5443 5444 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5445 } 5446 5447 /** 5448 * @brief Pushes a command into the ringbuffer 5449 * 5450 * @param rb DMUB ringbuffer 5451 * @param cmd The command to push 5452 * @return true if the ringbuffer was not full 5453 * @return false otherwise 5454 */ 5455 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5456 const union dmub_rb_cmd *cmd) 5457 { 5458 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5459 const uint64_t *src = (const uint64_t *)cmd; 5460 uint8_t i; 5461 5462 if (dmub_rb_full(rb)) 5463 return false; 5464 5465 // copying data 5466 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5467 *dst++ = *src++; 5468 5469 rb->wrpt += DMUB_RB_CMD_SIZE; 5470 5471 if (rb->wrpt >= rb->capacity) 5472 rb->wrpt %= rb->capacity; 5473 5474 return true; 5475 } 5476 5477 /** 5478 * @brief Pushes a command into the DMUB outbox ringbuffer 5479 * 5480 * @param rb DMUB outbox ringbuffer 5481 * @param cmd Outbox command 5482 * @return true if not full 5483 * @return false otherwise 5484 */ 5485 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5486 const union dmub_rb_out_cmd *cmd) 5487 { 5488 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 5489 const uint8_t *src = (const uint8_t *)cmd; 5490 5491 if (dmub_rb_full(rb)) 5492 return false; 5493 5494 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 5495 5496 rb->wrpt += DMUB_RB_CMD_SIZE; 5497 5498 if (rb->wrpt >= rb->capacity) 5499 rb->wrpt %= rb->capacity; 5500 5501 return true; 5502 } 5503 5504 /** 5505 * @brief Returns the next unprocessed command in the ringbuffer. 5506 * 5507 * @param rb DMUB ringbuffer 5508 * @param cmd The command to return 5509 * @return true if not empty 5510 * @return false otherwise 5511 */ 5512 static inline bool dmub_rb_front(struct dmub_rb *rb, 5513 union dmub_rb_cmd **cmd) 5514 { 5515 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 5516 5517 if (dmub_rb_empty(rb)) 5518 return false; 5519 5520 *cmd = (union dmub_rb_cmd *)rb_cmd; 5521 5522 return true; 5523 } 5524 5525 /** 5526 * @brief Determines the next ringbuffer offset. 5527 * 5528 * @param rb DMUB inbox ringbuffer 5529 * @param num_cmds Number of commands 5530 * @param next_rptr The next offset in the ringbuffer 5531 */ 5532 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 5533 uint32_t num_cmds, 5534 uint32_t *next_rptr) 5535 { 5536 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 5537 5538 if (*next_rptr >= rb->capacity) 5539 *next_rptr %= rb->capacity; 5540 } 5541 5542 /** 5543 * @brief Returns a pointer to a command in the inbox. 5544 * 5545 * @param rb DMUB inbox ringbuffer 5546 * @param cmd The inbox command to return 5547 * @param rptr The ringbuffer offset 5548 * @return true if not empty 5549 * @return false otherwise 5550 */ 5551 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 5552 union dmub_rb_cmd **cmd, 5553 uint32_t rptr) 5554 { 5555 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 5556 5557 if (dmub_rb_empty(rb)) 5558 return false; 5559 5560 *cmd = (union dmub_rb_cmd *)rb_cmd; 5561 5562 return true; 5563 } 5564 5565 /** 5566 * @brief Returns the next unprocessed command in the outbox. 5567 * 5568 * @param rb DMUB outbox ringbuffer 5569 * @param cmd The outbox command to return 5570 * @return true if not empty 5571 * @return false otherwise 5572 */ 5573 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 5574 union dmub_rb_out_cmd *cmd) 5575 { 5576 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 5577 uint64_t *dst = (uint64_t *)cmd; 5578 uint8_t i; 5579 5580 if (dmub_rb_empty(rb)) 5581 return false; 5582 5583 // copying data 5584 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5585 *dst++ = *src++; 5586 5587 return true; 5588 } 5589 5590 /** 5591 * @brief Removes the front entry in the ringbuffer. 5592 * 5593 * @param rb DMUB ringbuffer 5594 * @return true if the command was removed 5595 * @return false if there were no commands 5596 */ 5597 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 5598 { 5599 if (dmub_rb_empty(rb)) 5600 return false; 5601 5602 rb->rptr += DMUB_RB_CMD_SIZE; 5603 5604 if (rb->rptr >= rb->capacity) 5605 rb->rptr %= rb->capacity; 5606 5607 return true; 5608 } 5609 5610 /** 5611 * @brief Flushes commands in the ringbuffer to framebuffer memory. 5612 * 5613 * Avoids a race condition where DMCUB accesses memory while 5614 * there are still writes in flight to framebuffer. 5615 * 5616 * @param rb DMUB ringbuffer 5617 */ 5618 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 5619 { 5620 uint32_t rptr = rb->rptr; 5621 uint32_t wptr = rb->wrpt; 5622 5623 while (rptr != wptr) { 5624 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 5625 uint8_t i; 5626 5627 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5628 (void)READ_ONCE(*data++); 5629 5630 rptr += DMUB_RB_CMD_SIZE; 5631 if (rptr >= rb->capacity) 5632 rptr %= rb->capacity; 5633 } 5634 } 5635 5636 /** 5637 * @brief Initializes a DMCUB ringbuffer 5638 * 5639 * @param rb DMUB ringbuffer 5640 * @param init_params initial configuration for the ringbuffer 5641 */ 5642 static inline void dmub_rb_init(struct dmub_rb *rb, 5643 struct dmub_rb_init_params *init_params) 5644 { 5645 rb->base_address = init_params->base_address; 5646 rb->capacity = init_params->capacity; 5647 rb->rptr = init_params->read_ptr; 5648 rb->wrpt = init_params->write_ptr; 5649 } 5650 5651 /** 5652 * @brief Copies output data from in/out commands into the given command. 5653 * 5654 * @param rb DMUB ringbuffer 5655 * @param cmd Command to copy data into 5656 */ 5657 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5658 union dmub_rb_cmd *cmd) 5659 { 5660 // Copy rb entry back into command 5661 uint8_t *rd_ptr = (rb->rptr == 0) ? 5662 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5663 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5664 5665 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5666 } 5667 5668 //============================================================================== 5669 //</DMUB_RB>==================================================================== 5670 //============================================================================== 5671 #endif /* _DMUB_CMD_H_ */ 5672