1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310 struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326 }; 327 #pragma pack(pop) 328 329 /** 330 * Dirty rect definition. 331 */ 332 struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352 }; 353 354 /** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357 union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397 }; 398 399 /** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402 union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 uint32_t reserved : 18; 489 } bitfields; 490 491 uint32_t u32All; 492 }; 493 494 /** 495 * Flags record error state. 496 */ 497 union replay_visual_confirm_error_state_flags { 498 struct { 499 /** 500 * 0x1 (bit 0) - Desync Error flag. 501 */ 502 uint32_t desync_error : 1; 503 504 /** 505 * 0x2 (bit 1) - State Transition Error flag. 506 */ 507 uint32_t state_transition_error : 1; 508 509 /** 510 * 0x4 (bit 2) - Crc Error flag 511 */ 512 uint32_t crc_error : 1; 513 514 /** 515 * 0x8 (bit 3) - Reserved 516 */ 517 uint32_t reserved_3 : 1; 518 519 /** 520 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 521 * Added new debug flag to control DPCD. 522 */ 523 uint32_t incorrect_vtotal_in_static_screen : 1; 524 525 /** 526 * 0x20 (bit 5) - No doubled Refresh Rate. 527 */ 528 uint32_t no_double_rr : 1; 529 530 /** 531 * Reserved bit 6-7 532 */ 533 uint32_t reserved_6_7 : 2; 534 535 /** 536 * Reserved bit 9-31 537 */ 538 uint32_t reserved_9_31 : 24; 539 } bitfields; 540 541 uint32_t u32All; 542 }; 543 544 union replay_hw_flags { 545 struct { 546 /** 547 * @allow_alpm_fw_standby_mode: To indicate whether the 548 * ALPM FW standby mode is allowed 549 */ 550 uint32_t allow_alpm_fw_standby_mode : 1; 551 552 /* 553 * @dsc_enable_status: DSC enable status in driver 554 */ 555 uint32_t dsc_enable_status : 1; 556 557 /** 558 * @fec_enable_status: receive fec enable/disable status from driver 559 */ 560 uint32_t fec_enable_status : 1; 561 562 /* 563 * @smu_optimizations_en: SMU power optimization. 564 * Only when active display is Replay capable and display enters Replay. 565 * Trigger interrupt to SMU to powerup/down. 566 */ 567 uint32_t smu_optimizations_en : 1; 568 569 /** 570 * @phy_power_state: Indicates current phy power state 571 */ 572 uint32_t phy_power_state : 1; 573 574 /** 575 * @link_power_state: Indicates current link power state 576 */ 577 uint32_t link_power_state : 1; 578 /** 579 * Use TPS3 signal when restore main link. 580 */ 581 uint32_t force_wakeup_by_tps3 : 1; 582 /** 583 * @is_alpm_initialized: Indicates whether ALPM is initialized 584 */ 585 uint32_t is_alpm_initialized : 1; 586 587 /** 588 * @alpm_mode: Indicates ALPM mode selected 589 */ 590 uint32_t alpm_mode : 2; 591 } bitfields; 592 593 uint32_t u32All; 594 }; 595 596 union fw_assisted_mclk_switch_version { 597 struct { 598 uint8_t minor : 5; 599 uint8_t major : 3; 600 }; 601 uint8_t ver; 602 }; 603 604 /** 605 * DMUB feature capabilities. 606 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 607 */ 608 struct dmub_feature_caps { 609 /** 610 * Max PSR version supported by FW. 611 */ 612 uint8_t psr; 613 uint8_t fw_assisted_mclk_switch_ver; 614 uint8_t reserved[4]; 615 uint8_t subvp_psr_support; 616 uint8_t gecc_enable; 617 uint8_t replay_supported; 618 uint8_t replay_reserved[3]; 619 uint8_t abm_aux_backlight_support; 620 }; 621 622 struct dmub_visual_confirm_color { 623 /** 624 * Maximum 10 bits color value 625 */ 626 uint16_t color_r_cr; 627 uint16_t color_g_y; 628 uint16_t color_b_cb; 629 uint16_t panel_inst; 630 }; 631 632 //============================================================================== 633 //</DMUB_TYPES>================================================================= 634 //============================================================================== 635 //< DMUB_META>================================================================== 636 //============================================================================== 637 #pragma pack(push, 1) 638 639 /* Magic value for identifying dmub_fw_meta_info */ 640 #define DMUB_FW_META_MAGIC 0x444D5542 641 642 /* Offset from the end of the file to the dmub_fw_meta_info */ 643 #define DMUB_FW_META_OFFSET 0x24 644 645 /** 646 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 647 */ 648 union dmub_fw_meta_feature_bits { 649 struct { 650 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 651 uint32_t reserved : 31; 652 } bits; /**< status bits */ 653 uint32_t all; /**< 32-bit access to status bits */ 654 }; 655 656 /** 657 * struct dmub_fw_meta_info - metadata associated with fw binary 658 * 659 * NOTE: This should be considered a stable API. Fields should 660 * not be repurposed or reordered. New fields should be 661 * added instead to extend the structure. 662 * 663 * @magic_value: magic value identifying DMUB firmware meta info 664 * @fw_region_size: size of the firmware state region 665 * @trace_buffer_size: size of the tracebuffer region 666 * @fw_version: the firmware version information 667 * @dal_fw: 1 if the firmware is DAL 668 * @shared_state_size: size of the shared state region in bytes 669 * @shared_state_features: number of shared state features 670 */ 671 struct dmub_fw_meta_info { 672 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 673 uint32_t fw_region_size; /**< size of the firmware state region */ 674 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 675 uint32_t fw_version; /**< the firmware version information */ 676 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 677 uint8_t reserved[3]; /**< padding bits */ 678 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 679 uint16_t shared_state_features; /**< number of shared state features */ 680 uint16_t reserved2; /**< padding bytes */ 681 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 682 }; 683 684 /** 685 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 686 */ 687 union dmub_fw_meta { 688 struct dmub_fw_meta_info info; /**< metadata info */ 689 uint8_t reserved[64]; /**< padding bits */ 690 }; 691 692 #pragma pack(pop) 693 694 //============================================================================== 695 //< DMUB Trace Buffer>================================================================ 696 //============================================================================== 697 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 698 /** 699 * dmub_trace_code_t - firmware trace code, 32-bits 700 */ 701 typedef uint32_t dmub_trace_code_t; 702 703 /** 704 * struct dmcub_trace_buf_entry - Firmware trace entry 705 */ 706 struct dmcub_trace_buf_entry { 707 dmub_trace_code_t trace_code; /**< trace code for the event */ 708 uint32_t tick_count; /**< the tick count at time of trace */ 709 uint32_t param0; /**< trace defined parameter 0 */ 710 uint32_t param1; /**< trace defined parameter 1 */ 711 }; 712 #endif 713 714 //============================================================================== 715 //< DMUB_STATUS>================================================================ 716 //============================================================================== 717 718 /** 719 * DMCUB scratch registers can be used to determine firmware status. 720 * Current scratch register usage is as follows: 721 * 722 * SCRATCH0: FW Boot Status register 723 * SCRATCH5: LVTMA Status Register 724 * SCRATCH15: FW Boot Options register 725 */ 726 727 /** 728 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 729 */ 730 union dmub_fw_boot_status { 731 struct { 732 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 733 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 734 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 735 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 736 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 737 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 738 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 739 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 740 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 741 } bits; /**< status bits */ 742 uint32_t all; /**< 32-bit access to status bits */ 743 }; 744 745 /** 746 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 747 */ 748 enum dmub_fw_boot_status_bit { 749 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 750 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 751 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 752 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 753 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 754 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 755 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 756 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 757 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 758 }; 759 760 /* Register bit definition for SCRATCH5 */ 761 union dmub_lvtma_status { 762 struct { 763 uint32_t psp_ok : 1; 764 uint32_t edp_on : 1; 765 uint32_t reserved : 30; 766 } bits; 767 uint32_t all; 768 }; 769 770 enum dmub_lvtma_status_bit { 771 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 772 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 773 }; 774 775 enum dmub_ips_disable_type { 776 DMUB_IPS_ENABLE = 0, 777 DMUB_IPS_DISABLE_ALL = 1, 778 DMUB_IPS_DISABLE_IPS1 = 2, 779 DMUB_IPS_DISABLE_IPS2 = 3, 780 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 781 DMUB_IPS_DISABLE_DYNAMIC = 5, 782 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 783 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 784 }; 785 786 enum dmub_ips_rcg_disable_type { 787 DMUB_IPS_RCG_ENABLE = 0, 788 DMUB_IPS0_RCG_DISABLE = 1, 789 DMUB_IPS1_RCG_DISABLE = 2, 790 DMUB_IPS_RCG_DISABLE = 3 791 }; 792 793 enum dmub_ips_in_vpb_disable_type { 794 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 795 DMUB_IPS_VPB_DISABLE_ALL = 1, 796 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 797 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 798 }; 799 800 #define DMUB_IPS1_ALLOW_MASK 0x00000001 801 #define DMUB_IPS2_ALLOW_MASK 0x00000002 802 #define DMUB_IPS1_COMMIT_MASK 0x00000004 803 #define DMUB_IPS2_COMMIT_MASK 0x00000008 804 805 enum dmub_ips_comand_type { 806 /** 807 * Start/stop IPS residency measurements for a given IPS mode 808 */ 809 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 810 /** 811 * Query IPS residency information for a given IPS mode 812 */ 813 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 814 }; 815 816 /** 817 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 818 */ 819 union dmub_fw_boot_options { 820 struct { 821 uint32_t pemu_env : 1; /**< 1 if PEMU */ 822 uint32_t fpga_env : 1; /**< 1 if FPGA */ 823 uint32_t optimized_init : 1; /**< 1 if optimized init */ 824 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 825 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 826 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 827 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 828 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 829 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 830 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 831 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 832 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 833 uint32_t power_optimization: 1; 834 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 835 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 836 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 837 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 838 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 839 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 840 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 841 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 842 uint32_t ips_disable: 3; /* options to disable ips support*/ 843 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 844 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 845 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 846 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 847 uint32_t reserved : 5; /**< reserved */ 848 } bits; /**< boot bits */ 849 uint32_t all; /**< 32-bit access to bits */ 850 }; 851 852 enum dmub_fw_boot_options_bit { 853 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 854 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 855 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 856 }; 857 858 //============================================================================== 859 //< DMUB_SHARED_STATE>========================================================== 860 //============================================================================== 861 862 /** 863 * Shared firmware state between driver and firmware for lockless communication 864 * in situations where the inbox/outbox may be unavailable. 865 * 866 * Each structure *must* be at most 256-bytes in size. The layout allocation is 867 * described below: 868 * 869 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 870 */ 871 872 /** 873 * enum dmub_shared_state_feature_id - List of shared state features. 874 */ 875 enum dmub_shared_state_feature_id { 876 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 877 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 878 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 879 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 880 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 881 }; 882 883 /** 884 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 885 */ 886 union dmub_shared_state_ips_fw_signals { 887 struct { 888 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 889 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 890 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 891 uint32_t detection_required : 1; /**< 1 if detection is required */ 892 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 893 uint32_t reserved_bits : 27; /**< Reversed */ 894 } bits; 895 uint32_t all; 896 }; 897 898 /** 899 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 900 */ 901 union dmub_shared_state_ips_driver_signals { 902 struct { 903 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 904 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 905 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 906 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 907 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 908 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 909 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 910 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 911 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 912 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 913 uint32_t reserved_bits : 22; /**< Reversed bits */ 914 } bits; 915 uint32_t all; 916 }; 917 918 /** 919 * IPS FW Version 920 */ 921 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 922 923 struct dmub_shared_state_debug_setup { 924 union { 925 struct { 926 uint32_t exclude_points[62]; 927 } profile_mode; 928 }; 929 }; 930 931 /** 932 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 933 */ 934 struct dmub_shared_state_ips_fw { 935 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 936 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 937 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 938 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 939 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 940 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 941 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 942 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 943 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 944 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 945 }; /* 248-bytes, fixed */ 946 947 /** 948 * IPS Driver Version 949 */ 950 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 951 952 /** 953 * struct dmub_shared_state_ips_driver - Driver state for IPS. 954 */ 955 struct dmub_shared_state_ips_driver { 956 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 957 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 958 }; /* 248-bytes, fixed */ 959 960 /** 961 * enum dmub_shared_state_feature_common - Generic payload. 962 */ 963 struct dmub_shared_state_feature_common { 964 uint32_t padding[62]; 965 }; /* 248-bytes, fixed */ 966 967 /** 968 * enum dmub_shared_state_feature_header - Feature description. 969 */ 970 struct dmub_shared_state_feature_header { 971 uint16_t id; /**< Feature ID */ 972 uint16_t version; /**< Feature version */ 973 uint32_t reserved; /**< Reserved bytes. */ 974 }; /* 8 bytes, fixed */ 975 976 /** 977 * struct dmub_shared_state_feature_block - Feature block. 978 */ 979 struct dmub_shared_state_feature_block { 980 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 981 union dmub_shared_feature_state_union { 982 struct dmub_shared_state_feature_common common; /**< Generic data */ 983 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 984 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 985 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 986 } data; /**< Shared state data. */ 987 }; /* 256-bytes, fixed */ 988 989 /** 990 * Shared state size in bytes. 991 */ 992 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 993 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 994 995 //============================================================================== 996 //</DMUB_STATUS>================================================================ 997 //============================================================================== 998 //< DMUB_VBIOS>================================================================= 999 //============================================================================== 1000 1001 /* 1002 * enum dmub_cmd_vbios_type - VBIOS commands. 1003 * 1004 * Command IDs should be treated as stable ABI. 1005 * Do not reuse or modify IDs. 1006 */ 1007 enum dmub_cmd_vbios_type { 1008 /** 1009 * Configures the DIG encoder. 1010 */ 1011 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1012 /** 1013 * Controls the PHY. 1014 */ 1015 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1016 /** 1017 * Sets the pixel clock/symbol clock. 1018 */ 1019 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1020 /** 1021 * Enables or disables power gating. 1022 */ 1023 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1024 /** 1025 * Controls embedded panels. 1026 */ 1027 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1028 /** 1029 * Query DP alt status on a transmitter. 1030 */ 1031 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1032 /** 1033 * Control PHY FSM 1034 */ 1035 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1036 /** 1037 * Controls domain power gating 1038 */ 1039 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1040 }; 1041 1042 //============================================================================== 1043 //</DMUB_VBIOS>================================================================= 1044 //============================================================================== 1045 //< DMUB_GPINT>================================================================= 1046 //============================================================================== 1047 1048 /** 1049 * The shifts and masks below may alternatively be used to format and read 1050 * the command register bits. 1051 */ 1052 1053 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1054 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1055 1056 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1057 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1058 1059 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1060 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1061 1062 /** 1063 * Command responses. 1064 */ 1065 1066 /** 1067 * Return response for DMUB_GPINT__STOP_FW command. 1068 */ 1069 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1070 1071 /** 1072 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1073 */ 1074 union dmub_gpint_data_register { 1075 struct { 1076 uint32_t param : 16; /**< 16-bit parameter */ 1077 uint32_t command_code : 12; /**< GPINT command */ 1078 uint32_t status : 4; /**< Command status bit */ 1079 } bits; /**< GPINT bit access */ 1080 uint32_t all; /**< GPINT 32-bit access */ 1081 }; 1082 1083 /* 1084 * enum dmub_gpint_command - GPINT command to DMCUB FW 1085 * 1086 * Command IDs should be treated as stable ABI. 1087 * Do not reuse or modify IDs. 1088 */ 1089 enum dmub_gpint_command { 1090 /** 1091 * Invalid command, ignored. 1092 */ 1093 DMUB_GPINT__INVALID_COMMAND = 0, 1094 /** 1095 * DESC: Queries the firmware version. 1096 * RETURN: Firmware version. 1097 */ 1098 DMUB_GPINT__GET_FW_VERSION = 1, 1099 /** 1100 * DESC: Halts the firmware. 1101 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1102 */ 1103 DMUB_GPINT__STOP_FW = 2, 1104 /** 1105 * DESC: Get PSR state from FW. 1106 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1107 */ 1108 DMUB_GPINT__GET_PSR_STATE = 7, 1109 /** 1110 * DESC: Notifies DMCUB of the currently active streams. 1111 * ARGS: Stream mask, 1 bit per active stream index. 1112 */ 1113 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1114 /** 1115 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1116 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1117 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1118 * RETURN: PSR residency in milli-percent. 1119 */ 1120 DMUB_GPINT__PSR_RESIDENCY = 9, 1121 1122 /** 1123 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1124 */ 1125 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1126 1127 /** 1128 * DESC: Get REPLAY state from FW. 1129 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1130 */ 1131 DMUB_GPINT__GET_REPLAY_STATE = 13, 1132 1133 /** 1134 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1135 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1136 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1137 * RETURN: REPLAY residency in milli-percent. 1138 */ 1139 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1140 1141 /** 1142 * DESC: Copy bounding box to the host. 1143 * ARGS: Version of bounding box to copy 1144 * RETURN: Result of copying bounding box 1145 */ 1146 DMUB_GPINT__BB_COPY = 96, 1147 1148 /** 1149 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1150 * ARGS: The word3 for the 64 bit address 1151 */ 1152 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1153 1154 /** 1155 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1156 * ARGS: The word2 for the 64 bit address 1157 */ 1158 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1159 1160 /** 1161 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1162 * ARGS: The word1 for the 64 bit address 1163 */ 1164 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1165 1166 /** 1167 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1168 * ARGS: The word0 for the 64 bit address 1169 */ 1170 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1171 1172 /** 1173 * DESC: Updates the trace buffer lower 32-bit mask. 1174 * ARGS: The new mask 1175 * RETURN: Lower 32-bit mask. 1176 */ 1177 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1178 1179 /** 1180 * DESC: Updates the trace buffer mask bit0~bit15. 1181 * ARGS: The new mask 1182 * RETURN: Lower 32-bit mask. 1183 */ 1184 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1185 1186 /** 1187 * DESC: Updates the trace buffer mask bit16~bit31. 1188 * ARGS: The new mask 1189 * RETURN: Lower 32-bit mask. 1190 */ 1191 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1192 1193 /** 1194 * DESC: Updates the trace buffer mask bit32~bit47. 1195 * ARGS: The new mask 1196 * RETURN: Lower 32-bit mask. 1197 */ 1198 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1199 1200 /** 1201 * DESC: Updates the trace buffer mask bit48~bit63. 1202 * ARGS: The new mask 1203 * RETURN: Lower 32-bit mask. 1204 */ 1205 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1206 1207 /** 1208 * DESC: Read the trace buffer mask bi0~bit15. 1209 */ 1210 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1211 1212 /** 1213 * DESC: Read the trace buffer mask bit16~bit31. 1214 */ 1215 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1216 1217 /** 1218 * DESC: Read the trace buffer mask bi32~bit47. 1219 */ 1220 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1221 1222 /** 1223 * DESC: Updates the trace buffer mask bit32~bit63. 1224 */ 1225 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1226 1227 /** 1228 * DESC: Set IPS residency measurement 1229 * ARGS: 0 - Disable ips measurement 1230 * 1 - Enable ips measurement 1231 */ 1232 DMUB_GPINT__IPS_RESIDENCY = 121, 1233 1234 /** 1235 * DESC: Enable measurements for various task duration 1236 * ARGS: 0 - Disable measurement 1237 * 1 - Enable measurement 1238 */ 1239 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1240 1241 /** 1242 * DESC: Gets IPS residency in microseconds 1243 * ARGS: 0 - Return IPS1 residency 1244 * 1 - Return IPS2 residency 1245 * 2 - Return IPS1_RCG residency 1246 * 3 - Return IPS1_ONO2_ON residency 1247 * RETURN: Total residency in microseconds - lower 32 bits 1248 */ 1249 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1250 1251 /** 1252 * DESC: Gets IPS1 histogram counts 1253 * ARGS: Bucket index 1254 * RETURN: Total count for the bucket 1255 */ 1256 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1257 1258 /** 1259 * DESC: Gets IPS2 histogram counts 1260 * ARGS: Bucket index 1261 * RETURN: Total count for the bucket 1262 */ 1263 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1264 1265 /** 1266 * DESC: Gets IPS residency 1267 * ARGS: 0 - Return IPS1 residency 1268 * 1 - Return IPS2 residency 1269 * 2 - Return IPS1_RCG residency 1270 * 3 - Return IPS1_ONO2_ON residency 1271 * RETURN: Total residency in milli-percent. 1272 */ 1273 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1274 1275 /** 1276 * DESC: Gets IPS1_RCG histogram counts 1277 * ARGS: Bucket index 1278 * RETURN: Total count for the bucket 1279 */ 1280 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1281 1282 /** 1283 * DESC: Gets IPS1_ONO2_ON histogram counts 1284 * ARGS: Bucket index 1285 * RETURN: Total count for the bucket 1286 */ 1287 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1288 1289 /** 1290 * DESC: Gets IPS entry counter during residency measurement 1291 * ARGS: 0 - Return IPS1 entry counts 1292 * 1 - Return IPS2 entry counts 1293 * 2 - Return IPS1_RCG entry counts 1294 * 3 - Return IPS2_ONO2_ON entry counts 1295 * RETURN: Entry counter for selected IPS mode 1296 */ 1297 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1298 1299 /** 1300 * DESC: Gets IPS inactive residency in microseconds 1301 * ARGS: 0 - Return IPS1_MAX residency 1302 * 1 - Return IPS2 residency 1303 * 2 - Return IPS1_RCG residency 1304 * 3 - Return IPS1_ONO2_ON residency 1305 * RETURN: Total inactive residency in microseconds - lower 32 bits 1306 */ 1307 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1308 1309 /** 1310 * DESC: Gets IPS inactive residency in microseconds 1311 * ARGS: 0 - Return IPS1_MAX residency 1312 * 1 - Return IPS2 residency 1313 * 2 - Return IPS1_RCG residency 1314 * 3 - Return IPS1_ONO2_ON residency 1315 * RETURN: Total inactive residency in microseconds - upper 32 bits 1316 */ 1317 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1318 1319 /** 1320 * DESC: Gets IPS residency in microseconds 1321 * ARGS: 0 - Return IPS1 residency 1322 * 1 - Return IPS2 residency 1323 * 2 - Return IPS1_RCG residency 1324 * 3 - Return IPS1_ONO2_ON residency 1325 * RETURN: Total residency in microseconds - upper 32 bits 1326 */ 1327 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1328 /** 1329 * DESC: Setup debug configs. 1330 */ 1331 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1332 /** 1333 * DESC: Initiates IPS wake sequence. 1334 */ 1335 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1336 }; 1337 1338 /** 1339 * INBOX0 generic command definition 1340 */ 1341 union dmub_inbox0_cmd_common { 1342 struct { 1343 uint32_t command_code: 8; /**< INBOX0 command code */ 1344 uint32_t param: 24; /**< 24-bit parameter */ 1345 } bits; 1346 uint32_t all; 1347 }; 1348 1349 /** 1350 * INBOX0 hw_lock command definition 1351 */ 1352 union dmub_inbox0_cmd_lock_hw { 1353 struct { 1354 uint32_t command_code: 8; 1355 1356 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1357 uint32_t hw_lock_client: 2; 1358 1359 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1360 uint32_t otg_inst: 3; 1361 uint32_t opp_inst: 3; 1362 uint32_t dig_inst: 3; 1363 1364 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1365 uint32_t lock_pipe: 1; 1366 uint32_t lock_cursor: 1; 1367 uint32_t lock_dig: 1; 1368 uint32_t triple_buffer_lock: 1; 1369 1370 uint32_t lock: 1; /**< Lock */ 1371 uint32_t should_release: 1; /**< Release */ 1372 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1373 } bits; 1374 uint32_t all; 1375 }; 1376 1377 union dmub_inbox0_data_register { 1378 union dmub_inbox0_cmd_common inbox0_cmd_common; 1379 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1380 }; 1381 1382 enum dmub_inbox0_command { 1383 /** 1384 * DESC: Invalid command, ignored. 1385 */ 1386 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1387 /** 1388 * DESC: Notification to acquire/release HW lock 1389 * ARGS: 1390 */ 1391 DMUB_INBOX0_CMD__HW_LOCK = 1, 1392 }; 1393 //============================================================================== 1394 //</DMUB_GPINT>================================================================= 1395 //============================================================================== 1396 //< DMUB_CMD>=================================================================== 1397 //============================================================================== 1398 1399 /** 1400 * Size in bytes of each DMUB command. 1401 */ 1402 #define DMUB_RB_CMD_SIZE 64 1403 1404 /** 1405 * Maximum number of items in the DMUB ringbuffer. 1406 */ 1407 #define DMUB_RB_MAX_ENTRY 128 1408 1409 /** 1410 * Ringbuffer size in bytes. 1411 */ 1412 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1413 1414 /** 1415 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1416 */ 1417 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1418 1419 /** 1420 * Ringbuffer size in bytes. 1421 */ 1422 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1423 1424 /** 1425 * REG_SET mask for reg offload. 1426 */ 1427 #define REG_SET_MASK 0xFFFF 1428 1429 /* 1430 * enum dmub_cmd_type - DMUB inbox command. 1431 * 1432 * Command IDs should be treated as stable ABI. 1433 * Do not reuse or modify IDs. 1434 */ 1435 enum dmub_cmd_type { 1436 /** 1437 * Invalid command. 1438 */ 1439 DMUB_CMD__NULL = 0, 1440 /** 1441 * Read modify write register sequence offload. 1442 */ 1443 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1444 /** 1445 * Field update register sequence offload. 1446 */ 1447 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1448 /** 1449 * Burst write sequence offload. 1450 */ 1451 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1452 /** 1453 * Reg wait sequence offload. 1454 */ 1455 DMUB_CMD__REG_REG_WAIT = 4, 1456 /** 1457 * Workaround to avoid HUBP underflow during NV12 playback. 1458 */ 1459 DMUB_CMD__PLAT_54186_WA = 5, 1460 /** 1461 * Command type used to query FW feature caps. 1462 */ 1463 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1464 /** 1465 * Command type used to get visual confirm color. 1466 */ 1467 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1468 /** 1469 * Command type used for all PSR commands. 1470 */ 1471 DMUB_CMD__PSR = 64, 1472 /** 1473 * Command type used for all MALL commands. 1474 */ 1475 DMUB_CMD__MALL = 65, 1476 /** 1477 * Command type used for all ABM commands. 1478 */ 1479 DMUB_CMD__ABM = 66, 1480 /** 1481 * Command type used to update dirty rects in FW. 1482 */ 1483 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1484 /** 1485 * Command type used to update cursor info in FW. 1486 */ 1487 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1488 /** 1489 * Command type used for HW locking in FW. 1490 */ 1491 DMUB_CMD__HW_LOCK = 69, 1492 /** 1493 * Command type used to access DP AUX. 1494 */ 1495 DMUB_CMD__DP_AUX_ACCESS = 70, 1496 /** 1497 * Command type used for OUTBOX1 notification enable 1498 */ 1499 DMUB_CMD__OUTBOX1_ENABLE = 71, 1500 1501 /** 1502 * Command type used for all idle optimization commands. 1503 */ 1504 DMUB_CMD__IDLE_OPT = 72, 1505 /** 1506 * Command type used for all clock manager commands. 1507 */ 1508 DMUB_CMD__CLK_MGR = 73, 1509 /** 1510 * Command type used for all panel control commands. 1511 */ 1512 DMUB_CMD__PANEL_CNTL = 74, 1513 1514 /** 1515 * Command type used for all CAB commands. 1516 */ 1517 DMUB_CMD__CAB_FOR_SS = 75, 1518 1519 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1520 1521 /** 1522 * Command type used for interfacing with DPIA. 1523 */ 1524 DMUB_CMD__DPIA = 77, 1525 /** 1526 * Command type used for EDID CEA parsing 1527 */ 1528 DMUB_CMD__EDID_CEA = 79, 1529 /** 1530 * Command type used for getting usbc cable ID 1531 */ 1532 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1533 /** 1534 * Command type used to query HPD state. 1535 */ 1536 DMUB_CMD__QUERY_HPD_STATE = 82, 1537 /** 1538 * Command type used for all VBIOS interface commands. 1539 */ 1540 /** 1541 * Command type used for all REPLAY commands. 1542 */ 1543 DMUB_CMD__REPLAY = 83, 1544 1545 /** 1546 * Command type used for all SECURE_DISPLAY commands. 1547 */ 1548 DMUB_CMD__SECURE_DISPLAY = 85, 1549 1550 /** 1551 * Command type used to set DPIA HPD interrupt state 1552 */ 1553 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1554 1555 /** 1556 * Command type used for all PSP commands. 1557 */ 1558 DMUB_CMD__PSP = 88, 1559 1560 /** 1561 * Command type used for all Fused IO commands. 1562 */ 1563 DMUB_CMD__FUSED_IO = 89, 1564 1565 /** 1566 * Command type used for all LSDMA commands. 1567 */ 1568 DMUB_CMD__LSDMA = 90, 1569 1570 /** 1571 * Command type use for all IPS commands. 1572 */ 1573 DMUB_CMD__IPS = 91, 1574 1575 DMUB_CMD__VBIOS = 128, 1576 }; 1577 1578 /** 1579 * enum dmub_out_cmd_type - DMUB outbox commands. 1580 */ 1581 enum dmub_out_cmd_type { 1582 /** 1583 * Invalid outbox command, ignored. 1584 */ 1585 DMUB_OUT_CMD__NULL = 0, 1586 /** 1587 * Command type used for DP AUX Reply data notification 1588 */ 1589 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1590 /** 1591 * Command type used for DP HPD event notification 1592 */ 1593 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1594 /** 1595 * Command type used for SET_CONFIG Reply notification 1596 */ 1597 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1598 /** 1599 * Command type used for USB4 DPIA notification 1600 */ 1601 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1602 /** 1603 * Command type used for HPD redetect notification 1604 */ 1605 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1606 /** 1607 * Command type used for Fused IO notification 1608 */ 1609 DMUB_OUT_CMD__FUSED_IO = 7, 1610 }; 1611 1612 /* DMUB_CMD__DPIA command sub-types. */ 1613 enum dmub_cmd_dpia_type { 1614 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1615 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1616 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1617 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1618 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1619 }; 1620 1621 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1622 enum dmub_cmd_dpia_notification_type { 1623 DPIA_NOTIFY__BW_ALLOCATION = 0, 1624 }; 1625 1626 #pragma pack(push, 1) 1627 1628 /** 1629 * struct dmub_cmd_header - Common command header fields. 1630 */ 1631 struct dmub_cmd_header { 1632 unsigned int type : 8; /**< command type */ 1633 unsigned int sub_type : 8; /**< command sub type */ 1634 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1635 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1636 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1637 unsigned int reserved0 : 5; /**< reserved bits */ 1638 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1639 unsigned int reserved1 : 2; /**< reserved bits */ 1640 }; 1641 1642 /* 1643 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1644 * 1645 * 60 payload bytes can hold up to 5 sets of read modify writes, 1646 * each take 3 dwords. 1647 * 1648 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1649 * 1650 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1651 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1652 */ 1653 struct dmub_cmd_read_modify_write_sequence { 1654 uint32_t addr; /**< register address */ 1655 uint32_t modify_mask; /**< modify mask */ 1656 uint32_t modify_value; /**< modify value */ 1657 }; 1658 1659 /** 1660 * Maximum number of ops in read modify write sequence. 1661 */ 1662 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1663 1664 /** 1665 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1666 */ 1667 struct dmub_rb_cmd_read_modify_write { 1668 struct dmub_cmd_header header; /**< command header */ 1669 /** 1670 * Read modify write sequence. 1671 */ 1672 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1673 }; 1674 1675 /* 1676 * Update a register with specified masks and values sequeunce 1677 * 1678 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1679 * 1680 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1681 * 1682 * 1683 * USE CASE: 1684 * 1. auto-increment register where additional read would update pointer and produce wrong result 1685 * 2. toggle a bit without read in the middle 1686 */ 1687 1688 struct dmub_cmd_reg_field_update_sequence { 1689 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1690 uint32_t modify_value; /**< value to update with */ 1691 }; 1692 1693 /** 1694 * Maximum number of ops in field update sequence. 1695 */ 1696 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1697 1698 /** 1699 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1700 */ 1701 struct dmub_rb_cmd_reg_field_update_sequence { 1702 struct dmub_cmd_header header; /**< command header */ 1703 uint32_t addr; /**< register address */ 1704 /** 1705 * Field update sequence. 1706 */ 1707 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1708 }; 1709 1710 1711 /** 1712 * Maximum number of burst write values. 1713 */ 1714 #define DMUB_BURST_WRITE_VALUES__MAX 14 1715 1716 /* 1717 * struct dmub_rb_cmd_burst_write - Burst write 1718 * 1719 * support use case such as writing out LUTs. 1720 * 1721 * 60 payload bytes can hold up to 14 values to write to given address 1722 * 1723 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1724 */ 1725 struct dmub_rb_cmd_burst_write { 1726 struct dmub_cmd_header header; /**< command header */ 1727 uint32_t addr; /**< register start address */ 1728 /** 1729 * Burst write register values. 1730 */ 1731 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1732 }; 1733 1734 /** 1735 * struct dmub_rb_cmd_common - Common command header 1736 */ 1737 struct dmub_rb_cmd_common { 1738 struct dmub_cmd_header header; /**< command header */ 1739 /** 1740 * Padding to RB_CMD_SIZE 1741 */ 1742 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1743 }; 1744 1745 /** 1746 * struct dmub_cmd_reg_wait_data - Register wait data 1747 */ 1748 struct dmub_cmd_reg_wait_data { 1749 uint32_t addr; /**< Register address */ 1750 uint32_t mask; /**< Mask for register bits */ 1751 uint32_t condition_field_value; /**< Value to wait for */ 1752 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1753 }; 1754 1755 /** 1756 * struct dmub_rb_cmd_reg_wait - Register wait command 1757 */ 1758 struct dmub_rb_cmd_reg_wait { 1759 struct dmub_cmd_header header; /**< Command header */ 1760 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1761 }; 1762 1763 /** 1764 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1765 * 1766 * Reprograms surface parameters to avoid underflow. 1767 */ 1768 struct dmub_cmd_PLAT_54186_wa { 1769 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1770 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1771 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1772 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1773 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1774 struct { 1775 uint32_t hubp_inst : 4; /**< HUBP instance */ 1776 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1777 uint32_t immediate :1; /**< Immediate flip */ 1778 uint32_t vmid : 4; /**< VMID */ 1779 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1780 uint32_t reserved : 21; /**< Reserved */ 1781 } flip_params; /**< Pageflip parameters */ 1782 uint32_t reserved[9]; /**< Reserved bits */ 1783 }; 1784 1785 /** 1786 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1787 */ 1788 struct dmub_rb_cmd_PLAT_54186_wa { 1789 struct dmub_cmd_header header; /**< Command header */ 1790 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1791 }; 1792 1793 /** 1794 * enum dmub_cmd_mall_type - MALL commands 1795 */ 1796 enum dmub_cmd_mall_type { 1797 /** 1798 * Allows display refresh from MALL. 1799 */ 1800 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1801 /** 1802 * Disallows display refresh from MALL. 1803 */ 1804 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1805 /** 1806 * Cursor copy for MALL. 1807 */ 1808 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1809 /** 1810 * Controls DF requests. 1811 */ 1812 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1813 }; 1814 1815 /** 1816 * struct dmub_rb_cmd_mall - MALL command data. 1817 */ 1818 struct dmub_rb_cmd_mall { 1819 struct dmub_cmd_header header; /**< Common command header */ 1820 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1821 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1822 uint32_t tmr_delay; /**< Timer delay */ 1823 uint32_t tmr_scale; /**< Timer scale */ 1824 uint16_t cursor_width; /**< Cursor width in pixels */ 1825 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1826 uint16_t cursor_height; /**< Cursor height in pixels */ 1827 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1828 uint8_t debug_bits; /**< Debug bits */ 1829 1830 uint8_t reserved1; /**< Reserved bits */ 1831 uint8_t reserved2; /**< Reserved bits */ 1832 }; 1833 1834 /** 1835 * enum dmub_cmd_cab_type - CAB command data. 1836 */ 1837 enum dmub_cmd_cab_type { 1838 /** 1839 * No idle optimizations (i.e. no CAB) 1840 */ 1841 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1842 /** 1843 * No DCN requests for memory 1844 */ 1845 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1846 /** 1847 * Fit surfaces in CAB (i.e. CAB enable) 1848 */ 1849 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1850 /** 1851 * Do not fit surfaces in CAB (i.e. no CAB) 1852 */ 1853 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1854 }; 1855 1856 /** 1857 * struct dmub_rb_cmd_cab - CAB command data. 1858 */ 1859 struct dmub_rb_cmd_cab_for_ss { 1860 struct dmub_cmd_header header; 1861 uint8_t cab_alloc_ways; /* total number of ways */ 1862 uint8_t debug_bits; /* debug bits */ 1863 }; 1864 1865 /** 1866 * Enum for indicating which MCLK switch mode per pipe 1867 */ 1868 enum mclk_switch_mode { 1869 NONE = 0, 1870 FPO = 1, 1871 SUBVP = 2, 1872 VBLANK = 3, 1873 }; 1874 1875 /* Per pipe struct which stores the MCLK switch mode 1876 * data to be sent to DMUB. 1877 * Named "v2" for now -- once FPO and SUBVP are fully merged 1878 * the type name can be updated 1879 */ 1880 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1881 union { 1882 struct { 1883 uint32_t pix_clk_100hz; 1884 uint16_t main_vblank_start; 1885 uint16_t main_vblank_end; 1886 uint16_t mall_region_lines; 1887 uint16_t prefetch_lines; 1888 uint16_t prefetch_to_mall_start_lines; 1889 uint16_t processing_delay_lines; 1890 uint16_t htotal; // required to calculate line time for multi-display cases 1891 uint16_t vtotal; 1892 uint8_t main_pipe_index; 1893 uint8_t phantom_pipe_index; 1894 /* Since the microschedule is calculated in terms of OTG lines, 1895 * include any scaling factors to make sure when we get accurate 1896 * conversion when programming MALL_START_LINE (which is in terms 1897 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1898 * is 1/2 (numerator = 1, denominator = 2). 1899 */ 1900 uint8_t scale_factor_numerator; 1901 uint8_t scale_factor_denominator; 1902 uint8_t is_drr; 1903 uint8_t main_split_pipe_index; 1904 uint8_t phantom_split_pipe_index; 1905 } subvp_data; 1906 1907 struct { 1908 uint32_t pix_clk_100hz; 1909 uint16_t vblank_start; 1910 uint16_t vblank_end; 1911 uint16_t vstartup_start; 1912 uint16_t vtotal; 1913 uint16_t htotal; 1914 uint8_t vblank_pipe_index; 1915 uint8_t padding[1]; 1916 struct { 1917 uint8_t drr_in_use; 1918 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1919 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1920 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1921 uint8_t use_ramping; // Use ramping or not 1922 uint8_t drr_vblank_start_margin; 1923 } drr_info; // DRR considered as part of SubVP + VBLANK case 1924 } vblank_data; 1925 } pipe_config; 1926 1927 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1928 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1929 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1930 */ 1931 uint8_t mode; // enum mclk_switch_mode 1932 }; 1933 1934 /** 1935 * Config data for Sub-VP and FPO 1936 * Named "v2" for now -- once FPO and SUBVP are fully merged 1937 * the type name can be updated 1938 */ 1939 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1940 uint16_t watermark_a_cache; 1941 uint8_t vertical_int_margin_us; 1942 uint8_t pstate_allow_width_us; 1943 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1944 }; 1945 1946 /** 1947 * DMUB rb command definition for Sub-VP and FPO 1948 * Named "v2" for now -- once FPO and SUBVP are fully merged 1949 * the type name can be updated 1950 */ 1951 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1952 struct dmub_cmd_header header; 1953 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1954 }; 1955 1956 struct dmub_flip_addr_info { 1957 uint32_t surf_addr_lo; 1958 uint32_t surf_addr_c_lo; 1959 uint32_t meta_addr_lo; 1960 uint32_t meta_addr_c_lo; 1961 uint16_t surf_addr_hi; 1962 uint16_t surf_addr_c_hi; 1963 uint16_t meta_addr_hi; 1964 uint16_t meta_addr_c_hi; 1965 }; 1966 1967 struct dmub_fams2_flip_info { 1968 union { 1969 struct { 1970 uint8_t is_immediate: 1; 1971 } bits; 1972 uint8_t all; 1973 } config; 1974 uint8_t otg_inst; 1975 uint8_t pipe_mask; 1976 uint8_t pad; 1977 struct dmub_flip_addr_info addr_info; 1978 }; 1979 1980 struct dmub_rb_cmd_fams2_flip { 1981 struct dmub_cmd_header header; 1982 struct dmub_fams2_flip_info flip_info; 1983 }; 1984 1985 struct dmub_cmd_lsdma_data { 1986 union { 1987 struct lsdma_init_data { 1988 union dmub_addr gpu_addr_base; 1989 uint32_t ring_size; 1990 } init_data; 1991 struct lsdma_tiled_copy_data { 1992 uint32_t src_addr_lo; 1993 uint32_t src_addr_hi; 1994 1995 uint32_t dst_addr_lo; 1996 uint32_t dst_addr_hi; 1997 1998 uint32_t src_x : 16; 1999 uint32_t src_y : 16; 2000 2001 uint32_t dst_x : 16; 2002 uint32_t dst_y : 16; 2003 2004 uint32_t src_width : 16; 2005 uint32_t src_height : 16; 2006 2007 uint32_t dst_width : 16; 2008 uint32_t dst_height : 16; 2009 2010 uint32_t rect_x : 16; 2011 uint32_t rect_y : 16; 2012 2013 uint32_t src_swizzle_mode : 5; 2014 uint32_t src_mip_max : 5; 2015 uint32_t src_mip_id : 5; 2016 uint32_t dst_mip_max : 5; 2017 uint32_t dst_swizzle_mode : 5; 2018 uint32_t dst_mip_id : 5; 2019 uint32_t tmz : 1; 2020 uint32_t dcc : 1; 2021 2022 uint32_t data_format : 6; 2023 uint32_t padding1 : 4; 2024 uint32_t dst_element_size : 3; 2025 uint32_t num_type : 3; 2026 uint32_t src_element_size : 3; 2027 uint32_t write_compress : 2; 2028 uint32_t cache_policy_dst : 2; 2029 uint32_t cache_policy_src : 2; 2030 uint32_t read_compress : 2; 2031 uint32_t src_dim : 2; 2032 uint32_t dst_dim : 2; 2033 uint32_t max_uncom : 1; 2034 2035 uint32_t max_com : 2; 2036 uint32_t padding : 30; 2037 } tiled_copy_data; 2038 struct lsdma_linear_copy_data { 2039 uint32_t src_lo; 2040 uint32_t src_hi; 2041 2042 uint32_t dst_lo; 2043 uint32_t dst_hi; 2044 2045 uint32_t count : 30; 2046 uint32_t cache_policy_dst : 2; 2047 2048 uint32_t tmz : 1; 2049 uint32_t cache_policy_src : 2; 2050 uint32_t padding : 29; 2051 } linear_copy_data; 2052 struct lsdma_linear_sub_window_copy_data { 2053 uint32_t src_lo; 2054 uint32_t src_hi; 2055 2056 uint32_t dst_lo; 2057 uint32_t dst_hi; 2058 2059 uint32_t src_x : 16; 2060 uint32_t src_y : 16; 2061 2062 uint32_t dst_x : 16; 2063 uint32_t dst_y : 16; 2064 2065 uint32_t rect_x : 16; 2066 uint32_t rect_y : 16; 2067 2068 uint32_t src_pitch : 16; 2069 uint32_t dst_pitch : 16; 2070 2071 uint32_t src_slice_pitch; 2072 uint32_t dst_slice_pitch; 2073 2074 uint32_t tmz : 1; 2075 uint32_t element_size : 3; 2076 uint32_t src_cache_policy : 3; 2077 uint32_t dst_cache_policy : 3; 2078 uint32_t reserved0 : 22; 2079 } linear_sub_window_copy_data; 2080 struct lsdma_reg_write_data { 2081 uint32_t reg_addr; 2082 uint32_t reg_data; 2083 } reg_write_data; 2084 struct lsdma_pio_copy_data { 2085 uint32_t src_lo; 2086 uint32_t src_hi; 2087 2088 uint32_t dst_lo; 2089 uint32_t dst_hi; 2090 2091 union { 2092 struct { 2093 uint32_t byte_count : 26; 2094 uint32_t src_loc : 1; 2095 uint32_t dst_loc : 1; 2096 uint32_t src_addr_inc : 1; 2097 uint32_t dst_addr_inc : 1; 2098 uint32_t overlap_disable : 1; 2099 uint32_t constant_fill : 1; 2100 } fields; 2101 uint32_t raw; 2102 } packet; 2103 } pio_copy_data; 2104 struct lsdma_pio_constfill_data { 2105 uint32_t dst_lo; 2106 uint32_t dst_hi; 2107 2108 union { 2109 struct { 2110 uint32_t byte_count : 26; 2111 uint32_t src_loc : 1; 2112 uint32_t dst_loc : 1; 2113 uint32_t src_addr_inc : 1; 2114 uint32_t dst_addr_inc : 1; 2115 uint32_t overlap_disable : 1; 2116 uint32_t constant_fill : 1; 2117 } fields; 2118 uint32_t raw; 2119 } packet; 2120 2121 uint32_t data; 2122 } pio_constfill_data; 2123 2124 uint32_t all[14]; 2125 } u; 2126 }; 2127 2128 struct dmub_rb_cmd_lsdma { 2129 struct dmub_cmd_header header; 2130 struct dmub_cmd_lsdma_data lsdma_data; 2131 }; 2132 2133 struct dmub_optc_state_v2 { 2134 uint32_t v_total_min; 2135 uint32_t v_total_max; 2136 uint32_t v_total_mid; 2137 uint32_t v_total_mid_frame_num; 2138 uint8_t program_manual_trigger; 2139 uint8_t tg_inst; 2140 uint8_t pad[2]; 2141 }; 2142 2143 struct dmub_optc_position { 2144 uint32_t vpos; 2145 uint32_t hpos; 2146 uint32_t frame; 2147 }; 2148 2149 struct dmub_rb_cmd_fams2_drr_update { 2150 struct dmub_cmd_header header; 2151 struct dmub_optc_state_v2 dmub_optc_state_req; 2152 }; 2153 2154 /* HW and FW global configuration data for FAMS2 */ 2155 /* FAMS2 types and structs */ 2156 enum fams2_stream_type { 2157 FAMS2_STREAM_TYPE_NONE = 0, 2158 FAMS2_STREAM_TYPE_VBLANK = 1, 2159 FAMS2_STREAM_TYPE_VACTIVE = 2, 2160 FAMS2_STREAM_TYPE_DRR = 3, 2161 FAMS2_STREAM_TYPE_SUBVP = 4, 2162 }; 2163 2164 struct dmub_rect16 { 2165 /** 2166 * Dirty rect x offset. 2167 */ 2168 uint16_t x; 2169 2170 /** 2171 * Dirty rect y offset. 2172 */ 2173 uint16_t y; 2174 2175 /** 2176 * Dirty rect width. 2177 */ 2178 uint16_t width; 2179 2180 /** 2181 * Dirty rect height. 2182 */ 2183 uint16_t height; 2184 }; 2185 2186 /* static stream state */ 2187 struct dmub_fams2_legacy_stream_static_state { 2188 uint8_t vactive_det_fill_delay_otg_vlines; 2189 uint8_t programming_delay_otg_vlines; 2190 }; //v0 2191 2192 struct dmub_fams2_subvp_stream_static_state { 2193 uint16_t vratio_numerator; 2194 uint16_t vratio_denominator; 2195 uint16_t phantom_vtotal; 2196 uint16_t phantom_vactive; 2197 union { 2198 struct { 2199 uint8_t is_multi_planar : 1; 2200 uint8_t is_yuv420 : 1; 2201 } bits; 2202 uint8_t all; 2203 } config; 2204 uint8_t programming_delay_otg_vlines; 2205 uint8_t prefetch_to_mall_otg_vlines; 2206 uint8_t phantom_otg_inst; 2207 uint8_t phantom_pipe_mask; 2208 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2209 }; //v0 2210 2211 struct dmub_fams2_drr_stream_static_state { 2212 uint16_t nom_stretched_vtotal; 2213 uint8_t programming_delay_otg_vlines; 2214 uint8_t only_stretch_if_required; 2215 uint8_t pad[2]; 2216 }; //v0 2217 2218 struct dmub_fams2_cmd_legacy_stream_static_state { 2219 uint16_t vactive_det_fill_delay_otg_vlines; 2220 uint16_t programming_delay_otg_vlines; 2221 }; //v1 2222 2223 struct dmub_fams2_cmd_subvp_stream_static_state { 2224 uint16_t vratio_numerator; 2225 uint16_t vratio_denominator; 2226 uint16_t phantom_vtotal; 2227 uint16_t phantom_vactive; 2228 uint16_t programming_delay_otg_vlines; 2229 uint16_t prefetch_to_mall_otg_vlines; 2230 union { 2231 struct { 2232 uint8_t is_multi_planar : 1; 2233 uint8_t is_yuv420 : 1; 2234 } bits; 2235 uint8_t all; 2236 } config; 2237 uint8_t phantom_otg_inst; 2238 uint8_t phantom_pipe_mask; 2239 uint8_t pad0; 2240 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2241 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2242 }; //v1 2243 2244 struct dmub_fams2_cmd_drr_stream_static_state { 2245 uint16_t nom_stretched_vtotal; 2246 uint16_t programming_delay_otg_vlines; 2247 uint8_t only_stretch_if_required; 2248 uint8_t pad[3]; 2249 }; //v1 2250 2251 union dmub_fams2_stream_static_sub_state { 2252 struct dmub_fams2_legacy_stream_static_state legacy; 2253 struct dmub_fams2_subvp_stream_static_state subvp; 2254 struct dmub_fams2_drr_stream_static_state drr; 2255 }; //v0 2256 2257 union dmub_fams2_cmd_stream_static_sub_state { 2258 COMMON_STREAM_STATIC_SUB_STATE 2259 }; //v1 2260 2261 union dmub_fams2_stream_static_sub_state_v2 { 2262 COMMON_STREAM_STATIC_SUB_STATE 2263 }; //v2 2264 2265 struct dmub_fams2_stream_static_state { 2266 enum fams2_stream_type type; 2267 uint32_t otg_vline_time_ns; 2268 uint32_t otg_vline_time_ticks; 2269 uint16_t htotal; 2270 uint16_t vtotal; // nominal vtotal 2271 uint16_t vblank_start; 2272 uint16_t vblank_end; 2273 uint16_t max_vtotal; 2274 uint16_t allow_start_otg_vline; 2275 uint16_t allow_end_otg_vline; 2276 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2277 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2278 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2279 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2280 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2281 union { 2282 struct { 2283 uint8_t is_drr: 1; // stream is DRR enabled 2284 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2285 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2286 } bits; 2287 uint8_t all; 2288 } config; 2289 uint8_t otg_inst; 2290 uint8_t pipe_mask; // pipe mask for the whole config 2291 uint8_t num_planes; 2292 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2293 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2294 union dmub_fams2_stream_static_sub_state sub_state; 2295 }; //v0 2296 2297 struct dmub_fams2_cmd_stream_static_base_state { 2298 enum fams2_stream_type type; 2299 uint32_t otg_vline_time_ns; 2300 uint32_t otg_vline_time_ticks; 2301 uint16_t htotal; 2302 uint16_t vtotal; // nominal vtotal 2303 uint16_t vblank_start; 2304 uint16_t vblank_end; 2305 uint16_t max_vtotal; 2306 uint16_t allow_start_otg_vline; 2307 uint16_t allow_end_otg_vline; 2308 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2309 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2310 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2311 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2312 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2313 union { 2314 struct { 2315 uint8_t is_drr : 1; // stream is DRR enabled 2316 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2317 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2318 } bits; 2319 uint8_t all; 2320 } config; 2321 uint8_t otg_inst; 2322 uint8_t pipe_mask; // pipe mask for the whole config 2323 uint8_t num_planes; 2324 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2325 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2326 }; //v1 2327 2328 struct dmub_fams2_stream_static_state_v1 { 2329 struct dmub_fams2_cmd_stream_static_base_state base; 2330 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2331 }; //v1 2332 2333 /** 2334 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2335 * p-state request to allow latency 2336 */ 2337 enum dmub_fams2_allow_delay_check_mode { 2338 /* No check for request to allow delay */ 2339 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2340 /* Check for request to allow delay */ 2341 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2342 /* Check for prepare to allow delay */ 2343 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2344 }; 2345 2346 union dmub_fams2_global_feature_config { 2347 struct { 2348 uint32_t enable: 1; 2349 uint32_t enable_ppt_check: 1; 2350 uint32_t enable_stall_recovery: 1; 2351 uint32_t enable_debug: 1; 2352 uint32_t enable_offload_flip: 1; 2353 uint32_t enable_visual_confirm: 1; 2354 uint32_t allow_delay_check_mode: 2; 2355 uint32_t reserved: 24; 2356 } bits; 2357 uint32_t all; 2358 }; 2359 2360 struct dmub_cmd_fams2_global_config { 2361 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2362 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2363 uint32_t num_streams; 2364 union dmub_fams2_global_feature_config features; 2365 uint32_t recovery_timeout_us; 2366 uint32_t hwfq_flip_programming_delay_us; 2367 uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target 2368 }; 2369 2370 union dmub_cmd_fams2_config { 2371 struct dmub_cmd_fams2_global_config global; 2372 struct dmub_fams2_stream_static_state stream; //v0 2373 union { 2374 struct dmub_fams2_cmd_stream_static_base_state base; 2375 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2376 } stream_v1; //v1 2377 }; 2378 2379 struct dmub_fams2_config_v2 { 2380 struct dmub_cmd_fams2_global_config global; 2381 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2382 }; 2383 2384 /** 2385 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2386 */ 2387 struct dmub_rb_cmd_fams2 { 2388 struct dmub_cmd_header header; 2389 union dmub_cmd_fams2_config config; 2390 }; 2391 2392 /** 2393 * Indirect buffer descriptor 2394 */ 2395 struct dmub_ib_data { 2396 union dmub_addr src; // location of indirect buffer in memory 2397 uint16_t size; // indirect buffer size in bytes 2398 }; 2399 2400 /** 2401 * DMUB rb command definition for commands passed over indirect buffer 2402 */ 2403 struct dmub_rb_cmd_ib { 2404 struct dmub_cmd_header header; 2405 struct dmub_ib_data ib_data; 2406 }; 2407 2408 /** 2409 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2410 */ 2411 enum dmub_cmd_idle_opt_type { 2412 /** 2413 * DCN hardware restore. 2414 */ 2415 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2416 2417 /** 2418 * DCN hardware save. 2419 */ 2420 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2421 2422 /** 2423 * DCN hardware notify idle. 2424 */ 2425 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2426 2427 /** 2428 * DCN hardware notify power state. 2429 */ 2430 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2431 2432 /** 2433 * DCN notify to release HW. 2434 */ 2435 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2436 }; 2437 2438 /** 2439 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2440 */ 2441 struct dmub_rb_cmd_idle_opt_dcn_restore { 2442 struct dmub_cmd_header header; /**< header */ 2443 }; 2444 2445 /** 2446 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2447 */ 2448 struct dmub_dcn_notify_idle_cntl_data { 2449 uint8_t driver_idle; 2450 uint8_t skip_otg_disable; 2451 uint8_t reserved[58]; 2452 }; 2453 2454 /** 2455 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2456 */ 2457 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2458 struct dmub_cmd_header header; /**< header */ 2459 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2460 }; 2461 2462 /** 2463 * enum dmub_idle_opt_dc_power_state - DC power states. 2464 */ 2465 enum dmub_idle_opt_dc_power_state { 2466 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2467 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2468 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2469 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2470 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2471 }; 2472 2473 /** 2474 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2475 */ 2476 struct dmub_idle_opt_set_dc_power_state_data { 2477 uint8_t power_state; /**< power state */ 2478 uint8_t pad[3]; /**< padding */ 2479 }; 2480 2481 /** 2482 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2483 */ 2484 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2485 struct dmub_cmd_header header; /**< header */ 2486 struct dmub_idle_opt_set_dc_power_state_data data; 2487 }; 2488 2489 /** 2490 * struct dmub_clocks - Clock update notification. 2491 */ 2492 struct dmub_clocks { 2493 uint32_t dispclk_khz; /**< dispclk kHz */ 2494 uint32_t dppclk_khz; /**< dppclk kHz */ 2495 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2496 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2497 }; 2498 2499 /** 2500 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2501 */ 2502 enum dmub_cmd_clk_mgr_type { 2503 /** 2504 * Notify DMCUB of clock update. 2505 */ 2506 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2507 }; 2508 2509 /** 2510 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2511 */ 2512 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2513 struct dmub_cmd_header header; /**< header */ 2514 struct dmub_clocks clocks; /**< clock data */ 2515 }; 2516 2517 /** 2518 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2519 */ 2520 struct dmub_cmd_digx_encoder_control_data { 2521 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2522 }; 2523 2524 /** 2525 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2526 */ 2527 struct dmub_rb_cmd_digx_encoder_control { 2528 struct dmub_cmd_header header; /**< header */ 2529 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2530 }; 2531 2532 /** 2533 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2534 */ 2535 struct dmub_cmd_set_pixel_clock_data { 2536 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2537 }; 2538 2539 /** 2540 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2541 */ 2542 struct dmub_rb_cmd_set_pixel_clock { 2543 struct dmub_cmd_header header; /**< header */ 2544 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2545 }; 2546 2547 /** 2548 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2549 */ 2550 struct dmub_cmd_enable_disp_power_gating_data { 2551 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2552 }; 2553 2554 /** 2555 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2556 */ 2557 struct dmub_rb_cmd_enable_disp_power_gating { 2558 struct dmub_cmd_header header; /**< header */ 2559 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2560 }; 2561 2562 /** 2563 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2564 */ 2565 struct dmub_dig_transmitter_control_data_v1_7 { 2566 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2567 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2568 union { 2569 uint8_t digmode; /**< enum atom_encode_mode_def */ 2570 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2571 } mode_laneset; 2572 uint8_t lanenum; /**< Number of lanes */ 2573 union { 2574 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2575 } symclk_units; 2576 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2577 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2578 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2579 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2580 uint8_t reserved1; /**< For future use */ 2581 uint8_t skip_phy_ssc_reduction; 2582 uint8_t reserved2[2]; /**< For future use */ 2583 uint32_t reserved3[11]; /**< For future use */ 2584 }; 2585 2586 /** 2587 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2588 */ 2589 union dmub_cmd_dig1_transmitter_control_data { 2590 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2591 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2592 }; 2593 2594 /** 2595 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2596 */ 2597 struct dmub_rb_cmd_dig1_transmitter_control { 2598 struct dmub_cmd_header header; /**< header */ 2599 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2600 }; 2601 2602 /** 2603 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2604 */ 2605 struct dmub_rb_cmd_domain_control_data { 2606 uint8_t inst : 6; /**< DOMAIN instance to control */ 2607 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2608 uint8_t reserved[3]; /**< Reserved for future use */ 2609 }; 2610 2611 /** 2612 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2613 */ 2614 struct dmub_rb_cmd_domain_control { 2615 struct dmub_cmd_header header; /**< header */ 2616 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2617 }; 2618 2619 /** 2620 * DPIA tunnel command parameters. 2621 */ 2622 struct dmub_cmd_dig_dpia_control_data { 2623 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2624 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2625 union { 2626 uint8_t digmode; /** enum atom_encode_mode_def */ 2627 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2628 } mode_laneset; 2629 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2630 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2631 uint8_t hpdsel; /** =0: HPD is not assigned */ 2632 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2633 uint8_t dpia_id; /** Index of DPIA */ 2634 uint8_t fec_rdy : 1; 2635 uint8_t reserved : 7; 2636 uint32_t reserved1; 2637 }; 2638 2639 /** 2640 * DMUB command for DPIA tunnel control. 2641 */ 2642 struct dmub_rb_cmd_dig1_dpia_control { 2643 struct dmub_cmd_header header; 2644 struct dmub_cmd_dig_dpia_control_data dpia_control; 2645 }; 2646 2647 /** 2648 * SET_CONFIG Command Payload (deprecated) 2649 */ 2650 struct set_config_cmd_payload { 2651 uint8_t msg_type; /* set config message type */ 2652 uint8_t msg_data; /* set config message data */ 2653 }; 2654 2655 /** 2656 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2657 */ 2658 struct dmub_cmd_set_config_control_data { 2659 struct set_config_cmd_payload cmd_pkt; 2660 uint8_t instance; /* DPIA instance */ 2661 uint8_t immed_status; /* Immediate status returned in case of error */ 2662 }; 2663 2664 /** 2665 * SET_CONFIG Request Command Payload 2666 */ 2667 struct set_config_request_cmd_payload { 2668 uint8_t instance; /* DPIA instance */ 2669 uint8_t immed_status; /* Immediate status returned in case of error */ 2670 uint8_t msg_type; /* set config message type */ 2671 uint8_t reserved; 2672 uint32_t msg_data; /* set config message data */ 2673 }; 2674 2675 /** 2676 * DMUB command structure for SET_CONFIG command. 2677 */ 2678 struct dmub_rb_cmd_set_config_access { 2679 struct dmub_cmd_header header; /* header */ 2680 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2681 }; 2682 2683 /** 2684 * DMUB command structure for SET_CONFIG request command. 2685 */ 2686 struct dmub_rb_cmd_set_config_request { 2687 struct dmub_cmd_header header; /* header */ 2688 struct set_config_request_cmd_payload payload; /* set config request payload */ 2689 }; 2690 2691 /** 2692 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2693 */ 2694 struct dmub_cmd_mst_alloc_slots_control_data { 2695 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2696 uint8_t instance; /* DPIA instance */ 2697 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2698 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2699 }; 2700 2701 /** 2702 * DMUB command structure for SET_ command. 2703 */ 2704 struct dmub_rb_cmd_set_mst_alloc_slots { 2705 struct dmub_cmd_header header; /* header */ 2706 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2707 }; 2708 2709 /** 2710 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2711 */ 2712 struct dmub_cmd_tps_notification_data { 2713 uint8_t instance; /* DPIA instance */ 2714 uint8_t tps; /* requested training pattern */ 2715 uint8_t reserved1; 2716 uint8_t reserved2; 2717 }; 2718 2719 /** 2720 * DMUB command structure for SET_TPS_NOTIFICATION command. 2721 */ 2722 struct dmub_rb_cmd_set_tps_notification { 2723 struct dmub_cmd_header header; /* header */ 2724 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2725 }; 2726 2727 /** 2728 * DMUB command structure for DPIA HPD int enable control. 2729 */ 2730 struct dmub_rb_cmd_dpia_hpd_int_enable { 2731 struct dmub_cmd_header header; /* header */ 2732 uint32_t enable; /* dpia hpd interrupt enable */ 2733 }; 2734 2735 /** 2736 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2737 */ 2738 struct dmub_rb_cmd_dpphy_init { 2739 struct dmub_cmd_header header; /**< header */ 2740 uint8_t reserved[60]; /**< reserved bits */ 2741 }; 2742 2743 /** 2744 * enum dp_aux_request_action - DP AUX request command listing. 2745 * 2746 * 4 AUX request command bits are shifted to high nibble. 2747 */ 2748 enum dp_aux_request_action { 2749 /** I2C-over-AUX write request */ 2750 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2751 /** I2C-over-AUX read request */ 2752 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2753 /** I2C-over-AUX write status request */ 2754 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2755 /** I2C-over-AUX write request with MOT=1 */ 2756 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2757 /** I2C-over-AUX read request with MOT=1 */ 2758 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2759 /** I2C-over-AUX write status request with MOT=1 */ 2760 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2761 /** Native AUX write request */ 2762 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2763 /** Native AUX read request */ 2764 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2765 }; 2766 2767 /** 2768 * enum aux_return_code_type - DP AUX process return code listing. 2769 */ 2770 enum aux_return_code_type { 2771 /** AUX process succeeded */ 2772 AUX_RET_SUCCESS = 0, 2773 /** AUX process failed with unknown reason */ 2774 AUX_RET_ERROR_UNKNOWN, 2775 /** AUX process completed with invalid reply */ 2776 AUX_RET_ERROR_INVALID_REPLY, 2777 /** AUX process timed out */ 2778 AUX_RET_ERROR_TIMEOUT, 2779 /** HPD was low during AUX process */ 2780 AUX_RET_ERROR_HPD_DISCON, 2781 /** Failed to acquire AUX engine */ 2782 AUX_RET_ERROR_ENGINE_ACQUIRE, 2783 /** AUX request not supported */ 2784 AUX_RET_ERROR_INVALID_OPERATION, 2785 /** AUX process not available */ 2786 AUX_RET_ERROR_PROTOCOL_ERROR, 2787 }; 2788 2789 /** 2790 * enum aux_channel_type - DP AUX channel type listing. 2791 */ 2792 enum aux_channel_type { 2793 /** AUX thru Legacy DP AUX */ 2794 AUX_CHANNEL_LEGACY_DDC, 2795 /** AUX thru DPIA DP tunneling */ 2796 AUX_CHANNEL_DPIA 2797 }; 2798 2799 /** 2800 * struct aux_transaction_parameters - DP AUX request transaction data 2801 */ 2802 struct aux_transaction_parameters { 2803 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2804 uint8_t action; /**< enum dp_aux_request_action */ 2805 uint8_t length; /**< DP AUX request data length */ 2806 uint8_t reserved; /**< For future use */ 2807 uint32_t address; /**< DP AUX address */ 2808 uint8_t data[16]; /**< DP AUX write data */ 2809 }; 2810 2811 /** 2812 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2813 */ 2814 struct dmub_cmd_dp_aux_control_data { 2815 uint8_t instance; /**< AUX instance or DPIA instance */ 2816 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2817 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2818 uint8_t reserved0; /**< For future use */ 2819 uint16_t timeout; /**< timeout time in us */ 2820 uint16_t reserved1; /**< For future use */ 2821 enum aux_channel_type type; /**< enum aux_channel_type */ 2822 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2823 }; 2824 2825 /** 2826 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2827 */ 2828 struct dmub_rb_cmd_dp_aux_access { 2829 /** 2830 * Command header. 2831 */ 2832 struct dmub_cmd_header header; 2833 /** 2834 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2835 */ 2836 struct dmub_cmd_dp_aux_control_data aux_control; 2837 }; 2838 2839 /** 2840 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2841 */ 2842 struct dmub_rb_cmd_outbox1_enable { 2843 /** 2844 * Command header. 2845 */ 2846 struct dmub_cmd_header header; 2847 /** 2848 * enable: 0x0 -> disable outbox1 notification (default value) 2849 * 0x1 -> enable outbox1 notification 2850 */ 2851 uint32_t enable; 2852 }; 2853 2854 /* DP AUX Reply command - OutBox Cmd */ 2855 /** 2856 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2857 */ 2858 struct aux_reply_data { 2859 /** 2860 * Aux cmd 2861 */ 2862 uint8_t command; 2863 /** 2864 * Aux reply data length (max: 16 bytes) 2865 */ 2866 uint8_t length; 2867 /** 2868 * Alignment only 2869 */ 2870 uint8_t pad[2]; 2871 /** 2872 * Aux reply data 2873 */ 2874 uint8_t data[16]; 2875 }; 2876 2877 /** 2878 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2879 */ 2880 struct aux_reply_control_data { 2881 /** 2882 * Reserved for future use 2883 */ 2884 uint32_t handle; 2885 /** 2886 * Aux Instance 2887 */ 2888 uint8_t instance; 2889 /** 2890 * Aux transaction result: definition in enum aux_return_code_type 2891 */ 2892 uint8_t result; 2893 /** 2894 * Alignment only 2895 */ 2896 uint16_t pad; 2897 }; 2898 2899 /** 2900 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2901 */ 2902 struct dmub_rb_cmd_dp_aux_reply { 2903 /** 2904 * Command header. 2905 */ 2906 struct dmub_cmd_header header; 2907 /** 2908 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2909 */ 2910 struct aux_reply_control_data control; 2911 /** 2912 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2913 */ 2914 struct aux_reply_data reply_data; 2915 }; 2916 2917 /* DP HPD Notify command - OutBox Cmd */ 2918 /** 2919 * DP HPD Type 2920 */ 2921 enum dp_hpd_type { 2922 /** 2923 * Normal DP HPD 2924 */ 2925 DP_HPD = 0, 2926 /** 2927 * DP HPD short pulse 2928 */ 2929 DP_IRQ = 1, 2930 /** 2931 * Failure to acquire DP HPD state 2932 */ 2933 DP_NONE_HPD = 2 2934 }; 2935 2936 /** 2937 * DP HPD Status 2938 */ 2939 enum dp_hpd_status { 2940 /** 2941 * DP_HPD status low 2942 */ 2943 DP_HPD_UNPLUG = 0, 2944 /** 2945 * DP_HPD status high 2946 */ 2947 DP_HPD_PLUG 2948 }; 2949 2950 /** 2951 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2952 */ 2953 struct dp_hpd_data { 2954 /** 2955 * DP HPD instance 2956 */ 2957 uint8_t instance; 2958 /** 2959 * HPD type 2960 */ 2961 uint8_t hpd_type; 2962 /** 2963 * HPD status: only for type: DP_HPD to indicate status 2964 */ 2965 uint8_t hpd_status; 2966 /** 2967 * Alignment only 2968 */ 2969 uint8_t pad; 2970 }; 2971 2972 /** 2973 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2974 */ 2975 struct dmub_rb_cmd_dp_hpd_notify { 2976 /** 2977 * Command header. 2978 */ 2979 struct dmub_cmd_header header; 2980 /** 2981 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2982 */ 2983 struct dp_hpd_data hpd_data; 2984 }; 2985 2986 /** 2987 * Definition of a SET_CONFIG reply from DPOA. 2988 */ 2989 enum set_config_status { 2990 SET_CONFIG_PENDING = 0, 2991 SET_CONFIG_ACK_RECEIVED, 2992 SET_CONFIG_RX_TIMEOUT, 2993 SET_CONFIG_UNKNOWN_ERROR, 2994 }; 2995 2996 /** 2997 * Definition of a set_config reply 2998 */ 2999 struct set_config_reply_control_data { 3000 uint8_t instance; /* DPIA Instance */ 3001 uint8_t status; /* Set Config reply */ 3002 uint16_t pad; /* Alignment */ 3003 }; 3004 3005 /** 3006 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 3007 */ 3008 struct dmub_rb_cmd_dp_set_config_reply { 3009 struct dmub_cmd_header header; 3010 struct set_config_reply_control_data set_config_reply_control; 3011 }; 3012 3013 /** 3014 * Definition of a DPIA notification header 3015 */ 3016 struct dpia_notification_header { 3017 uint8_t instance; /**< DPIA Instance */ 3018 uint8_t reserved[3]; 3019 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 3020 }; 3021 3022 /** 3023 * Definition of the common data struct of DPIA notification 3024 */ 3025 struct dpia_notification_common { 3026 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 3027 - sizeof(struct dpia_notification_header)]; 3028 }; 3029 3030 /** 3031 * Definition of a DPIA notification data 3032 */ 3033 struct dpia_bw_allocation_notify_data { 3034 union { 3035 struct { 3036 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3037 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3038 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3039 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3040 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3041 uint16_t reserved: 11; /**< Reserved */ 3042 } bits; 3043 3044 uint16_t flags; 3045 }; 3046 3047 uint8_t cm_id; /**< CM ID */ 3048 uint8_t group_id; /**< Group ID */ 3049 uint8_t granularity; /**< BW Allocation Granularity */ 3050 uint8_t estimated_bw; /**< Estimated_BW */ 3051 uint8_t allocated_bw; /**< Allocated_BW */ 3052 uint8_t reserved; 3053 }; 3054 3055 /** 3056 * union dpia_notify_data_type - DPIA Notification in Outbox command 3057 */ 3058 union dpia_notification_data { 3059 /** 3060 * DPIA Notification for common data struct 3061 */ 3062 struct dpia_notification_common common_data; 3063 3064 /** 3065 * DPIA Notification for DP BW Allocation support 3066 */ 3067 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3068 }; 3069 3070 /** 3071 * Definition of a DPIA notification payload 3072 */ 3073 struct dpia_notification_payload { 3074 struct dpia_notification_header header; 3075 union dpia_notification_data data; /**< DPIA notification payload data */ 3076 }; 3077 3078 /** 3079 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3080 */ 3081 struct dmub_rb_cmd_dpia_notification { 3082 struct dmub_cmd_header header; /**< DPIA notification header */ 3083 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3084 }; 3085 3086 /** 3087 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3088 */ 3089 struct dmub_cmd_hpd_state_query_data { 3090 uint8_t instance; /**< HPD instance or DPIA instance */ 3091 uint8_t result; /**< For returning HPD state */ 3092 uint16_t pad; /** < Alignment */ 3093 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3094 enum aux_return_code_type status; /**< for returning the status of command */ 3095 }; 3096 3097 /** 3098 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3099 */ 3100 struct dmub_rb_cmd_query_hpd_state { 3101 /** 3102 * Command header. 3103 */ 3104 struct dmub_cmd_header header; 3105 /** 3106 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3107 */ 3108 struct dmub_cmd_hpd_state_query_data data; 3109 }; 3110 3111 /** 3112 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3113 */ 3114 struct dmub_rb_cmd_hpd_sense_notify_data { 3115 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3116 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3117 }; 3118 3119 /** 3120 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3121 */ 3122 struct dmub_rb_cmd_hpd_sense_notify { 3123 struct dmub_cmd_header header; /**< header */ 3124 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3125 }; 3126 3127 /* 3128 * Command IDs should be treated as stable ABI. 3129 * Do not reuse or modify IDs. 3130 */ 3131 3132 /** 3133 * PSR command sub-types. 3134 */ 3135 enum dmub_cmd_psr_type { 3136 /** 3137 * Set PSR version support. 3138 */ 3139 DMUB_CMD__PSR_SET_VERSION = 0, 3140 /** 3141 * Copy driver-calculated parameters to PSR state. 3142 */ 3143 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3144 /** 3145 * Enable PSR. 3146 */ 3147 DMUB_CMD__PSR_ENABLE = 2, 3148 3149 /** 3150 * Disable PSR. 3151 */ 3152 DMUB_CMD__PSR_DISABLE = 3, 3153 3154 /** 3155 * Set PSR level. 3156 * PSR level is a 16-bit value dicated by driver that 3157 * will enable/disable different functionality. 3158 */ 3159 DMUB_CMD__PSR_SET_LEVEL = 4, 3160 3161 /** 3162 * Forces PSR enabled until an explicit PSR disable call. 3163 */ 3164 DMUB_CMD__PSR_FORCE_STATIC = 5, 3165 /** 3166 * Set vtotal in psr active for FreeSync PSR. 3167 */ 3168 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3169 /** 3170 * Set PSR power option 3171 */ 3172 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3173 }; 3174 3175 /** 3176 * Different PSR residency modes. 3177 * Different modes change the definition of PSR residency. 3178 */ 3179 enum psr_residency_mode { 3180 PSR_RESIDENCY_MODE_PHY = 0, 3181 PSR_RESIDENCY_MODE_ALPM, 3182 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3183 /* Do not add below. */ 3184 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3185 }; 3186 3187 enum dmub_cmd_fams_type { 3188 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3189 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3190 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3191 /** 3192 * For SubVP set manual trigger in FW because it 3193 * triggers DRR_UPDATE_PENDING which SubVP relies 3194 * on (for any SubVP cases that use a DRR display) 3195 */ 3196 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3197 DMUB_CMD__FAMS2_CONFIG = 4, 3198 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3199 DMUB_CMD__FAMS2_FLIP = 6, 3200 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3201 }; 3202 3203 /** 3204 * PSR versions. 3205 */ 3206 enum psr_version { 3207 /** 3208 * PSR version 1. 3209 */ 3210 PSR_VERSION_1 = 0, 3211 /** 3212 * Freesync PSR SU. 3213 */ 3214 PSR_VERSION_SU_1 = 1, 3215 /** 3216 * PSR not supported. 3217 */ 3218 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3219 }; 3220 3221 /** 3222 * PHY Link rate for DP. 3223 */ 3224 enum phy_link_rate { 3225 /** 3226 * not supported. 3227 */ 3228 PHY_RATE_UNKNOWN = 0, 3229 /** 3230 * Rate_1 (RBR) - 1.62 Gbps/Lane 3231 */ 3232 PHY_RATE_162 = 1, 3233 /** 3234 * Rate_2 - 2.16 Gbps/Lane 3235 */ 3236 PHY_RATE_216 = 2, 3237 /** 3238 * Rate_3 - 2.43 Gbps/Lane 3239 */ 3240 PHY_RATE_243 = 3, 3241 /** 3242 * Rate_4 (HBR) - 2.70 Gbps/Lane 3243 */ 3244 PHY_RATE_270 = 4, 3245 /** 3246 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3247 */ 3248 PHY_RATE_324 = 5, 3249 /** 3250 * Rate_6 - 4.32 Gbps/Lane 3251 */ 3252 PHY_RATE_432 = 6, 3253 /** 3254 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3255 */ 3256 PHY_RATE_540 = 7, 3257 /** 3258 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3259 */ 3260 PHY_RATE_810 = 8, 3261 /** 3262 * UHBR10 - 10.0 Gbps/Lane 3263 */ 3264 PHY_RATE_1000 = 9, 3265 /** 3266 * UHBR13.5 - 13.5 Gbps/Lane 3267 */ 3268 PHY_RATE_1350 = 10, 3269 /** 3270 * UHBR10 - 20.0 Gbps/Lane 3271 */ 3272 PHY_RATE_2000 = 11, 3273 3274 PHY_RATE_675 = 12, 3275 /** 3276 * Rate 12 - 6.75 Gbps/Lane 3277 */ 3278 }; 3279 3280 /** 3281 * enum dmub_phy_fsm_state - PHY FSM states. 3282 * PHY FSM state to transit to during PSR enable/disable. 3283 */ 3284 enum dmub_phy_fsm_state { 3285 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3286 DMUB_PHY_FSM_RESET, 3287 DMUB_PHY_FSM_RESET_RELEASED, 3288 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3289 DMUB_PHY_FSM_INITIALIZED, 3290 DMUB_PHY_FSM_CALIBRATED, 3291 DMUB_PHY_FSM_CALIBRATED_LP, 3292 DMUB_PHY_FSM_CALIBRATED_PG, 3293 DMUB_PHY_FSM_POWER_DOWN, 3294 DMUB_PHY_FSM_PLL_EN, 3295 DMUB_PHY_FSM_TX_EN, 3296 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3297 DMUB_PHY_FSM_FAST_LP, 3298 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3299 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3300 DMUB_PHY_FSM_P2_PLL_OFF, 3301 DMUB_PHY_FSM_P2_PLL_ON, 3302 }; 3303 3304 /** 3305 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3306 */ 3307 struct dmub_cmd_psr_copy_settings_data { 3308 /** 3309 * Flags that can be set by driver to change some PSR behaviour. 3310 */ 3311 union dmub_psr_debug_flags debug; 3312 /** 3313 * 16-bit value dicated by driver that will enable/disable different functionality. 3314 */ 3315 uint16_t psr_level; 3316 /** 3317 * DPP HW instance. 3318 */ 3319 uint8_t dpp_inst; 3320 /** 3321 * MPCC HW instance. 3322 * Not used in dmub fw, 3323 * dmub fw will get active opp by reading odm registers. 3324 */ 3325 uint8_t mpcc_inst; 3326 /** 3327 * OPP HW instance. 3328 * Not used in dmub fw, 3329 * dmub fw will get active opp by reading odm registers. 3330 */ 3331 uint8_t opp_inst; 3332 /** 3333 * OTG HW instance. 3334 */ 3335 uint8_t otg_inst; 3336 /** 3337 * DIG FE HW instance. 3338 */ 3339 uint8_t digfe_inst; 3340 /** 3341 * DIG BE HW instance. 3342 */ 3343 uint8_t digbe_inst; 3344 /** 3345 * DP PHY HW instance. 3346 */ 3347 uint8_t dpphy_inst; 3348 /** 3349 * AUX HW instance. 3350 */ 3351 uint8_t aux_inst; 3352 /** 3353 * Determines if SMU optimzations are enabled/disabled. 3354 */ 3355 uint8_t smu_optimizations_en; 3356 /** 3357 * Unused. 3358 * TODO: Remove. 3359 */ 3360 uint8_t frame_delay; 3361 /** 3362 * If RFB setup time is greater than the total VBLANK time, 3363 * it is not possible for the sink to capture the video frame 3364 * in the same frame the SDP is sent. In this case, 3365 * the frame capture indication bit should be set and an extra 3366 * static frame should be transmitted to the sink. 3367 */ 3368 uint8_t frame_cap_ind; 3369 /** 3370 * Granularity of Y offset supported by sink. 3371 */ 3372 uint8_t su_y_granularity; 3373 /** 3374 * Indicates whether sink should start capturing 3375 * immediately following active scan line, 3376 * or starting with the 2nd active scan line. 3377 */ 3378 uint8_t line_capture_indication; 3379 /** 3380 * Multi-display optimizations are implemented on certain ASICs. 3381 */ 3382 uint8_t multi_disp_optimizations_en; 3383 /** 3384 * The last possible line SDP may be transmitted without violating 3385 * the RFB setup time or entering the active video frame. 3386 */ 3387 uint16_t init_sdp_deadline; 3388 /** 3389 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3390 */ 3391 uint8_t rate_control_caps ; 3392 /* 3393 * Force PSRSU always doing full frame update 3394 */ 3395 uint8_t force_ffu_mode; 3396 /** 3397 * Length of each horizontal line in us. 3398 */ 3399 uint32_t line_time_in_us; 3400 /** 3401 * FEC enable status in driver 3402 */ 3403 uint8_t fec_enable_status; 3404 /** 3405 * FEC re-enable delay when PSR exit. 3406 * unit is 100us, range form 0~255(0xFF). 3407 */ 3408 uint8_t fec_enable_delay_in100us; 3409 /** 3410 * PSR control version. 3411 */ 3412 uint8_t cmd_version; 3413 /** 3414 * Panel Instance. 3415 * Panel instance to identify which psr_state to use 3416 * Currently the support is only for 0 or 1 3417 */ 3418 uint8_t panel_inst; 3419 /* 3420 * DSC enable status in driver 3421 */ 3422 uint8_t dsc_enable_status; 3423 /* 3424 * Use FSM state for PSR power up/down 3425 */ 3426 uint8_t use_phy_fsm; 3427 /** 3428 * frame delay for frame re-lock 3429 */ 3430 uint8_t relock_delay_frame_cnt; 3431 /** 3432 * esd recovery indicate. 3433 */ 3434 uint8_t esd_recovery; 3435 /** 3436 * DSC Slice height. 3437 */ 3438 uint16_t dsc_slice_height; 3439 /** 3440 * Some panels request main link off before xth vertical line 3441 */ 3442 uint16_t poweroff_before_vertical_line; 3443 /** 3444 * Some panels cannot handle idle pattern during PSR entry. 3445 * To power down phy before disable stream to avoid sending 3446 * idle pattern. 3447 */ 3448 uint8_t power_down_phy_before_disable_stream; 3449 }; 3450 3451 /** 3452 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3453 */ 3454 struct dmub_rb_cmd_psr_copy_settings { 3455 /** 3456 * Command header. 3457 */ 3458 struct dmub_cmd_header header; 3459 /** 3460 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3461 */ 3462 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3463 }; 3464 3465 /** 3466 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3467 */ 3468 struct dmub_cmd_psr_set_level_data { 3469 /** 3470 * 16-bit value dicated by driver that will enable/disable different functionality. 3471 */ 3472 uint16_t psr_level; 3473 /** 3474 * PSR control version. 3475 */ 3476 uint8_t cmd_version; 3477 /** 3478 * Panel Instance. 3479 * Panel instance to identify which psr_state to use 3480 * Currently the support is only for 0 or 1 3481 */ 3482 uint8_t panel_inst; 3483 }; 3484 3485 /** 3486 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3487 */ 3488 struct dmub_rb_cmd_psr_set_level { 3489 /** 3490 * Command header. 3491 */ 3492 struct dmub_cmd_header header; 3493 /** 3494 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3495 */ 3496 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3497 }; 3498 3499 struct dmub_rb_cmd_psr_enable_data { 3500 /** 3501 * PSR control version. 3502 */ 3503 uint8_t cmd_version; 3504 /** 3505 * Panel Instance. 3506 * Panel instance to identify which psr_state to use 3507 * Currently the support is only for 0 or 1 3508 */ 3509 uint8_t panel_inst; 3510 /** 3511 * Phy state to enter. 3512 * Values to use are defined in dmub_phy_fsm_state 3513 */ 3514 uint8_t phy_fsm_state; 3515 /** 3516 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3517 * Set this using enum phy_link_rate. 3518 * This does not support HDMI/DP2 for now. 3519 */ 3520 uint8_t phy_rate; 3521 }; 3522 3523 /** 3524 * Definition of a DMUB_CMD__PSR_ENABLE command. 3525 * PSR enable/disable is controlled using the sub_type. 3526 */ 3527 struct dmub_rb_cmd_psr_enable { 3528 /** 3529 * Command header. 3530 */ 3531 struct dmub_cmd_header header; 3532 3533 struct dmub_rb_cmd_psr_enable_data data; 3534 }; 3535 3536 /** 3537 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3538 */ 3539 struct dmub_cmd_psr_set_version_data { 3540 /** 3541 * PSR version that FW should implement. 3542 */ 3543 enum psr_version version; 3544 /** 3545 * PSR control version. 3546 */ 3547 uint8_t cmd_version; 3548 /** 3549 * Panel Instance. 3550 * Panel instance to identify which psr_state to use 3551 * Currently the support is only for 0 or 1 3552 */ 3553 uint8_t panel_inst; 3554 /** 3555 * Explicit padding to 4 byte boundary. 3556 */ 3557 uint8_t pad[2]; 3558 }; 3559 3560 /** 3561 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3562 */ 3563 struct dmub_rb_cmd_psr_set_version { 3564 /** 3565 * Command header. 3566 */ 3567 struct dmub_cmd_header header; 3568 /** 3569 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3570 */ 3571 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3572 }; 3573 3574 struct dmub_cmd_psr_force_static_data { 3575 /** 3576 * PSR control version. 3577 */ 3578 uint8_t cmd_version; 3579 /** 3580 * Panel Instance. 3581 * Panel instance to identify which psr_state to use 3582 * Currently the support is only for 0 or 1 3583 */ 3584 uint8_t panel_inst; 3585 /** 3586 * Explicit padding to 4 byte boundary. 3587 */ 3588 uint8_t pad[2]; 3589 }; 3590 3591 /** 3592 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3593 */ 3594 struct dmub_rb_cmd_psr_force_static { 3595 /** 3596 * Command header. 3597 */ 3598 struct dmub_cmd_header header; 3599 /** 3600 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3601 */ 3602 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3603 }; 3604 3605 /** 3606 * PSR SU debug flags. 3607 */ 3608 union dmub_psr_su_debug_flags { 3609 /** 3610 * PSR SU debug flags. 3611 */ 3612 struct { 3613 /** 3614 * Update dirty rect in SW only. 3615 */ 3616 uint8_t update_dirty_rect_only : 1; 3617 /** 3618 * Reset the cursor/plane state before processing the call. 3619 */ 3620 uint8_t reset_state : 1; 3621 } bitfields; 3622 3623 /** 3624 * Union for debug flags. 3625 */ 3626 uint32_t u32All; 3627 }; 3628 3629 /** 3630 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3631 * This triggers a selective update for PSR SU. 3632 */ 3633 struct dmub_cmd_update_dirty_rect_data { 3634 /** 3635 * Dirty rects from OS. 3636 */ 3637 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3638 /** 3639 * PSR SU debug flags. 3640 */ 3641 union dmub_psr_su_debug_flags debug_flags; 3642 /** 3643 * OTG HW instance. 3644 */ 3645 uint8_t pipe_idx; 3646 /** 3647 * Number of dirty rects. 3648 */ 3649 uint8_t dirty_rect_count; 3650 /** 3651 * PSR control version. 3652 */ 3653 uint8_t cmd_version; 3654 /** 3655 * Panel Instance. 3656 * Panel instance to identify which psr_state to use 3657 * Currently the support is only for 0 or 1 3658 */ 3659 uint8_t panel_inst; 3660 }; 3661 3662 /** 3663 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3664 */ 3665 struct dmub_rb_cmd_update_dirty_rect { 3666 /** 3667 * Command header. 3668 */ 3669 struct dmub_cmd_header header; 3670 /** 3671 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3672 */ 3673 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3674 }; 3675 3676 /** 3677 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3678 */ 3679 union dmub_reg_cursor_control_cfg { 3680 struct { 3681 uint32_t cur_enable: 1; 3682 uint32_t reser0: 3; 3683 uint32_t cur_2x_magnify: 1; 3684 uint32_t reser1: 3; 3685 uint32_t mode: 3; 3686 uint32_t reser2: 5; 3687 uint32_t pitch: 2; 3688 uint32_t reser3: 6; 3689 uint32_t line_per_chunk: 5; 3690 uint32_t reser4: 3; 3691 } bits; 3692 uint32_t raw; 3693 }; 3694 struct dmub_cursor_position_cache_hubp { 3695 union dmub_reg_cursor_control_cfg cur_ctl; 3696 union dmub_reg_position_cfg { 3697 struct { 3698 uint32_t cur_x_pos: 16; 3699 uint32_t cur_y_pos: 16; 3700 } bits; 3701 uint32_t raw; 3702 } position; 3703 union dmub_reg_hot_spot_cfg { 3704 struct { 3705 uint32_t hot_x: 16; 3706 uint32_t hot_y: 16; 3707 } bits; 3708 uint32_t raw; 3709 } hot_spot; 3710 union dmub_reg_dst_offset_cfg { 3711 struct { 3712 uint32_t dst_x_offset: 13; 3713 uint32_t reserved: 19; 3714 } bits; 3715 uint32_t raw; 3716 } dst_offset; 3717 }; 3718 3719 union dmub_reg_cur0_control_cfg { 3720 struct { 3721 uint32_t cur0_enable: 1; 3722 uint32_t expansion_mode: 1; 3723 uint32_t reser0: 1; 3724 uint32_t cur0_rom_en: 1; 3725 uint32_t mode: 3; 3726 uint32_t reserved: 25; 3727 } bits; 3728 uint32_t raw; 3729 }; 3730 struct dmub_cursor_position_cache_dpp { 3731 union dmub_reg_cur0_control_cfg cur0_ctl; 3732 }; 3733 struct dmub_cursor_position_cfg { 3734 struct dmub_cursor_position_cache_hubp pHubp; 3735 struct dmub_cursor_position_cache_dpp pDpp; 3736 uint8_t pipe_idx; 3737 /* 3738 * Padding is required. To be 4 Bytes Aligned. 3739 */ 3740 uint8_t padding[3]; 3741 }; 3742 3743 struct dmub_cursor_attribute_cache_hubp { 3744 uint32_t SURFACE_ADDR_HIGH; 3745 uint32_t SURFACE_ADDR; 3746 union dmub_reg_cursor_control_cfg cur_ctl; 3747 union dmub_reg_cursor_size_cfg { 3748 struct { 3749 uint32_t width: 16; 3750 uint32_t height: 16; 3751 } bits; 3752 uint32_t raw; 3753 } size; 3754 union dmub_reg_cursor_settings_cfg { 3755 struct { 3756 uint32_t dst_y_offset: 8; 3757 uint32_t chunk_hdl_adjust: 2; 3758 uint32_t reserved: 22; 3759 } bits; 3760 uint32_t raw; 3761 } settings; 3762 }; 3763 struct dmub_cursor_attribute_cache_dpp { 3764 union dmub_reg_cur0_control_cfg cur0_ctl; 3765 }; 3766 struct dmub_cursor_attributes_cfg { 3767 struct dmub_cursor_attribute_cache_hubp aHubp; 3768 struct dmub_cursor_attribute_cache_dpp aDpp; 3769 }; 3770 3771 struct dmub_cmd_update_cursor_payload0 { 3772 /** 3773 * Cursor dirty rects. 3774 */ 3775 struct dmub_rect cursor_rect; 3776 /** 3777 * PSR SU debug flags. 3778 */ 3779 union dmub_psr_su_debug_flags debug_flags; 3780 /** 3781 * Cursor enable/disable. 3782 */ 3783 uint8_t enable; 3784 /** 3785 * OTG HW instance. 3786 */ 3787 uint8_t pipe_idx; 3788 /** 3789 * PSR control version. 3790 */ 3791 uint8_t cmd_version; 3792 /** 3793 * Panel Instance. 3794 * Panel instance to identify which psr_state to use 3795 * Currently the support is only for 0 or 1 3796 */ 3797 uint8_t panel_inst; 3798 /** 3799 * Cursor Position Register. 3800 * Registers contains Hubp & Dpp modules 3801 */ 3802 struct dmub_cursor_position_cfg position_cfg; 3803 }; 3804 3805 struct dmub_cmd_update_cursor_payload1 { 3806 struct dmub_cursor_attributes_cfg attribute_cfg; 3807 }; 3808 3809 union dmub_cmd_update_cursor_info_data { 3810 struct dmub_cmd_update_cursor_payload0 payload0; 3811 struct dmub_cmd_update_cursor_payload1 payload1; 3812 }; 3813 /** 3814 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3815 */ 3816 struct dmub_rb_cmd_update_cursor_info { 3817 /** 3818 * Command header. 3819 */ 3820 struct dmub_cmd_header header; 3821 /** 3822 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3823 */ 3824 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3825 }; 3826 3827 /** 3828 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3829 */ 3830 struct dmub_cmd_psr_set_vtotal_data { 3831 /** 3832 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3833 */ 3834 uint16_t psr_vtotal_idle; 3835 /** 3836 * PSR control version. 3837 */ 3838 uint8_t cmd_version; 3839 /** 3840 * Panel Instance. 3841 * Panel instance to identify which psr_state to use 3842 * Currently the support is only for 0 or 1 3843 */ 3844 uint8_t panel_inst; 3845 /* 3846 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3847 */ 3848 uint16_t psr_vtotal_su; 3849 /** 3850 * Explicit padding to 4 byte boundary. 3851 */ 3852 uint8_t pad2[2]; 3853 }; 3854 3855 /** 3856 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3857 */ 3858 struct dmub_rb_cmd_psr_set_vtotal { 3859 /** 3860 * Command header. 3861 */ 3862 struct dmub_cmd_header header; 3863 /** 3864 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3865 */ 3866 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3867 }; 3868 3869 /** 3870 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3871 */ 3872 struct dmub_cmd_psr_set_power_opt_data { 3873 /** 3874 * PSR control version. 3875 */ 3876 uint8_t cmd_version; 3877 /** 3878 * Panel Instance. 3879 * Panel instance to identify which psr_state to use 3880 * Currently the support is only for 0 or 1 3881 */ 3882 uint8_t panel_inst; 3883 /** 3884 * Explicit padding to 4 byte boundary. 3885 */ 3886 uint8_t pad[2]; 3887 /** 3888 * PSR power option 3889 */ 3890 uint32_t power_opt; 3891 }; 3892 3893 /** 3894 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3895 */ 3896 struct dmub_rb_cmd_psr_set_power_opt { 3897 /** 3898 * Command header. 3899 */ 3900 struct dmub_cmd_header header; 3901 /** 3902 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3903 */ 3904 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3905 }; 3906 3907 enum dmub_alpm_mode { 3908 ALPM_AUXWAKE = 0, 3909 ALPM_AUXLESS = 1, 3910 ALPM_UNSUPPORTED = 2, 3911 }; 3912 3913 /** 3914 * Definition of Replay Residency GPINT command. 3915 * Bit[0] - Residency mode for Revision 0 3916 * Bit[1] - Enable/Disable state 3917 * Bit[2-3] - Revision number 3918 * Bit[4-7] - Residency mode for Revision 1 3919 * Bit[8] - Panel instance 3920 * Bit[9-15] - Reserved 3921 */ 3922 3923 enum pr_residency_mode { 3924 PR_RESIDENCY_MODE_PHY = 0x0, 3925 PR_RESIDENCY_MODE_ALPM, 3926 PR_RESIDENCY_MODE_IPS2, 3927 PR_RESIDENCY_MODE_FRAME_CNT, 3928 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3929 }; 3930 3931 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3932 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3933 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3934 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3935 3936 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3937 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3938 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3939 3940 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3941 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3942 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3943 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3944 3945 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3946 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3947 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3948 3949 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3950 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3951 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3952 3953 /** 3954 * Definition of a replay_state. 3955 */ 3956 enum replay_state { 3957 REPLAY_STATE_0 = 0x0, 3958 REPLAY_STATE_1 = 0x10, 3959 REPLAY_STATE_1A = 0x11, 3960 REPLAY_STATE_2 = 0x20, 3961 REPLAY_STATE_2A = 0x21, 3962 REPLAY_STATE_3 = 0x30, 3963 REPLAY_STATE_3INIT = 0x31, 3964 REPLAY_STATE_4 = 0x40, 3965 REPLAY_STATE_4A = 0x41, 3966 REPLAY_STATE_4B = 0x42, 3967 REPLAY_STATE_4C = 0x43, 3968 REPLAY_STATE_4D = 0x44, 3969 REPLAY_STATE_4E = 0x45, 3970 REPLAY_STATE_4B_LOCKED = 0x4A, 3971 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3972 REPLAY_STATE_5 = 0x50, 3973 REPLAY_STATE_5A = 0x51, 3974 REPLAY_STATE_5B = 0x52, 3975 REPLAY_STATE_5A_LOCKED = 0x5A, 3976 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3977 REPLAY_STATE_6 = 0x60, 3978 REPLAY_STATE_6A = 0x61, 3979 REPLAY_STATE_6B = 0x62, 3980 REPLAY_STATE_INVALID = 0xFF, 3981 }; 3982 3983 /** 3984 * Replay command sub-types. 3985 */ 3986 enum dmub_cmd_replay_type { 3987 /** 3988 * Copy driver-calculated parameters to REPLAY state. 3989 */ 3990 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3991 /** 3992 * Enable REPLAY. 3993 */ 3994 DMUB_CMD__REPLAY_ENABLE = 1, 3995 /** 3996 * Set Replay power option. 3997 */ 3998 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3999 /** 4000 * Set coasting vtotal. 4001 */ 4002 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 4003 /** 4004 * Set power opt and coasting vtotal. 4005 */ 4006 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 4007 /** 4008 * Set disabled iiming sync. 4009 */ 4010 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 4011 /** 4012 * Set Residency Frameupdate Timer. 4013 */ 4014 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 4015 /** 4016 * Set pseudo vtotal 4017 */ 4018 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 4019 /** 4020 * Set adaptive sync sdp enabled 4021 */ 4022 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4023 /** 4024 * Set version 4025 */ 4026 DMUB_CMD__REPLAY_SET_VERSION = 9, 4027 /** 4028 * Set Replay General command. 4029 */ 4030 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4031 }; 4032 4033 /** 4034 * Replay general command sub-types. 4035 */ 4036 enum dmub_cmd_replay_general_subtype { 4037 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 4038 /** 4039 * TODO: For backward compatible, allow new command only. 4040 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4041 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4042 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4043 */ 4044 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4045 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4046 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4047 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4048 }; 4049 4050 struct dmub_alpm_auxless_data { 4051 uint16_t lfps_setup_ns; 4052 uint16_t lfps_period_ns; 4053 uint16_t lfps_silence_ns; 4054 uint16_t lfps_t1_t2_override_us; 4055 short lfps_t1_t2_offset_us; 4056 uint8_t lttpr_count; 4057 /* 4058 * Padding to align structure to 4 byte boundary. 4059 */ 4060 uint8_t pad[1]; 4061 }; 4062 4063 /** 4064 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4065 */ 4066 struct dmub_cmd_replay_copy_settings_data { 4067 /** 4068 * Flags that can be set by driver to change some replay behaviour. 4069 */ 4070 union replay_debug_flags debug; 4071 4072 /** 4073 * @flags: Flags used to determine feature functionality. 4074 */ 4075 union replay_hw_flags flags; 4076 4077 /** 4078 * DPP HW instance. 4079 */ 4080 uint8_t dpp_inst; 4081 /** 4082 * OTG HW instance. 4083 */ 4084 uint8_t otg_inst; 4085 /** 4086 * DIG FE HW instance. 4087 */ 4088 uint8_t digfe_inst; 4089 /** 4090 * DIG BE HW instance. 4091 */ 4092 uint8_t digbe_inst; 4093 /** 4094 * AUX HW instance. 4095 */ 4096 uint8_t aux_inst; 4097 /** 4098 * Panel Instance. 4099 * Panel isntance to identify which psr_state to use 4100 * Currently the support is only for 0 or 1 4101 */ 4102 uint8_t panel_inst; 4103 /** 4104 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4105 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4106 */ 4107 uint8_t pixel_deviation_per_line; 4108 /** 4109 * @max_deviation_line: The max number of deviation line that can keep the timing 4110 * synchronized between the Source and Sink during Replay normal sleep mode. 4111 */ 4112 uint8_t max_deviation_line; 4113 /** 4114 * Length of each horizontal line in ns. 4115 */ 4116 uint32_t line_time_in_ns; 4117 /** 4118 * PHY instance. 4119 */ 4120 uint8_t dpphy_inst; 4121 /** 4122 * Determines if SMU optimzations are enabled/disabled. 4123 */ 4124 uint8_t smu_optimizations_en; 4125 /** 4126 * Determines if timing sync are enabled/disabled. 4127 */ 4128 uint8_t replay_timing_sync_supported; 4129 /* 4130 * Use FSM state for Replay power up/down 4131 */ 4132 uint8_t use_phy_fsm; 4133 /** 4134 * Use for AUX-less ALPM LFPS wake operation 4135 */ 4136 struct dmub_alpm_auxless_data auxless_alpm_data; 4137 /** 4138 * @hpo_stream_enc_inst: HPO stream encoder instance 4139 */ 4140 uint8_t hpo_stream_enc_inst; 4141 /** 4142 * @hpo_link_enc_inst: HPO link encoder instance 4143 */ 4144 uint8_t hpo_link_enc_inst; 4145 /** 4146 * @pad: Align structure to 4 byte boundary. 4147 */ 4148 uint8_t pad[2]; 4149 }; 4150 4151 4152 /** 4153 * Replay versions. 4154 */ 4155 enum replay_version { 4156 /** 4157 * FreeSync Replay 4158 */ 4159 REPLAY_VERSION_FREESYNC_REPLAY = 0, 4160 /** 4161 * Panel Replay 4162 */ 4163 REPLAY_VERSION_PANEL_REPLAY = 1, 4164 /** 4165 * Replay not supported. 4166 */ 4167 REPLAY_VERSION_UNSUPPORTED = 0xFF, 4168 }; 4169 4170 /** 4171 * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command. 4172 */ 4173 struct dmub_cmd_replay_set_version_data { 4174 /** 4175 * Panel Instance. 4176 * Panel instance to identify which psr_state to use 4177 * Currently the support is only for 0 or 1 4178 */ 4179 uint8_t panel_inst; 4180 /** 4181 * PSR version that FW should implement. 4182 */ 4183 enum replay_version version; 4184 /** 4185 * PSR control version. 4186 */ 4187 uint8_t cmd_version; 4188 /** 4189 * Explicit padding to 4 byte boundary. 4190 */ 4191 uint8_t pad[2]; 4192 }; 4193 4194 /** 4195 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 4196 */ 4197 struct dmub_rb_cmd_replay_set_version { 4198 /** 4199 * Command header. 4200 */ 4201 struct dmub_cmd_header header; 4202 /** 4203 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_VERSION command. 4204 */ 4205 struct dmub_cmd_replay_set_version_data replay_set_version_data; 4206 }; 4207 4208 /** 4209 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4210 */ 4211 struct dmub_rb_cmd_replay_copy_settings { 4212 /** 4213 * Command header. 4214 */ 4215 struct dmub_cmd_header header; 4216 /** 4217 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4218 */ 4219 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4220 }; 4221 4222 /** 4223 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4224 */ 4225 enum replay_enable { 4226 /** 4227 * Disable REPLAY. 4228 */ 4229 REPLAY_DISABLE = 0, 4230 /** 4231 * Enable REPLAY. 4232 */ 4233 REPLAY_ENABLE = 1, 4234 }; 4235 4236 /** 4237 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4238 */ 4239 struct dmub_rb_cmd_replay_enable_data { 4240 /** 4241 * Replay enable or disable. 4242 */ 4243 uint8_t enable; 4244 /** 4245 * Panel Instance. 4246 * Panel isntance to identify which replay_state to use 4247 * Currently the support is only for 0 or 1 4248 */ 4249 uint8_t panel_inst; 4250 /** 4251 * Phy state to enter. 4252 * Values to use are defined in dmub_phy_fsm_state 4253 */ 4254 uint8_t phy_fsm_state; 4255 /** 4256 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4257 * Set this using enum phy_link_rate. 4258 * This does not support HDMI/DP2 for now. 4259 */ 4260 uint8_t phy_rate; 4261 /** 4262 * @hpo_stream_enc_inst: HPO stream encoder instance 4263 */ 4264 uint8_t hpo_stream_enc_inst; 4265 /** 4266 * @hpo_link_enc_inst: HPO link encoder instance 4267 */ 4268 uint8_t hpo_link_enc_inst; 4269 /** 4270 * @pad: Align structure to 4 byte boundary. 4271 */ 4272 uint8_t pad[2]; 4273 }; 4274 4275 /** 4276 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4277 * Replay enable/disable is controlled using action in data. 4278 */ 4279 struct dmub_rb_cmd_replay_enable { 4280 /** 4281 * Command header. 4282 */ 4283 struct dmub_cmd_header header; 4284 4285 struct dmub_rb_cmd_replay_enable_data data; 4286 }; 4287 4288 /** 4289 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4290 */ 4291 struct dmub_cmd_replay_set_power_opt_data { 4292 /** 4293 * Panel Instance. 4294 * Panel isntance to identify which replay_state to use 4295 * Currently the support is only for 0 or 1 4296 */ 4297 uint8_t panel_inst; 4298 /** 4299 * Explicit padding to 4 byte boundary. 4300 */ 4301 uint8_t pad[3]; 4302 /** 4303 * REPLAY power option 4304 */ 4305 uint32_t power_opt; 4306 }; 4307 4308 /** 4309 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4310 */ 4311 struct dmub_cmd_replay_set_timing_sync_data { 4312 /** 4313 * Panel Instance. 4314 * Panel isntance to identify which replay_state to use 4315 * Currently the support is only for 0 or 1 4316 */ 4317 uint8_t panel_inst; 4318 /** 4319 * REPLAY set_timing_sync 4320 */ 4321 uint8_t timing_sync_supported; 4322 /** 4323 * Explicit padding to 4 byte boundary. 4324 */ 4325 uint8_t pad[2]; 4326 }; 4327 4328 /** 4329 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4330 */ 4331 struct dmub_cmd_replay_set_pseudo_vtotal { 4332 /** 4333 * Panel Instance. 4334 * Panel isntance to identify which replay_state to use 4335 * Currently the support is only for 0 or 1 4336 */ 4337 uint8_t panel_inst; 4338 /** 4339 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4340 */ 4341 uint16_t vtotal; 4342 /** 4343 * Explicit padding to 4 byte boundary. 4344 */ 4345 uint8_t pad; 4346 }; 4347 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4348 /** 4349 * Panel Instance. 4350 * Panel isntance to identify which replay_state to use 4351 * Currently the support is only for 0 or 1 4352 */ 4353 uint8_t panel_inst; 4354 /** 4355 * enabled: set adaptive sync sdp enabled 4356 */ 4357 uint8_t force_disabled; 4358 4359 uint8_t pad[2]; 4360 }; 4361 struct dmub_cmd_replay_set_general_cmd_data { 4362 /** 4363 * Panel Instance. 4364 * Panel isntance to identify which replay_state to use 4365 * Currently the support is only for 0 or 1 4366 */ 4367 uint8_t panel_inst; 4368 /** 4369 * subtype: replay general cmd sub type 4370 */ 4371 uint8_t subtype; 4372 4373 uint8_t pad[2]; 4374 /** 4375 * config data with param1 and param2 4376 */ 4377 uint32_t param1; 4378 4379 uint32_t param2; 4380 }; 4381 4382 /** 4383 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4384 */ 4385 struct dmub_rb_cmd_replay_set_power_opt { 4386 /** 4387 * Command header. 4388 */ 4389 struct dmub_cmd_header header; 4390 /** 4391 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4392 */ 4393 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4394 }; 4395 4396 /** 4397 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4398 */ 4399 struct dmub_cmd_replay_set_coasting_vtotal_data { 4400 /** 4401 * 16-bit value dicated by driver that indicates the coasting vtotal. 4402 */ 4403 uint16_t coasting_vtotal; 4404 /** 4405 * REPLAY control version. 4406 */ 4407 uint8_t cmd_version; 4408 /** 4409 * Panel Instance. 4410 * Panel isntance to identify which replay_state to use 4411 * Currently the support is only for 0 or 1 4412 */ 4413 uint8_t panel_inst; 4414 /** 4415 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4416 */ 4417 uint16_t coasting_vtotal_high; 4418 /** 4419 * Explicit padding to 4 byte boundary. 4420 */ 4421 uint8_t pad[2]; 4422 }; 4423 4424 /** 4425 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4426 */ 4427 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4428 /** 4429 * Command header. 4430 */ 4431 struct dmub_cmd_header header; 4432 /** 4433 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4434 */ 4435 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4436 }; 4437 4438 /** 4439 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4440 */ 4441 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4442 /** 4443 * Command header. 4444 */ 4445 struct dmub_cmd_header header; 4446 /** 4447 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4448 */ 4449 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4450 /** 4451 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4452 */ 4453 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4454 }; 4455 4456 /** 4457 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4458 */ 4459 struct dmub_rb_cmd_replay_set_timing_sync { 4460 /** 4461 * Command header. 4462 */ 4463 struct dmub_cmd_header header; 4464 /** 4465 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4466 */ 4467 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4468 }; 4469 4470 /** 4471 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4472 */ 4473 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4474 /** 4475 * Command header. 4476 */ 4477 struct dmub_cmd_header header; 4478 /** 4479 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4480 */ 4481 struct dmub_cmd_replay_set_pseudo_vtotal data; 4482 }; 4483 4484 /** 4485 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4486 */ 4487 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4488 /** 4489 * Command header. 4490 */ 4491 struct dmub_cmd_header header; 4492 /** 4493 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4494 */ 4495 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4496 }; 4497 4498 /** 4499 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4500 */ 4501 struct dmub_rb_cmd_replay_set_general_cmd { 4502 /** 4503 * Command header. 4504 */ 4505 struct dmub_cmd_header header; 4506 /** 4507 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4508 */ 4509 struct dmub_cmd_replay_set_general_cmd_data data; 4510 }; 4511 4512 /** 4513 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4514 */ 4515 struct dmub_cmd_replay_frameupdate_timer_data { 4516 /** 4517 * Panel Instance. 4518 * Panel isntance to identify which replay_state to use 4519 * Currently the support is only for 0 or 1 4520 */ 4521 uint8_t panel_inst; 4522 /** 4523 * Replay Frameupdate Timer Enable or not 4524 */ 4525 uint8_t enable; 4526 /** 4527 * REPLAY force reflash frame update number 4528 */ 4529 uint16_t frameupdate_count; 4530 }; 4531 /** 4532 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4533 */ 4534 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4535 /** 4536 * Command header. 4537 */ 4538 struct dmub_cmd_header header; 4539 /** 4540 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4541 */ 4542 struct dmub_cmd_replay_frameupdate_timer_data data; 4543 }; 4544 4545 /** 4546 * Definition union of replay command set 4547 */ 4548 union dmub_replay_cmd_set { 4549 /** 4550 * Panel Instance. 4551 * Panel isntance to identify which replay_state to use 4552 * Currently the support is only for 0 or 1 4553 */ 4554 uint8_t panel_inst; 4555 /** 4556 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4557 */ 4558 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4559 /** 4560 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4561 */ 4562 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4563 /** 4564 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4565 */ 4566 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4567 /** 4568 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4569 */ 4570 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4571 /** 4572 * Definition of DMUB_CMD__REPLAY_SET_VERSION command data. 4573 */ 4574 struct dmub_cmd_replay_set_version_data version_data; 4575 /** 4576 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4577 */ 4578 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4579 }; 4580 4581 /** 4582 * Set of HW components that can be locked. 4583 * 4584 * Note: If updating with more HW components, fields 4585 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4586 */ 4587 union dmub_hw_lock_flags { 4588 /** 4589 * Set of HW components that can be locked. 4590 */ 4591 struct { 4592 /** 4593 * Lock/unlock OTG master update lock. 4594 */ 4595 uint8_t lock_pipe : 1; 4596 /** 4597 * Lock/unlock cursor. 4598 */ 4599 uint8_t lock_cursor : 1; 4600 /** 4601 * Lock/unlock global update lock. 4602 */ 4603 uint8_t lock_dig : 1; 4604 /** 4605 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4606 */ 4607 uint8_t triple_buffer_lock : 1; 4608 } bits; 4609 4610 /** 4611 * Union for HW Lock flags. 4612 */ 4613 uint8_t u8All; 4614 }; 4615 4616 /** 4617 * Instances of HW to be locked. 4618 * 4619 * Note: If updating with more HW components, fields 4620 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4621 */ 4622 struct dmub_hw_lock_inst_flags { 4623 /** 4624 * OTG HW instance for OTG master update lock. 4625 */ 4626 uint8_t otg_inst; 4627 /** 4628 * OPP instance for cursor lock. 4629 */ 4630 uint8_t opp_inst; 4631 /** 4632 * OTG HW instance for global update lock. 4633 * TODO: Remove, and re-use otg_inst. 4634 */ 4635 uint8_t dig_inst; 4636 /** 4637 * Explicit pad to 4 byte boundary. 4638 */ 4639 uint8_t pad; 4640 }; 4641 4642 /** 4643 * Clients that can acquire the HW Lock Manager. 4644 * 4645 * Note: If updating with more clients, fields in 4646 * dmub_inbox0_cmd_lock_hw must be updated to match. 4647 */ 4648 enum hw_lock_client { 4649 /** 4650 * Driver is the client of HW Lock Manager. 4651 */ 4652 HW_LOCK_CLIENT_DRIVER = 0, 4653 /** 4654 * PSR SU is the client of HW Lock Manager. 4655 */ 4656 HW_LOCK_CLIENT_PSR_SU = 1, 4657 HW_LOCK_CLIENT_SUBVP = 3, 4658 /** 4659 * Replay is the client of HW Lock Manager. 4660 */ 4661 HW_LOCK_CLIENT_REPLAY = 4, 4662 HW_LOCK_CLIENT_FAMS2 = 5, 4663 /** 4664 * Invalid client. 4665 */ 4666 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4667 }; 4668 4669 /** 4670 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4671 */ 4672 struct dmub_cmd_lock_hw_data { 4673 /** 4674 * Specifies the client accessing HW Lock Manager. 4675 */ 4676 enum hw_lock_client client; 4677 /** 4678 * HW instances to be locked. 4679 */ 4680 struct dmub_hw_lock_inst_flags inst_flags; 4681 /** 4682 * Which components to be locked. 4683 */ 4684 union dmub_hw_lock_flags hw_locks; 4685 /** 4686 * Specifies lock/unlock. 4687 */ 4688 uint8_t lock; 4689 /** 4690 * HW can be unlocked separately from releasing the HW Lock Mgr. 4691 * This flag is set if the client wishes to release the object. 4692 */ 4693 uint8_t should_release; 4694 /** 4695 * Explicit padding to 4 byte boundary. 4696 */ 4697 uint8_t pad; 4698 }; 4699 4700 /** 4701 * Definition of a DMUB_CMD__HW_LOCK command. 4702 * Command is used by driver and FW. 4703 */ 4704 struct dmub_rb_cmd_lock_hw { 4705 /** 4706 * Command header. 4707 */ 4708 struct dmub_cmd_header header; 4709 /** 4710 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4711 */ 4712 struct dmub_cmd_lock_hw_data lock_hw_data; 4713 }; 4714 4715 /** 4716 * ABM command sub-types. 4717 */ 4718 enum dmub_cmd_abm_type { 4719 /** 4720 * Initialize parameters for ABM algorithm. 4721 * Data is passed through an indirect buffer. 4722 */ 4723 DMUB_CMD__ABM_INIT_CONFIG = 0, 4724 /** 4725 * Set OTG and panel HW instance. 4726 */ 4727 DMUB_CMD__ABM_SET_PIPE = 1, 4728 /** 4729 * Set user requested backklight level. 4730 */ 4731 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4732 /** 4733 * Set ABM operating/aggression level. 4734 */ 4735 DMUB_CMD__ABM_SET_LEVEL = 3, 4736 /** 4737 * Set ambient light level. 4738 */ 4739 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4740 /** 4741 * Enable/disable fractional duty cycle for backlight PWM. 4742 */ 4743 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4744 4745 /** 4746 * unregister vertical interrupt after steady state is reached 4747 */ 4748 DMUB_CMD__ABM_PAUSE = 6, 4749 4750 /** 4751 * Save and Restore ABM state. On save we save parameters, and 4752 * on restore we update state with passed in data. 4753 */ 4754 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4755 4756 /** 4757 * Query ABM caps. 4758 */ 4759 DMUB_CMD__ABM_QUERY_CAPS = 8, 4760 4761 /** 4762 * Set ABM Events 4763 */ 4764 DMUB_CMD__ABM_SET_EVENT = 9, 4765 4766 /** 4767 * Get the current ACE curve. 4768 */ 4769 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4770 4771 /** 4772 * Get current histogram data 4773 */ 4774 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4775 }; 4776 4777 /** 4778 * LSDMA command sub-types. 4779 */ 4780 enum dmub_cmd_lsdma_type { 4781 /** 4782 * Initialize parameters for LSDMA. 4783 * Ring buffer is mapped to the ring buffer 4784 */ 4785 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 4786 /** 4787 * LSDMA copies data from source to destination linearly 4788 */ 4789 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 4790 /** 4791 * LSDMA copies data from source to destination linearly in sub window 4792 */ 4793 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, 4794 /** 4795 * Send the tiled-to-tiled copy command 4796 */ 4797 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, 4798 /** 4799 * Send the poll reg write command 4800 */ 4801 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, 4802 /** 4803 * Send the pio copy command 4804 */ 4805 DMUB_CMD__LSDMA_PIO_COPY = 5, 4806 /** 4807 * Send the pio constfill command 4808 */ 4809 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, 4810 }; 4811 4812 struct abm_ace_curve { 4813 /** 4814 * @offsets: ACE curve offsets. 4815 */ 4816 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4817 4818 /** 4819 * @thresholds: ACE curve thresholds. 4820 */ 4821 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4822 4823 /** 4824 * @slopes: ACE curve slopes. 4825 */ 4826 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4827 }; 4828 4829 struct fixed_pt_format { 4830 /** 4831 * @sign_bit: Indicates whether one bit is reserved for the sign. 4832 */ 4833 bool sign_bit; 4834 4835 /** 4836 * @num_int_bits: Number of bits used for integer part. 4837 */ 4838 uint8_t num_int_bits; 4839 4840 /** 4841 * @num_frac_bits: Number of bits used for fractional part. 4842 */ 4843 uint8_t num_frac_bits; 4844 4845 /** 4846 * @pad: Explicit padding to 4 byte boundary. 4847 */ 4848 uint8_t pad; 4849 }; 4850 4851 struct abm_caps { 4852 /** 4853 * @num_hg_bins: Number of histogram bins. 4854 */ 4855 uint8_t num_hg_bins; 4856 4857 /** 4858 * @num_ace_segments: Number of ACE curve segments. 4859 */ 4860 uint8_t num_ace_segments; 4861 4862 /** 4863 * @pad: Explicit padding to 4 byte boundary. 4864 */ 4865 uint8_t pad[2]; 4866 4867 /** 4868 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4869 */ 4870 struct fixed_pt_format ace_thresholds_format; 4871 4872 /** 4873 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4874 */ 4875 struct fixed_pt_format ace_offsets_format; 4876 4877 /** 4878 * @ace_slopes_format: Format of the ACE slopes. 4879 */ 4880 struct fixed_pt_format ace_slopes_format; 4881 }; 4882 4883 /** 4884 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4885 * Requirements: 4886 * - Padded explicitly to 32-bit boundary. 4887 * - Must ensure this structure matches the one on driver-side, 4888 * otherwise it won't be aligned. 4889 */ 4890 struct abm_config_table { 4891 /** 4892 * Gamma curve thresholds, used for crgb conversion. 4893 */ 4894 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4895 /** 4896 * Gamma curve offsets, used for crgb conversion. 4897 */ 4898 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4899 /** 4900 * Gamma curve slopes, used for crgb conversion. 4901 */ 4902 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4903 /** 4904 * Custom backlight curve thresholds. 4905 */ 4906 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4907 /** 4908 * Custom backlight curve offsets. 4909 */ 4910 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4911 /** 4912 * Ambient light thresholds. 4913 */ 4914 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4915 /** 4916 * Minimum programmable backlight. 4917 */ 4918 uint16_t min_abm_backlight; // 122B 4919 /** 4920 * Minimum reduction values. 4921 */ 4922 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4923 /** 4924 * Maximum reduction values. 4925 */ 4926 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4927 /** 4928 * Bright positive gain. 4929 */ 4930 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4931 /** 4932 * Dark negative gain. 4933 */ 4934 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4935 /** 4936 * Hybrid factor. 4937 */ 4938 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4939 /** 4940 * Contrast factor. 4941 */ 4942 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4943 /** 4944 * Deviation gain. 4945 */ 4946 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4947 /** 4948 * Minimum knee. 4949 */ 4950 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4951 /** 4952 * Maximum knee. 4953 */ 4954 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4955 /** 4956 * Unused. 4957 */ 4958 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4959 /** 4960 * Explicit padding to 4 byte boundary. 4961 */ 4962 uint8_t pad3[3]; // 229B 4963 /** 4964 * Backlight ramp reduction. 4965 */ 4966 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4967 /** 4968 * Backlight ramp start. 4969 */ 4970 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4971 }; 4972 4973 /** 4974 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4975 */ 4976 struct dmub_cmd_abm_set_pipe_data { 4977 /** 4978 * OTG HW instance. 4979 */ 4980 uint8_t otg_inst; 4981 4982 /** 4983 * Panel Control HW instance. 4984 */ 4985 uint8_t panel_inst; 4986 4987 /** 4988 * Controls how ABM will interpret a set pipe or set level command. 4989 */ 4990 uint8_t set_pipe_option; 4991 4992 /** 4993 * Unused. 4994 * TODO: Remove. 4995 */ 4996 uint8_t ramping_boundary; 4997 4998 /** 4999 * PwrSeq HW Instance. 5000 */ 5001 uint8_t pwrseq_inst; 5002 5003 /** 5004 * Explicit padding to 4 byte boundary. 5005 */ 5006 uint8_t pad[3]; 5007 }; 5008 5009 /** 5010 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5011 */ 5012 struct dmub_rb_cmd_abm_set_pipe { 5013 /** 5014 * Command header. 5015 */ 5016 struct dmub_cmd_header header; 5017 5018 /** 5019 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5020 */ 5021 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 5022 }; 5023 5024 /** 5025 * Type of backlight control method to be used by ABM module 5026 */ 5027 enum dmub_backlight_control_type { 5028 /** 5029 * PWM Backlight control 5030 */ 5031 DMU_BACKLIGHT_CONTROL_PWM = 0, 5032 /** 5033 * VESA Aux-based backlight control 5034 */ 5035 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 5036 /** 5037 * AMD DPCD Aux-based backlight control 5038 */ 5039 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 5040 }; 5041 5042 /** 5043 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5044 */ 5045 struct dmub_cmd_abm_set_backlight_data { 5046 /** 5047 * Number of frames to ramp to backlight user level. 5048 */ 5049 uint32_t frame_ramp; 5050 5051 /** 5052 * Requested backlight level from user. 5053 */ 5054 uint32_t backlight_user_level; 5055 5056 /** 5057 * ABM control version. 5058 */ 5059 uint8_t version; 5060 5061 /** 5062 * Panel Control HW instance mask. 5063 * Bit 0 is Panel Control HW instance 0. 5064 * Bit 1 is Panel Control HW instance 1. 5065 */ 5066 uint8_t panel_mask; 5067 5068 /** 5069 * AUX HW Instance. 5070 */ 5071 uint8_t aux_inst; 5072 5073 /** 5074 * Explicit padding to 4 byte boundary. 5075 */ 5076 uint8_t pad[1]; 5077 5078 /** 5079 * Backlight control type. 5080 * Value 0 is PWM backlight control. 5081 * Value 1 is VAUX backlight control. 5082 * Value 2 is AMD DPCD AUX backlight control. 5083 */ 5084 enum dmub_backlight_control_type backlight_control_type; 5085 5086 /** 5087 * Minimum luminance in nits. 5088 */ 5089 uint32_t min_luminance; 5090 5091 /** 5092 * Maximum luminance in nits. 5093 */ 5094 uint32_t max_luminance; 5095 5096 /** 5097 * Minimum backlight in pwm. 5098 */ 5099 uint32_t min_backlight_pwm; 5100 5101 /** 5102 * Maximum backlight in pwm. 5103 */ 5104 uint32_t max_backlight_pwm; 5105 }; 5106 5107 /** 5108 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5109 */ 5110 struct dmub_rb_cmd_abm_set_backlight { 5111 /** 5112 * Command header. 5113 */ 5114 struct dmub_cmd_header header; 5115 5116 /** 5117 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5118 */ 5119 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 5120 }; 5121 5122 /** 5123 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5124 */ 5125 struct dmub_cmd_abm_set_level_data { 5126 /** 5127 * Set current ABM operating/aggression level. 5128 */ 5129 uint32_t level; 5130 5131 /** 5132 * ABM control version. 5133 */ 5134 uint8_t version; 5135 5136 /** 5137 * Panel Control HW instance mask. 5138 * Bit 0 is Panel Control HW instance 0. 5139 * Bit 1 is Panel Control HW instance 1. 5140 */ 5141 uint8_t panel_mask; 5142 5143 /** 5144 * Explicit padding to 4 byte boundary. 5145 */ 5146 uint8_t pad[2]; 5147 }; 5148 5149 /** 5150 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5151 */ 5152 struct dmub_rb_cmd_abm_set_level { 5153 /** 5154 * Command header. 5155 */ 5156 struct dmub_cmd_header header; 5157 5158 /** 5159 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5160 */ 5161 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5162 }; 5163 5164 /** 5165 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5166 */ 5167 struct dmub_cmd_abm_set_ambient_level_data { 5168 /** 5169 * Ambient light sensor reading from OS. 5170 */ 5171 uint32_t ambient_lux; 5172 5173 /** 5174 * ABM control version. 5175 */ 5176 uint8_t version; 5177 5178 /** 5179 * Panel Control HW instance mask. 5180 * Bit 0 is Panel Control HW instance 0. 5181 * Bit 1 is Panel Control HW instance 1. 5182 */ 5183 uint8_t panel_mask; 5184 5185 /** 5186 * Explicit padding to 4 byte boundary. 5187 */ 5188 uint8_t pad[2]; 5189 }; 5190 5191 /** 5192 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5193 */ 5194 struct dmub_rb_cmd_abm_set_ambient_level { 5195 /** 5196 * Command header. 5197 */ 5198 struct dmub_cmd_header header; 5199 5200 /** 5201 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5202 */ 5203 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5204 }; 5205 5206 /** 5207 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5208 */ 5209 struct dmub_cmd_abm_set_pwm_frac_data { 5210 /** 5211 * Enable/disable fractional duty cycle for backlight PWM. 5212 * TODO: Convert to uint8_t. 5213 */ 5214 uint32_t fractional_pwm; 5215 5216 /** 5217 * ABM control version. 5218 */ 5219 uint8_t version; 5220 5221 /** 5222 * Panel Control HW instance mask. 5223 * Bit 0 is Panel Control HW instance 0. 5224 * Bit 1 is Panel Control HW instance 1. 5225 */ 5226 uint8_t panel_mask; 5227 5228 /** 5229 * Explicit padding to 4 byte boundary. 5230 */ 5231 uint8_t pad[2]; 5232 }; 5233 5234 /** 5235 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5236 */ 5237 struct dmub_rb_cmd_abm_set_pwm_frac { 5238 /** 5239 * Command header. 5240 */ 5241 struct dmub_cmd_header header; 5242 5243 /** 5244 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5245 */ 5246 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5247 }; 5248 5249 /** 5250 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5251 */ 5252 struct dmub_cmd_abm_init_config_data { 5253 /** 5254 * Location of indirect buffer used to pass init data to ABM. 5255 */ 5256 union dmub_addr src; 5257 5258 /** 5259 * Indirect buffer length. 5260 */ 5261 uint16_t bytes; 5262 5263 5264 /** 5265 * ABM control version. 5266 */ 5267 uint8_t version; 5268 5269 /** 5270 * Panel Control HW instance mask. 5271 * Bit 0 is Panel Control HW instance 0. 5272 * Bit 1 is Panel Control HW instance 1. 5273 */ 5274 uint8_t panel_mask; 5275 5276 /** 5277 * Explicit padding to 4 byte boundary. 5278 */ 5279 uint8_t pad[2]; 5280 }; 5281 5282 /** 5283 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5284 */ 5285 struct dmub_rb_cmd_abm_init_config { 5286 /** 5287 * Command header. 5288 */ 5289 struct dmub_cmd_header header; 5290 5291 /** 5292 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5293 */ 5294 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5295 }; 5296 5297 /** 5298 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5299 */ 5300 5301 struct dmub_cmd_abm_pause_data { 5302 5303 /** 5304 * Panel Control HW instance mask. 5305 * Bit 0 is Panel Control HW instance 0. 5306 * Bit 1 is Panel Control HW instance 1. 5307 */ 5308 uint8_t panel_mask; 5309 5310 /** 5311 * OTG hw instance 5312 */ 5313 uint8_t otg_inst; 5314 5315 /** 5316 * Enable or disable ABM pause 5317 */ 5318 uint8_t enable; 5319 5320 /** 5321 * Explicit padding to 4 byte boundary. 5322 */ 5323 uint8_t pad[1]; 5324 }; 5325 5326 /** 5327 * Definition of a DMUB_CMD__ABM_PAUSE command. 5328 */ 5329 struct dmub_rb_cmd_abm_pause { 5330 /** 5331 * Command header. 5332 */ 5333 struct dmub_cmd_header header; 5334 5335 /** 5336 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5337 */ 5338 struct dmub_cmd_abm_pause_data abm_pause_data; 5339 }; 5340 5341 /** 5342 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5343 */ 5344 struct dmub_cmd_abm_query_caps_in { 5345 /** 5346 * Panel instance. 5347 */ 5348 uint8_t panel_inst; 5349 5350 /** 5351 * Explicit padding to 4 byte boundary. 5352 */ 5353 uint8_t pad[3]; 5354 }; 5355 5356 /** 5357 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5358 */ 5359 struct dmub_cmd_abm_query_caps_out { 5360 /** 5361 * SW Algorithm caps. 5362 */ 5363 struct abm_caps sw_caps; 5364 5365 /** 5366 * ABM HW caps. 5367 */ 5368 struct abm_caps hw_caps; 5369 }; 5370 5371 /** 5372 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5373 */ 5374 struct dmub_rb_cmd_abm_query_caps { 5375 /** 5376 * Command header. 5377 */ 5378 struct dmub_cmd_header header; 5379 5380 /** 5381 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5382 */ 5383 union { 5384 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5385 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5386 } data; 5387 }; 5388 5389 /** 5390 * enum dmub_abm_ace_curve_type - ACE curve type. 5391 */ 5392 enum dmub_abm_ace_curve_type { 5393 /** 5394 * ACE curve as defined by the SW layer. 5395 */ 5396 ABM_ACE_CURVE_TYPE__SW = 0, 5397 /** 5398 * ACE curve as defined by the SW to HW translation interface layer. 5399 */ 5400 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5401 }; 5402 5403 /** 5404 * enum dmub_abm_histogram_type - Histogram type. 5405 */ 5406 enum dmub_abm_histogram_type { 5407 /** 5408 * ACE curve as defined by the SW layer. 5409 */ 5410 ABM_HISTOGRAM_TYPE__SW = 0, 5411 /** 5412 * ACE curve as defined by the SW to HW translation interface layer. 5413 */ 5414 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5415 }; 5416 5417 /** 5418 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5419 */ 5420 struct dmub_rb_cmd_abm_get_ace_curve { 5421 /** 5422 * Command header. 5423 */ 5424 struct dmub_cmd_header header; 5425 5426 /** 5427 * Address where ACE curve should be copied. 5428 */ 5429 union dmub_addr dest; 5430 5431 /** 5432 * Type of ACE curve being queried. 5433 */ 5434 enum dmub_abm_ace_curve_type ace_type; 5435 5436 /** 5437 * Indirect buffer length. 5438 */ 5439 uint16_t bytes; 5440 5441 /** 5442 * eDP panel instance. 5443 */ 5444 uint8_t panel_inst; 5445 5446 /** 5447 * Explicit padding to 4 byte boundary. 5448 */ 5449 uint8_t pad; 5450 }; 5451 5452 /** 5453 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5454 */ 5455 struct dmub_rb_cmd_abm_get_histogram { 5456 /** 5457 * Command header. 5458 */ 5459 struct dmub_cmd_header header; 5460 5461 /** 5462 * Address where Histogram should be copied. 5463 */ 5464 union dmub_addr dest; 5465 5466 /** 5467 * Type of Histogram being queried. 5468 */ 5469 enum dmub_abm_histogram_type histogram_type; 5470 5471 /** 5472 * Indirect buffer length. 5473 */ 5474 uint16_t bytes; 5475 5476 /** 5477 * eDP panel instance. 5478 */ 5479 uint8_t panel_inst; 5480 5481 /** 5482 * Explicit padding to 4 byte boundary. 5483 */ 5484 uint8_t pad; 5485 }; 5486 5487 /** 5488 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5489 */ 5490 struct dmub_rb_cmd_abm_save_restore { 5491 /** 5492 * Command header. 5493 */ 5494 struct dmub_cmd_header header; 5495 5496 /** 5497 * OTG hw instance 5498 */ 5499 uint8_t otg_inst; 5500 5501 /** 5502 * Enable or disable ABM pause 5503 */ 5504 uint8_t freeze; 5505 5506 /** 5507 * Explicit padding to 4 byte boundary. 5508 */ 5509 uint8_t debug; 5510 5511 /** 5512 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5513 */ 5514 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5515 }; 5516 5517 /** 5518 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5519 */ 5520 5521 struct dmub_cmd_abm_set_event_data { 5522 5523 /** 5524 * VB Scaling Init. Strength Mapping 5525 * Byte 0: 0~255 for VB level 0 5526 * Byte 1: 0~255 for VB level 1 5527 * Byte 2: 0~255 for VB level 2 5528 * Byte 3: 0~255 for VB level 3 5529 */ 5530 uint32_t vb_scaling_strength_mapping; 5531 /** 5532 * VariBright Scaling Enable 5533 */ 5534 uint8_t vb_scaling_enable; 5535 /** 5536 * Panel Control HW instance mask. 5537 * Bit 0 is Panel Control HW instance 0. 5538 * Bit 1 is Panel Control HW instance 1. 5539 */ 5540 uint8_t panel_mask; 5541 5542 /** 5543 * Explicit padding to 4 byte boundary. 5544 */ 5545 uint8_t pad[2]; 5546 }; 5547 5548 /** 5549 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5550 */ 5551 struct dmub_rb_cmd_abm_set_event { 5552 /** 5553 * Command header. 5554 */ 5555 struct dmub_cmd_header header; 5556 5557 /** 5558 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5559 */ 5560 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5561 }; 5562 5563 /** 5564 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5565 */ 5566 struct dmub_cmd_query_feature_caps_data { 5567 /** 5568 * DMUB feature capabilities. 5569 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5570 */ 5571 struct dmub_feature_caps feature_caps; 5572 }; 5573 5574 /** 5575 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5576 */ 5577 struct dmub_rb_cmd_query_feature_caps { 5578 /** 5579 * Command header. 5580 */ 5581 struct dmub_cmd_header header; 5582 /** 5583 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5584 */ 5585 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5586 }; 5587 5588 /** 5589 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5590 */ 5591 struct dmub_cmd_visual_confirm_color_data { 5592 /** 5593 * DMUB visual confirm color 5594 */ 5595 struct dmub_visual_confirm_color visual_confirm_color; 5596 }; 5597 5598 /** 5599 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5600 */ 5601 struct dmub_rb_cmd_get_visual_confirm_color { 5602 /** 5603 * Command header. 5604 */ 5605 struct dmub_cmd_header header; 5606 /** 5607 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5608 */ 5609 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5610 }; 5611 5612 /** 5613 * enum dmub_cmd_panel_cntl_type - Panel control command. 5614 */ 5615 enum dmub_cmd_panel_cntl_type { 5616 /** 5617 * Initializes embedded panel hardware blocks. 5618 */ 5619 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5620 /** 5621 * Queries backlight info for the embedded panel. 5622 */ 5623 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5624 /** 5625 * Sets the PWM Freq as per user's requirement. 5626 */ 5627 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5628 }; 5629 5630 /** 5631 * struct dmub_cmd_panel_cntl_data - Panel control data. 5632 */ 5633 struct dmub_cmd_panel_cntl_data { 5634 uint32_t pwrseq_inst; /**< pwrseq instance */ 5635 uint32_t current_backlight; /* in/out */ 5636 uint32_t bl_pwm_cntl; /* in/out */ 5637 uint32_t bl_pwm_period_cntl; /* in/out */ 5638 uint32_t bl_pwm_ref_div1; /* in/out */ 5639 uint8_t is_backlight_on : 1; /* in/out */ 5640 uint8_t is_powered_on : 1; /* in/out */ 5641 uint8_t padding[3]; 5642 uint32_t bl_pwm_ref_div2; /* in/out */ 5643 uint8_t reserved[4]; 5644 }; 5645 5646 /** 5647 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5648 */ 5649 struct dmub_rb_cmd_panel_cntl { 5650 struct dmub_cmd_header header; /**< header */ 5651 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5652 }; 5653 5654 struct dmub_optc_state { 5655 uint32_t v_total_max; 5656 uint32_t v_total_min; 5657 uint32_t tg_inst; 5658 }; 5659 5660 struct dmub_rb_cmd_drr_update { 5661 struct dmub_cmd_header header; 5662 struct dmub_optc_state dmub_optc_state_req; 5663 }; 5664 5665 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5666 uint32_t pix_clk_100hz; 5667 uint8_t max_ramp_step; 5668 uint8_t pipes; 5669 uint8_t min_refresh_in_hz; 5670 uint8_t pipe_count; 5671 uint8_t pipe_index[4]; 5672 }; 5673 5674 struct dmub_cmd_fw_assisted_mclk_switch_config { 5675 uint8_t fams_enabled; 5676 uint8_t visual_confirm_enabled; 5677 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5678 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5679 }; 5680 5681 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5682 struct dmub_cmd_header header; 5683 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5684 }; 5685 5686 /** 5687 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5688 */ 5689 struct dmub_cmd_lvtma_control_data { 5690 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5691 uint8_t bypass_panel_control_wait; 5692 uint8_t reserved_0[2]; /**< For future use */ 5693 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5694 uint8_t reserved_1[3]; /**< For future use */ 5695 }; 5696 5697 /** 5698 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5699 */ 5700 struct dmub_rb_cmd_lvtma_control { 5701 /** 5702 * Command header. 5703 */ 5704 struct dmub_cmd_header header; 5705 /** 5706 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5707 */ 5708 struct dmub_cmd_lvtma_control_data data; 5709 }; 5710 5711 /** 5712 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5713 */ 5714 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5715 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5716 uint8_t is_usb; /**< is phy is usb */ 5717 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5718 uint8_t is_dp4; /**< is dp in 4 lane */ 5719 }; 5720 5721 /** 5722 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5723 */ 5724 struct dmub_rb_cmd_transmitter_query_dp_alt { 5725 struct dmub_cmd_header header; /**< header */ 5726 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5727 }; 5728 5729 struct phy_test_mode { 5730 uint8_t mode; 5731 uint8_t pat0; 5732 uint8_t pad[2]; 5733 }; 5734 5735 /** 5736 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5737 */ 5738 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5739 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5740 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5741 uint8_t lane_num; /**< Number of lanes */ 5742 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5743 struct phy_test_mode test_mode; 5744 enum dmub_phy_fsm_state state; 5745 uint32_t status; 5746 uint8_t pad; 5747 }; 5748 5749 /** 5750 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5751 */ 5752 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5753 struct dmub_cmd_header header; /**< header */ 5754 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5755 }; 5756 5757 /** 5758 * Maximum number of bytes a chunk sent to DMUB for parsing 5759 */ 5760 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5761 5762 /** 5763 * Represent a chunk of CEA blocks sent to DMUB for parsing 5764 */ 5765 struct dmub_cmd_send_edid_cea { 5766 uint16_t offset; /**< offset into the CEA block */ 5767 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5768 uint16_t cea_total_length; /**< total length of the CEA block */ 5769 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5770 uint8_t pad[3]; /**< padding and for future expansion */ 5771 }; 5772 5773 /** 5774 * Result of VSDB parsing from CEA block 5775 */ 5776 struct dmub_cmd_edid_cea_amd_vsdb { 5777 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5778 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5779 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5780 uint16_t min_frame_rate; /**< Maximum frame rate */ 5781 uint16_t max_frame_rate; /**< Minimum frame rate */ 5782 }; 5783 5784 /** 5785 * Result of sending a CEA chunk 5786 */ 5787 struct dmub_cmd_edid_cea_ack { 5788 uint16_t offset; /**< offset of the chunk into the CEA block */ 5789 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5790 uint8_t pad; /**< padding and for future expansion */ 5791 }; 5792 5793 /** 5794 * Specify whether the result is an ACK/NACK or the parsing has finished 5795 */ 5796 enum dmub_cmd_edid_cea_reply_type { 5797 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5798 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5799 }; 5800 5801 /** 5802 * Definition of a DMUB_CMD__EDID_CEA command. 5803 */ 5804 struct dmub_rb_cmd_edid_cea { 5805 struct dmub_cmd_header header; /**< Command header */ 5806 union dmub_cmd_edid_cea_data { 5807 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5808 struct dmub_cmd_edid_cea_output { /**< output with results */ 5809 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5810 union { 5811 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5812 struct dmub_cmd_edid_cea_ack ack; 5813 }; 5814 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5815 } data; /**< Command data */ 5816 5817 }; 5818 5819 /** 5820 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5821 */ 5822 struct dmub_cmd_cable_id_input { 5823 uint8_t phy_inst; /**< phy inst for cable id data */ 5824 }; 5825 5826 /** 5827 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5828 */ 5829 struct dmub_cmd_cable_id_output { 5830 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5831 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5832 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5833 uint8_t RESERVED :2; /**< reserved means not defined */ 5834 }; 5835 5836 /** 5837 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5838 */ 5839 struct dmub_rb_cmd_get_usbc_cable_id { 5840 struct dmub_cmd_header header; /**< Command header */ 5841 /** 5842 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5843 */ 5844 union dmub_cmd_cable_id_data { 5845 struct dmub_cmd_cable_id_input input; /**< Input */ 5846 struct dmub_cmd_cable_id_output output; /**< Output */ 5847 uint8_t output_raw; /**< Raw data output */ 5848 } data; 5849 }; 5850 5851 enum dmub_cmd_fused_io_sub_type { 5852 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5853 DMUB_CMD__FUSED_IO_ABORT = 1, 5854 }; 5855 5856 enum dmub_cmd_fused_request_type { 5857 FUSED_REQUEST_READ, 5858 FUSED_REQUEST_WRITE, 5859 FUSED_REQUEST_POLL, 5860 }; 5861 5862 enum dmub_cmd_fused_request_status { 5863 FUSED_REQUEST_STATUS_SUCCESS, 5864 FUSED_REQUEST_STATUS_BEGIN, 5865 FUSED_REQUEST_STATUS_SUBMIT, 5866 FUSED_REQUEST_STATUS_REPLY, 5867 FUSED_REQUEST_STATUS_POLL, 5868 FUSED_REQUEST_STATUS_ABORTED, 5869 FUSED_REQUEST_STATUS_FAILED = 0x80, 5870 FUSED_REQUEST_STATUS_INVALID, 5871 FUSED_REQUEST_STATUS_BUSY, 5872 FUSED_REQUEST_STATUS_TIMEOUT, 5873 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5874 }; 5875 5876 struct dmub_cmd_fused_request { 5877 uint8_t status; 5878 uint8_t type : 2; 5879 uint8_t _reserved0 : 3; 5880 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5881 uint8_t identifier; 5882 uint8_t _reserved1; 5883 uint32_t timeout_us; 5884 union dmub_cmd_fused_request_location { 5885 struct dmub_cmd_fused_request_location_i2c { 5886 uint8_t is_aux : 1; // False 5887 uint8_t ddc_line : 3; 5888 uint8_t over_aux : 1; 5889 uint8_t _reserved0 : 3; 5890 uint8_t address; 5891 uint8_t offset; 5892 uint8_t length; 5893 } i2c; 5894 struct dmub_cmd_fused_request_location_aux { 5895 uint32_t is_aux : 1; // True 5896 uint32_t ddc_line : 3; 5897 uint32_t address : 20; 5898 uint32_t length : 8; // Automatically split into 16B transactions 5899 } aux; 5900 } u; 5901 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5902 }; 5903 5904 struct dmub_rb_cmd_fused_io { 5905 struct dmub_cmd_header header; 5906 struct dmub_cmd_fused_request request; 5907 }; 5908 5909 /** 5910 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5911 */ 5912 enum dmub_cmd_secure_display_type { 5913 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5914 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5915 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5916 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5917 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5918 }; 5919 5920 #define MAX_ROI_NUM 2 5921 5922 struct dmub_cmd_roi_info { 5923 uint16_t x_start; 5924 uint16_t x_end; 5925 uint16_t y_start; 5926 uint16_t y_end; 5927 uint8_t otg_id; 5928 uint8_t phy_id; 5929 }; 5930 5931 struct dmub_cmd_roi_window_ctl { 5932 uint16_t x_start; 5933 uint16_t x_end; 5934 uint16_t y_start; 5935 uint16_t y_end; 5936 bool enable; 5937 }; 5938 5939 struct dmub_cmd_roi_ctl_info { 5940 uint8_t otg_id; 5941 uint8_t phy_id; 5942 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5943 }; 5944 5945 /** 5946 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5947 */ 5948 struct dmub_rb_cmd_secure_display { 5949 struct dmub_cmd_header header; 5950 /** 5951 * Data passed from driver to dmub firmware. 5952 */ 5953 struct dmub_cmd_roi_info roi_info; 5954 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5955 }; 5956 5957 /** 5958 * Command type of a DMUB_CMD__PSP command 5959 */ 5960 enum dmub_cmd_psp_type { 5961 DMUB_CMD__PSP_ASSR_ENABLE = 0 5962 }; 5963 5964 /** 5965 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5966 */ 5967 struct dmub_cmd_assr_enable_data { 5968 /** 5969 * ASSR enable or disable. 5970 */ 5971 uint8_t enable; 5972 /** 5973 * PHY port type. 5974 * Indicates eDP / non-eDP port type 5975 */ 5976 uint8_t phy_port_type; 5977 /** 5978 * PHY port ID. 5979 */ 5980 uint8_t phy_port_id; 5981 /** 5982 * Link encoder index. 5983 */ 5984 uint8_t link_enc_index; 5985 /** 5986 * HPO mode. 5987 */ 5988 uint8_t hpo_mode; 5989 5990 /** 5991 * Reserved field. 5992 */ 5993 uint8_t reserved[7]; 5994 }; 5995 5996 /** 5997 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5998 */ 5999 struct dmub_rb_cmd_assr_enable { 6000 /** 6001 * Command header. 6002 */ 6003 struct dmub_cmd_header header; 6004 6005 /** 6006 * Assr data. 6007 */ 6008 struct dmub_cmd_assr_enable_data assr_data; 6009 6010 /** 6011 * Reserved field. 6012 */ 6013 uint32_t reserved[3]; 6014 }; 6015 6016 /** 6017 * Current definition of "ips_mode" from driver 6018 */ 6019 enum ips_residency_mode { 6020 IPS_RESIDENCY__IPS1_MAX, 6021 IPS_RESIDENCY__IPS2, 6022 IPS_RESIDENCY__IPS1_RCG, 6023 IPS_RESIDENCY__IPS1_ONO2_ON, 6024 IPS_RESIDENCY__IPS1_Z8_RETENTION, 6025 IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, 6026 IPS_RESIDENCY__PG_ONO_CURRENT_STATE 6027 }; 6028 6029 #define NUM_IPS_HISTOGRAM_BUCKETS 16 6030 6031 /** 6032 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 6033 */ 6034 struct dmub_ips_residency_info { 6035 uint32_t residency_millipercent; 6036 uint32_t entry_counter; 6037 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 6038 uint64_t total_time_us; 6039 uint64_t total_inactive_time_us; 6040 uint32_t ono_pg_state_at_collection; 6041 uint32_t ono_pg_state_last_seen_in_ips; 6042 }; 6043 6044 /** 6045 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 6046 */ 6047 struct dmub_cmd_ips_residency_cntl_data { 6048 uint8_t panel_inst; 6049 uint8_t start_measurement; 6050 uint8_t padding[2]; // align to 4-byte boundary 6051 }; 6052 6053 struct dmub_rb_cmd_ips_residency_cntl { 6054 struct dmub_cmd_header header; 6055 struct dmub_cmd_ips_residency_cntl_data cntl_data; 6056 }; 6057 6058 /** 6059 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 6060 */ 6061 struct dmub_cmd_ips_query_residency_info_data { 6062 union dmub_addr dest; 6063 uint32_t size; 6064 uint32_t ips_mode; 6065 uint8_t panel_inst; 6066 uint8_t padding[3]; // align to 4-byte boundary 6067 }; 6068 6069 struct dmub_rb_cmd_ips_query_residency_info { 6070 struct dmub_cmd_header header; 6071 struct dmub_cmd_ips_query_residency_info_data info_data; 6072 }; 6073 6074 /** 6075 * union dmub_rb_cmd - DMUB inbox command. 6076 */ 6077 union dmub_rb_cmd { 6078 /** 6079 * Elements shared with all commands. 6080 */ 6081 struct dmub_rb_cmd_common cmd_common; 6082 /** 6083 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 6084 */ 6085 struct dmub_rb_cmd_read_modify_write read_modify_write; 6086 /** 6087 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 6088 */ 6089 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 6090 /** 6091 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 6092 */ 6093 struct dmub_rb_cmd_burst_write burst_write; 6094 /** 6095 * Definition of a DMUB_CMD__REG_REG_WAIT command. 6096 */ 6097 struct dmub_rb_cmd_reg_wait reg_wait; 6098 /** 6099 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 6100 */ 6101 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 6102 /** 6103 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 6104 */ 6105 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 6106 /** 6107 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 6108 */ 6109 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 6110 /** 6111 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 6112 */ 6113 struct dmub_rb_cmd_dpphy_init dpphy_init; 6114 /** 6115 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 6116 */ 6117 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 6118 /** 6119 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 6120 */ 6121 struct dmub_rb_cmd_domain_control domain_control; 6122 /** 6123 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 6124 */ 6125 struct dmub_rb_cmd_psr_set_version psr_set_version; 6126 /** 6127 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 6128 */ 6129 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 6130 /** 6131 * Definition of a DMUB_CMD__PSR_ENABLE command. 6132 */ 6133 struct dmub_rb_cmd_psr_enable psr_enable; 6134 /** 6135 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 6136 */ 6137 struct dmub_rb_cmd_psr_set_level psr_set_level; 6138 /** 6139 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 6140 */ 6141 struct dmub_rb_cmd_psr_force_static psr_force_static; 6142 /** 6143 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 6144 */ 6145 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6146 /** 6147 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6148 */ 6149 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6150 /** 6151 * Definition of a DMUB_CMD__HW_LOCK command. 6152 * Command is used by driver and FW. 6153 */ 6154 struct dmub_rb_cmd_lock_hw lock_hw; 6155 /** 6156 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6157 */ 6158 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6159 /** 6160 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6161 */ 6162 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6163 /** 6164 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6165 */ 6166 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6167 /** 6168 * Definition of a DMUB_CMD__MALL command. 6169 */ 6170 struct dmub_rb_cmd_mall mall; 6171 6172 /** 6173 * Definition of a DMUB_CMD__CAB command. 6174 */ 6175 struct dmub_rb_cmd_cab_for_ss cab; 6176 6177 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6178 6179 /** 6180 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6181 */ 6182 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6183 6184 /** 6185 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6186 */ 6187 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6188 6189 /** 6190 * Definition of DMUB_CMD__PANEL_CNTL commands. 6191 */ 6192 struct dmub_rb_cmd_panel_cntl panel_cntl; 6193 6194 /** 6195 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6196 */ 6197 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6198 6199 /** 6200 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6201 */ 6202 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6203 6204 /** 6205 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6206 */ 6207 struct dmub_rb_cmd_abm_set_level abm_set_level; 6208 6209 /** 6210 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6211 */ 6212 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6213 6214 /** 6215 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6216 */ 6217 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6218 6219 /** 6220 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6221 */ 6222 struct dmub_rb_cmd_abm_init_config abm_init_config; 6223 6224 /** 6225 * Definition of a DMUB_CMD__ABM_PAUSE command. 6226 */ 6227 struct dmub_rb_cmd_abm_pause abm_pause; 6228 6229 /** 6230 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6231 */ 6232 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6233 6234 /** 6235 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6236 */ 6237 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6238 6239 /** 6240 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6241 */ 6242 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6243 6244 /** 6245 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6246 */ 6247 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6248 6249 /** 6250 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6251 */ 6252 struct dmub_rb_cmd_abm_set_event abm_set_event; 6253 6254 /** 6255 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6256 */ 6257 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6258 6259 /** 6260 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6261 */ 6262 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6263 6264 /** 6265 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6266 */ 6267 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6268 6269 /** 6270 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6271 */ 6272 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6273 struct dmub_rb_cmd_drr_update drr_update; 6274 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6275 6276 /** 6277 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6278 */ 6279 struct dmub_rb_cmd_lvtma_control lvtma_control; 6280 /** 6281 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6282 */ 6283 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6284 /** 6285 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6286 */ 6287 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6288 /** 6289 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6290 */ 6291 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6292 /** 6293 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6294 */ 6295 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6296 /** 6297 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6298 */ 6299 struct dmub_rb_cmd_set_config_request set_config_request; 6300 /** 6301 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6302 */ 6303 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6304 /** 6305 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6306 */ 6307 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6308 /** 6309 * Definition of a DMUB_CMD__EDID_CEA command. 6310 */ 6311 struct dmub_rb_cmd_edid_cea edid_cea; 6312 /** 6313 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6314 */ 6315 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6316 6317 /** 6318 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6319 */ 6320 struct dmub_rb_cmd_query_hpd_state query_hpd; 6321 /** 6322 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6323 */ 6324 struct dmub_rb_cmd_secure_display secure_display; 6325 6326 /** 6327 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6328 */ 6329 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6330 /** 6331 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6332 */ 6333 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6334 /** 6335 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6336 */ 6337 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6338 /** 6339 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 6340 */ 6341 struct dmub_rb_cmd_replay_set_version replay_set_version; 6342 /* 6343 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6344 */ 6345 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6346 /** 6347 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6348 */ 6349 struct dmub_rb_cmd_replay_enable replay_enable; 6350 /** 6351 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6352 */ 6353 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6354 /** 6355 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6356 */ 6357 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6358 /** 6359 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6360 */ 6361 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6362 6363 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6364 /** 6365 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6366 */ 6367 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6368 /** 6369 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6370 */ 6371 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6372 /** 6373 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6374 */ 6375 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6376 /** 6377 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6378 */ 6379 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6380 /** 6381 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6382 */ 6383 struct dmub_rb_cmd_assr_enable assr_enable; 6384 6385 struct dmub_rb_cmd_fams2 fams2_config; 6386 6387 struct dmub_rb_cmd_ib ib_fams2_config; 6388 6389 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6390 6391 struct dmub_rb_cmd_fams2_flip fams2_flip; 6392 6393 struct dmub_rb_cmd_fused_io fused_io; 6394 6395 /** 6396 * Definition of a DMUB_CMD__LSDMA command. 6397 */ 6398 struct dmub_rb_cmd_lsdma lsdma; 6399 6400 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 6401 6402 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 6403 }; 6404 6405 /** 6406 * union dmub_rb_out_cmd - Outbox command 6407 */ 6408 union dmub_rb_out_cmd { 6409 /** 6410 * Parameters common to every command. 6411 */ 6412 struct dmub_rb_cmd_common cmd_common; 6413 /** 6414 * AUX reply command. 6415 */ 6416 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6417 /** 6418 * HPD notify command. 6419 */ 6420 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6421 /** 6422 * SET_CONFIG reply command. 6423 */ 6424 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6425 /** 6426 * DPIA notification command. 6427 */ 6428 struct dmub_rb_cmd_dpia_notification dpia_notification; 6429 /** 6430 * HPD sense notification command. 6431 */ 6432 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6433 struct dmub_rb_cmd_fused_io fused_io; 6434 }; 6435 #pragma pack(pop) 6436 6437 6438 //============================================================================== 6439 //</DMUB_CMD>=================================================================== 6440 //============================================================================== 6441 //< DMUB_RB>==================================================================== 6442 //============================================================================== 6443 6444 /** 6445 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6446 */ 6447 struct dmub_rb_init_params { 6448 void *ctx; /**< Caller provided context pointer */ 6449 void *base_address; /**< CPU base address for ring's data */ 6450 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6451 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6452 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6453 }; 6454 6455 /** 6456 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6457 */ 6458 struct dmub_rb { 6459 void *base_address; /**< CPU address for the ring's data */ 6460 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6461 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6462 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6463 6464 void *ctx; /**< Caller provided context pointer */ 6465 void *dmub; /**< Pointer to the DMUB interface */ 6466 }; 6467 6468 /** 6469 * @brief Checks if the ringbuffer is empty. 6470 * 6471 * @param rb DMUB Ringbuffer 6472 * @return true if empty 6473 * @return false otherwise 6474 */ 6475 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6476 { 6477 return (rb->wrpt == rb->rptr); 6478 } 6479 6480 /** 6481 * @brief gets number of outstanding requests in the RB 6482 * 6483 * @param rb DMUB Ringbuffer 6484 * @return true if full 6485 */ 6486 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6487 { 6488 uint32_t data_count; 6489 6490 if (rb->wrpt >= rb->rptr) 6491 data_count = rb->wrpt - rb->rptr; 6492 else 6493 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6494 6495 return data_count / DMUB_RB_CMD_SIZE; 6496 } 6497 6498 /** 6499 * @brief gets number of free buffers in the RB 6500 * 6501 * @param rb DMUB Ringbuffer 6502 * @return true if full 6503 */ 6504 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6505 { 6506 uint32_t data_count; 6507 6508 if (rb->wrpt >= rb->rptr) 6509 data_count = rb->wrpt - rb->rptr; 6510 else 6511 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6512 6513 /* +1 because 1 entry is always unusable */ 6514 data_count += DMUB_RB_CMD_SIZE; 6515 6516 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6517 } 6518 6519 /** 6520 * @brief Checks if the ringbuffer is full 6521 * 6522 * @param rb DMUB Ringbuffer 6523 * @return true if full 6524 * @return false otherwise 6525 */ 6526 static inline bool dmub_rb_full(struct dmub_rb *rb) 6527 { 6528 uint32_t data_count; 6529 6530 if (rb->wrpt >= rb->rptr) 6531 data_count = rb->wrpt - rb->rptr; 6532 else 6533 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6534 6535 /* -1 because 1 entry is always unusable */ 6536 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6537 } 6538 6539 /** 6540 * @brief Pushes a command into the ringbuffer 6541 * 6542 * @param rb DMUB ringbuffer 6543 * @param cmd The command to push 6544 * @return true if the ringbuffer was not full 6545 * @return false otherwise 6546 */ 6547 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6548 const union dmub_rb_cmd *cmd) 6549 { 6550 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6551 const uint8_t *src = (const uint8_t *)cmd; 6552 uint8_t i; 6553 6554 if (rb->capacity == 0) 6555 return false; 6556 6557 if (dmub_rb_full(rb)) 6558 return false; 6559 6560 // copying data 6561 for (i = 0; i < DMUB_RB_CMD_SIZE; i++) 6562 *dst++ = *src++; 6563 6564 rb->wrpt += DMUB_RB_CMD_SIZE; 6565 6566 if (rb->wrpt >= rb->capacity) 6567 rb->wrpt %= rb->capacity; 6568 6569 return true; 6570 } 6571 6572 /** 6573 * @brief Pushes a command into the DMUB outbox ringbuffer 6574 * 6575 * @param rb DMUB outbox ringbuffer 6576 * @param cmd Outbox command 6577 * @return true if not full 6578 * @return false otherwise 6579 */ 6580 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6581 const union dmub_rb_out_cmd *cmd) 6582 { 6583 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6584 const uint8_t *src = (const uint8_t *)cmd; 6585 6586 if (rb->capacity == 0) 6587 return false; 6588 6589 if (dmub_rb_full(rb)) 6590 return false; 6591 6592 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6593 6594 rb->wrpt += DMUB_RB_CMD_SIZE; 6595 6596 if (rb->wrpt >= rb->capacity) 6597 rb->wrpt %= rb->capacity; 6598 6599 return true; 6600 } 6601 6602 /** 6603 * @brief Returns the next unprocessed command in the ringbuffer. 6604 * 6605 * @param rb DMUB ringbuffer 6606 * @param cmd The command to return 6607 * @return true if not empty 6608 * @return false otherwise 6609 */ 6610 static inline bool dmub_rb_front(struct dmub_rb *rb, 6611 union dmub_rb_cmd **cmd) 6612 { 6613 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6614 6615 if (dmub_rb_empty(rb)) 6616 return false; 6617 6618 *cmd = (union dmub_rb_cmd *)rb_cmd; 6619 6620 return true; 6621 } 6622 6623 /** 6624 * @brief Determines the next ringbuffer offset. 6625 * 6626 * @param rb DMUB inbox ringbuffer 6627 * @param num_cmds Number of commands 6628 * @param next_rptr The next offset in the ringbuffer 6629 */ 6630 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6631 uint32_t num_cmds, 6632 uint32_t *next_rptr) 6633 { 6634 if (rb->capacity == 0) 6635 return; 6636 6637 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6638 6639 if (*next_rptr >= rb->capacity) 6640 *next_rptr %= rb->capacity; 6641 } 6642 6643 /** 6644 * @brief Returns a pointer to a command in the inbox. 6645 * 6646 * @param rb DMUB inbox ringbuffer 6647 * @param cmd The inbox command to return 6648 * @param rptr The ringbuffer offset 6649 * @return true if not empty 6650 * @return false otherwise 6651 */ 6652 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6653 union dmub_rb_cmd **cmd, 6654 uint32_t rptr) 6655 { 6656 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6657 6658 if (dmub_rb_empty(rb)) 6659 return false; 6660 6661 *cmd = (union dmub_rb_cmd *)rb_cmd; 6662 6663 return true; 6664 } 6665 6666 /** 6667 * @brief Returns the next unprocessed command in the outbox. 6668 * 6669 * @param rb DMUB outbox ringbuffer 6670 * @param cmd The outbox command to return 6671 * @return true if not empty 6672 * @return false otherwise 6673 */ 6674 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6675 union dmub_rb_out_cmd *cmd) 6676 { 6677 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6678 uint64_t *dst = (uint64_t *)cmd; 6679 uint8_t i; 6680 6681 if (dmub_rb_empty(rb)) 6682 return false; 6683 6684 // copying data 6685 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6686 *dst++ = *src++; 6687 6688 return true; 6689 } 6690 6691 /** 6692 * @brief Removes the front entry in the ringbuffer. 6693 * 6694 * @param rb DMUB ringbuffer 6695 * @return true if the command was removed 6696 * @return false if there were no commands 6697 */ 6698 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6699 { 6700 if (rb->capacity == 0) 6701 return false; 6702 6703 if (dmub_rb_empty(rb)) 6704 return false; 6705 6706 rb->rptr += DMUB_RB_CMD_SIZE; 6707 6708 if (rb->rptr >= rb->capacity) 6709 rb->rptr %= rb->capacity; 6710 6711 return true; 6712 } 6713 6714 /** 6715 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6716 * 6717 * Avoids a race condition where DMCUB accesses memory while 6718 * there are still writes in flight to framebuffer. 6719 * 6720 * @param rb DMUB ringbuffer 6721 */ 6722 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6723 { 6724 uint32_t rptr = rb->rptr; 6725 uint32_t wptr = rb->wrpt; 6726 6727 if (rb->capacity == 0) 6728 return; 6729 6730 while (rptr != wptr) { 6731 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6732 uint8_t i; 6733 6734 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6735 (void)READ_ONCE(*data++); 6736 6737 rptr += DMUB_RB_CMD_SIZE; 6738 if (rptr >= rb->capacity) 6739 rptr %= rb->capacity; 6740 } 6741 } 6742 6743 /** 6744 * @brief Initializes a DMCUB ringbuffer 6745 * 6746 * @param rb DMUB ringbuffer 6747 * @param init_params initial configuration for the ringbuffer 6748 */ 6749 static inline void dmub_rb_init(struct dmub_rb *rb, 6750 struct dmub_rb_init_params *init_params) 6751 { 6752 rb->base_address = init_params->base_address; 6753 rb->capacity = init_params->capacity; 6754 rb->rptr = init_params->read_ptr; 6755 rb->wrpt = init_params->write_ptr; 6756 } 6757 6758 /** 6759 * @brief Copies output data from in/out commands into the given command. 6760 * 6761 * @param rb DMUB ringbuffer 6762 * @param cmd Command to copy data into 6763 */ 6764 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6765 union dmub_rb_cmd *cmd) 6766 { 6767 // Copy rb entry back into command 6768 uint8_t *rd_ptr = (rb->rptr == 0) ? 6769 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6770 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6771 6772 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6773 } 6774 6775 //============================================================================== 6776 //</DMUB_RB>==================================================================== 6777 //============================================================================== 6778 #endif /* _DMUB_CMD_H_ */ 6779