1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310 struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326 }; 327 #pragma pack(pop) 328 329 /** 330 * Dirty rect definition. 331 */ 332 struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352 }; 353 354 /** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357 union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397 }; 398 399 /** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402 union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 uint32_t reserved : 18; 489 } bitfields; 490 491 uint32_t u32All; 492 }; 493 494 /** 495 * Flags record error state. 496 */ 497 union replay_visual_confirm_error_state_flags { 498 struct { 499 /** 500 * 0x1 (bit 0) - Desync Error flag. 501 */ 502 uint32_t desync_error : 1; 503 504 /** 505 * 0x2 (bit 1) - State Transition Error flag. 506 */ 507 uint32_t state_transition_error : 1; 508 509 /** 510 * 0x4 (bit 2) - Crc Error flag 511 */ 512 uint32_t crc_error : 1; 513 514 /** 515 * 0x8 (bit 3) - Reserved 516 */ 517 uint32_t reserved_3 : 1; 518 519 /** 520 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 521 * Added new debug flag to control DPCD. 522 */ 523 uint32_t incorrect_vtotal_in_static_screen : 1; 524 525 /** 526 * 0x20 (bit 5) - No doubled Refresh Rate. 527 */ 528 uint32_t no_double_rr : 1; 529 530 /** 531 * Reserved bit 6-7 532 */ 533 uint32_t reserved_6_7 : 2; 534 535 /** 536 * Reserved bit 9-31 537 */ 538 uint32_t reserved_9_31 : 24; 539 } bitfields; 540 541 uint32_t u32All; 542 }; 543 544 union replay_hw_flags { 545 struct { 546 /** 547 * @allow_alpm_fw_standby_mode: To indicate whether the 548 * ALPM FW standby mode is allowed 549 */ 550 uint32_t allow_alpm_fw_standby_mode : 1; 551 552 /* 553 * @dsc_enable_status: DSC enable status in driver 554 */ 555 uint32_t dsc_enable_status : 1; 556 557 /** 558 * @fec_enable_status: receive fec enable/disable status from driver 559 */ 560 uint32_t fec_enable_status : 1; 561 562 /* 563 * @smu_optimizations_en: SMU power optimization. 564 * Only when active display is Replay capable and display enters Replay. 565 * Trigger interrupt to SMU to powerup/down. 566 */ 567 uint32_t smu_optimizations_en : 1; 568 569 /** 570 * @phy_power_state: Indicates current phy power state 571 */ 572 uint32_t phy_power_state : 1; 573 574 /** 575 * @link_power_state: Indicates current link power state 576 */ 577 uint32_t link_power_state : 1; 578 /** 579 * Use TPS3 signal when restore main link. 580 */ 581 uint32_t force_wakeup_by_tps3 : 1; 582 /** 583 * @is_alpm_initialized: Indicates whether ALPM is initialized 584 */ 585 uint32_t is_alpm_initialized : 1; 586 587 /** 588 * @alpm_mode: Indicates ALPM mode selected 589 */ 590 uint32_t alpm_mode : 2; 591 } bitfields; 592 593 uint32_t u32All; 594 }; 595 596 union fw_assisted_mclk_switch_version { 597 struct { 598 uint8_t minor : 5; 599 uint8_t major : 3; 600 }; 601 uint8_t ver; 602 }; 603 604 /** 605 * DMUB feature capabilities. 606 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 607 */ 608 struct dmub_feature_caps { 609 /** 610 * Max PSR version supported by FW. 611 */ 612 uint8_t psr; 613 uint8_t fw_assisted_mclk_switch_ver; 614 uint8_t reserved[4]; 615 uint8_t subvp_psr_support; 616 uint8_t gecc_enable; 617 uint8_t replay_supported; 618 uint8_t replay_reserved[3]; 619 uint8_t abm_aux_backlight_support; 620 }; 621 622 struct dmub_visual_confirm_color { 623 /** 624 * Maximum 10 bits color value 625 */ 626 uint16_t color_r_cr; 627 uint16_t color_g_y; 628 uint16_t color_b_cb; 629 uint16_t panel_inst; 630 }; 631 632 //============================================================================== 633 //</DMUB_TYPES>================================================================= 634 //============================================================================== 635 //< DMUB_META>================================================================== 636 //============================================================================== 637 #pragma pack(push, 1) 638 639 /* Magic value for identifying dmub_fw_meta_info */ 640 #define DMUB_FW_META_MAGIC 0x444D5542 641 642 /* Offset from the end of the file to the dmub_fw_meta_info */ 643 #define DMUB_FW_META_OFFSET 0x24 644 645 /** 646 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 647 */ 648 union dmub_fw_meta_feature_bits { 649 struct { 650 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 651 uint32_t reserved : 31; 652 } bits; /**< status bits */ 653 uint32_t all; /**< 32-bit access to status bits */ 654 }; 655 656 /** 657 * struct dmub_fw_meta_info - metadata associated with fw binary 658 * 659 * NOTE: This should be considered a stable API. Fields should 660 * not be repurposed or reordered. New fields should be 661 * added instead to extend the structure. 662 * 663 * @magic_value: magic value identifying DMUB firmware meta info 664 * @fw_region_size: size of the firmware state region 665 * @trace_buffer_size: size of the tracebuffer region 666 * @fw_version: the firmware version information 667 * @dal_fw: 1 if the firmware is DAL 668 * @shared_state_size: size of the shared state region in bytes 669 * @shared_state_features: number of shared state features 670 */ 671 struct dmub_fw_meta_info { 672 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 673 uint32_t fw_region_size; /**< size of the firmware state region */ 674 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 675 uint32_t fw_version; /**< the firmware version information */ 676 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 677 uint8_t reserved[3]; /**< padding bits */ 678 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 679 uint16_t shared_state_features; /**< number of shared state features */ 680 uint16_t reserved2; /**< padding bytes */ 681 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 682 }; 683 684 /** 685 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 686 */ 687 union dmub_fw_meta { 688 struct dmub_fw_meta_info info; /**< metadata info */ 689 uint8_t reserved[64]; /**< padding bits */ 690 }; 691 692 #pragma pack(pop) 693 694 //============================================================================== 695 //< DMUB Trace Buffer>================================================================ 696 //============================================================================== 697 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 698 /** 699 * dmub_trace_code_t - firmware trace code, 32-bits 700 */ 701 typedef uint32_t dmub_trace_code_t; 702 703 /** 704 * struct dmcub_trace_buf_entry - Firmware trace entry 705 */ 706 struct dmcub_trace_buf_entry { 707 dmub_trace_code_t trace_code; /**< trace code for the event */ 708 uint32_t tick_count; /**< the tick count at time of trace */ 709 uint32_t param0; /**< trace defined parameter 0 */ 710 uint32_t param1; /**< trace defined parameter 1 */ 711 }; 712 #endif 713 714 //============================================================================== 715 //< DMUB_STATUS>================================================================ 716 //============================================================================== 717 718 /** 719 * DMCUB scratch registers can be used to determine firmware status. 720 * Current scratch register usage is as follows: 721 * 722 * SCRATCH0: FW Boot Status register 723 * SCRATCH5: LVTMA Status Register 724 * SCRATCH15: FW Boot Options register 725 */ 726 727 /** 728 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 729 */ 730 union dmub_fw_boot_status { 731 struct { 732 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 733 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 734 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 735 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 736 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 737 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 738 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 739 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 740 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 741 } bits; /**< status bits */ 742 uint32_t all; /**< 32-bit access to status bits */ 743 }; 744 745 /** 746 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 747 */ 748 enum dmub_fw_boot_status_bit { 749 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 750 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 751 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 752 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 753 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 754 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 755 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 756 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 757 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 758 }; 759 760 /* Register bit definition for SCRATCH5 */ 761 union dmub_lvtma_status { 762 struct { 763 uint32_t psp_ok : 1; 764 uint32_t edp_on : 1; 765 uint32_t reserved : 30; 766 } bits; 767 uint32_t all; 768 }; 769 770 enum dmub_lvtma_status_bit { 771 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 772 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 773 }; 774 775 enum dmub_ips_disable_type { 776 DMUB_IPS_ENABLE = 0, 777 DMUB_IPS_DISABLE_ALL = 1, 778 DMUB_IPS_DISABLE_IPS1 = 2, 779 DMUB_IPS_DISABLE_IPS2 = 3, 780 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 781 DMUB_IPS_DISABLE_DYNAMIC = 5, 782 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 783 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 784 }; 785 786 enum dmub_ips_rcg_disable_type { 787 DMUB_IPS_RCG_ENABLE = 0, 788 DMUB_IPS0_RCG_DISABLE = 1, 789 DMUB_IPS1_RCG_DISABLE = 2, 790 DMUB_IPS_RCG_DISABLE = 3 791 }; 792 793 #define DMUB_IPS1_ALLOW_MASK 0x00000001 794 #define DMUB_IPS2_ALLOW_MASK 0x00000002 795 #define DMUB_IPS1_COMMIT_MASK 0x00000004 796 #define DMUB_IPS2_COMMIT_MASK 0x00000008 797 798 enum dmub_ips_comand_type { 799 /** 800 * Start/stop IPS residency measurements for a given IPS mode 801 */ 802 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 803 /** 804 * Query IPS residency information for a given IPS mode 805 */ 806 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 807 }; 808 809 /** 810 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 811 */ 812 union dmub_fw_boot_options { 813 struct { 814 uint32_t pemu_env : 1; /**< 1 if PEMU */ 815 uint32_t fpga_env : 1; /**< 1 if FPGA */ 816 uint32_t optimized_init : 1; /**< 1 if optimized init */ 817 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 818 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 819 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 820 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 821 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 822 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 823 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 824 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 825 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 826 uint32_t power_optimization: 1; 827 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 828 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 829 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 830 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 831 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 832 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 833 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 834 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 835 uint32_t ips_disable: 3; /* options to disable ips support*/ 836 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 837 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 838 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 839 uint32_t reserved : 6; /**< reserved */ 840 } bits; /**< boot bits */ 841 uint32_t all; /**< 32-bit access to bits */ 842 }; 843 844 enum dmub_fw_boot_options_bit { 845 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 846 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 847 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 848 }; 849 850 //============================================================================== 851 //< DMUB_SHARED_STATE>========================================================== 852 //============================================================================== 853 854 /** 855 * Shared firmware state between driver and firmware for lockless communication 856 * in situations where the inbox/outbox may be unavailable. 857 * 858 * Each structure *must* be at most 256-bytes in size. The layout allocation is 859 * described below: 860 * 861 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 862 */ 863 864 /** 865 * enum dmub_shared_state_feature_id - List of shared state features. 866 */ 867 enum dmub_shared_state_feature_id { 868 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 869 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 870 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 871 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 872 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 873 }; 874 875 /** 876 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 877 */ 878 union dmub_shared_state_ips_fw_signals { 879 struct { 880 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 881 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 882 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 883 uint32_t detection_required : 1; /**< 1 if detection is required */ 884 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 885 uint32_t reserved_bits : 27; /**< Reversed */ 886 } bits; 887 uint32_t all; 888 }; 889 890 /** 891 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 892 */ 893 union dmub_shared_state_ips_driver_signals { 894 struct { 895 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 896 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 897 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 898 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 899 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 900 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 901 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 902 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 903 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 904 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 905 uint32_t reserved_bits : 22; /**< Reversed bits */ 906 } bits; 907 uint32_t all; 908 }; 909 910 /** 911 * IPS FW Version 912 */ 913 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 914 915 struct dmub_shared_state_debug_setup { 916 union { 917 struct { 918 uint32_t exclude_points[62]; 919 } profile_mode; 920 }; 921 }; 922 923 /** 924 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 925 */ 926 struct dmub_shared_state_ips_fw { 927 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 928 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 929 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 930 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 931 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 932 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 933 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 934 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 935 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 936 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 937 }; /* 248-bytes, fixed */ 938 939 /** 940 * IPS Driver Version 941 */ 942 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 943 944 /** 945 * struct dmub_shared_state_ips_driver - Driver state for IPS. 946 */ 947 struct dmub_shared_state_ips_driver { 948 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 949 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 950 }; /* 248-bytes, fixed */ 951 952 /** 953 * enum dmub_shared_state_feature_common - Generic payload. 954 */ 955 struct dmub_shared_state_feature_common { 956 uint32_t padding[62]; 957 }; /* 248-bytes, fixed */ 958 959 /** 960 * enum dmub_shared_state_feature_header - Feature description. 961 */ 962 struct dmub_shared_state_feature_header { 963 uint16_t id; /**< Feature ID */ 964 uint16_t version; /**< Feature version */ 965 uint32_t reserved; /**< Reserved bytes. */ 966 }; /* 8 bytes, fixed */ 967 968 /** 969 * struct dmub_shared_state_feature_block - Feature block. 970 */ 971 struct dmub_shared_state_feature_block { 972 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 973 union dmub_shared_feature_state_union { 974 struct dmub_shared_state_feature_common common; /**< Generic data */ 975 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 976 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 977 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 978 } data; /**< Shared state data. */ 979 }; /* 256-bytes, fixed */ 980 981 /** 982 * Shared state size in bytes. 983 */ 984 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 985 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 986 987 //============================================================================== 988 //</DMUB_STATUS>================================================================ 989 //============================================================================== 990 //< DMUB_VBIOS>================================================================= 991 //============================================================================== 992 993 /* 994 * enum dmub_cmd_vbios_type - VBIOS commands. 995 * 996 * Command IDs should be treated as stable ABI. 997 * Do not reuse or modify IDs. 998 */ 999 enum dmub_cmd_vbios_type { 1000 /** 1001 * Configures the DIG encoder. 1002 */ 1003 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1004 /** 1005 * Controls the PHY. 1006 */ 1007 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1008 /** 1009 * Sets the pixel clock/symbol clock. 1010 */ 1011 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1012 /** 1013 * Enables or disables power gating. 1014 */ 1015 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1016 /** 1017 * Controls embedded panels. 1018 */ 1019 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1020 /** 1021 * Query DP alt status on a transmitter. 1022 */ 1023 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1024 /** 1025 * Control PHY FSM 1026 */ 1027 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1028 /** 1029 * Controls domain power gating 1030 */ 1031 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1032 }; 1033 1034 //============================================================================== 1035 //</DMUB_VBIOS>================================================================= 1036 //============================================================================== 1037 //< DMUB_GPINT>================================================================= 1038 //============================================================================== 1039 1040 /** 1041 * The shifts and masks below may alternatively be used to format and read 1042 * the command register bits. 1043 */ 1044 1045 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1046 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1047 1048 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1049 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1050 1051 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1052 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1053 1054 /** 1055 * Command responses. 1056 */ 1057 1058 /** 1059 * Return response for DMUB_GPINT__STOP_FW command. 1060 */ 1061 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1062 1063 /** 1064 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1065 */ 1066 union dmub_gpint_data_register { 1067 struct { 1068 uint32_t param : 16; /**< 16-bit parameter */ 1069 uint32_t command_code : 12; /**< GPINT command */ 1070 uint32_t status : 4; /**< Command status bit */ 1071 } bits; /**< GPINT bit access */ 1072 uint32_t all; /**< GPINT 32-bit access */ 1073 }; 1074 1075 /* 1076 * enum dmub_gpint_command - GPINT command to DMCUB FW 1077 * 1078 * Command IDs should be treated as stable ABI. 1079 * Do not reuse or modify IDs. 1080 */ 1081 enum dmub_gpint_command { 1082 /** 1083 * Invalid command, ignored. 1084 */ 1085 DMUB_GPINT__INVALID_COMMAND = 0, 1086 /** 1087 * DESC: Queries the firmware version. 1088 * RETURN: Firmware version. 1089 */ 1090 DMUB_GPINT__GET_FW_VERSION = 1, 1091 /** 1092 * DESC: Halts the firmware. 1093 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1094 */ 1095 DMUB_GPINT__STOP_FW = 2, 1096 /** 1097 * DESC: Get PSR state from FW. 1098 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1099 */ 1100 DMUB_GPINT__GET_PSR_STATE = 7, 1101 /** 1102 * DESC: Notifies DMCUB of the currently active streams. 1103 * ARGS: Stream mask, 1 bit per active stream index. 1104 */ 1105 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1106 /** 1107 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1108 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1109 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1110 * RETURN: PSR residency in milli-percent. 1111 */ 1112 DMUB_GPINT__PSR_RESIDENCY = 9, 1113 1114 /** 1115 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1116 */ 1117 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1118 1119 /** 1120 * DESC: Get REPLAY state from FW. 1121 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1122 */ 1123 DMUB_GPINT__GET_REPLAY_STATE = 13, 1124 1125 /** 1126 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1127 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1128 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1129 * RETURN: REPLAY residency in milli-percent. 1130 */ 1131 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1132 1133 /** 1134 * DESC: Copy bounding box to the host. 1135 * ARGS: Version of bounding box to copy 1136 * RETURN: Result of copying bounding box 1137 */ 1138 DMUB_GPINT__BB_COPY = 96, 1139 1140 /** 1141 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1142 * ARGS: The word3 for the 64 bit address 1143 */ 1144 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1145 1146 /** 1147 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1148 * ARGS: The word2 for the 64 bit address 1149 */ 1150 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1151 1152 /** 1153 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1154 * ARGS: The word1 for the 64 bit address 1155 */ 1156 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1157 1158 /** 1159 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1160 * ARGS: The word0 for the 64 bit address 1161 */ 1162 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1163 1164 /** 1165 * DESC: Updates the trace buffer lower 32-bit mask. 1166 * ARGS: The new mask 1167 * RETURN: Lower 32-bit mask. 1168 */ 1169 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1170 1171 /** 1172 * DESC: Updates the trace buffer mask bit0~bit15. 1173 * ARGS: The new mask 1174 * RETURN: Lower 32-bit mask. 1175 */ 1176 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1177 1178 /** 1179 * DESC: Updates the trace buffer mask bit16~bit31. 1180 * ARGS: The new mask 1181 * RETURN: Lower 32-bit mask. 1182 */ 1183 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1184 1185 /** 1186 * DESC: Updates the trace buffer mask bit32~bit47. 1187 * ARGS: The new mask 1188 * RETURN: Lower 32-bit mask. 1189 */ 1190 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1191 1192 /** 1193 * DESC: Updates the trace buffer mask bit48~bit63. 1194 * ARGS: The new mask 1195 * RETURN: Lower 32-bit mask. 1196 */ 1197 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1198 1199 /** 1200 * DESC: Read the trace buffer mask bi0~bit15. 1201 */ 1202 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1203 1204 /** 1205 * DESC: Read the trace buffer mask bit16~bit31. 1206 */ 1207 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1208 1209 /** 1210 * DESC: Read the trace buffer mask bi32~bit47. 1211 */ 1212 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1213 1214 /** 1215 * DESC: Updates the trace buffer mask bit32~bit63. 1216 */ 1217 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1218 1219 /** 1220 * DESC: Set IPS residency measurement 1221 * ARGS: 0 - Disable ips measurement 1222 * 1 - Enable ips measurement 1223 */ 1224 DMUB_GPINT__IPS_RESIDENCY = 121, 1225 1226 /** 1227 * DESC: Enable measurements for various task duration 1228 * ARGS: 0 - Disable measurement 1229 * 1 - Enable measurement 1230 */ 1231 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1232 1233 /** 1234 * DESC: Gets IPS residency in microseconds 1235 * ARGS: 0 - Return IPS1 residency 1236 * 1 - Return IPS2 residency 1237 * 2 - Return IPS1_RCG residency 1238 * 3 - Return IPS1_ONO2_ON residency 1239 * RETURN: Total residency in microseconds - lower 32 bits 1240 */ 1241 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1242 1243 /** 1244 * DESC: Gets IPS1 histogram counts 1245 * ARGS: Bucket index 1246 * RETURN: Total count for the bucket 1247 */ 1248 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1249 1250 /** 1251 * DESC: Gets IPS2 histogram counts 1252 * ARGS: Bucket index 1253 * RETURN: Total count for the bucket 1254 */ 1255 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1256 1257 /** 1258 * DESC: Gets IPS residency 1259 * ARGS: 0 - Return IPS1 residency 1260 * 1 - Return IPS2 residency 1261 * 2 - Return IPS1_RCG residency 1262 * 3 - Return IPS1_ONO2_ON residency 1263 * RETURN: Total residency in milli-percent. 1264 */ 1265 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1266 1267 /** 1268 * DESC: Gets IPS1_RCG histogram counts 1269 * ARGS: Bucket index 1270 * RETURN: Total count for the bucket 1271 */ 1272 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1273 1274 /** 1275 * DESC: Gets IPS1_ONO2_ON histogram counts 1276 * ARGS: Bucket index 1277 * RETURN: Total count for the bucket 1278 */ 1279 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1280 1281 /** 1282 * DESC: Gets IPS entry counter during residency measurement 1283 * ARGS: 0 - Return IPS1 entry counts 1284 * 1 - Return IPS2 entry counts 1285 * 2 - Return IPS1_RCG entry counts 1286 * 3 - Return IPS2_ONO2_ON entry counts 1287 * RETURN: Entry counter for selected IPS mode 1288 */ 1289 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1290 1291 /** 1292 * DESC: Gets IPS inactive residency in microseconds 1293 * ARGS: 0 - Return IPS1_MAX residency 1294 * 1 - Return IPS2 residency 1295 * 2 - Return IPS1_RCG residency 1296 * 3 - Return IPS1_ONO2_ON residency 1297 * RETURN: Total inactive residency in microseconds - lower 32 bits 1298 */ 1299 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1300 1301 /** 1302 * DESC: Gets IPS inactive residency in microseconds 1303 * ARGS: 0 - Return IPS1_MAX residency 1304 * 1 - Return IPS2 residency 1305 * 2 - Return IPS1_RCG residency 1306 * 3 - Return IPS1_ONO2_ON residency 1307 * RETURN: Total inactive residency in microseconds - upper 32 bits 1308 */ 1309 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1310 1311 /** 1312 * DESC: Gets IPS residency in microseconds 1313 * ARGS: 0 - Return IPS1 residency 1314 * 1 - Return IPS2 residency 1315 * 2 - Return IPS1_RCG residency 1316 * 3 - Return IPS1_ONO2_ON residency 1317 * RETURN: Total residency in microseconds - upper 32 bits 1318 */ 1319 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1320 /** 1321 * DESC: Setup debug configs. 1322 */ 1323 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1324 /** 1325 * DESC: Initiates IPS wake sequence. 1326 */ 1327 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1328 }; 1329 1330 /** 1331 * INBOX0 generic command definition 1332 */ 1333 union dmub_inbox0_cmd_common { 1334 struct { 1335 uint32_t command_code: 8; /**< INBOX0 command code */ 1336 uint32_t param: 24; /**< 24-bit parameter */ 1337 } bits; 1338 uint32_t all; 1339 }; 1340 1341 /** 1342 * INBOX0 hw_lock command definition 1343 */ 1344 union dmub_inbox0_cmd_lock_hw { 1345 struct { 1346 uint32_t command_code: 8; 1347 1348 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1349 uint32_t hw_lock_client: 2; 1350 1351 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1352 uint32_t otg_inst: 3; 1353 uint32_t opp_inst: 3; 1354 uint32_t dig_inst: 3; 1355 1356 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1357 uint32_t lock_pipe: 1; 1358 uint32_t lock_cursor: 1; 1359 uint32_t lock_dig: 1; 1360 uint32_t triple_buffer_lock: 1; 1361 1362 uint32_t lock: 1; /**< Lock */ 1363 uint32_t should_release: 1; /**< Release */ 1364 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1365 } bits; 1366 uint32_t all; 1367 }; 1368 1369 union dmub_inbox0_data_register { 1370 union dmub_inbox0_cmd_common inbox0_cmd_common; 1371 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1372 }; 1373 1374 enum dmub_inbox0_command { 1375 /** 1376 * DESC: Invalid command, ignored. 1377 */ 1378 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1379 /** 1380 * DESC: Notification to acquire/release HW lock 1381 * ARGS: 1382 */ 1383 DMUB_INBOX0_CMD__HW_LOCK = 1, 1384 }; 1385 //============================================================================== 1386 //</DMUB_GPINT>================================================================= 1387 //============================================================================== 1388 //< DMUB_CMD>=================================================================== 1389 //============================================================================== 1390 1391 /** 1392 * Size in bytes of each DMUB command. 1393 */ 1394 #define DMUB_RB_CMD_SIZE 64 1395 1396 /** 1397 * Maximum number of items in the DMUB ringbuffer. 1398 */ 1399 #define DMUB_RB_MAX_ENTRY 128 1400 1401 /** 1402 * Ringbuffer size in bytes. 1403 */ 1404 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1405 1406 /** 1407 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1408 */ 1409 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1410 1411 /** 1412 * Ringbuffer size in bytes. 1413 */ 1414 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1415 1416 /** 1417 * REG_SET mask for reg offload. 1418 */ 1419 #define REG_SET_MASK 0xFFFF 1420 1421 /* 1422 * enum dmub_cmd_type - DMUB inbox command. 1423 * 1424 * Command IDs should be treated as stable ABI. 1425 * Do not reuse or modify IDs. 1426 */ 1427 enum dmub_cmd_type { 1428 /** 1429 * Invalid command. 1430 */ 1431 DMUB_CMD__NULL = 0, 1432 /** 1433 * Read modify write register sequence offload. 1434 */ 1435 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1436 /** 1437 * Field update register sequence offload. 1438 */ 1439 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1440 /** 1441 * Burst write sequence offload. 1442 */ 1443 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1444 /** 1445 * Reg wait sequence offload. 1446 */ 1447 DMUB_CMD__REG_REG_WAIT = 4, 1448 /** 1449 * Workaround to avoid HUBP underflow during NV12 playback. 1450 */ 1451 DMUB_CMD__PLAT_54186_WA = 5, 1452 /** 1453 * Command type used to query FW feature caps. 1454 */ 1455 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1456 /** 1457 * Command type used to get visual confirm color. 1458 */ 1459 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1460 /** 1461 * Command type used for all PSR commands. 1462 */ 1463 DMUB_CMD__PSR = 64, 1464 /** 1465 * Command type used for all MALL commands. 1466 */ 1467 DMUB_CMD__MALL = 65, 1468 /** 1469 * Command type used for all ABM commands. 1470 */ 1471 DMUB_CMD__ABM = 66, 1472 /** 1473 * Command type used to update dirty rects in FW. 1474 */ 1475 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1476 /** 1477 * Command type used to update cursor info in FW. 1478 */ 1479 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1480 /** 1481 * Command type used for HW locking in FW. 1482 */ 1483 DMUB_CMD__HW_LOCK = 69, 1484 /** 1485 * Command type used to access DP AUX. 1486 */ 1487 DMUB_CMD__DP_AUX_ACCESS = 70, 1488 /** 1489 * Command type used for OUTBOX1 notification enable 1490 */ 1491 DMUB_CMD__OUTBOX1_ENABLE = 71, 1492 1493 /** 1494 * Command type used for all idle optimization commands. 1495 */ 1496 DMUB_CMD__IDLE_OPT = 72, 1497 /** 1498 * Command type used for all clock manager commands. 1499 */ 1500 DMUB_CMD__CLK_MGR = 73, 1501 /** 1502 * Command type used for all panel control commands. 1503 */ 1504 DMUB_CMD__PANEL_CNTL = 74, 1505 1506 /** 1507 * Command type used for all CAB commands. 1508 */ 1509 DMUB_CMD__CAB_FOR_SS = 75, 1510 1511 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1512 1513 /** 1514 * Command type used for interfacing with DPIA. 1515 */ 1516 DMUB_CMD__DPIA = 77, 1517 /** 1518 * Command type used for EDID CEA parsing 1519 */ 1520 DMUB_CMD__EDID_CEA = 79, 1521 /** 1522 * Command type used for getting usbc cable ID 1523 */ 1524 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1525 /** 1526 * Command type used to query HPD state. 1527 */ 1528 DMUB_CMD__QUERY_HPD_STATE = 82, 1529 /** 1530 * Command type used for all VBIOS interface commands. 1531 */ 1532 /** 1533 * Command type used for all REPLAY commands. 1534 */ 1535 DMUB_CMD__REPLAY = 83, 1536 1537 /** 1538 * Command type used for all SECURE_DISPLAY commands. 1539 */ 1540 DMUB_CMD__SECURE_DISPLAY = 85, 1541 1542 /** 1543 * Command type used to set DPIA HPD interrupt state 1544 */ 1545 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1546 1547 /** 1548 * Command type used for all PSP commands. 1549 */ 1550 DMUB_CMD__PSP = 88, 1551 1552 /** 1553 * Command type used for all Fused IO commands. 1554 */ 1555 DMUB_CMD__FUSED_IO = 89, 1556 1557 /** 1558 * Command type used for all LSDMA commands. 1559 */ 1560 DMUB_CMD__LSDMA = 90, 1561 1562 /** 1563 * Command type use for all IPS commands. 1564 */ 1565 DMUB_CMD__IPS = 91, 1566 1567 DMUB_CMD__VBIOS = 128, 1568 }; 1569 1570 /** 1571 * enum dmub_out_cmd_type - DMUB outbox commands. 1572 */ 1573 enum dmub_out_cmd_type { 1574 /** 1575 * Invalid outbox command, ignored. 1576 */ 1577 DMUB_OUT_CMD__NULL = 0, 1578 /** 1579 * Command type used for DP AUX Reply data notification 1580 */ 1581 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1582 /** 1583 * Command type used for DP HPD event notification 1584 */ 1585 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1586 /** 1587 * Command type used for SET_CONFIG Reply notification 1588 */ 1589 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1590 /** 1591 * Command type used for USB4 DPIA notification 1592 */ 1593 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1594 /** 1595 * Command type used for HPD redetect notification 1596 */ 1597 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1598 /** 1599 * Command type used for Fused IO notification 1600 */ 1601 DMUB_OUT_CMD__FUSED_IO = 7, 1602 }; 1603 1604 /* DMUB_CMD__DPIA command sub-types. */ 1605 enum dmub_cmd_dpia_type { 1606 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1607 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1608 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1609 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1610 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1611 }; 1612 1613 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1614 enum dmub_cmd_dpia_notification_type { 1615 DPIA_NOTIFY__BW_ALLOCATION = 0, 1616 }; 1617 1618 #pragma pack(push, 1) 1619 1620 /** 1621 * struct dmub_cmd_header - Common command header fields. 1622 */ 1623 struct dmub_cmd_header { 1624 unsigned int type : 8; /**< command type */ 1625 unsigned int sub_type : 8; /**< command sub type */ 1626 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1627 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1628 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1629 unsigned int reserved0 : 5; /**< reserved bits */ 1630 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1631 unsigned int reserved1 : 2; /**< reserved bits */ 1632 }; 1633 1634 /* 1635 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1636 * 1637 * 60 payload bytes can hold up to 5 sets of read modify writes, 1638 * each take 3 dwords. 1639 * 1640 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1641 * 1642 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1643 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1644 */ 1645 struct dmub_cmd_read_modify_write_sequence { 1646 uint32_t addr; /**< register address */ 1647 uint32_t modify_mask; /**< modify mask */ 1648 uint32_t modify_value; /**< modify value */ 1649 }; 1650 1651 /** 1652 * Maximum number of ops in read modify write sequence. 1653 */ 1654 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1655 1656 /** 1657 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1658 */ 1659 struct dmub_rb_cmd_read_modify_write { 1660 struct dmub_cmd_header header; /**< command header */ 1661 /** 1662 * Read modify write sequence. 1663 */ 1664 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1665 }; 1666 1667 /* 1668 * Update a register with specified masks and values sequeunce 1669 * 1670 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1671 * 1672 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1673 * 1674 * 1675 * USE CASE: 1676 * 1. auto-increment register where additional read would update pointer and produce wrong result 1677 * 2. toggle a bit without read in the middle 1678 */ 1679 1680 struct dmub_cmd_reg_field_update_sequence { 1681 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1682 uint32_t modify_value; /**< value to update with */ 1683 }; 1684 1685 /** 1686 * Maximum number of ops in field update sequence. 1687 */ 1688 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1689 1690 /** 1691 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1692 */ 1693 struct dmub_rb_cmd_reg_field_update_sequence { 1694 struct dmub_cmd_header header; /**< command header */ 1695 uint32_t addr; /**< register address */ 1696 /** 1697 * Field update sequence. 1698 */ 1699 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1700 }; 1701 1702 1703 /** 1704 * Maximum number of burst write values. 1705 */ 1706 #define DMUB_BURST_WRITE_VALUES__MAX 14 1707 1708 /* 1709 * struct dmub_rb_cmd_burst_write - Burst write 1710 * 1711 * support use case such as writing out LUTs. 1712 * 1713 * 60 payload bytes can hold up to 14 values to write to given address 1714 * 1715 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1716 */ 1717 struct dmub_rb_cmd_burst_write { 1718 struct dmub_cmd_header header; /**< command header */ 1719 uint32_t addr; /**< register start address */ 1720 /** 1721 * Burst write register values. 1722 */ 1723 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1724 }; 1725 1726 /** 1727 * struct dmub_rb_cmd_common - Common command header 1728 */ 1729 struct dmub_rb_cmd_common { 1730 struct dmub_cmd_header header; /**< command header */ 1731 /** 1732 * Padding to RB_CMD_SIZE 1733 */ 1734 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1735 }; 1736 1737 /** 1738 * struct dmub_cmd_reg_wait_data - Register wait data 1739 */ 1740 struct dmub_cmd_reg_wait_data { 1741 uint32_t addr; /**< Register address */ 1742 uint32_t mask; /**< Mask for register bits */ 1743 uint32_t condition_field_value; /**< Value to wait for */ 1744 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1745 }; 1746 1747 /** 1748 * struct dmub_rb_cmd_reg_wait - Register wait command 1749 */ 1750 struct dmub_rb_cmd_reg_wait { 1751 struct dmub_cmd_header header; /**< Command header */ 1752 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1753 }; 1754 1755 /** 1756 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1757 * 1758 * Reprograms surface parameters to avoid underflow. 1759 */ 1760 struct dmub_cmd_PLAT_54186_wa { 1761 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1762 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1763 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1764 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1765 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1766 struct { 1767 uint32_t hubp_inst : 4; /**< HUBP instance */ 1768 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1769 uint32_t immediate :1; /**< Immediate flip */ 1770 uint32_t vmid : 4; /**< VMID */ 1771 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1772 uint32_t reserved : 21; /**< Reserved */ 1773 } flip_params; /**< Pageflip parameters */ 1774 uint32_t reserved[9]; /**< Reserved bits */ 1775 }; 1776 1777 /** 1778 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1779 */ 1780 struct dmub_rb_cmd_PLAT_54186_wa { 1781 struct dmub_cmd_header header; /**< Command header */ 1782 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1783 }; 1784 1785 /** 1786 * enum dmub_cmd_mall_type - MALL commands 1787 */ 1788 enum dmub_cmd_mall_type { 1789 /** 1790 * Allows display refresh from MALL. 1791 */ 1792 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1793 /** 1794 * Disallows display refresh from MALL. 1795 */ 1796 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1797 /** 1798 * Cursor copy for MALL. 1799 */ 1800 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1801 /** 1802 * Controls DF requests. 1803 */ 1804 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1805 }; 1806 1807 /** 1808 * struct dmub_rb_cmd_mall - MALL command data. 1809 */ 1810 struct dmub_rb_cmd_mall { 1811 struct dmub_cmd_header header; /**< Common command header */ 1812 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1813 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1814 uint32_t tmr_delay; /**< Timer delay */ 1815 uint32_t tmr_scale; /**< Timer scale */ 1816 uint16_t cursor_width; /**< Cursor width in pixels */ 1817 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1818 uint16_t cursor_height; /**< Cursor height in pixels */ 1819 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1820 uint8_t debug_bits; /**< Debug bits */ 1821 1822 uint8_t reserved1; /**< Reserved bits */ 1823 uint8_t reserved2; /**< Reserved bits */ 1824 }; 1825 1826 /** 1827 * enum dmub_cmd_cab_type - CAB command data. 1828 */ 1829 enum dmub_cmd_cab_type { 1830 /** 1831 * No idle optimizations (i.e. no CAB) 1832 */ 1833 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1834 /** 1835 * No DCN requests for memory 1836 */ 1837 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1838 /** 1839 * Fit surfaces in CAB (i.e. CAB enable) 1840 */ 1841 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1842 /** 1843 * Do not fit surfaces in CAB (i.e. no CAB) 1844 */ 1845 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1846 }; 1847 1848 /** 1849 * struct dmub_rb_cmd_cab - CAB command data. 1850 */ 1851 struct dmub_rb_cmd_cab_for_ss { 1852 struct dmub_cmd_header header; 1853 uint8_t cab_alloc_ways; /* total number of ways */ 1854 uint8_t debug_bits; /* debug bits */ 1855 }; 1856 1857 /** 1858 * Enum for indicating which MCLK switch mode per pipe 1859 */ 1860 enum mclk_switch_mode { 1861 NONE = 0, 1862 FPO = 1, 1863 SUBVP = 2, 1864 VBLANK = 3, 1865 }; 1866 1867 /* Per pipe struct which stores the MCLK switch mode 1868 * data to be sent to DMUB. 1869 * Named "v2" for now -- once FPO and SUBVP are fully merged 1870 * the type name can be updated 1871 */ 1872 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1873 union { 1874 struct { 1875 uint32_t pix_clk_100hz; 1876 uint16_t main_vblank_start; 1877 uint16_t main_vblank_end; 1878 uint16_t mall_region_lines; 1879 uint16_t prefetch_lines; 1880 uint16_t prefetch_to_mall_start_lines; 1881 uint16_t processing_delay_lines; 1882 uint16_t htotal; // required to calculate line time for multi-display cases 1883 uint16_t vtotal; 1884 uint8_t main_pipe_index; 1885 uint8_t phantom_pipe_index; 1886 /* Since the microschedule is calculated in terms of OTG lines, 1887 * include any scaling factors to make sure when we get accurate 1888 * conversion when programming MALL_START_LINE (which is in terms 1889 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1890 * is 1/2 (numerator = 1, denominator = 2). 1891 */ 1892 uint8_t scale_factor_numerator; 1893 uint8_t scale_factor_denominator; 1894 uint8_t is_drr; 1895 uint8_t main_split_pipe_index; 1896 uint8_t phantom_split_pipe_index; 1897 } subvp_data; 1898 1899 struct { 1900 uint32_t pix_clk_100hz; 1901 uint16_t vblank_start; 1902 uint16_t vblank_end; 1903 uint16_t vstartup_start; 1904 uint16_t vtotal; 1905 uint16_t htotal; 1906 uint8_t vblank_pipe_index; 1907 uint8_t padding[1]; 1908 struct { 1909 uint8_t drr_in_use; 1910 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1911 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1912 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1913 uint8_t use_ramping; // Use ramping or not 1914 uint8_t drr_vblank_start_margin; 1915 } drr_info; // DRR considered as part of SubVP + VBLANK case 1916 } vblank_data; 1917 } pipe_config; 1918 1919 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1920 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1921 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1922 */ 1923 uint8_t mode; // enum mclk_switch_mode 1924 }; 1925 1926 /** 1927 * Config data for Sub-VP and FPO 1928 * Named "v2" for now -- once FPO and SUBVP are fully merged 1929 * the type name can be updated 1930 */ 1931 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1932 uint16_t watermark_a_cache; 1933 uint8_t vertical_int_margin_us; 1934 uint8_t pstate_allow_width_us; 1935 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1936 }; 1937 1938 /** 1939 * DMUB rb command definition for Sub-VP and FPO 1940 * Named "v2" for now -- once FPO and SUBVP are fully merged 1941 * the type name can be updated 1942 */ 1943 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1944 struct dmub_cmd_header header; 1945 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1946 }; 1947 1948 struct dmub_flip_addr_info { 1949 uint32_t surf_addr_lo; 1950 uint32_t surf_addr_c_lo; 1951 uint32_t meta_addr_lo; 1952 uint32_t meta_addr_c_lo; 1953 uint16_t surf_addr_hi; 1954 uint16_t surf_addr_c_hi; 1955 uint16_t meta_addr_hi; 1956 uint16_t meta_addr_c_hi; 1957 }; 1958 1959 struct dmub_fams2_flip_info { 1960 union { 1961 struct { 1962 uint8_t is_immediate: 1; 1963 } bits; 1964 uint8_t all; 1965 } config; 1966 uint8_t otg_inst; 1967 uint8_t pipe_mask; 1968 uint8_t pad; 1969 struct dmub_flip_addr_info addr_info; 1970 }; 1971 1972 struct dmub_rb_cmd_fams2_flip { 1973 struct dmub_cmd_header header; 1974 struct dmub_fams2_flip_info flip_info; 1975 }; 1976 1977 struct dmub_cmd_lsdma_data { 1978 union { 1979 struct lsdma_init_data { 1980 union dmub_addr gpu_addr_base; 1981 uint32_t ring_size; 1982 } init_data; 1983 struct lsdma_tiled_copy_data { 1984 uint32_t src_addr_lo; 1985 uint32_t src_addr_hi; 1986 uint32_t dst_addr_lo; 1987 uint32_t dst_addr_hi; 1988 1989 uint32_t src_x : 16; 1990 uint32_t src_y : 16; 1991 1992 uint32_t src_width : 16; 1993 uint32_t src_height : 16; 1994 1995 uint32_t dst_x : 16; 1996 uint32_t dst_y : 16; 1997 1998 uint32_t dst_width : 16; 1999 uint32_t dst_height : 16; 2000 2001 uint32_t rect_x : 16; 2002 uint32_t rect_y : 16; 2003 2004 uint32_t src_swizzle_mode : 5; 2005 uint32_t src_mip_max : 5; 2006 uint32_t src_mip_id : 5; 2007 uint32_t dst_mip_max : 5; 2008 uint32_t dst_swizzle_mode : 5; 2009 uint32_t dst_mip_id : 5; 2010 uint32_t tmz : 1; 2011 uint32_t dcc : 1; 2012 2013 uint32_t data_format : 6; 2014 uint32_t padding1 : 4; 2015 uint32_t dst_element_size : 3; 2016 uint32_t num_type : 3; 2017 uint32_t src_element_size : 3; 2018 uint32_t write_compress : 2; 2019 uint32_t cache_policy_dst : 2; 2020 uint32_t cache_policy_src : 2; 2021 uint32_t read_compress : 2; 2022 uint32_t src_dim : 2; 2023 uint32_t dst_dim : 2; 2024 uint32_t max_uncom : 1; 2025 2026 uint32_t max_com : 2; 2027 uint32_t padding : 30; 2028 } tiled_copy_data; 2029 struct lsdma_linear_copy_data { 2030 uint32_t count : 30; 2031 uint32_t cache_policy_dst : 2; 2032 2033 uint32_t tmz : 1; 2034 uint32_t cache_policy_src : 2; 2035 uint32_t padding : 29; 2036 2037 uint32_t src_lo; 2038 uint32_t src_hi; 2039 uint32_t dst_lo; 2040 uint32_t dst_hi; 2041 } linear_copy_data; 2042 struct lsdma_reg_write_data { 2043 uint32_t reg_addr; 2044 uint32_t reg_data; 2045 } reg_write_data; 2046 struct lsdma_pio_copy_data { 2047 union { 2048 struct { 2049 uint32_t byte_count : 26; 2050 uint32_t src_loc : 1; 2051 uint32_t dst_loc : 1; 2052 uint32_t src_addr_inc : 1; 2053 uint32_t dst_addr_inc : 1; 2054 uint32_t overlap_disable : 1; 2055 uint32_t constant_fill : 1; 2056 } fields; 2057 uint32_t raw; 2058 } packet; 2059 uint32_t src_lo; 2060 uint32_t src_hi; 2061 uint32_t dst_lo; 2062 uint32_t dst_hi; 2063 } pio_copy_data; 2064 struct lsdma_pio_constfill_data { 2065 union { 2066 struct { 2067 uint32_t byte_count : 26; 2068 uint32_t src_loc : 1; 2069 uint32_t dst_loc : 1; 2070 uint32_t src_addr_inc : 1; 2071 uint32_t dst_addr_inc : 1; 2072 uint32_t overlap_disable : 1; 2073 uint32_t constant_fill : 1; 2074 } fields; 2075 uint32_t raw; 2076 } packet; 2077 uint32_t dst_lo; 2078 uint32_t dst_hi; 2079 uint32_t data; 2080 } pio_constfill_data; 2081 2082 uint32_t all[14]; 2083 } u; 2084 2085 }; 2086 2087 struct dmub_rb_cmd_lsdma { 2088 struct dmub_cmd_header header; 2089 struct dmub_cmd_lsdma_data lsdma_data; 2090 }; 2091 2092 struct dmub_optc_state_v2 { 2093 uint32_t v_total_min; 2094 uint32_t v_total_max; 2095 uint32_t v_total_mid; 2096 uint32_t v_total_mid_frame_num; 2097 uint8_t program_manual_trigger; 2098 uint8_t tg_inst; 2099 uint8_t pad[2]; 2100 }; 2101 2102 struct dmub_optc_position { 2103 uint32_t vpos; 2104 uint32_t hpos; 2105 uint32_t frame; 2106 }; 2107 2108 struct dmub_rb_cmd_fams2_drr_update { 2109 struct dmub_cmd_header header; 2110 struct dmub_optc_state_v2 dmub_optc_state_req; 2111 }; 2112 2113 /* HW and FW global configuration data for FAMS2 */ 2114 /* FAMS2 types and structs */ 2115 enum fams2_stream_type { 2116 FAMS2_STREAM_TYPE_NONE = 0, 2117 FAMS2_STREAM_TYPE_VBLANK = 1, 2118 FAMS2_STREAM_TYPE_VACTIVE = 2, 2119 FAMS2_STREAM_TYPE_DRR = 3, 2120 FAMS2_STREAM_TYPE_SUBVP = 4, 2121 }; 2122 2123 struct dmub_rect16 { 2124 /** 2125 * Dirty rect x offset. 2126 */ 2127 uint16_t x; 2128 2129 /** 2130 * Dirty rect y offset. 2131 */ 2132 uint16_t y; 2133 2134 /** 2135 * Dirty rect width. 2136 */ 2137 uint16_t width; 2138 2139 /** 2140 * Dirty rect height. 2141 */ 2142 uint16_t height; 2143 }; 2144 2145 /* static stream state */ 2146 struct dmub_fams2_legacy_stream_static_state { 2147 uint8_t vactive_det_fill_delay_otg_vlines; 2148 uint8_t programming_delay_otg_vlines; 2149 }; //v0 2150 2151 struct dmub_fams2_subvp_stream_static_state { 2152 uint16_t vratio_numerator; 2153 uint16_t vratio_denominator; 2154 uint16_t phantom_vtotal; 2155 uint16_t phantom_vactive; 2156 union { 2157 struct { 2158 uint8_t is_multi_planar : 1; 2159 uint8_t is_yuv420 : 1; 2160 } bits; 2161 uint8_t all; 2162 } config; 2163 uint8_t programming_delay_otg_vlines; 2164 uint8_t prefetch_to_mall_otg_vlines; 2165 uint8_t phantom_otg_inst; 2166 uint8_t phantom_pipe_mask; 2167 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2168 }; //v0 2169 2170 struct dmub_fams2_drr_stream_static_state { 2171 uint16_t nom_stretched_vtotal; 2172 uint8_t programming_delay_otg_vlines; 2173 uint8_t only_stretch_if_required; 2174 uint8_t pad[2]; 2175 }; //v0 2176 2177 struct dmub_fams2_cmd_legacy_stream_static_state { 2178 uint16_t vactive_det_fill_delay_otg_vlines; 2179 uint16_t programming_delay_otg_vlines; 2180 }; //v1 2181 2182 struct dmub_fams2_cmd_subvp_stream_static_state { 2183 uint16_t vratio_numerator; 2184 uint16_t vratio_denominator; 2185 uint16_t phantom_vtotal; 2186 uint16_t phantom_vactive; 2187 uint16_t programming_delay_otg_vlines; 2188 uint16_t prefetch_to_mall_otg_vlines; 2189 union { 2190 struct { 2191 uint8_t is_multi_planar : 1; 2192 uint8_t is_yuv420 : 1; 2193 } bits; 2194 uint8_t all; 2195 } config; 2196 uint8_t phantom_otg_inst; 2197 uint8_t phantom_pipe_mask; 2198 uint8_t pad0; 2199 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2200 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2201 }; //v1 2202 2203 struct dmub_fams2_cmd_drr_stream_static_state { 2204 uint16_t nom_stretched_vtotal; 2205 uint16_t programming_delay_otg_vlines; 2206 uint8_t only_stretch_if_required; 2207 uint8_t pad[3]; 2208 }; //v1 2209 2210 union dmub_fams2_stream_static_sub_state { 2211 struct dmub_fams2_legacy_stream_static_state legacy; 2212 struct dmub_fams2_subvp_stream_static_state subvp; 2213 struct dmub_fams2_drr_stream_static_state drr; 2214 }; //v0 2215 2216 union dmub_fams2_cmd_stream_static_sub_state { 2217 COMMON_STREAM_STATIC_SUB_STATE 2218 }; //v1 2219 2220 union dmub_fams2_stream_static_sub_state_v2 { 2221 COMMON_STREAM_STATIC_SUB_STATE 2222 }; //v2 2223 2224 struct dmub_fams2_stream_static_state { 2225 enum fams2_stream_type type; 2226 uint32_t otg_vline_time_ns; 2227 uint32_t otg_vline_time_ticks; 2228 uint16_t htotal; 2229 uint16_t vtotal; // nominal vtotal 2230 uint16_t vblank_start; 2231 uint16_t vblank_end; 2232 uint16_t max_vtotal; 2233 uint16_t allow_start_otg_vline; 2234 uint16_t allow_end_otg_vline; 2235 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2236 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2237 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2238 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2239 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2240 union { 2241 struct { 2242 uint8_t is_drr: 1; // stream is DRR enabled 2243 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2244 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2245 } bits; 2246 uint8_t all; 2247 } config; 2248 uint8_t otg_inst; 2249 uint8_t pipe_mask; // pipe mask for the whole config 2250 uint8_t num_planes; 2251 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2252 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2253 union dmub_fams2_stream_static_sub_state sub_state; 2254 }; //v0 2255 2256 struct dmub_fams2_cmd_stream_static_base_state { 2257 enum fams2_stream_type type; 2258 uint32_t otg_vline_time_ns; 2259 uint32_t otg_vline_time_ticks; 2260 uint16_t htotal; 2261 uint16_t vtotal; // nominal vtotal 2262 uint16_t vblank_start; 2263 uint16_t vblank_end; 2264 uint16_t max_vtotal; 2265 uint16_t allow_start_otg_vline; 2266 uint16_t allow_end_otg_vline; 2267 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2268 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2269 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2270 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2271 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2272 union { 2273 struct { 2274 uint8_t is_drr : 1; // stream is DRR enabled 2275 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2276 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2277 } bits; 2278 uint8_t all; 2279 } config; 2280 uint8_t otg_inst; 2281 uint8_t pipe_mask; // pipe mask for the whole config 2282 uint8_t num_planes; 2283 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2284 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2285 }; //v1 2286 2287 struct dmub_fams2_stream_static_state_v1 { 2288 struct dmub_fams2_cmd_stream_static_base_state base; 2289 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2290 }; //v1 2291 2292 /** 2293 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2294 * p-state request to allow latency 2295 */ 2296 enum dmub_fams2_allow_delay_check_mode { 2297 /* No check for request to allow delay */ 2298 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2299 /* Check for request to allow delay */ 2300 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2301 /* Check for prepare to allow delay */ 2302 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2303 }; 2304 2305 union dmub_fams2_global_feature_config { 2306 struct { 2307 uint32_t enable: 1; 2308 uint32_t enable_ppt_check: 1; 2309 uint32_t enable_stall_recovery: 1; 2310 uint32_t enable_debug: 1; 2311 uint32_t enable_offload_flip: 1; 2312 uint32_t enable_visual_confirm: 1; 2313 uint32_t allow_delay_check_mode: 2; 2314 uint32_t reserved: 24; 2315 } bits; 2316 uint32_t all; 2317 }; 2318 2319 struct dmub_cmd_fams2_global_config { 2320 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2321 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2322 uint32_t num_streams; 2323 union dmub_fams2_global_feature_config features; 2324 uint32_t recovery_timeout_us; 2325 uint32_t hwfq_flip_programming_delay_us; 2326 }; 2327 2328 union dmub_cmd_fams2_config { 2329 struct dmub_cmd_fams2_global_config global; 2330 struct dmub_fams2_stream_static_state stream; //v0 2331 union { 2332 struct dmub_fams2_cmd_stream_static_base_state base; 2333 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2334 } stream_v1; //v1 2335 }; 2336 2337 struct dmub_fams2_config_v2 { 2338 struct dmub_cmd_fams2_global_config global; 2339 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2340 }; 2341 2342 /** 2343 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2344 */ 2345 struct dmub_rb_cmd_fams2 { 2346 struct dmub_cmd_header header; 2347 union dmub_cmd_fams2_config config; 2348 }; 2349 2350 /** 2351 * Indirect buffer descriptor 2352 */ 2353 struct dmub_ib_data { 2354 union dmub_addr src; // location of indirect buffer in memory 2355 uint16_t size; // indirect buffer size in bytes 2356 }; 2357 2358 /** 2359 * DMUB rb command definition for commands passed over indirect buffer 2360 */ 2361 struct dmub_rb_cmd_ib { 2362 struct dmub_cmd_header header; 2363 struct dmub_ib_data ib_data; 2364 }; 2365 2366 /** 2367 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2368 */ 2369 enum dmub_cmd_idle_opt_type { 2370 /** 2371 * DCN hardware restore. 2372 */ 2373 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2374 2375 /** 2376 * DCN hardware save. 2377 */ 2378 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2379 2380 /** 2381 * DCN hardware notify idle. 2382 */ 2383 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2384 2385 /** 2386 * DCN hardware notify power state. 2387 */ 2388 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2389 2390 /** 2391 * DCN notify to release HW. 2392 */ 2393 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2394 }; 2395 2396 /** 2397 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2398 */ 2399 struct dmub_rb_cmd_idle_opt_dcn_restore { 2400 struct dmub_cmd_header header; /**< header */ 2401 }; 2402 2403 /** 2404 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2405 */ 2406 struct dmub_dcn_notify_idle_cntl_data { 2407 uint8_t driver_idle; 2408 uint8_t skip_otg_disable; 2409 uint8_t reserved[58]; 2410 }; 2411 2412 /** 2413 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2414 */ 2415 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2416 struct dmub_cmd_header header; /**< header */ 2417 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2418 }; 2419 2420 /** 2421 * enum dmub_idle_opt_dc_power_state - DC power states. 2422 */ 2423 enum dmub_idle_opt_dc_power_state { 2424 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2425 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2426 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2427 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2428 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2429 }; 2430 2431 /** 2432 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2433 */ 2434 struct dmub_idle_opt_set_dc_power_state_data { 2435 uint8_t power_state; /**< power state */ 2436 uint8_t pad[3]; /**< padding */ 2437 }; 2438 2439 /** 2440 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2441 */ 2442 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2443 struct dmub_cmd_header header; /**< header */ 2444 struct dmub_idle_opt_set_dc_power_state_data data; 2445 }; 2446 2447 /** 2448 * struct dmub_clocks - Clock update notification. 2449 */ 2450 struct dmub_clocks { 2451 uint32_t dispclk_khz; /**< dispclk kHz */ 2452 uint32_t dppclk_khz; /**< dppclk kHz */ 2453 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2454 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2455 }; 2456 2457 /** 2458 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2459 */ 2460 enum dmub_cmd_clk_mgr_type { 2461 /** 2462 * Notify DMCUB of clock update. 2463 */ 2464 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2465 }; 2466 2467 /** 2468 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2469 */ 2470 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2471 struct dmub_cmd_header header; /**< header */ 2472 struct dmub_clocks clocks; /**< clock data */ 2473 }; 2474 2475 /** 2476 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2477 */ 2478 struct dmub_cmd_digx_encoder_control_data { 2479 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2480 }; 2481 2482 /** 2483 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2484 */ 2485 struct dmub_rb_cmd_digx_encoder_control { 2486 struct dmub_cmd_header header; /**< header */ 2487 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2488 }; 2489 2490 /** 2491 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2492 */ 2493 struct dmub_cmd_set_pixel_clock_data { 2494 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2495 }; 2496 2497 /** 2498 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2499 */ 2500 struct dmub_rb_cmd_set_pixel_clock { 2501 struct dmub_cmd_header header; /**< header */ 2502 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2503 }; 2504 2505 /** 2506 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2507 */ 2508 struct dmub_cmd_enable_disp_power_gating_data { 2509 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2510 }; 2511 2512 /** 2513 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2514 */ 2515 struct dmub_rb_cmd_enable_disp_power_gating { 2516 struct dmub_cmd_header header; /**< header */ 2517 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2518 }; 2519 2520 /** 2521 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2522 */ 2523 struct dmub_dig_transmitter_control_data_v1_7 { 2524 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2525 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2526 union { 2527 uint8_t digmode; /**< enum atom_encode_mode_def */ 2528 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2529 } mode_laneset; 2530 uint8_t lanenum; /**< Number of lanes */ 2531 union { 2532 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2533 } symclk_units; 2534 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2535 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2536 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2537 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2538 uint8_t reserved1; /**< For future use */ 2539 uint8_t skip_phy_ssc_reduction; 2540 uint8_t reserved2[2]; /**< For future use */ 2541 uint32_t reserved3[11]; /**< For future use */ 2542 }; 2543 2544 /** 2545 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2546 */ 2547 union dmub_cmd_dig1_transmitter_control_data { 2548 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2549 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2550 }; 2551 2552 /** 2553 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2554 */ 2555 struct dmub_rb_cmd_dig1_transmitter_control { 2556 struct dmub_cmd_header header; /**< header */ 2557 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2558 }; 2559 2560 /** 2561 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2562 */ 2563 struct dmub_rb_cmd_domain_control_data { 2564 uint8_t inst : 6; /**< DOMAIN instance to control */ 2565 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2566 uint8_t reserved[3]; /**< Reserved for future use */ 2567 }; 2568 2569 /** 2570 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2571 */ 2572 struct dmub_rb_cmd_domain_control { 2573 struct dmub_cmd_header header; /**< header */ 2574 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2575 }; 2576 2577 /** 2578 * DPIA tunnel command parameters. 2579 */ 2580 struct dmub_cmd_dig_dpia_control_data { 2581 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2582 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2583 union { 2584 uint8_t digmode; /** enum atom_encode_mode_def */ 2585 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2586 } mode_laneset; 2587 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2588 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2589 uint8_t hpdsel; /** =0: HPD is not assigned */ 2590 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2591 uint8_t dpia_id; /** Index of DPIA */ 2592 uint8_t fec_rdy : 1; 2593 uint8_t reserved : 7; 2594 uint32_t reserved1; 2595 }; 2596 2597 /** 2598 * DMUB command for DPIA tunnel control. 2599 */ 2600 struct dmub_rb_cmd_dig1_dpia_control { 2601 struct dmub_cmd_header header; 2602 struct dmub_cmd_dig_dpia_control_data dpia_control; 2603 }; 2604 2605 /** 2606 * SET_CONFIG Command Payload (deprecated) 2607 */ 2608 struct set_config_cmd_payload { 2609 uint8_t msg_type; /* set config message type */ 2610 uint8_t msg_data; /* set config message data */ 2611 }; 2612 2613 /** 2614 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2615 */ 2616 struct dmub_cmd_set_config_control_data { 2617 struct set_config_cmd_payload cmd_pkt; 2618 uint8_t instance; /* DPIA instance */ 2619 uint8_t immed_status; /* Immediate status returned in case of error */ 2620 }; 2621 2622 /** 2623 * SET_CONFIG Request Command Payload 2624 */ 2625 struct set_config_request_cmd_payload { 2626 uint8_t instance; /* DPIA instance */ 2627 uint8_t immed_status; /* Immediate status returned in case of error */ 2628 uint8_t msg_type; /* set config message type */ 2629 uint8_t reserved; 2630 uint32_t msg_data; /* set config message data */ 2631 }; 2632 2633 /** 2634 * DMUB command structure for SET_CONFIG command. 2635 */ 2636 struct dmub_rb_cmd_set_config_access { 2637 struct dmub_cmd_header header; /* header */ 2638 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2639 }; 2640 2641 /** 2642 * DMUB command structure for SET_CONFIG request command. 2643 */ 2644 struct dmub_rb_cmd_set_config_request { 2645 struct dmub_cmd_header header; /* header */ 2646 struct set_config_request_cmd_payload payload; /* set config request payload */ 2647 }; 2648 2649 /** 2650 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2651 */ 2652 struct dmub_cmd_mst_alloc_slots_control_data { 2653 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2654 uint8_t instance; /* DPIA instance */ 2655 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2656 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2657 }; 2658 2659 /** 2660 * DMUB command structure for SET_ command. 2661 */ 2662 struct dmub_rb_cmd_set_mst_alloc_slots { 2663 struct dmub_cmd_header header; /* header */ 2664 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2665 }; 2666 2667 /** 2668 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2669 */ 2670 struct dmub_cmd_tps_notification_data { 2671 uint8_t instance; /* DPIA instance */ 2672 uint8_t tps; /* requested training pattern */ 2673 uint8_t reserved1; 2674 uint8_t reserved2; 2675 }; 2676 2677 /** 2678 * DMUB command structure for SET_TPS_NOTIFICATION command. 2679 */ 2680 struct dmub_rb_cmd_set_tps_notification { 2681 struct dmub_cmd_header header; /* header */ 2682 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2683 }; 2684 2685 /** 2686 * DMUB command structure for DPIA HPD int enable control. 2687 */ 2688 struct dmub_rb_cmd_dpia_hpd_int_enable { 2689 struct dmub_cmd_header header; /* header */ 2690 uint32_t enable; /* dpia hpd interrupt enable */ 2691 }; 2692 2693 /** 2694 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2695 */ 2696 struct dmub_rb_cmd_dpphy_init { 2697 struct dmub_cmd_header header; /**< header */ 2698 uint8_t reserved[60]; /**< reserved bits */ 2699 }; 2700 2701 /** 2702 * enum dp_aux_request_action - DP AUX request command listing. 2703 * 2704 * 4 AUX request command bits are shifted to high nibble. 2705 */ 2706 enum dp_aux_request_action { 2707 /** I2C-over-AUX write request */ 2708 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2709 /** I2C-over-AUX read request */ 2710 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2711 /** I2C-over-AUX write status request */ 2712 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2713 /** I2C-over-AUX write request with MOT=1 */ 2714 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2715 /** I2C-over-AUX read request with MOT=1 */ 2716 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2717 /** I2C-over-AUX write status request with MOT=1 */ 2718 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2719 /** Native AUX write request */ 2720 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2721 /** Native AUX read request */ 2722 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2723 }; 2724 2725 /** 2726 * enum aux_return_code_type - DP AUX process return code listing. 2727 */ 2728 enum aux_return_code_type { 2729 /** AUX process succeeded */ 2730 AUX_RET_SUCCESS = 0, 2731 /** AUX process failed with unknown reason */ 2732 AUX_RET_ERROR_UNKNOWN, 2733 /** AUX process completed with invalid reply */ 2734 AUX_RET_ERROR_INVALID_REPLY, 2735 /** AUX process timed out */ 2736 AUX_RET_ERROR_TIMEOUT, 2737 /** HPD was low during AUX process */ 2738 AUX_RET_ERROR_HPD_DISCON, 2739 /** Failed to acquire AUX engine */ 2740 AUX_RET_ERROR_ENGINE_ACQUIRE, 2741 /** AUX request not supported */ 2742 AUX_RET_ERROR_INVALID_OPERATION, 2743 /** AUX process not available */ 2744 AUX_RET_ERROR_PROTOCOL_ERROR, 2745 }; 2746 2747 /** 2748 * enum aux_channel_type - DP AUX channel type listing. 2749 */ 2750 enum aux_channel_type { 2751 /** AUX thru Legacy DP AUX */ 2752 AUX_CHANNEL_LEGACY_DDC, 2753 /** AUX thru DPIA DP tunneling */ 2754 AUX_CHANNEL_DPIA 2755 }; 2756 2757 /** 2758 * struct aux_transaction_parameters - DP AUX request transaction data 2759 */ 2760 struct aux_transaction_parameters { 2761 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2762 uint8_t action; /**< enum dp_aux_request_action */ 2763 uint8_t length; /**< DP AUX request data length */ 2764 uint8_t reserved; /**< For future use */ 2765 uint32_t address; /**< DP AUX address */ 2766 uint8_t data[16]; /**< DP AUX write data */ 2767 }; 2768 2769 /** 2770 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2771 */ 2772 struct dmub_cmd_dp_aux_control_data { 2773 uint8_t instance; /**< AUX instance or DPIA instance */ 2774 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2775 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2776 uint8_t reserved0; /**< For future use */ 2777 uint16_t timeout; /**< timeout time in us */ 2778 uint16_t reserved1; /**< For future use */ 2779 enum aux_channel_type type; /**< enum aux_channel_type */ 2780 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2781 }; 2782 2783 /** 2784 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2785 */ 2786 struct dmub_rb_cmd_dp_aux_access { 2787 /** 2788 * Command header. 2789 */ 2790 struct dmub_cmd_header header; 2791 /** 2792 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2793 */ 2794 struct dmub_cmd_dp_aux_control_data aux_control; 2795 }; 2796 2797 /** 2798 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2799 */ 2800 struct dmub_rb_cmd_outbox1_enable { 2801 /** 2802 * Command header. 2803 */ 2804 struct dmub_cmd_header header; 2805 /** 2806 * enable: 0x0 -> disable outbox1 notification (default value) 2807 * 0x1 -> enable outbox1 notification 2808 */ 2809 uint32_t enable; 2810 }; 2811 2812 /* DP AUX Reply command - OutBox Cmd */ 2813 /** 2814 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2815 */ 2816 struct aux_reply_data { 2817 /** 2818 * Aux cmd 2819 */ 2820 uint8_t command; 2821 /** 2822 * Aux reply data length (max: 16 bytes) 2823 */ 2824 uint8_t length; 2825 /** 2826 * Alignment only 2827 */ 2828 uint8_t pad[2]; 2829 /** 2830 * Aux reply data 2831 */ 2832 uint8_t data[16]; 2833 }; 2834 2835 /** 2836 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2837 */ 2838 struct aux_reply_control_data { 2839 /** 2840 * Reserved for future use 2841 */ 2842 uint32_t handle; 2843 /** 2844 * Aux Instance 2845 */ 2846 uint8_t instance; 2847 /** 2848 * Aux transaction result: definition in enum aux_return_code_type 2849 */ 2850 uint8_t result; 2851 /** 2852 * Alignment only 2853 */ 2854 uint16_t pad; 2855 }; 2856 2857 /** 2858 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2859 */ 2860 struct dmub_rb_cmd_dp_aux_reply { 2861 /** 2862 * Command header. 2863 */ 2864 struct dmub_cmd_header header; 2865 /** 2866 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2867 */ 2868 struct aux_reply_control_data control; 2869 /** 2870 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2871 */ 2872 struct aux_reply_data reply_data; 2873 }; 2874 2875 /* DP HPD Notify command - OutBox Cmd */ 2876 /** 2877 * DP HPD Type 2878 */ 2879 enum dp_hpd_type { 2880 /** 2881 * Normal DP HPD 2882 */ 2883 DP_HPD = 0, 2884 /** 2885 * DP HPD short pulse 2886 */ 2887 DP_IRQ = 1, 2888 /** 2889 * Failure to acquire DP HPD state 2890 */ 2891 DP_NONE_HPD = 2 2892 }; 2893 2894 /** 2895 * DP HPD Status 2896 */ 2897 enum dp_hpd_status { 2898 /** 2899 * DP_HPD status low 2900 */ 2901 DP_HPD_UNPLUG = 0, 2902 /** 2903 * DP_HPD status high 2904 */ 2905 DP_HPD_PLUG 2906 }; 2907 2908 /** 2909 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2910 */ 2911 struct dp_hpd_data { 2912 /** 2913 * DP HPD instance 2914 */ 2915 uint8_t instance; 2916 /** 2917 * HPD type 2918 */ 2919 uint8_t hpd_type; 2920 /** 2921 * HPD status: only for type: DP_HPD to indicate status 2922 */ 2923 uint8_t hpd_status; 2924 /** 2925 * Alignment only 2926 */ 2927 uint8_t pad; 2928 }; 2929 2930 /** 2931 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2932 */ 2933 struct dmub_rb_cmd_dp_hpd_notify { 2934 /** 2935 * Command header. 2936 */ 2937 struct dmub_cmd_header header; 2938 /** 2939 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2940 */ 2941 struct dp_hpd_data hpd_data; 2942 }; 2943 2944 /** 2945 * Definition of a SET_CONFIG reply from DPOA. 2946 */ 2947 enum set_config_status { 2948 SET_CONFIG_PENDING = 0, 2949 SET_CONFIG_ACK_RECEIVED, 2950 SET_CONFIG_RX_TIMEOUT, 2951 SET_CONFIG_UNKNOWN_ERROR, 2952 }; 2953 2954 /** 2955 * Definition of a set_config reply 2956 */ 2957 struct set_config_reply_control_data { 2958 uint8_t instance; /* DPIA Instance */ 2959 uint8_t status; /* Set Config reply */ 2960 uint16_t pad; /* Alignment */ 2961 }; 2962 2963 /** 2964 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2965 */ 2966 struct dmub_rb_cmd_dp_set_config_reply { 2967 struct dmub_cmd_header header; 2968 struct set_config_reply_control_data set_config_reply_control; 2969 }; 2970 2971 /** 2972 * Definition of a DPIA notification header 2973 */ 2974 struct dpia_notification_header { 2975 uint8_t instance; /**< DPIA Instance */ 2976 uint8_t reserved[3]; 2977 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2978 }; 2979 2980 /** 2981 * Definition of the common data struct of DPIA notification 2982 */ 2983 struct dpia_notification_common { 2984 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2985 - sizeof(struct dpia_notification_header)]; 2986 }; 2987 2988 /** 2989 * Definition of a DPIA notification data 2990 */ 2991 struct dpia_bw_allocation_notify_data { 2992 union { 2993 struct { 2994 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2995 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2996 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2997 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2998 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2999 uint16_t reserved: 11; /**< Reserved */ 3000 } bits; 3001 3002 uint16_t flags; 3003 }; 3004 3005 uint8_t cm_id; /**< CM ID */ 3006 uint8_t group_id; /**< Group ID */ 3007 uint8_t granularity; /**< BW Allocation Granularity */ 3008 uint8_t estimated_bw; /**< Estimated_BW */ 3009 uint8_t allocated_bw; /**< Allocated_BW */ 3010 uint8_t reserved; 3011 }; 3012 3013 /** 3014 * union dpia_notify_data_type - DPIA Notification in Outbox command 3015 */ 3016 union dpia_notification_data { 3017 /** 3018 * DPIA Notification for common data struct 3019 */ 3020 struct dpia_notification_common common_data; 3021 3022 /** 3023 * DPIA Notification for DP BW Allocation support 3024 */ 3025 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3026 }; 3027 3028 /** 3029 * Definition of a DPIA notification payload 3030 */ 3031 struct dpia_notification_payload { 3032 struct dpia_notification_header header; 3033 union dpia_notification_data data; /**< DPIA notification payload data */ 3034 }; 3035 3036 /** 3037 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3038 */ 3039 struct dmub_rb_cmd_dpia_notification { 3040 struct dmub_cmd_header header; /**< DPIA notification header */ 3041 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3042 }; 3043 3044 /** 3045 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3046 */ 3047 struct dmub_cmd_hpd_state_query_data { 3048 uint8_t instance; /**< HPD instance or DPIA instance */ 3049 uint8_t result; /**< For returning HPD state */ 3050 uint16_t pad; /** < Alignment */ 3051 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3052 enum aux_return_code_type status; /**< for returning the status of command */ 3053 }; 3054 3055 /** 3056 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3057 */ 3058 struct dmub_rb_cmd_query_hpd_state { 3059 /** 3060 * Command header. 3061 */ 3062 struct dmub_cmd_header header; 3063 /** 3064 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3065 */ 3066 struct dmub_cmd_hpd_state_query_data data; 3067 }; 3068 3069 /** 3070 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3071 */ 3072 struct dmub_rb_cmd_hpd_sense_notify_data { 3073 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3074 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3075 }; 3076 3077 /** 3078 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3079 */ 3080 struct dmub_rb_cmd_hpd_sense_notify { 3081 struct dmub_cmd_header header; /**< header */ 3082 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3083 }; 3084 3085 /* 3086 * Command IDs should be treated as stable ABI. 3087 * Do not reuse or modify IDs. 3088 */ 3089 3090 /** 3091 * PSR command sub-types. 3092 */ 3093 enum dmub_cmd_psr_type { 3094 /** 3095 * Set PSR version support. 3096 */ 3097 DMUB_CMD__PSR_SET_VERSION = 0, 3098 /** 3099 * Copy driver-calculated parameters to PSR state. 3100 */ 3101 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3102 /** 3103 * Enable PSR. 3104 */ 3105 DMUB_CMD__PSR_ENABLE = 2, 3106 3107 /** 3108 * Disable PSR. 3109 */ 3110 DMUB_CMD__PSR_DISABLE = 3, 3111 3112 /** 3113 * Set PSR level. 3114 * PSR level is a 16-bit value dicated by driver that 3115 * will enable/disable different functionality. 3116 */ 3117 DMUB_CMD__PSR_SET_LEVEL = 4, 3118 3119 /** 3120 * Forces PSR enabled until an explicit PSR disable call. 3121 */ 3122 DMUB_CMD__PSR_FORCE_STATIC = 5, 3123 /** 3124 * Set vtotal in psr active for FreeSync PSR. 3125 */ 3126 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3127 /** 3128 * Set PSR power option 3129 */ 3130 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3131 }; 3132 3133 /** 3134 * Different PSR residency modes. 3135 * Different modes change the definition of PSR residency. 3136 */ 3137 enum psr_residency_mode { 3138 PSR_RESIDENCY_MODE_PHY = 0, 3139 PSR_RESIDENCY_MODE_ALPM, 3140 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3141 /* Do not add below. */ 3142 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3143 }; 3144 3145 enum dmub_cmd_fams_type { 3146 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3147 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3148 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3149 /** 3150 * For SubVP set manual trigger in FW because it 3151 * triggers DRR_UPDATE_PENDING which SubVP relies 3152 * on (for any SubVP cases that use a DRR display) 3153 */ 3154 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3155 DMUB_CMD__FAMS2_CONFIG = 4, 3156 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3157 DMUB_CMD__FAMS2_FLIP = 6, 3158 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3159 }; 3160 3161 /** 3162 * PSR versions. 3163 */ 3164 enum psr_version { 3165 /** 3166 * PSR version 1. 3167 */ 3168 PSR_VERSION_1 = 0, 3169 /** 3170 * Freesync PSR SU. 3171 */ 3172 PSR_VERSION_SU_1 = 1, 3173 /** 3174 * PSR not supported. 3175 */ 3176 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3177 }; 3178 3179 /** 3180 * PHY Link rate for DP. 3181 */ 3182 enum phy_link_rate { 3183 /** 3184 * not supported. 3185 */ 3186 PHY_RATE_UNKNOWN = 0, 3187 /** 3188 * Rate_1 (RBR) - 1.62 Gbps/Lane 3189 */ 3190 PHY_RATE_162 = 1, 3191 /** 3192 * Rate_2 - 2.16 Gbps/Lane 3193 */ 3194 PHY_RATE_216 = 2, 3195 /** 3196 * Rate_3 - 2.43 Gbps/Lane 3197 */ 3198 PHY_RATE_243 = 3, 3199 /** 3200 * Rate_4 (HBR) - 2.70 Gbps/Lane 3201 */ 3202 PHY_RATE_270 = 4, 3203 /** 3204 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3205 */ 3206 PHY_RATE_324 = 5, 3207 /** 3208 * Rate_6 - 4.32 Gbps/Lane 3209 */ 3210 PHY_RATE_432 = 6, 3211 /** 3212 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3213 */ 3214 PHY_RATE_540 = 7, 3215 /** 3216 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3217 */ 3218 PHY_RATE_810 = 8, 3219 /** 3220 * UHBR10 - 10.0 Gbps/Lane 3221 */ 3222 PHY_RATE_1000 = 9, 3223 /** 3224 * UHBR13.5 - 13.5 Gbps/Lane 3225 */ 3226 PHY_RATE_1350 = 10, 3227 /** 3228 * UHBR10 - 20.0 Gbps/Lane 3229 */ 3230 PHY_RATE_2000 = 11, 3231 3232 PHY_RATE_675 = 12, 3233 /** 3234 * Rate 12 - 6.75 Gbps/Lane 3235 */ 3236 }; 3237 3238 /** 3239 * enum dmub_phy_fsm_state - PHY FSM states. 3240 * PHY FSM state to transit to during PSR enable/disable. 3241 */ 3242 enum dmub_phy_fsm_state { 3243 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3244 DMUB_PHY_FSM_RESET, 3245 DMUB_PHY_FSM_RESET_RELEASED, 3246 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3247 DMUB_PHY_FSM_INITIALIZED, 3248 DMUB_PHY_FSM_CALIBRATED, 3249 DMUB_PHY_FSM_CALIBRATED_LP, 3250 DMUB_PHY_FSM_CALIBRATED_PG, 3251 DMUB_PHY_FSM_POWER_DOWN, 3252 DMUB_PHY_FSM_PLL_EN, 3253 DMUB_PHY_FSM_TX_EN, 3254 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3255 DMUB_PHY_FSM_FAST_LP, 3256 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3257 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3258 DMUB_PHY_FSM_P2_PLL_OFF, 3259 DMUB_PHY_FSM_P2_PLL_ON, 3260 }; 3261 3262 /** 3263 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3264 */ 3265 struct dmub_cmd_psr_copy_settings_data { 3266 /** 3267 * Flags that can be set by driver to change some PSR behaviour. 3268 */ 3269 union dmub_psr_debug_flags debug; 3270 /** 3271 * 16-bit value dicated by driver that will enable/disable different functionality. 3272 */ 3273 uint16_t psr_level; 3274 /** 3275 * DPP HW instance. 3276 */ 3277 uint8_t dpp_inst; 3278 /** 3279 * MPCC HW instance. 3280 * Not used in dmub fw, 3281 * dmub fw will get active opp by reading odm registers. 3282 */ 3283 uint8_t mpcc_inst; 3284 /** 3285 * OPP HW instance. 3286 * Not used in dmub fw, 3287 * dmub fw will get active opp by reading odm registers. 3288 */ 3289 uint8_t opp_inst; 3290 /** 3291 * OTG HW instance. 3292 */ 3293 uint8_t otg_inst; 3294 /** 3295 * DIG FE HW instance. 3296 */ 3297 uint8_t digfe_inst; 3298 /** 3299 * DIG BE HW instance. 3300 */ 3301 uint8_t digbe_inst; 3302 /** 3303 * DP PHY HW instance. 3304 */ 3305 uint8_t dpphy_inst; 3306 /** 3307 * AUX HW instance. 3308 */ 3309 uint8_t aux_inst; 3310 /** 3311 * Determines if SMU optimzations are enabled/disabled. 3312 */ 3313 uint8_t smu_optimizations_en; 3314 /** 3315 * Unused. 3316 * TODO: Remove. 3317 */ 3318 uint8_t frame_delay; 3319 /** 3320 * If RFB setup time is greater than the total VBLANK time, 3321 * it is not possible for the sink to capture the video frame 3322 * in the same frame the SDP is sent. In this case, 3323 * the frame capture indication bit should be set and an extra 3324 * static frame should be transmitted to the sink. 3325 */ 3326 uint8_t frame_cap_ind; 3327 /** 3328 * Granularity of Y offset supported by sink. 3329 */ 3330 uint8_t su_y_granularity; 3331 /** 3332 * Indicates whether sink should start capturing 3333 * immediately following active scan line, 3334 * or starting with the 2nd active scan line. 3335 */ 3336 uint8_t line_capture_indication; 3337 /** 3338 * Multi-display optimizations are implemented on certain ASICs. 3339 */ 3340 uint8_t multi_disp_optimizations_en; 3341 /** 3342 * The last possible line SDP may be transmitted without violating 3343 * the RFB setup time or entering the active video frame. 3344 */ 3345 uint16_t init_sdp_deadline; 3346 /** 3347 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3348 */ 3349 uint8_t rate_control_caps ; 3350 /* 3351 * Force PSRSU always doing full frame update 3352 */ 3353 uint8_t force_ffu_mode; 3354 /** 3355 * Length of each horizontal line in us. 3356 */ 3357 uint32_t line_time_in_us; 3358 /** 3359 * FEC enable status in driver 3360 */ 3361 uint8_t fec_enable_status; 3362 /** 3363 * FEC re-enable delay when PSR exit. 3364 * unit is 100us, range form 0~255(0xFF). 3365 */ 3366 uint8_t fec_enable_delay_in100us; 3367 /** 3368 * PSR control version. 3369 */ 3370 uint8_t cmd_version; 3371 /** 3372 * Panel Instance. 3373 * Panel instance to identify which psr_state to use 3374 * Currently the support is only for 0 or 1 3375 */ 3376 uint8_t panel_inst; 3377 /* 3378 * DSC enable status in driver 3379 */ 3380 uint8_t dsc_enable_status; 3381 /* 3382 * Use FSM state for PSR power up/down 3383 */ 3384 uint8_t use_phy_fsm; 3385 /** 3386 * frame delay for frame re-lock 3387 */ 3388 uint8_t relock_delay_frame_cnt; 3389 /** 3390 * esd recovery indicate. 3391 */ 3392 uint8_t esd_recovery; 3393 /** 3394 * DSC Slice height. 3395 */ 3396 uint16_t dsc_slice_height; 3397 /** 3398 * Some panels request main link off before xth vertical line 3399 */ 3400 uint16_t poweroff_before_vertical_line; 3401 /** 3402 * Some panels cannot handle idle pattern during PSR entry. 3403 * To power down phy before disable stream to avoid sending 3404 * idle pattern. 3405 */ 3406 uint8_t power_down_phy_before_disable_stream; 3407 }; 3408 3409 /** 3410 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3411 */ 3412 struct dmub_rb_cmd_psr_copy_settings { 3413 /** 3414 * Command header. 3415 */ 3416 struct dmub_cmd_header header; 3417 /** 3418 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3419 */ 3420 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3421 }; 3422 3423 /** 3424 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3425 */ 3426 struct dmub_cmd_psr_set_level_data { 3427 /** 3428 * 16-bit value dicated by driver that will enable/disable different functionality. 3429 */ 3430 uint16_t psr_level; 3431 /** 3432 * PSR control version. 3433 */ 3434 uint8_t cmd_version; 3435 /** 3436 * Panel Instance. 3437 * Panel instance to identify which psr_state to use 3438 * Currently the support is only for 0 or 1 3439 */ 3440 uint8_t panel_inst; 3441 }; 3442 3443 /** 3444 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3445 */ 3446 struct dmub_rb_cmd_psr_set_level { 3447 /** 3448 * Command header. 3449 */ 3450 struct dmub_cmd_header header; 3451 /** 3452 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3453 */ 3454 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3455 }; 3456 3457 struct dmub_rb_cmd_psr_enable_data { 3458 /** 3459 * PSR control version. 3460 */ 3461 uint8_t cmd_version; 3462 /** 3463 * Panel Instance. 3464 * Panel instance to identify which psr_state to use 3465 * Currently the support is only for 0 or 1 3466 */ 3467 uint8_t panel_inst; 3468 /** 3469 * Phy state to enter. 3470 * Values to use are defined in dmub_phy_fsm_state 3471 */ 3472 uint8_t phy_fsm_state; 3473 /** 3474 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3475 * Set this using enum phy_link_rate. 3476 * This does not support HDMI/DP2 for now. 3477 */ 3478 uint8_t phy_rate; 3479 }; 3480 3481 /** 3482 * Definition of a DMUB_CMD__PSR_ENABLE command. 3483 * PSR enable/disable is controlled using the sub_type. 3484 */ 3485 struct dmub_rb_cmd_psr_enable { 3486 /** 3487 * Command header. 3488 */ 3489 struct dmub_cmd_header header; 3490 3491 struct dmub_rb_cmd_psr_enable_data data; 3492 }; 3493 3494 /** 3495 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3496 */ 3497 struct dmub_cmd_psr_set_version_data { 3498 /** 3499 * PSR version that FW should implement. 3500 */ 3501 enum psr_version version; 3502 /** 3503 * PSR control version. 3504 */ 3505 uint8_t cmd_version; 3506 /** 3507 * Panel Instance. 3508 * Panel instance to identify which psr_state to use 3509 * Currently the support is only for 0 or 1 3510 */ 3511 uint8_t panel_inst; 3512 /** 3513 * Explicit padding to 4 byte boundary. 3514 */ 3515 uint8_t pad[2]; 3516 }; 3517 3518 /** 3519 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3520 */ 3521 struct dmub_rb_cmd_psr_set_version { 3522 /** 3523 * Command header. 3524 */ 3525 struct dmub_cmd_header header; 3526 /** 3527 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3528 */ 3529 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3530 }; 3531 3532 struct dmub_cmd_psr_force_static_data { 3533 /** 3534 * PSR control version. 3535 */ 3536 uint8_t cmd_version; 3537 /** 3538 * Panel Instance. 3539 * Panel instance to identify which psr_state to use 3540 * Currently the support is only for 0 or 1 3541 */ 3542 uint8_t panel_inst; 3543 /** 3544 * Explicit padding to 4 byte boundary. 3545 */ 3546 uint8_t pad[2]; 3547 }; 3548 3549 /** 3550 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3551 */ 3552 struct dmub_rb_cmd_psr_force_static { 3553 /** 3554 * Command header. 3555 */ 3556 struct dmub_cmd_header header; 3557 /** 3558 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3559 */ 3560 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3561 }; 3562 3563 /** 3564 * PSR SU debug flags. 3565 */ 3566 union dmub_psr_su_debug_flags { 3567 /** 3568 * PSR SU debug flags. 3569 */ 3570 struct { 3571 /** 3572 * Update dirty rect in SW only. 3573 */ 3574 uint8_t update_dirty_rect_only : 1; 3575 /** 3576 * Reset the cursor/plane state before processing the call. 3577 */ 3578 uint8_t reset_state : 1; 3579 } bitfields; 3580 3581 /** 3582 * Union for debug flags. 3583 */ 3584 uint32_t u32All; 3585 }; 3586 3587 /** 3588 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3589 * This triggers a selective update for PSR SU. 3590 */ 3591 struct dmub_cmd_update_dirty_rect_data { 3592 /** 3593 * Dirty rects from OS. 3594 */ 3595 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3596 /** 3597 * PSR SU debug flags. 3598 */ 3599 union dmub_psr_su_debug_flags debug_flags; 3600 /** 3601 * OTG HW instance. 3602 */ 3603 uint8_t pipe_idx; 3604 /** 3605 * Number of dirty rects. 3606 */ 3607 uint8_t dirty_rect_count; 3608 /** 3609 * PSR control version. 3610 */ 3611 uint8_t cmd_version; 3612 /** 3613 * Panel Instance. 3614 * Panel instance to identify which psr_state to use 3615 * Currently the support is only for 0 or 1 3616 */ 3617 uint8_t panel_inst; 3618 }; 3619 3620 /** 3621 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3622 */ 3623 struct dmub_rb_cmd_update_dirty_rect { 3624 /** 3625 * Command header. 3626 */ 3627 struct dmub_cmd_header header; 3628 /** 3629 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3630 */ 3631 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3632 }; 3633 3634 /** 3635 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3636 */ 3637 union dmub_reg_cursor_control_cfg { 3638 struct { 3639 uint32_t cur_enable: 1; 3640 uint32_t reser0: 3; 3641 uint32_t cur_2x_magnify: 1; 3642 uint32_t reser1: 3; 3643 uint32_t mode: 3; 3644 uint32_t reser2: 5; 3645 uint32_t pitch: 2; 3646 uint32_t reser3: 6; 3647 uint32_t line_per_chunk: 5; 3648 uint32_t reser4: 3; 3649 } bits; 3650 uint32_t raw; 3651 }; 3652 struct dmub_cursor_position_cache_hubp { 3653 union dmub_reg_cursor_control_cfg cur_ctl; 3654 union dmub_reg_position_cfg { 3655 struct { 3656 uint32_t cur_x_pos: 16; 3657 uint32_t cur_y_pos: 16; 3658 } bits; 3659 uint32_t raw; 3660 } position; 3661 union dmub_reg_hot_spot_cfg { 3662 struct { 3663 uint32_t hot_x: 16; 3664 uint32_t hot_y: 16; 3665 } bits; 3666 uint32_t raw; 3667 } hot_spot; 3668 union dmub_reg_dst_offset_cfg { 3669 struct { 3670 uint32_t dst_x_offset: 13; 3671 uint32_t reserved: 19; 3672 } bits; 3673 uint32_t raw; 3674 } dst_offset; 3675 }; 3676 3677 union dmub_reg_cur0_control_cfg { 3678 struct { 3679 uint32_t cur0_enable: 1; 3680 uint32_t expansion_mode: 1; 3681 uint32_t reser0: 1; 3682 uint32_t cur0_rom_en: 1; 3683 uint32_t mode: 3; 3684 uint32_t reserved: 25; 3685 } bits; 3686 uint32_t raw; 3687 }; 3688 struct dmub_cursor_position_cache_dpp { 3689 union dmub_reg_cur0_control_cfg cur0_ctl; 3690 }; 3691 struct dmub_cursor_position_cfg { 3692 struct dmub_cursor_position_cache_hubp pHubp; 3693 struct dmub_cursor_position_cache_dpp pDpp; 3694 uint8_t pipe_idx; 3695 /* 3696 * Padding is required. To be 4 Bytes Aligned. 3697 */ 3698 uint8_t padding[3]; 3699 }; 3700 3701 struct dmub_cursor_attribute_cache_hubp { 3702 uint32_t SURFACE_ADDR_HIGH; 3703 uint32_t SURFACE_ADDR; 3704 union dmub_reg_cursor_control_cfg cur_ctl; 3705 union dmub_reg_cursor_size_cfg { 3706 struct { 3707 uint32_t width: 16; 3708 uint32_t height: 16; 3709 } bits; 3710 uint32_t raw; 3711 } size; 3712 union dmub_reg_cursor_settings_cfg { 3713 struct { 3714 uint32_t dst_y_offset: 8; 3715 uint32_t chunk_hdl_adjust: 2; 3716 uint32_t reserved: 22; 3717 } bits; 3718 uint32_t raw; 3719 } settings; 3720 }; 3721 struct dmub_cursor_attribute_cache_dpp { 3722 union dmub_reg_cur0_control_cfg cur0_ctl; 3723 }; 3724 struct dmub_cursor_attributes_cfg { 3725 struct dmub_cursor_attribute_cache_hubp aHubp; 3726 struct dmub_cursor_attribute_cache_dpp aDpp; 3727 }; 3728 3729 struct dmub_cmd_update_cursor_payload0 { 3730 /** 3731 * Cursor dirty rects. 3732 */ 3733 struct dmub_rect cursor_rect; 3734 /** 3735 * PSR SU debug flags. 3736 */ 3737 union dmub_psr_su_debug_flags debug_flags; 3738 /** 3739 * Cursor enable/disable. 3740 */ 3741 uint8_t enable; 3742 /** 3743 * OTG HW instance. 3744 */ 3745 uint8_t pipe_idx; 3746 /** 3747 * PSR control version. 3748 */ 3749 uint8_t cmd_version; 3750 /** 3751 * Panel Instance. 3752 * Panel instance to identify which psr_state to use 3753 * Currently the support is only for 0 or 1 3754 */ 3755 uint8_t panel_inst; 3756 /** 3757 * Cursor Position Register. 3758 * Registers contains Hubp & Dpp modules 3759 */ 3760 struct dmub_cursor_position_cfg position_cfg; 3761 }; 3762 3763 struct dmub_cmd_update_cursor_payload1 { 3764 struct dmub_cursor_attributes_cfg attribute_cfg; 3765 }; 3766 3767 union dmub_cmd_update_cursor_info_data { 3768 struct dmub_cmd_update_cursor_payload0 payload0; 3769 struct dmub_cmd_update_cursor_payload1 payload1; 3770 }; 3771 /** 3772 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3773 */ 3774 struct dmub_rb_cmd_update_cursor_info { 3775 /** 3776 * Command header. 3777 */ 3778 struct dmub_cmd_header header; 3779 /** 3780 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3781 */ 3782 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3783 }; 3784 3785 /** 3786 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3787 */ 3788 struct dmub_cmd_psr_set_vtotal_data { 3789 /** 3790 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3791 */ 3792 uint16_t psr_vtotal_idle; 3793 /** 3794 * PSR control version. 3795 */ 3796 uint8_t cmd_version; 3797 /** 3798 * Panel Instance. 3799 * Panel instance to identify which psr_state to use 3800 * Currently the support is only for 0 or 1 3801 */ 3802 uint8_t panel_inst; 3803 /* 3804 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3805 */ 3806 uint16_t psr_vtotal_su; 3807 /** 3808 * Explicit padding to 4 byte boundary. 3809 */ 3810 uint8_t pad2[2]; 3811 }; 3812 3813 /** 3814 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3815 */ 3816 struct dmub_rb_cmd_psr_set_vtotal { 3817 /** 3818 * Command header. 3819 */ 3820 struct dmub_cmd_header header; 3821 /** 3822 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3823 */ 3824 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3825 }; 3826 3827 /** 3828 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3829 */ 3830 struct dmub_cmd_psr_set_power_opt_data { 3831 /** 3832 * PSR control version. 3833 */ 3834 uint8_t cmd_version; 3835 /** 3836 * Panel Instance. 3837 * Panel instance to identify which psr_state to use 3838 * Currently the support is only for 0 or 1 3839 */ 3840 uint8_t panel_inst; 3841 /** 3842 * Explicit padding to 4 byte boundary. 3843 */ 3844 uint8_t pad[2]; 3845 /** 3846 * PSR power option 3847 */ 3848 uint32_t power_opt; 3849 }; 3850 3851 /** 3852 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3853 */ 3854 struct dmub_rb_cmd_psr_set_power_opt { 3855 /** 3856 * Command header. 3857 */ 3858 struct dmub_cmd_header header; 3859 /** 3860 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3861 */ 3862 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3863 }; 3864 3865 enum dmub_alpm_mode { 3866 ALPM_AUXWAKE = 0, 3867 ALPM_AUXLESS = 1, 3868 ALPM_UNSUPPORTED = 2, 3869 }; 3870 3871 /** 3872 * Definition of Replay Residency GPINT command. 3873 * Bit[0] - Residency mode for Revision 0 3874 * Bit[1] - Enable/Disable state 3875 * Bit[2-3] - Revision number 3876 * Bit[4-7] - Residency mode for Revision 1 3877 * Bit[8] - Panel instance 3878 * Bit[9-15] - Reserved 3879 */ 3880 3881 enum pr_residency_mode { 3882 PR_RESIDENCY_MODE_PHY = 0x0, 3883 PR_RESIDENCY_MODE_ALPM, 3884 PR_RESIDENCY_MODE_IPS2, 3885 PR_RESIDENCY_MODE_FRAME_CNT, 3886 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3887 }; 3888 3889 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3890 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3891 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3892 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3893 3894 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3895 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3896 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3897 3898 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3899 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3900 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3901 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3902 3903 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3904 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3905 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3906 3907 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3908 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3909 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3910 3911 /** 3912 * Definition of a replay_state. 3913 */ 3914 enum replay_state { 3915 REPLAY_STATE_0 = 0x0, 3916 REPLAY_STATE_1 = 0x10, 3917 REPLAY_STATE_1A = 0x11, 3918 REPLAY_STATE_2 = 0x20, 3919 REPLAY_STATE_2A = 0x21, 3920 REPLAY_STATE_3 = 0x30, 3921 REPLAY_STATE_3INIT = 0x31, 3922 REPLAY_STATE_4 = 0x40, 3923 REPLAY_STATE_4A = 0x41, 3924 REPLAY_STATE_4B = 0x42, 3925 REPLAY_STATE_4C = 0x43, 3926 REPLAY_STATE_4D = 0x44, 3927 REPLAY_STATE_4E = 0x45, 3928 REPLAY_STATE_4B_LOCKED = 0x4A, 3929 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3930 REPLAY_STATE_5 = 0x50, 3931 REPLAY_STATE_5A = 0x51, 3932 REPLAY_STATE_5B = 0x52, 3933 REPLAY_STATE_5A_LOCKED = 0x5A, 3934 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3935 REPLAY_STATE_6 = 0x60, 3936 REPLAY_STATE_6A = 0x61, 3937 REPLAY_STATE_6B = 0x62, 3938 REPLAY_STATE_INVALID = 0xFF, 3939 }; 3940 3941 /** 3942 * Replay command sub-types. 3943 */ 3944 enum dmub_cmd_replay_type { 3945 /** 3946 * Copy driver-calculated parameters to REPLAY state. 3947 */ 3948 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3949 /** 3950 * Enable REPLAY. 3951 */ 3952 DMUB_CMD__REPLAY_ENABLE = 1, 3953 /** 3954 * Set Replay power option. 3955 */ 3956 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3957 /** 3958 * Set coasting vtotal. 3959 */ 3960 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3961 /** 3962 * Set power opt and coasting vtotal. 3963 */ 3964 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3965 /** 3966 * Set disabled iiming sync. 3967 */ 3968 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3969 /** 3970 * Set Residency Frameupdate Timer. 3971 */ 3972 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3973 /** 3974 * Set pseudo vtotal 3975 */ 3976 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3977 /** 3978 * Set adaptive sync sdp enabled 3979 */ 3980 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3981 /** 3982 * Set Replay General command. 3983 */ 3984 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3985 }; 3986 3987 /** 3988 * Replay general command sub-types. 3989 */ 3990 enum dmub_cmd_replay_general_subtype { 3991 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3992 /** 3993 * TODO: For backward compatible, allow new command only. 3994 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3995 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3996 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3997 */ 3998 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3999 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4000 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4001 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4002 }; 4003 4004 struct dmub_alpm_auxless_data { 4005 uint16_t lfps_setup_ns; 4006 uint16_t lfps_period_ns; 4007 uint16_t lfps_silence_ns; 4008 uint16_t lfps_t1_t2_override_us; 4009 short lfps_t1_t2_offset_us; 4010 uint8_t lttpr_count; 4011 }; 4012 4013 /** 4014 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4015 */ 4016 struct dmub_cmd_replay_copy_settings_data { 4017 /** 4018 * Flags that can be set by driver to change some replay behaviour. 4019 */ 4020 union replay_debug_flags debug; 4021 4022 /** 4023 * @flags: Flags used to determine feature functionality. 4024 */ 4025 union replay_hw_flags flags; 4026 4027 /** 4028 * DPP HW instance. 4029 */ 4030 uint8_t dpp_inst; 4031 /** 4032 * OTG HW instance. 4033 */ 4034 uint8_t otg_inst; 4035 /** 4036 * DIG FE HW instance. 4037 */ 4038 uint8_t digfe_inst; 4039 /** 4040 * DIG BE HW instance. 4041 */ 4042 uint8_t digbe_inst; 4043 /** 4044 * AUX HW instance. 4045 */ 4046 uint8_t aux_inst; 4047 /** 4048 * Panel Instance. 4049 * Panel isntance to identify which psr_state to use 4050 * Currently the support is only for 0 or 1 4051 */ 4052 uint8_t panel_inst; 4053 /** 4054 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4055 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4056 */ 4057 uint8_t pixel_deviation_per_line; 4058 /** 4059 * @max_deviation_line: The max number of deviation line that can keep the timing 4060 * synchronized between the Source and Sink during Replay normal sleep mode. 4061 */ 4062 uint8_t max_deviation_line; 4063 /** 4064 * Length of each horizontal line in ns. 4065 */ 4066 uint32_t line_time_in_ns; 4067 /** 4068 * PHY instance. 4069 */ 4070 uint8_t dpphy_inst; 4071 /** 4072 * Determines if SMU optimzations are enabled/disabled. 4073 */ 4074 uint8_t smu_optimizations_en; 4075 /** 4076 * Determines if timing sync are enabled/disabled. 4077 */ 4078 uint8_t replay_timing_sync_supported; 4079 /* 4080 * Use FSM state for Replay power up/down 4081 */ 4082 uint8_t use_phy_fsm; 4083 /** 4084 * Use for AUX-less ALPM LFPS wake operation 4085 */ 4086 struct dmub_alpm_auxless_data auxless_alpm_data; 4087 }; 4088 4089 /** 4090 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4091 */ 4092 struct dmub_rb_cmd_replay_copy_settings { 4093 /** 4094 * Command header. 4095 */ 4096 struct dmub_cmd_header header; 4097 /** 4098 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4099 */ 4100 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4101 }; 4102 4103 /** 4104 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4105 */ 4106 enum replay_enable { 4107 /** 4108 * Disable REPLAY. 4109 */ 4110 REPLAY_DISABLE = 0, 4111 /** 4112 * Enable REPLAY. 4113 */ 4114 REPLAY_ENABLE = 1, 4115 }; 4116 4117 /** 4118 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4119 */ 4120 struct dmub_rb_cmd_replay_enable_data { 4121 /** 4122 * Replay enable or disable. 4123 */ 4124 uint8_t enable; 4125 /** 4126 * Panel Instance. 4127 * Panel isntance to identify which replay_state to use 4128 * Currently the support is only for 0 or 1 4129 */ 4130 uint8_t panel_inst; 4131 /** 4132 * Phy state to enter. 4133 * Values to use are defined in dmub_phy_fsm_state 4134 */ 4135 uint8_t phy_fsm_state; 4136 /** 4137 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4138 * Set this using enum phy_link_rate. 4139 * This does not support HDMI/DP2 for now. 4140 */ 4141 uint8_t phy_rate; 4142 }; 4143 4144 /** 4145 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4146 * Replay enable/disable is controlled using action in data. 4147 */ 4148 struct dmub_rb_cmd_replay_enable { 4149 /** 4150 * Command header. 4151 */ 4152 struct dmub_cmd_header header; 4153 4154 struct dmub_rb_cmd_replay_enable_data data; 4155 }; 4156 4157 /** 4158 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4159 */ 4160 struct dmub_cmd_replay_set_power_opt_data { 4161 /** 4162 * Panel Instance. 4163 * Panel isntance to identify which replay_state to use 4164 * Currently the support is only for 0 or 1 4165 */ 4166 uint8_t panel_inst; 4167 /** 4168 * Explicit padding to 4 byte boundary. 4169 */ 4170 uint8_t pad[3]; 4171 /** 4172 * REPLAY power option 4173 */ 4174 uint32_t power_opt; 4175 }; 4176 4177 /** 4178 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4179 */ 4180 struct dmub_cmd_replay_set_timing_sync_data { 4181 /** 4182 * Panel Instance. 4183 * Panel isntance to identify which replay_state to use 4184 * Currently the support is only for 0 or 1 4185 */ 4186 uint8_t panel_inst; 4187 /** 4188 * REPLAY set_timing_sync 4189 */ 4190 uint8_t timing_sync_supported; 4191 /** 4192 * Explicit padding to 4 byte boundary. 4193 */ 4194 uint8_t pad[2]; 4195 }; 4196 4197 /** 4198 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4199 */ 4200 struct dmub_cmd_replay_set_pseudo_vtotal { 4201 /** 4202 * Panel Instance. 4203 * Panel isntance to identify which replay_state to use 4204 * Currently the support is only for 0 or 1 4205 */ 4206 uint8_t panel_inst; 4207 /** 4208 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4209 */ 4210 uint16_t vtotal; 4211 /** 4212 * Explicit padding to 4 byte boundary. 4213 */ 4214 uint8_t pad; 4215 }; 4216 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4217 /** 4218 * Panel Instance. 4219 * Panel isntance to identify which replay_state to use 4220 * Currently the support is only for 0 or 1 4221 */ 4222 uint8_t panel_inst; 4223 /** 4224 * enabled: set adaptive sync sdp enabled 4225 */ 4226 uint8_t force_disabled; 4227 4228 uint8_t pad[2]; 4229 }; 4230 struct dmub_cmd_replay_set_general_cmd_data { 4231 /** 4232 * Panel Instance. 4233 * Panel isntance to identify which replay_state to use 4234 * Currently the support is only for 0 or 1 4235 */ 4236 uint8_t panel_inst; 4237 /** 4238 * subtype: replay general cmd sub type 4239 */ 4240 uint8_t subtype; 4241 4242 uint8_t pad[2]; 4243 /** 4244 * config data with param1 and param2 4245 */ 4246 uint32_t param1; 4247 4248 uint32_t param2; 4249 }; 4250 4251 /** 4252 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4253 */ 4254 struct dmub_rb_cmd_replay_set_power_opt { 4255 /** 4256 * Command header. 4257 */ 4258 struct dmub_cmd_header header; 4259 /** 4260 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4261 */ 4262 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4263 }; 4264 4265 /** 4266 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4267 */ 4268 struct dmub_cmd_replay_set_coasting_vtotal_data { 4269 /** 4270 * 16-bit value dicated by driver that indicates the coasting vtotal. 4271 */ 4272 uint16_t coasting_vtotal; 4273 /** 4274 * REPLAY control version. 4275 */ 4276 uint8_t cmd_version; 4277 /** 4278 * Panel Instance. 4279 * Panel isntance to identify which replay_state to use 4280 * Currently the support is only for 0 or 1 4281 */ 4282 uint8_t panel_inst; 4283 /** 4284 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4285 */ 4286 uint16_t coasting_vtotal_high; 4287 /** 4288 * Explicit padding to 4 byte boundary. 4289 */ 4290 uint8_t pad[2]; 4291 }; 4292 4293 /** 4294 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4295 */ 4296 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4297 /** 4298 * Command header. 4299 */ 4300 struct dmub_cmd_header header; 4301 /** 4302 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4303 */ 4304 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4305 }; 4306 4307 /** 4308 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4309 */ 4310 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4311 /** 4312 * Command header. 4313 */ 4314 struct dmub_cmd_header header; 4315 /** 4316 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4317 */ 4318 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4319 /** 4320 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4321 */ 4322 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4323 }; 4324 4325 /** 4326 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4327 */ 4328 struct dmub_rb_cmd_replay_set_timing_sync { 4329 /** 4330 * Command header. 4331 */ 4332 struct dmub_cmd_header header; 4333 /** 4334 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4335 */ 4336 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4337 }; 4338 4339 /** 4340 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4341 */ 4342 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4343 /** 4344 * Command header. 4345 */ 4346 struct dmub_cmd_header header; 4347 /** 4348 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4349 */ 4350 struct dmub_cmd_replay_set_pseudo_vtotal data; 4351 }; 4352 4353 /** 4354 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4355 */ 4356 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4357 /** 4358 * Command header. 4359 */ 4360 struct dmub_cmd_header header; 4361 /** 4362 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4363 */ 4364 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4365 }; 4366 4367 /** 4368 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4369 */ 4370 struct dmub_rb_cmd_replay_set_general_cmd { 4371 /** 4372 * Command header. 4373 */ 4374 struct dmub_cmd_header header; 4375 /** 4376 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4377 */ 4378 struct dmub_cmd_replay_set_general_cmd_data data; 4379 }; 4380 4381 /** 4382 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4383 */ 4384 struct dmub_cmd_replay_frameupdate_timer_data { 4385 /** 4386 * Panel Instance. 4387 * Panel isntance to identify which replay_state to use 4388 * Currently the support is only for 0 or 1 4389 */ 4390 uint8_t panel_inst; 4391 /** 4392 * Replay Frameupdate Timer Enable or not 4393 */ 4394 uint8_t enable; 4395 /** 4396 * REPLAY force reflash frame update number 4397 */ 4398 uint16_t frameupdate_count; 4399 }; 4400 /** 4401 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4402 */ 4403 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4404 /** 4405 * Command header. 4406 */ 4407 struct dmub_cmd_header header; 4408 /** 4409 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4410 */ 4411 struct dmub_cmd_replay_frameupdate_timer_data data; 4412 }; 4413 4414 /** 4415 * Definition union of replay command set 4416 */ 4417 union dmub_replay_cmd_set { 4418 /** 4419 * Panel Instance. 4420 * Panel isntance to identify which replay_state to use 4421 * Currently the support is only for 0 or 1 4422 */ 4423 uint8_t panel_inst; 4424 /** 4425 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4426 */ 4427 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4428 /** 4429 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4430 */ 4431 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4432 /** 4433 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4434 */ 4435 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4436 /** 4437 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4438 */ 4439 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4440 /** 4441 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4442 */ 4443 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4444 }; 4445 4446 /** 4447 * Set of HW components that can be locked. 4448 * 4449 * Note: If updating with more HW components, fields 4450 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4451 */ 4452 union dmub_hw_lock_flags { 4453 /** 4454 * Set of HW components that can be locked. 4455 */ 4456 struct { 4457 /** 4458 * Lock/unlock OTG master update lock. 4459 */ 4460 uint8_t lock_pipe : 1; 4461 /** 4462 * Lock/unlock cursor. 4463 */ 4464 uint8_t lock_cursor : 1; 4465 /** 4466 * Lock/unlock global update lock. 4467 */ 4468 uint8_t lock_dig : 1; 4469 /** 4470 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4471 */ 4472 uint8_t triple_buffer_lock : 1; 4473 } bits; 4474 4475 /** 4476 * Union for HW Lock flags. 4477 */ 4478 uint8_t u8All; 4479 }; 4480 4481 /** 4482 * Instances of HW to be locked. 4483 * 4484 * Note: If updating with more HW components, fields 4485 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4486 */ 4487 struct dmub_hw_lock_inst_flags { 4488 /** 4489 * OTG HW instance for OTG master update lock. 4490 */ 4491 uint8_t otg_inst; 4492 /** 4493 * OPP instance for cursor lock. 4494 */ 4495 uint8_t opp_inst; 4496 /** 4497 * OTG HW instance for global update lock. 4498 * TODO: Remove, and re-use otg_inst. 4499 */ 4500 uint8_t dig_inst; 4501 /** 4502 * Explicit pad to 4 byte boundary. 4503 */ 4504 uint8_t pad; 4505 }; 4506 4507 /** 4508 * Clients that can acquire the HW Lock Manager. 4509 * 4510 * Note: If updating with more clients, fields in 4511 * dmub_inbox0_cmd_lock_hw must be updated to match. 4512 */ 4513 enum hw_lock_client { 4514 /** 4515 * Driver is the client of HW Lock Manager. 4516 */ 4517 HW_LOCK_CLIENT_DRIVER = 0, 4518 /** 4519 * PSR SU is the client of HW Lock Manager. 4520 */ 4521 HW_LOCK_CLIENT_PSR_SU = 1, 4522 HW_LOCK_CLIENT_SUBVP = 3, 4523 /** 4524 * Replay is the client of HW Lock Manager. 4525 */ 4526 HW_LOCK_CLIENT_REPLAY = 4, 4527 HW_LOCK_CLIENT_FAMS2 = 5, 4528 /** 4529 * Invalid client. 4530 */ 4531 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4532 }; 4533 4534 /** 4535 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4536 */ 4537 struct dmub_cmd_lock_hw_data { 4538 /** 4539 * Specifies the client accessing HW Lock Manager. 4540 */ 4541 enum hw_lock_client client; 4542 /** 4543 * HW instances to be locked. 4544 */ 4545 struct dmub_hw_lock_inst_flags inst_flags; 4546 /** 4547 * Which components to be locked. 4548 */ 4549 union dmub_hw_lock_flags hw_locks; 4550 /** 4551 * Specifies lock/unlock. 4552 */ 4553 uint8_t lock; 4554 /** 4555 * HW can be unlocked separately from releasing the HW Lock Mgr. 4556 * This flag is set if the client wishes to release the object. 4557 */ 4558 uint8_t should_release; 4559 /** 4560 * Explicit padding to 4 byte boundary. 4561 */ 4562 uint8_t pad; 4563 }; 4564 4565 /** 4566 * Definition of a DMUB_CMD__HW_LOCK command. 4567 * Command is used by driver and FW. 4568 */ 4569 struct dmub_rb_cmd_lock_hw { 4570 /** 4571 * Command header. 4572 */ 4573 struct dmub_cmd_header header; 4574 /** 4575 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4576 */ 4577 struct dmub_cmd_lock_hw_data lock_hw_data; 4578 }; 4579 4580 /** 4581 * ABM command sub-types. 4582 */ 4583 enum dmub_cmd_abm_type { 4584 /** 4585 * Initialize parameters for ABM algorithm. 4586 * Data is passed through an indirect buffer. 4587 */ 4588 DMUB_CMD__ABM_INIT_CONFIG = 0, 4589 /** 4590 * Set OTG and panel HW instance. 4591 */ 4592 DMUB_CMD__ABM_SET_PIPE = 1, 4593 /** 4594 * Set user requested backklight level. 4595 */ 4596 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4597 /** 4598 * Set ABM operating/aggression level. 4599 */ 4600 DMUB_CMD__ABM_SET_LEVEL = 3, 4601 /** 4602 * Set ambient light level. 4603 */ 4604 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4605 /** 4606 * Enable/disable fractional duty cycle for backlight PWM. 4607 */ 4608 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4609 4610 /** 4611 * unregister vertical interrupt after steady state is reached 4612 */ 4613 DMUB_CMD__ABM_PAUSE = 6, 4614 4615 /** 4616 * Save and Restore ABM state. On save we save parameters, and 4617 * on restore we update state with passed in data. 4618 */ 4619 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4620 4621 /** 4622 * Query ABM caps. 4623 */ 4624 DMUB_CMD__ABM_QUERY_CAPS = 8, 4625 4626 /** 4627 * Set ABM Events 4628 */ 4629 DMUB_CMD__ABM_SET_EVENT = 9, 4630 4631 /** 4632 * Get the current ACE curve. 4633 */ 4634 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4635 4636 /** 4637 * Get current histogram data 4638 */ 4639 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4640 }; 4641 4642 /** 4643 * LSDMA command sub-types. 4644 */ 4645 enum dmub_cmd_lsdma_type { 4646 /** 4647 * Initialize parameters for LSDMA. 4648 * Ring buffer is mapped to the ring buffer 4649 */ 4650 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 4651 /** 4652 * LSDMA copies data from source to destination linearly 4653 */ 4654 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 4655 /** 4656 * Send the tiled-to-tiled copy command 4657 */ 4658 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 2, 4659 /** 4660 * Send the poll reg write command 4661 */ 4662 DMUB_CMD__LSDMA_POLL_REG_WRITE = 3, 4663 /** 4664 * Send the pio copy command 4665 */ 4666 DMUB_CMD__LSDMA_PIO_COPY = 4, 4667 /** 4668 * Send the pio constfill command 4669 */ 4670 DMUB_CMD__LSDMA_PIO_CONSTFILL = 5, 4671 }; 4672 4673 struct abm_ace_curve { 4674 /** 4675 * @offsets: ACE curve offsets. 4676 */ 4677 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4678 4679 /** 4680 * @thresholds: ACE curve thresholds. 4681 */ 4682 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4683 4684 /** 4685 * @slopes: ACE curve slopes. 4686 */ 4687 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4688 }; 4689 4690 struct fixed_pt_format { 4691 /** 4692 * @sign_bit: Indicates whether one bit is reserved for the sign. 4693 */ 4694 bool sign_bit; 4695 4696 /** 4697 * @num_int_bits: Number of bits used for integer part. 4698 */ 4699 uint8_t num_int_bits; 4700 4701 /** 4702 * @num_frac_bits: Number of bits used for fractional part. 4703 */ 4704 uint8_t num_frac_bits; 4705 4706 /** 4707 * @pad: Explicit padding to 4 byte boundary. 4708 */ 4709 uint8_t pad; 4710 }; 4711 4712 struct abm_caps { 4713 /** 4714 * @num_hg_bins: Number of histogram bins. 4715 */ 4716 uint8_t num_hg_bins; 4717 4718 /** 4719 * @num_ace_segments: Number of ACE curve segments. 4720 */ 4721 uint8_t num_ace_segments; 4722 4723 /** 4724 * @pad: Explicit padding to 4 byte boundary. 4725 */ 4726 uint8_t pad[2]; 4727 4728 /** 4729 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4730 */ 4731 struct fixed_pt_format ace_thresholds_format; 4732 4733 /** 4734 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4735 */ 4736 struct fixed_pt_format ace_offsets_format; 4737 4738 /** 4739 * @ace_slopes_format: Format of the ACE slopes. 4740 */ 4741 struct fixed_pt_format ace_slopes_format; 4742 }; 4743 4744 /** 4745 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4746 * Requirements: 4747 * - Padded explicitly to 32-bit boundary. 4748 * - Must ensure this structure matches the one on driver-side, 4749 * otherwise it won't be aligned. 4750 */ 4751 struct abm_config_table { 4752 /** 4753 * Gamma curve thresholds, used for crgb conversion. 4754 */ 4755 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4756 /** 4757 * Gamma curve offsets, used for crgb conversion. 4758 */ 4759 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4760 /** 4761 * Gamma curve slopes, used for crgb conversion. 4762 */ 4763 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4764 /** 4765 * Custom backlight curve thresholds. 4766 */ 4767 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4768 /** 4769 * Custom backlight curve offsets. 4770 */ 4771 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4772 /** 4773 * Ambient light thresholds. 4774 */ 4775 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4776 /** 4777 * Minimum programmable backlight. 4778 */ 4779 uint16_t min_abm_backlight; // 122B 4780 /** 4781 * Minimum reduction values. 4782 */ 4783 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4784 /** 4785 * Maximum reduction values. 4786 */ 4787 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4788 /** 4789 * Bright positive gain. 4790 */ 4791 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4792 /** 4793 * Dark negative gain. 4794 */ 4795 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4796 /** 4797 * Hybrid factor. 4798 */ 4799 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4800 /** 4801 * Contrast factor. 4802 */ 4803 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4804 /** 4805 * Deviation gain. 4806 */ 4807 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4808 /** 4809 * Minimum knee. 4810 */ 4811 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4812 /** 4813 * Maximum knee. 4814 */ 4815 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4816 /** 4817 * Unused. 4818 */ 4819 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4820 /** 4821 * Explicit padding to 4 byte boundary. 4822 */ 4823 uint8_t pad3[3]; // 229B 4824 /** 4825 * Backlight ramp reduction. 4826 */ 4827 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4828 /** 4829 * Backlight ramp start. 4830 */ 4831 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4832 }; 4833 4834 /** 4835 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4836 */ 4837 struct dmub_cmd_abm_set_pipe_data { 4838 /** 4839 * OTG HW instance. 4840 */ 4841 uint8_t otg_inst; 4842 4843 /** 4844 * Panel Control HW instance. 4845 */ 4846 uint8_t panel_inst; 4847 4848 /** 4849 * Controls how ABM will interpret a set pipe or set level command. 4850 */ 4851 uint8_t set_pipe_option; 4852 4853 /** 4854 * Unused. 4855 * TODO: Remove. 4856 */ 4857 uint8_t ramping_boundary; 4858 4859 /** 4860 * PwrSeq HW Instance. 4861 */ 4862 uint8_t pwrseq_inst; 4863 4864 /** 4865 * Explicit padding to 4 byte boundary. 4866 */ 4867 uint8_t pad[3]; 4868 }; 4869 4870 /** 4871 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4872 */ 4873 struct dmub_rb_cmd_abm_set_pipe { 4874 /** 4875 * Command header. 4876 */ 4877 struct dmub_cmd_header header; 4878 4879 /** 4880 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4881 */ 4882 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4883 }; 4884 4885 /** 4886 * Type of backlight control method to be used by ABM module 4887 */ 4888 enum dmub_backlight_control_type { 4889 /** 4890 * PWM Backlight control 4891 */ 4892 DMU_BACKLIGHT_CONTROL_PWM = 0, 4893 /** 4894 * VESA Aux-based backlight control 4895 */ 4896 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4897 /** 4898 * AMD DPCD Aux-based backlight control 4899 */ 4900 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4901 }; 4902 4903 /** 4904 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4905 */ 4906 struct dmub_cmd_abm_set_backlight_data { 4907 /** 4908 * Number of frames to ramp to backlight user level. 4909 */ 4910 uint32_t frame_ramp; 4911 4912 /** 4913 * Requested backlight level from user. 4914 */ 4915 uint32_t backlight_user_level; 4916 4917 /** 4918 * ABM control version. 4919 */ 4920 uint8_t version; 4921 4922 /** 4923 * Panel Control HW instance mask. 4924 * Bit 0 is Panel Control HW instance 0. 4925 * Bit 1 is Panel Control HW instance 1. 4926 */ 4927 uint8_t panel_mask; 4928 4929 /** 4930 * AUX HW Instance. 4931 */ 4932 uint8_t aux_inst; 4933 4934 /** 4935 * Explicit padding to 4 byte boundary. 4936 */ 4937 uint8_t pad[1]; 4938 4939 /** 4940 * Backlight control type. 4941 * Value 0 is PWM backlight control. 4942 * Value 1 is VAUX backlight control. 4943 * Value 2 is AMD DPCD AUX backlight control. 4944 */ 4945 enum dmub_backlight_control_type backlight_control_type; 4946 4947 /** 4948 * Minimum luminance in nits. 4949 */ 4950 uint32_t min_luminance; 4951 4952 /** 4953 * Maximum luminance in nits. 4954 */ 4955 uint32_t max_luminance; 4956 4957 /** 4958 * Minimum backlight in pwm. 4959 */ 4960 uint32_t min_backlight_pwm; 4961 4962 /** 4963 * Maximum backlight in pwm. 4964 */ 4965 uint32_t max_backlight_pwm; 4966 }; 4967 4968 /** 4969 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4970 */ 4971 struct dmub_rb_cmd_abm_set_backlight { 4972 /** 4973 * Command header. 4974 */ 4975 struct dmub_cmd_header header; 4976 4977 /** 4978 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4979 */ 4980 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4981 }; 4982 4983 /** 4984 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4985 */ 4986 struct dmub_cmd_abm_set_level_data { 4987 /** 4988 * Set current ABM operating/aggression level. 4989 */ 4990 uint32_t level; 4991 4992 /** 4993 * ABM control version. 4994 */ 4995 uint8_t version; 4996 4997 /** 4998 * Panel Control HW instance mask. 4999 * Bit 0 is Panel Control HW instance 0. 5000 * Bit 1 is Panel Control HW instance 1. 5001 */ 5002 uint8_t panel_mask; 5003 5004 /** 5005 * Explicit padding to 4 byte boundary. 5006 */ 5007 uint8_t pad[2]; 5008 }; 5009 5010 /** 5011 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5012 */ 5013 struct dmub_rb_cmd_abm_set_level { 5014 /** 5015 * Command header. 5016 */ 5017 struct dmub_cmd_header header; 5018 5019 /** 5020 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5021 */ 5022 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5023 }; 5024 5025 /** 5026 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5027 */ 5028 struct dmub_cmd_abm_set_ambient_level_data { 5029 /** 5030 * Ambient light sensor reading from OS. 5031 */ 5032 uint32_t ambient_lux; 5033 5034 /** 5035 * ABM control version. 5036 */ 5037 uint8_t version; 5038 5039 /** 5040 * Panel Control HW instance mask. 5041 * Bit 0 is Panel Control HW instance 0. 5042 * Bit 1 is Panel Control HW instance 1. 5043 */ 5044 uint8_t panel_mask; 5045 5046 /** 5047 * Explicit padding to 4 byte boundary. 5048 */ 5049 uint8_t pad[2]; 5050 }; 5051 5052 /** 5053 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5054 */ 5055 struct dmub_rb_cmd_abm_set_ambient_level { 5056 /** 5057 * Command header. 5058 */ 5059 struct dmub_cmd_header header; 5060 5061 /** 5062 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5063 */ 5064 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5065 }; 5066 5067 /** 5068 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5069 */ 5070 struct dmub_cmd_abm_set_pwm_frac_data { 5071 /** 5072 * Enable/disable fractional duty cycle for backlight PWM. 5073 * TODO: Convert to uint8_t. 5074 */ 5075 uint32_t fractional_pwm; 5076 5077 /** 5078 * ABM control version. 5079 */ 5080 uint8_t version; 5081 5082 /** 5083 * Panel Control HW instance mask. 5084 * Bit 0 is Panel Control HW instance 0. 5085 * Bit 1 is Panel Control HW instance 1. 5086 */ 5087 uint8_t panel_mask; 5088 5089 /** 5090 * Explicit padding to 4 byte boundary. 5091 */ 5092 uint8_t pad[2]; 5093 }; 5094 5095 /** 5096 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5097 */ 5098 struct dmub_rb_cmd_abm_set_pwm_frac { 5099 /** 5100 * Command header. 5101 */ 5102 struct dmub_cmd_header header; 5103 5104 /** 5105 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5106 */ 5107 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5108 }; 5109 5110 /** 5111 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5112 */ 5113 struct dmub_cmd_abm_init_config_data { 5114 /** 5115 * Location of indirect buffer used to pass init data to ABM. 5116 */ 5117 union dmub_addr src; 5118 5119 /** 5120 * Indirect buffer length. 5121 */ 5122 uint16_t bytes; 5123 5124 5125 /** 5126 * ABM control version. 5127 */ 5128 uint8_t version; 5129 5130 /** 5131 * Panel Control HW instance mask. 5132 * Bit 0 is Panel Control HW instance 0. 5133 * Bit 1 is Panel Control HW instance 1. 5134 */ 5135 uint8_t panel_mask; 5136 5137 /** 5138 * Explicit padding to 4 byte boundary. 5139 */ 5140 uint8_t pad[2]; 5141 }; 5142 5143 /** 5144 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5145 */ 5146 struct dmub_rb_cmd_abm_init_config { 5147 /** 5148 * Command header. 5149 */ 5150 struct dmub_cmd_header header; 5151 5152 /** 5153 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5154 */ 5155 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5156 }; 5157 5158 /** 5159 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5160 */ 5161 5162 struct dmub_cmd_abm_pause_data { 5163 5164 /** 5165 * Panel Control HW instance mask. 5166 * Bit 0 is Panel Control HW instance 0. 5167 * Bit 1 is Panel Control HW instance 1. 5168 */ 5169 uint8_t panel_mask; 5170 5171 /** 5172 * OTG hw instance 5173 */ 5174 uint8_t otg_inst; 5175 5176 /** 5177 * Enable or disable ABM pause 5178 */ 5179 uint8_t enable; 5180 5181 /** 5182 * Explicit padding to 4 byte boundary. 5183 */ 5184 uint8_t pad[1]; 5185 }; 5186 5187 /** 5188 * Definition of a DMUB_CMD__ABM_PAUSE command. 5189 */ 5190 struct dmub_rb_cmd_abm_pause { 5191 /** 5192 * Command header. 5193 */ 5194 struct dmub_cmd_header header; 5195 5196 /** 5197 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5198 */ 5199 struct dmub_cmd_abm_pause_data abm_pause_data; 5200 }; 5201 5202 /** 5203 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5204 */ 5205 struct dmub_cmd_abm_query_caps_in { 5206 /** 5207 * Panel instance. 5208 */ 5209 uint8_t panel_inst; 5210 5211 /** 5212 * Explicit padding to 4 byte boundary. 5213 */ 5214 uint8_t pad[3]; 5215 }; 5216 5217 /** 5218 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5219 */ 5220 struct dmub_cmd_abm_query_caps_out { 5221 /** 5222 * SW Algorithm caps. 5223 */ 5224 struct abm_caps sw_caps; 5225 5226 /** 5227 * ABM HW caps. 5228 */ 5229 struct abm_caps hw_caps; 5230 }; 5231 5232 /** 5233 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5234 */ 5235 struct dmub_rb_cmd_abm_query_caps { 5236 /** 5237 * Command header. 5238 */ 5239 struct dmub_cmd_header header; 5240 5241 /** 5242 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5243 */ 5244 union { 5245 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5246 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5247 } data; 5248 }; 5249 5250 /** 5251 * enum dmub_abm_ace_curve_type - ACE curve type. 5252 */ 5253 enum dmub_abm_ace_curve_type { 5254 /** 5255 * ACE curve as defined by the SW layer. 5256 */ 5257 ABM_ACE_CURVE_TYPE__SW = 0, 5258 /** 5259 * ACE curve as defined by the SW to HW translation interface layer. 5260 */ 5261 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5262 }; 5263 5264 /** 5265 * enum dmub_abm_histogram_type - Histogram type. 5266 */ 5267 enum dmub_abm_histogram_type { 5268 /** 5269 * ACE curve as defined by the SW layer. 5270 */ 5271 ABM_HISTOGRAM_TYPE__SW = 0, 5272 /** 5273 * ACE curve as defined by the SW to HW translation interface layer. 5274 */ 5275 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5276 }; 5277 5278 /** 5279 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5280 */ 5281 struct dmub_rb_cmd_abm_get_ace_curve { 5282 /** 5283 * Command header. 5284 */ 5285 struct dmub_cmd_header header; 5286 5287 /** 5288 * Address where ACE curve should be copied. 5289 */ 5290 union dmub_addr dest; 5291 5292 /** 5293 * Type of ACE curve being queried. 5294 */ 5295 enum dmub_abm_ace_curve_type ace_type; 5296 5297 /** 5298 * Indirect buffer length. 5299 */ 5300 uint16_t bytes; 5301 5302 /** 5303 * eDP panel instance. 5304 */ 5305 uint8_t panel_inst; 5306 5307 /** 5308 * Explicit padding to 4 byte boundary. 5309 */ 5310 uint8_t pad; 5311 }; 5312 5313 /** 5314 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5315 */ 5316 struct dmub_rb_cmd_abm_get_histogram { 5317 /** 5318 * Command header. 5319 */ 5320 struct dmub_cmd_header header; 5321 5322 /** 5323 * Address where Histogram should be copied. 5324 */ 5325 union dmub_addr dest; 5326 5327 /** 5328 * Type of Histogram being queried. 5329 */ 5330 enum dmub_abm_histogram_type histogram_type; 5331 5332 /** 5333 * Indirect buffer length. 5334 */ 5335 uint16_t bytes; 5336 5337 /** 5338 * eDP panel instance. 5339 */ 5340 uint8_t panel_inst; 5341 5342 /** 5343 * Explicit padding to 4 byte boundary. 5344 */ 5345 uint8_t pad; 5346 }; 5347 5348 /** 5349 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5350 */ 5351 struct dmub_rb_cmd_abm_save_restore { 5352 /** 5353 * Command header. 5354 */ 5355 struct dmub_cmd_header header; 5356 5357 /** 5358 * OTG hw instance 5359 */ 5360 uint8_t otg_inst; 5361 5362 /** 5363 * Enable or disable ABM pause 5364 */ 5365 uint8_t freeze; 5366 5367 /** 5368 * Explicit padding to 4 byte boundary. 5369 */ 5370 uint8_t debug; 5371 5372 /** 5373 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5374 */ 5375 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5376 }; 5377 5378 /** 5379 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5380 */ 5381 5382 struct dmub_cmd_abm_set_event_data { 5383 5384 /** 5385 * VB Scaling Init. Strength Mapping 5386 * Byte 0: 0~255 for VB level 0 5387 * Byte 1: 0~255 for VB level 1 5388 * Byte 2: 0~255 for VB level 2 5389 * Byte 3: 0~255 for VB level 3 5390 */ 5391 uint32_t vb_scaling_strength_mapping; 5392 /** 5393 * VariBright Scaling Enable 5394 */ 5395 uint8_t vb_scaling_enable; 5396 /** 5397 * Panel Control HW instance mask. 5398 * Bit 0 is Panel Control HW instance 0. 5399 * Bit 1 is Panel Control HW instance 1. 5400 */ 5401 uint8_t panel_mask; 5402 5403 /** 5404 * Explicit padding to 4 byte boundary. 5405 */ 5406 uint8_t pad[2]; 5407 }; 5408 5409 /** 5410 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5411 */ 5412 struct dmub_rb_cmd_abm_set_event { 5413 /** 5414 * Command header. 5415 */ 5416 struct dmub_cmd_header header; 5417 5418 /** 5419 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5420 */ 5421 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5422 }; 5423 5424 /** 5425 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5426 */ 5427 struct dmub_cmd_query_feature_caps_data { 5428 /** 5429 * DMUB feature capabilities. 5430 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5431 */ 5432 struct dmub_feature_caps feature_caps; 5433 }; 5434 5435 /** 5436 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5437 */ 5438 struct dmub_rb_cmd_query_feature_caps { 5439 /** 5440 * Command header. 5441 */ 5442 struct dmub_cmd_header header; 5443 /** 5444 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5445 */ 5446 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5447 }; 5448 5449 /** 5450 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5451 */ 5452 struct dmub_cmd_visual_confirm_color_data { 5453 /** 5454 * DMUB visual confirm color 5455 */ 5456 struct dmub_visual_confirm_color visual_confirm_color; 5457 }; 5458 5459 /** 5460 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5461 */ 5462 struct dmub_rb_cmd_get_visual_confirm_color { 5463 /** 5464 * Command header. 5465 */ 5466 struct dmub_cmd_header header; 5467 /** 5468 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5469 */ 5470 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5471 }; 5472 5473 /** 5474 * enum dmub_cmd_panel_cntl_type - Panel control command. 5475 */ 5476 enum dmub_cmd_panel_cntl_type { 5477 /** 5478 * Initializes embedded panel hardware blocks. 5479 */ 5480 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5481 /** 5482 * Queries backlight info for the embedded panel. 5483 */ 5484 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5485 /** 5486 * Sets the PWM Freq as per user's requirement. 5487 */ 5488 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5489 }; 5490 5491 /** 5492 * struct dmub_cmd_panel_cntl_data - Panel control data. 5493 */ 5494 struct dmub_cmd_panel_cntl_data { 5495 uint32_t pwrseq_inst; /**< pwrseq instance */ 5496 uint32_t current_backlight; /* in/out */ 5497 uint32_t bl_pwm_cntl; /* in/out */ 5498 uint32_t bl_pwm_period_cntl; /* in/out */ 5499 uint32_t bl_pwm_ref_div1; /* in/out */ 5500 uint8_t is_backlight_on : 1; /* in/out */ 5501 uint8_t is_powered_on : 1; /* in/out */ 5502 uint8_t padding[3]; 5503 uint32_t bl_pwm_ref_div2; /* in/out */ 5504 uint8_t reserved[4]; 5505 }; 5506 5507 /** 5508 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5509 */ 5510 struct dmub_rb_cmd_panel_cntl { 5511 struct dmub_cmd_header header; /**< header */ 5512 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5513 }; 5514 5515 struct dmub_optc_state { 5516 uint32_t v_total_max; 5517 uint32_t v_total_min; 5518 uint32_t tg_inst; 5519 }; 5520 5521 struct dmub_rb_cmd_drr_update { 5522 struct dmub_cmd_header header; 5523 struct dmub_optc_state dmub_optc_state_req; 5524 }; 5525 5526 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5527 uint32_t pix_clk_100hz; 5528 uint8_t max_ramp_step; 5529 uint8_t pipes; 5530 uint8_t min_refresh_in_hz; 5531 uint8_t pipe_count; 5532 uint8_t pipe_index[4]; 5533 }; 5534 5535 struct dmub_cmd_fw_assisted_mclk_switch_config { 5536 uint8_t fams_enabled; 5537 uint8_t visual_confirm_enabled; 5538 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5539 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5540 }; 5541 5542 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5543 struct dmub_cmd_header header; 5544 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5545 }; 5546 5547 /** 5548 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5549 */ 5550 struct dmub_cmd_lvtma_control_data { 5551 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5552 uint8_t bypass_panel_control_wait; 5553 uint8_t reserved_0[2]; /**< For future use */ 5554 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5555 uint8_t reserved_1[3]; /**< For future use */ 5556 }; 5557 5558 /** 5559 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5560 */ 5561 struct dmub_rb_cmd_lvtma_control { 5562 /** 5563 * Command header. 5564 */ 5565 struct dmub_cmd_header header; 5566 /** 5567 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5568 */ 5569 struct dmub_cmd_lvtma_control_data data; 5570 }; 5571 5572 /** 5573 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5574 */ 5575 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5576 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5577 uint8_t is_usb; /**< is phy is usb */ 5578 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5579 uint8_t is_dp4; /**< is dp in 4 lane */ 5580 }; 5581 5582 /** 5583 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5584 */ 5585 struct dmub_rb_cmd_transmitter_query_dp_alt { 5586 struct dmub_cmd_header header; /**< header */ 5587 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5588 }; 5589 5590 struct phy_test_mode { 5591 uint8_t mode; 5592 uint8_t pat0; 5593 uint8_t pad[2]; 5594 }; 5595 5596 /** 5597 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5598 */ 5599 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5600 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5601 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5602 uint8_t lane_num; /**< Number of lanes */ 5603 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5604 struct phy_test_mode test_mode; 5605 enum dmub_phy_fsm_state state; 5606 uint32_t status; 5607 uint8_t pad; 5608 }; 5609 5610 /** 5611 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5612 */ 5613 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5614 struct dmub_cmd_header header; /**< header */ 5615 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5616 }; 5617 5618 /** 5619 * Maximum number of bytes a chunk sent to DMUB for parsing 5620 */ 5621 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5622 5623 /** 5624 * Represent a chunk of CEA blocks sent to DMUB for parsing 5625 */ 5626 struct dmub_cmd_send_edid_cea { 5627 uint16_t offset; /**< offset into the CEA block */ 5628 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5629 uint16_t cea_total_length; /**< total length of the CEA block */ 5630 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5631 uint8_t pad[3]; /**< padding and for future expansion */ 5632 }; 5633 5634 /** 5635 * Result of VSDB parsing from CEA block 5636 */ 5637 struct dmub_cmd_edid_cea_amd_vsdb { 5638 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5639 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5640 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5641 uint16_t min_frame_rate; /**< Maximum frame rate */ 5642 uint16_t max_frame_rate; /**< Minimum frame rate */ 5643 }; 5644 5645 /** 5646 * Result of sending a CEA chunk 5647 */ 5648 struct dmub_cmd_edid_cea_ack { 5649 uint16_t offset; /**< offset of the chunk into the CEA block */ 5650 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5651 uint8_t pad; /**< padding and for future expansion */ 5652 }; 5653 5654 /** 5655 * Specify whether the result is an ACK/NACK or the parsing has finished 5656 */ 5657 enum dmub_cmd_edid_cea_reply_type { 5658 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5659 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5660 }; 5661 5662 /** 5663 * Definition of a DMUB_CMD__EDID_CEA command. 5664 */ 5665 struct dmub_rb_cmd_edid_cea { 5666 struct dmub_cmd_header header; /**< Command header */ 5667 union dmub_cmd_edid_cea_data { 5668 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5669 struct dmub_cmd_edid_cea_output { /**< output with results */ 5670 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5671 union { 5672 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5673 struct dmub_cmd_edid_cea_ack ack; 5674 }; 5675 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5676 } data; /**< Command data */ 5677 5678 }; 5679 5680 /** 5681 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5682 */ 5683 struct dmub_cmd_cable_id_input { 5684 uint8_t phy_inst; /**< phy inst for cable id data */ 5685 }; 5686 5687 /** 5688 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5689 */ 5690 struct dmub_cmd_cable_id_output { 5691 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5692 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5693 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5694 uint8_t RESERVED :2; /**< reserved means not defined */ 5695 }; 5696 5697 /** 5698 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5699 */ 5700 struct dmub_rb_cmd_get_usbc_cable_id { 5701 struct dmub_cmd_header header; /**< Command header */ 5702 /** 5703 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5704 */ 5705 union dmub_cmd_cable_id_data { 5706 struct dmub_cmd_cable_id_input input; /**< Input */ 5707 struct dmub_cmd_cable_id_output output; /**< Output */ 5708 uint8_t output_raw; /**< Raw data output */ 5709 } data; 5710 }; 5711 5712 enum dmub_cmd_fused_io_sub_type { 5713 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5714 DMUB_CMD__FUSED_IO_ABORT = 1, 5715 }; 5716 5717 enum dmub_cmd_fused_request_type { 5718 FUSED_REQUEST_READ, 5719 FUSED_REQUEST_WRITE, 5720 FUSED_REQUEST_POLL, 5721 }; 5722 5723 enum dmub_cmd_fused_request_status { 5724 FUSED_REQUEST_STATUS_SUCCESS, 5725 FUSED_REQUEST_STATUS_BEGIN, 5726 FUSED_REQUEST_STATUS_SUBMIT, 5727 FUSED_REQUEST_STATUS_REPLY, 5728 FUSED_REQUEST_STATUS_POLL, 5729 FUSED_REQUEST_STATUS_ABORTED, 5730 FUSED_REQUEST_STATUS_FAILED = 0x80, 5731 FUSED_REQUEST_STATUS_INVALID, 5732 FUSED_REQUEST_STATUS_BUSY, 5733 FUSED_REQUEST_STATUS_TIMEOUT, 5734 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5735 }; 5736 5737 struct dmub_cmd_fused_request { 5738 uint8_t status; 5739 uint8_t type : 2; 5740 uint8_t _reserved0 : 3; 5741 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5742 uint8_t identifier; 5743 uint8_t _reserved1; 5744 uint32_t timeout_us; 5745 union dmub_cmd_fused_request_location { 5746 struct dmub_cmd_fused_request_location_i2c { 5747 uint8_t is_aux : 1; // False 5748 uint8_t ddc_line : 3; 5749 uint8_t over_aux : 1; 5750 uint8_t _reserved0 : 3; 5751 uint8_t address; 5752 uint8_t offset; 5753 uint8_t length; 5754 } i2c; 5755 struct dmub_cmd_fused_request_location_aux { 5756 uint32_t is_aux : 1; // True 5757 uint32_t ddc_line : 3; 5758 uint32_t address : 20; 5759 uint32_t length : 8; // Automatically split into 16B transactions 5760 } aux; 5761 } u; 5762 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5763 }; 5764 5765 struct dmub_rb_cmd_fused_io { 5766 struct dmub_cmd_header header; 5767 struct dmub_cmd_fused_request request; 5768 }; 5769 5770 /** 5771 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5772 */ 5773 enum dmub_cmd_secure_display_type { 5774 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5775 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5776 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5777 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5778 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5779 }; 5780 5781 #define MAX_ROI_NUM 2 5782 5783 struct dmub_cmd_roi_info { 5784 uint16_t x_start; 5785 uint16_t x_end; 5786 uint16_t y_start; 5787 uint16_t y_end; 5788 uint8_t otg_id; 5789 uint8_t phy_id; 5790 }; 5791 5792 struct dmub_cmd_roi_window_ctl { 5793 uint16_t x_start; 5794 uint16_t x_end; 5795 uint16_t y_start; 5796 uint16_t y_end; 5797 bool enable; 5798 }; 5799 5800 struct dmub_cmd_roi_ctl_info { 5801 uint8_t otg_id; 5802 uint8_t phy_id; 5803 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5804 }; 5805 5806 /** 5807 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5808 */ 5809 struct dmub_rb_cmd_secure_display { 5810 struct dmub_cmd_header header; 5811 /** 5812 * Data passed from driver to dmub firmware. 5813 */ 5814 struct dmub_cmd_roi_info roi_info; 5815 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5816 }; 5817 5818 /** 5819 * Command type of a DMUB_CMD__PSP command 5820 */ 5821 enum dmub_cmd_psp_type { 5822 DMUB_CMD__PSP_ASSR_ENABLE = 0 5823 }; 5824 5825 /** 5826 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5827 */ 5828 struct dmub_cmd_assr_enable_data { 5829 /** 5830 * ASSR enable or disable. 5831 */ 5832 uint8_t enable; 5833 /** 5834 * PHY port type. 5835 * Indicates eDP / non-eDP port type 5836 */ 5837 uint8_t phy_port_type; 5838 /** 5839 * PHY port ID. 5840 */ 5841 uint8_t phy_port_id; 5842 /** 5843 * Link encoder index. 5844 */ 5845 uint8_t link_enc_index; 5846 /** 5847 * HPO mode. 5848 */ 5849 uint8_t hpo_mode; 5850 5851 /** 5852 * Reserved field. 5853 */ 5854 uint8_t reserved[7]; 5855 }; 5856 5857 /** 5858 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5859 */ 5860 struct dmub_rb_cmd_assr_enable { 5861 /** 5862 * Command header. 5863 */ 5864 struct dmub_cmd_header header; 5865 5866 /** 5867 * Assr data. 5868 */ 5869 struct dmub_cmd_assr_enable_data assr_data; 5870 5871 /** 5872 * Reserved field. 5873 */ 5874 uint32_t reserved[3]; 5875 }; 5876 5877 /** 5878 * Current definition of "ips_mode" from driver 5879 */ 5880 enum ips_residency_mode { 5881 IPS_RESIDENCY__IPS1_MAX, 5882 IPS_RESIDENCY__IPS2, 5883 IPS_RESIDENCY__IPS1_RCG, 5884 IPS_RESIDENCY__IPS1_ONO2_ON, 5885 }; 5886 5887 #define NUM_IPS_HISTOGRAM_BUCKETS 16 5888 5889 /** 5890 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 5891 */ 5892 struct dmub_ips_residency_info { 5893 uint32_t residency_millipercent; 5894 uint32_t entry_counter; 5895 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 5896 uint64_t total_time_us; 5897 uint64_t total_inactive_time_us; 5898 }; 5899 5900 /** 5901 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 5902 */ 5903 struct dmub_cmd_ips_residency_cntl_data { 5904 uint8_t panel_inst; 5905 uint8_t start_measurement; 5906 uint8_t padding[2]; // align to 4-byte boundary 5907 }; 5908 5909 struct dmub_rb_cmd_ips_residency_cntl { 5910 struct dmub_cmd_header header; 5911 struct dmub_cmd_ips_residency_cntl_data cntl_data; 5912 }; 5913 5914 /** 5915 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 5916 */ 5917 struct dmub_cmd_ips_query_residency_info_data { 5918 union dmub_addr dest; 5919 uint32_t size; 5920 uint32_t ips_mode; 5921 uint8_t panel_inst; 5922 uint8_t padding[3]; // align to 4-byte boundary 5923 }; 5924 5925 struct dmub_rb_cmd_ips_query_residency_info { 5926 struct dmub_cmd_header header; 5927 struct dmub_cmd_ips_query_residency_info_data info_data; 5928 }; 5929 5930 /** 5931 * union dmub_rb_cmd - DMUB inbox command. 5932 */ 5933 union dmub_rb_cmd { 5934 /** 5935 * Elements shared with all commands. 5936 */ 5937 struct dmub_rb_cmd_common cmd_common; 5938 /** 5939 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5940 */ 5941 struct dmub_rb_cmd_read_modify_write read_modify_write; 5942 /** 5943 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5944 */ 5945 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5946 /** 5947 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5948 */ 5949 struct dmub_rb_cmd_burst_write burst_write; 5950 /** 5951 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5952 */ 5953 struct dmub_rb_cmd_reg_wait reg_wait; 5954 /** 5955 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5956 */ 5957 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5958 /** 5959 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5960 */ 5961 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5962 /** 5963 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5964 */ 5965 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5966 /** 5967 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5968 */ 5969 struct dmub_rb_cmd_dpphy_init dpphy_init; 5970 /** 5971 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5972 */ 5973 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5974 /** 5975 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5976 */ 5977 struct dmub_rb_cmd_domain_control domain_control; 5978 /** 5979 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5980 */ 5981 struct dmub_rb_cmd_psr_set_version psr_set_version; 5982 /** 5983 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5984 */ 5985 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5986 /** 5987 * Definition of a DMUB_CMD__PSR_ENABLE command. 5988 */ 5989 struct dmub_rb_cmd_psr_enable psr_enable; 5990 /** 5991 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5992 */ 5993 struct dmub_rb_cmd_psr_set_level psr_set_level; 5994 /** 5995 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5996 */ 5997 struct dmub_rb_cmd_psr_force_static psr_force_static; 5998 /** 5999 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 6000 */ 6001 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6002 /** 6003 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6004 */ 6005 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6006 /** 6007 * Definition of a DMUB_CMD__HW_LOCK command. 6008 * Command is used by driver and FW. 6009 */ 6010 struct dmub_rb_cmd_lock_hw lock_hw; 6011 /** 6012 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6013 */ 6014 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6015 /** 6016 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6017 */ 6018 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6019 /** 6020 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6021 */ 6022 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6023 /** 6024 * Definition of a DMUB_CMD__MALL command. 6025 */ 6026 struct dmub_rb_cmd_mall mall; 6027 6028 /** 6029 * Definition of a DMUB_CMD__CAB command. 6030 */ 6031 struct dmub_rb_cmd_cab_for_ss cab; 6032 6033 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6034 6035 /** 6036 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6037 */ 6038 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6039 6040 /** 6041 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6042 */ 6043 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6044 6045 /** 6046 * Definition of DMUB_CMD__PANEL_CNTL commands. 6047 */ 6048 struct dmub_rb_cmd_panel_cntl panel_cntl; 6049 6050 /** 6051 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6052 */ 6053 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6054 6055 /** 6056 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6057 */ 6058 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6059 6060 /** 6061 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6062 */ 6063 struct dmub_rb_cmd_abm_set_level abm_set_level; 6064 6065 /** 6066 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6067 */ 6068 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6069 6070 /** 6071 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6072 */ 6073 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6074 6075 /** 6076 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6077 */ 6078 struct dmub_rb_cmd_abm_init_config abm_init_config; 6079 6080 /** 6081 * Definition of a DMUB_CMD__ABM_PAUSE command. 6082 */ 6083 struct dmub_rb_cmd_abm_pause abm_pause; 6084 6085 /** 6086 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6087 */ 6088 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6089 6090 /** 6091 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6092 */ 6093 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6094 6095 /** 6096 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6097 */ 6098 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6099 6100 /** 6101 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6102 */ 6103 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6104 6105 /** 6106 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6107 */ 6108 struct dmub_rb_cmd_abm_set_event abm_set_event; 6109 6110 /** 6111 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6112 */ 6113 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6114 6115 /** 6116 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6117 */ 6118 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6119 6120 /** 6121 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6122 */ 6123 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6124 6125 /** 6126 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6127 */ 6128 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6129 struct dmub_rb_cmd_drr_update drr_update; 6130 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6131 6132 /** 6133 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6134 */ 6135 struct dmub_rb_cmd_lvtma_control lvtma_control; 6136 /** 6137 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6138 */ 6139 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6140 /** 6141 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6142 */ 6143 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6144 /** 6145 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6146 */ 6147 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6148 /** 6149 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6150 */ 6151 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6152 /** 6153 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6154 */ 6155 struct dmub_rb_cmd_set_config_request set_config_request; 6156 /** 6157 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6158 */ 6159 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6160 /** 6161 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6162 */ 6163 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6164 /** 6165 * Definition of a DMUB_CMD__EDID_CEA command. 6166 */ 6167 struct dmub_rb_cmd_edid_cea edid_cea; 6168 /** 6169 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6170 */ 6171 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6172 6173 /** 6174 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6175 */ 6176 struct dmub_rb_cmd_query_hpd_state query_hpd; 6177 /** 6178 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6179 */ 6180 struct dmub_rb_cmd_secure_display secure_display; 6181 6182 /** 6183 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6184 */ 6185 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6186 /** 6187 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6188 */ 6189 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6190 /** 6191 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6192 */ 6193 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6194 /* 6195 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6196 */ 6197 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6198 /** 6199 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6200 */ 6201 struct dmub_rb_cmd_replay_enable replay_enable; 6202 /** 6203 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6204 */ 6205 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6206 /** 6207 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6208 */ 6209 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6210 /** 6211 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6212 */ 6213 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6214 6215 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6216 /** 6217 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6218 */ 6219 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6220 /** 6221 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6222 */ 6223 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6224 /** 6225 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6226 */ 6227 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6228 /** 6229 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6230 */ 6231 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6232 /** 6233 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6234 */ 6235 struct dmub_rb_cmd_assr_enable assr_enable; 6236 6237 struct dmub_rb_cmd_fams2 fams2_config; 6238 6239 struct dmub_rb_cmd_ib ib_fams2_config; 6240 6241 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6242 6243 struct dmub_rb_cmd_fams2_flip fams2_flip; 6244 6245 struct dmub_rb_cmd_fused_io fused_io; 6246 6247 /** 6248 * Definition of a DMUB_CMD__LSDMA command. 6249 */ 6250 struct dmub_rb_cmd_lsdma lsdma; 6251 6252 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 6253 6254 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 6255 }; 6256 6257 /** 6258 * union dmub_rb_out_cmd - Outbox command 6259 */ 6260 union dmub_rb_out_cmd { 6261 /** 6262 * Parameters common to every command. 6263 */ 6264 struct dmub_rb_cmd_common cmd_common; 6265 /** 6266 * AUX reply command. 6267 */ 6268 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6269 /** 6270 * HPD notify command. 6271 */ 6272 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6273 /** 6274 * SET_CONFIG reply command. 6275 */ 6276 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6277 /** 6278 * DPIA notification command. 6279 */ 6280 struct dmub_rb_cmd_dpia_notification dpia_notification; 6281 /** 6282 * HPD sense notification command. 6283 */ 6284 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6285 struct dmub_rb_cmd_fused_io fused_io; 6286 }; 6287 #pragma pack(pop) 6288 6289 6290 //============================================================================== 6291 //</DMUB_CMD>=================================================================== 6292 //============================================================================== 6293 //< DMUB_RB>==================================================================== 6294 //============================================================================== 6295 6296 /** 6297 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6298 */ 6299 struct dmub_rb_init_params { 6300 void *ctx; /**< Caller provided context pointer */ 6301 void *base_address; /**< CPU base address for ring's data */ 6302 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6303 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6304 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6305 }; 6306 6307 /** 6308 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6309 */ 6310 struct dmub_rb { 6311 void *base_address; /**< CPU address for the ring's data */ 6312 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6313 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6314 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6315 6316 void *ctx; /**< Caller provided context pointer */ 6317 void *dmub; /**< Pointer to the DMUB interface */ 6318 }; 6319 6320 /** 6321 * @brief Checks if the ringbuffer is empty. 6322 * 6323 * @param rb DMUB Ringbuffer 6324 * @return true if empty 6325 * @return false otherwise 6326 */ 6327 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6328 { 6329 return (rb->wrpt == rb->rptr); 6330 } 6331 6332 /** 6333 * @brief gets number of outstanding requests in the RB 6334 * 6335 * @param rb DMUB Ringbuffer 6336 * @return true if full 6337 */ 6338 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6339 { 6340 uint32_t data_count; 6341 6342 if (rb->wrpt >= rb->rptr) 6343 data_count = rb->wrpt - rb->rptr; 6344 else 6345 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6346 6347 return data_count / DMUB_RB_CMD_SIZE; 6348 } 6349 6350 /** 6351 * @brief gets number of free buffers in the RB 6352 * 6353 * @param rb DMUB Ringbuffer 6354 * @return true if full 6355 */ 6356 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6357 { 6358 uint32_t data_count; 6359 6360 if (rb->wrpt >= rb->rptr) 6361 data_count = rb->wrpt - rb->rptr; 6362 else 6363 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6364 6365 /* +1 because 1 entry is always unusable */ 6366 data_count += DMUB_RB_CMD_SIZE; 6367 6368 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6369 } 6370 6371 /** 6372 * @brief Checks if the ringbuffer is full 6373 * 6374 * @param rb DMUB Ringbuffer 6375 * @return true if full 6376 * @return false otherwise 6377 */ 6378 static inline bool dmub_rb_full(struct dmub_rb *rb) 6379 { 6380 uint32_t data_count; 6381 6382 if (rb->wrpt >= rb->rptr) 6383 data_count = rb->wrpt - rb->rptr; 6384 else 6385 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6386 6387 /* -1 because 1 entry is always unusable */ 6388 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6389 } 6390 6391 /** 6392 * @brief Pushes a command into the ringbuffer 6393 * 6394 * @param rb DMUB ringbuffer 6395 * @param cmd The command to push 6396 * @return true if the ringbuffer was not full 6397 * @return false otherwise 6398 */ 6399 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6400 const union dmub_rb_cmd *cmd) 6401 { 6402 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6403 const uint64_t *src = (const uint64_t *)cmd; 6404 uint8_t i; 6405 6406 if (dmub_rb_full(rb)) 6407 return false; 6408 6409 // copying data 6410 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6411 *dst++ = *src++; 6412 6413 rb->wrpt += DMUB_RB_CMD_SIZE; 6414 6415 if (rb->wrpt >= rb->capacity) 6416 rb->wrpt %= rb->capacity; 6417 6418 return true; 6419 } 6420 6421 /** 6422 * @brief Pushes a command into the DMUB outbox ringbuffer 6423 * 6424 * @param rb DMUB outbox ringbuffer 6425 * @param cmd Outbox command 6426 * @return true if not full 6427 * @return false otherwise 6428 */ 6429 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6430 const union dmub_rb_out_cmd *cmd) 6431 { 6432 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6433 const uint8_t *src = (const uint8_t *)cmd; 6434 6435 if (dmub_rb_full(rb)) 6436 return false; 6437 6438 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6439 6440 rb->wrpt += DMUB_RB_CMD_SIZE; 6441 6442 if (rb->wrpt >= rb->capacity) 6443 rb->wrpt %= rb->capacity; 6444 6445 return true; 6446 } 6447 6448 /** 6449 * @brief Returns the next unprocessed command in the ringbuffer. 6450 * 6451 * @param rb DMUB ringbuffer 6452 * @param cmd The command to return 6453 * @return true if not empty 6454 * @return false otherwise 6455 */ 6456 static inline bool dmub_rb_front(struct dmub_rb *rb, 6457 union dmub_rb_cmd **cmd) 6458 { 6459 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6460 6461 if (dmub_rb_empty(rb)) 6462 return false; 6463 6464 *cmd = (union dmub_rb_cmd *)rb_cmd; 6465 6466 return true; 6467 } 6468 6469 /** 6470 * @brief Determines the next ringbuffer offset. 6471 * 6472 * @param rb DMUB inbox ringbuffer 6473 * @param num_cmds Number of commands 6474 * @param next_rptr The next offset in the ringbuffer 6475 */ 6476 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6477 uint32_t num_cmds, 6478 uint32_t *next_rptr) 6479 { 6480 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6481 6482 if (*next_rptr >= rb->capacity) 6483 *next_rptr %= rb->capacity; 6484 } 6485 6486 /** 6487 * @brief Returns a pointer to a command in the inbox. 6488 * 6489 * @param rb DMUB inbox ringbuffer 6490 * @param cmd The inbox command to return 6491 * @param rptr The ringbuffer offset 6492 * @return true if not empty 6493 * @return false otherwise 6494 */ 6495 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6496 union dmub_rb_cmd **cmd, 6497 uint32_t rptr) 6498 { 6499 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6500 6501 if (dmub_rb_empty(rb)) 6502 return false; 6503 6504 *cmd = (union dmub_rb_cmd *)rb_cmd; 6505 6506 return true; 6507 } 6508 6509 /** 6510 * @brief Returns the next unprocessed command in the outbox. 6511 * 6512 * @param rb DMUB outbox ringbuffer 6513 * @param cmd The outbox command to return 6514 * @return true if not empty 6515 * @return false otherwise 6516 */ 6517 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6518 union dmub_rb_out_cmd *cmd) 6519 { 6520 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6521 uint64_t *dst = (uint64_t *)cmd; 6522 uint8_t i; 6523 6524 if (dmub_rb_empty(rb)) 6525 return false; 6526 6527 // copying data 6528 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6529 *dst++ = *src++; 6530 6531 return true; 6532 } 6533 6534 /** 6535 * @brief Removes the front entry in the ringbuffer. 6536 * 6537 * @param rb DMUB ringbuffer 6538 * @return true if the command was removed 6539 * @return false if there were no commands 6540 */ 6541 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6542 { 6543 if (dmub_rb_empty(rb)) 6544 return false; 6545 6546 rb->rptr += DMUB_RB_CMD_SIZE; 6547 6548 if (rb->rptr >= rb->capacity) 6549 rb->rptr %= rb->capacity; 6550 6551 return true; 6552 } 6553 6554 /** 6555 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6556 * 6557 * Avoids a race condition where DMCUB accesses memory while 6558 * there are still writes in flight to framebuffer. 6559 * 6560 * @param rb DMUB ringbuffer 6561 */ 6562 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6563 { 6564 uint32_t rptr = rb->rptr; 6565 uint32_t wptr = rb->wrpt; 6566 6567 while (rptr != wptr) { 6568 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6569 uint8_t i; 6570 6571 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6572 (void)READ_ONCE(*data++); 6573 6574 rptr += DMUB_RB_CMD_SIZE; 6575 if (rptr >= rb->capacity) 6576 rptr %= rb->capacity; 6577 } 6578 } 6579 6580 /** 6581 * @brief Initializes a DMCUB ringbuffer 6582 * 6583 * @param rb DMUB ringbuffer 6584 * @param init_params initial configuration for the ringbuffer 6585 */ 6586 static inline void dmub_rb_init(struct dmub_rb *rb, 6587 struct dmub_rb_init_params *init_params) 6588 { 6589 rb->base_address = init_params->base_address; 6590 rb->capacity = init_params->capacity; 6591 rb->rptr = init_params->read_ptr; 6592 rb->wrpt = init_params->write_ptr; 6593 } 6594 6595 /** 6596 * @brief Copies output data from in/out commands into the given command. 6597 * 6598 * @param rb DMUB ringbuffer 6599 * @param cmd Command to copy data into 6600 */ 6601 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6602 union dmub_rb_cmd *cmd) 6603 { 6604 // Copy rb entry back into command 6605 uint8_t *rd_ptr = (rb->rptr == 0) ? 6606 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6607 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6608 6609 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6610 } 6611 6612 //============================================================================== 6613 //</DMUB_RB>==================================================================== 6614 //============================================================================== 6615 #endif /* _DMUB_CMD_H_ */ 6616