1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310 struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326 }; 327 #pragma pack(pop) 328 329 /** 330 * Dirty rect definition. 331 */ 332 struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352 }; 353 354 /** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357 union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397 }; 398 399 /** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402 union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 uint32_t reserved : 18; 489 } bitfields; 490 491 uint32_t u32All; 492 }; 493 494 /** 495 * Flags record error state. 496 */ 497 union replay_visual_confirm_error_state_flags { 498 struct { 499 /** 500 * 0x1 (bit 0) - Desync Error flag. 501 */ 502 uint32_t desync_error : 1; 503 504 /** 505 * 0x2 (bit 1) - State Transition Error flag. 506 */ 507 uint32_t state_transition_error : 1; 508 509 /** 510 * 0x4 (bit 2) - Crc Error flag 511 */ 512 uint32_t crc_error : 1; 513 514 /** 515 * 0x8 (bit 3) - Reserved 516 */ 517 uint32_t reserved_3 : 1; 518 519 /** 520 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 521 * Added new debug flag to control DPCD. 522 */ 523 uint32_t incorrect_vtotal_in_static_screen : 1; 524 525 /** 526 * 0x20 (bit 5) - No doubled Refresh Rate. 527 */ 528 uint32_t no_double_rr : 1; 529 530 /** 531 * Reserved bit 6-7 532 */ 533 uint32_t reserved_6_7 : 2; 534 535 /** 536 * Reserved bit 9-31 537 */ 538 uint32_t reserved_9_31 : 24; 539 } bitfields; 540 541 uint32_t u32All; 542 }; 543 544 union replay_hw_flags { 545 struct { 546 /** 547 * @allow_alpm_fw_standby_mode: To indicate whether the 548 * ALPM FW standby mode is allowed 549 */ 550 uint32_t allow_alpm_fw_standby_mode : 1; 551 552 /* 553 * @dsc_enable_status: DSC enable status in driver 554 */ 555 uint32_t dsc_enable_status : 1; 556 557 /** 558 * @fec_enable_status: receive fec enable/disable status from driver 559 */ 560 uint32_t fec_enable_status : 1; 561 562 /* 563 * @smu_optimizations_en: SMU power optimization. 564 * Only when active display is Replay capable and display enters Replay. 565 * Trigger interrupt to SMU to powerup/down. 566 */ 567 uint32_t smu_optimizations_en : 1; 568 569 /** 570 * @phy_power_state: Indicates current phy power state 571 */ 572 uint32_t phy_power_state : 1; 573 574 /** 575 * @link_power_state: Indicates current link power state 576 */ 577 uint32_t link_power_state : 1; 578 /** 579 * Use TPS3 signal when restore main link. 580 */ 581 uint32_t force_wakeup_by_tps3 : 1; 582 /** 583 * @is_alpm_initialized: Indicates whether ALPM is initialized 584 */ 585 uint32_t is_alpm_initialized : 1; 586 587 /** 588 * @alpm_mode: Indicates ALPM mode selected 589 */ 590 uint32_t alpm_mode : 2; 591 } bitfields; 592 593 uint32_t u32All; 594 }; 595 596 union fw_assisted_mclk_switch_version { 597 struct { 598 uint8_t minor : 5; 599 uint8_t major : 3; 600 }; 601 uint8_t ver; 602 }; 603 604 /** 605 * DMUB feature capabilities. 606 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 607 */ 608 struct dmub_feature_caps { 609 /** 610 * Max PSR version supported by FW. 611 */ 612 uint8_t psr; 613 uint8_t fw_assisted_mclk_switch_ver; 614 uint8_t reserved[4]; 615 uint8_t subvp_psr_support; 616 uint8_t gecc_enable; 617 uint8_t replay_supported; 618 uint8_t replay_reserved[3]; 619 uint8_t abm_aux_backlight_support; 620 }; 621 622 struct dmub_visual_confirm_color { 623 /** 624 * Maximum 10 bits color value 625 */ 626 uint16_t color_r_cr; 627 uint16_t color_g_y; 628 uint16_t color_b_cb; 629 uint16_t panel_inst; 630 }; 631 632 /** 633 * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data. 634 */ 635 struct dmub_cursor_offload_pipe_data_dcn30_v1 { 636 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 637 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 638 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 639 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 640 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 641 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 642 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 643 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 644 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 645 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 646 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 647 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 648 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 649 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 650 uint32_t reserved0[4]; 651 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 652 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 653 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 654 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 655 uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 656 uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 657 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16; 658 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16; 659 uint32_t reserved1[5]; 660 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 661 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 662 uint32_t reserved2[3]; 663 }; 664 665 /** 666 * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data. 667 */ 668 struct dmub_cursor_offload_pipe_data_dcn401_v1 { 669 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 670 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 671 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 672 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 673 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 674 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 675 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 676 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 677 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 678 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 679 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 680 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 681 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 682 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 683 uint32_t reserved0[4]; 684 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 685 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 686 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 687 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 688 uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 689 uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 690 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16; 691 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16; 692 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16; 693 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16; 694 uint32_t reserved1[4]; 695 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 696 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 697 uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1; 698 uint32_t reserved2[3]; 699 }; 700 701 /** 702 * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload. 703 */ 704 struct dmub_cursor_offload_pipe_data_v1 { 705 union { 706 struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */ 707 struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */ 708 uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */ 709 }; 710 }; 711 712 /** 713 * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data. 714 */ 715 struct dmub_cursor_offload_payload_data_v1 { 716 uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */ 717 uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */ 718 uint32_t pipe_mask; /**< Mask of pipes to update. */ 719 uint32_t reserved; /**< Reserved for future use. */ 720 struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */ 721 }; 722 723 /** 724 * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload. 725 */ 726 struct dmub_cursor_offload_stream_v1 { 727 struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */ 728 uint32_t write_idx; /**< The index of the last written payload. */ 729 }; 730 731 /** 732 * struct dmub_cursor_offload_v1 - Cursor offload feature state. 733 */ 734 struct dmub_cursor_offload_v1 { 735 struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */ 736 }; 737 738 //============================================================================== 739 //</DMUB_TYPES>================================================================= 740 //============================================================================== 741 //< DMUB_META>================================================================== 742 //============================================================================== 743 #pragma pack(push, 1) 744 745 /* Magic value for identifying dmub_fw_meta_info */ 746 #define DMUB_FW_META_MAGIC 0x444D5542 747 748 /* Offset from the end of the file to the dmub_fw_meta_info */ 749 #define DMUB_FW_META_OFFSET 0x24 750 751 /** 752 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 753 */ 754 union dmub_fw_meta_feature_bits { 755 struct { 756 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 757 uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ 758 uint32_t reserved : 30; 759 } bits; /**< status bits */ 760 uint32_t all; /**< 32-bit access to status bits */ 761 }; 762 763 /** 764 * struct dmub_fw_meta_info - metadata associated with fw binary 765 * 766 * NOTE: This should be considered a stable API. Fields should 767 * not be repurposed or reordered. New fields should be 768 * added instead to extend the structure. 769 * 770 * @magic_value: magic value identifying DMUB firmware meta info 771 * @fw_region_size: size of the firmware state region 772 * @trace_buffer_size: size of the tracebuffer region 773 * @fw_version: the firmware version information 774 * @dal_fw: 1 if the firmware is DAL 775 * @shared_state_size: size of the shared state region in bytes 776 * @shared_state_features: number of shared state features 777 */ 778 struct dmub_fw_meta_info { 779 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 780 uint32_t fw_region_size; /**< size of the firmware state region */ 781 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 782 uint32_t fw_version; /**< the firmware version information */ 783 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 784 uint8_t reserved[3]; /**< padding bits */ 785 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 786 uint16_t shared_state_features; /**< number of shared state features */ 787 uint16_t reserved2; /**< padding bytes */ 788 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 789 }; 790 791 /** 792 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 793 */ 794 union dmub_fw_meta { 795 struct dmub_fw_meta_info info; /**< metadata info */ 796 uint8_t reserved[64]; /**< padding bits */ 797 }; 798 799 #pragma pack(pop) 800 801 //============================================================================== 802 //< DMUB Trace Buffer>================================================================ 803 //============================================================================== 804 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 805 /** 806 * dmub_trace_code_t - firmware trace code, 32-bits 807 */ 808 typedef uint32_t dmub_trace_code_t; 809 810 /** 811 * struct dmcub_trace_buf_entry - Firmware trace entry 812 */ 813 struct dmcub_trace_buf_entry { 814 dmub_trace_code_t trace_code; /**< trace code for the event */ 815 uint32_t tick_count; /**< the tick count at time of trace */ 816 uint32_t param0; /**< trace defined parameter 0 */ 817 uint32_t param1; /**< trace defined parameter 1 */ 818 }; 819 #endif 820 821 //============================================================================== 822 //< DMUB_STATUS>================================================================ 823 //============================================================================== 824 825 /** 826 * DMCUB scratch registers can be used to determine firmware status. 827 * Current scratch register usage is as follows: 828 * 829 * SCRATCH0: FW Boot Status register 830 * SCRATCH5: LVTMA Status Register 831 * SCRATCH15: FW Boot Options register 832 */ 833 834 /** 835 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 836 */ 837 union dmub_fw_boot_status { 838 struct { 839 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 840 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 841 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 842 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 843 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 844 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 845 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 846 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 847 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 848 } bits; /**< status bits */ 849 uint32_t all; /**< 32-bit access to status bits */ 850 }; 851 852 /** 853 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 854 */ 855 enum dmub_fw_boot_status_bit { 856 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 857 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 858 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 859 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 860 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 861 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 862 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 863 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 864 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 865 }; 866 867 /* Register bit definition for SCRATCH5 */ 868 union dmub_lvtma_status { 869 struct { 870 uint32_t psp_ok : 1; 871 uint32_t edp_on : 1; 872 uint32_t reserved : 30; 873 } bits; 874 uint32_t all; 875 }; 876 877 enum dmub_lvtma_status_bit { 878 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 879 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 880 }; 881 882 enum dmub_ips_disable_type { 883 DMUB_IPS_ENABLE = 0, 884 DMUB_IPS_DISABLE_ALL = 1, 885 DMUB_IPS_DISABLE_IPS1 = 2, 886 DMUB_IPS_DISABLE_IPS2 = 3, 887 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 888 DMUB_IPS_DISABLE_DYNAMIC = 5, 889 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 890 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 891 }; 892 893 enum dmub_ips_rcg_disable_type { 894 DMUB_IPS_RCG_ENABLE = 0, 895 DMUB_IPS0_RCG_DISABLE = 1, 896 DMUB_IPS1_RCG_DISABLE = 2, 897 DMUB_IPS_RCG_DISABLE = 3 898 }; 899 900 enum dmub_ips_in_vpb_disable_type { 901 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 902 DMUB_IPS_VPB_DISABLE_ALL = 1, 903 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 904 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 905 }; 906 907 #define DMUB_IPS1_ALLOW_MASK 0x00000001 908 #define DMUB_IPS2_ALLOW_MASK 0x00000002 909 #define DMUB_IPS1_COMMIT_MASK 0x00000004 910 #define DMUB_IPS2_COMMIT_MASK 0x00000008 911 912 enum dmub_ips_comand_type { 913 /** 914 * Start/stop IPS residency measurements for a given IPS mode 915 */ 916 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 917 /** 918 * Query IPS residency information for a given IPS mode 919 */ 920 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 921 }; 922 923 /** 924 * enum dmub_cursor_offload_comand_type - Cursor offload subcommands. 925 */ 926 enum dmub_cursor_offload_comand_type { 927 /** 928 * Initializes the cursor offload feature. 929 */ 930 DMUB_CMD__CURSOR_OFFLOAD_INIT = 0, 931 /** 932 * Enables cursor offloading for a stream and updates the timing parameters. 933 */ 934 DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1, 935 /** 936 * Disables cursor offloading for a given stream. 937 */ 938 DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2, 939 /** 940 * Programs the latest data for a given stream. 941 */ 942 DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3, 943 }; 944 945 /** 946 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 947 */ 948 union dmub_fw_boot_options { 949 struct { 950 uint32_t pemu_env : 1; /**< 1 if PEMU */ 951 uint32_t fpga_env : 1; /**< 1 if FPGA */ 952 uint32_t optimized_init : 1; /**< 1 if optimized init */ 953 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 954 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 955 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 956 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 957 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 958 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 959 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 960 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 961 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 962 uint32_t power_optimization: 1; 963 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 964 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 965 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 966 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 967 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 968 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 969 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 970 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 971 uint32_t ips_disable: 3; /* options to disable ips support*/ 972 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 973 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 974 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 975 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 976 uint32_t reserved : 5; /**< reserved */ 977 } bits; /**< boot bits */ 978 uint32_t all; /**< 32-bit access to bits */ 979 }; 980 981 enum dmub_fw_boot_options_bit { 982 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 983 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 984 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 985 }; 986 987 //============================================================================== 988 //< DMUB_SHARED_STATE>========================================================== 989 //============================================================================== 990 991 /** 992 * Shared firmware state between driver and firmware for lockless communication 993 * in situations where the inbox/outbox may be unavailable. 994 * 995 * Each structure *must* be at most 256-bytes in size. The layout allocation is 996 * described below: 997 * 998 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 999 */ 1000 1001 /** 1002 * enum dmub_shared_state_feature_id - List of shared state features. 1003 */ 1004 enum dmub_shared_state_feature_id { 1005 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 1006 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 1007 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 1008 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 1009 DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4, 1010 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 1011 }; 1012 1013 /** 1014 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 1015 */ 1016 union dmub_shared_state_ips_fw_signals { 1017 struct { 1018 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 1019 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 1020 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 1021 uint32_t detection_required : 1; /**< 1 if detection is required */ 1022 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 1023 uint32_t reserved_bits : 27; /**< Reversed */ 1024 } bits; 1025 uint32_t all; 1026 }; 1027 1028 /** 1029 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 1030 */ 1031 union dmub_shared_state_ips_driver_signals { 1032 struct { 1033 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 1034 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 1035 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 1036 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 1037 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 1038 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 1039 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 1040 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 1041 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 1042 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 1043 uint32_t reserved_bits : 22; /**< Reversed bits */ 1044 } bits; 1045 uint32_t all; 1046 }; 1047 1048 /** 1049 * IPS FW Version 1050 */ 1051 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 1052 1053 struct dmub_shared_state_debug_setup { 1054 union { 1055 struct { 1056 uint32_t exclude_points[62]; 1057 } profile_mode; 1058 }; 1059 }; 1060 1061 /** 1062 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 1063 */ 1064 struct dmub_shared_state_ips_fw { 1065 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 1066 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 1067 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 1068 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 1069 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 1070 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 1071 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 1072 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 1073 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 1074 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 1075 }; /* 248-bytes, fixed */ 1076 1077 /** 1078 * IPS Driver Version 1079 */ 1080 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 1081 1082 /** 1083 * struct dmub_shared_state_ips_driver - Driver state for IPS. 1084 */ 1085 struct dmub_shared_state_ips_driver { 1086 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 1087 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 1088 }; /* 248-bytes, fixed */ 1089 1090 /** 1091 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1092 */ 1093 struct dmub_shared_state_cursor_offload_stream_v1 { 1094 uint32_t last_write_idx; /**< Last write index */ 1095 uint8_t reserved[28]; /**< Reserved bytes. */ 1096 }; /* 32-bytes, fixed */ 1097 1098 /** 1099 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1100 */ 1101 struct dmub_shared_state_cursor_offload_v1 { 1102 struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */ 1103 uint8_t reserved[56]; /**< reserved for future use */ 1104 }; /* 248-bytes, fixed */ 1105 1106 /** 1107 * enum dmub_shared_state_feature_common - Generic payload. 1108 */ 1109 struct dmub_shared_state_feature_common { 1110 uint32_t padding[62]; 1111 }; /* 248-bytes, fixed */ 1112 1113 /** 1114 * enum dmub_shared_state_feature_header - Feature description. 1115 */ 1116 struct dmub_shared_state_feature_header { 1117 uint16_t id; /**< Feature ID */ 1118 uint16_t version; /**< Feature version */ 1119 uint32_t reserved; /**< Reserved bytes. */ 1120 }; /* 8 bytes, fixed */ 1121 1122 /** 1123 * struct dmub_shared_state_feature_block - Feature block. 1124 */ 1125 struct dmub_shared_state_feature_block { 1126 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 1127 union dmub_shared_feature_state_union { 1128 struct dmub_shared_state_feature_common common; /**< Generic data */ 1129 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 1130 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 1131 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 1132 struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */ 1133 } data; /**< Shared state data. */ 1134 }; /* 256-bytes, fixed */ 1135 1136 /** 1137 * Shared state size in bytes. 1138 */ 1139 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 1140 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 1141 1142 //============================================================================== 1143 //</DMUB_STATUS>================================================================ 1144 //============================================================================== 1145 //< DMUB_VBIOS>================================================================= 1146 //============================================================================== 1147 1148 /* 1149 * enum dmub_cmd_vbios_type - VBIOS commands. 1150 * 1151 * Command IDs should be treated as stable ABI. 1152 * Do not reuse or modify IDs. 1153 */ 1154 enum dmub_cmd_vbios_type { 1155 /** 1156 * Configures the DIG encoder. 1157 */ 1158 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1159 /** 1160 * Controls the PHY. 1161 */ 1162 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1163 /** 1164 * Sets the pixel clock/symbol clock. 1165 */ 1166 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1167 /** 1168 * Enables or disables power gating. 1169 */ 1170 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1171 /** 1172 * Controls embedded panels. 1173 */ 1174 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1175 /** 1176 * Query DP alt status on a transmitter. 1177 */ 1178 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1179 /** 1180 * Control PHY FSM 1181 */ 1182 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1183 /** 1184 * Controls domain power gating 1185 */ 1186 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1187 }; 1188 1189 //============================================================================== 1190 //</DMUB_VBIOS>================================================================= 1191 //============================================================================== 1192 //< DMUB_GPINT>================================================================= 1193 //============================================================================== 1194 1195 /** 1196 * The shifts and masks below may alternatively be used to format and read 1197 * the command register bits. 1198 */ 1199 1200 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1201 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1202 1203 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1204 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1205 1206 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1207 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1208 1209 /** 1210 * Command responses. 1211 */ 1212 1213 /** 1214 * Return response for DMUB_GPINT__STOP_FW command. 1215 */ 1216 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1217 1218 /** 1219 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1220 */ 1221 union dmub_gpint_data_register { 1222 struct { 1223 uint32_t param : 16; /**< 16-bit parameter */ 1224 uint32_t command_code : 12; /**< GPINT command */ 1225 uint32_t status : 4; /**< Command status bit */ 1226 } bits; /**< GPINT bit access */ 1227 uint32_t all; /**< GPINT 32-bit access */ 1228 }; 1229 1230 /* 1231 * enum dmub_gpint_command - GPINT command to DMCUB FW 1232 * 1233 * Command IDs should be treated as stable ABI. 1234 * Do not reuse or modify IDs. 1235 */ 1236 enum dmub_gpint_command { 1237 /** 1238 * Invalid command, ignored. 1239 */ 1240 DMUB_GPINT__INVALID_COMMAND = 0, 1241 /** 1242 * DESC: Queries the firmware version. 1243 * RETURN: Firmware version. 1244 */ 1245 DMUB_GPINT__GET_FW_VERSION = 1, 1246 /** 1247 * DESC: Halts the firmware. 1248 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1249 */ 1250 DMUB_GPINT__STOP_FW = 2, 1251 /** 1252 * DESC: Get PSR state from FW. 1253 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1254 */ 1255 DMUB_GPINT__GET_PSR_STATE = 7, 1256 /** 1257 * DESC: Notifies DMCUB of the currently active streams. 1258 * ARGS: Stream mask, 1 bit per active stream index. 1259 */ 1260 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1261 /** 1262 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1263 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1264 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1265 * RETURN: PSR residency in milli-percent. 1266 */ 1267 DMUB_GPINT__PSR_RESIDENCY = 9, 1268 1269 /** 1270 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1271 */ 1272 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1273 1274 /** 1275 * DESC: Get REPLAY state from FW. 1276 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1277 */ 1278 DMUB_GPINT__GET_REPLAY_STATE = 13, 1279 1280 /** 1281 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1282 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1283 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1284 * RETURN: REPLAY residency in milli-percent. 1285 */ 1286 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1287 1288 /** 1289 * DESC: Copy bounding box to the host. 1290 * ARGS: Version of bounding box to copy 1291 * RETURN: Result of copying bounding box 1292 */ 1293 DMUB_GPINT__BB_COPY = 96, 1294 1295 /** 1296 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1297 * ARGS: The word3 for the 64 bit address 1298 */ 1299 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1300 1301 /** 1302 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1303 * ARGS: The word2 for the 64 bit address 1304 */ 1305 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1306 1307 /** 1308 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1309 * ARGS: The word1 for the 64 bit address 1310 */ 1311 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1312 1313 /** 1314 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1315 * ARGS: The word0 for the 64 bit address 1316 */ 1317 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1318 1319 /** 1320 * DESC: Updates the trace buffer lower 32-bit mask. 1321 * ARGS: The new mask 1322 * RETURN: Lower 32-bit mask. 1323 */ 1324 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1325 1326 /** 1327 * DESC: Updates the trace buffer mask bit0~bit15. 1328 * ARGS: The new mask 1329 * RETURN: Lower 32-bit mask. 1330 */ 1331 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1332 1333 /** 1334 * DESC: Updates the trace buffer mask bit16~bit31. 1335 * ARGS: The new mask 1336 * RETURN: Lower 32-bit mask. 1337 */ 1338 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1339 1340 /** 1341 * DESC: Updates the trace buffer mask bit32~bit47. 1342 * ARGS: The new mask 1343 * RETURN: Lower 32-bit mask. 1344 */ 1345 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1346 1347 /** 1348 * DESC: Updates the trace buffer mask bit48~bit63. 1349 * ARGS: The new mask 1350 * RETURN: Lower 32-bit mask. 1351 */ 1352 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1353 1354 /** 1355 * DESC: Read the trace buffer mask bi0~bit15. 1356 */ 1357 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1358 1359 /** 1360 * DESC: Read the trace buffer mask bit16~bit31. 1361 */ 1362 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1363 1364 /** 1365 * DESC: Read the trace buffer mask bi32~bit47. 1366 */ 1367 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1368 1369 /** 1370 * DESC: Updates the trace buffer mask bit32~bit63. 1371 */ 1372 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1373 1374 /** 1375 * DESC: Set IPS residency measurement 1376 * ARGS: 0 - Disable ips measurement 1377 * 1 - Enable ips measurement 1378 */ 1379 DMUB_GPINT__IPS_RESIDENCY = 121, 1380 1381 /** 1382 * DESC: Enable measurements for various task duration 1383 * ARGS: 0 - Disable measurement 1384 * 1 - Enable measurement 1385 */ 1386 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1387 1388 /** 1389 * DESC: Gets IPS residency in microseconds 1390 * ARGS: 0 - Return IPS1 residency 1391 * 1 - Return IPS2 residency 1392 * 2 - Return IPS1_RCG residency 1393 * 3 - Return IPS1_ONO2_ON residency 1394 * RETURN: Total residency in microseconds - lower 32 bits 1395 */ 1396 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1397 1398 /** 1399 * DESC: Gets IPS1 histogram counts 1400 * ARGS: Bucket index 1401 * RETURN: Total count for the bucket 1402 */ 1403 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1404 1405 /** 1406 * DESC: Gets IPS2 histogram counts 1407 * ARGS: Bucket index 1408 * RETURN: Total count for the bucket 1409 */ 1410 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1411 1412 /** 1413 * DESC: Gets IPS residency 1414 * ARGS: 0 - Return IPS1 residency 1415 * 1 - Return IPS2 residency 1416 * 2 - Return IPS1_RCG residency 1417 * 3 - Return IPS1_ONO2_ON residency 1418 * RETURN: Total residency in milli-percent. 1419 */ 1420 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1421 1422 /** 1423 * DESC: Gets IPS1_RCG histogram counts 1424 * ARGS: Bucket index 1425 * RETURN: Total count for the bucket 1426 */ 1427 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1428 1429 /** 1430 * DESC: Gets IPS1_ONO2_ON histogram counts 1431 * ARGS: Bucket index 1432 * RETURN: Total count for the bucket 1433 */ 1434 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1435 1436 /** 1437 * DESC: Gets IPS entry counter during residency measurement 1438 * ARGS: 0 - Return IPS1 entry counts 1439 * 1 - Return IPS2 entry counts 1440 * 2 - Return IPS1_RCG entry counts 1441 * 3 - Return IPS2_ONO2_ON entry counts 1442 * RETURN: Entry counter for selected IPS mode 1443 */ 1444 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1445 1446 /** 1447 * DESC: Gets IPS inactive residency in microseconds 1448 * ARGS: 0 - Return IPS1_MAX residency 1449 * 1 - Return IPS2 residency 1450 * 2 - Return IPS1_RCG residency 1451 * 3 - Return IPS1_ONO2_ON residency 1452 * RETURN: Total inactive residency in microseconds - lower 32 bits 1453 */ 1454 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1455 1456 /** 1457 * DESC: Gets IPS inactive residency in microseconds 1458 * ARGS: 0 - Return IPS1_MAX residency 1459 * 1 - Return IPS2 residency 1460 * 2 - Return IPS1_RCG residency 1461 * 3 - Return IPS1_ONO2_ON residency 1462 * RETURN: Total inactive residency in microseconds - upper 32 bits 1463 */ 1464 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1465 1466 /** 1467 * DESC: Gets IPS residency in microseconds 1468 * ARGS: 0 - Return IPS1 residency 1469 * 1 - Return IPS2 residency 1470 * 2 - Return IPS1_RCG residency 1471 * 3 - Return IPS1_ONO2_ON residency 1472 * RETURN: Total residency in microseconds - upper 32 bits 1473 */ 1474 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1475 /** 1476 * DESC: Setup debug configs. 1477 */ 1478 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1479 /** 1480 * DESC: Initiates IPS wake sequence. 1481 */ 1482 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1483 }; 1484 1485 /** 1486 * INBOX0 generic command definition 1487 */ 1488 union dmub_inbox0_cmd_common { 1489 struct { 1490 uint32_t command_code: 8; /**< INBOX0 command code */ 1491 uint32_t param: 24; /**< 24-bit parameter */ 1492 } bits; 1493 uint32_t all; 1494 }; 1495 1496 /** 1497 * INBOX0 hw_lock command definition 1498 */ 1499 union dmub_inbox0_cmd_lock_hw { 1500 struct { 1501 uint32_t command_code: 8; 1502 1503 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1504 uint32_t hw_lock_client: 2; 1505 1506 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1507 uint32_t otg_inst: 3; 1508 uint32_t opp_inst: 3; 1509 uint32_t dig_inst: 3; 1510 1511 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1512 uint32_t lock_pipe: 1; 1513 uint32_t lock_cursor: 1; 1514 uint32_t lock_dig: 1; 1515 uint32_t triple_buffer_lock: 1; 1516 1517 uint32_t lock: 1; /**< Lock */ 1518 uint32_t should_release: 1; /**< Release */ 1519 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1520 } bits; 1521 uint32_t all; 1522 }; 1523 1524 union dmub_inbox0_data_register { 1525 union dmub_inbox0_cmd_common inbox0_cmd_common; 1526 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1527 }; 1528 1529 enum dmub_inbox0_command { 1530 /** 1531 * DESC: Invalid command, ignored. 1532 */ 1533 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1534 /** 1535 * DESC: Notification to acquire/release HW lock 1536 * ARGS: 1537 */ 1538 DMUB_INBOX0_CMD__HW_LOCK = 1, 1539 }; 1540 //============================================================================== 1541 //</DMUB_GPINT>================================================================= 1542 //============================================================================== 1543 //< DMUB_CMD>=================================================================== 1544 //============================================================================== 1545 1546 /** 1547 * Size in bytes of each DMUB command. 1548 */ 1549 #define DMUB_RB_CMD_SIZE 64 1550 1551 /** 1552 * Maximum number of items in the DMUB ringbuffer. 1553 */ 1554 #define DMUB_RB_MAX_ENTRY 128 1555 1556 /** 1557 * Ringbuffer size in bytes. 1558 */ 1559 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1560 1561 /** 1562 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1563 */ 1564 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1565 1566 /** 1567 * Ringbuffer size in bytes. 1568 */ 1569 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1570 1571 /** 1572 * REG_SET mask for reg offload. 1573 */ 1574 #define REG_SET_MASK 0xFFFF 1575 1576 /* 1577 * enum dmub_cmd_type - DMUB inbox command. 1578 * 1579 * Command IDs should be treated as stable ABI. 1580 * Do not reuse or modify IDs. 1581 */ 1582 enum dmub_cmd_type { 1583 /** 1584 * Invalid command. 1585 */ 1586 DMUB_CMD__NULL = 0, 1587 /** 1588 * Read modify write register sequence offload. 1589 */ 1590 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1591 /** 1592 * Field update register sequence offload. 1593 */ 1594 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1595 /** 1596 * Burst write sequence offload. 1597 */ 1598 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1599 /** 1600 * Reg wait sequence offload. 1601 */ 1602 DMUB_CMD__REG_REG_WAIT = 4, 1603 /** 1604 * Workaround to avoid HUBP underflow during NV12 playback. 1605 */ 1606 DMUB_CMD__PLAT_54186_WA = 5, 1607 /** 1608 * Command type used to query FW feature caps. 1609 */ 1610 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1611 /** 1612 * Command type used to get visual confirm color. 1613 */ 1614 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1615 /** 1616 * Command type used for all PSR commands. 1617 */ 1618 DMUB_CMD__PSR = 64, 1619 /** 1620 * Command type used for all MALL commands. 1621 */ 1622 DMUB_CMD__MALL = 65, 1623 /** 1624 * Command type used for all ABM commands. 1625 */ 1626 DMUB_CMD__ABM = 66, 1627 /** 1628 * Command type used to update dirty rects in FW. 1629 */ 1630 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1631 /** 1632 * Command type used to update cursor info in FW. 1633 */ 1634 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1635 /** 1636 * Command type used for HW locking in FW. 1637 */ 1638 DMUB_CMD__HW_LOCK = 69, 1639 /** 1640 * Command type used to access DP AUX. 1641 */ 1642 DMUB_CMD__DP_AUX_ACCESS = 70, 1643 /** 1644 * Command type used for OUTBOX1 notification enable 1645 */ 1646 DMUB_CMD__OUTBOX1_ENABLE = 71, 1647 1648 /** 1649 * Command type used for all idle optimization commands. 1650 */ 1651 DMUB_CMD__IDLE_OPT = 72, 1652 /** 1653 * Command type used for all clock manager commands. 1654 */ 1655 DMUB_CMD__CLK_MGR = 73, 1656 /** 1657 * Command type used for all panel control commands. 1658 */ 1659 DMUB_CMD__PANEL_CNTL = 74, 1660 1661 /** 1662 * Command type used for all CAB commands. 1663 */ 1664 DMUB_CMD__CAB_FOR_SS = 75, 1665 1666 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1667 1668 /** 1669 * Command type used for interfacing with DPIA. 1670 */ 1671 DMUB_CMD__DPIA = 77, 1672 /** 1673 * Command type used for EDID CEA parsing 1674 */ 1675 DMUB_CMD__EDID_CEA = 79, 1676 /** 1677 * Command type used for getting usbc cable ID 1678 */ 1679 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1680 /** 1681 * Command type used to query HPD state. 1682 */ 1683 DMUB_CMD__QUERY_HPD_STATE = 82, 1684 /** 1685 * Command type used for all VBIOS interface commands. 1686 */ 1687 /** 1688 * Command type used for all REPLAY commands. 1689 */ 1690 DMUB_CMD__REPLAY = 83, 1691 1692 /** 1693 * Command type used for all SECURE_DISPLAY commands. 1694 */ 1695 DMUB_CMD__SECURE_DISPLAY = 85, 1696 1697 /** 1698 * Command type used to set DPIA HPD interrupt state 1699 */ 1700 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1701 1702 /** 1703 * Command type used for all PSP commands. 1704 */ 1705 DMUB_CMD__PSP = 88, 1706 1707 /** 1708 * Command type used for all Fused IO commands. 1709 */ 1710 DMUB_CMD__FUSED_IO = 89, 1711 1712 /** 1713 * Command type used for all LSDMA commands. 1714 */ 1715 DMUB_CMD__LSDMA = 90, 1716 1717 /** 1718 * Command type use for all IPS commands. 1719 */ 1720 DMUB_CMD__IPS = 91, 1721 1722 /** 1723 * Command type use for Cursor offload. 1724 */ 1725 DMUB_CMD__CURSOR_OFFLOAD = 92, 1726 1727 /** 1728 * Command type used for all SMART_POWER_HDR commands. 1729 */ 1730 DMUB_CMD__SMART_POWER_HDR = 93, 1731 1732 /** 1733 * Command type use for VBIOS shared commands. 1734 */ 1735 DMUB_CMD__VBIOS = 128, 1736 }; 1737 1738 /** 1739 * enum dmub_out_cmd_type - DMUB outbox commands. 1740 */ 1741 enum dmub_out_cmd_type { 1742 /** 1743 * Invalid outbox command, ignored. 1744 */ 1745 DMUB_OUT_CMD__NULL = 0, 1746 /** 1747 * Command type used for DP AUX Reply data notification 1748 */ 1749 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1750 /** 1751 * Command type used for DP HPD event notification 1752 */ 1753 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1754 /** 1755 * Command type used for SET_CONFIG Reply notification 1756 */ 1757 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1758 /** 1759 * Command type used for USB4 DPIA notification 1760 */ 1761 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1762 /** 1763 * Command type used for HPD redetect notification 1764 */ 1765 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1766 /** 1767 * Command type used for Fused IO notification 1768 */ 1769 DMUB_OUT_CMD__FUSED_IO = 7, 1770 }; 1771 1772 /* DMUB_CMD__DPIA command sub-types. */ 1773 enum dmub_cmd_dpia_type { 1774 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1775 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1776 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1777 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1778 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1779 }; 1780 1781 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1782 enum dmub_cmd_dpia_notification_type { 1783 DPIA_NOTIFY__BW_ALLOCATION = 0, 1784 }; 1785 1786 #pragma pack(push, 1) 1787 1788 /** 1789 * struct dmub_cmd_header - Common command header fields. 1790 */ 1791 struct dmub_cmd_header { 1792 unsigned int type : 8; /**< command type */ 1793 unsigned int sub_type : 8; /**< command sub type */ 1794 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1795 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1796 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1797 unsigned int reserved0 : 5; /**< reserved bits */ 1798 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1799 unsigned int reserved1 : 2; /**< reserved bits */ 1800 }; 1801 1802 /* 1803 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1804 * 1805 * 60 payload bytes can hold up to 5 sets of read modify writes, 1806 * each take 3 dwords. 1807 * 1808 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1809 * 1810 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1811 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1812 */ 1813 struct dmub_cmd_read_modify_write_sequence { 1814 uint32_t addr; /**< register address */ 1815 uint32_t modify_mask; /**< modify mask */ 1816 uint32_t modify_value; /**< modify value */ 1817 }; 1818 1819 /** 1820 * Maximum number of ops in read modify write sequence. 1821 */ 1822 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1823 1824 /** 1825 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1826 */ 1827 struct dmub_rb_cmd_read_modify_write { 1828 struct dmub_cmd_header header; /**< command header */ 1829 /** 1830 * Read modify write sequence. 1831 */ 1832 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1833 }; 1834 1835 /* 1836 * Update a register with specified masks and values sequeunce 1837 * 1838 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1839 * 1840 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1841 * 1842 * 1843 * USE CASE: 1844 * 1. auto-increment register where additional read would update pointer and produce wrong result 1845 * 2. toggle a bit without read in the middle 1846 */ 1847 1848 struct dmub_cmd_reg_field_update_sequence { 1849 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1850 uint32_t modify_value; /**< value to update with */ 1851 }; 1852 1853 /** 1854 * Maximum number of ops in field update sequence. 1855 */ 1856 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1857 1858 /** 1859 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1860 */ 1861 struct dmub_rb_cmd_reg_field_update_sequence { 1862 struct dmub_cmd_header header; /**< command header */ 1863 uint32_t addr; /**< register address */ 1864 /** 1865 * Field update sequence. 1866 */ 1867 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1868 }; 1869 1870 1871 /** 1872 * Maximum number of burst write values. 1873 */ 1874 #define DMUB_BURST_WRITE_VALUES__MAX 14 1875 1876 /* 1877 * struct dmub_rb_cmd_burst_write - Burst write 1878 * 1879 * support use case such as writing out LUTs. 1880 * 1881 * 60 payload bytes can hold up to 14 values to write to given address 1882 * 1883 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1884 */ 1885 struct dmub_rb_cmd_burst_write { 1886 struct dmub_cmd_header header; /**< command header */ 1887 uint32_t addr; /**< register start address */ 1888 /** 1889 * Burst write register values. 1890 */ 1891 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1892 }; 1893 1894 /** 1895 * struct dmub_rb_cmd_common - Common command header 1896 */ 1897 struct dmub_rb_cmd_common { 1898 struct dmub_cmd_header header; /**< command header */ 1899 /** 1900 * Padding to RB_CMD_SIZE 1901 */ 1902 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1903 }; 1904 1905 /** 1906 * struct dmub_cmd_reg_wait_data - Register wait data 1907 */ 1908 struct dmub_cmd_reg_wait_data { 1909 uint32_t addr; /**< Register address */ 1910 uint32_t mask; /**< Mask for register bits */ 1911 uint32_t condition_field_value; /**< Value to wait for */ 1912 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1913 }; 1914 1915 /** 1916 * struct dmub_rb_cmd_reg_wait - Register wait command 1917 */ 1918 struct dmub_rb_cmd_reg_wait { 1919 struct dmub_cmd_header header; /**< Command header */ 1920 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1921 }; 1922 1923 /** 1924 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1925 * 1926 * Reprograms surface parameters to avoid underflow. 1927 */ 1928 struct dmub_cmd_PLAT_54186_wa { 1929 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1930 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1931 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1932 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1933 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1934 struct { 1935 uint32_t hubp_inst : 4; /**< HUBP instance */ 1936 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1937 uint32_t immediate :1; /**< Immediate flip */ 1938 uint32_t vmid : 4; /**< VMID */ 1939 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1940 uint32_t reserved : 21; /**< Reserved */ 1941 } flip_params; /**< Pageflip parameters */ 1942 uint32_t reserved[9]; /**< Reserved bits */ 1943 }; 1944 1945 /** 1946 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1947 */ 1948 struct dmub_rb_cmd_PLAT_54186_wa { 1949 struct dmub_cmd_header header; /**< Command header */ 1950 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1951 }; 1952 1953 /** 1954 * enum dmub_cmd_mall_type - MALL commands 1955 */ 1956 enum dmub_cmd_mall_type { 1957 /** 1958 * Allows display refresh from MALL. 1959 */ 1960 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1961 /** 1962 * Disallows display refresh from MALL. 1963 */ 1964 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1965 /** 1966 * Cursor copy for MALL. 1967 */ 1968 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1969 /** 1970 * Controls DF requests. 1971 */ 1972 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1973 }; 1974 1975 /** 1976 * struct dmub_rb_cmd_mall - MALL command data. 1977 */ 1978 struct dmub_rb_cmd_mall { 1979 struct dmub_cmd_header header; /**< Common command header */ 1980 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1981 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1982 uint32_t tmr_delay; /**< Timer delay */ 1983 uint32_t tmr_scale; /**< Timer scale */ 1984 uint16_t cursor_width; /**< Cursor width in pixels */ 1985 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1986 uint16_t cursor_height; /**< Cursor height in pixels */ 1987 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1988 uint8_t debug_bits; /**< Debug bits */ 1989 1990 uint8_t reserved1; /**< Reserved bits */ 1991 uint8_t reserved2; /**< Reserved bits */ 1992 }; 1993 1994 /** 1995 * enum dmub_cmd_cab_type - CAB command data. 1996 */ 1997 enum dmub_cmd_cab_type { 1998 /** 1999 * No idle optimizations (i.e. no CAB) 2000 */ 2001 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 2002 /** 2003 * No DCN requests for memory 2004 */ 2005 DMUB_CMD__CAB_NO_DCN_REQ = 1, 2006 /** 2007 * Fit surfaces in CAB (i.e. CAB enable) 2008 */ 2009 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 2010 /** 2011 * Do not fit surfaces in CAB (i.e. no CAB) 2012 */ 2013 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 2014 }; 2015 2016 /** 2017 * struct dmub_rb_cmd_cab - CAB command data. 2018 */ 2019 struct dmub_rb_cmd_cab_for_ss { 2020 struct dmub_cmd_header header; 2021 uint8_t cab_alloc_ways; /* total number of ways */ 2022 uint8_t debug_bits; /* debug bits */ 2023 }; 2024 2025 /** 2026 * Enum for indicating which MCLK switch mode per pipe 2027 */ 2028 enum mclk_switch_mode { 2029 NONE = 0, 2030 FPO = 1, 2031 SUBVP = 2, 2032 VBLANK = 3, 2033 }; 2034 2035 /* Per pipe struct which stores the MCLK switch mode 2036 * data to be sent to DMUB. 2037 * Named "v2" for now -- once FPO and SUBVP are fully merged 2038 * the type name can be updated 2039 */ 2040 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 2041 union { 2042 struct { 2043 uint32_t pix_clk_100hz; 2044 uint16_t main_vblank_start; 2045 uint16_t main_vblank_end; 2046 uint16_t mall_region_lines; 2047 uint16_t prefetch_lines; 2048 uint16_t prefetch_to_mall_start_lines; 2049 uint16_t processing_delay_lines; 2050 uint16_t htotal; // required to calculate line time for multi-display cases 2051 uint16_t vtotal; 2052 uint8_t main_pipe_index; 2053 uint8_t phantom_pipe_index; 2054 /* Since the microschedule is calculated in terms of OTG lines, 2055 * include any scaling factors to make sure when we get accurate 2056 * conversion when programming MALL_START_LINE (which is in terms 2057 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 2058 * is 1/2 (numerator = 1, denominator = 2). 2059 */ 2060 uint8_t scale_factor_numerator; 2061 uint8_t scale_factor_denominator; 2062 uint8_t is_drr; 2063 uint8_t main_split_pipe_index; 2064 uint8_t phantom_split_pipe_index; 2065 } subvp_data; 2066 2067 struct { 2068 uint32_t pix_clk_100hz; 2069 uint16_t vblank_start; 2070 uint16_t vblank_end; 2071 uint16_t vstartup_start; 2072 uint16_t vtotal; 2073 uint16_t htotal; 2074 uint8_t vblank_pipe_index; 2075 uint8_t padding[1]; 2076 struct { 2077 uint8_t drr_in_use; 2078 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 2079 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 2080 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 2081 uint8_t use_ramping; // Use ramping or not 2082 uint8_t drr_vblank_start_margin; 2083 } drr_info; // DRR considered as part of SubVP + VBLANK case 2084 } vblank_data; 2085 } pipe_config; 2086 2087 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 2088 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 2089 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 2090 */ 2091 uint8_t mode; // enum mclk_switch_mode 2092 }; 2093 2094 /** 2095 * Config data for Sub-VP and FPO 2096 * Named "v2" for now -- once FPO and SUBVP are fully merged 2097 * the type name can be updated 2098 */ 2099 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 2100 uint16_t watermark_a_cache; 2101 uint8_t vertical_int_margin_us; 2102 uint8_t pstate_allow_width_us; 2103 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 2104 }; 2105 2106 /** 2107 * DMUB rb command definition for Sub-VP and FPO 2108 * Named "v2" for now -- once FPO and SUBVP are fully merged 2109 * the type name can be updated 2110 */ 2111 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 2112 struct dmub_cmd_header header; 2113 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 2114 }; 2115 2116 struct dmub_flip_addr_info { 2117 uint32_t surf_addr_lo; 2118 uint32_t surf_addr_c_lo; 2119 uint32_t meta_addr_lo; 2120 uint32_t meta_addr_c_lo; 2121 uint16_t surf_addr_hi; 2122 uint16_t surf_addr_c_hi; 2123 uint16_t meta_addr_hi; 2124 uint16_t meta_addr_c_hi; 2125 }; 2126 2127 struct dmub_fams2_flip_info { 2128 union { 2129 struct { 2130 uint8_t is_immediate: 1; 2131 } bits; 2132 uint8_t all; 2133 } config; 2134 uint8_t otg_inst; 2135 uint8_t pipe_mask; 2136 uint8_t pad; 2137 struct dmub_flip_addr_info addr_info; 2138 }; 2139 2140 struct dmub_rb_cmd_fams2_flip { 2141 struct dmub_cmd_header header; 2142 struct dmub_fams2_flip_info flip_info; 2143 }; 2144 2145 struct dmub_cmd_lsdma_data { 2146 union { 2147 struct lsdma_init_data { 2148 union dmub_addr gpu_addr_base; 2149 uint32_t ring_size; 2150 } init_data; 2151 struct lsdma_tiled_copy_data { 2152 uint32_t src_addr_lo; 2153 uint32_t src_addr_hi; 2154 2155 uint32_t dst_addr_lo; 2156 uint32_t dst_addr_hi; 2157 2158 uint32_t src_x : 16; 2159 uint32_t src_y : 16; 2160 2161 uint32_t dst_x : 16; 2162 uint32_t dst_y : 16; 2163 2164 uint32_t src_width : 16; 2165 uint32_t src_height : 16; 2166 2167 uint32_t dst_width : 16; 2168 uint32_t dst_height : 16; 2169 2170 uint32_t rect_x : 16; 2171 uint32_t rect_y : 16; 2172 2173 uint32_t src_swizzle_mode : 5; 2174 uint32_t src_mip_max : 5; 2175 uint32_t src_mip_id : 5; 2176 uint32_t dst_mip_max : 5; 2177 uint32_t dst_swizzle_mode : 5; 2178 uint32_t dst_mip_id : 5; 2179 uint32_t tmz : 1; 2180 uint32_t dcc : 1; 2181 2182 uint32_t data_format : 6; 2183 uint32_t padding1 : 4; 2184 uint32_t dst_element_size : 3; 2185 uint32_t num_type : 3; 2186 uint32_t src_element_size : 3; 2187 uint32_t write_compress : 2; 2188 uint32_t cache_policy_dst : 2; 2189 uint32_t cache_policy_src : 2; 2190 uint32_t read_compress : 2; 2191 uint32_t src_dim : 2; 2192 uint32_t dst_dim : 2; 2193 uint32_t max_uncom : 1; 2194 2195 uint32_t max_com : 2; 2196 uint32_t padding : 30; 2197 } tiled_copy_data; 2198 struct lsdma_linear_copy_data { 2199 uint32_t src_lo; 2200 uint32_t src_hi; 2201 2202 uint32_t dst_lo; 2203 uint32_t dst_hi; 2204 2205 uint32_t count : 30; 2206 uint32_t cache_policy_dst : 2; 2207 2208 uint32_t tmz : 1; 2209 uint32_t cache_policy_src : 2; 2210 uint32_t padding : 29; 2211 } linear_copy_data; 2212 struct lsdma_linear_sub_window_copy_data { 2213 uint32_t src_lo; 2214 uint32_t src_hi; 2215 2216 uint32_t dst_lo; 2217 uint32_t dst_hi; 2218 2219 uint32_t src_x : 16; 2220 uint32_t src_y : 16; 2221 2222 uint32_t dst_x : 16; 2223 uint32_t dst_y : 16; 2224 2225 uint32_t rect_x : 16; 2226 uint32_t rect_y : 16; 2227 2228 uint32_t src_pitch : 16; 2229 uint32_t dst_pitch : 16; 2230 2231 uint32_t src_slice_pitch; 2232 uint32_t dst_slice_pitch; 2233 2234 uint32_t tmz : 1; 2235 uint32_t element_size : 3; 2236 uint32_t src_cache_policy : 3; 2237 uint32_t dst_cache_policy : 3; 2238 uint32_t reserved0 : 22; 2239 } linear_sub_window_copy_data; 2240 struct lsdma_reg_write_data { 2241 uint32_t reg_addr; 2242 uint32_t reg_data; 2243 } reg_write_data; 2244 struct lsdma_pio_copy_data { 2245 uint32_t src_lo; 2246 uint32_t src_hi; 2247 2248 uint32_t dst_lo; 2249 uint32_t dst_hi; 2250 2251 union { 2252 struct { 2253 uint32_t byte_count : 26; 2254 uint32_t src_loc : 1; 2255 uint32_t dst_loc : 1; 2256 uint32_t src_addr_inc : 1; 2257 uint32_t dst_addr_inc : 1; 2258 uint32_t overlap_disable : 1; 2259 uint32_t constant_fill : 1; 2260 } fields; 2261 uint32_t raw; 2262 } packet; 2263 } pio_copy_data; 2264 struct lsdma_pio_constfill_data { 2265 uint32_t dst_lo; 2266 uint32_t dst_hi; 2267 2268 union { 2269 struct { 2270 uint32_t byte_count : 26; 2271 uint32_t src_loc : 1; 2272 uint32_t dst_loc : 1; 2273 uint32_t src_addr_inc : 1; 2274 uint32_t dst_addr_inc : 1; 2275 uint32_t overlap_disable : 1; 2276 uint32_t constant_fill : 1; 2277 } fields; 2278 uint32_t raw; 2279 } packet; 2280 2281 uint32_t data; 2282 } pio_constfill_data; 2283 2284 uint32_t all[14]; 2285 } u; 2286 }; 2287 2288 struct dmub_rb_cmd_lsdma { 2289 struct dmub_cmd_header header; 2290 struct dmub_cmd_lsdma_data lsdma_data; 2291 }; 2292 2293 struct dmub_optc_state_v2 { 2294 uint32_t v_total_min; 2295 uint32_t v_total_max; 2296 uint32_t v_total_mid; 2297 uint32_t v_total_mid_frame_num; 2298 uint8_t program_manual_trigger; 2299 uint8_t tg_inst; 2300 uint8_t pad[2]; 2301 }; 2302 2303 struct dmub_optc_position { 2304 uint32_t vpos; 2305 uint32_t hpos; 2306 uint32_t frame; 2307 }; 2308 2309 struct dmub_rb_cmd_fams2_drr_update { 2310 struct dmub_cmd_header header; 2311 struct dmub_optc_state_v2 dmub_optc_state_req; 2312 }; 2313 2314 /* HW and FW global configuration data for FAMS2 */ 2315 /* FAMS2 types and structs */ 2316 enum fams2_stream_type { 2317 FAMS2_STREAM_TYPE_NONE = 0, 2318 FAMS2_STREAM_TYPE_VBLANK = 1, 2319 FAMS2_STREAM_TYPE_VACTIVE = 2, 2320 FAMS2_STREAM_TYPE_DRR = 3, 2321 FAMS2_STREAM_TYPE_SUBVP = 4, 2322 }; 2323 2324 struct dmub_rect16 { 2325 /** 2326 * Dirty rect x offset. 2327 */ 2328 uint16_t x; 2329 2330 /** 2331 * Dirty rect y offset. 2332 */ 2333 uint16_t y; 2334 2335 /** 2336 * Dirty rect width. 2337 */ 2338 uint16_t width; 2339 2340 /** 2341 * Dirty rect height. 2342 */ 2343 uint16_t height; 2344 }; 2345 2346 /* static stream state */ 2347 struct dmub_fams2_legacy_stream_static_state { 2348 uint8_t vactive_det_fill_delay_otg_vlines; 2349 uint8_t programming_delay_otg_vlines; 2350 }; //v0 2351 2352 struct dmub_fams2_subvp_stream_static_state { 2353 uint16_t vratio_numerator; 2354 uint16_t vratio_denominator; 2355 uint16_t phantom_vtotal; 2356 uint16_t phantom_vactive; 2357 union { 2358 struct { 2359 uint8_t is_multi_planar : 1; 2360 uint8_t is_yuv420 : 1; 2361 } bits; 2362 uint8_t all; 2363 } config; 2364 uint8_t programming_delay_otg_vlines; 2365 uint8_t prefetch_to_mall_otg_vlines; 2366 uint8_t phantom_otg_inst; 2367 uint8_t phantom_pipe_mask; 2368 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2369 }; //v0 2370 2371 struct dmub_fams2_drr_stream_static_state { 2372 uint16_t nom_stretched_vtotal; 2373 uint8_t programming_delay_otg_vlines; 2374 uint8_t only_stretch_if_required; 2375 uint8_t pad[2]; 2376 }; //v0 2377 2378 struct dmub_fams2_cmd_legacy_stream_static_state { 2379 uint16_t vactive_det_fill_delay_otg_vlines; 2380 uint16_t programming_delay_otg_vlines; 2381 }; //v1 2382 2383 struct dmub_fams2_cmd_subvp_stream_static_state { 2384 uint16_t vratio_numerator; 2385 uint16_t vratio_denominator; 2386 uint16_t phantom_vtotal; 2387 uint16_t phantom_vactive; 2388 uint16_t programming_delay_otg_vlines; 2389 uint16_t prefetch_to_mall_otg_vlines; 2390 union { 2391 struct { 2392 uint8_t is_multi_planar : 1; 2393 uint8_t is_yuv420 : 1; 2394 } bits; 2395 uint8_t all; 2396 } config; 2397 uint8_t phantom_otg_inst; 2398 uint8_t phantom_pipe_mask; 2399 uint8_t pad0; 2400 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2401 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2402 }; //v1 2403 2404 struct dmub_fams2_cmd_drr_stream_static_state { 2405 uint16_t nom_stretched_vtotal; 2406 uint16_t programming_delay_otg_vlines; 2407 uint8_t only_stretch_if_required; 2408 uint8_t pad[3]; 2409 }; //v1 2410 2411 union dmub_fams2_stream_static_sub_state { 2412 struct dmub_fams2_legacy_stream_static_state legacy; 2413 struct dmub_fams2_subvp_stream_static_state subvp; 2414 struct dmub_fams2_drr_stream_static_state drr; 2415 }; //v0 2416 2417 union dmub_fams2_cmd_stream_static_sub_state { 2418 COMMON_STREAM_STATIC_SUB_STATE 2419 }; //v1 2420 2421 union dmub_fams2_stream_static_sub_state_v2 { 2422 COMMON_STREAM_STATIC_SUB_STATE 2423 }; //v2 2424 2425 struct dmub_fams2_stream_static_state { 2426 enum fams2_stream_type type; 2427 uint32_t otg_vline_time_ns; 2428 uint32_t otg_vline_time_ticks; 2429 uint16_t htotal; 2430 uint16_t vtotal; // nominal vtotal 2431 uint16_t vblank_start; 2432 uint16_t vblank_end; 2433 uint16_t max_vtotal; 2434 uint16_t allow_start_otg_vline; 2435 uint16_t allow_end_otg_vline; 2436 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2437 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2438 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2439 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2440 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2441 union { 2442 struct { 2443 uint8_t is_drr: 1; // stream is DRR enabled 2444 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2445 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2446 } bits; 2447 uint8_t all; 2448 } config; 2449 uint8_t otg_inst; 2450 uint8_t pipe_mask; // pipe mask for the whole config 2451 uint8_t num_planes; 2452 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2453 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2454 union dmub_fams2_stream_static_sub_state sub_state; 2455 }; //v0 2456 2457 struct dmub_fams2_cmd_stream_static_base_state { 2458 enum fams2_stream_type type; 2459 uint32_t otg_vline_time_ns; 2460 uint32_t otg_vline_time_ticks; 2461 uint16_t htotal; 2462 uint16_t vtotal; // nominal vtotal 2463 uint16_t vblank_start; 2464 uint16_t vblank_end; 2465 uint16_t max_vtotal; 2466 uint16_t allow_start_otg_vline; 2467 uint16_t allow_end_otg_vline; 2468 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2469 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2470 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2471 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2472 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2473 union { 2474 struct { 2475 uint8_t is_drr : 1; // stream is DRR enabled 2476 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2477 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2478 } bits; 2479 uint8_t all; 2480 } config; 2481 uint8_t otg_inst; 2482 uint8_t pipe_mask; // pipe mask for the whole config 2483 uint8_t num_planes; 2484 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2485 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2486 }; //v1 2487 2488 struct dmub_fams2_stream_static_state_v1 { 2489 struct dmub_fams2_cmd_stream_static_base_state base; 2490 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2491 }; //v1 2492 2493 /** 2494 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2495 * p-state request to allow latency 2496 */ 2497 enum dmub_fams2_allow_delay_check_mode { 2498 /* No check for request to allow delay */ 2499 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2500 /* Check for request to allow delay */ 2501 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2502 /* Check for prepare to allow delay */ 2503 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2504 }; 2505 2506 union dmub_fams2_global_feature_config { 2507 struct { 2508 uint32_t enable: 1; 2509 uint32_t enable_ppt_check: 1; 2510 uint32_t enable_stall_recovery: 1; 2511 uint32_t enable_debug: 1; 2512 uint32_t enable_offload_flip: 1; 2513 uint32_t enable_visual_confirm: 1; 2514 uint32_t allow_delay_check_mode: 2; 2515 uint32_t reserved: 24; 2516 } bits; 2517 uint32_t all; 2518 }; 2519 2520 struct dmub_cmd_fams2_global_config { 2521 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2522 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2523 uint32_t num_streams; 2524 union dmub_fams2_global_feature_config features; 2525 uint32_t recovery_timeout_us; 2526 uint32_t hwfq_flip_programming_delay_us; 2527 uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target 2528 }; 2529 2530 union dmub_cmd_fams2_config { 2531 struct dmub_cmd_fams2_global_config global; 2532 struct dmub_fams2_stream_static_state stream; //v0 2533 union { 2534 struct dmub_fams2_cmd_stream_static_base_state base; 2535 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2536 } stream_v1; //v1 2537 }; 2538 2539 struct dmub_fams2_config_v2 { 2540 struct dmub_cmd_fams2_global_config global; 2541 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2542 }; 2543 2544 /** 2545 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2546 */ 2547 struct dmub_rb_cmd_fams2 { 2548 struct dmub_cmd_header header; 2549 union dmub_cmd_fams2_config config; 2550 }; 2551 2552 /** 2553 * Indirect buffer descriptor 2554 */ 2555 struct dmub_ib_data { 2556 union dmub_addr src; // location of indirect buffer in memory 2557 uint16_t size; // indirect buffer size in bytes 2558 }; 2559 2560 /** 2561 * DMUB rb command definition for commands passed over indirect buffer 2562 */ 2563 struct dmub_rb_cmd_ib { 2564 struct dmub_cmd_header header; 2565 struct dmub_ib_data ib_data; 2566 }; 2567 2568 /** 2569 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2570 */ 2571 enum dmub_cmd_idle_opt_type { 2572 /** 2573 * DCN hardware restore. 2574 */ 2575 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2576 2577 /** 2578 * DCN hardware save. 2579 */ 2580 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2581 2582 /** 2583 * DCN hardware notify idle. 2584 */ 2585 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2586 2587 /** 2588 * DCN hardware notify power state. 2589 */ 2590 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2591 2592 /** 2593 * DCN notify to release HW. 2594 */ 2595 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2596 }; 2597 2598 /** 2599 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2600 */ 2601 struct dmub_rb_cmd_idle_opt_dcn_restore { 2602 struct dmub_cmd_header header; /**< header */ 2603 }; 2604 2605 /** 2606 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2607 */ 2608 struct dmub_dcn_notify_idle_cntl_data { 2609 uint8_t driver_idle; 2610 uint8_t skip_otg_disable; 2611 uint8_t reserved[58]; 2612 }; 2613 2614 /** 2615 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2616 */ 2617 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2618 struct dmub_cmd_header header; /**< header */ 2619 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2620 }; 2621 2622 /** 2623 * enum dmub_idle_opt_dc_power_state - DC power states. 2624 */ 2625 enum dmub_idle_opt_dc_power_state { 2626 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2627 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2628 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2629 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2630 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2631 }; 2632 2633 /** 2634 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2635 */ 2636 struct dmub_idle_opt_set_dc_power_state_data { 2637 uint8_t power_state; /**< power state */ 2638 uint8_t pad[3]; /**< padding */ 2639 }; 2640 2641 /** 2642 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2643 */ 2644 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2645 struct dmub_cmd_header header; /**< header */ 2646 struct dmub_idle_opt_set_dc_power_state_data data; 2647 }; 2648 2649 /** 2650 * struct dmub_clocks - Clock update notification. 2651 */ 2652 struct dmub_clocks { 2653 uint32_t dispclk_khz; /**< dispclk kHz */ 2654 uint32_t dppclk_khz; /**< dppclk kHz */ 2655 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2656 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2657 }; 2658 2659 /** 2660 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2661 */ 2662 enum dmub_cmd_clk_mgr_type { 2663 /** 2664 * Notify DMCUB of clock update. 2665 */ 2666 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2667 }; 2668 2669 /** 2670 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2671 */ 2672 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2673 struct dmub_cmd_header header; /**< header */ 2674 struct dmub_clocks clocks; /**< clock data */ 2675 }; 2676 2677 /** 2678 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2679 */ 2680 struct dmub_cmd_digx_encoder_control_data { 2681 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2682 }; 2683 2684 /** 2685 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2686 */ 2687 struct dmub_rb_cmd_digx_encoder_control { 2688 struct dmub_cmd_header header; /**< header */ 2689 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2690 }; 2691 2692 /** 2693 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2694 */ 2695 struct dmub_cmd_set_pixel_clock_data { 2696 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2697 }; 2698 2699 /** 2700 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2701 */ 2702 struct dmub_rb_cmd_set_pixel_clock { 2703 struct dmub_cmd_header header; /**< header */ 2704 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2705 }; 2706 2707 /** 2708 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2709 */ 2710 struct dmub_cmd_enable_disp_power_gating_data { 2711 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2712 }; 2713 2714 /** 2715 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2716 */ 2717 struct dmub_rb_cmd_enable_disp_power_gating { 2718 struct dmub_cmd_header header; /**< header */ 2719 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2720 }; 2721 2722 /** 2723 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2724 */ 2725 struct dmub_dig_transmitter_control_data_v1_7 { 2726 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2727 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2728 union { 2729 uint8_t digmode; /**< enum atom_encode_mode_def */ 2730 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2731 } mode_laneset; 2732 uint8_t lanenum; /**< Number of lanes */ 2733 union { 2734 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2735 } symclk_units; 2736 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2737 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2738 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2739 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2740 uint8_t reserved1; /**< For future use */ 2741 uint8_t skip_phy_ssc_reduction; 2742 uint8_t reserved2[2]; /**< For future use */ 2743 uint32_t reserved3[11]; /**< For future use */ 2744 }; 2745 2746 /** 2747 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2748 */ 2749 union dmub_cmd_dig1_transmitter_control_data { 2750 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2751 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2752 }; 2753 2754 /** 2755 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2756 */ 2757 struct dmub_rb_cmd_dig1_transmitter_control { 2758 struct dmub_cmd_header header; /**< header */ 2759 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2760 }; 2761 2762 /** 2763 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2764 */ 2765 struct dmub_rb_cmd_domain_control_data { 2766 uint8_t inst : 6; /**< DOMAIN instance to control */ 2767 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2768 uint8_t reserved[3]; /**< Reserved for future use */ 2769 }; 2770 2771 /** 2772 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2773 */ 2774 struct dmub_rb_cmd_domain_control { 2775 struct dmub_cmd_header header; /**< header */ 2776 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2777 }; 2778 2779 /** 2780 * DPIA tunnel command parameters. 2781 */ 2782 struct dmub_cmd_dig_dpia_control_data { 2783 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2784 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2785 union { 2786 uint8_t digmode; /** enum atom_encode_mode_def */ 2787 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2788 } mode_laneset; 2789 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2790 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2791 uint8_t hpdsel; /** =0: HPD is not assigned */ 2792 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2793 uint8_t dpia_id; /** Index of DPIA */ 2794 uint8_t fec_rdy : 1; 2795 uint8_t reserved : 7; 2796 uint32_t reserved1; 2797 }; 2798 2799 /** 2800 * DMUB command for DPIA tunnel control. 2801 */ 2802 struct dmub_rb_cmd_dig1_dpia_control { 2803 struct dmub_cmd_header header; 2804 struct dmub_cmd_dig_dpia_control_data dpia_control; 2805 }; 2806 2807 /** 2808 * SET_CONFIG Command Payload (deprecated) 2809 */ 2810 struct set_config_cmd_payload { 2811 uint8_t msg_type; /* set config message type */ 2812 uint8_t msg_data; /* set config message data */ 2813 }; 2814 2815 /** 2816 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2817 */ 2818 struct dmub_cmd_set_config_control_data { 2819 struct set_config_cmd_payload cmd_pkt; 2820 uint8_t instance; /* DPIA instance */ 2821 uint8_t immed_status; /* Immediate status returned in case of error */ 2822 }; 2823 2824 /** 2825 * SET_CONFIG Request Command Payload 2826 */ 2827 struct set_config_request_cmd_payload { 2828 uint8_t instance; /* DPIA instance */ 2829 uint8_t immed_status; /* Immediate status returned in case of error */ 2830 uint8_t msg_type; /* set config message type */ 2831 uint8_t reserved; 2832 uint32_t msg_data; /* set config message data */ 2833 }; 2834 2835 /** 2836 * DMUB command structure for SET_CONFIG command. 2837 */ 2838 struct dmub_rb_cmd_set_config_access { 2839 struct dmub_cmd_header header; /* header */ 2840 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2841 }; 2842 2843 /** 2844 * DMUB command structure for SET_CONFIG request command. 2845 */ 2846 struct dmub_rb_cmd_set_config_request { 2847 struct dmub_cmd_header header; /* header */ 2848 struct set_config_request_cmd_payload payload; /* set config request payload */ 2849 }; 2850 2851 /** 2852 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2853 */ 2854 struct dmub_cmd_mst_alloc_slots_control_data { 2855 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2856 uint8_t instance; /* DPIA instance */ 2857 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2858 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2859 }; 2860 2861 /** 2862 * DMUB command structure for SET_ command. 2863 */ 2864 struct dmub_rb_cmd_set_mst_alloc_slots { 2865 struct dmub_cmd_header header; /* header */ 2866 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2867 }; 2868 2869 /** 2870 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2871 */ 2872 struct dmub_cmd_tps_notification_data { 2873 uint8_t instance; /* DPIA instance */ 2874 uint8_t tps; /* requested training pattern */ 2875 uint8_t reserved1; 2876 uint8_t reserved2; 2877 }; 2878 2879 /** 2880 * DMUB command structure for SET_TPS_NOTIFICATION command. 2881 */ 2882 struct dmub_rb_cmd_set_tps_notification { 2883 struct dmub_cmd_header header; /* header */ 2884 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2885 }; 2886 2887 /** 2888 * DMUB command structure for DPIA HPD int enable control. 2889 */ 2890 struct dmub_rb_cmd_dpia_hpd_int_enable { 2891 struct dmub_cmd_header header; /* header */ 2892 uint32_t enable; /* dpia hpd interrupt enable */ 2893 }; 2894 2895 /** 2896 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2897 */ 2898 struct dmub_rb_cmd_dpphy_init { 2899 struct dmub_cmd_header header; /**< header */ 2900 uint8_t reserved[60]; /**< reserved bits */ 2901 }; 2902 2903 /** 2904 * enum dp_aux_request_action - DP AUX request command listing. 2905 * 2906 * 4 AUX request command bits are shifted to high nibble. 2907 */ 2908 enum dp_aux_request_action { 2909 /** I2C-over-AUX write request */ 2910 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2911 /** I2C-over-AUX read request */ 2912 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2913 /** I2C-over-AUX write status request */ 2914 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2915 /** I2C-over-AUX write request with MOT=1 */ 2916 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2917 /** I2C-over-AUX read request with MOT=1 */ 2918 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2919 /** I2C-over-AUX write status request with MOT=1 */ 2920 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2921 /** Native AUX write request */ 2922 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2923 /** Native AUX read request */ 2924 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2925 }; 2926 2927 /** 2928 * enum aux_return_code_type - DP AUX process return code listing. 2929 */ 2930 enum aux_return_code_type { 2931 /** AUX process succeeded */ 2932 AUX_RET_SUCCESS = 0, 2933 /** AUX process failed with unknown reason */ 2934 AUX_RET_ERROR_UNKNOWN, 2935 /** AUX process completed with invalid reply */ 2936 AUX_RET_ERROR_INVALID_REPLY, 2937 /** AUX process timed out */ 2938 AUX_RET_ERROR_TIMEOUT, 2939 /** HPD was low during AUX process */ 2940 AUX_RET_ERROR_HPD_DISCON, 2941 /** Failed to acquire AUX engine */ 2942 AUX_RET_ERROR_ENGINE_ACQUIRE, 2943 /** AUX request not supported */ 2944 AUX_RET_ERROR_INVALID_OPERATION, 2945 /** AUX process not available */ 2946 AUX_RET_ERROR_PROTOCOL_ERROR, 2947 }; 2948 2949 /** 2950 * enum aux_channel_type - DP AUX channel type listing. 2951 */ 2952 enum aux_channel_type { 2953 /** AUX thru Legacy DP AUX */ 2954 AUX_CHANNEL_LEGACY_DDC, 2955 /** AUX thru DPIA DP tunneling */ 2956 AUX_CHANNEL_DPIA 2957 }; 2958 2959 /** 2960 * struct aux_transaction_parameters - DP AUX request transaction data 2961 */ 2962 struct aux_transaction_parameters { 2963 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2964 uint8_t action; /**< enum dp_aux_request_action */ 2965 uint8_t length; /**< DP AUX request data length */ 2966 uint8_t reserved; /**< For future use */ 2967 uint32_t address; /**< DP AUX address */ 2968 uint8_t data[16]; /**< DP AUX write data */ 2969 }; 2970 2971 /** 2972 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2973 */ 2974 struct dmub_cmd_dp_aux_control_data { 2975 uint8_t instance; /**< AUX instance or DPIA instance */ 2976 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2977 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2978 uint8_t reserved0; /**< For future use */ 2979 uint16_t timeout; /**< timeout time in us */ 2980 uint16_t reserved1; /**< For future use */ 2981 enum aux_channel_type type; /**< enum aux_channel_type */ 2982 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2983 }; 2984 2985 /** 2986 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2987 */ 2988 struct dmub_rb_cmd_dp_aux_access { 2989 /** 2990 * Command header. 2991 */ 2992 struct dmub_cmd_header header; 2993 /** 2994 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2995 */ 2996 struct dmub_cmd_dp_aux_control_data aux_control; 2997 }; 2998 2999 /** 3000 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3001 */ 3002 struct dmub_rb_cmd_outbox1_enable { 3003 /** 3004 * Command header. 3005 */ 3006 struct dmub_cmd_header header; 3007 /** 3008 * enable: 0x0 -> disable outbox1 notification (default value) 3009 * 0x1 -> enable outbox1 notification 3010 */ 3011 uint32_t enable; 3012 }; 3013 3014 /* DP AUX Reply command - OutBox Cmd */ 3015 /** 3016 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3017 */ 3018 struct aux_reply_data { 3019 /** 3020 * Aux cmd 3021 */ 3022 uint8_t command; 3023 /** 3024 * Aux reply data length (max: 16 bytes) 3025 */ 3026 uint8_t length; 3027 /** 3028 * Alignment only 3029 */ 3030 uint8_t pad[2]; 3031 /** 3032 * Aux reply data 3033 */ 3034 uint8_t data[16]; 3035 }; 3036 3037 /** 3038 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3039 */ 3040 struct aux_reply_control_data { 3041 /** 3042 * Reserved for future use 3043 */ 3044 uint32_t handle; 3045 /** 3046 * Aux Instance 3047 */ 3048 uint8_t instance; 3049 /** 3050 * Aux transaction result: definition in enum aux_return_code_type 3051 */ 3052 uint8_t result; 3053 /** 3054 * Alignment only 3055 */ 3056 uint16_t pad; 3057 }; 3058 3059 /** 3060 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 3061 */ 3062 struct dmub_rb_cmd_dp_aux_reply { 3063 /** 3064 * Command header. 3065 */ 3066 struct dmub_cmd_header header; 3067 /** 3068 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3069 */ 3070 struct aux_reply_control_data control; 3071 /** 3072 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3073 */ 3074 struct aux_reply_data reply_data; 3075 }; 3076 3077 /* DP HPD Notify command - OutBox Cmd */ 3078 /** 3079 * DP HPD Type 3080 */ 3081 enum dp_hpd_type { 3082 /** 3083 * Normal DP HPD 3084 */ 3085 DP_HPD = 0, 3086 /** 3087 * DP HPD short pulse 3088 */ 3089 DP_IRQ = 1, 3090 /** 3091 * Failure to acquire DP HPD state 3092 */ 3093 DP_NONE_HPD = 2 3094 }; 3095 3096 /** 3097 * DP HPD Status 3098 */ 3099 enum dp_hpd_status { 3100 /** 3101 * DP_HPD status low 3102 */ 3103 DP_HPD_UNPLUG = 0, 3104 /** 3105 * DP_HPD status high 3106 */ 3107 DP_HPD_PLUG 3108 }; 3109 3110 /** 3111 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3112 */ 3113 struct dp_hpd_data { 3114 /** 3115 * DP HPD instance 3116 */ 3117 uint8_t instance; 3118 /** 3119 * HPD type 3120 */ 3121 uint8_t hpd_type; 3122 /** 3123 * HPD status: only for type: DP_HPD to indicate status 3124 */ 3125 uint8_t hpd_status; 3126 /** 3127 * Alignment only 3128 */ 3129 uint8_t pad; 3130 }; 3131 3132 /** 3133 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3134 */ 3135 struct dmub_rb_cmd_dp_hpd_notify { 3136 /** 3137 * Command header. 3138 */ 3139 struct dmub_cmd_header header; 3140 /** 3141 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3142 */ 3143 struct dp_hpd_data hpd_data; 3144 }; 3145 3146 /** 3147 * Definition of a SET_CONFIG reply from DPOA. 3148 */ 3149 enum set_config_status { 3150 SET_CONFIG_PENDING = 0, 3151 SET_CONFIG_ACK_RECEIVED, 3152 SET_CONFIG_RX_TIMEOUT, 3153 SET_CONFIG_UNKNOWN_ERROR, 3154 }; 3155 3156 /** 3157 * Definition of a set_config reply 3158 */ 3159 struct set_config_reply_control_data { 3160 uint8_t instance; /* DPIA Instance */ 3161 uint8_t status; /* Set Config reply */ 3162 uint16_t pad; /* Alignment */ 3163 }; 3164 3165 /** 3166 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 3167 */ 3168 struct dmub_rb_cmd_dp_set_config_reply { 3169 struct dmub_cmd_header header; 3170 struct set_config_reply_control_data set_config_reply_control; 3171 }; 3172 3173 /** 3174 * Definition of a DPIA notification header 3175 */ 3176 struct dpia_notification_header { 3177 uint8_t instance; /**< DPIA Instance */ 3178 uint8_t reserved[3]; 3179 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 3180 }; 3181 3182 /** 3183 * Definition of the common data struct of DPIA notification 3184 */ 3185 struct dpia_notification_common { 3186 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 3187 - sizeof(struct dpia_notification_header)]; 3188 }; 3189 3190 /** 3191 * Definition of a DPIA notification data 3192 */ 3193 struct dpia_bw_allocation_notify_data { 3194 union { 3195 struct { 3196 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3197 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3198 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3199 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3200 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3201 uint16_t reserved: 11; /**< Reserved */ 3202 } bits; 3203 3204 uint16_t flags; 3205 }; 3206 3207 uint8_t cm_id; /**< CM ID */ 3208 uint8_t group_id; /**< Group ID */ 3209 uint8_t granularity; /**< BW Allocation Granularity */ 3210 uint8_t estimated_bw; /**< Estimated_BW */ 3211 uint8_t allocated_bw; /**< Allocated_BW */ 3212 uint8_t reserved; 3213 }; 3214 3215 /** 3216 * union dpia_notify_data_type - DPIA Notification in Outbox command 3217 */ 3218 union dpia_notification_data { 3219 /** 3220 * DPIA Notification for common data struct 3221 */ 3222 struct dpia_notification_common common_data; 3223 3224 /** 3225 * DPIA Notification for DP BW Allocation support 3226 */ 3227 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3228 }; 3229 3230 /** 3231 * Definition of a DPIA notification payload 3232 */ 3233 struct dpia_notification_payload { 3234 struct dpia_notification_header header; 3235 union dpia_notification_data data; /**< DPIA notification payload data */ 3236 }; 3237 3238 /** 3239 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3240 */ 3241 struct dmub_rb_cmd_dpia_notification { 3242 struct dmub_cmd_header header; /**< DPIA notification header */ 3243 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3244 }; 3245 3246 /** 3247 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3248 */ 3249 struct dmub_cmd_hpd_state_query_data { 3250 uint8_t instance; /**< HPD instance or DPIA instance */ 3251 uint8_t result; /**< For returning HPD state */ 3252 uint16_t pad; /** < Alignment */ 3253 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3254 enum aux_return_code_type status; /**< for returning the status of command */ 3255 }; 3256 3257 /** 3258 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3259 */ 3260 struct dmub_rb_cmd_query_hpd_state { 3261 /** 3262 * Command header. 3263 */ 3264 struct dmub_cmd_header header; 3265 /** 3266 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3267 */ 3268 struct dmub_cmd_hpd_state_query_data data; 3269 }; 3270 3271 /** 3272 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3273 */ 3274 struct dmub_rb_cmd_hpd_sense_notify_data { 3275 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3276 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3277 }; 3278 3279 /** 3280 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3281 */ 3282 struct dmub_rb_cmd_hpd_sense_notify { 3283 struct dmub_cmd_header header; /**< header */ 3284 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3285 }; 3286 3287 /* 3288 * Command IDs should be treated as stable ABI. 3289 * Do not reuse or modify IDs. 3290 */ 3291 3292 /** 3293 * PSR command sub-types. 3294 */ 3295 enum dmub_cmd_psr_type { 3296 /** 3297 * Set PSR version support. 3298 */ 3299 DMUB_CMD__PSR_SET_VERSION = 0, 3300 /** 3301 * Copy driver-calculated parameters to PSR state. 3302 */ 3303 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3304 /** 3305 * Enable PSR. 3306 */ 3307 DMUB_CMD__PSR_ENABLE = 2, 3308 3309 /** 3310 * Disable PSR. 3311 */ 3312 DMUB_CMD__PSR_DISABLE = 3, 3313 3314 /** 3315 * Set PSR level. 3316 * PSR level is a 16-bit value dicated by driver that 3317 * will enable/disable different functionality. 3318 */ 3319 DMUB_CMD__PSR_SET_LEVEL = 4, 3320 3321 /** 3322 * Forces PSR enabled until an explicit PSR disable call. 3323 */ 3324 DMUB_CMD__PSR_FORCE_STATIC = 5, 3325 /** 3326 * Set vtotal in psr active for FreeSync PSR. 3327 */ 3328 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3329 /** 3330 * Set PSR power option 3331 */ 3332 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3333 }; 3334 3335 /** 3336 * Different PSR residency modes. 3337 * Different modes change the definition of PSR residency. 3338 */ 3339 enum psr_residency_mode { 3340 PSR_RESIDENCY_MODE_PHY = 0, 3341 PSR_RESIDENCY_MODE_ALPM, 3342 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3343 /* Do not add below. */ 3344 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3345 }; 3346 3347 enum dmub_cmd_fams_type { 3348 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3349 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3350 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3351 /** 3352 * For SubVP set manual trigger in FW because it 3353 * triggers DRR_UPDATE_PENDING which SubVP relies 3354 * on (for any SubVP cases that use a DRR display) 3355 */ 3356 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3357 DMUB_CMD__FAMS2_CONFIG = 4, 3358 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3359 DMUB_CMD__FAMS2_FLIP = 6, 3360 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3361 }; 3362 3363 /** 3364 * PSR versions. 3365 */ 3366 enum psr_version { 3367 /** 3368 * PSR version 1. 3369 */ 3370 PSR_VERSION_1 = 0, 3371 /** 3372 * Freesync PSR SU. 3373 */ 3374 PSR_VERSION_SU_1 = 1, 3375 /** 3376 * PSR not supported. 3377 */ 3378 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3379 }; 3380 3381 /** 3382 * PHY Link rate for DP. 3383 */ 3384 enum phy_link_rate { 3385 /** 3386 * not supported. 3387 */ 3388 PHY_RATE_UNKNOWN = 0, 3389 /** 3390 * Rate_1 (RBR) - 1.62 Gbps/Lane 3391 */ 3392 PHY_RATE_162 = 1, 3393 /** 3394 * Rate_2 - 2.16 Gbps/Lane 3395 */ 3396 PHY_RATE_216 = 2, 3397 /** 3398 * Rate_3 - 2.43 Gbps/Lane 3399 */ 3400 PHY_RATE_243 = 3, 3401 /** 3402 * Rate_4 (HBR) - 2.70 Gbps/Lane 3403 */ 3404 PHY_RATE_270 = 4, 3405 /** 3406 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3407 */ 3408 PHY_RATE_324 = 5, 3409 /** 3410 * Rate_6 - 4.32 Gbps/Lane 3411 */ 3412 PHY_RATE_432 = 6, 3413 /** 3414 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3415 */ 3416 PHY_RATE_540 = 7, 3417 /** 3418 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3419 */ 3420 PHY_RATE_810 = 8, 3421 /** 3422 * UHBR10 - 10.0 Gbps/Lane 3423 */ 3424 PHY_RATE_1000 = 9, 3425 /** 3426 * UHBR13.5 - 13.5 Gbps/Lane 3427 */ 3428 PHY_RATE_1350 = 10, 3429 /** 3430 * UHBR10 - 20.0 Gbps/Lane 3431 */ 3432 PHY_RATE_2000 = 11, 3433 3434 PHY_RATE_675 = 12, 3435 /** 3436 * Rate 12 - 6.75 Gbps/Lane 3437 */ 3438 }; 3439 3440 /** 3441 * enum dmub_phy_fsm_state - PHY FSM states. 3442 * PHY FSM state to transit to during PSR enable/disable. 3443 */ 3444 enum dmub_phy_fsm_state { 3445 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3446 DMUB_PHY_FSM_RESET, 3447 DMUB_PHY_FSM_RESET_RELEASED, 3448 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3449 DMUB_PHY_FSM_INITIALIZED, 3450 DMUB_PHY_FSM_CALIBRATED, 3451 DMUB_PHY_FSM_CALIBRATED_LP, 3452 DMUB_PHY_FSM_CALIBRATED_PG, 3453 DMUB_PHY_FSM_POWER_DOWN, 3454 DMUB_PHY_FSM_PLL_EN, 3455 DMUB_PHY_FSM_TX_EN, 3456 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3457 DMUB_PHY_FSM_FAST_LP, 3458 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3459 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3460 DMUB_PHY_FSM_P2_PLL_OFF, 3461 DMUB_PHY_FSM_P2_PLL_ON, 3462 }; 3463 3464 /** 3465 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3466 */ 3467 struct dmub_cmd_psr_copy_settings_data { 3468 /** 3469 * Flags that can be set by driver to change some PSR behaviour. 3470 */ 3471 union dmub_psr_debug_flags debug; 3472 /** 3473 * 16-bit value dicated by driver that will enable/disable different functionality. 3474 */ 3475 uint16_t psr_level; 3476 /** 3477 * DPP HW instance. 3478 */ 3479 uint8_t dpp_inst; 3480 /** 3481 * MPCC HW instance. 3482 * Not used in dmub fw, 3483 * dmub fw will get active opp by reading odm registers. 3484 */ 3485 uint8_t mpcc_inst; 3486 /** 3487 * OPP HW instance. 3488 * Not used in dmub fw, 3489 * dmub fw will get active opp by reading odm registers. 3490 */ 3491 uint8_t opp_inst; 3492 /** 3493 * OTG HW instance. 3494 */ 3495 uint8_t otg_inst; 3496 /** 3497 * DIG FE HW instance. 3498 */ 3499 uint8_t digfe_inst; 3500 /** 3501 * DIG BE HW instance. 3502 */ 3503 uint8_t digbe_inst; 3504 /** 3505 * DP PHY HW instance. 3506 */ 3507 uint8_t dpphy_inst; 3508 /** 3509 * AUX HW instance. 3510 */ 3511 uint8_t aux_inst; 3512 /** 3513 * Determines if SMU optimzations are enabled/disabled. 3514 */ 3515 uint8_t smu_optimizations_en; 3516 /** 3517 * Unused. 3518 * TODO: Remove. 3519 */ 3520 uint8_t frame_delay; 3521 /** 3522 * If RFB setup time is greater than the total VBLANK time, 3523 * it is not possible for the sink to capture the video frame 3524 * in the same frame the SDP is sent. In this case, 3525 * the frame capture indication bit should be set and an extra 3526 * static frame should be transmitted to the sink. 3527 */ 3528 uint8_t frame_cap_ind; 3529 /** 3530 * Granularity of Y offset supported by sink. 3531 */ 3532 uint8_t su_y_granularity; 3533 /** 3534 * Indicates whether sink should start capturing 3535 * immediately following active scan line, 3536 * or starting with the 2nd active scan line. 3537 */ 3538 uint8_t line_capture_indication; 3539 /** 3540 * Multi-display optimizations are implemented on certain ASICs. 3541 */ 3542 uint8_t multi_disp_optimizations_en; 3543 /** 3544 * The last possible line SDP may be transmitted without violating 3545 * the RFB setup time or entering the active video frame. 3546 */ 3547 uint16_t init_sdp_deadline; 3548 /** 3549 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3550 */ 3551 uint8_t rate_control_caps ; 3552 /* 3553 * Force PSRSU always doing full frame update 3554 */ 3555 uint8_t force_ffu_mode; 3556 /** 3557 * Length of each horizontal line in us. 3558 */ 3559 uint32_t line_time_in_us; 3560 /** 3561 * FEC enable status in driver 3562 */ 3563 uint8_t fec_enable_status; 3564 /** 3565 * FEC re-enable delay when PSR exit. 3566 * unit is 100us, range form 0~255(0xFF). 3567 */ 3568 uint8_t fec_enable_delay_in100us; 3569 /** 3570 * PSR control version. 3571 */ 3572 uint8_t cmd_version; 3573 /** 3574 * Panel Instance. 3575 * Panel instance to identify which psr_state to use 3576 * Currently the support is only for 0 or 1 3577 */ 3578 uint8_t panel_inst; 3579 /* 3580 * DSC enable status in driver 3581 */ 3582 uint8_t dsc_enable_status; 3583 /* 3584 * Use FSM state for PSR power up/down 3585 */ 3586 uint8_t use_phy_fsm; 3587 /** 3588 * frame delay for frame re-lock 3589 */ 3590 uint8_t relock_delay_frame_cnt; 3591 /** 3592 * esd recovery indicate. 3593 */ 3594 uint8_t esd_recovery; 3595 /** 3596 * DSC Slice height. 3597 */ 3598 uint16_t dsc_slice_height; 3599 /** 3600 * Some panels request main link off before xth vertical line 3601 */ 3602 uint16_t poweroff_before_vertical_line; 3603 /** 3604 * Some panels cannot handle idle pattern during PSR entry. 3605 * To power down phy before disable stream to avoid sending 3606 * idle pattern. 3607 */ 3608 uint8_t power_down_phy_before_disable_stream; 3609 }; 3610 3611 /** 3612 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3613 */ 3614 struct dmub_rb_cmd_psr_copy_settings { 3615 /** 3616 * Command header. 3617 */ 3618 struct dmub_cmd_header header; 3619 /** 3620 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3621 */ 3622 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3623 }; 3624 3625 /** 3626 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3627 */ 3628 struct dmub_cmd_psr_set_level_data { 3629 /** 3630 * 16-bit value dicated by driver that will enable/disable different functionality. 3631 */ 3632 uint16_t psr_level; 3633 /** 3634 * PSR control version. 3635 */ 3636 uint8_t cmd_version; 3637 /** 3638 * Panel Instance. 3639 * Panel instance to identify which psr_state to use 3640 * Currently the support is only for 0 or 1 3641 */ 3642 uint8_t panel_inst; 3643 }; 3644 3645 /** 3646 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3647 */ 3648 struct dmub_rb_cmd_psr_set_level { 3649 /** 3650 * Command header. 3651 */ 3652 struct dmub_cmd_header header; 3653 /** 3654 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3655 */ 3656 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3657 }; 3658 3659 struct dmub_rb_cmd_psr_enable_data { 3660 /** 3661 * PSR control version. 3662 */ 3663 uint8_t cmd_version; 3664 /** 3665 * Panel Instance. 3666 * Panel instance to identify which psr_state to use 3667 * Currently the support is only for 0 or 1 3668 */ 3669 uint8_t panel_inst; 3670 /** 3671 * Phy state to enter. 3672 * Values to use are defined in dmub_phy_fsm_state 3673 */ 3674 uint8_t phy_fsm_state; 3675 /** 3676 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3677 * Set this using enum phy_link_rate. 3678 * This does not support HDMI/DP2 for now. 3679 */ 3680 uint8_t phy_rate; 3681 }; 3682 3683 /** 3684 * Definition of a DMUB_CMD__PSR_ENABLE command. 3685 * PSR enable/disable is controlled using the sub_type. 3686 */ 3687 struct dmub_rb_cmd_psr_enable { 3688 /** 3689 * Command header. 3690 */ 3691 struct dmub_cmd_header header; 3692 3693 struct dmub_rb_cmd_psr_enable_data data; 3694 }; 3695 3696 /** 3697 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3698 */ 3699 struct dmub_cmd_psr_set_version_data { 3700 /** 3701 * PSR version that FW should implement. 3702 */ 3703 enum psr_version version; 3704 /** 3705 * PSR control version. 3706 */ 3707 uint8_t cmd_version; 3708 /** 3709 * Panel Instance. 3710 * Panel instance to identify which psr_state to use 3711 * Currently the support is only for 0 or 1 3712 */ 3713 uint8_t panel_inst; 3714 /** 3715 * Explicit padding to 4 byte boundary. 3716 */ 3717 uint8_t pad[2]; 3718 }; 3719 3720 /** 3721 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3722 */ 3723 struct dmub_rb_cmd_psr_set_version { 3724 /** 3725 * Command header. 3726 */ 3727 struct dmub_cmd_header header; 3728 /** 3729 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3730 */ 3731 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3732 }; 3733 3734 struct dmub_cmd_psr_force_static_data { 3735 /** 3736 * PSR control version. 3737 */ 3738 uint8_t cmd_version; 3739 /** 3740 * Panel Instance. 3741 * Panel instance to identify which psr_state to use 3742 * Currently the support is only for 0 or 1 3743 */ 3744 uint8_t panel_inst; 3745 /** 3746 * Explicit padding to 4 byte boundary. 3747 */ 3748 uint8_t pad[2]; 3749 }; 3750 3751 /** 3752 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3753 */ 3754 struct dmub_rb_cmd_psr_force_static { 3755 /** 3756 * Command header. 3757 */ 3758 struct dmub_cmd_header header; 3759 /** 3760 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3761 */ 3762 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3763 }; 3764 3765 /** 3766 * PSR SU debug flags. 3767 */ 3768 union dmub_psr_su_debug_flags { 3769 /** 3770 * PSR SU debug flags. 3771 */ 3772 struct { 3773 /** 3774 * Update dirty rect in SW only. 3775 */ 3776 uint8_t update_dirty_rect_only : 1; 3777 /** 3778 * Reset the cursor/plane state before processing the call. 3779 */ 3780 uint8_t reset_state : 1; 3781 } bitfields; 3782 3783 /** 3784 * Union for debug flags. 3785 */ 3786 uint32_t u32All; 3787 }; 3788 3789 /** 3790 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3791 * This triggers a selective update for PSR SU. 3792 */ 3793 struct dmub_cmd_update_dirty_rect_data { 3794 /** 3795 * Dirty rects from OS. 3796 */ 3797 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3798 /** 3799 * PSR SU debug flags. 3800 */ 3801 union dmub_psr_su_debug_flags debug_flags; 3802 /** 3803 * OTG HW instance. 3804 */ 3805 uint8_t pipe_idx; 3806 /** 3807 * Number of dirty rects. 3808 */ 3809 uint8_t dirty_rect_count; 3810 /** 3811 * PSR control version. 3812 */ 3813 uint8_t cmd_version; 3814 /** 3815 * Panel Instance. 3816 * Panel instance to identify which psr_state to use 3817 * Currently the support is only for 0 or 1 3818 */ 3819 uint8_t panel_inst; 3820 }; 3821 3822 /** 3823 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3824 */ 3825 struct dmub_rb_cmd_update_dirty_rect { 3826 /** 3827 * Command header. 3828 */ 3829 struct dmub_cmd_header header; 3830 /** 3831 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3832 */ 3833 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3834 }; 3835 3836 /** 3837 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3838 */ 3839 union dmub_reg_cursor_control_cfg { 3840 struct { 3841 uint32_t cur_enable: 1; 3842 uint32_t reser0: 3; 3843 uint32_t cur_2x_magnify: 1; 3844 uint32_t reser1: 3; 3845 uint32_t mode: 3; 3846 uint32_t reser2: 5; 3847 uint32_t pitch: 2; 3848 uint32_t reser3: 6; 3849 uint32_t line_per_chunk: 5; 3850 uint32_t reser4: 3; 3851 } bits; 3852 uint32_t raw; 3853 }; 3854 struct dmub_cursor_position_cache_hubp { 3855 union dmub_reg_cursor_control_cfg cur_ctl; 3856 union dmub_reg_position_cfg { 3857 struct { 3858 uint32_t cur_x_pos: 16; 3859 uint32_t cur_y_pos: 16; 3860 } bits; 3861 uint32_t raw; 3862 } position; 3863 union dmub_reg_hot_spot_cfg { 3864 struct { 3865 uint32_t hot_x: 16; 3866 uint32_t hot_y: 16; 3867 } bits; 3868 uint32_t raw; 3869 } hot_spot; 3870 union dmub_reg_dst_offset_cfg { 3871 struct { 3872 uint32_t dst_x_offset: 13; 3873 uint32_t reserved: 19; 3874 } bits; 3875 uint32_t raw; 3876 } dst_offset; 3877 }; 3878 3879 union dmub_reg_cur0_control_cfg { 3880 struct { 3881 uint32_t cur0_enable: 1; 3882 uint32_t expansion_mode: 1; 3883 uint32_t reser0: 1; 3884 uint32_t cur0_rom_en: 1; 3885 uint32_t mode: 3; 3886 uint32_t reserved: 25; 3887 } bits; 3888 uint32_t raw; 3889 }; 3890 struct dmub_cursor_position_cache_dpp { 3891 union dmub_reg_cur0_control_cfg cur0_ctl; 3892 }; 3893 struct dmub_cursor_position_cfg { 3894 struct dmub_cursor_position_cache_hubp pHubp; 3895 struct dmub_cursor_position_cache_dpp pDpp; 3896 uint8_t pipe_idx; 3897 /* 3898 * Padding is required. To be 4 Bytes Aligned. 3899 */ 3900 uint8_t padding[3]; 3901 }; 3902 3903 struct dmub_cursor_attribute_cache_hubp { 3904 uint32_t SURFACE_ADDR_HIGH; 3905 uint32_t SURFACE_ADDR; 3906 union dmub_reg_cursor_control_cfg cur_ctl; 3907 union dmub_reg_cursor_size_cfg { 3908 struct { 3909 uint32_t width: 16; 3910 uint32_t height: 16; 3911 } bits; 3912 uint32_t raw; 3913 } size; 3914 union dmub_reg_cursor_settings_cfg { 3915 struct { 3916 uint32_t dst_y_offset: 8; 3917 uint32_t chunk_hdl_adjust: 2; 3918 uint32_t reserved: 22; 3919 } bits; 3920 uint32_t raw; 3921 } settings; 3922 }; 3923 struct dmub_cursor_attribute_cache_dpp { 3924 union dmub_reg_cur0_control_cfg cur0_ctl; 3925 }; 3926 struct dmub_cursor_attributes_cfg { 3927 struct dmub_cursor_attribute_cache_hubp aHubp; 3928 struct dmub_cursor_attribute_cache_dpp aDpp; 3929 }; 3930 3931 struct dmub_cmd_update_cursor_payload0 { 3932 /** 3933 * Cursor dirty rects. 3934 */ 3935 struct dmub_rect cursor_rect; 3936 /** 3937 * PSR SU debug flags. 3938 */ 3939 union dmub_psr_su_debug_flags debug_flags; 3940 /** 3941 * Cursor enable/disable. 3942 */ 3943 uint8_t enable; 3944 /** 3945 * OTG HW instance. 3946 */ 3947 uint8_t pipe_idx; 3948 /** 3949 * PSR control version. 3950 */ 3951 uint8_t cmd_version; 3952 /** 3953 * Panel Instance. 3954 * Panel instance to identify which psr_state to use 3955 * Currently the support is only for 0 or 1 3956 */ 3957 uint8_t panel_inst; 3958 /** 3959 * Cursor Position Register. 3960 * Registers contains Hubp & Dpp modules 3961 */ 3962 struct dmub_cursor_position_cfg position_cfg; 3963 }; 3964 3965 struct dmub_cmd_update_cursor_payload1 { 3966 struct dmub_cursor_attributes_cfg attribute_cfg; 3967 }; 3968 3969 union dmub_cmd_update_cursor_info_data { 3970 struct dmub_cmd_update_cursor_payload0 payload0; 3971 struct dmub_cmd_update_cursor_payload1 payload1; 3972 }; 3973 /** 3974 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3975 */ 3976 struct dmub_rb_cmd_update_cursor_info { 3977 /** 3978 * Command header. 3979 */ 3980 struct dmub_cmd_header header; 3981 /** 3982 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3983 */ 3984 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3985 }; 3986 3987 /** 3988 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3989 */ 3990 struct dmub_cmd_psr_set_vtotal_data { 3991 /** 3992 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3993 */ 3994 uint16_t psr_vtotal_idle; 3995 /** 3996 * PSR control version. 3997 */ 3998 uint8_t cmd_version; 3999 /** 4000 * Panel Instance. 4001 * Panel instance to identify which psr_state to use 4002 * Currently the support is only for 0 or 1 4003 */ 4004 uint8_t panel_inst; 4005 /* 4006 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 4007 */ 4008 uint16_t psr_vtotal_su; 4009 /** 4010 * Explicit padding to 4 byte boundary. 4011 */ 4012 uint8_t pad2[2]; 4013 }; 4014 4015 /** 4016 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4017 */ 4018 struct dmub_rb_cmd_psr_set_vtotal { 4019 /** 4020 * Command header. 4021 */ 4022 struct dmub_cmd_header header; 4023 /** 4024 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4025 */ 4026 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 4027 }; 4028 4029 /** 4030 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 4031 */ 4032 struct dmub_cmd_psr_set_power_opt_data { 4033 /** 4034 * PSR control version. 4035 */ 4036 uint8_t cmd_version; 4037 /** 4038 * Panel Instance. 4039 * Panel instance to identify which psr_state to use 4040 * Currently the support is only for 0 or 1 4041 */ 4042 uint8_t panel_inst; 4043 /** 4044 * Explicit padding to 4 byte boundary. 4045 */ 4046 uint8_t pad[2]; 4047 /** 4048 * PSR power option 4049 */ 4050 uint32_t power_opt; 4051 }; 4052 4053 /** 4054 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4055 */ 4056 struct dmub_rb_cmd_psr_set_power_opt { 4057 /** 4058 * Command header. 4059 */ 4060 struct dmub_cmd_header header; 4061 /** 4062 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4063 */ 4064 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 4065 }; 4066 4067 enum dmub_alpm_mode { 4068 ALPM_AUXWAKE = 0, 4069 ALPM_AUXLESS = 1, 4070 ALPM_UNSUPPORTED = 2, 4071 }; 4072 4073 /** 4074 * Definition of Replay Residency GPINT command. 4075 * Bit[0] - Residency mode for Revision 0 4076 * Bit[1] - Enable/Disable state 4077 * Bit[2-3] - Revision number 4078 * Bit[4-7] - Residency mode for Revision 1 4079 * Bit[8] - Panel instance 4080 * Bit[9-15] - Reserved 4081 */ 4082 4083 enum pr_residency_mode { 4084 PR_RESIDENCY_MODE_PHY = 0x0, 4085 PR_RESIDENCY_MODE_ALPM, 4086 PR_RESIDENCY_MODE_IPS2, 4087 PR_RESIDENCY_MODE_FRAME_CNT, 4088 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 4089 }; 4090 4091 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 4092 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 4093 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 4094 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 4095 4096 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4097 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 4098 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4099 4100 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 4101 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 4102 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 4103 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 4104 4105 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4106 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4107 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4108 4109 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 4110 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 4111 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 4112 4113 /** 4114 * Definition of a replay_state. 4115 */ 4116 enum replay_state { 4117 REPLAY_STATE_0 = 0x0, 4118 REPLAY_STATE_1 = 0x10, 4119 REPLAY_STATE_1A = 0x11, 4120 REPLAY_STATE_2 = 0x20, 4121 REPLAY_STATE_2A = 0x21, 4122 REPLAY_STATE_3 = 0x30, 4123 REPLAY_STATE_3INIT = 0x31, 4124 REPLAY_STATE_4 = 0x40, 4125 REPLAY_STATE_4A = 0x41, 4126 REPLAY_STATE_4B = 0x42, 4127 REPLAY_STATE_4C = 0x43, 4128 REPLAY_STATE_4D = 0x44, 4129 REPLAY_STATE_4E = 0x45, 4130 REPLAY_STATE_4B_LOCKED = 0x4A, 4131 REPLAY_STATE_4C_UNLOCKED = 0x4B, 4132 REPLAY_STATE_5 = 0x50, 4133 REPLAY_STATE_5A = 0x51, 4134 REPLAY_STATE_5B = 0x52, 4135 REPLAY_STATE_5A_LOCKED = 0x5A, 4136 REPLAY_STATE_5B_UNLOCKED = 0x5B, 4137 REPLAY_STATE_6 = 0x60, 4138 REPLAY_STATE_6A = 0x61, 4139 REPLAY_STATE_6B = 0x62, 4140 REPLAY_STATE_INVALID = 0xFF, 4141 }; 4142 4143 /** 4144 * Replay command sub-types. 4145 */ 4146 enum dmub_cmd_replay_type { 4147 /** 4148 * Copy driver-calculated parameters to REPLAY state. 4149 */ 4150 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 4151 /** 4152 * Enable REPLAY. 4153 */ 4154 DMUB_CMD__REPLAY_ENABLE = 1, 4155 /** 4156 * Set Replay power option. 4157 */ 4158 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 4159 /** 4160 * Set coasting vtotal. 4161 */ 4162 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 4163 /** 4164 * Set power opt and coasting vtotal. 4165 */ 4166 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 4167 /** 4168 * Set disabled iiming sync. 4169 */ 4170 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 4171 /** 4172 * Set Residency Frameupdate Timer. 4173 */ 4174 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 4175 /** 4176 * Set pseudo vtotal 4177 */ 4178 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 4179 /** 4180 * Set adaptive sync sdp enabled 4181 */ 4182 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4183 /** 4184 * Set version 4185 */ 4186 DMUB_CMD__REPLAY_SET_VERSION = 9, 4187 /** 4188 * Set Replay General command. 4189 */ 4190 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4191 }; 4192 4193 /** 4194 * Replay general command sub-types. 4195 */ 4196 enum dmub_cmd_replay_general_subtype { 4197 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 4198 /** 4199 * TODO: For backward compatible, allow new command only. 4200 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4201 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4202 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4203 */ 4204 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4205 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4206 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4207 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4208 }; 4209 4210 struct dmub_alpm_auxless_data { 4211 uint16_t lfps_setup_ns; 4212 uint16_t lfps_period_ns; 4213 uint16_t lfps_silence_ns; 4214 uint16_t lfps_t1_t2_override_us; 4215 short lfps_t1_t2_offset_us; 4216 uint8_t lttpr_count; 4217 /* 4218 * Padding to align structure to 4 byte boundary. 4219 */ 4220 uint8_t pad[1]; 4221 }; 4222 4223 /** 4224 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4225 */ 4226 struct dmub_cmd_replay_copy_settings_data { 4227 /** 4228 * Flags that can be set by driver to change some replay behaviour. 4229 */ 4230 union replay_debug_flags debug; 4231 4232 /** 4233 * @flags: Flags used to determine feature functionality. 4234 */ 4235 union replay_hw_flags flags; 4236 4237 /** 4238 * DPP HW instance. 4239 */ 4240 uint8_t dpp_inst; 4241 /** 4242 * OTG HW instance. 4243 */ 4244 uint8_t otg_inst; 4245 /** 4246 * DIG FE HW instance. 4247 */ 4248 uint8_t digfe_inst; 4249 /** 4250 * DIG BE HW instance. 4251 */ 4252 uint8_t digbe_inst; 4253 /** 4254 * AUX HW instance. 4255 */ 4256 uint8_t aux_inst; 4257 /** 4258 * Panel Instance. 4259 * Panel isntance to identify which psr_state to use 4260 * Currently the support is only for 0 or 1 4261 */ 4262 uint8_t panel_inst; 4263 /** 4264 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4265 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4266 */ 4267 uint8_t pixel_deviation_per_line; 4268 /** 4269 * @max_deviation_line: The max number of deviation line that can keep the timing 4270 * synchronized between the Source and Sink during Replay normal sleep mode. 4271 */ 4272 uint8_t max_deviation_line; 4273 /** 4274 * Length of each horizontal line in ns. 4275 */ 4276 uint32_t line_time_in_ns; 4277 /** 4278 * PHY instance. 4279 */ 4280 uint8_t dpphy_inst; 4281 /** 4282 * Determines if SMU optimzations are enabled/disabled. 4283 */ 4284 uint8_t smu_optimizations_en; 4285 /** 4286 * Determines if timing sync are enabled/disabled. 4287 */ 4288 uint8_t replay_timing_sync_supported; 4289 /* 4290 * Use FSM state for Replay power up/down 4291 */ 4292 uint8_t use_phy_fsm; 4293 /** 4294 * Use for AUX-less ALPM LFPS wake operation 4295 */ 4296 struct dmub_alpm_auxless_data auxless_alpm_data; 4297 /** 4298 * @hpo_stream_enc_inst: HPO stream encoder instance 4299 */ 4300 uint8_t hpo_stream_enc_inst; 4301 /** 4302 * @hpo_link_enc_inst: HPO link encoder instance 4303 */ 4304 uint8_t hpo_link_enc_inst; 4305 /** 4306 * Determines if fast resync in ultra sleep mode is enabled/disabled. 4307 */ 4308 uint8_t replay_support_fast_resync_in_ultra_sleep_mode; 4309 /** 4310 * @pad: Align structure to 4 byte boundary. 4311 */ 4312 uint8_t pad[1]; 4313 }; 4314 4315 4316 /** 4317 * Replay versions. 4318 */ 4319 enum replay_version { 4320 /** 4321 * FreeSync Replay 4322 */ 4323 REPLAY_VERSION_FREESYNC_REPLAY = 0, 4324 /** 4325 * Panel Replay 4326 */ 4327 REPLAY_VERSION_PANEL_REPLAY = 1, 4328 /** 4329 * Replay not supported. 4330 */ 4331 REPLAY_VERSION_UNSUPPORTED = 0xFF, 4332 }; 4333 4334 /** 4335 * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command. 4336 */ 4337 struct dmub_cmd_replay_set_version_data { 4338 /** 4339 * Panel Instance. 4340 * Panel instance to identify which psr_state to use 4341 * Currently the support is only for 0 or 1 4342 */ 4343 uint8_t panel_inst; 4344 /** 4345 * PSR version that FW should implement. 4346 */ 4347 enum replay_version version; 4348 /** 4349 * PSR control version. 4350 */ 4351 uint8_t cmd_version; 4352 /** 4353 * Explicit padding to 4 byte boundary. 4354 */ 4355 uint8_t pad[2]; 4356 }; 4357 4358 /** 4359 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 4360 */ 4361 struct dmub_rb_cmd_replay_set_version { 4362 /** 4363 * Command header. 4364 */ 4365 struct dmub_cmd_header header; 4366 /** 4367 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_VERSION command. 4368 */ 4369 struct dmub_cmd_replay_set_version_data replay_set_version_data; 4370 }; 4371 4372 /** 4373 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4374 */ 4375 struct dmub_rb_cmd_replay_copy_settings { 4376 /** 4377 * Command header. 4378 */ 4379 struct dmub_cmd_header header; 4380 /** 4381 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4382 */ 4383 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4384 }; 4385 4386 /** 4387 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4388 */ 4389 enum replay_enable { 4390 /** 4391 * Disable REPLAY. 4392 */ 4393 REPLAY_DISABLE = 0, 4394 /** 4395 * Enable REPLAY. 4396 */ 4397 REPLAY_ENABLE = 1, 4398 }; 4399 4400 /** 4401 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_ENABLE command. 4402 */ 4403 struct dmub_rb_cmd_smart_power_hdr_enable_data { 4404 /** 4405 * SMART_POWER_HDR enable or disable. 4406 */ 4407 uint8_t enable; 4408 /** 4409 * Panel Instance. 4410 * Panel isntance to identify which replay_state to use 4411 * Currently the support is only for 0 or 1 4412 */ 4413 uint8_t panel_inst; 4414 4415 uint16_t peak_nits; 4416 /** 4417 * OTG HW instance. 4418 */ 4419 uint8_t otg_inst; 4420 /** 4421 * DIG FE HW instance. 4422 */ 4423 uint8_t digfe_inst; 4424 /** 4425 * DIG BE HW instance. 4426 */ 4427 uint8_t digbe_inst; 4428 uint8_t debugcontrol; 4429 /* 4430 * vertical interrupt trigger line 4431 */ 4432 uint32_t triggerline; 4433 4434 uint16_t fixed_max_cll; 4435 4436 uint8_t pad[2]; 4437 }; 4438 4439 /** 4440 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4441 */ 4442 struct dmub_rb_cmd_replay_enable_data { 4443 /** 4444 * Replay enable or disable. 4445 */ 4446 uint8_t enable; 4447 /** 4448 * Panel Instance. 4449 * Panel isntance to identify which replay_state to use 4450 * Currently the support is only for 0 or 1 4451 */ 4452 uint8_t panel_inst; 4453 /** 4454 * Phy state to enter. 4455 * Values to use are defined in dmub_phy_fsm_state 4456 */ 4457 uint8_t phy_fsm_state; 4458 /** 4459 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4460 * Set this using enum phy_link_rate. 4461 * This does not support HDMI/DP2 for now. 4462 */ 4463 uint8_t phy_rate; 4464 }; 4465 4466 /** 4467 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4468 * Replay enable/disable is controlled using action in data. 4469 */ 4470 struct dmub_rb_cmd_replay_enable { 4471 /** 4472 * Command header. 4473 */ 4474 struct dmub_cmd_header header; 4475 4476 struct dmub_rb_cmd_replay_enable_data data; 4477 }; 4478 4479 /** 4480 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4481 */ 4482 struct dmub_cmd_replay_set_power_opt_data { 4483 /** 4484 * Panel Instance. 4485 * Panel isntance to identify which replay_state to use 4486 * Currently the support is only for 0 or 1 4487 */ 4488 uint8_t panel_inst; 4489 /** 4490 * Explicit padding to 4 byte boundary. 4491 */ 4492 uint8_t pad[3]; 4493 /** 4494 * REPLAY power option 4495 */ 4496 uint32_t power_opt; 4497 }; 4498 4499 /** 4500 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4501 */ 4502 struct dmub_cmd_replay_set_timing_sync_data { 4503 /** 4504 * Panel Instance. 4505 * Panel isntance to identify which replay_state to use 4506 * Currently the support is only for 0 or 1 4507 */ 4508 uint8_t panel_inst; 4509 /** 4510 * REPLAY set_timing_sync 4511 */ 4512 uint8_t timing_sync_supported; 4513 /** 4514 * Explicit padding to 4 byte boundary. 4515 */ 4516 uint8_t pad[2]; 4517 }; 4518 4519 /** 4520 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4521 */ 4522 struct dmub_cmd_replay_set_pseudo_vtotal { 4523 /** 4524 * Panel Instance. 4525 * Panel isntance to identify which replay_state to use 4526 * Currently the support is only for 0 or 1 4527 */ 4528 uint8_t panel_inst; 4529 /** 4530 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4531 */ 4532 uint16_t vtotal; 4533 /** 4534 * Explicit padding to 4 byte boundary. 4535 */ 4536 uint8_t pad; 4537 }; 4538 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4539 /** 4540 * Panel Instance. 4541 * Panel isntance to identify which replay_state to use 4542 * Currently the support is only for 0 or 1 4543 */ 4544 uint8_t panel_inst; 4545 /** 4546 * enabled: set adaptive sync sdp enabled 4547 */ 4548 uint8_t force_disabled; 4549 4550 uint8_t pad[2]; 4551 }; 4552 struct dmub_cmd_replay_set_general_cmd_data { 4553 /** 4554 * Panel Instance. 4555 * Panel isntance to identify which replay_state to use 4556 * Currently the support is only for 0 or 1 4557 */ 4558 uint8_t panel_inst; 4559 /** 4560 * subtype: replay general cmd sub type 4561 */ 4562 uint8_t subtype; 4563 4564 uint8_t pad[2]; 4565 /** 4566 * config data with param1 and param2 4567 */ 4568 uint32_t param1; 4569 4570 uint32_t param2; 4571 }; 4572 4573 /** 4574 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4575 */ 4576 struct dmub_rb_cmd_replay_set_power_opt { 4577 /** 4578 * Command header. 4579 */ 4580 struct dmub_cmd_header header; 4581 /** 4582 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4583 */ 4584 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4585 }; 4586 4587 /** 4588 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4589 */ 4590 struct dmub_cmd_replay_set_coasting_vtotal_data { 4591 /** 4592 * 16-bit value dicated by driver that indicates the coasting vtotal. 4593 */ 4594 uint16_t coasting_vtotal; 4595 /** 4596 * REPLAY control version. 4597 */ 4598 uint8_t cmd_version; 4599 /** 4600 * Panel Instance. 4601 * Panel isntance to identify which replay_state to use 4602 * Currently the support is only for 0 or 1 4603 */ 4604 uint8_t panel_inst; 4605 /** 4606 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4607 */ 4608 uint16_t coasting_vtotal_high; 4609 /** 4610 * Explicit padding to 4 byte boundary. 4611 */ 4612 uint8_t pad[2]; 4613 }; 4614 4615 /** 4616 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4617 */ 4618 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4619 /** 4620 * Command header. 4621 */ 4622 struct dmub_cmd_header header; 4623 /** 4624 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4625 */ 4626 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4627 }; 4628 4629 /** 4630 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4631 */ 4632 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4633 /** 4634 * Command header. 4635 */ 4636 struct dmub_cmd_header header; 4637 /** 4638 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4639 */ 4640 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4641 /** 4642 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4643 */ 4644 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4645 }; 4646 4647 /** 4648 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4649 */ 4650 struct dmub_rb_cmd_replay_set_timing_sync { 4651 /** 4652 * Command header. 4653 */ 4654 struct dmub_cmd_header header; 4655 /** 4656 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4657 */ 4658 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4659 }; 4660 4661 /** 4662 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4663 */ 4664 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4665 /** 4666 * Command header. 4667 */ 4668 struct dmub_cmd_header header; 4669 /** 4670 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4671 */ 4672 struct dmub_cmd_replay_set_pseudo_vtotal data; 4673 }; 4674 4675 /** 4676 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4677 */ 4678 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4679 /** 4680 * Command header. 4681 */ 4682 struct dmub_cmd_header header; 4683 /** 4684 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4685 */ 4686 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4687 }; 4688 4689 /** 4690 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4691 */ 4692 struct dmub_rb_cmd_replay_set_general_cmd { 4693 /** 4694 * Command header. 4695 */ 4696 struct dmub_cmd_header header; 4697 /** 4698 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4699 */ 4700 struct dmub_cmd_replay_set_general_cmd_data data; 4701 }; 4702 4703 /** 4704 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4705 */ 4706 struct dmub_cmd_replay_frameupdate_timer_data { 4707 /** 4708 * Panel Instance. 4709 * Panel isntance to identify which replay_state to use 4710 * Currently the support is only for 0 or 1 4711 */ 4712 uint8_t panel_inst; 4713 /** 4714 * Replay Frameupdate Timer Enable or not 4715 */ 4716 uint8_t enable; 4717 /** 4718 * REPLAY force reflash frame update number 4719 */ 4720 uint16_t frameupdate_count; 4721 }; 4722 /** 4723 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4724 */ 4725 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4726 /** 4727 * Command header. 4728 */ 4729 struct dmub_cmd_header header; 4730 /** 4731 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4732 */ 4733 struct dmub_cmd_replay_frameupdate_timer_data data; 4734 }; 4735 4736 /** 4737 * Definition union of replay command set 4738 */ 4739 union dmub_replay_cmd_set { 4740 /** 4741 * Panel Instance. 4742 * Panel isntance to identify which replay_state to use 4743 * Currently the support is only for 0 or 1 4744 */ 4745 uint8_t panel_inst; 4746 /** 4747 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4748 */ 4749 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4750 /** 4751 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4752 */ 4753 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4754 /** 4755 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4756 */ 4757 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4758 /** 4759 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4760 */ 4761 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4762 /** 4763 * Definition of DMUB_CMD__REPLAY_SET_VERSION command data. 4764 */ 4765 struct dmub_cmd_replay_set_version_data version_data; 4766 /** 4767 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4768 */ 4769 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4770 }; 4771 4772 /** 4773 * SMART POWER HDR command sub-types. 4774 */ 4775 enum dmub_cmd_smart_power_hdr_type { 4776 4777 /** 4778 * Enable/Disable SMART_POWER_HDR. 4779 */ 4780 DMUB_CMD__SMART_POWER_HDR_ENABLE = 1, 4781 /** 4782 * Get current MaxCLL value if SMART POWER HDR is enabled. 4783 */ 4784 DMUB_CMD__SMART_POWER_HDR_GETMAXCLL = 2, 4785 }; 4786 4787 /** 4788 * Definition of a DMUB_CMD__SMART_POWER_HDR command. 4789 */ 4790 struct dmub_rb_cmd_smart_power_hdr_enable { 4791 /** 4792 * Command header. 4793 */ 4794 struct dmub_cmd_header header; 4795 4796 struct dmub_rb_cmd_smart_power_hdr_enable_data data; 4797 }; 4798 4799 struct dmub_cmd_smart_power_hdr_getmaxcll_input { 4800 uint8_t panel_inst; 4801 uint8_t pad[3]; 4802 }; 4803 4804 struct dmub_cmd_smart_power_hdr_getmaxcll_output { 4805 uint16_t current_max_cll; 4806 uint8_t pad[2]; 4807 }; 4808 4809 /** 4810 * Definition of a DMUB_CMD__SMART_POWER_HDR command. 4811 */ 4812 struct dmub_rb_cmd_smart_power_hdr_getmaxcll { 4813 struct dmub_cmd_header header; /**< Command header */ 4814 /** 4815 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. 4816 */ 4817 union dmub_cmd_smart_power_hdr_getmaxcll_data { 4818 struct dmub_cmd_smart_power_hdr_getmaxcll_input input; /**< Input */ 4819 struct dmub_cmd_smart_power_hdr_getmaxcll_output output; /**< Output */ 4820 uint32_t output_raw; /**< Raw data output */ 4821 } data; 4822 }; 4823 4824 /** 4825 * Set of HW components that can be locked. 4826 * 4827 * Note: If updating with more HW components, fields 4828 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4829 */ 4830 union dmub_hw_lock_flags { 4831 /** 4832 * Set of HW components that can be locked. 4833 */ 4834 struct { 4835 /** 4836 * Lock/unlock OTG master update lock. 4837 */ 4838 uint8_t lock_pipe : 1; 4839 /** 4840 * Lock/unlock cursor. 4841 */ 4842 uint8_t lock_cursor : 1; 4843 /** 4844 * Lock/unlock global update lock. 4845 */ 4846 uint8_t lock_dig : 1; 4847 /** 4848 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4849 */ 4850 uint8_t triple_buffer_lock : 1; 4851 } bits; 4852 4853 /** 4854 * Union for HW Lock flags. 4855 */ 4856 uint8_t u8All; 4857 }; 4858 4859 /** 4860 * Instances of HW to be locked. 4861 * 4862 * Note: If updating with more HW components, fields 4863 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4864 */ 4865 struct dmub_hw_lock_inst_flags { 4866 /** 4867 * OTG HW instance for OTG master update lock. 4868 */ 4869 uint8_t otg_inst; 4870 /** 4871 * OPP instance for cursor lock. 4872 */ 4873 uint8_t opp_inst; 4874 /** 4875 * OTG HW instance for global update lock. 4876 * TODO: Remove, and re-use otg_inst. 4877 */ 4878 uint8_t dig_inst; 4879 /** 4880 * Explicit pad to 4 byte boundary. 4881 */ 4882 uint8_t pad; 4883 }; 4884 4885 /** 4886 * Clients that can acquire the HW Lock Manager. 4887 * 4888 * Note: If updating with more clients, fields in 4889 * dmub_inbox0_cmd_lock_hw must be updated to match. 4890 */ 4891 enum hw_lock_client { 4892 /** 4893 * Driver is the client of HW Lock Manager. 4894 */ 4895 HW_LOCK_CLIENT_DRIVER = 0, 4896 /** 4897 * PSR SU is the client of HW Lock Manager. 4898 */ 4899 HW_LOCK_CLIENT_PSR_SU = 1, 4900 HW_LOCK_CLIENT_SUBVP = 3, 4901 /** 4902 * Replay is the client of HW Lock Manager. 4903 */ 4904 HW_LOCK_CLIENT_REPLAY = 4, 4905 HW_LOCK_CLIENT_FAMS2 = 5, 4906 HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6, 4907 /** 4908 * Invalid client. 4909 */ 4910 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4911 }; 4912 4913 /** 4914 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4915 */ 4916 struct dmub_cmd_lock_hw_data { 4917 /** 4918 * Specifies the client accessing HW Lock Manager. 4919 */ 4920 enum hw_lock_client client; 4921 /** 4922 * HW instances to be locked. 4923 */ 4924 struct dmub_hw_lock_inst_flags inst_flags; 4925 /** 4926 * Which components to be locked. 4927 */ 4928 union dmub_hw_lock_flags hw_locks; 4929 /** 4930 * Specifies lock/unlock. 4931 */ 4932 uint8_t lock; 4933 /** 4934 * HW can be unlocked separately from releasing the HW Lock Mgr. 4935 * This flag is set if the client wishes to release the object. 4936 */ 4937 uint8_t should_release; 4938 /** 4939 * Explicit padding to 4 byte boundary. 4940 */ 4941 uint8_t pad; 4942 }; 4943 4944 /** 4945 * Definition of a DMUB_CMD__HW_LOCK command. 4946 * Command is used by driver and FW. 4947 */ 4948 struct dmub_rb_cmd_lock_hw { 4949 /** 4950 * Command header. 4951 */ 4952 struct dmub_cmd_header header; 4953 /** 4954 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4955 */ 4956 struct dmub_cmd_lock_hw_data lock_hw_data; 4957 }; 4958 4959 /** 4960 * ABM command sub-types. 4961 */ 4962 enum dmub_cmd_abm_type { 4963 /** 4964 * Initialize parameters for ABM algorithm. 4965 * Data is passed through an indirect buffer. 4966 */ 4967 DMUB_CMD__ABM_INIT_CONFIG = 0, 4968 /** 4969 * Set OTG and panel HW instance. 4970 */ 4971 DMUB_CMD__ABM_SET_PIPE = 1, 4972 /** 4973 * Set user requested backklight level. 4974 */ 4975 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4976 /** 4977 * Set ABM operating/aggression level. 4978 */ 4979 DMUB_CMD__ABM_SET_LEVEL = 3, 4980 /** 4981 * Set ambient light level. 4982 */ 4983 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4984 /** 4985 * Enable/disable fractional duty cycle for backlight PWM. 4986 */ 4987 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4988 4989 /** 4990 * unregister vertical interrupt after steady state is reached 4991 */ 4992 DMUB_CMD__ABM_PAUSE = 6, 4993 4994 /** 4995 * Save and Restore ABM state. On save we save parameters, and 4996 * on restore we update state with passed in data. 4997 */ 4998 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4999 5000 /** 5001 * Query ABM caps. 5002 */ 5003 DMUB_CMD__ABM_QUERY_CAPS = 8, 5004 5005 /** 5006 * Set ABM Events 5007 */ 5008 DMUB_CMD__ABM_SET_EVENT = 9, 5009 5010 /** 5011 * Get the current ACE curve. 5012 */ 5013 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 5014 5015 /** 5016 * Get current histogram data 5017 */ 5018 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 5019 }; 5020 5021 /** 5022 * LSDMA command sub-types. 5023 */ 5024 enum dmub_cmd_lsdma_type { 5025 /** 5026 * Initialize parameters for LSDMA. 5027 * Ring buffer is mapped to the ring buffer 5028 */ 5029 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 5030 /** 5031 * LSDMA copies data from source to destination linearly 5032 */ 5033 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 5034 /** 5035 * LSDMA copies data from source to destination linearly in sub window 5036 */ 5037 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, 5038 /** 5039 * Send the tiled-to-tiled copy command 5040 */ 5041 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, 5042 /** 5043 * Send the poll reg write command 5044 */ 5045 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, 5046 /** 5047 * Send the pio copy command 5048 */ 5049 DMUB_CMD__LSDMA_PIO_COPY = 5, 5050 /** 5051 * Send the pio constfill command 5052 */ 5053 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, 5054 }; 5055 5056 struct abm_ace_curve { 5057 /** 5058 * @offsets: ACE curve offsets. 5059 */ 5060 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5061 5062 /** 5063 * @thresholds: ACE curve thresholds. 5064 */ 5065 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5066 5067 /** 5068 * @slopes: ACE curve slopes. 5069 */ 5070 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5071 }; 5072 5073 struct fixed_pt_format { 5074 /** 5075 * @sign_bit: Indicates whether one bit is reserved for the sign. 5076 */ 5077 bool sign_bit; 5078 5079 /** 5080 * @num_int_bits: Number of bits used for integer part. 5081 */ 5082 uint8_t num_int_bits; 5083 5084 /** 5085 * @num_frac_bits: Number of bits used for fractional part. 5086 */ 5087 uint8_t num_frac_bits; 5088 5089 /** 5090 * @pad: Explicit padding to 4 byte boundary. 5091 */ 5092 uint8_t pad; 5093 }; 5094 5095 struct abm_caps { 5096 /** 5097 * @num_hg_bins: Number of histogram bins. 5098 */ 5099 uint8_t num_hg_bins; 5100 5101 /** 5102 * @num_ace_segments: Number of ACE curve segments. 5103 */ 5104 uint8_t num_ace_segments; 5105 5106 /** 5107 * @pad: Explicit padding to 4 byte boundary. 5108 */ 5109 uint8_t pad[2]; 5110 5111 /** 5112 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 5113 */ 5114 struct fixed_pt_format ace_thresholds_format; 5115 5116 /** 5117 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 5118 */ 5119 struct fixed_pt_format ace_offsets_format; 5120 5121 /** 5122 * @ace_slopes_format: Format of the ACE slopes. 5123 */ 5124 struct fixed_pt_format ace_slopes_format; 5125 }; 5126 5127 /** 5128 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 5129 * Requirements: 5130 * - Padded explicitly to 32-bit boundary. 5131 * - Must ensure this structure matches the one on driver-side, 5132 * otherwise it won't be aligned. 5133 */ 5134 struct abm_config_table { 5135 /** 5136 * Gamma curve thresholds, used for crgb conversion. 5137 */ 5138 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 5139 /** 5140 * Gamma curve offsets, used for crgb conversion. 5141 */ 5142 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 5143 /** 5144 * Gamma curve slopes, used for crgb conversion. 5145 */ 5146 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 5147 /** 5148 * Custom backlight curve thresholds. 5149 */ 5150 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 5151 /** 5152 * Custom backlight curve offsets. 5153 */ 5154 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 5155 /** 5156 * Ambient light thresholds. 5157 */ 5158 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 5159 /** 5160 * Minimum programmable backlight. 5161 */ 5162 uint16_t min_abm_backlight; // 122B 5163 /** 5164 * Minimum reduction values. 5165 */ 5166 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 5167 /** 5168 * Maximum reduction values. 5169 */ 5170 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 5171 /** 5172 * Bright positive gain. 5173 */ 5174 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 5175 /** 5176 * Dark negative gain. 5177 */ 5178 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 5179 /** 5180 * Hybrid factor. 5181 */ 5182 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 5183 /** 5184 * Contrast factor. 5185 */ 5186 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 5187 /** 5188 * Deviation gain. 5189 */ 5190 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 5191 /** 5192 * Minimum knee. 5193 */ 5194 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 5195 /** 5196 * Maximum knee. 5197 */ 5198 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 5199 /** 5200 * Unused. 5201 */ 5202 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 5203 /** 5204 * Explicit padding to 4 byte boundary. 5205 */ 5206 uint8_t pad3[3]; // 229B 5207 /** 5208 * Backlight ramp reduction. 5209 */ 5210 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 5211 /** 5212 * Backlight ramp start. 5213 */ 5214 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 5215 }; 5216 5217 /** 5218 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5219 */ 5220 struct dmub_cmd_abm_set_pipe_data { 5221 /** 5222 * OTG HW instance. 5223 */ 5224 uint8_t otg_inst; 5225 5226 /** 5227 * Panel Control HW instance. 5228 */ 5229 uint8_t panel_inst; 5230 5231 /** 5232 * Controls how ABM will interpret a set pipe or set level command. 5233 */ 5234 uint8_t set_pipe_option; 5235 5236 /** 5237 * Unused. 5238 * TODO: Remove. 5239 */ 5240 uint8_t ramping_boundary; 5241 5242 /** 5243 * PwrSeq HW Instance. 5244 */ 5245 uint8_t pwrseq_inst; 5246 5247 /** 5248 * Explicit padding to 4 byte boundary. 5249 */ 5250 uint8_t pad[3]; 5251 }; 5252 5253 /** 5254 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5255 */ 5256 struct dmub_rb_cmd_abm_set_pipe { 5257 /** 5258 * Command header. 5259 */ 5260 struct dmub_cmd_header header; 5261 5262 /** 5263 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5264 */ 5265 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 5266 }; 5267 5268 /** 5269 * Type of backlight control method to be used by ABM module 5270 */ 5271 enum dmub_backlight_control_type { 5272 /** 5273 * PWM Backlight control 5274 */ 5275 DMU_BACKLIGHT_CONTROL_PWM = 0, 5276 /** 5277 * VESA Aux-based backlight control 5278 */ 5279 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 5280 /** 5281 * AMD DPCD Aux-based backlight control 5282 */ 5283 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 5284 }; 5285 5286 /** 5287 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5288 */ 5289 struct dmub_cmd_abm_set_backlight_data { 5290 /** 5291 * Number of frames to ramp to backlight user level. 5292 */ 5293 uint32_t frame_ramp; 5294 5295 /** 5296 * Requested backlight level from user. 5297 */ 5298 uint32_t backlight_user_level; 5299 5300 /** 5301 * ABM control version. 5302 */ 5303 uint8_t version; 5304 5305 /** 5306 * Panel Control HW instance mask. 5307 * Bit 0 is Panel Control HW instance 0. 5308 * Bit 1 is Panel Control HW instance 1. 5309 */ 5310 uint8_t panel_mask; 5311 5312 /** 5313 * AUX HW Instance. 5314 */ 5315 uint8_t aux_inst; 5316 5317 /** 5318 * Explicit padding to 4 byte boundary. 5319 */ 5320 uint8_t pad[1]; 5321 5322 /** 5323 * Backlight control type. 5324 * Value 0 is PWM backlight control. 5325 * Value 1 is VAUX backlight control. 5326 * Value 2 is AMD DPCD AUX backlight control. 5327 */ 5328 enum dmub_backlight_control_type backlight_control_type; 5329 5330 /** 5331 * Minimum luminance in nits. 5332 */ 5333 uint32_t min_luminance; 5334 5335 /** 5336 * Maximum luminance in nits. 5337 */ 5338 uint32_t max_luminance; 5339 5340 /** 5341 * Minimum backlight in pwm. 5342 */ 5343 uint32_t min_backlight_pwm; 5344 5345 /** 5346 * Maximum backlight in pwm. 5347 */ 5348 uint32_t max_backlight_pwm; 5349 }; 5350 5351 /** 5352 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5353 */ 5354 struct dmub_rb_cmd_abm_set_backlight { 5355 /** 5356 * Command header. 5357 */ 5358 struct dmub_cmd_header header; 5359 5360 /** 5361 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5362 */ 5363 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 5364 }; 5365 5366 /** 5367 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5368 */ 5369 struct dmub_cmd_abm_set_level_data { 5370 /** 5371 * Set current ABM operating/aggression level. 5372 */ 5373 uint32_t level; 5374 5375 /** 5376 * ABM control version. 5377 */ 5378 uint8_t version; 5379 5380 /** 5381 * Panel Control HW instance mask. 5382 * Bit 0 is Panel Control HW instance 0. 5383 * Bit 1 is Panel Control HW instance 1. 5384 */ 5385 uint8_t panel_mask; 5386 5387 /** 5388 * Explicit padding to 4 byte boundary. 5389 */ 5390 uint8_t pad[2]; 5391 }; 5392 5393 /** 5394 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5395 */ 5396 struct dmub_rb_cmd_abm_set_level { 5397 /** 5398 * Command header. 5399 */ 5400 struct dmub_cmd_header header; 5401 5402 /** 5403 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5404 */ 5405 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5406 }; 5407 5408 /** 5409 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5410 */ 5411 struct dmub_cmd_abm_set_ambient_level_data { 5412 /** 5413 * Ambient light sensor reading from OS. 5414 */ 5415 uint32_t ambient_lux; 5416 5417 /** 5418 * ABM control version. 5419 */ 5420 uint8_t version; 5421 5422 /** 5423 * Panel Control HW instance mask. 5424 * Bit 0 is Panel Control HW instance 0. 5425 * Bit 1 is Panel Control HW instance 1. 5426 */ 5427 uint8_t panel_mask; 5428 5429 /** 5430 * Explicit padding to 4 byte boundary. 5431 */ 5432 uint8_t pad[2]; 5433 }; 5434 5435 /** 5436 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5437 */ 5438 struct dmub_rb_cmd_abm_set_ambient_level { 5439 /** 5440 * Command header. 5441 */ 5442 struct dmub_cmd_header header; 5443 5444 /** 5445 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5446 */ 5447 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5448 }; 5449 5450 /** 5451 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5452 */ 5453 struct dmub_cmd_abm_set_pwm_frac_data { 5454 /** 5455 * Enable/disable fractional duty cycle for backlight PWM. 5456 * TODO: Convert to uint8_t. 5457 */ 5458 uint32_t fractional_pwm; 5459 5460 /** 5461 * ABM control version. 5462 */ 5463 uint8_t version; 5464 5465 /** 5466 * Panel Control HW instance mask. 5467 * Bit 0 is Panel Control HW instance 0. 5468 * Bit 1 is Panel Control HW instance 1. 5469 */ 5470 uint8_t panel_mask; 5471 5472 /** 5473 * Explicit padding to 4 byte boundary. 5474 */ 5475 uint8_t pad[2]; 5476 }; 5477 5478 /** 5479 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5480 */ 5481 struct dmub_rb_cmd_abm_set_pwm_frac { 5482 /** 5483 * Command header. 5484 */ 5485 struct dmub_cmd_header header; 5486 5487 /** 5488 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5489 */ 5490 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5491 }; 5492 5493 /** 5494 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5495 */ 5496 struct dmub_cmd_abm_init_config_data { 5497 /** 5498 * Location of indirect buffer used to pass init data to ABM. 5499 */ 5500 union dmub_addr src; 5501 5502 /** 5503 * Indirect buffer length. 5504 */ 5505 uint16_t bytes; 5506 5507 5508 /** 5509 * ABM control version. 5510 */ 5511 uint8_t version; 5512 5513 /** 5514 * Panel Control HW instance mask. 5515 * Bit 0 is Panel Control HW instance 0. 5516 * Bit 1 is Panel Control HW instance 1. 5517 */ 5518 uint8_t panel_mask; 5519 5520 /** 5521 * Explicit padding to 4 byte boundary. 5522 */ 5523 uint8_t pad[2]; 5524 }; 5525 5526 /** 5527 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5528 */ 5529 struct dmub_rb_cmd_abm_init_config { 5530 /** 5531 * Command header. 5532 */ 5533 struct dmub_cmd_header header; 5534 5535 /** 5536 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5537 */ 5538 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5539 }; 5540 5541 /** 5542 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5543 */ 5544 5545 struct dmub_cmd_abm_pause_data { 5546 5547 /** 5548 * Panel Control HW instance mask. 5549 * Bit 0 is Panel Control HW instance 0. 5550 * Bit 1 is Panel Control HW instance 1. 5551 */ 5552 uint8_t panel_mask; 5553 5554 /** 5555 * OTG hw instance 5556 */ 5557 uint8_t otg_inst; 5558 5559 /** 5560 * Enable or disable ABM pause 5561 */ 5562 uint8_t enable; 5563 5564 /** 5565 * Explicit padding to 4 byte boundary. 5566 */ 5567 uint8_t pad[1]; 5568 }; 5569 5570 /** 5571 * Definition of a DMUB_CMD__ABM_PAUSE command. 5572 */ 5573 struct dmub_rb_cmd_abm_pause { 5574 /** 5575 * Command header. 5576 */ 5577 struct dmub_cmd_header header; 5578 5579 /** 5580 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5581 */ 5582 struct dmub_cmd_abm_pause_data abm_pause_data; 5583 }; 5584 5585 /** 5586 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5587 */ 5588 struct dmub_cmd_abm_query_caps_in { 5589 /** 5590 * Panel instance. 5591 */ 5592 uint8_t panel_inst; 5593 5594 /** 5595 * Explicit padding to 4 byte boundary. 5596 */ 5597 uint8_t pad[3]; 5598 }; 5599 5600 /** 5601 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5602 */ 5603 struct dmub_cmd_abm_query_caps_out { 5604 /** 5605 * SW Algorithm caps. 5606 */ 5607 struct abm_caps sw_caps; 5608 5609 /** 5610 * ABM HW caps. 5611 */ 5612 struct abm_caps hw_caps; 5613 }; 5614 5615 /** 5616 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5617 */ 5618 struct dmub_rb_cmd_abm_query_caps { 5619 /** 5620 * Command header. 5621 */ 5622 struct dmub_cmd_header header; 5623 5624 /** 5625 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5626 */ 5627 union { 5628 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5629 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5630 } data; 5631 }; 5632 5633 /** 5634 * enum dmub_abm_ace_curve_type - ACE curve type. 5635 */ 5636 enum dmub_abm_ace_curve_type { 5637 /** 5638 * ACE curve as defined by the SW layer. 5639 */ 5640 ABM_ACE_CURVE_TYPE__SW = 0, 5641 /** 5642 * ACE curve as defined by the SW to HW translation interface layer. 5643 */ 5644 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5645 }; 5646 5647 /** 5648 * enum dmub_abm_histogram_type - Histogram type. 5649 */ 5650 enum dmub_abm_histogram_type { 5651 /** 5652 * ACE curve as defined by the SW layer. 5653 */ 5654 ABM_HISTOGRAM_TYPE__SW = 0, 5655 /** 5656 * ACE curve as defined by the SW to HW translation interface layer. 5657 */ 5658 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5659 }; 5660 5661 /** 5662 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5663 */ 5664 struct dmub_rb_cmd_abm_get_ace_curve { 5665 /** 5666 * Command header. 5667 */ 5668 struct dmub_cmd_header header; 5669 5670 /** 5671 * Address where ACE curve should be copied. 5672 */ 5673 union dmub_addr dest; 5674 5675 /** 5676 * Type of ACE curve being queried. 5677 */ 5678 enum dmub_abm_ace_curve_type ace_type; 5679 5680 /** 5681 * Indirect buffer length. 5682 */ 5683 uint16_t bytes; 5684 5685 /** 5686 * eDP panel instance. 5687 */ 5688 uint8_t panel_inst; 5689 5690 /** 5691 * Explicit padding to 4 byte boundary. 5692 */ 5693 uint8_t pad; 5694 }; 5695 5696 /** 5697 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5698 */ 5699 struct dmub_rb_cmd_abm_get_histogram { 5700 /** 5701 * Command header. 5702 */ 5703 struct dmub_cmd_header header; 5704 5705 /** 5706 * Address where Histogram should be copied. 5707 */ 5708 union dmub_addr dest; 5709 5710 /** 5711 * Type of Histogram being queried. 5712 */ 5713 enum dmub_abm_histogram_type histogram_type; 5714 5715 /** 5716 * Indirect buffer length. 5717 */ 5718 uint16_t bytes; 5719 5720 /** 5721 * eDP panel instance. 5722 */ 5723 uint8_t panel_inst; 5724 5725 /** 5726 * Explicit padding to 4 byte boundary. 5727 */ 5728 uint8_t pad; 5729 }; 5730 5731 /** 5732 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5733 */ 5734 struct dmub_rb_cmd_abm_save_restore { 5735 /** 5736 * Command header. 5737 */ 5738 struct dmub_cmd_header header; 5739 5740 /** 5741 * OTG hw instance 5742 */ 5743 uint8_t otg_inst; 5744 5745 /** 5746 * Enable or disable ABM pause 5747 */ 5748 uint8_t freeze; 5749 5750 /** 5751 * Explicit padding to 4 byte boundary. 5752 */ 5753 uint8_t debug; 5754 5755 /** 5756 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5757 */ 5758 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5759 }; 5760 5761 /** 5762 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5763 */ 5764 5765 struct dmub_cmd_abm_set_event_data { 5766 5767 /** 5768 * VB Scaling Init. Strength Mapping 5769 * Byte 0: 0~255 for VB level 0 5770 * Byte 1: 0~255 for VB level 1 5771 * Byte 2: 0~255 for VB level 2 5772 * Byte 3: 0~255 for VB level 3 5773 */ 5774 uint32_t vb_scaling_strength_mapping; 5775 /** 5776 * VariBright Scaling Enable 5777 */ 5778 uint8_t vb_scaling_enable; 5779 /** 5780 * Panel Control HW instance mask. 5781 * Bit 0 is Panel Control HW instance 0. 5782 * Bit 1 is Panel Control HW instance 1. 5783 */ 5784 uint8_t panel_mask; 5785 5786 /** 5787 * Explicit padding to 4 byte boundary. 5788 */ 5789 uint8_t pad[2]; 5790 }; 5791 5792 /** 5793 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5794 */ 5795 struct dmub_rb_cmd_abm_set_event { 5796 /** 5797 * Command header. 5798 */ 5799 struct dmub_cmd_header header; 5800 5801 /** 5802 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5803 */ 5804 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5805 }; 5806 5807 /** 5808 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5809 */ 5810 struct dmub_cmd_query_feature_caps_data { 5811 /** 5812 * DMUB feature capabilities. 5813 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5814 */ 5815 struct dmub_feature_caps feature_caps; 5816 }; 5817 5818 /** 5819 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5820 */ 5821 struct dmub_rb_cmd_query_feature_caps { 5822 /** 5823 * Command header. 5824 */ 5825 struct dmub_cmd_header header; 5826 /** 5827 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5828 */ 5829 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5830 }; 5831 5832 /** 5833 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5834 */ 5835 struct dmub_cmd_visual_confirm_color_data { 5836 /** 5837 * DMUB visual confirm color 5838 */ 5839 struct dmub_visual_confirm_color visual_confirm_color; 5840 }; 5841 5842 /** 5843 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5844 */ 5845 struct dmub_rb_cmd_get_visual_confirm_color { 5846 /** 5847 * Command header. 5848 */ 5849 struct dmub_cmd_header header; 5850 /** 5851 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5852 */ 5853 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5854 }; 5855 5856 /** 5857 * enum dmub_cmd_panel_cntl_type - Panel control command. 5858 */ 5859 enum dmub_cmd_panel_cntl_type { 5860 /** 5861 * Initializes embedded panel hardware blocks. 5862 */ 5863 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5864 /** 5865 * Queries backlight info for the embedded panel. 5866 */ 5867 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5868 /** 5869 * Sets the PWM Freq as per user's requirement. 5870 */ 5871 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5872 }; 5873 5874 /** 5875 * struct dmub_cmd_panel_cntl_data - Panel control data. 5876 */ 5877 struct dmub_cmd_panel_cntl_data { 5878 uint32_t pwrseq_inst; /**< pwrseq instance */ 5879 uint32_t current_backlight; /* in/out */ 5880 uint32_t bl_pwm_cntl; /* in/out */ 5881 uint32_t bl_pwm_period_cntl; /* in/out */ 5882 uint32_t bl_pwm_ref_div1; /* in/out */ 5883 uint8_t is_backlight_on : 1; /* in/out */ 5884 uint8_t is_powered_on : 1; /* in/out */ 5885 uint8_t padding[3]; 5886 uint32_t bl_pwm_ref_div2; /* in/out */ 5887 uint8_t reserved[4]; 5888 }; 5889 5890 /** 5891 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5892 */ 5893 struct dmub_rb_cmd_panel_cntl { 5894 struct dmub_cmd_header header; /**< header */ 5895 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5896 }; 5897 5898 struct dmub_optc_state { 5899 uint32_t v_total_max; 5900 uint32_t v_total_min; 5901 uint32_t tg_inst; 5902 }; 5903 5904 struct dmub_rb_cmd_drr_update { 5905 struct dmub_cmd_header header; 5906 struct dmub_optc_state dmub_optc_state_req; 5907 }; 5908 5909 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5910 uint32_t pix_clk_100hz; 5911 uint8_t max_ramp_step; 5912 uint8_t pipes; 5913 uint8_t min_refresh_in_hz; 5914 uint8_t pipe_count; 5915 uint8_t pipe_index[4]; 5916 }; 5917 5918 struct dmub_cmd_fw_assisted_mclk_switch_config { 5919 uint8_t fams_enabled; 5920 uint8_t visual_confirm_enabled; 5921 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5922 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5923 }; 5924 5925 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5926 struct dmub_cmd_header header; 5927 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5928 }; 5929 5930 /** 5931 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5932 */ 5933 struct dmub_cmd_lvtma_control_data { 5934 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5935 uint8_t bypass_panel_control_wait; 5936 uint8_t reserved_0[2]; /**< For future use */ 5937 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5938 uint8_t reserved_1[3]; /**< For future use */ 5939 }; 5940 5941 /** 5942 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5943 */ 5944 struct dmub_rb_cmd_lvtma_control { 5945 /** 5946 * Command header. 5947 */ 5948 struct dmub_cmd_header header; 5949 /** 5950 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5951 */ 5952 struct dmub_cmd_lvtma_control_data data; 5953 }; 5954 5955 /** 5956 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5957 */ 5958 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5959 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5960 uint8_t is_usb; /**< is phy is usb */ 5961 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5962 uint8_t is_dp4; /**< is dp in 4 lane */ 5963 }; 5964 5965 /** 5966 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5967 */ 5968 struct dmub_rb_cmd_transmitter_query_dp_alt { 5969 struct dmub_cmd_header header; /**< header */ 5970 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5971 }; 5972 5973 struct phy_test_mode { 5974 uint8_t mode; 5975 uint8_t pat0; 5976 uint8_t pad[2]; 5977 }; 5978 5979 /** 5980 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5981 */ 5982 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5983 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5984 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5985 uint8_t lane_num; /**< Number of lanes */ 5986 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5987 struct phy_test_mode test_mode; 5988 enum dmub_phy_fsm_state state; 5989 uint32_t status; 5990 uint8_t pad; 5991 }; 5992 5993 /** 5994 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5995 */ 5996 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5997 struct dmub_cmd_header header; /**< header */ 5998 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5999 }; 6000 6001 /** 6002 * Maximum number of bytes a chunk sent to DMUB for parsing 6003 */ 6004 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 6005 6006 /** 6007 * Represent a chunk of CEA blocks sent to DMUB for parsing 6008 */ 6009 struct dmub_cmd_send_edid_cea { 6010 uint16_t offset; /**< offset into the CEA block */ 6011 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 6012 uint16_t cea_total_length; /**< total length of the CEA block */ 6013 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 6014 uint8_t pad[3]; /**< padding and for future expansion */ 6015 }; 6016 6017 /** 6018 * Result of VSDB parsing from CEA block 6019 */ 6020 struct dmub_cmd_edid_cea_amd_vsdb { 6021 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 6022 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 6023 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 6024 uint16_t min_frame_rate; /**< Maximum frame rate */ 6025 uint16_t max_frame_rate; /**< Minimum frame rate */ 6026 }; 6027 6028 /** 6029 * Result of sending a CEA chunk 6030 */ 6031 struct dmub_cmd_edid_cea_ack { 6032 uint16_t offset; /**< offset of the chunk into the CEA block */ 6033 uint8_t success; /**< 1 if this sending of chunk succeeded */ 6034 uint8_t pad; /**< padding and for future expansion */ 6035 }; 6036 6037 /** 6038 * Specify whether the result is an ACK/NACK or the parsing has finished 6039 */ 6040 enum dmub_cmd_edid_cea_reply_type { 6041 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 6042 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 6043 }; 6044 6045 /** 6046 * Definition of a DMUB_CMD__EDID_CEA command. 6047 */ 6048 struct dmub_rb_cmd_edid_cea { 6049 struct dmub_cmd_header header; /**< Command header */ 6050 union dmub_cmd_edid_cea_data { 6051 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 6052 struct dmub_cmd_edid_cea_output { /**< output with results */ 6053 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 6054 union { 6055 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 6056 struct dmub_cmd_edid_cea_ack ack; 6057 }; 6058 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 6059 } data; /**< Command data */ 6060 6061 }; 6062 6063 /** 6064 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 6065 */ 6066 struct dmub_cmd_cable_id_input { 6067 uint8_t phy_inst; /**< phy inst for cable id data */ 6068 }; 6069 6070 /** 6071 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 6072 */ 6073 struct dmub_cmd_cable_id_output { 6074 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 6075 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 6076 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 6077 uint8_t RESERVED :2; /**< reserved means not defined */ 6078 }; 6079 6080 /** 6081 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 6082 */ 6083 struct dmub_rb_cmd_get_usbc_cable_id { 6084 struct dmub_cmd_header header; /**< Command header */ 6085 /** 6086 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 6087 */ 6088 union dmub_cmd_cable_id_data { 6089 struct dmub_cmd_cable_id_input input; /**< Input */ 6090 struct dmub_cmd_cable_id_output output; /**< Output */ 6091 uint8_t output_raw; /**< Raw data output */ 6092 } data; 6093 }; 6094 6095 enum dmub_cmd_fused_io_sub_type { 6096 DMUB_CMD__FUSED_IO_EXECUTE = 0, 6097 DMUB_CMD__FUSED_IO_ABORT = 1, 6098 }; 6099 6100 enum dmub_cmd_fused_request_type { 6101 FUSED_REQUEST_READ, 6102 FUSED_REQUEST_WRITE, 6103 FUSED_REQUEST_POLL, 6104 }; 6105 6106 enum dmub_cmd_fused_request_status { 6107 FUSED_REQUEST_STATUS_SUCCESS, 6108 FUSED_REQUEST_STATUS_BEGIN, 6109 FUSED_REQUEST_STATUS_SUBMIT, 6110 FUSED_REQUEST_STATUS_REPLY, 6111 FUSED_REQUEST_STATUS_POLL, 6112 FUSED_REQUEST_STATUS_ABORTED, 6113 FUSED_REQUEST_STATUS_FAILED = 0x80, 6114 FUSED_REQUEST_STATUS_INVALID, 6115 FUSED_REQUEST_STATUS_BUSY, 6116 FUSED_REQUEST_STATUS_TIMEOUT, 6117 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 6118 }; 6119 6120 struct dmub_cmd_fused_request { 6121 uint8_t status; 6122 uint8_t type : 2; 6123 uint8_t _reserved0 : 3; 6124 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 6125 uint8_t identifier; 6126 uint8_t _reserved1; 6127 uint32_t timeout_us; 6128 union dmub_cmd_fused_request_location { 6129 struct dmub_cmd_fused_request_location_i2c { 6130 uint8_t is_aux : 1; // False 6131 uint8_t ddc_line : 3; 6132 uint8_t over_aux : 1; 6133 uint8_t _reserved0 : 3; 6134 uint8_t address; 6135 uint8_t offset; 6136 uint8_t length; 6137 } i2c; 6138 struct dmub_cmd_fused_request_location_aux { 6139 uint32_t is_aux : 1; // True 6140 uint32_t ddc_line : 3; 6141 uint32_t address : 20; 6142 uint32_t length : 8; // Automatically split into 16B transactions 6143 } aux; 6144 } u; 6145 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 6146 }; 6147 6148 struct dmub_rb_cmd_fused_io { 6149 struct dmub_cmd_header header; 6150 struct dmub_cmd_fused_request request; 6151 }; 6152 6153 /** 6154 * Command type of a DMUB_CMD__SECURE_DISPLAY command 6155 */ 6156 enum dmub_cmd_secure_display_type { 6157 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 6158 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 6159 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 6160 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 6161 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 6162 }; 6163 6164 #define MAX_ROI_NUM 2 6165 6166 struct dmub_cmd_roi_info { 6167 uint16_t x_start; 6168 uint16_t x_end; 6169 uint16_t y_start; 6170 uint16_t y_end; 6171 uint8_t otg_id; 6172 uint8_t phy_id; 6173 }; 6174 6175 struct dmub_cmd_roi_window_ctl { 6176 uint16_t x_start; 6177 uint16_t x_end; 6178 uint16_t y_start; 6179 uint16_t y_end; 6180 bool enable; 6181 }; 6182 6183 struct dmub_cmd_roi_ctl_info { 6184 uint8_t otg_id; 6185 uint8_t phy_id; 6186 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 6187 }; 6188 6189 /** 6190 * Definition of a DMUB_CMD__SECURE_DISPLAY command 6191 */ 6192 struct dmub_rb_cmd_secure_display { 6193 struct dmub_cmd_header header; 6194 /** 6195 * Data passed from driver to dmub firmware. 6196 */ 6197 struct dmub_cmd_roi_info roi_info; 6198 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 6199 }; 6200 6201 /** 6202 * Command type of a DMUB_CMD__PSP command 6203 */ 6204 enum dmub_cmd_psp_type { 6205 DMUB_CMD__PSP_ASSR_ENABLE = 0 6206 }; 6207 6208 /** 6209 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 6210 */ 6211 struct dmub_cmd_assr_enable_data { 6212 /** 6213 * ASSR enable or disable. 6214 */ 6215 uint8_t enable; 6216 /** 6217 * PHY port type. 6218 * Indicates eDP / non-eDP port type 6219 */ 6220 uint8_t phy_port_type; 6221 /** 6222 * PHY port ID. 6223 */ 6224 uint8_t phy_port_id; 6225 /** 6226 * Link encoder index. 6227 */ 6228 uint8_t link_enc_index; 6229 /** 6230 * HPO mode. 6231 */ 6232 uint8_t hpo_mode; 6233 6234 /** 6235 * Reserved field. 6236 */ 6237 uint8_t reserved[7]; 6238 }; 6239 6240 /** 6241 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6242 */ 6243 struct dmub_rb_cmd_assr_enable { 6244 /** 6245 * Command header. 6246 */ 6247 struct dmub_cmd_header header; 6248 6249 /** 6250 * Assr data. 6251 */ 6252 struct dmub_cmd_assr_enable_data assr_data; 6253 6254 /** 6255 * Reserved field. 6256 */ 6257 uint32_t reserved[3]; 6258 }; 6259 6260 /** 6261 * Current definition of "ips_mode" from driver 6262 */ 6263 enum ips_residency_mode { 6264 IPS_RESIDENCY__IPS1_MAX, 6265 IPS_RESIDENCY__IPS2, 6266 IPS_RESIDENCY__IPS1_RCG, 6267 IPS_RESIDENCY__IPS1_ONO2_ON, 6268 IPS_RESIDENCY__IPS1_Z8_RETENTION, 6269 IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, 6270 IPS_RESIDENCY__PG_ONO_CURRENT_STATE 6271 }; 6272 6273 #define NUM_IPS_HISTOGRAM_BUCKETS 16 6274 6275 /** 6276 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 6277 */ 6278 struct dmub_ips_residency_info { 6279 uint32_t residency_millipercent; 6280 uint32_t entry_counter; 6281 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 6282 uint64_t total_time_us; 6283 uint64_t total_inactive_time_us; 6284 uint32_t ono_pg_state_at_collection; 6285 uint32_t ono_pg_state_last_seen_in_ips; 6286 }; 6287 6288 /** 6289 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 6290 */ 6291 struct dmub_cmd_ips_residency_cntl_data { 6292 uint8_t panel_inst; 6293 uint8_t start_measurement; 6294 uint8_t padding[2]; // align to 4-byte boundary 6295 }; 6296 6297 struct dmub_rb_cmd_ips_residency_cntl { 6298 struct dmub_cmd_header header; 6299 struct dmub_cmd_ips_residency_cntl_data cntl_data; 6300 }; 6301 6302 /** 6303 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 6304 */ 6305 struct dmub_cmd_ips_query_residency_info_data { 6306 union dmub_addr dest; 6307 uint32_t size; 6308 uint32_t ips_mode; 6309 uint8_t panel_inst; 6310 uint8_t padding[3]; // align to 4-byte boundary 6311 }; 6312 6313 struct dmub_rb_cmd_ips_query_residency_info { 6314 struct dmub_cmd_header header; 6315 struct dmub_cmd_ips_query_residency_info_data info_data; 6316 }; 6317 6318 /** 6319 * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command. 6320 */ 6321 struct dmub_cmd_cursor_offload_init_data { 6322 union dmub_addr state_addr; /**< State address for dmub_cursor_offload */ 6323 uint32_t state_size; /**< State size for dmub_cursor_offload */ 6324 }; 6325 6326 /** 6327 * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload. 6328 */ 6329 struct dmub_rb_cmd_cursor_offload_init { 6330 struct dmub_cmd_header header; 6331 struct dmub_cmd_cursor_offload_init_data init_data; 6332 }; 6333 6334 /** 6335 * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command. 6336 */ 6337 struct dmub_cmd_cursor_offload_stream_data { 6338 uint32_t otg_inst: 4; /**< OTG instance to control */ 6339 uint32_t reserved: 28; /**< Reserved for future use */ 6340 uint32_t line_time_in_ns; /**< Line time in ns for the OTG */ 6341 uint32_t v_total_max; /**< OTG v_total_max */ 6342 }; 6343 6344 /** 6345 * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload. 6346 */ 6347 struct dmub_rb_cmd_cursor_offload_stream_cntl { 6348 struct dmub_cmd_header header; 6349 struct dmub_cmd_cursor_offload_stream_data data; 6350 }; 6351 6352 /** 6353 * union dmub_rb_cmd - DMUB inbox command. 6354 */ 6355 union dmub_rb_cmd { 6356 /** 6357 * Elements shared with all commands. 6358 */ 6359 struct dmub_rb_cmd_common cmd_common; 6360 /** 6361 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 6362 */ 6363 struct dmub_rb_cmd_read_modify_write read_modify_write; 6364 /** 6365 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 6366 */ 6367 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 6368 /** 6369 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 6370 */ 6371 struct dmub_rb_cmd_burst_write burst_write; 6372 /** 6373 * Definition of a DMUB_CMD__REG_REG_WAIT command. 6374 */ 6375 struct dmub_rb_cmd_reg_wait reg_wait; 6376 /** 6377 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 6378 */ 6379 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 6380 /** 6381 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 6382 */ 6383 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 6384 /** 6385 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 6386 */ 6387 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 6388 /** 6389 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 6390 */ 6391 struct dmub_rb_cmd_dpphy_init dpphy_init; 6392 /** 6393 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 6394 */ 6395 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 6396 /** 6397 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 6398 */ 6399 struct dmub_rb_cmd_domain_control domain_control; 6400 /** 6401 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 6402 */ 6403 struct dmub_rb_cmd_psr_set_version psr_set_version; 6404 /** 6405 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 6406 */ 6407 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 6408 /** 6409 * Definition of a DMUB_CMD__PSR_ENABLE command. 6410 */ 6411 struct dmub_rb_cmd_psr_enable psr_enable; 6412 /** 6413 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 6414 */ 6415 struct dmub_rb_cmd_psr_set_level psr_set_level; 6416 /** 6417 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 6418 */ 6419 struct dmub_rb_cmd_psr_force_static psr_force_static; 6420 /** 6421 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 6422 */ 6423 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6424 /** 6425 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6426 */ 6427 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6428 /** 6429 * Definition of a DMUB_CMD__HW_LOCK command. 6430 * Command is used by driver and FW. 6431 */ 6432 struct dmub_rb_cmd_lock_hw lock_hw; 6433 /** 6434 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6435 */ 6436 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6437 /** 6438 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6439 */ 6440 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6441 /** 6442 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6443 */ 6444 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6445 /** 6446 * Definition of a DMUB_CMD__MALL command. 6447 */ 6448 struct dmub_rb_cmd_mall mall; 6449 6450 /** 6451 * Definition of a DMUB_CMD__CAB command. 6452 */ 6453 struct dmub_rb_cmd_cab_for_ss cab; 6454 6455 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6456 6457 /** 6458 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6459 */ 6460 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6461 6462 /** 6463 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6464 */ 6465 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6466 6467 /** 6468 * Definition of DMUB_CMD__PANEL_CNTL commands. 6469 */ 6470 struct dmub_rb_cmd_panel_cntl panel_cntl; 6471 6472 /** 6473 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6474 */ 6475 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6476 6477 /** 6478 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6479 */ 6480 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6481 6482 /** 6483 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6484 */ 6485 struct dmub_rb_cmd_abm_set_level abm_set_level; 6486 6487 /** 6488 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6489 */ 6490 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6491 6492 /** 6493 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6494 */ 6495 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6496 6497 /** 6498 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6499 */ 6500 struct dmub_rb_cmd_abm_init_config abm_init_config; 6501 6502 /** 6503 * Definition of a DMUB_CMD__ABM_PAUSE command. 6504 */ 6505 struct dmub_rb_cmd_abm_pause abm_pause; 6506 6507 /** 6508 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6509 */ 6510 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6511 6512 /** 6513 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6514 */ 6515 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6516 6517 /** 6518 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6519 */ 6520 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6521 6522 /** 6523 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6524 */ 6525 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6526 6527 /** 6528 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6529 */ 6530 struct dmub_rb_cmd_abm_set_event abm_set_event; 6531 6532 /** 6533 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6534 */ 6535 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6536 6537 /** 6538 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6539 */ 6540 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6541 6542 /** 6543 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6544 */ 6545 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6546 6547 /** 6548 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6549 */ 6550 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6551 struct dmub_rb_cmd_drr_update drr_update; 6552 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6553 6554 /** 6555 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6556 */ 6557 struct dmub_rb_cmd_lvtma_control lvtma_control; 6558 /** 6559 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6560 */ 6561 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6562 /** 6563 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6564 */ 6565 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6566 /** 6567 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6568 */ 6569 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6570 /** 6571 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6572 */ 6573 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6574 /** 6575 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6576 */ 6577 struct dmub_rb_cmd_set_config_request set_config_request; 6578 /** 6579 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6580 */ 6581 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6582 /** 6583 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6584 */ 6585 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6586 /** 6587 * Definition of a DMUB_CMD__EDID_CEA command. 6588 */ 6589 struct dmub_rb_cmd_edid_cea edid_cea; 6590 /** 6591 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6592 */ 6593 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6594 6595 /** 6596 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6597 */ 6598 struct dmub_rb_cmd_query_hpd_state query_hpd; 6599 /** 6600 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6601 */ 6602 struct dmub_rb_cmd_secure_display secure_display; 6603 6604 /** 6605 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6606 */ 6607 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6608 /** 6609 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6610 */ 6611 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6612 /** 6613 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6614 */ 6615 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6616 /** 6617 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 6618 */ 6619 struct dmub_rb_cmd_replay_set_version replay_set_version; 6620 /* 6621 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6622 */ 6623 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6624 /** 6625 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6626 */ 6627 struct dmub_rb_cmd_replay_enable replay_enable; 6628 /** 6629 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6630 */ 6631 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6632 /** 6633 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6634 */ 6635 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6636 /** 6637 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6638 */ 6639 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6640 6641 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6642 /** 6643 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6644 */ 6645 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6646 /** 6647 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6648 */ 6649 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6650 /** 6651 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6652 */ 6653 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6654 /** 6655 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6656 */ 6657 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6658 /** 6659 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6660 */ 6661 struct dmub_rb_cmd_assr_enable assr_enable; 6662 6663 struct dmub_rb_cmd_fams2 fams2_config; 6664 6665 struct dmub_rb_cmd_ib ib_fams2_config; 6666 6667 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6668 6669 struct dmub_rb_cmd_fams2_flip fams2_flip; 6670 6671 struct dmub_rb_cmd_fused_io fused_io; 6672 6673 /** 6674 * Definition of a DMUB_CMD__LSDMA command. 6675 */ 6676 struct dmub_rb_cmd_lsdma lsdma; 6677 6678 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 6679 6680 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 6681 /** 6682 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command. 6683 */ 6684 struct dmub_rb_cmd_cursor_offload_init cursor_offload_init; 6685 /** 6686 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands. 6687 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE 6688 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE 6689 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM 6690 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR 6691 */ 6692 struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; 6693 /** 6694 * Definition of a DMUB_CMD__SMART_POWER_HDR_ENABLE command. 6695 */ 6696 struct dmub_rb_cmd_smart_power_hdr_enable smart_power_hdr_enable; 6697 /** 6698 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. 6699 */ 6700 struct dmub_rb_cmd_smart_power_hdr_getmaxcll smart_power_hdr_getmaxcll; 6701 }; 6702 6703 /** 6704 * union dmub_rb_out_cmd - Outbox command 6705 */ 6706 union dmub_rb_out_cmd { 6707 /** 6708 * Parameters common to every command. 6709 */ 6710 struct dmub_rb_cmd_common cmd_common; 6711 /** 6712 * AUX reply command. 6713 */ 6714 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6715 /** 6716 * HPD notify command. 6717 */ 6718 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6719 /** 6720 * SET_CONFIG reply command. 6721 */ 6722 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6723 /** 6724 * DPIA notification command. 6725 */ 6726 struct dmub_rb_cmd_dpia_notification dpia_notification; 6727 /** 6728 * HPD sense notification command. 6729 */ 6730 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6731 struct dmub_rb_cmd_fused_io fused_io; 6732 }; 6733 #pragma pack(pop) 6734 6735 6736 //============================================================================== 6737 //</DMUB_CMD>=================================================================== 6738 //============================================================================== 6739 //< DMUB_RB>==================================================================== 6740 //============================================================================== 6741 6742 /** 6743 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6744 */ 6745 struct dmub_rb_init_params { 6746 void *ctx; /**< Caller provided context pointer */ 6747 void *base_address; /**< CPU base address for ring's data */ 6748 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6749 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6750 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6751 }; 6752 6753 /** 6754 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6755 */ 6756 struct dmub_rb { 6757 void *base_address; /**< CPU address for the ring's data */ 6758 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6759 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6760 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6761 6762 void *ctx; /**< Caller provided context pointer */ 6763 void *dmub; /**< Pointer to the DMUB interface */ 6764 }; 6765 6766 /** 6767 * @brief Checks if the ringbuffer is empty. 6768 * 6769 * @param rb DMUB Ringbuffer 6770 * @return true if empty 6771 * @return false otherwise 6772 */ 6773 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6774 { 6775 return (rb->wrpt == rb->rptr); 6776 } 6777 6778 /** 6779 * @brief gets number of outstanding requests in the RB 6780 * 6781 * @param rb DMUB Ringbuffer 6782 * @return true if full 6783 */ 6784 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6785 { 6786 uint32_t data_count; 6787 6788 if (rb->wrpt >= rb->rptr) 6789 data_count = rb->wrpt - rb->rptr; 6790 else 6791 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6792 6793 return data_count / DMUB_RB_CMD_SIZE; 6794 } 6795 6796 /** 6797 * @brief gets number of free buffers in the RB 6798 * 6799 * @param rb DMUB Ringbuffer 6800 * @return true if full 6801 */ 6802 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6803 { 6804 uint32_t data_count; 6805 6806 if (rb->wrpt >= rb->rptr) 6807 data_count = rb->wrpt - rb->rptr; 6808 else 6809 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6810 6811 /* +1 because 1 entry is always unusable */ 6812 data_count += DMUB_RB_CMD_SIZE; 6813 6814 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6815 } 6816 6817 /** 6818 * @brief Checks if the ringbuffer is full 6819 * 6820 * @param rb DMUB Ringbuffer 6821 * @return true if full 6822 * @return false otherwise 6823 */ 6824 static inline bool dmub_rb_full(struct dmub_rb *rb) 6825 { 6826 uint32_t data_count; 6827 6828 if (rb->wrpt >= rb->rptr) 6829 data_count = rb->wrpt - rb->rptr; 6830 else 6831 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6832 6833 /* -1 because 1 entry is always unusable */ 6834 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6835 } 6836 6837 /** 6838 * @brief Pushes a command into the ringbuffer 6839 * 6840 * @param rb DMUB ringbuffer 6841 * @param cmd The command to push 6842 * @return true if the ringbuffer was not full 6843 * @return false otherwise 6844 */ 6845 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6846 const union dmub_rb_cmd *cmd) 6847 { 6848 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6849 const uint8_t *src = (const uint8_t *)cmd; 6850 uint8_t i; 6851 6852 if (rb->capacity == 0) 6853 return false; 6854 6855 if (dmub_rb_full(rb)) 6856 return false; 6857 6858 // copying data 6859 for (i = 0; i < DMUB_RB_CMD_SIZE; i++) 6860 *dst++ = *src++; 6861 6862 rb->wrpt += DMUB_RB_CMD_SIZE; 6863 6864 if (rb->wrpt >= rb->capacity) 6865 rb->wrpt %= rb->capacity; 6866 6867 return true; 6868 } 6869 6870 /** 6871 * @brief Pushes a command into the DMUB outbox ringbuffer 6872 * 6873 * @param rb DMUB outbox ringbuffer 6874 * @param cmd Outbox command 6875 * @return true if not full 6876 * @return false otherwise 6877 */ 6878 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6879 const union dmub_rb_out_cmd *cmd) 6880 { 6881 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6882 const uint8_t *src = (const uint8_t *)cmd; 6883 6884 if (rb->capacity == 0) 6885 return false; 6886 6887 if (dmub_rb_full(rb)) 6888 return false; 6889 6890 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6891 6892 rb->wrpt += DMUB_RB_CMD_SIZE; 6893 6894 if (rb->wrpt >= rb->capacity) 6895 rb->wrpt %= rb->capacity; 6896 6897 return true; 6898 } 6899 6900 /** 6901 * @brief Returns the next unprocessed command in the ringbuffer. 6902 * 6903 * @param rb DMUB ringbuffer 6904 * @param cmd The command to return 6905 * @return true if not empty 6906 * @return false otherwise 6907 */ 6908 static inline bool dmub_rb_front(struct dmub_rb *rb, 6909 union dmub_rb_cmd **cmd) 6910 { 6911 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6912 6913 if (dmub_rb_empty(rb)) 6914 return false; 6915 6916 *cmd = (union dmub_rb_cmd *)rb_cmd; 6917 6918 return true; 6919 } 6920 6921 /** 6922 * @brief Determines the next ringbuffer offset. 6923 * 6924 * @param rb DMUB inbox ringbuffer 6925 * @param num_cmds Number of commands 6926 * @param next_rptr The next offset in the ringbuffer 6927 */ 6928 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6929 uint32_t num_cmds, 6930 uint32_t *next_rptr) 6931 { 6932 if (rb->capacity == 0) 6933 return; 6934 6935 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6936 6937 if (*next_rptr >= rb->capacity) 6938 *next_rptr %= rb->capacity; 6939 } 6940 6941 /** 6942 * @brief Returns a pointer to a command in the inbox. 6943 * 6944 * @param rb DMUB inbox ringbuffer 6945 * @param cmd The inbox command to return 6946 * @param rptr The ringbuffer offset 6947 * @return true if not empty 6948 * @return false otherwise 6949 */ 6950 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6951 union dmub_rb_cmd **cmd, 6952 uint32_t rptr) 6953 { 6954 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6955 6956 if (dmub_rb_empty(rb)) 6957 return false; 6958 6959 *cmd = (union dmub_rb_cmd *)rb_cmd; 6960 6961 return true; 6962 } 6963 6964 /** 6965 * @brief Returns the next unprocessed command in the outbox. 6966 * 6967 * @param rb DMUB outbox ringbuffer 6968 * @param cmd The outbox command to return 6969 * @return true if not empty 6970 * @return false otherwise 6971 */ 6972 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6973 union dmub_rb_out_cmd *cmd) 6974 { 6975 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6976 uint64_t *dst = (uint64_t *)cmd; 6977 uint8_t i; 6978 6979 if (dmub_rb_empty(rb)) 6980 return false; 6981 6982 // copying data 6983 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6984 *dst++ = *src++; 6985 6986 return true; 6987 } 6988 6989 /** 6990 * @brief Removes the front entry in the ringbuffer. 6991 * 6992 * @param rb DMUB ringbuffer 6993 * @return true if the command was removed 6994 * @return false if there were no commands 6995 */ 6996 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6997 { 6998 if (rb->capacity == 0) 6999 return false; 7000 7001 if (dmub_rb_empty(rb)) 7002 return false; 7003 7004 rb->rptr += DMUB_RB_CMD_SIZE; 7005 7006 if (rb->rptr >= rb->capacity) 7007 rb->rptr %= rb->capacity; 7008 7009 return true; 7010 } 7011 7012 /** 7013 * @brief Flushes commands in the ringbuffer to framebuffer memory. 7014 * 7015 * Avoids a race condition where DMCUB accesses memory while 7016 * there are still writes in flight to framebuffer. 7017 * 7018 * @param rb DMUB ringbuffer 7019 */ 7020 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 7021 { 7022 uint32_t rptr = rb->rptr; 7023 uint32_t wptr = rb->wrpt; 7024 7025 if (rb->capacity == 0) 7026 return; 7027 7028 while (rptr != wptr) { 7029 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 7030 uint8_t i; 7031 7032 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 7033 (void)READ_ONCE(*data++); 7034 7035 rptr += DMUB_RB_CMD_SIZE; 7036 if (rptr >= rb->capacity) 7037 rptr %= rb->capacity; 7038 } 7039 } 7040 7041 /** 7042 * @brief Initializes a DMCUB ringbuffer 7043 * 7044 * @param rb DMUB ringbuffer 7045 * @param init_params initial configuration for the ringbuffer 7046 */ 7047 static inline void dmub_rb_init(struct dmub_rb *rb, 7048 struct dmub_rb_init_params *init_params) 7049 { 7050 rb->base_address = init_params->base_address; 7051 rb->capacity = init_params->capacity; 7052 rb->rptr = init_params->read_ptr; 7053 rb->wrpt = init_params->write_ptr; 7054 } 7055 7056 /** 7057 * @brief Copies output data from in/out commands into the given command. 7058 * 7059 * @param rb DMUB ringbuffer 7060 * @param cmd Command to copy data into 7061 */ 7062 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 7063 union dmub_rb_cmd *cmd) 7064 { 7065 // Copy rb entry back into command 7066 uint8_t *rd_ptr = (rb->rptr == 0) ? 7067 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 7068 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 7069 7070 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 7071 } 7072 7073 //============================================================================== 7074 //</DMUB_RB>==================================================================== 7075 //============================================================================== 7076 #endif /* _DMUB_CMD_H_ */ 7077