1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310 struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326 }; 327 #pragma pack(pop) 328 329 /** 330 * Dirty rect definition. 331 */ 332 struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352 }; 353 354 /** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357 union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397 }; 398 399 /** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402 union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 uint32_t reserved : 18; 489 } bitfields; 490 491 uint32_t u32All; 492 }; 493 494 /** 495 * Flags record error state. 496 */ 497 union replay_visual_confirm_error_state_flags { 498 struct { 499 /** 500 * 0x1 (bit 0) - Desync Error flag. 501 */ 502 uint32_t desync_error : 1; 503 504 /** 505 * 0x2 (bit 1) - State Transition Error flag. 506 */ 507 uint32_t state_transition_error : 1; 508 509 /** 510 * 0x4 (bit 2) - Crc Error flag 511 */ 512 uint32_t crc_error : 1; 513 514 /** 515 * 0x8 (bit 3) - Reserved 516 */ 517 uint32_t reserved_3 : 1; 518 519 /** 520 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 521 * Added new debug flag to control DPCD. 522 */ 523 uint32_t incorrect_vtotal_in_static_screen : 1; 524 525 /** 526 * 0x20 (bit 5) - No doubled Refresh Rate. 527 */ 528 uint32_t no_double_rr : 1; 529 530 /** 531 * Reserved bit 6-7 532 */ 533 uint32_t reserved_6_7 : 2; 534 535 /** 536 * Reserved bit 9-31 537 */ 538 uint32_t reserved_9_31 : 24; 539 } bitfields; 540 541 uint32_t u32All; 542 }; 543 544 union replay_hw_flags { 545 struct { 546 /** 547 * @allow_alpm_fw_standby_mode: To indicate whether the 548 * ALPM FW standby mode is allowed 549 */ 550 uint32_t allow_alpm_fw_standby_mode : 1; 551 552 /* 553 * @dsc_enable_status: DSC enable status in driver 554 */ 555 uint32_t dsc_enable_status : 1; 556 557 /** 558 * @fec_enable_status: receive fec enable/disable status from driver 559 */ 560 uint32_t fec_enable_status : 1; 561 562 /* 563 * @smu_optimizations_en: SMU power optimization. 564 * Only when active display is Replay capable and display enters Replay. 565 * Trigger interrupt to SMU to powerup/down. 566 */ 567 uint32_t smu_optimizations_en : 1; 568 569 /** 570 * @phy_power_state: Indicates current phy power state 571 */ 572 uint32_t phy_power_state : 1; 573 574 /** 575 * @link_power_state: Indicates current link power state 576 */ 577 uint32_t link_power_state : 1; 578 /** 579 * Use TPS3 signal when restore main link. 580 */ 581 uint32_t force_wakeup_by_tps3 : 1; 582 /** 583 * @is_alpm_initialized: Indicates whether ALPM is initialized 584 */ 585 uint32_t is_alpm_initialized : 1; 586 587 /** 588 * @alpm_mode: Indicates ALPM mode selected 589 */ 590 uint32_t alpm_mode : 2; 591 } bitfields; 592 593 uint32_t u32All; 594 }; 595 596 union fw_assisted_mclk_switch_version { 597 struct { 598 uint8_t minor : 5; 599 uint8_t major : 3; 600 }; 601 uint8_t ver; 602 }; 603 604 /** 605 * DMUB feature capabilities. 606 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 607 */ 608 struct dmub_feature_caps { 609 /** 610 * Max PSR version supported by FW. 611 */ 612 uint8_t psr; 613 uint8_t fw_assisted_mclk_switch_ver; 614 uint8_t reserved[4]; 615 uint8_t subvp_psr_support; 616 uint8_t gecc_enable; 617 uint8_t replay_supported; 618 uint8_t replay_reserved[3]; 619 uint8_t abm_aux_backlight_support; 620 }; 621 622 struct dmub_visual_confirm_color { 623 /** 624 * Maximum 10 bits color value 625 */ 626 uint16_t color_r_cr; 627 uint16_t color_g_y; 628 uint16_t color_b_cb; 629 uint16_t panel_inst; 630 }; 631 632 //============================================================================== 633 //</DMUB_TYPES>================================================================= 634 //============================================================================== 635 //< DMUB_META>================================================================== 636 //============================================================================== 637 #pragma pack(push, 1) 638 639 /* Magic value for identifying dmub_fw_meta_info */ 640 #define DMUB_FW_META_MAGIC 0x444D5542 641 642 /* Offset from the end of the file to the dmub_fw_meta_info */ 643 #define DMUB_FW_META_OFFSET 0x24 644 645 /** 646 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 647 */ 648 union dmub_fw_meta_feature_bits { 649 struct { 650 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 651 uint32_t reserved : 31; 652 } bits; /**< status bits */ 653 uint32_t all; /**< 32-bit access to status bits */ 654 }; 655 656 /** 657 * struct dmub_fw_meta_info - metadata associated with fw binary 658 * 659 * NOTE: This should be considered a stable API. Fields should 660 * not be repurposed or reordered. New fields should be 661 * added instead to extend the structure. 662 * 663 * @magic_value: magic value identifying DMUB firmware meta info 664 * @fw_region_size: size of the firmware state region 665 * @trace_buffer_size: size of the tracebuffer region 666 * @fw_version: the firmware version information 667 * @dal_fw: 1 if the firmware is DAL 668 * @shared_state_size: size of the shared state region in bytes 669 * @shared_state_features: number of shared state features 670 */ 671 struct dmub_fw_meta_info { 672 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 673 uint32_t fw_region_size; /**< size of the firmware state region */ 674 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 675 uint32_t fw_version; /**< the firmware version information */ 676 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 677 uint8_t reserved[3]; /**< padding bits */ 678 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 679 uint16_t shared_state_features; /**< number of shared state features */ 680 uint16_t reserved2; /**< padding bytes */ 681 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 682 }; 683 684 /** 685 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 686 */ 687 union dmub_fw_meta { 688 struct dmub_fw_meta_info info; /**< metadata info */ 689 uint8_t reserved[64]; /**< padding bits */ 690 }; 691 692 #pragma pack(pop) 693 694 //============================================================================== 695 //< DMUB Trace Buffer>================================================================ 696 //============================================================================== 697 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 698 /** 699 * dmub_trace_code_t - firmware trace code, 32-bits 700 */ 701 typedef uint32_t dmub_trace_code_t; 702 703 /** 704 * struct dmcub_trace_buf_entry - Firmware trace entry 705 */ 706 struct dmcub_trace_buf_entry { 707 dmub_trace_code_t trace_code; /**< trace code for the event */ 708 uint32_t tick_count; /**< the tick count at time of trace */ 709 uint32_t param0; /**< trace defined parameter 0 */ 710 uint32_t param1; /**< trace defined parameter 1 */ 711 }; 712 #endif 713 714 //============================================================================== 715 //< DMUB_STATUS>================================================================ 716 //============================================================================== 717 718 /** 719 * DMCUB scratch registers can be used to determine firmware status. 720 * Current scratch register usage is as follows: 721 * 722 * SCRATCH0: FW Boot Status register 723 * SCRATCH5: LVTMA Status Register 724 * SCRATCH15: FW Boot Options register 725 */ 726 727 /** 728 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 729 */ 730 union dmub_fw_boot_status { 731 struct { 732 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 733 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 734 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 735 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 736 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 737 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 738 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 739 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 740 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 741 } bits; /**< status bits */ 742 uint32_t all; /**< 32-bit access to status bits */ 743 }; 744 745 /** 746 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 747 */ 748 enum dmub_fw_boot_status_bit { 749 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 750 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 751 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 752 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 753 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 754 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 755 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 756 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 757 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 758 }; 759 760 /* Register bit definition for SCRATCH5 */ 761 union dmub_lvtma_status { 762 struct { 763 uint32_t psp_ok : 1; 764 uint32_t edp_on : 1; 765 uint32_t reserved : 30; 766 } bits; 767 uint32_t all; 768 }; 769 770 enum dmub_lvtma_status_bit { 771 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 772 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 773 }; 774 775 enum dmub_ips_disable_type { 776 DMUB_IPS_ENABLE = 0, 777 DMUB_IPS_DISABLE_ALL = 1, 778 DMUB_IPS_DISABLE_IPS1 = 2, 779 DMUB_IPS_DISABLE_IPS2 = 3, 780 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 781 DMUB_IPS_DISABLE_DYNAMIC = 5, 782 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 783 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 784 }; 785 786 enum dmub_ips_rcg_disable_type { 787 DMUB_IPS_RCG_ENABLE = 0, 788 DMUB_IPS0_RCG_DISABLE = 1, 789 DMUB_IPS1_RCG_DISABLE = 2, 790 DMUB_IPS_RCG_DISABLE = 3 791 }; 792 793 #define DMUB_IPS1_ALLOW_MASK 0x00000001 794 #define DMUB_IPS2_ALLOW_MASK 0x00000002 795 #define DMUB_IPS1_COMMIT_MASK 0x00000004 796 #define DMUB_IPS2_COMMIT_MASK 0x00000008 797 798 enum dmub_ips_comand_type { 799 /** 800 * Start/stop IPS residency measurements for a given IPS mode 801 */ 802 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 803 /** 804 * Query IPS residency information for a given IPS mode 805 */ 806 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 807 }; 808 809 /** 810 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 811 */ 812 union dmub_fw_boot_options { 813 struct { 814 uint32_t pemu_env : 1; /**< 1 if PEMU */ 815 uint32_t fpga_env : 1; /**< 1 if FPGA */ 816 uint32_t optimized_init : 1; /**< 1 if optimized init */ 817 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 818 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 819 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 820 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 821 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 822 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 823 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 824 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 825 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 826 uint32_t power_optimization: 1; 827 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 828 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 829 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 830 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 831 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 832 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 833 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 834 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 835 uint32_t ips_disable: 3; /* options to disable ips support*/ 836 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 837 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 838 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 839 uint32_t reserved : 6; /**< reserved */ 840 } bits; /**< boot bits */ 841 uint32_t all; /**< 32-bit access to bits */ 842 }; 843 844 enum dmub_fw_boot_options_bit { 845 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 846 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 847 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 848 }; 849 850 //============================================================================== 851 //< DMUB_SHARED_STATE>========================================================== 852 //============================================================================== 853 854 /** 855 * Shared firmware state between driver and firmware for lockless communication 856 * in situations where the inbox/outbox may be unavailable. 857 * 858 * Each structure *must* be at most 256-bytes in size. The layout allocation is 859 * described below: 860 * 861 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 862 */ 863 864 /** 865 * enum dmub_shared_state_feature_id - List of shared state features. 866 */ 867 enum dmub_shared_state_feature_id { 868 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 869 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 870 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 871 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 872 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 873 }; 874 875 /** 876 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 877 */ 878 union dmub_shared_state_ips_fw_signals { 879 struct { 880 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 881 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 882 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 883 uint32_t detection_required : 1; /**< 1 if detection is required */ 884 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 885 uint32_t reserved_bits : 27; /**< Reversed */ 886 } bits; 887 uint32_t all; 888 }; 889 890 /** 891 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 892 */ 893 union dmub_shared_state_ips_driver_signals { 894 struct { 895 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 896 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 897 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 898 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 899 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 900 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 901 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 902 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 903 uint32_t reserved_bits : 24; /**< Reversed bits */ 904 } bits; 905 uint32_t all; 906 }; 907 908 /** 909 * IPS FW Version 910 */ 911 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 912 913 struct dmub_shared_state_debug_setup { 914 union { 915 struct { 916 uint32_t exclude_points[62]; 917 } profile_mode; 918 }; 919 }; 920 921 /** 922 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 923 */ 924 struct dmub_shared_state_ips_fw { 925 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 926 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 927 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 928 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 929 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 930 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 931 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 932 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 933 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 934 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 935 }; /* 248-bytes, fixed */ 936 937 /** 938 * IPS Driver Version 939 */ 940 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 941 942 /** 943 * struct dmub_shared_state_ips_driver - Driver state for IPS. 944 */ 945 struct dmub_shared_state_ips_driver { 946 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 947 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 948 }; /* 248-bytes, fixed */ 949 950 /** 951 * enum dmub_shared_state_feature_common - Generic payload. 952 */ 953 struct dmub_shared_state_feature_common { 954 uint32_t padding[62]; 955 }; /* 248-bytes, fixed */ 956 957 /** 958 * enum dmub_shared_state_feature_header - Feature description. 959 */ 960 struct dmub_shared_state_feature_header { 961 uint16_t id; /**< Feature ID */ 962 uint16_t version; /**< Feature version */ 963 uint32_t reserved; /**< Reserved bytes. */ 964 }; /* 8 bytes, fixed */ 965 966 /** 967 * struct dmub_shared_state_feature_block - Feature block. 968 */ 969 struct dmub_shared_state_feature_block { 970 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 971 union dmub_shared_feature_state_union { 972 struct dmub_shared_state_feature_common common; /**< Generic data */ 973 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 974 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 975 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 976 } data; /**< Shared state data. */ 977 }; /* 256-bytes, fixed */ 978 979 /** 980 * Shared state size in bytes. 981 */ 982 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 983 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 984 985 //============================================================================== 986 //</DMUB_STATUS>================================================================ 987 //============================================================================== 988 //< DMUB_VBIOS>================================================================= 989 //============================================================================== 990 991 /* 992 * enum dmub_cmd_vbios_type - VBIOS commands. 993 * 994 * Command IDs should be treated as stable ABI. 995 * Do not reuse or modify IDs. 996 */ 997 enum dmub_cmd_vbios_type { 998 /** 999 * Configures the DIG encoder. 1000 */ 1001 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1002 /** 1003 * Controls the PHY. 1004 */ 1005 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1006 /** 1007 * Sets the pixel clock/symbol clock. 1008 */ 1009 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1010 /** 1011 * Enables or disables power gating. 1012 */ 1013 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1014 /** 1015 * Controls embedded panels. 1016 */ 1017 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1018 /** 1019 * Query DP alt status on a transmitter. 1020 */ 1021 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1022 /** 1023 * Control PHY FSM 1024 */ 1025 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1026 /** 1027 * Controls domain power gating 1028 */ 1029 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1030 }; 1031 1032 //============================================================================== 1033 //</DMUB_VBIOS>================================================================= 1034 //============================================================================== 1035 //< DMUB_GPINT>================================================================= 1036 //============================================================================== 1037 1038 /** 1039 * The shifts and masks below may alternatively be used to format and read 1040 * the command register bits. 1041 */ 1042 1043 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1044 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1045 1046 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1047 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1048 1049 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1050 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1051 1052 /** 1053 * Command responses. 1054 */ 1055 1056 /** 1057 * Return response for DMUB_GPINT__STOP_FW command. 1058 */ 1059 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1060 1061 /** 1062 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1063 */ 1064 union dmub_gpint_data_register { 1065 struct { 1066 uint32_t param : 16; /**< 16-bit parameter */ 1067 uint32_t command_code : 12; /**< GPINT command */ 1068 uint32_t status : 4; /**< Command status bit */ 1069 } bits; /**< GPINT bit access */ 1070 uint32_t all; /**< GPINT 32-bit access */ 1071 }; 1072 1073 /* 1074 * enum dmub_gpint_command - GPINT command to DMCUB FW 1075 * 1076 * Command IDs should be treated as stable ABI. 1077 * Do not reuse or modify IDs. 1078 */ 1079 enum dmub_gpint_command { 1080 /** 1081 * Invalid command, ignored. 1082 */ 1083 DMUB_GPINT__INVALID_COMMAND = 0, 1084 /** 1085 * DESC: Queries the firmware version. 1086 * RETURN: Firmware version. 1087 */ 1088 DMUB_GPINT__GET_FW_VERSION = 1, 1089 /** 1090 * DESC: Halts the firmware. 1091 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1092 */ 1093 DMUB_GPINT__STOP_FW = 2, 1094 /** 1095 * DESC: Get PSR state from FW. 1096 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1097 */ 1098 DMUB_GPINT__GET_PSR_STATE = 7, 1099 /** 1100 * DESC: Notifies DMCUB of the currently active streams. 1101 * ARGS: Stream mask, 1 bit per active stream index. 1102 */ 1103 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1104 /** 1105 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1106 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1107 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1108 * RETURN: PSR residency in milli-percent. 1109 */ 1110 DMUB_GPINT__PSR_RESIDENCY = 9, 1111 1112 /** 1113 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1114 */ 1115 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1116 1117 /** 1118 * DESC: Get REPLAY state from FW. 1119 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1120 */ 1121 DMUB_GPINT__GET_REPLAY_STATE = 13, 1122 1123 /** 1124 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1125 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1126 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1127 * RETURN: REPLAY residency in milli-percent. 1128 */ 1129 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1130 1131 /** 1132 * DESC: Copy bounding box to the host. 1133 * ARGS: Version of bounding box to copy 1134 * RETURN: Result of copying bounding box 1135 */ 1136 DMUB_GPINT__BB_COPY = 96, 1137 1138 /** 1139 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1140 * ARGS: The word3 for the 64 bit address 1141 */ 1142 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1143 1144 /** 1145 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1146 * ARGS: The word2 for the 64 bit address 1147 */ 1148 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1149 1150 /** 1151 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1152 * ARGS: The word1 for the 64 bit address 1153 */ 1154 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1155 1156 /** 1157 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1158 * ARGS: The word0 for the 64 bit address 1159 */ 1160 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1161 1162 /** 1163 * DESC: Updates the trace buffer lower 32-bit mask. 1164 * ARGS: The new mask 1165 * RETURN: Lower 32-bit mask. 1166 */ 1167 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1168 1169 /** 1170 * DESC: Updates the trace buffer mask bit0~bit15. 1171 * ARGS: The new mask 1172 * RETURN: Lower 32-bit mask. 1173 */ 1174 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1175 1176 /** 1177 * DESC: Updates the trace buffer mask bit16~bit31. 1178 * ARGS: The new mask 1179 * RETURN: Lower 32-bit mask. 1180 */ 1181 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1182 1183 /** 1184 * DESC: Updates the trace buffer mask bit32~bit47. 1185 * ARGS: The new mask 1186 * RETURN: Lower 32-bit mask. 1187 */ 1188 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1189 1190 /** 1191 * DESC: Updates the trace buffer mask bit48~bit63. 1192 * ARGS: The new mask 1193 * RETURN: Lower 32-bit mask. 1194 */ 1195 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1196 1197 /** 1198 * DESC: Read the trace buffer mask bi0~bit15. 1199 */ 1200 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1201 1202 /** 1203 * DESC: Read the trace buffer mask bit16~bit31. 1204 */ 1205 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1206 1207 /** 1208 * DESC: Read the trace buffer mask bi32~bit47. 1209 */ 1210 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1211 1212 /** 1213 * DESC: Updates the trace buffer mask bit32~bit63. 1214 */ 1215 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1216 1217 /** 1218 * DESC: Set IPS residency measurement 1219 * ARGS: 0 - Disable ips measurement 1220 * 1 - Enable ips measurement 1221 */ 1222 DMUB_GPINT__IPS_RESIDENCY = 121, 1223 1224 /** 1225 * DESC: Enable measurements for various task duration 1226 * ARGS: 0 - Disable measurement 1227 * 1 - Enable measurement 1228 */ 1229 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1230 1231 /** 1232 * DESC: Gets IPS residency in microseconds 1233 * ARGS: 0 - Return IPS1 residency 1234 * 1 - Return IPS2 residency 1235 * 2 - Return IPS1_RCG residency 1236 * 3 - Return IPS1_ONO2_ON residency 1237 * RETURN: Total residency in microseconds - lower 32 bits 1238 */ 1239 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1240 1241 /** 1242 * DESC: Gets IPS1 histogram counts 1243 * ARGS: Bucket index 1244 * RETURN: Total count for the bucket 1245 */ 1246 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1247 1248 /** 1249 * DESC: Gets IPS2 histogram counts 1250 * ARGS: Bucket index 1251 * RETURN: Total count for the bucket 1252 */ 1253 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1254 1255 /** 1256 * DESC: Gets IPS residency 1257 * ARGS: 0 - Return IPS1 residency 1258 * 1 - Return IPS2 residency 1259 * 2 - Return IPS1_RCG residency 1260 * 3 - Return IPS1_ONO2_ON residency 1261 * RETURN: Total residency in milli-percent. 1262 */ 1263 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1264 1265 /** 1266 * DESC: Gets IPS1_RCG histogram counts 1267 * ARGS: Bucket index 1268 * RETURN: Total count for the bucket 1269 */ 1270 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1271 1272 /** 1273 * DESC: Gets IPS1_ONO2_ON histogram counts 1274 * ARGS: Bucket index 1275 * RETURN: Total count for the bucket 1276 */ 1277 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1278 1279 /** 1280 * DESC: Gets IPS entry counter during residency measurement 1281 * ARGS: 0 - Return IPS1 entry counts 1282 * 1 - Return IPS2 entry counts 1283 * 2 - Return IPS1_RCG entry counts 1284 * 3 - Return IPS2_ONO2_ON entry counts 1285 * RETURN: Entry counter for selected IPS mode 1286 */ 1287 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1288 1289 /** 1290 * DESC: Gets IPS inactive residency in microseconds 1291 * ARGS: 0 - Return IPS1_MAX residency 1292 * 1 - Return IPS2 residency 1293 * 2 - Return IPS1_RCG residency 1294 * 3 - Return IPS1_ONO2_ON residency 1295 * RETURN: Total inactive residency in microseconds - lower 32 bits 1296 */ 1297 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1298 1299 /** 1300 * DESC: Gets IPS inactive residency in microseconds 1301 * ARGS: 0 - Return IPS1_MAX residency 1302 * 1 - Return IPS2 residency 1303 * 2 - Return IPS1_RCG residency 1304 * 3 - Return IPS1_ONO2_ON residency 1305 * RETURN: Total inactive residency in microseconds - upper 32 bits 1306 */ 1307 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1308 1309 /** 1310 * DESC: Gets IPS residency in microseconds 1311 * ARGS: 0 - Return IPS1 residency 1312 * 1 - Return IPS2 residency 1313 * 2 - Return IPS1_RCG residency 1314 * 3 - Return IPS1_ONO2_ON residency 1315 * RETURN: Total residency in microseconds - upper 32 bits 1316 */ 1317 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1318 /** 1319 * DESC: Setup debug configs. 1320 */ 1321 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1322 /** 1323 * DESC: Initiates IPS wake sequence. 1324 */ 1325 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1326 }; 1327 1328 /** 1329 * INBOX0 generic command definition 1330 */ 1331 union dmub_inbox0_cmd_common { 1332 struct { 1333 uint32_t command_code: 8; /**< INBOX0 command code */ 1334 uint32_t param: 24; /**< 24-bit parameter */ 1335 } bits; 1336 uint32_t all; 1337 }; 1338 1339 /** 1340 * INBOX0 hw_lock command definition 1341 */ 1342 union dmub_inbox0_cmd_lock_hw { 1343 struct { 1344 uint32_t command_code: 8; 1345 1346 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1347 uint32_t hw_lock_client: 2; 1348 1349 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1350 uint32_t otg_inst: 3; 1351 uint32_t opp_inst: 3; 1352 uint32_t dig_inst: 3; 1353 1354 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1355 uint32_t lock_pipe: 1; 1356 uint32_t lock_cursor: 1; 1357 uint32_t lock_dig: 1; 1358 uint32_t triple_buffer_lock: 1; 1359 1360 uint32_t lock: 1; /**< Lock */ 1361 uint32_t should_release: 1; /**< Release */ 1362 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1363 } bits; 1364 uint32_t all; 1365 }; 1366 1367 union dmub_inbox0_data_register { 1368 union dmub_inbox0_cmd_common inbox0_cmd_common; 1369 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1370 }; 1371 1372 enum dmub_inbox0_command { 1373 /** 1374 * DESC: Invalid command, ignored. 1375 */ 1376 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1377 /** 1378 * DESC: Notification to acquire/release HW lock 1379 * ARGS: 1380 */ 1381 DMUB_INBOX0_CMD__HW_LOCK = 1, 1382 }; 1383 //============================================================================== 1384 //</DMUB_GPINT>================================================================= 1385 //============================================================================== 1386 //< DMUB_CMD>=================================================================== 1387 //============================================================================== 1388 1389 /** 1390 * Size in bytes of each DMUB command. 1391 */ 1392 #define DMUB_RB_CMD_SIZE 64 1393 1394 /** 1395 * Maximum number of items in the DMUB ringbuffer. 1396 */ 1397 #define DMUB_RB_MAX_ENTRY 128 1398 1399 /** 1400 * Ringbuffer size in bytes. 1401 */ 1402 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1403 1404 /** 1405 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1406 */ 1407 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1408 1409 /** 1410 * Ringbuffer size in bytes. 1411 */ 1412 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1413 1414 /** 1415 * REG_SET mask for reg offload. 1416 */ 1417 #define REG_SET_MASK 0xFFFF 1418 1419 /* 1420 * enum dmub_cmd_type - DMUB inbox command. 1421 * 1422 * Command IDs should be treated as stable ABI. 1423 * Do not reuse or modify IDs. 1424 */ 1425 enum dmub_cmd_type { 1426 /** 1427 * Invalid command. 1428 */ 1429 DMUB_CMD__NULL = 0, 1430 /** 1431 * Read modify write register sequence offload. 1432 */ 1433 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1434 /** 1435 * Field update register sequence offload. 1436 */ 1437 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1438 /** 1439 * Burst write sequence offload. 1440 */ 1441 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1442 /** 1443 * Reg wait sequence offload. 1444 */ 1445 DMUB_CMD__REG_REG_WAIT = 4, 1446 /** 1447 * Workaround to avoid HUBP underflow during NV12 playback. 1448 */ 1449 DMUB_CMD__PLAT_54186_WA = 5, 1450 /** 1451 * Command type used to query FW feature caps. 1452 */ 1453 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1454 /** 1455 * Command type used to get visual confirm color. 1456 */ 1457 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1458 /** 1459 * Command type used for all PSR commands. 1460 */ 1461 DMUB_CMD__PSR = 64, 1462 /** 1463 * Command type used for all MALL commands. 1464 */ 1465 DMUB_CMD__MALL = 65, 1466 /** 1467 * Command type used for all ABM commands. 1468 */ 1469 DMUB_CMD__ABM = 66, 1470 /** 1471 * Command type used to update dirty rects in FW. 1472 */ 1473 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1474 /** 1475 * Command type used to update cursor info in FW. 1476 */ 1477 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1478 /** 1479 * Command type used for HW locking in FW. 1480 */ 1481 DMUB_CMD__HW_LOCK = 69, 1482 /** 1483 * Command type used to access DP AUX. 1484 */ 1485 DMUB_CMD__DP_AUX_ACCESS = 70, 1486 /** 1487 * Command type used for OUTBOX1 notification enable 1488 */ 1489 DMUB_CMD__OUTBOX1_ENABLE = 71, 1490 1491 /** 1492 * Command type used for all idle optimization commands. 1493 */ 1494 DMUB_CMD__IDLE_OPT = 72, 1495 /** 1496 * Command type used for all clock manager commands. 1497 */ 1498 DMUB_CMD__CLK_MGR = 73, 1499 /** 1500 * Command type used for all panel control commands. 1501 */ 1502 DMUB_CMD__PANEL_CNTL = 74, 1503 1504 /** 1505 * Command type used for all CAB commands. 1506 */ 1507 DMUB_CMD__CAB_FOR_SS = 75, 1508 1509 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1510 1511 /** 1512 * Command type used for interfacing with DPIA. 1513 */ 1514 DMUB_CMD__DPIA = 77, 1515 /** 1516 * Command type used for EDID CEA parsing 1517 */ 1518 DMUB_CMD__EDID_CEA = 79, 1519 /** 1520 * Command type used for getting usbc cable ID 1521 */ 1522 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1523 /** 1524 * Command type used to query HPD state. 1525 */ 1526 DMUB_CMD__QUERY_HPD_STATE = 82, 1527 /** 1528 * Command type used for all VBIOS interface commands. 1529 */ 1530 /** 1531 * Command type used for all REPLAY commands. 1532 */ 1533 DMUB_CMD__REPLAY = 83, 1534 1535 /** 1536 * Command type used for all SECURE_DISPLAY commands. 1537 */ 1538 DMUB_CMD__SECURE_DISPLAY = 85, 1539 1540 /** 1541 * Command type used to set DPIA HPD interrupt state 1542 */ 1543 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1544 1545 /** 1546 * Command type used for all PSP commands. 1547 */ 1548 DMUB_CMD__PSP = 88, 1549 1550 /** 1551 * Command type used for all Fused IO commands. 1552 */ 1553 DMUB_CMD__FUSED_IO = 89, 1554 1555 /** 1556 * Command type used for all LSDMA commands. 1557 */ 1558 DMUB_CMD__LSDMA = 90, 1559 1560 /** 1561 * Command type use for all IPS commands. 1562 */ 1563 DMUB_CMD__IPS = 91, 1564 1565 DMUB_CMD__VBIOS = 128, 1566 }; 1567 1568 /** 1569 * enum dmub_out_cmd_type - DMUB outbox commands. 1570 */ 1571 enum dmub_out_cmd_type { 1572 /** 1573 * Invalid outbox command, ignored. 1574 */ 1575 DMUB_OUT_CMD__NULL = 0, 1576 /** 1577 * Command type used for DP AUX Reply data notification 1578 */ 1579 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1580 /** 1581 * Command type used for DP HPD event notification 1582 */ 1583 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1584 /** 1585 * Command type used for SET_CONFIG Reply notification 1586 */ 1587 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1588 /** 1589 * Command type used for USB4 DPIA notification 1590 */ 1591 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1592 /** 1593 * Command type used for HPD redetect notification 1594 */ 1595 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1596 /** 1597 * Command type used for Fused IO notification 1598 */ 1599 DMUB_OUT_CMD__FUSED_IO = 7, 1600 }; 1601 1602 /* DMUB_CMD__DPIA command sub-types. */ 1603 enum dmub_cmd_dpia_type { 1604 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1605 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1606 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1607 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1608 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1609 }; 1610 1611 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1612 enum dmub_cmd_dpia_notification_type { 1613 DPIA_NOTIFY__BW_ALLOCATION = 0, 1614 }; 1615 1616 #pragma pack(push, 1) 1617 1618 /** 1619 * struct dmub_cmd_header - Common command header fields. 1620 */ 1621 struct dmub_cmd_header { 1622 unsigned int type : 8; /**< command type */ 1623 unsigned int sub_type : 8; /**< command sub type */ 1624 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1625 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1626 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1627 unsigned int reserved0 : 5; /**< reserved bits */ 1628 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1629 unsigned int reserved1 : 2; /**< reserved bits */ 1630 }; 1631 1632 /* 1633 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1634 * 1635 * 60 payload bytes can hold up to 5 sets of read modify writes, 1636 * each take 3 dwords. 1637 * 1638 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1639 * 1640 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1641 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1642 */ 1643 struct dmub_cmd_read_modify_write_sequence { 1644 uint32_t addr; /**< register address */ 1645 uint32_t modify_mask; /**< modify mask */ 1646 uint32_t modify_value; /**< modify value */ 1647 }; 1648 1649 /** 1650 * Maximum number of ops in read modify write sequence. 1651 */ 1652 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1653 1654 /** 1655 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1656 */ 1657 struct dmub_rb_cmd_read_modify_write { 1658 struct dmub_cmd_header header; /**< command header */ 1659 /** 1660 * Read modify write sequence. 1661 */ 1662 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1663 }; 1664 1665 /* 1666 * Update a register with specified masks and values sequeunce 1667 * 1668 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1669 * 1670 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1671 * 1672 * 1673 * USE CASE: 1674 * 1. auto-increment register where additional read would update pointer and produce wrong result 1675 * 2. toggle a bit without read in the middle 1676 */ 1677 1678 struct dmub_cmd_reg_field_update_sequence { 1679 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1680 uint32_t modify_value; /**< value to update with */ 1681 }; 1682 1683 /** 1684 * Maximum number of ops in field update sequence. 1685 */ 1686 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1687 1688 /** 1689 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1690 */ 1691 struct dmub_rb_cmd_reg_field_update_sequence { 1692 struct dmub_cmd_header header; /**< command header */ 1693 uint32_t addr; /**< register address */ 1694 /** 1695 * Field update sequence. 1696 */ 1697 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1698 }; 1699 1700 1701 /** 1702 * Maximum number of burst write values. 1703 */ 1704 #define DMUB_BURST_WRITE_VALUES__MAX 14 1705 1706 /* 1707 * struct dmub_rb_cmd_burst_write - Burst write 1708 * 1709 * support use case such as writing out LUTs. 1710 * 1711 * 60 payload bytes can hold up to 14 values to write to given address 1712 * 1713 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1714 */ 1715 struct dmub_rb_cmd_burst_write { 1716 struct dmub_cmd_header header; /**< command header */ 1717 uint32_t addr; /**< register start address */ 1718 /** 1719 * Burst write register values. 1720 */ 1721 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1722 }; 1723 1724 /** 1725 * struct dmub_rb_cmd_common - Common command header 1726 */ 1727 struct dmub_rb_cmd_common { 1728 struct dmub_cmd_header header; /**< command header */ 1729 /** 1730 * Padding to RB_CMD_SIZE 1731 */ 1732 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1733 }; 1734 1735 /** 1736 * struct dmub_cmd_reg_wait_data - Register wait data 1737 */ 1738 struct dmub_cmd_reg_wait_data { 1739 uint32_t addr; /**< Register address */ 1740 uint32_t mask; /**< Mask for register bits */ 1741 uint32_t condition_field_value; /**< Value to wait for */ 1742 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1743 }; 1744 1745 /** 1746 * struct dmub_rb_cmd_reg_wait - Register wait command 1747 */ 1748 struct dmub_rb_cmd_reg_wait { 1749 struct dmub_cmd_header header; /**< Command header */ 1750 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1751 }; 1752 1753 /** 1754 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1755 * 1756 * Reprograms surface parameters to avoid underflow. 1757 */ 1758 struct dmub_cmd_PLAT_54186_wa { 1759 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1760 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1761 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1762 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1763 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1764 struct { 1765 uint32_t hubp_inst : 4; /**< HUBP instance */ 1766 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1767 uint32_t immediate :1; /**< Immediate flip */ 1768 uint32_t vmid : 4; /**< VMID */ 1769 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1770 uint32_t reserved : 21; /**< Reserved */ 1771 } flip_params; /**< Pageflip parameters */ 1772 uint32_t reserved[9]; /**< Reserved bits */ 1773 }; 1774 1775 /** 1776 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1777 */ 1778 struct dmub_rb_cmd_PLAT_54186_wa { 1779 struct dmub_cmd_header header; /**< Command header */ 1780 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1781 }; 1782 1783 /** 1784 * enum dmub_cmd_mall_type - MALL commands 1785 */ 1786 enum dmub_cmd_mall_type { 1787 /** 1788 * Allows display refresh from MALL. 1789 */ 1790 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1791 /** 1792 * Disallows display refresh from MALL. 1793 */ 1794 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1795 /** 1796 * Cursor copy for MALL. 1797 */ 1798 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1799 /** 1800 * Controls DF requests. 1801 */ 1802 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1803 }; 1804 1805 /** 1806 * struct dmub_rb_cmd_mall - MALL command data. 1807 */ 1808 struct dmub_rb_cmd_mall { 1809 struct dmub_cmd_header header; /**< Common command header */ 1810 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1811 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1812 uint32_t tmr_delay; /**< Timer delay */ 1813 uint32_t tmr_scale; /**< Timer scale */ 1814 uint16_t cursor_width; /**< Cursor width in pixels */ 1815 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1816 uint16_t cursor_height; /**< Cursor height in pixels */ 1817 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1818 uint8_t debug_bits; /**< Debug bits */ 1819 1820 uint8_t reserved1; /**< Reserved bits */ 1821 uint8_t reserved2; /**< Reserved bits */ 1822 }; 1823 1824 /** 1825 * enum dmub_cmd_cab_type - CAB command data. 1826 */ 1827 enum dmub_cmd_cab_type { 1828 /** 1829 * No idle optimizations (i.e. no CAB) 1830 */ 1831 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1832 /** 1833 * No DCN requests for memory 1834 */ 1835 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1836 /** 1837 * Fit surfaces in CAB (i.e. CAB enable) 1838 */ 1839 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1840 /** 1841 * Do not fit surfaces in CAB (i.e. no CAB) 1842 */ 1843 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1844 }; 1845 1846 /** 1847 * struct dmub_rb_cmd_cab - CAB command data. 1848 */ 1849 struct dmub_rb_cmd_cab_for_ss { 1850 struct dmub_cmd_header header; 1851 uint8_t cab_alloc_ways; /* total number of ways */ 1852 uint8_t debug_bits; /* debug bits */ 1853 }; 1854 1855 /** 1856 * Enum for indicating which MCLK switch mode per pipe 1857 */ 1858 enum mclk_switch_mode { 1859 NONE = 0, 1860 FPO = 1, 1861 SUBVP = 2, 1862 VBLANK = 3, 1863 }; 1864 1865 /* Per pipe struct which stores the MCLK switch mode 1866 * data to be sent to DMUB. 1867 * Named "v2" for now -- once FPO and SUBVP are fully merged 1868 * the type name can be updated 1869 */ 1870 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1871 union { 1872 struct { 1873 uint32_t pix_clk_100hz; 1874 uint16_t main_vblank_start; 1875 uint16_t main_vblank_end; 1876 uint16_t mall_region_lines; 1877 uint16_t prefetch_lines; 1878 uint16_t prefetch_to_mall_start_lines; 1879 uint16_t processing_delay_lines; 1880 uint16_t htotal; // required to calculate line time for multi-display cases 1881 uint16_t vtotal; 1882 uint8_t main_pipe_index; 1883 uint8_t phantom_pipe_index; 1884 /* Since the microschedule is calculated in terms of OTG lines, 1885 * include any scaling factors to make sure when we get accurate 1886 * conversion when programming MALL_START_LINE (which is in terms 1887 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1888 * is 1/2 (numerator = 1, denominator = 2). 1889 */ 1890 uint8_t scale_factor_numerator; 1891 uint8_t scale_factor_denominator; 1892 uint8_t is_drr; 1893 uint8_t main_split_pipe_index; 1894 uint8_t phantom_split_pipe_index; 1895 } subvp_data; 1896 1897 struct { 1898 uint32_t pix_clk_100hz; 1899 uint16_t vblank_start; 1900 uint16_t vblank_end; 1901 uint16_t vstartup_start; 1902 uint16_t vtotal; 1903 uint16_t htotal; 1904 uint8_t vblank_pipe_index; 1905 uint8_t padding[1]; 1906 struct { 1907 uint8_t drr_in_use; 1908 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1909 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1910 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1911 uint8_t use_ramping; // Use ramping or not 1912 uint8_t drr_vblank_start_margin; 1913 } drr_info; // DRR considered as part of SubVP + VBLANK case 1914 } vblank_data; 1915 } pipe_config; 1916 1917 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1918 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1919 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1920 */ 1921 uint8_t mode; // enum mclk_switch_mode 1922 }; 1923 1924 /** 1925 * Config data for Sub-VP and FPO 1926 * Named "v2" for now -- once FPO and SUBVP are fully merged 1927 * the type name can be updated 1928 */ 1929 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1930 uint16_t watermark_a_cache; 1931 uint8_t vertical_int_margin_us; 1932 uint8_t pstate_allow_width_us; 1933 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1934 }; 1935 1936 /** 1937 * DMUB rb command definition for Sub-VP and FPO 1938 * Named "v2" for now -- once FPO and SUBVP are fully merged 1939 * the type name can be updated 1940 */ 1941 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1942 struct dmub_cmd_header header; 1943 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1944 }; 1945 1946 struct dmub_flip_addr_info { 1947 uint32_t surf_addr_lo; 1948 uint32_t surf_addr_c_lo; 1949 uint32_t meta_addr_lo; 1950 uint32_t meta_addr_c_lo; 1951 uint16_t surf_addr_hi; 1952 uint16_t surf_addr_c_hi; 1953 uint16_t meta_addr_hi; 1954 uint16_t meta_addr_c_hi; 1955 }; 1956 1957 struct dmub_fams2_flip_info { 1958 union { 1959 struct { 1960 uint8_t is_immediate: 1; 1961 } bits; 1962 uint8_t all; 1963 } config; 1964 uint8_t otg_inst; 1965 uint8_t pipe_mask; 1966 uint8_t pad; 1967 struct dmub_flip_addr_info addr_info; 1968 }; 1969 1970 struct dmub_rb_cmd_fams2_flip { 1971 struct dmub_cmd_header header; 1972 struct dmub_fams2_flip_info flip_info; 1973 }; 1974 1975 struct dmub_cmd_lsdma_data { 1976 union { 1977 struct lsdma_init_data { 1978 union dmub_addr gpu_addr_base; 1979 uint32_t ring_size; 1980 } init_data; 1981 struct lsdma_tiled_copy_data { 1982 uint32_t src_addr_lo; 1983 uint32_t src_addr_hi; 1984 uint32_t dst_addr_lo; 1985 uint32_t dst_addr_hi; 1986 1987 uint32_t src_x : 16; 1988 uint32_t src_y : 16; 1989 1990 uint32_t src_width : 16; 1991 uint32_t src_height : 16; 1992 1993 uint32_t dst_x : 16; 1994 uint32_t dst_y : 16; 1995 1996 uint32_t dst_width : 16; 1997 uint32_t dst_height : 16; 1998 1999 uint32_t rect_x : 16; 2000 uint32_t rect_y : 16; 2001 2002 uint32_t src_swizzle_mode : 5; 2003 uint32_t src_mip_max : 5; 2004 uint32_t src_mip_id : 5; 2005 uint32_t dst_mip_max : 5; 2006 uint32_t dst_swizzle_mode : 5; 2007 uint32_t dst_mip_id : 5; 2008 uint32_t tmz : 1; 2009 uint32_t dcc : 1; 2010 2011 uint32_t data_format : 6; 2012 uint32_t padding1 : 4; 2013 uint32_t dst_element_size : 3; 2014 uint32_t num_type : 3; 2015 uint32_t src_element_size : 3; 2016 uint32_t write_compress : 2; 2017 uint32_t cache_policy_dst : 2; 2018 uint32_t cache_policy_src : 2; 2019 uint32_t read_compress : 2; 2020 uint32_t src_dim : 2; 2021 uint32_t dst_dim : 2; 2022 uint32_t max_uncom : 1; 2023 2024 uint32_t max_com : 2; 2025 uint32_t padding : 30; 2026 } tiled_copy_data; 2027 struct lsdma_linear_copy_data { 2028 uint32_t count : 30; 2029 uint32_t cache_policy_dst : 2; 2030 2031 uint32_t tmz : 1; 2032 uint32_t cache_policy_src : 2; 2033 uint32_t padding : 29; 2034 2035 uint32_t src_lo; 2036 uint32_t src_hi; 2037 uint32_t dst_lo; 2038 uint32_t dst_hi; 2039 } linear_copy_data; 2040 struct lsdma_reg_write_data { 2041 uint32_t reg_addr; 2042 uint32_t reg_data; 2043 } reg_write_data; 2044 struct lsdma_pio_copy_data { 2045 union { 2046 struct { 2047 uint32_t byte_count : 26; 2048 uint32_t src_loc : 1; 2049 uint32_t dst_loc : 1; 2050 uint32_t src_addr_inc : 1; 2051 uint32_t dst_addr_inc : 1; 2052 uint32_t overlap_disable : 1; 2053 uint32_t constant_fill : 1; 2054 } fields; 2055 uint32_t raw; 2056 } packet; 2057 uint32_t src_lo; 2058 uint32_t src_hi; 2059 uint32_t dst_lo; 2060 uint32_t dst_hi; 2061 } pio_copy_data; 2062 struct lsdma_pio_constfill_data { 2063 union { 2064 struct { 2065 uint32_t byte_count : 26; 2066 uint32_t src_loc : 1; 2067 uint32_t dst_loc : 1; 2068 uint32_t src_addr_inc : 1; 2069 uint32_t dst_addr_inc : 1; 2070 uint32_t overlap_disable : 1; 2071 uint32_t constant_fill : 1; 2072 } fields; 2073 uint32_t raw; 2074 } packet; 2075 uint32_t dst_lo; 2076 uint32_t dst_hi; 2077 uint32_t data; 2078 } pio_constfill_data; 2079 2080 uint32_t all[14]; 2081 } u; 2082 2083 }; 2084 2085 struct dmub_rb_cmd_lsdma { 2086 struct dmub_cmd_header header; 2087 struct dmub_cmd_lsdma_data lsdma_data; 2088 }; 2089 2090 struct dmub_optc_state_v2 { 2091 uint32_t v_total_min; 2092 uint32_t v_total_max; 2093 uint32_t v_total_mid; 2094 uint32_t v_total_mid_frame_num; 2095 uint8_t program_manual_trigger; 2096 uint8_t tg_inst; 2097 uint8_t pad[2]; 2098 }; 2099 2100 struct dmub_optc_position { 2101 uint32_t vpos; 2102 uint32_t hpos; 2103 uint32_t frame; 2104 }; 2105 2106 struct dmub_rb_cmd_fams2_drr_update { 2107 struct dmub_cmd_header header; 2108 struct dmub_optc_state_v2 dmub_optc_state_req; 2109 }; 2110 2111 /* HW and FW global configuration data for FAMS2 */ 2112 /* FAMS2 types and structs */ 2113 enum fams2_stream_type { 2114 FAMS2_STREAM_TYPE_NONE = 0, 2115 FAMS2_STREAM_TYPE_VBLANK = 1, 2116 FAMS2_STREAM_TYPE_VACTIVE = 2, 2117 FAMS2_STREAM_TYPE_DRR = 3, 2118 FAMS2_STREAM_TYPE_SUBVP = 4, 2119 }; 2120 2121 struct dmub_rect16 { 2122 /** 2123 * Dirty rect x offset. 2124 */ 2125 uint16_t x; 2126 2127 /** 2128 * Dirty rect y offset. 2129 */ 2130 uint16_t y; 2131 2132 /** 2133 * Dirty rect width. 2134 */ 2135 uint16_t width; 2136 2137 /** 2138 * Dirty rect height. 2139 */ 2140 uint16_t height; 2141 }; 2142 2143 /* static stream state */ 2144 struct dmub_fams2_legacy_stream_static_state { 2145 uint8_t vactive_det_fill_delay_otg_vlines; 2146 uint8_t programming_delay_otg_vlines; 2147 }; //v0 2148 2149 struct dmub_fams2_subvp_stream_static_state { 2150 uint16_t vratio_numerator; 2151 uint16_t vratio_denominator; 2152 uint16_t phantom_vtotal; 2153 uint16_t phantom_vactive; 2154 union { 2155 struct { 2156 uint8_t is_multi_planar : 1; 2157 uint8_t is_yuv420 : 1; 2158 } bits; 2159 uint8_t all; 2160 } config; 2161 uint8_t programming_delay_otg_vlines; 2162 uint8_t prefetch_to_mall_otg_vlines; 2163 uint8_t phantom_otg_inst; 2164 uint8_t phantom_pipe_mask; 2165 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2166 }; //v0 2167 2168 struct dmub_fams2_drr_stream_static_state { 2169 uint16_t nom_stretched_vtotal; 2170 uint8_t programming_delay_otg_vlines; 2171 uint8_t only_stretch_if_required; 2172 uint8_t pad[2]; 2173 }; //v0 2174 2175 struct dmub_fams2_cmd_legacy_stream_static_state { 2176 uint16_t vactive_det_fill_delay_otg_vlines; 2177 uint16_t programming_delay_otg_vlines; 2178 }; //v1 2179 2180 struct dmub_fams2_cmd_subvp_stream_static_state { 2181 uint16_t vratio_numerator; 2182 uint16_t vratio_denominator; 2183 uint16_t phantom_vtotal; 2184 uint16_t phantom_vactive; 2185 uint16_t programming_delay_otg_vlines; 2186 uint16_t prefetch_to_mall_otg_vlines; 2187 union { 2188 struct { 2189 uint8_t is_multi_planar : 1; 2190 uint8_t is_yuv420 : 1; 2191 } bits; 2192 uint8_t all; 2193 } config; 2194 uint8_t phantom_otg_inst; 2195 uint8_t phantom_pipe_mask; 2196 uint8_t pad0; 2197 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2198 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2199 }; //v1 2200 2201 struct dmub_fams2_cmd_drr_stream_static_state { 2202 uint16_t nom_stretched_vtotal; 2203 uint16_t programming_delay_otg_vlines; 2204 uint8_t only_stretch_if_required; 2205 uint8_t pad[3]; 2206 }; //v1 2207 2208 union dmub_fams2_stream_static_sub_state { 2209 struct dmub_fams2_legacy_stream_static_state legacy; 2210 struct dmub_fams2_subvp_stream_static_state subvp; 2211 struct dmub_fams2_drr_stream_static_state drr; 2212 }; //v0 2213 2214 union dmub_fams2_cmd_stream_static_sub_state { 2215 COMMON_STREAM_STATIC_SUB_STATE 2216 }; //v1 2217 2218 union dmub_fams2_stream_static_sub_state_v2 { 2219 COMMON_STREAM_STATIC_SUB_STATE 2220 }; //v2 2221 2222 struct dmub_fams2_stream_static_state { 2223 enum fams2_stream_type type; 2224 uint32_t otg_vline_time_ns; 2225 uint32_t otg_vline_time_ticks; 2226 uint16_t htotal; 2227 uint16_t vtotal; // nominal vtotal 2228 uint16_t vblank_start; 2229 uint16_t vblank_end; 2230 uint16_t max_vtotal; 2231 uint16_t allow_start_otg_vline; 2232 uint16_t allow_end_otg_vline; 2233 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2234 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2235 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2236 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2237 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2238 union { 2239 struct { 2240 uint8_t is_drr: 1; // stream is DRR enabled 2241 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2242 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2243 } bits; 2244 uint8_t all; 2245 } config; 2246 uint8_t otg_inst; 2247 uint8_t pipe_mask; // pipe mask for the whole config 2248 uint8_t num_planes; 2249 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2250 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2251 union dmub_fams2_stream_static_sub_state sub_state; 2252 }; //v0 2253 2254 struct dmub_fams2_cmd_stream_static_base_state { 2255 enum fams2_stream_type type; 2256 uint32_t otg_vline_time_ns; 2257 uint32_t otg_vline_time_ticks; 2258 uint16_t htotal; 2259 uint16_t vtotal; // nominal vtotal 2260 uint16_t vblank_start; 2261 uint16_t vblank_end; 2262 uint16_t max_vtotal; 2263 uint16_t allow_start_otg_vline; 2264 uint16_t allow_end_otg_vline; 2265 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2266 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2267 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2268 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2269 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2270 union { 2271 struct { 2272 uint8_t is_drr : 1; // stream is DRR enabled 2273 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2274 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2275 } bits; 2276 uint8_t all; 2277 } config; 2278 uint8_t otg_inst; 2279 uint8_t pipe_mask; // pipe mask for the whole config 2280 uint8_t num_planes; 2281 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2282 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2283 }; //v1 2284 2285 struct dmub_fams2_stream_static_state_v1 { 2286 struct dmub_fams2_cmd_stream_static_base_state base; 2287 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2288 }; //v1 2289 2290 /** 2291 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2292 * p-state request to allow latency 2293 */ 2294 enum dmub_fams2_allow_delay_check_mode { 2295 /* No check for request to allow delay */ 2296 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2297 /* Check for request to allow delay */ 2298 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2299 /* Check for prepare to allow delay */ 2300 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2301 }; 2302 2303 union dmub_fams2_global_feature_config { 2304 struct { 2305 uint32_t enable: 1; 2306 uint32_t enable_ppt_check: 1; 2307 uint32_t enable_stall_recovery: 1; 2308 uint32_t enable_debug: 1; 2309 uint32_t enable_offload_flip: 1; 2310 uint32_t enable_visual_confirm: 1; 2311 uint32_t allow_delay_check_mode: 2; 2312 uint32_t reserved: 24; 2313 } bits; 2314 uint32_t all; 2315 }; 2316 2317 struct dmub_cmd_fams2_global_config { 2318 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2319 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2320 uint32_t num_streams; 2321 union dmub_fams2_global_feature_config features; 2322 uint32_t recovery_timeout_us; 2323 uint32_t hwfq_flip_programming_delay_us; 2324 }; 2325 2326 union dmub_cmd_fams2_config { 2327 struct dmub_cmd_fams2_global_config global; 2328 struct dmub_fams2_stream_static_state stream; //v0 2329 union { 2330 struct dmub_fams2_cmd_stream_static_base_state base; 2331 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2332 } stream_v1; //v1 2333 }; 2334 2335 struct dmub_fams2_config_v2 { 2336 struct dmub_cmd_fams2_global_config global; 2337 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2338 }; 2339 2340 /** 2341 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2342 */ 2343 struct dmub_rb_cmd_fams2 { 2344 struct dmub_cmd_header header; 2345 union dmub_cmd_fams2_config config; 2346 }; 2347 2348 /** 2349 * Indirect buffer descriptor 2350 */ 2351 struct dmub_ib_data { 2352 union dmub_addr src; // location of indirect buffer in memory 2353 uint16_t size; // indirect buffer size in bytes 2354 }; 2355 2356 /** 2357 * DMUB rb command definition for commands passed over indirect buffer 2358 */ 2359 struct dmub_rb_cmd_ib { 2360 struct dmub_cmd_header header; 2361 struct dmub_ib_data ib_data; 2362 }; 2363 2364 /** 2365 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2366 */ 2367 enum dmub_cmd_idle_opt_type { 2368 /** 2369 * DCN hardware restore. 2370 */ 2371 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2372 2373 /** 2374 * DCN hardware save. 2375 */ 2376 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2377 2378 /** 2379 * DCN hardware notify idle. 2380 */ 2381 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2382 2383 /** 2384 * DCN hardware notify power state. 2385 */ 2386 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2387 2388 /** 2389 * DCN notify to release HW. 2390 */ 2391 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2392 }; 2393 2394 /** 2395 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2396 */ 2397 struct dmub_rb_cmd_idle_opt_dcn_restore { 2398 struct dmub_cmd_header header; /**< header */ 2399 }; 2400 2401 /** 2402 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2403 */ 2404 struct dmub_dcn_notify_idle_cntl_data { 2405 uint8_t driver_idle; 2406 uint8_t skip_otg_disable; 2407 uint8_t reserved[58]; 2408 }; 2409 2410 /** 2411 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2412 */ 2413 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2414 struct dmub_cmd_header header; /**< header */ 2415 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2416 }; 2417 2418 /** 2419 * enum dmub_idle_opt_dc_power_state - DC power states. 2420 */ 2421 enum dmub_idle_opt_dc_power_state { 2422 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2423 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2424 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2425 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2426 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2427 }; 2428 2429 /** 2430 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2431 */ 2432 struct dmub_idle_opt_set_dc_power_state_data { 2433 uint8_t power_state; /**< power state */ 2434 uint8_t pad[3]; /**< padding */ 2435 }; 2436 2437 /** 2438 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2439 */ 2440 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2441 struct dmub_cmd_header header; /**< header */ 2442 struct dmub_idle_opt_set_dc_power_state_data data; 2443 }; 2444 2445 /** 2446 * struct dmub_clocks - Clock update notification. 2447 */ 2448 struct dmub_clocks { 2449 uint32_t dispclk_khz; /**< dispclk kHz */ 2450 uint32_t dppclk_khz; /**< dppclk kHz */ 2451 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2452 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2453 }; 2454 2455 /** 2456 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2457 */ 2458 enum dmub_cmd_clk_mgr_type { 2459 /** 2460 * Notify DMCUB of clock update. 2461 */ 2462 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2463 }; 2464 2465 /** 2466 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2467 */ 2468 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2469 struct dmub_cmd_header header; /**< header */ 2470 struct dmub_clocks clocks; /**< clock data */ 2471 }; 2472 2473 /** 2474 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2475 */ 2476 struct dmub_cmd_digx_encoder_control_data { 2477 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2478 }; 2479 2480 /** 2481 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2482 */ 2483 struct dmub_rb_cmd_digx_encoder_control { 2484 struct dmub_cmd_header header; /**< header */ 2485 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2486 }; 2487 2488 /** 2489 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2490 */ 2491 struct dmub_cmd_set_pixel_clock_data { 2492 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2493 }; 2494 2495 /** 2496 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2497 */ 2498 struct dmub_rb_cmd_set_pixel_clock { 2499 struct dmub_cmd_header header; /**< header */ 2500 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2501 }; 2502 2503 /** 2504 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2505 */ 2506 struct dmub_cmd_enable_disp_power_gating_data { 2507 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2508 }; 2509 2510 /** 2511 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2512 */ 2513 struct dmub_rb_cmd_enable_disp_power_gating { 2514 struct dmub_cmd_header header; /**< header */ 2515 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2516 }; 2517 2518 /** 2519 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2520 */ 2521 struct dmub_dig_transmitter_control_data_v1_7 { 2522 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2523 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2524 union { 2525 uint8_t digmode; /**< enum atom_encode_mode_def */ 2526 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2527 } mode_laneset; 2528 uint8_t lanenum; /**< Number of lanes */ 2529 union { 2530 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2531 } symclk_units; 2532 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2533 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2534 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2535 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2536 uint8_t reserved1; /**< For future use */ 2537 uint8_t skip_phy_ssc_reduction; 2538 uint8_t reserved2[2]; /**< For future use */ 2539 uint32_t reserved3[11]; /**< For future use */ 2540 }; 2541 2542 /** 2543 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2544 */ 2545 union dmub_cmd_dig1_transmitter_control_data { 2546 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2547 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2548 }; 2549 2550 /** 2551 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2552 */ 2553 struct dmub_rb_cmd_dig1_transmitter_control { 2554 struct dmub_cmd_header header; /**< header */ 2555 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2556 }; 2557 2558 /** 2559 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2560 */ 2561 struct dmub_rb_cmd_domain_control_data { 2562 uint8_t inst : 6; /**< DOMAIN instance to control */ 2563 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2564 uint8_t reserved[3]; /**< Reserved for future use */ 2565 }; 2566 2567 /** 2568 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2569 */ 2570 struct dmub_rb_cmd_domain_control { 2571 struct dmub_cmd_header header; /**< header */ 2572 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2573 }; 2574 2575 /** 2576 * DPIA tunnel command parameters. 2577 */ 2578 struct dmub_cmd_dig_dpia_control_data { 2579 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2580 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2581 union { 2582 uint8_t digmode; /** enum atom_encode_mode_def */ 2583 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2584 } mode_laneset; 2585 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2586 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2587 uint8_t hpdsel; /** =0: HPD is not assigned */ 2588 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2589 uint8_t dpia_id; /** Index of DPIA */ 2590 uint8_t fec_rdy : 1; 2591 uint8_t reserved : 7; 2592 uint32_t reserved1; 2593 }; 2594 2595 /** 2596 * DMUB command for DPIA tunnel control. 2597 */ 2598 struct dmub_rb_cmd_dig1_dpia_control { 2599 struct dmub_cmd_header header; 2600 struct dmub_cmd_dig_dpia_control_data dpia_control; 2601 }; 2602 2603 /** 2604 * SET_CONFIG Command Payload (deprecated) 2605 */ 2606 struct set_config_cmd_payload { 2607 uint8_t msg_type; /* set config message type */ 2608 uint8_t msg_data; /* set config message data */ 2609 }; 2610 2611 /** 2612 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2613 */ 2614 struct dmub_cmd_set_config_control_data { 2615 struct set_config_cmd_payload cmd_pkt; 2616 uint8_t instance; /* DPIA instance */ 2617 uint8_t immed_status; /* Immediate status returned in case of error */ 2618 }; 2619 2620 /** 2621 * SET_CONFIG Request Command Payload 2622 */ 2623 struct set_config_request_cmd_payload { 2624 uint8_t instance; /* DPIA instance */ 2625 uint8_t immed_status; /* Immediate status returned in case of error */ 2626 uint8_t msg_type; /* set config message type */ 2627 uint8_t reserved; 2628 uint32_t msg_data; /* set config message data */ 2629 }; 2630 2631 /** 2632 * DMUB command structure for SET_CONFIG command. 2633 */ 2634 struct dmub_rb_cmd_set_config_access { 2635 struct dmub_cmd_header header; /* header */ 2636 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2637 }; 2638 2639 /** 2640 * DMUB command structure for SET_CONFIG request command. 2641 */ 2642 struct dmub_rb_cmd_set_config_request { 2643 struct dmub_cmd_header header; /* header */ 2644 struct set_config_request_cmd_payload payload; /* set config request payload */ 2645 }; 2646 2647 /** 2648 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2649 */ 2650 struct dmub_cmd_mst_alloc_slots_control_data { 2651 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2652 uint8_t instance; /* DPIA instance */ 2653 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2654 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2655 }; 2656 2657 /** 2658 * DMUB command structure for SET_ command. 2659 */ 2660 struct dmub_rb_cmd_set_mst_alloc_slots { 2661 struct dmub_cmd_header header; /* header */ 2662 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2663 }; 2664 2665 /** 2666 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2667 */ 2668 struct dmub_cmd_tps_notification_data { 2669 uint8_t instance; /* DPIA instance */ 2670 uint8_t tps; /* requested training pattern */ 2671 uint8_t reserved1; 2672 uint8_t reserved2; 2673 }; 2674 2675 /** 2676 * DMUB command structure for SET_TPS_NOTIFICATION command. 2677 */ 2678 struct dmub_rb_cmd_set_tps_notification { 2679 struct dmub_cmd_header header; /* header */ 2680 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2681 }; 2682 2683 /** 2684 * DMUB command structure for DPIA HPD int enable control. 2685 */ 2686 struct dmub_rb_cmd_dpia_hpd_int_enable { 2687 struct dmub_cmd_header header; /* header */ 2688 uint32_t enable; /* dpia hpd interrupt enable */ 2689 }; 2690 2691 /** 2692 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2693 */ 2694 struct dmub_rb_cmd_dpphy_init { 2695 struct dmub_cmd_header header; /**< header */ 2696 uint8_t reserved[60]; /**< reserved bits */ 2697 }; 2698 2699 /** 2700 * enum dp_aux_request_action - DP AUX request command listing. 2701 * 2702 * 4 AUX request command bits are shifted to high nibble. 2703 */ 2704 enum dp_aux_request_action { 2705 /** I2C-over-AUX write request */ 2706 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2707 /** I2C-over-AUX read request */ 2708 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2709 /** I2C-over-AUX write status request */ 2710 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2711 /** I2C-over-AUX write request with MOT=1 */ 2712 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2713 /** I2C-over-AUX read request with MOT=1 */ 2714 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2715 /** I2C-over-AUX write status request with MOT=1 */ 2716 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2717 /** Native AUX write request */ 2718 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2719 /** Native AUX read request */ 2720 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2721 }; 2722 2723 /** 2724 * enum aux_return_code_type - DP AUX process return code listing. 2725 */ 2726 enum aux_return_code_type { 2727 /** AUX process succeeded */ 2728 AUX_RET_SUCCESS = 0, 2729 /** AUX process failed with unknown reason */ 2730 AUX_RET_ERROR_UNKNOWN, 2731 /** AUX process completed with invalid reply */ 2732 AUX_RET_ERROR_INVALID_REPLY, 2733 /** AUX process timed out */ 2734 AUX_RET_ERROR_TIMEOUT, 2735 /** HPD was low during AUX process */ 2736 AUX_RET_ERROR_HPD_DISCON, 2737 /** Failed to acquire AUX engine */ 2738 AUX_RET_ERROR_ENGINE_ACQUIRE, 2739 /** AUX request not supported */ 2740 AUX_RET_ERROR_INVALID_OPERATION, 2741 /** AUX process not available */ 2742 AUX_RET_ERROR_PROTOCOL_ERROR, 2743 }; 2744 2745 /** 2746 * enum aux_channel_type - DP AUX channel type listing. 2747 */ 2748 enum aux_channel_type { 2749 /** AUX thru Legacy DP AUX */ 2750 AUX_CHANNEL_LEGACY_DDC, 2751 /** AUX thru DPIA DP tunneling */ 2752 AUX_CHANNEL_DPIA 2753 }; 2754 2755 /** 2756 * struct aux_transaction_parameters - DP AUX request transaction data 2757 */ 2758 struct aux_transaction_parameters { 2759 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2760 uint8_t action; /**< enum dp_aux_request_action */ 2761 uint8_t length; /**< DP AUX request data length */ 2762 uint8_t reserved; /**< For future use */ 2763 uint32_t address; /**< DP AUX address */ 2764 uint8_t data[16]; /**< DP AUX write data */ 2765 }; 2766 2767 /** 2768 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2769 */ 2770 struct dmub_cmd_dp_aux_control_data { 2771 uint8_t instance; /**< AUX instance or DPIA instance */ 2772 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2773 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2774 uint8_t reserved0; /**< For future use */ 2775 uint16_t timeout; /**< timeout time in us */ 2776 uint16_t reserved1; /**< For future use */ 2777 enum aux_channel_type type; /**< enum aux_channel_type */ 2778 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2779 }; 2780 2781 /** 2782 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2783 */ 2784 struct dmub_rb_cmd_dp_aux_access { 2785 /** 2786 * Command header. 2787 */ 2788 struct dmub_cmd_header header; 2789 /** 2790 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2791 */ 2792 struct dmub_cmd_dp_aux_control_data aux_control; 2793 }; 2794 2795 /** 2796 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2797 */ 2798 struct dmub_rb_cmd_outbox1_enable { 2799 /** 2800 * Command header. 2801 */ 2802 struct dmub_cmd_header header; 2803 /** 2804 * enable: 0x0 -> disable outbox1 notification (default value) 2805 * 0x1 -> enable outbox1 notification 2806 */ 2807 uint32_t enable; 2808 }; 2809 2810 /* DP AUX Reply command - OutBox Cmd */ 2811 /** 2812 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2813 */ 2814 struct aux_reply_data { 2815 /** 2816 * Aux cmd 2817 */ 2818 uint8_t command; 2819 /** 2820 * Aux reply data length (max: 16 bytes) 2821 */ 2822 uint8_t length; 2823 /** 2824 * Alignment only 2825 */ 2826 uint8_t pad[2]; 2827 /** 2828 * Aux reply data 2829 */ 2830 uint8_t data[16]; 2831 }; 2832 2833 /** 2834 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2835 */ 2836 struct aux_reply_control_data { 2837 /** 2838 * Reserved for future use 2839 */ 2840 uint32_t handle; 2841 /** 2842 * Aux Instance 2843 */ 2844 uint8_t instance; 2845 /** 2846 * Aux transaction result: definition in enum aux_return_code_type 2847 */ 2848 uint8_t result; 2849 /** 2850 * Alignment only 2851 */ 2852 uint16_t pad; 2853 }; 2854 2855 /** 2856 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2857 */ 2858 struct dmub_rb_cmd_dp_aux_reply { 2859 /** 2860 * Command header. 2861 */ 2862 struct dmub_cmd_header header; 2863 /** 2864 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2865 */ 2866 struct aux_reply_control_data control; 2867 /** 2868 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2869 */ 2870 struct aux_reply_data reply_data; 2871 }; 2872 2873 /* DP HPD Notify command - OutBox Cmd */ 2874 /** 2875 * DP HPD Type 2876 */ 2877 enum dp_hpd_type { 2878 /** 2879 * Normal DP HPD 2880 */ 2881 DP_HPD = 0, 2882 /** 2883 * DP HPD short pulse 2884 */ 2885 DP_IRQ = 1, 2886 /** 2887 * Failure to acquire DP HPD state 2888 */ 2889 DP_NONE_HPD = 2 2890 }; 2891 2892 /** 2893 * DP HPD Status 2894 */ 2895 enum dp_hpd_status { 2896 /** 2897 * DP_HPD status low 2898 */ 2899 DP_HPD_UNPLUG = 0, 2900 /** 2901 * DP_HPD status high 2902 */ 2903 DP_HPD_PLUG 2904 }; 2905 2906 /** 2907 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2908 */ 2909 struct dp_hpd_data { 2910 /** 2911 * DP HPD instance 2912 */ 2913 uint8_t instance; 2914 /** 2915 * HPD type 2916 */ 2917 uint8_t hpd_type; 2918 /** 2919 * HPD status: only for type: DP_HPD to indicate status 2920 */ 2921 uint8_t hpd_status; 2922 /** 2923 * Alignment only 2924 */ 2925 uint8_t pad; 2926 }; 2927 2928 /** 2929 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2930 */ 2931 struct dmub_rb_cmd_dp_hpd_notify { 2932 /** 2933 * Command header. 2934 */ 2935 struct dmub_cmd_header header; 2936 /** 2937 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2938 */ 2939 struct dp_hpd_data hpd_data; 2940 }; 2941 2942 /** 2943 * Definition of a SET_CONFIG reply from DPOA. 2944 */ 2945 enum set_config_status { 2946 SET_CONFIG_PENDING = 0, 2947 SET_CONFIG_ACK_RECEIVED, 2948 SET_CONFIG_RX_TIMEOUT, 2949 SET_CONFIG_UNKNOWN_ERROR, 2950 }; 2951 2952 /** 2953 * Definition of a set_config reply 2954 */ 2955 struct set_config_reply_control_data { 2956 uint8_t instance; /* DPIA Instance */ 2957 uint8_t status; /* Set Config reply */ 2958 uint16_t pad; /* Alignment */ 2959 }; 2960 2961 /** 2962 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2963 */ 2964 struct dmub_rb_cmd_dp_set_config_reply { 2965 struct dmub_cmd_header header; 2966 struct set_config_reply_control_data set_config_reply_control; 2967 }; 2968 2969 /** 2970 * Definition of a DPIA notification header 2971 */ 2972 struct dpia_notification_header { 2973 uint8_t instance; /**< DPIA Instance */ 2974 uint8_t reserved[3]; 2975 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2976 }; 2977 2978 /** 2979 * Definition of the common data struct of DPIA notification 2980 */ 2981 struct dpia_notification_common { 2982 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2983 - sizeof(struct dpia_notification_header)]; 2984 }; 2985 2986 /** 2987 * Definition of a DPIA notification data 2988 */ 2989 struct dpia_bw_allocation_notify_data { 2990 union { 2991 struct { 2992 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2993 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2994 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2995 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2996 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2997 uint16_t reserved: 11; /**< Reserved */ 2998 } bits; 2999 3000 uint16_t flags; 3001 }; 3002 3003 uint8_t cm_id; /**< CM ID */ 3004 uint8_t group_id; /**< Group ID */ 3005 uint8_t granularity; /**< BW Allocation Granularity */ 3006 uint8_t estimated_bw; /**< Estimated_BW */ 3007 uint8_t allocated_bw; /**< Allocated_BW */ 3008 uint8_t reserved; 3009 }; 3010 3011 /** 3012 * union dpia_notify_data_type - DPIA Notification in Outbox command 3013 */ 3014 union dpia_notification_data { 3015 /** 3016 * DPIA Notification for common data struct 3017 */ 3018 struct dpia_notification_common common_data; 3019 3020 /** 3021 * DPIA Notification for DP BW Allocation support 3022 */ 3023 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3024 }; 3025 3026 /** 3027 * Definition of a DPIA notification payload 3028 */ 3029 struct dpia_notification_payload { 3030 struct dpia_notification_header header; 3031 union dpia_notification_data data; /**< DPIA notification payload data */ 3032 }; 3033 3034 /** 3035 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3036 */ 3037 struct dmub_rb_cmd_dpia_notification { 3038 struct dmub_cmd_header header; /**< DPIA notification header */ 3039 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3040 }; 3041 3042 /** 3043 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3044 */ 3045 struct dmub_cmd_hpd_state_query_data { 3046 uint8_t instance; /**< HPD instance or DPIA instance */ 3047 uint8_t result; /**< For returning HPD state */ 3048 uint16_t pad; /** < Alignment */ 3049 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3050 enum aux_return_code_type status; /**< for returning the status of command */ 3051 }; 3052 3053 /** 3054 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3055 */ 3056 struct dmub_rb_cmd_query_hpd_state { 3057 /** 3058 * Command header. 3059 */ 3060 struct dmub_cmd_header header; 3061 /** 3062 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3063 */ 3064 struct dmub_cmd_hpd_state_query_data data; 3065 }; 3066 3067 /** 3068 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3069 */ 3070 struct dmub_rb_cmd_hpd_sense_notify_data { 3071 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3072 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3073 }; 3074 3075 /** 3076 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3077 */ 3078 struct dmub_rb_cmd_hpd_sense_notify { 3079 struct dmub_cmd_header header; /**< header */ 3080 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3081 }; 3082 3083 /* 3084 * Command IDs should be treated as stable ABI. 3085 * Do not reuse or modify IDs. 3086 */ 3087 3088 /** 3089 * PSR command sub-types. 3090 */ 3091 enum dmub_cmd_psr_type { 3092 /** 3093 * Set PSR version support. 3094 */ 3095 DMUB_CMD__PSR_SET_VERSION = 0, 3096 /** 3097 * Copy driver-calculated parameters to PSR state. 3098 */ 3099 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3100 /** 3101 * Enable PSR. 3102 */ 3103 DMUB_CMD__PSR_ENABLE = 2, 3104 3105 /** 3106 * Disable PSR. 3107 */ 3108 DMUB_CMD__PSR_DISABLE = 3, 3109 3110 /** 3111 * Set PSR level. 3112 * PSR level is a 16-bit value dicated by driver that 3113 * will enable/disable different functionality. 3114 */ 3115 DMUB_CMD__PSR_SET_LEVEL = 4, 3116 3117 /** 3118 * Forces PSR enabled until an explicit PSR disable call. 3119 */ 3120 DMUB_CMD__PSR_FORCE_STATIC = 5, 3121 /** 3122 * Set vtotal in psr active for FreeSync PSR. 3123 */ 3124 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3125 /** 3126 * Set PSR power option 3127 */ 3128 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3129 }; 3130 3131 /** 3132 * Different PSR residency modes. 3133 * Different modes change the definition of PSR residency. 3134 */ 3135 enum psr_residency_mode { 3136 PSR_RESIDENCY_MODE_PHY = 0, 3137 PSR_RESIDENCY_MODE_ALPM, 3138 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3139 /* Do not add below. */ 3140 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3141 }; 3142 3143 enum dmub_cmd_fams_type { 3144 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3145 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3146 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3147 /** 3148 * For SubVP set manual trigger in FW because it 3149 * triggers DRR_UPDATE_PENDING which SubVP relies 3150 * on (for any SubVP cases that use a DRR display) 3151 */ 3152 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3153 DMUB_CMD__FAMS2_CONFIG = 4, 3154 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3155 DMUB_CMD__FAMS2_FLIP = 6, 3156 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3157 }; 3158 3159 /** 3160 * PSR versions. 3161 */ 3162 enum psr_version { 3163 /** 3164 * PSR version 1. 3165 */ 3166 PSR_VERSION_1 = 0, 3167 /** 3168 * Freesync PSR SU. 3169 */ 3170 PSR_VERSION_SU_1 = 1, 3171 /** 3172 * PSR not supported. 3173 */ 3174 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3175 }; 3176 3177 /** 3178 * PHY Link rate for DP. 3179 */ 3180 enum phy_link_rate { 3181 /** 3182 * not supported. 3183 */ 3184 PHY_RATE_UNKNOWN = 0, 3185 /** 3186 * Rate_1 (RBR) - 1.62 Gbps/Lane 3187 */ 3188 PHY_RATE_162 = 1, 3189 /** 3190 * Rate_2 - 2.16 Gbps/Lane 3191 */ 3192 PHY_RATE_216 = 2, 3193 /** 3194 * Rate_3 - 2.43 Gbps/Lane 3195 */ 3196 PHY_RATE_243 = 3, 3197 /** 3198 * Rate_4 (HBR) - 2.70 Gbps/Lane 3199 */ 3200 PHY_RATE_270 = 4, 3201 /** 3202 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3203 */ 3204 PHY_RATE_324 = 5, 3205 /** 3206 * Rate_6 - 4.32 Gbps/Lane 3207 */ 3208 PHY_RATE_432 = 6, 3209 /** 3210 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3211 */ 3212 PHY_RATE_540 = 7, 3213 /** 3214 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3215 */ 3216 PHY_RATE_810 = 8, 3217 /** 3218 * UHBR10 - 10.0 Gbps/Lane 3219 */ 3220 PHY_RATE_1000 = 9, 3221 /** 3222 * UHBR13.5 - 13.5 Gbps/Lane 3223 */ 3224 PHY_RATE_1350 = 10, 3225 /** 3226 * UHBR10 - 20.0 Gbps/Lane 3227 */ 3228 PHY_RATE_2000 = 11, 3229 3230 PHY_RATE_675 = 12, 3231 /** 3232 * Rate 12 - 6.75 Gbps/Lane 3233 */ 3234 }; 3235 3236 /** 3237 * enum dmub_phy_fsm_state - PHY FSM states. 3238 * PHY FSM state to transit to during PSR enable/disable. 3239 */ 3240 enum dmub_phy_fsm_state { 3241 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3242 DMUB_PHY_FSM_RESET, 3243 DMUB_PHY_FSM_RESET_RELEASED, 3244 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3245 DMUB_PHY_FSM_INITIALIZED, 3246 DMUB_PHY_FSM_CALIBRATED, 3247 DMUB_PHY_FSM_CALIBRATED_LP, 3248 DMUB_PHY_FSM_CALIBRATED_PG, 3249 DMUB_PHY_FSM_POWER_DOWN, 3250 DMUB_PHY_FSM_PLL_EN, 3251 DMUB_PHY_FSM_TX_EN, 3252 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3253 DMUB_PHY_FSM_FAST_LP, 3254 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3255 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3256 DMUB_PHY_FSM_P2_PLL_OFF, 3257 DMUB_PHY_FSM_P2_PLL_ON, 3258 }; 3259 3260 /** 3261 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3262 */ 3263 struct dmub_cmd_psr_copy_settings_data { 3264 /** 3265 * Flags that can be set by driver to change some PSR behaviour. 3266 */ 3267 union dmub_psr_debug_flags debug; 3268 /** 3269 * 16-bit value dicated by driver that will enable/disable different functionality. 3270 */ 3271 uint16_t psr_level; 3272 /** 3273 * DPP HW instance. 3274 */ 3275 uint8_t dpp_inst; 3276 /** 3277 * MPCC HW instance. 3278 * Not used in dmub fw, 3279 * dmub fw will get active opp by reading odm registers. 3280 */ 3281 uint8_t mpcc_inst; 3282 /** 3283 * OPP HW instance. 3284 * Not used in dmub fw, 3285 * dmub fw will get active opp by reading odm registers. 3286 */ 3287 uint8_t opp_inst; 3288 /** 3289 * OTG HW instance. 3290 */ 3291 uint8_t otg_inst; 3292 /** 3293 * DIG FE HW instance. 3294 */ 3295 uint8_t digfe_inst; 3296 /** 3297 * DIG BE HW instance. 3298 */ 3299 uint8_t digbe_inst; 3300 /** 3301 * DP PHY HW instance. 3302 */ 3303 uint8_t dpphy_inst; 3304 /** 3305 * AUX HW instance. 3306 */ 3307 uint8_t aux_inst; 3308 /** 3309 * Determines if SMU optimzations are enabled/disabled. 3310 */ 3311 uint8_t smu_optimizations_en; 3312 /** 3313 * Unused. 3314 * TODO: Remove. 3315 */ 3316 uint8_t frame_delay; 3317 /** 3318 * If RFB setup time is greater than the total VBLANK time, 3319 * it is not possible for the sink to capture the video frame 3320 * in the same frame the SDP is sent. In this case, 3321 * the frame capture indication bit should be set and an extra 3322 * static frame should be transmitted to the sink. 3323 */ 3324 uint8_t frame_cap_ind; 3325 /** 3326 * Granularity of Y offset supported by sink. 3327 */ 3328 uint8_t su_y_granularity; 3329 /** 3330 * Indicates whether sink should start capturing 3331 * immediately following active scan line, 3332 * or starting with the 2nd active scan line. 3333 */ 3334 uint8_t line_capture_indication; 3335 /** 3336 * Multi-display optimizations are implemented on certain ASICs. 3337 */ 3338 uint8_t multi_disp_optimizations_en; 3339 /** 3340 * The last possible line SDP may be transmitted without violating 3341 * the RFB setup time or entering the active video frame. 3342 */ 3343 uint16_t init_sdp_deadline; 3344 /** 3345 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3346 */ 3347 uint8_t rate_control_caps ; 3348 /* 3349 * Force PSRSU always doing full frame update 3350 */ 3351 uint8_t force_ffu_mode; 3352 /** 3353 * Length of each horizontal line in us. 3354 */ 3355 uint32_t line_time_in_us; 3356 /** 3357 * FEC enable status in driver 3358 */ 3359 uint8_t fec_enable_status; 3360 /** 3361 * FEC re-enable delay when PSR exit. 3362 * unit is 100us, range form 0~255(0xFF). 3363 */ 3364 uint8_t fec_enable_delay_in100us; 3365 /** 3366 * PSR control version. 3367 */ 3368 uint8_t cmd_version; 3369 /** 3370 * Panel Instance. 3371 * Panel instance to identify which psr_state to use 3372 * Currently the support is only for 0 or 1 3373 */ 3374 uint8_t panel_inst; 3375 /* 3376 * DSC enable status in driver 3377 */ 3378 uint8_t dsc_enable_status; 3379 /* 3380 * Use FSM state for PSR power up/down 3381 */ 3382 uint8_t use_phy_fsm; 3383 /** 3384 * frame delay for frame re-lock 3385 */ 3386 uint8_t relock_delay_frame_cnt; 3387 /** 3388 * esd recovery indicate. 3389 */ 3390 uint8_t esd_recovery; 3391 /** 3392 * DSC Slice height. 3393 */ 3394 uint16_t dsc_slice_height; 3395 /** 3396 * Some panels request main link off before xth vertical line 3397 */ 3398 uint16_t poweroff_before_vertical_line; 3399 /** 3400 * Some panels cannot handle idle pattern during PSR entry. 3401 * To power down phy before disable stream to avoid sending 3402 * idle pattern. 3403 */ 3404 uint8_t power_down_phy_before_disable_stream; 3405 }; 3406 3407 /** 3408 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3409 */ 3410 struct dmub_rb_cmd_psr_copy_settings { 3411 /** 3412 * Command header. 3413 */ 3414 struct dmub_cmd_header header; 3415 /** 3416 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3417 */ 3418 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3419 }; 3420 3421 /** 3422 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3423 */ 3424 struct dmub_cmd_psr_set_level_data { 3425 /** 3426 * 16-bit value dicated by driver that will enable/disable different functionality. 3427 */ 3428 uint16_t psr_level; 3429 /** 3430 * PSR control version. 3431 */ 3432 uint8_t cmd_version; 3433 /** 3434 * Panel Instance. 3435 * Panel instance to identify which psr_state to use 3436 * Currently the support is only for 0 or 1 3437 */ 3438 uint8_t panel_inst; 3439 }; 3440 3441 /** 3442 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3443 */ 3444 struct dmub_rb_cmd_psr_set_level { 3445 /** 3446 * Command header. 3447 */ 3448 struct dmub_cmd_header header; 3449 /** 3450 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3451 */ 3452 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3453 }; 3454 3455 struct dmub_rb_cmd_psr_enable_data { 3456 /** 3457 * PSR control version. 3458 */ 3459 uint8_t cmd_version; 3460 /** 3461 * Panel Instance. 3462 * Panel instance to identify which psr_state to use 3463 * Currently the support is only for 0 or 1 3464 */ 3465 uint8_t panel_inst; 3466 /** 3467 * Phy state to enter. 3468 * Values to use are defined in dmub_phy_fsm_state 3469 */ 3470 uint8_t phy_fsm_state; 3471 /** 3472 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3473 * Set this using enum phy_link_rate. 3474 * This does not support HDMI/DP2 for now. 3475 */ 3476 uint8_t phy_rate; 3477 }; 3478 3479 /** 3480 * Definition of a DMUB_CMD__PSR_ENABLE command. 3481 * PSR enable/disable is controlled using the sub_type. 3482 */ 3483 struct dmub_rb_cmd_psr_enable { 3484 /** 3485 * Command header. 3486 */ 3487 struct dmub_cmd_header header; 3488 3489 struct dmub_rb_cmd_psr_enable_data data; 3490 }; 3491 3492 /** 3493 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3494 */ 3495 struct dmub_cmd_psr_set_version_data { 3496 /** 3497 * PSR version that FW should implement. 3498 */ 3499 enum psr_version version; 3500 /** 3501 * PSR control version. 3502 */ 3503 uint8_t cmd_version; 3504 /** 3505 * Panel Instance. 3506 * Panel instance to identify which psr_state to use 3507 * Currently the support is only for 0 or 1 3508 */ 3509 uint8_t panel_inst; 3510 /** 3511 * Explicit padding to 4 byte boundary. 3512 */ 3513 uint8_t pad[2]; 3514 }; 3515 3516 /** 3517 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3518 */ 3519 struct dmub_rb_cmd_psr_set_version { 3520 /** 3521 * Command header. 3522 */ 3523 struct dmub_cmd_header header; 3524 /** 3525 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3526 */ 3527 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3528 }; 3529 3530 struct dmub_cmd_psr_force_static_data { 3531 /** 3532 * PSR control version. 3533 */ 3534 uint8_t cmd_version; 3535 /** 3536 * Panel Instance. 3537 * Panel instance to identify which psr_state to use 3538 * Currently the support is only for 0 or 1 3539 */ 3540 uint8_t panel_inst; 3541 /** 3542 * Explicit padding to 4 byte boundary. 3543 */ 3544 uint8_t pad[2]; 3545 }; 3546 3547 /** 3548 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3549 */ 3550 struct dmub_rb_cmd_psr_force_static { 3551 /** 3552 * Command header. 3553 */ 3554 struct dmub_cmd_header header; 3555 /** 3556 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3557 */ 3558 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3559 }; 3560 3561 /** 3562 * PSR SU debug flags. 3563 */ 3564 union dmub_psr_su_debug_flags { 3565 /** 3566 * PSR SU debug flags. 3567 */ 3568 struct { 3569 /** 3570 * Update dirty rect in SW only. 3571 */ 3572 uint8_t update_dirty_rect_only : 1; 3573 /** 3574 * Reset the cursor/plane state before processing the call. 3575 */ 3576 uint8_t reset_state : 1; 3577 } bitfields; 3578 3579 /** 3580 * Union for debug flags. 3581 */ 3582 uint32_t u32All; 3583 }; 3584 3585 /** 3586 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3587 * This triggers a selective update for PSR SU. 3588 */ 3589 struct dmub_cmd_update_dirty_rect_data { 3590 /** 3591 * Dirty rects from OS. 3592 */ 3593 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3594 /** 3595 * PSR SU debug flags. 3596 */ 3597 union dmub_psr_su_debug_flags debug_flags; 3598 /** 3599 * OTG HW instance. 3600 */ 3601 uint8_t pipe_idx; 3602 /** 3603 * Number of dirty rects. 3604 */ 3605 uint8_t dirty_rect_count; 3606 /** 3607 * PSR control version. 3608 */ 3609 uint8_t cmd_version; 3610 /** 3611 * Panel Instance. 3612 * Panel instance to identify which psr_state to use 3613 * Currently the support is only for 0 or 1 3614 */ 3615 uint8_t panel_inst; 3616 }; 3617 3618 /** 3619 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3620 */ 3621 struct dmub_rb_cmd_update_dirty_rect { 3622 /** 3623 * Command header. 3624 */ 3625 struct dmub_cmd_header header; 3626 /** 3627 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3628 */ 3629 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3630 }; 3631 3632 /** 3633 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3634 */ 3635 union dmub_reg_cursor_control_cfg { 3636 struct { 3637 uint32_t cur_enable: 1; 3638 uint32_t reser0: 3; 3639 uint32_t cur_2x_magnify: 1; 3640 uint32_t reser1: 3; 3641 uint32_t mode: 3; 3642 uint32_t reser2: 5; 3643 uint32_t pitch: 2; 3644 uint32_t reser3: 6; 3645 uint32_t line_per_chunk: 5; 3646 uint32_t reser4: 3; 3647 } bits; 3648 uint32_t raw; 3649 }; 3650 struct dmub_cursor_position_cache_hubp { 3651 union dmub_reg_cursor_control_cfg cur_ctl; 3652 union dmub_reg_position_cfg { 3653 struct { 3654 uint32_t cur_x_pos: 16; 3655 uint32_t cur_y_pos: 16; 3656 } bits; 3657 uint32_t raw; 3658 } position; 3659 union dmub_reg_hot_spot_cfg { 3660 struct { 3661 uint32_t hot_x: 16; 3662 uint32_t hot_y: 16; 3663 } bits; 3664 uint32_t raw; 3665 } hot_spot; 3666 union dmub_reg_dst_offset_cfg { 3667 struct { 3668 uint32_t dst_x_offset: 13; 3669 uint32_t reserved: 19; 3670 } bits; 3671 uint32_t raw; 3672 } dst_offset; 3673 }; 3674 3675 union dmub_reg_cur0_control_cfg { 3676 struct { 3677 uint32_t cur0_enable: 1; 3678 uint32_t expansion_mode: 1; 3679 uint32_t reser0: 1; 3680 uint32_t cur0_rom_en: 1; 3681 uint32_t mode: 3; 3682 uint32_t reserved: 25; 3683 } bits; 3684 uint32_t raw; 3685 }; 3686 struct dmub_cursor_position_cache_dpp { 3687 union dmub_reg_cur0_control_cfg cur0_ctl; 3688 }; 3689 struct dmub_cursor_position_cfg { 3690 struct dmub_cursor_position_cache_hubp pHubp; 3691 struct dmub_cursor_position_cache_dpp pDpp; 3692 uint8_t pipe_idx; 3693 /* 3694 * Padding is required. To be 4 Bytes Aligned. 3695 */ 3696 uint8_t padding[3]; 3697 }; 3698 3699 struct dmub_cursor_attribute_cache_hubp { 3700 uint32_t SURFACE_ADDR_HIGH; 3701 uint32_t SURFACE_ADDR; 3702 union dmub_reg_cursor_control_cfg cur_ctl; 3703 union dmub_reg_cursor_size_cfg { 3704 struct { 3705 uint32_t width: 16; 3706 uint32_t height: 16; 3707 } bits; 3708 uint32_t raw; 3709 } size; 3710 union dmub_reg_cursor_settings_cfg { 3711 struct { 3712 uint32_t dst_y_offset: 8; 3713 uint32_t chunk_hdl_adjust: 2; 3714 uint32_t reserved: 22; 3715 } bits; 3716 uint32_t raw; 3717 } settings; 3718 }; 3719 struct dmub_cursor_attribute_cache_dpp { 3720 union dmub_reg_cur0_control_cfg cur0_ctl; 3721 }; 3722 struct dmub_cursor_attributes_cfg { 3723 struct dmub_cursor_attribute_cache_hubp aHubp; 3724 struct dmub_cursor_attribute_cache_dpp aDpp; 3725 }; 3726 3727 struct dmub_cmd_update_cursor_payload0 { 3728 /** 3729 * Cursor dirty rects. 3730 */ 3731 struct dmub_rect cursor_rect; 3732 /** 3733 * PSR SU debug flags. 3734 */ 3735 union dmub_psr_su_debug_flags debug_flags; 3736 /** 3737 * Cursor enable/disable. 3738 */ 3739 uint8_t enable; 3740 /** 3741 * OTG HW instance. 3742 */ 3743 uint8_t pipe_idx; 3744 /** 3745 * PSR control version. 3746 */ 3747 uint8_t cmd_version; 3748 /** 3749 * Panel Instance. 3750 * Panel instance to identify which psr_state to use 3751 * Currently the support is only for 0 or 1 3752 */ 3753 uint8_t panel_inst; 3754 /** 3755 * Cursor Position Register. 3756 * Registers contains Hubp & Dpp modules 3757 */ 3758 struct dmub_cursor_position_cfg position_cfg; 3759 }; 3760 3761 struct dmub_cmd_update_cursor_payload1 { 3762 struct dmub_cursor_attributes_cfg attribute_cfg; 3763 }; 3764 3765 union dmub_cmd_update_cursor_info_data { 3766 struct dmub_cmd_update_cursor_payload0 payload0; 3767 struct dmub_cmd_update_cursor_payload1 payload1; 3768 }; 3769 /** 3770 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3771 */ 3772 struct dmub_rb_cmd_update_cursor_info { 3773 /** 3774 * Command header. 3775 */ 3776 struct dmub_cmd_header header; 3777 /** 3778 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3779 */ 3780 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3781 }; 3782 3783 /** 3784 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3785 */ 3786 struct dmub_cmd_psr_set_vtotal_data { 3787 /** 3788 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3789 */ 3790 uint16_t psr_vtotal_idle; 3791 /** 3792 * PSR control version. 3793 */ 3794 uint8_t cmd_version; 3795 /** 3796 * Panel Instance. 3797 * Panel instance to identify which psr_state to use 3798 * Currently the support is only for 0 or 1 3799 */ 3800 uint8_t panel_inst; 3801 /* 3802 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3803 */ 3804 uint16_t psr_vtotal_su; 3805 /** 3806 * Explicit padding to 4 byte boundary. 3807 */ 3808 uint8_t pad2[2]; 3809 }; 3810 3811 /** 3812 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3813 */ 3814 struct dmub_rb_cmd_psr_set_vtotal { 3815 /** 3816 * Command header. 3817 */ 3818 struct dmub_cmd_header header; 3819 /** 3820 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3821 */ 3822 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3823 }; 3824 3825 /** 3826 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3827 */ 3828 struct dmub_cmd_psr_set_power_opt_data { 3829 /** 3830 * PSR control version. 3831 */ 3832 uint8_t cmd_version; 3833 /** 3834 * Panel Instance. 3835 * Panel instance to identify which psr_state to use 3836 * Currently the support is only for 0 or 1 3837 */ 3838 uint8_t panel_inst; 3839 /** 3840 * Explicit padding to 4 byte boundary. 3841 */ 3842 uint8_t pad[2]; 3843 /** 3844 * PSR power option 3845 */ 3846 uint32_t power_opt; 3847 }; 3848 3849 /** 3850 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3851 */ 3852 struct dmub_rb_cmd_psr_set_power_opt { 3853 /** 3854 * Command header. 3855 */ 3856 struct dmub_cmd_header header; 3857 /** 3858 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3859 */ 3860 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3861 }; 3862 3863 enum dmub_alpm_mode { 3864 ALPM_AUXWAKE = 0, 3865 ALPM_AUXLESS = 1, 3866 ALPM_UNSUPPORTED = 2, 3867 }; 3868 3869 /** 3870 * Definition of Replay Residency GPINT command. 3871 * Bit[0] - Residency mode for Revision 0 3872 * Bit[1] - Enable/Disable state 3873 * Bit[2-3] - Revision number 3874 * Bit[4-7] - Residency mode for Revision 1 3875 * Bit[8] - Panel instance 3876 * Bit[9-15] - Reserved 3877 */ 3878 3879 enum pr_residency_mode { 3880 PR_RESIDENCY_MODE_PHY = 0x0, 3881 PR_RESIDENCY_MODE_ALPM, 3882 PR_RESIDENCY_MODE_IPS2, 3883 PR_RESIDENCY_MODE_FRAME_CNT, 3884 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3885 }; 3886 3887 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3888 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3889 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3890 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3891 3892 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3893 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3894 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3895 3896 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3897 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3898 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3899 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3900 3901 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3902 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3903 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3904 3905 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3906 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3907 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3908 3909 /** 3910 * Definition of a replay_state. 3911 */ 3912 enum replay_state { 3913 REPLAY_STATE_0 = 0x0, 3914 REPLAY_STATE_1 = 0x10, 3915 REPLAY_STATE_1A = 0x11, 3916 REPLAY_STATE_2 = 0x20, 3917 REPLAY_STATE_2A = 0x21, 3918 REPLAY_STATE_3 = 0x30, 3919 REPLAY_STATE_3INIT = 0x31, 3920 REPLAY_STATE_4 = 0x40, 3921 REPLAY_STATE_4A = 0x41, 3922 REPLAY_STATE_4B = 0x42, 3923 REPLAY_STATE_4C = 0x43, 3924 REPLAY_STATE_4D = 0x44, 3925 REPLAY_STATE_4E = 0x45, 3926 REPLAY_STATE_4B_LOCKED = 0x4A, 3927 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3928 REPLAY_STATE_5 = 0x50, 3929 REPLAY_STATE_5A = 0x51, 3930 REPLAY_STATE_5B = 0x52, 3931 REPLAY_STATE_5A_LOCKED = 0x5A, 3932 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3933 REPLAY_STATE_6 = 0x60, 3934 REPLAY_STATE_6A = 0x61, 3935 REPLAY_STATE_6B = 0x62, 3936 REPLAY_STATE_INVALID = 0xFF, 3937 }; 3938 3939 /** 3940 * Replay command sub-types. 3941 */ 3942 enum dmub_cmd_replay_type { 3943 /** 3944 * Copy driver-calculated parameters to REPLAY state. 3945 */ 3946 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3947 /** 3948 * Enable REPLAY. 3949 */ 3950 DMUB_CMD__REPLAY_ENABLE = 1, 3951 /** 3952 * Set Replay power option. 3953 */ 3954 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3955 /** 3956 * Set coasting vtotal. 3957 */ 3958 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3959 /** 3960 * Set power opt and coasting vtotal. 3961 */ 3962 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3963 /** 3964 * Set disabled iiming sync. 3965 */ 3966 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3967 /** 3968 * Set Residency Frameupdate Timer. 3969 */ 3970 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3971 /** 3972 * Set pseudo vtotal 3973 */ 3974 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3975 /** 3976 * Set adaptive sync sdp enabled 3977 */ 3978 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3979 /** 3980 * Set Replay General command. 3981 */ 3982 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3983 }; 3984 3985 /** 3986 * Replay general command sub-types. 3987 */ 3988 enum dmub_cmd_replay_general_subtype { 3989 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3990 /** 3991 * TODO: For backward compatible, allow new command only. 3992 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3993 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3994 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3995 */ 3996 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3997 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3998 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 3999 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4000 }; 4001 4002 struct dmub_alpm_auxless_data { 4003 uint16_t lfps_setup_ns; 4004 uint16_t lfps_period_ns; 4005 uint16_t lfps_silence_ns; 4006 uint16_t lfps_t1_t2_override_us; 4007 short lfps_t1_t2_offset_us; 4008 uint8_t lttpr_count; 4009 }; 4010 4011 /** 4012 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4013 */ 4014 struct dmub_cmd_replay_copy_settings_data { 4015 /** 4016 * Flags that can be set by driver to change some replay behaviour. 4017 */ 4018 union replay_debug_flags debug; 4019 4020 /** 4021 * @flags: Flags used to determine feature functionality. 4022 */ 4023 union replay_hw_flags flags; 4024 4025 /** 4026 * DPP HW instance. 4027 */ 4028 uint8_t dpp_inst; 4029 /** 4030 * OTG HW instance. 4031 */ 4032 uint8_t otg_inst; 4033 /** 4034 * DIG FE HW instance. 4035 */ 4036 uint8_t digfe_inst; 4037 /** 4038 * DIG BE HW instance. 4039 */ 4040 uint8_t digbe_inst; 4041 /** 4042 * AUX HW instance. 4043 */ 4044 uint8_t aux_inst; 4045 /** 4046 * Panel Instance. 4047 * Panel isntance to identify which psr_state to use 4048 * Currently the support is only for 0 or 1 4049 */ 4050 uint8_t panel_inst; 4051 /** 4052 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4053 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4054 */ 4055 uint8_t pixel_deviation_per_line; 4056 /** 4057 * @max_deviation_line: The max number of deviation line that can keep the timing 4058 * synchronized between the Source and Sink during Replay normal sleep mode. 4059 */ 4060 uint8_t max_deviation_line; 4061 /** 4062 * Length of each horizontal line in ns. 4063 */ 4064 uint32_t line_time_in_ns; 4065 /** 4066 * PHY instance. 4067 */ 4068 uint8_t dpphy_inst; 4069 /** 4070 * Determines if SMU optimzations are enabled/disabled. 4071 */ 4072 uint8_t smu_optimizations_en; 4073 /** 4074 * Determines if timing sync are enabled/disabled. 4075 */ 4076 uint8_t replay_timing_sync_supported; 4077 /* 4078 * Use FSM state for Replay power up/down 4079 */ 4080 uint8_t use_phy_fsm; 4081 /** 4082 * Use for AUX-less ALPM LFPS wake operation 4083 */ 4084 struct dmub_alpm_auxless_data auxless_alpm_data; 4085 }; 4086 4087 /** 4088 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4089 */ 4090 struct dmub_rb_cmd_replay_copy_settings { 4091 /** 4092 * Command header. 4093 */ 4094 struct dmub_cmd_header header; 4095 /** 4096 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4097 */ 4098 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4099 }; 4100 4101 /** 4102 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4103 */ 4104 enum replay_enable { 4105 /** 4106 * Disable REPLAY. 4107 */ 4108 REPLAY_DISABLE = 0, 4109 /** 4110 * Enable REPLAY. 4111 */ 4112 REPLAY_ENABLE = 1, 4113 }; 4114 4115 /** 4116 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4117 */ 4118 struct dmub_rb_cmd_replay_enable_data { 4119 /** 4120 * Replay enable or disable. 4121 */ 4122 uint8_t enable; 4123 /** 4124 * Panel Instance. 4125 * Panel isntance to identify which replay_state to use 4126 * Currently the support is only for 0 or 1 4127 */ 4128 uint8_t panel_inst; 4129 /** 4130 * Phy state to enter. 4131 * Values to use are defined in dmub_phy_fsm_state 4132 */ 4133 uint8_t phy_fsm_state; 4134 /** 4135 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4136 * Set this using enum phy_link_rate. 4137 * This does not support HDMI/DP2 for now. 4138 */ 4139 uint8_t phy_rate; 4140 }; 4141 4142 /** 4143 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4144 * Replay enable/disable is controlled using action in data. 4145 */ 4146 struct dmub_rb_cmd_replay_enable { 4147 /** 4148 * Command header. 4149 */ 4150 struct dmub_cmd_header header; 4151 4152 struct dmub_rb_cmd_replay_enable_data data; 4153 }; 4154 4155 /** 4156 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4157 */ 4158 struct dmub_cmd_replay_set_power_opt_data { 4159 /** 4160 * Panel Instance. 4161 * Panel isntance to identify which replay_state to use 4162 * Currently the support is only for 0 or 1 4163 */ 4164 uint8_t panel_inst; 4165 /** 4166 * Explicit padding to 4 byte boundary. 4167 */ 4168 uint8_t pad[3]; 4169 /** 4170 * REPLAY power option 4171 */ 4172 uint32_t power_opt; 4173 }; 4174 4175 /** 4176 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4177 */ 4178 struct dmub_cmd_replay_set_timing_sync_data { 4179 /** 4180 * Panel Instance. 4181 * Panel isntance to identify which replay_state to use 4182 * Currently the support is only for 0 or 1 4183 */ 4184 uint8_t panel_inst; 4185 /** 4186 * REPLAY set_timing_sync 4187 */ 4188 uint8_t timing_sync_supported; 4189 /** 4190 * Explicit padding to 4 byte boundary. 4191 */ 4192 uint8_t pad[2]; 4193 }; 4194 4195 /** 4196 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4197 */ 4198 struct dmub_cmd_replay_set_pseudo_vtotal { 4199 /** 4200 * Panel Instance. 4201 * Panel isntance to identify which replay_state to use 4202 * Currently the support is only for 0 or 1 4203 */ 4204 uint8_t panel_inst; 4205 /** 4206 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4207 */ 4208 uint16_t vtotal; 4209 /** 4210 * Explicit padding to 4 byte boundary. 4211 */ 4212 uint8_t pad; 4213 }; 4214 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4215 /** 4216 * Panel Instance. 4217 * Panel isntance to identify which replay_state to use 4218 * Currently the support is only for 0 or 1 4219 */ 4220 uint8_t panel_inst; 4221 /** 4222 * enabled: set adaptive sync sdp enabled 4223 */ 4224 uint8_t force_disabled; 4225 4226 uint8_t pad[2]; 4227 }; 4228 struct dmub_cmd_replay_set_general_cmd_data { 4229 /** 4230 * Panel Instance. 4231 * Panel isntance to identify which replay_state to use 4232 * Currently the support is only for 0 or 1 4233 */ 4234 uint8_t panel_inst; 4235 /** 4236 * subtype: replay general cmd sub type 4237 */ 4238 uint8_t subtype; 4239 4240 uint8_t pad[2]; 4241 /** 4242 * config data with param1 and param2 4243 */ 4244 uint32_t param1; 4245 4246 uint32_t param2; 4247 }; 4248 4249 /** 4250 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4251 */ 4252 struct dmub_rb_cmd_replay_set_power_opt { 4253 /** 4254 * Command header. 4255 */ 4256 struct dmub_cmd_header header; 4257 /** 4258 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4259 */ 4260 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4261 }; 4262 4263 /** 4264 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4265 */ 4266 struct dmub_cmd_replay_set_coasting_vtotal_data { 4267 /** 4268 * 16-bit value dicated by driver that indicates the coasting vtotal. 4269 */ 4270 uint16_t coasting_vtotal; 4271 /** 4272 * REPLAY control version. 4273 */ 4274 uint8_t cmd_version; 4275 /** 4276 * Panel Instance. 4277 * Panel isntance to identify which replay_state to use 4278 * Currently the support is only for 0 or 1 4279 */ 4280 uint8_t panel_inst; 4281 /** 4282 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4283 */ 4284 uint16_t coasting_vtotal_high; 4285 /** 4286 * Explicit padding to 4 byte boundary. 4287 */ 4288 uint8_t pad[2]; 4289 }; 4290 4291 /** 4292 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4293 */ 4294 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4295 /** 4296 * Command header. 4297 */ 4298 struct dmub_cmd_header header; 4299 /** 4300 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4301 */ 4302 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4303 }; 4304 4305 /** 4306 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4307 */ 4308 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4309 /** 4310 * Command header. 4311 */ 4312 struct dmub_cmd_header header; 4313 /** 4314 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4315 */ 4316 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4317 /** 4318 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4319 */ 4320 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4321 }; 4322 4323 /** 4324 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4325 */ 4326 struct dmub_rb_cmd_replay_set_timing_sync { 4327 /** 4328 * Command header. 4329 */ 4330 struct dmub_cmd_header header; 4331 /** 4332 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4333 */ 4334 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4335 }; 4336 4337 /** 4338 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4339 */ 4340 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4341 /** 4342 * Command header. 4343 */ 4344 struct dmub_cmd_header header; 4345 /** 4346 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4347 */ 4348 struct dmub_cmd_replay_set_pseudo_vtotal data; 4349 }; 4350 4351 /** 4352 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4353 */ 4354 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4355 /** 4356 * Command header. 4357 */ 4358 struct dmub_cmd_header header; 4359 /** 4360 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4361 */ 4362 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4363 }; 4364 4365 /** 4366 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4367 */ 4368 struct dmub_rb_cmd_replay_set_general_cmd { 4369 /** 4370 * Command header. 4371 */ 4372 struct dmub_cmd_header header; 4373 /** 4374 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4375 */ 4376 struct dmub_cmd_replay_set_general_cmd_data data; 4377 }; 4378 4379 /** 4380 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4381 */ 4382 struct dmub_cmd_replay_frameupdate_timer_data { 4383 /** 4384 * Panel Instance. 4385 * Panel isntance to identify which replay_state to use 4386 * Currently the support is only for 0 or 1 4387 */ 4388 uint8_t panel_inst; 4389 /** 4390 * Replay Frameupdate Timer Enable or not 4391 */ 4392 uint8_t enable; 4393 /** 4394 * REPLAY force reflash frame update number 4395 */ 4396 uint16_t frameupdate_count; 4397 }; 4398 /** 4399 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4400 */ 4401 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4402 /** 4403 * Command header. 4404 */ 4405 struct dmub_cmd_header header; 4406 /** 4407 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4408 */ 4409 struct dmub_cmd_replay_frameupdate_timer_data data; 4410 }; 4411 4412 /** 4413 * Definition union of replay command set 4414 */ 4415 union dmub_replay_cmd_set { 4416 /** 4417 * Panel Instance. 4418 * Panel isntance to identify which replay_state to use 4419 * Currently the support is only for 0 or 1 4420 */ 4421 uint8_t panel_inst; 4422 /** 4423 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4424 */ 4425 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4426 /** 4427 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4428 */ 4429 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4430 /** 4431 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4432 */ 4433 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4434 /** 4435 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4436 */ 4437 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4438 /** 4439 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4440 */ 4441 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4442 }; 4443 4444 /** 4445 * Set of HW components that can be locked. 4446 * 4447 * Note: If updating with more HW components, fields 4448 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4449 */ 4450 union dmub_hw_lock_flags { 4451 /** 4452 * Set of HW components that can be locked. 4453 */ 4454 struct { 4455 /** 4456 * Lock/unlock OTG master update lock. 4457 */ 4458 uint8_t lock_pipe : 1; 4459 /** 4460 * Lock/unlock cursor. 4461 */ 4462 uint8_t lock_cursor : 1; 4463 /** 4464 * Lock/unlock global update lock. 4465 */ 4466 uint8_t lock_dig : 1; 4467 /** 4468 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4469 */ 4470 uint8_t triple_buffer_lock : 1; 4471 } bits; 4472 4473 /** 4474 * Union for HW Lock flags. 4475 */ 4476 uint8_t u8All; 4477 }; 4478 4479 /** 4480 * Instances of HW to be locked. 4481 * 4482 * Note: If updating with more HW components, fields 4483 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4484 */ 4485 struct dmub_hw_lock_inst_flags { 4486 /** 4487 * OTG HW instance for OTG master update lock. 4488 */ 4489 uint8_t otg_inst; 4490 /** 4491 * OPP instance for cursor lock. 4492 */ 4493 uint8_t opp_inst; 4494 /** 4495 * OTG HW instance for global update lock. 4496 * TODO: Remove, and re-use otg_inst. 4497 */ 4498 uint8_t dig_inst; 4499 /** 4500 * Explicit pad to 4 byte boundary. 4501 */ 4502 uint8_t pad; 4503 }; 4504 4505 /** 4506 * Clients that can acquire the HW Lock Manager. 4507 * 4508 * Note: If updating with more clients, fields in 4509 * dmub_inbox0_cmd_lock_hw must be updated to match. 4510 */ 4511 enum hw_lock_client { 4512 /** 4513 * Driver is the client of HW Lock Manager. 4514 */ 4515 HW_LOCK_CLIENT_DRIVER = 0, 4516 /** 4517 * PSR SU is the client of HW Lock Manager. 4518 */ 4519 HW_LOCK_CLIENT_PSR_SU = 1, 4520 HW_LOCK_CLIENT_SUBVP = 3, 4521 /** 4522 * Replay is the client of HW Lock Manager. 4523 */ 4524 HW_LOCK_CLIENT_REPLAY = 4, 4525 HW_LOCK_CLIENT_FAMS2 = 5, 4526 /** 4527 * Invalid client. 4528 */ 4529 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4530 }; 4531 4532 /** 4533 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4534 */ 4535 struct dmub_cmd_lock_hw_data { 4536 /** 4537 * Specifies the client accessing HW Lock Manager. 4538 */ 4539 enum hw_lock_client client; 4540 /** 4541 * HW instances to be locked. 4542 */ 4543 struct dmub_hw_lock_inst_flags inst_flags; 4544 /** 4545 * Which components to be locked. 4546 */ 4547 union dmub_hw_lock_flags hw_locks; 4548 /** 4549 * Specifies lock/unlock. 4550 */ 4551 uint8_t lock; 4552 /** 4553 * HW can be unlocked separately from releasing the HW Lock Mgr. 4554 * This flag is set if the client wishes to release the object. 4555 */ 4556 uint8_t should_release; 4557 /** 4558 * Explicit padding to 4 byte boundary. 4559 */ 4560 uint8_t pad; 4561 }; 4562 4563 /** 4564 * Definition of a DMUB_CMD__HW_LOCK command. 4565 * Command is used by driver and FW. 4566 */ 4567 struct dmub_rb_cmd_lock_hw { 4568 /** 4569 * Command header. 4570 */ 4571 struct dmub_cmd_header header; 4572 /** 4573 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4574 */ 4575 struct dmub_cmd_lock_hw_data lock_hw_data; 4576 }; 4577 4578 /** 4579 * ABM command sub-types. 4580 */ 4581 enum dmub_cmd_abm_type { 4582 /** 4583 * Initialize parameters for ABM algorithm. 4584 * Data is passed through an indirect buffer. 4585 */ 4586 DMUB_CMD__ABM_INIT_CONFIG = 0, 4587 /** 4588 * Set OTG and panel HW instance. 4589 */ 4590 DMUB_CMD__ABM_SET_PIPE = 1, 4591 /** 4592 * Set user requested backklight level. 4593 */ 4594 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4595 /** 4596 * Set ABM operating/aggression level. 4597 */ 4598 DMUB_CMD__ABM_SET_LEVEL = 3, 4599 /** 4600 * Set ambient light level. 4601 */ 4602 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4603 /** 4604 * Enable/disable fractional duty cycle for backlight PWM. 4605 */ 4606 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4607 4608 /** 4609 * unregister vertical interrupt after steady state is reached 4610 */ 4611 DMUB_CMD__ABM_PAUSE = 6, 4612 4613 /** 4614 * Save and Restore ABM state. On save we save parameters, and 4615 * on restore we update state with passed in data. 4616 */ 4617 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4618 4619 /** 4620 * Query ABM caps. 4621 */ 4622 DMUB_CMD__ABM_QUERY_CAPS = 8, 4623 4624 /** 4625 * Set ABM Events 4626 */ 4627 DMUB_CMD__ABM_SET_EVENT = 9, 4628 4629 /** 4630 * Get the current ACE curve. 4631 */ 4632 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4633 4634 /** 4635 * Get current histogram data 4636 */ 4637 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4638 }; 4639 4640 /** 4641 * LSDMA command sub-types. 4642 */ 4643 enum dmub_cmd_lsdma_type { 4644 /** 4645 * Initialize parameters for LSDMA. 4646 * Ring buffer is mapped to the ring buffer 4647 */ 4648 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 4649 /** 4650 * LSDMA copies data from source to destination linearly 4651 */ 4652 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 4653 /** 4654 * Send the tiled-to-tiled copy command 4655 */ 4656 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 2, 4657 /** 4658 * Send the poll reg write command 4659 */ 4660 DMUB_CMD__LSDMA_POLL_REG_WRITE = 3, 4661 /** 4662 * Send the pio copy command 4663 */ 4664 DMUB_CMD__LSDMA_PIO_COPY = 4, 4665 /** 4666 * Send the pio constfill command 4667 */ 4668 DMUB_CMD__LSDMA_PIO_CONSTFILL = 5, 4669 }; 4670 4671 struct abm_ace_curve { 4672 /** 4673 * @offsets: ACE curve offsets. 4674 */ 4675 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4676 4677 /** 4678 * @thresholds: ACE curve thresholds. 4679 */ 4680 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4681 4682 /** 4683 * @slopes: ACE curve slopes. 4684 */ 4685 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4686 }; 4687 4688 struct fixed_pt_format { 4689 /** 4690 * @sign_bit: Indicates whether one bit is reserved for the sign. 4691 */ 4692 bool sign_bit; 4693 4694 /** 4695 * @num_int_bits: Number of bits used for integer part. 4696 */ 4697 uint8_t num_int_bits; 4698 4699 /** 4700 * @num_frac_bits: Number of bits used for fractional part. 4701 */ 4702 uint8_t num_frac_bits; 4703 4704 /** 4705 * @pad: Explicit padding to 4 byte boundary. 4706 */ 4707 uint8_t pad; 4708 }; 4709 4710 struct abm_caps { 4711 /** 4712 * @num_hg_bins: Number of histogram bins. 4713 */ 4714 uint8_t num_hg_bins; 4715 4716 /** 4717 * @num_ace_segments: Number of ACE curve segments. 4718 */ 4719 uint8_t num_ace_segments; 4720 4721 /** 4722 * @pad: Explicit padding to 4 byte boundary. 4723 */ 4724 uint8_t pad[2]; 4725 4726 /** 4727 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4728 */ 4729 struct fixed_pt_format ace_thresholds_format; 4730 4731 /** 4732 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4733 */ 4734 struct fixed_pt_format ace_offsets_format; 4735 4736 /** 4737 * @ace_slopes_format: Format of the ACE slopes. 4738 */ 4739 struct fixed_pt_format ace_slopes_format; 4740 }; 4741 4742 /** 4743 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4744 * Requirements: 4745 * - Padded explicitly to 32-bit boundary. 4746 * - Must ensure this structure matches the one on driver-side, 4747 * otherwise it won't be aligned. 4748 */ 4749 struct abm_config_table { 4750 /** 4751 * Gamma curve thresholds, used for crgb conversion. 4752 */ 4753 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4754 /** 4755 * Gamma curve offsets, used for crgb conversion. 4756 */ 4757 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4758 /** 4759 * Gamma curve slopes, used for crgb conversion. 4760 */ 4761 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4762 /** 4763 * Custom backlight curve thresholds. 4764 */ 4765 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4766 /** 4767 * Custom backlight curve offsets. 4768 */ 4769 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4770 /** 4771 * Ambient light thresholds. 4772 */ 4773 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4774 /** 4775 * Minimum programmable backlight. 4776 */ 4777 uint16_t min_abm_backlight; // 122B 4778 /** 4779 * Minimum reduction values. 4780 */ 4781 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4782 /** 4783 * Maximum reduction values. 4784 */ 4785 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4786 /** 4787 * Bright positive gain. 4788 */ 4789 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4790 /** 4791 * Dark negative gain. 4792 */ 4793 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4794 /** 4795 * Hybrid factor. 4796 */ 4797 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4798 /** 4799 * Contrast factor. 4800 */ 4801 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4802 /** 4803 * Deviation gain. 4804 */ 4805 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4806 /** 4807 * Minimum knee. 4808 */ 4809 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4810 /** 4811 * Maximum knee. 4812 */ 4813 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4814 /** 4815 * Unused. 4816 */ 4817 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4818 /** 4819 * Explicit padding to 4 byte boundary. 4820 */ 4821 uint8_t pad3[3]; // 229B 4822 /** 4823 * Backlight ramp reduction. 4824 */ 4825 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4826 /** 4827 * Backlight ramp start. 4828 */ 4829 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4830 }; 4831 4832 /** 4833 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4834 */ 4835 struct dmub_cmd_abm_set_pipe_data { 4836 /** 4837 * OTG HW instance. 4838 */ 4839 uint8_t otg_inst; 4840 4841 /** 4842 * Panel Control HW instance. 4843 */ 4844 uint8_t panel_inst; 4845 4846 /** 4847 * Controls how ABM will interpret a set pipe or set level command. 4848 */ 4849 uint8_t set_pipe_option; 4850 4851 /** 4852 * Unused. 4853 * TODO: Remove. 4854 */ 4855 uint8_t ramping_boundary; 4856 4857 /** 4858 * PwrSeq HW Instance. 4859 */ 4860 uint8_t pwrseq_inst; 4861 4862 /** 4863 * Explicit padding to 4 byte boundary. 4864 */ 4865 uint8_t pad[3]; 4866 }; 4867 4868 /** 4869 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4870 */ 4871 struct dmub_rb_cmd_abm_set_pipe { 4872 /** 4873 * Command header. 4874 */ 4875 struct dmub_cmd_header header; 4876 4877 /** 4878 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4879 */ 4880 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4881 }; 4882 4883 /** 4884 * Type of backlight control method to be used by ABM module 4885 */ 4886 enum dmub_backlight_control_type { 4887 /** 4888 * PWM Backlight control 4889 */ 4890 DMU_BACKLIGHT_CONTROL_PWM = 0, 4891 /** 4892 * VESA Aux-based backlight control 4893 */ 4894 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4895 /** 4896 * AMD DPCD Aux-based backlight control 4897 */ 4898 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4899 }; 4900 4901 /** 4902 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4903 */ 4904 struct dmub_cmd_abm_set_backlight_data { 4905 /** 4906 * Number of frames to ramp to backlight user level. 4907 */ 4908 uint32_t frame_ramp; 4909 4910 /** 4911 * Requested backlight level from user. 4912 */ 4913 uint32_t backlight_user_level; 4914 4915 /** 4916 * ABM control version. 4917 */ 4918 uint8_t version; 4919 4920 /** 4921 * Panel Control HW instance mask. 4922 * Bit 0 is Panel Control HW instance 0. 4923 * Bit 1 is Panel Control HW instance 1. 4924 */ 4925 uint8_t panel_mask; 4926 4927 /** 4928 * AUX HW Instance. 4929 */ 4930 uint8_t aux_inst; 4931 4932 /** 4933 * Explicit padding to 4 byte boundary. 4934 */ 4935 uint8_t pad[1]; 4936 4937 /** 4938 * Backlight control type. 4939 * Value 0 is PWM backlight control. 4940 * Value 1 is VAUX backlight control. 4941 * Value 2 is AMD DPCD AUX backlight control. 4942 */ 4943 enum dmub_backlight_control_type backlight_control_type; 4944 4945 /** 4946 * Minimum luminance in nits. 4947 */ 4948 uint32_t min_luminance; 4949 4950 /** 4951 * Maximum luminance in nits. 4952 */ 4953 uint32_t max_luminance; 4954 4955 /** 4956 * Minimum backlight in pwm. 4957 */ 4958 uint32_t min_backlight_pwm; 4959 4960 /** 4961 * Maximum backlight in pwm. 4962 */ 4963 uint32_t max_backlight_pwm; 4964 }; 4965 4966 /** 4967 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4968 */ 4969 struct dmub_rb_cmd_abm_set_backlight { 4970 /** 4971 * Command header. 4972 */ 4973 struct dmub_cmd_header header; 4974 4975 /** 4976 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4977 */ 4978 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4979 }; 4980 4981 /** 4982 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4983 */ 4984 struct dmub_cmd_abm_set_level_data { 4985 /** 4986 * Set current ABM operating/aggression level. 4987 */ 4988 uint32_t level; 4989 4990 /** 4991 * ABM control version. 4992 */ 4993 uint8_t version; 4994 4995 /** 4996 * Panel Control HW instance mask. 4997 * Bit 0 is Panel Control HW instance 0. 4998 * Bit 1 is Panel Control HW instance 1. 4999 */ 5000 uint8_t panel_mask; 5001 5002 /** 5003 * Explicit padding to 4 byte boundary. 5004 */ 5005 uint8_t pad[2]; 5006 }; 5007 5008 /** 5009 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5010 */ 5011 struct dmub_rb_cmd_abm_set_level { 5012 /** 5013 * Command header. 5014 */ 5015 struct dmub_cmd_header header; 5016 5017 /** 5018 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5019 */ 5020 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5021 }; 5022 5023 /** 5024 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5025 */ 5026 struct dmub_cmd_abm_set_ambient_level_data { 5027 /** 5028 * Ambient light sensor reading from OS. 5029 */ 5030 uint32_t ambient_lux; 5031 5032 /** 5033 * ABM control version. 5034 */ 5035 uint8_t version; 5036 5037 /** 5038 * Panel Control HW instance mask. 5039 * Bit 0 is Panel Control HW instance 0. 5040 * Bit 1 is Panel Control HW instance 1. 5041 */ 5042 uint8_t panel_mask; 5043 5044 /** 5045 * Explicit padding to 4 byte boundary. 5046 */ 5047 uint8_t pad[2]; 5048 }; 5049 5050 /** 5051 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5052 */ 5053 struct dmub_rb_cmd_abm_set_ambient_level { 5054 /** 5055 * Command header. 5056 */ 5057 struct dmub_cmd_header header; 5058 5059 /** 5060 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5061 */ 5062 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5063 }; 5064 5065 /** 5066 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5067 */ 5068 struct dmub_cmd_abm_set_pwm_frac_data { 5069 /** 5070 * Enable/disable fractional duty cycle for backlight PWM. 5071 * TODO: Convert to uint8_t. 5072 */ 5073 uint32_t fractional_pwm; 5074 5075 /** 5076 * ABM control version. 5077 */ 5078 uint8_t version; 5079 5080 /** 5081 * Panel Control HW instance mask. 5082 * Bit 0 is Panel Control HW instance 0. 5083 * Bit 1 is Panel Control HW instance 1. 5084 */ 5085 uint8_t panel_mask; 5086 5087 /** 5088 * Explicit padding to 4 byte boundary. 5089 */ 5090 uint8_t pad[2]; 5091 }; 5092 5093 /** 5094 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5095 */ 5096 struct dmub_rb_cmd_abm_set_pwm_frac { 5097 /** 5098 * Command header. 5099 */ 5100 struct dmub_cmd_header header; 5101 5102 /** 5103 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5104 */ 5105 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5106 }; 5107 5108 /** 5109 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5110 */ 5111 struct dmub_cmd_abm_init_config_data { 5112 /** 5113 * Location of indirect buffer used to pass init data to ABM. 5114 */ 5115 union dmub_addr src; 5116 5117 /** 5118 * Indirect buffer length. 5119 */ 5120 uint16_t bytes; 5121 5122 5123 /** 5124 * ABM control version. 5125 */ 5126 uint8_t version; 5127 5128 /** 5129 * Panel Control HW instance mask. 5130 * Bit 0 is Panel Control HW instance 0. 5131 * Bit 1 is Panel Control HW instance 1. 5132 */ 5133 uint8_t panel_mask; 5134 5135 /** 5136 * Explicit padding to 4 byte boundary. 5137 */ 5138 uint8_t pad[2]; 5139 }; 5140 5141 /** 5142 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5143 */ 5144 struct dmub_rb_cmd_abm_init_config { 5145 /** 5146 * Command header. 5147 */ 5148 struct dmub_cmd_header header; 5149 5150 /** 5151 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5152 */ 5153 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5154 }; 5155 5156 /** 5157 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5158 */ 5159 5160 struct dmub_cmd_abm_pause_data { 5161 5162 /** 5163 * Panel Control HW instance mask. 5164 * Bit 0 is Panel Control HW instance 0. 5165 * Bit 1 is Panel Control HW instance 1. 5166 */ 5167 uint8_t panel_mask; 5168 5169 /** 5170 * OTG hw instance 5171 */ 5172 uint8_t otg_inst; 5173 5174 /** 5175 * Enable or disable ABM pause 5176 */ 5177 uint8_t enable; 5178 5179 /** 5180 * Explicit padding to 4 byte boundary. 5181 */ 5182 uint8_t pad[1]; 5183 }; 5184 5185 /** 5186 * Definition of a DMUB_CMD__ABM_PAUSE command. 5187 */ 5188 struct dmub_rb_cmd_abm_pause { 5189 /** 5190 * Command header. 5191 */ 5192 struct dmub_cmd_header header; 5193 5194 /** 5195 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5196 */ 5197 struct dmub_cmd_abm_pause_data abm_pause_data; 5198 }; 5199 5200 /** 5201 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5202 */ 5203 struct dmub_cmd_abm_query_caps_in { 5204 /** 5205 * Panel instance. 5206 */ 5207 uint8_t panel_inst; 5208 5209 /** 5210 * Explicit padding to 4 byte boundary. 5211 */ 5212 uint8_t pad[3]; 5213 }; 5214 5215 /** 5216 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5217 */ 5218 struct dmub_cmd_abm_query_caps_out { 5219 /** 5220 * SW Algorithm caps. 5221 */ 5222 struct abm_caps sw_caps; 5223 5224 /** 5225 * ABM HW caps. 5226 */ 5227 struct abm_caps hw_caps; 5228 }; 5229 5230 /** 5231 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5232 */ 5233 struct dmub_rb_cmd_abm_query_caps { 5234 /** 5235 * Command header. 5236 */ 5237 struct dmub_cmd_header header; 5238 5239 /** 5240 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5241 */ 5242 union { 5243 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5244 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5245 } data; 5246 }; 5247 5248 /** 5249 * enum dmub_abm_ace_curve_type - ACE curve type. 5250 */ 5251 enum dmub_abm_ace_curve_type { 5252 /** 5253 * ACE curve as defined by the SW layer. 5254 */ 5255 ABM_ACE_CURVE_TYPE__SW = 0, 5256 /** 5257 * ACE curve as defined by the SW to HW translation interface layer. 5258 */ 5259 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5260 }; 5261 5262 /** 5263 * enum dmub_abm_histogram_type - Histogram type. 5264 */ 5265 enum dmub_abm_histogram_type { 5266 /** 5267 * ACE curve as defined by the SW layer. 5268 */ 5269 ABM_HISTOGRAM_TYPE__SW = 0, 5270 /** 5271 * ACE curve as defined by the SW to HW translation interface layer. 5272 */ 5273 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5274 }; 5275 5276 /** 5277 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5278 */ 5279 struct dmub_rb_cmd_abm_get_ace_curve { 5280 /** 5281 * Command header. 5282 */ 5283 struct dmub_cmd_header header; 5284 5285 /** 5286 * Address where ACE curve should be copied. 5287 */ 5288 union dmub_addr dest; 5289 5290 /** 5291 * Type of ACE curve being queried. 5292 */ 5293 enum dmub_abm_ace_curve_type ace_type; 5294 5295 /** 5296 * Indirect buffer length. 5297 */ 5298 uint16_t bytes; 5299 5300 /** 5301 * eDP panel instance. 5302 */ 5303 uint8_t panel_inst; 5304 5305 /** 5306 * Explicit padding to 4 byte boundary. 5307 */ 5308 uint8_t pad; 5309 }; 5310 5311 /** 5312 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5313 */ 5314 struct dmub_rb_cmd_abm_get_histogram { 5315 /** 5316 * Command header. 5317 */ 5318 struct dmub_cmd_header header; 5319 5320 /** 5321 * Address where Histogram should be copied. 5322 */ 5323 union dmub_addr dest; 5324 5325 /** 5326 * Type of Histogram being queried. 5327 */ 5328 enum dmub_abm_histogram_type histogram_type; 5329 5330 /** 5331 * Indirect buffer length. 5332 */ 5333 uint16_t bytes; 5334 5335 /** 5336 * eDP panel instance. 5337 */ 5338 uint8_t panel_inst; 5339 5340 /** 5341 * Explicit padding to 4 byte boundary. 5342 */ 5343 uint8_t pad; 5344 }; 5345 5346 /** 5347 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5348 */ 5349 struct dmub_rb_cmd_abm_save_restore { 5350 /** 5351 * Command header. 5352 */ 5353 struct dmub_cmd_header header; 5354 5355 /** 5356 * OTG hw instance 5357 */ 5358 uint8_t otg_inst; 5359 5360 /** 5361 * Enable or disable ABM pause 5362 */ 5363 uint8_t freeze; 5364 5365 /** 5366 * Explicit padding to 4 byte boundary. 5367 */ 5368 uint8_t debug; 5369 5370 /** 5371 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5372 */ 5373 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5374 }; 5375 5376 /** 5377 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5378 */ 5379 5380 struct dmub_cmd_abm_set_event_data { 5381 5382 /** 5383 * VB Scaling Init. Strength Mapping 5384 * Byte 0: 0~255 for VB level 0 5385 * Byte 1: 0~255 for VB level 1 5386 * Byte 2: 0~255 for VB level 2 5387 * Byte 3: 0~255 for VB level 3 5388 */ 5389 uint32_t vb_scaling_strength_mapping; 5390 /** 5391 * VariBright Scaling Enable 5392 */ 5393 uint8_t vb_scaling_enable; 5394 /** 5395 * Panel Control HW instance mask. 5396 * Bit 0 is Panel Control HW instance 0. 5397 * Bit 1 is Panel Control HW instance 1. 5398 */ 5399 uint8_t panel_mask; 5400 5401 /** 5402 * Explicit padding to 4 byte boundary. 5403 */ 5404 uint8_t pad[2]; 5405 }; 5406 5407 /** 5408 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5409 */ 5410 struct dmub_rb_cmd_abm_set_event { 5411 /** 5412 * Command header. 5413 */ 5414 struct dmub_cmd_header header; 5415 5416 /** 5417 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5418 */ 5419 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5420 }; 5421 5422 /** 5423 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5424 */ 5425 struct dmub_cmd_query_feature_caps_data { 5426 /** 5427 * DMUB feature capabilities. 5428 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5429 */ 5430 struct dmub_feature_caps feature_caps; 5431 }; 5432 5433 /** 5434 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5435 */ 5436 struct dmub_rb_cmd_query_feature_caps { 5437 /** 5438 * Command header. 5439 */ 5440 struct dmub_cmd_header header; 5441 /** 5442 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5443 */ 5444 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5445 }; 5446 5447 /** 5448 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5449 */ 5450 struct dmub_cmd_visual_confirm_color_data { 5451 /** 5452 * DMUB visual confirm color 5453 */ 5454 struct dmub_visual_confirm_color visual_confirm_color; 5455 }; 5456 5457 /** 5458 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5459 */ 5460 struct dmub_rb_cmd_get_visual_confirm_color { 5461 /** 5462 * Command header. 5463 */ 5464 struct dmub_cmd_header header; 5465 /** 5466 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5467 */ 5468 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5469 }; 5470 5471 /** 5472 * enum dmub_cmd_panel_cntl_type - Panel control command. 5473 */ 5474 enum dmub_cmd_panel_cntl_type { 5475 /** 5476 * Initializes embedded panel hardware blocks. 5477 */ 5478 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5479 /** 5480 * Queries backlight info for the embedded panel. 5481 */ 5482 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5483 /** 5484 * Sets the PWM Freq as per user's requirement. 5485 */ 5486 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5487 }; 5488 5489 /** 5490 * struct dmub_cmd_panel_cntl_data - Panel control data. 5491 */ 5492 struct dmub_cmd_panel_cntl_data { 5493 uint32_t pwrseq_inst; /**< pwrseq instance */ 5494 uint32_t current_backlight; /* in/out */ 5495 uint32_t bl_pwm_cntl; /* in/out */ 5496 uint32_t bl_pwm_period_cntl; /* in/out */ 5497 uint32_t bl_pwm_ref_div1; /* in/out */ 5498 uint8_t is_backlight_on : 1; /* in/out */ 5499 uint8_t is_powered_on : 1; /* in/out */ 5500 uint8_t padding[3]; 5501 uint32_t bl_pwm_ref_div2; /* in/out */ 5502 uint8_t reserved[4]; 5503 }; 5504 5505 /** 5506 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5507 */ 5508 struct dmub_rb_cmd_panel_cntl { 5509 struct dmub_cmd_header header; /**< header */ 5510 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5511 }; 5512 5513 struct dmub_optc_state { 5514 uint32_t v_total_max; 5515 uint32_t v_total_min; 5516 uint32_t tg_inst; 5517 }; 5518 5519 struct dmub_rb_cmd_drr_update { 5520 struct dmub_cmd_header header; 5521 struct dmub_optc_state dmub_optc_state_req; 5522 }; 5523 5524 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5525 uint32_t pix_clk_100hz; 5526 uint8_t max_ramp_step; 5527 uint8_t pipes; 5528 uint8_t min_refresh_in_hz; 5529 uint8_t pipe_count; 5530 uint8_t pipe_index[4]; 5531 }; 5532 5533 struct dmub_cmd_fw_assisted_mclk_switch_config { 5534 uint8_t fams_enabled; 5535 uint8_t visual_confirm_enabled; 5536 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5537 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5538 }; 5539 5540 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5541 struct dmub_cmd_header header; 5542 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5543 }; 5544 5545 /** 5546 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5547 */ 5548 struct dmub_cmd_lvtma_control_data { 5549 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5550 uint8_t bypass_panel_control_wait; 5551 uint8_t reserved_0[2]; /**< For future use */ 5552 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5553 uint8_t reserved_1[3]; /**< For future use */ 5554 }; 5555 5556 /** 5557 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5558 */ 5559 struct dmub_rb_cmd_lvtma_control { 5560 /** 5561 * Command header. 5562 */ 5563 struct dmub_cmd_header header; 5564 /** 5565 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5566 */ 5567 struct dmub_cmd_lvtma_control_data data; 5568 }; 5569 5570 /** 5571 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5572 */ 5573 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5574 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5575 uint8_t is_usb; /**< is phy is usb */ 5576 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5577 uint8_t is_dp4; /**< is dp in 4 lane */ 5578 }; 5579 5580 /** 5581 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5582 */ 5583 struct dmub_rb_cmd_transmitter_query_dp_alt { 5584 struct dmub_cmd_header header; /**< header */ 5585 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5586 }; 5587 5588 struct phy_test_mode { 5589 uint8_t mode; 5590 uint8_t pat0; 5591 uint8_t pad[2]; 5592 }; 5593 5594 /** 5595 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5596 */ 5597 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5598 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5599 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5600 uint8_t lane_num; /**< Number of lanes */ 5601 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5602 struct phy_test_mode test_mode; 5603 enum dmub_phy_fsm_state state; 5604 uint32_t status; 5605 uint8_t pad; 5606 }; 5607 5608 /** 5609 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5610 */ 5611 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5612 struct dmub_cmd_header header; /**< header */ 5613 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5614 }; 5615 5616 /** 5617 * Maximum number of bytes a chunk sent to DMUB for parsing 5618 */ 5619 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5620 5621 /** 5622 * Represent a chunk of CEA blocks sent to DMUB for parsing 5623 */ 5624 struct dmub_cmd_send_edid_cea { 5625 uint16_t offset; /**< offset into the CEA block */ 5626 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5627 uint16_t cea_total_length; /**< total length of the CEA block */ 5628 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5629 uint8_t pad[3]; /**< padding and for future expansion */ 5630 }; 5631 5632 /** 5633 * Result of VSDB parsing from CEA block 5634 */ 5635 struct dmub_cmd_edid_cea_amd_vsdb { 5636 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5637 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5638 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5639 uint16_t min_frame_rate; /**< Maximum frame rate */ 5640 uint16_t max_frame_rate; /**< Minimum frame rate */ 5641 }; 5642 5643 /** 5644 * Result of sending a CEA chunk 5645 */ 5646 struct dmub_cmd_edid_cea_ack { 5647 uint16_t offset; /**< offset of the chunk into the CEA block */ 5648 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5649 uint8_t pad; /**< padding and for future expansion */ 5650 }; 5651 5652 /** 5653 * Specify whether the result is an ACK/NACK or the parsing has finished 5654 */ 5655 enum dmub_cmd_edid_cea_reply_type { 5656 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5657 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5658 }; 5659 5660 /** 5661 * Definition of a DMUB_CMD__EDID_CEA command. 5662 */ 5663 struct dmub_rb_cmd_edid_cea { 5664 struct dmub_cmd_header header; /**< Command header */ 5665 union dmub_cmd_edid_cea_data { 5666 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5667 struct dmub_cmd_edid_cea_output { /**< output with results */ 5668 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5669 union { 5670 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5671 struct dmub_cmd_edid_cea_ack ack; 5672 }; 5673 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5674 } data; /**< Command data */ 5675 5676 }; 5677 5678 /** 5679 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5680 */ 5681 struct dmub_cmd_cable_id_input { 5682 uint8_t phy_inst; /**< phy inst for cable id data */ 5683 }; 5684 5685 /** 5686 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5687 */ 5688 struct dmub_cmd_cable_id_output { 5689 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5690 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5691 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5692 uint8_t RESERVED :2; /**< reserved means not defined */ 5693 }; 5694 5695 /** 5696 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5697 */ 5698 struct dmub_rb_cmd_get_usbc_cable_id { 5699 struct dmub_cmd_header header; /**< Command header */ 5700 /** 5701 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5702 */ 5703 union dmub_cmd_cable_id_data { 5704 struct dmub_cmd_cable_id_input input; /**< Input */ 5705 struct dmub_cmd_cable_id_output output; /**< Output */ 5706 uint8_t output_raw; /**< Raw data output */ 5707 } data; 5708 }; 5709 5710 enum dmub_cmd_fused_io_sub_type { 5711 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5712 DMUB_CMD__FUSED_IO_ABORT = 1, 5713 }; 5714 5715 enum dmub_cmd_fused_request_type { 5716 FUSED_REQUEST_READ, 5717 FUSED_REQUEST_WRITE, 5718 FUSED_REQUEST_POLL, 5719 }; 5720 5721 enum dmub_cmd_fused_request_status { 5722 FUSED_REQUEST_STATUS_SUCCESS, 5723 FUSED_REQUEST_STATUS_BEGIN, 5724 FUSED_REQUEST_STATUS_SUBMIT, 5725 FUSED_REQUEST_STATUS_REPLY, 5726 FUSED_REQUEST_STATUS_POLL, 5727 FUSED_REQUEST_STATUS_ABORTED, 5728 FUSED_REQUEST_STATUS_FAILED = 0x80, 5729 FUSED_REQUEST_STATUS_INVALID, 5730 FUSED_REQUEST_STATUS_BUSY, 5731 FUSED_REQUEST_STATUS_TIMEOUT, 5732 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5733 }; 5734 5735 struct dmub_cmd_fused_request { 5736 uint8_t status; 5737 uint8_t type : 2; 5738 uint8_t _reserved0 : 3; 5739 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5740 uint8_t identifier; 5741 uint8_t _reserved1; 5742 uint32_t timeout_us; 5743 union dmub_cmd_fused_request_location { 5744 struct dmub_cmd_fused_request_location_i2c { 5745 uint8_t is_aux : 1; // False 5746 uint8_t ddc_line : 3; 5747 uint8_t over_aux : 1; 5748 uint8_t _reserved0 : 3; 5749 uint8_t address; 5750 uint8_t offset; 5751 uint8_t length; 5752 } i2c; 5753 struct dmub_cmd_fused_request_location_aux { 5754 uint32_t is_aux : 1; // True 5755 uint32_t ddc_line : 3; 5756 uint32_t address : 20; 5757 uint32_t length : 8; // Automatically split into 16B transactions 5758 } aux; 5759 } u; 5760 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5761 }; 5762 5763 struct dmub_rb_cmd_fused_io { 5764 struct dmub_cmd_header header; 5765 struct dmub_cmd_fused_request request; 5766 }; 5767 5768 /** 5769 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5770 */ 5771 enum dmub_cmd_secure_display_type { 5772 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5773 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5774 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5775 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5776 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5777 }; 5778 5779 #define MAX_ROI_NUM 2 5780 5781 struct dmub_cmd_roi_info { 5782 uint16_t x_start; 5783 uint16_t x_end; 5784 uint16_t y_start; 5785 uint16_t y_end; 5786 uint8_t otg_id; 5787 uint8_t phy_id; 5788 }; 5789 5790 struct dmub_cmd_roi_window_ctl { 5791 uint16_t x_start; 5792 uint16_t x_end; 5793 uint16_t y_start; 5794 uint16_t y_end; 5795 bool enable; 5796 }; 5797 5798 struct dmub_cmd_roi_ctl_info { 5799 uint8_t otg_id; 5800 uint8_t phy_id; 5801 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5802 }; 5803 5804 /** 5805 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5806 */ 5807 struct dmub_rb_cmd_secure_display { 5808 struct dmub_cmd_header header; 5809 /** 5810 * Data passed from driver to dmub firmware. 5811 */ 5812 struct dmub_cmd_roi_info roi_info; 5813 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5814 }; 5815 5816 /** 5817 * Command type of a DMUB_CMD__PSP command 5818 */ 5819 enum dmub_cmd_psp_type { 5820 DMUB_CMD__PSP_ASSR_ENABLE = 0 5821 }; 5822 5823 /** 5824 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5825 */ 5826 struct dmub_cmd_assr_enable_data { 5827 /** 5828 * ASSR enable or disable. 5829 */ 5830 uint8_t enable; 5831 /** 5832 * PHY port type. 5833 * Indicates eDP / non-eDP port type 5834 */ 5835 uint8_t phy_port_type; 5836 /** 5837 * PHY port ID. 5838 */ 5839 uint8_t phy_port_id; 5840 /** 5841 * Link encoder index. 5842 */ 5843 uint8_t link_enc_index; 5844 /** 5845 * HPO mode. 5846 */ 5847 uint8_t hpo_mode; 5848 5849 /** 5850 * Reserved field. 5851 */ 5852 uint8_t reserved[7]; 5853 }; 5854 5855 /** 5856 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5857 */ 5858 struct dmub_rb_cmd_assr_enable { 5859 /** 5860 * Command header. 5861 */ 5862 struct dmub_cmd_header header; 5863 5864 /** 5865 * Assr data. 5866 */ 5867 struct dmub_cmd_assr_enable_data assr_data; 5868 5869 /** 5870 * Reserved field. 5871 */ 5872 uint32_t reserved[3]; 5873 }; 5874 5875 /** 5876 * Current definition of "ips_mode" from driver 5877 */ 5878 enum ips_residency_mode { 5879 IPS_RESIDENCY__IPS1_MAX, 5880 IPS_RESIDENCY__IPS2, 5881 IPS_RESIDENCY__IPS1_RCG, 5882 IPS_RESIDENCY__IPS1_ONO2_ON, 5883 }; 5884 5885 #define NUM_IPS_HISTOGRAM_BUCKETS 16 5886 5887 /** 5888 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 5889 */ 5890 struct dmub_ips_residency_info { 5891 uint32_t residency_millipercent; 5892 uint32_t entry_counter; 5893 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 5894 uint64_t total_time_us; 5895 uint64_t total_inactive_time_us; 5896 }; 5897 5898 /** 5899 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 5900 */ 5901 struct dmub_cmd_ips_residency_cntl_data { 5902 uint8_t panel_inst; 5903 uint8_t start_measurement; 5904 uint8_t padding[2]; // align to 4-byte boundary 5905 }; 5906 5907 struct dmub_rb_cmd_ips_residency_cntl { 5908 struct dmub_cmd_header header; 5909 struct dmub_cmd_ips_residency_cntl_data cntl_data; 5910 }; 5911 5912 /** 5913 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 5914 */ 5915 struct dmub_cmd_ips_query_residency_info_data { 5916 union dmub_addr dest; 5917 uint32_t size; 5918 uint32_t ips_mode; 5919 uint8_t panel_inst; 5920 uint8_t padding[3]; // align to 4-byte boundary 5921 }; 5922 5923 struct dmub_rb_cmd_ips_query_residency_info { 5924 struct dmub_cmd_header header; 5925 struct dmub_cmd_ips_query_residency_info_data info_data; 5926 }; 5927 5928 /** 5929 * union dmub_rb_cmd - DMUB inbox command. 5930 */ 5931 union dmub_rb_cmd { 5932 /** 5933 * Elements shared with all commands. 5934 */ 5935 struct dmub_rb_cmd_common cmd_common; 5936 /** 5937 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5938 */ 5939 struct dmub_rb_cmd_read_modify_write read_modify_write; 5940 /** 5941 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5942 */ 5943 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5944 /** 5945 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5946 */ 5947 struct dmub_rb_cmd_burst_write burst_write; 5948 /** 5949 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5950 */ 5951 struct dmub_rb_cmd_reg_wait reg_wait; 5952 /** 5953 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5954 */ 5955 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5956 /** 5957 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5958 */ 5959 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5960 /** 5961 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5962 */ 5963 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5964 /** 5965 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5966 */ 5967 struct dmub_rb_cmd_dpphy_init dpphy_init; 5968 /** 5969 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5970 */ 5971 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5972 /** 5973 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5974 */ 5975 struct dmub_rb_cmd_domain_control domain_control; 5976 /** 5977 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5978 */ 5979 struct dmub_rb_cmd_psr_set_version psr_set_version; 5980 /** 5981 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5982 */ 5983 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5984 /** 5985 * Definition of a DMUB_CMD__PSR_ENABLE command. 5986 */ 5987 struct dmub_rb_cmd_psr_enable psr_enable; 5988 /** 5989 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5990 */ 5991 struct dmub_rb_cmd_psr_set_level psr_set_level; 5992 /** 5993 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5994 */ 5995 struct dmub_rb_cmd_psr_force_static psr_force_static; 5996 /** 5997 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5998 */ 5999 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6000 /** 6001 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6002 */ 6003 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6004 /** 6005 * Definition of a DMUB_CMD__HW_LOCK command. 6006 * Command is used by driver and FW. 6007 */ 6008 struct dmub_rb_cmd_lock_hw lock_hw; 6009 /** 6010 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6011 */ 6012 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6013 /** 6014 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6015 */ 6016 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6017 /** 6018 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6019 */ 6020 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6021 /** 6022 * Definition of a DMUB_CMD__MALL command. 6023 */ 6024 struct dmub_rb_cmd_mall mall; 6025 6026 /** 6027 * Definition of a DMUB_CMD__CAB command. 6028 */ 6029 struct dmub_rb_cmd_cab_for_ss cab; 6030 6031 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6032 6033 /** 6034 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6035 */ 6036 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6037 6038 /** 6039 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6040 */ 6041 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6042 6043 /** 6044 * Definition of DMUB_CMD__PANEL_CNTL commands. 6045 */ 6046 struct dmub_rb_cmd_panel_cntl panel_cntl; 6047 6048 /** 6049 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6050 */ 6051 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6052 6053 /** 6054 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6055 */ 6056 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6057 6058 /** 6059 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6060 */ 6061 struct dmub_rb_cmd_abm_set_level abm_set_level; 6062 6063 /** 6064 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6065 */ 6066 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6067 6068 /** 6069 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6070 */ 6071 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6072 6073 /** 6074 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6075 */ 6076 struct dmub_rb_cmd_abm_init_config abm_init_config; 6077 6078 /** 6079 * Definition of a DMUB_CMD__ABM_PAUSE command. 6080 */ 6081 struct dmub_rb_cmd_abm_pause abm_pause; 6082 6083 /** 6084 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6085 */ 6086 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6087 6088 /** 6089 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6090 */ 6091 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6092 6093 /** 6094 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6095 */ 6096 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6097 6098 /** 6099 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6100 */ 6101 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6102 6103 /** 6104 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6105 */ 6106 struct dmub_rb_cmd_abm_set_event abm_set_event; 6107 6108 /** 6109 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6110 */ 6111 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6112 6113 /** 6114 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6115 */ 6116 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6117 6118 /** 6119 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6120 */ 6121 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6122 6123 /** 6124 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6125 */ 6126 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6127 struct dmub_rb_cmd_drr_update drr_update; 6128 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6129 6130 /** 6131 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6132 */ 6133 struct dmub_rb_cmd_lvtma_control lvtma_control; 6134 /** 6135 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6136 */ 6137 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6138 /** 6139 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6140 */ 6141 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6142 /** 6143 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6144 */ 6145 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6146 /** 6147 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6148 */ 6149 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6150 /** 6151 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6152 */ 6153 struct dmub_rb_cmd_set_config_request set_config_request; 6154 /** 6155 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6156 */ 6157 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6158 /** 6159 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6160 */ 6161 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6162 /** 6163 * Definition of a DMUB_CMD__EDID_CEA command. 6164 */ 6165 struct dmub_rb_cmd_edid_cea edid_cea; 6166 /** 6167 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6168 */ 6169 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6170 6171 /** 6172 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6173 */ 6174 struct dmub_rb_cmd_query_hpd_state query_hpd; 6175 /** 6176 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6177 */ 6178 struct dmub_rb_cmd_secure_display secure_display; 6179 6180 /** 6181 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6182 */ 6183 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6184 /** 6185 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6186 */ 6187 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6188 /** 6189 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6190 */ 6191 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6192 /* 6193 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6194 */ 6195 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6196 /** 6197 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6198 */ 6199 struct dmub_rb_cmd_replay_enable replay_enable; 6200 /** 6201 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6202 */ 6203 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6204 /** 6205 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6206 */ 6207 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6208 /** 6209 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6210 */ 6211 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6212 6213 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6214 /** 6215 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6216 */ 6217 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6218 /** 6219 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6220 */ 6221 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6222 /** 6223 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6224 */ 6225 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6226 /** 6227 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6228 */ 6229 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6230 /** 6231 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6232 */ 6233 struct dmub_rb_cmd_assr_enable assr_enable; 6234 6235 struct dmub_rb_cmd_fams2 fams2_config; 6236 6237 struct dmub_rb_cmd_ib ib_fams2_config; 6238 6239 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6240 6241 struct dmub_rb_cmd_fams2_flip fams2_flip; 6242 6243 struct dmub_rb_cmd_fused_io fused_io; 6244 6245 /** 6246 * Definition of a DMUB_CMD__LSDMA command. 6247 */ 6248 struct dmub_rb_cmd_lsdma lsdma; 6249 6250 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 6251 6252 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 6253 }; 6254 6255 /** 6256 * union dmub_rb_out_cmd - Outbox command 6257 */ 6258 union dmub_rb_out_cmd { 6259 /** 6260 * Parameters common to every command. 6261 */ 6262 struct dmub_rb_cmd_common cmd_common; 6263 /** 6264 * AUX reply command. 6265 */ 6266 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6267 /** 6268 * HPD notify command. 6269 */ 6270 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6271 /** 6272 * SET_CONFIG reply command. 6273 */ 6274 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6275 /** 6276 * DPIA notification command. 6277 */ 6278 struct dmub_rb_cmd_dpia_notification dpia_notification; 6279 /** 6280 * HPD sense notification command. 6281 */ 6282 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6283 struct dmub_rb_cmd_fused_io fused_io; 6284 }; 6285 #pragma pack(pop) 6286 6287 6288 //============================================================================== 6289 //</DMUB_CMD>=================================================================== 6290 //============================================================================== 6291 //< DMUB_RB>==================================================================== 6292 //============================================================================== 6293 6294 /** 6295 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6296 */ 6297 struct dmub_rb_init_params { 6298 void *ctx; /**< Caller provided context pointer */ 6299 void *base_address; /**< CPU base address for ring's data */ 6300 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6301 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6302 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6303 }; 6304 6305 /** 6306 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6307 */ 6308 struct dmub_rb { 6309 void *base_address; /**< CPU address for the ring's data */ 6310 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6311 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6312 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6313 6314 void *ctx; /**< Caller provided context pointer */ 6315 void *dmub; /**< Pointer to the DMUB interface */ 6316 }; 6317 6318 /** 6319 * @brief Checks if the ringbuffer is empty. 6320 * 6321 * @param rb DMUB Ringbuffer 6322 * @return true if empty 6323 * @return false otherwise 6324 */ 6325 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6326 { 6327 return (rb->wrpt == rb->rptr); 6328 } 6329 6330 /** 6331 * @brief gets number of outstanding requests in the RB 6332 * 6333 * @param rb DMUB Ringbuffer 6334 * @return true if full 6335 */ 6336 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6337 { 6338 uint32_t data_count; 6339 6340 if (rb->wrpt >= rb->rptr) 6341 data_count = rb->wrpt - rb->rptr; 6342 else 6343 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6344 6345 return data_count / DMUB_RB_CMD_SIZE; 6346 } 6347 6348 /** 6349 * @brief gets number of free buffers in the RB 6350 * 6351 * @param rb DMUB Ringbuffer 6352 * @return true if full 6353 */ 6354 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6355 { 6356 uint32_t data_count; 6357 6358 if (rb->wrpt >= rb->rptr) 6359 data_count = rb->wrpt - rb->rptr; 6360 else 6361 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6362 6363 /* +1 because 1 entry is always unusable */ 6364 data_count += DMUB_RB_CMD_SIZE; 6365 6366 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6367 } 6368 6369 /** 6370 * @brief Checks if the ringbuffer is full 6371 * 6372 * @param rb DMUB Ringbuffer 6373 * @return true if full 6374 * @return false otherwise 6375 */ 6376 static inline bool dmub_rb_full(struct dmub_rb *rb) 6377 { 6378 uint32_t data_count; 6379 6380 if (rb->wrpt >= rb->rptr) 6381 data_count = rb->wrpt - rb->rptr; 6382 else 6383 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6384 6385 /* -1 because 1 entry is always unusable */ 6386 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6387 } 6388 6389 /** 6390 * @brief Pushes a command into the ringbuffer 6391 * 6392 * @param rb DMUB ringbuffer 6393 * @param cmd The command to push 6394 * @return true if the ringbuffer was not full 6395 * @return false otherwise 6396 */ 6397 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6398 const union dmub_rb_cmd *cmd) 6399 { 6400 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6401 const uint64_t *src = (const uint64_t *)cmd; 6402 uint8_t i; 6403 6404 if (dmub_rb_full(rb)) 6405 return false; 6406 6407 // copying data 6408 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6409 *dst++ = *src++; 6410 6411 rb->wrpt += DMUB_RB_CMD_SIZE; 6412 6413 if (rb->wrpt >= rb->capacity) 6414 rb->wrpt %= rb->capacity; 6415 6416 return true; 6417 } 6418 6419 /** 6420 * @brief Pushes a command into the DMUB outbox ringbuffer 6421 * 6422 * @param rb DMUB outbox ringbuffer 6423 * @param cmd Outbox command 6424 * @return true if not full 6425 * @return false otherwise 6426 */ 6427 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6428 const union dmub_rb_out_cmd *cmd) 6429 { 6430 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6431 const uint8_t *src = (const uint8_t *)cmd; 6432 6433 if (dmub_rb_full(rb)) 6434 return false; 6435 6436 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6437 6438 rb->wrpt += DMUB_RB_CMD_SIZE; 6439 6440 if (rb->wrpt >= rb->capacity) 6441 rb->wrpt %= rb->capacity; 6442 6443 return true; 6444 } 6445 6446 /** 6447 * @brief Returns the next unprocessed command in the ringbuffer. 6448 * 6449 * @param rb DMUB ringbuffer 6450 * @param cmd The command to return 6451 * @return true if not empty 6452 * @return false otherwise 6453 */ 6454 static inline bool dmub_rb_front(struct dmub_rb *rb, 6455 union dmub_rb_cmd **cmd) 6456 { 6457 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6458 6459 if (dmub_rb_empty(rb)) 6460 return false; 6461 6462 *cmd = (union dmub_rb_cmd *)rb_cmd; 6463 6464 return true; 6465 } 6466 6467 /** 6468 * @brief Determines the next ringbuffer offset. 6469 * 6470 * @param rb DMUB inbox ringbuffer 6471 * @param num_cmds Number of commands 6472 * @param next_rptr The next offset in the ringbuffer 6473 */ 6474 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6475 uint32_t num_cmds, 6476 uint32_t *next_rptr) 6477 { 6478 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6479 6480 if (*next_rptr >= rb->capacity) 6481 *next_rptr %= rb->capacity; 6482 } 6483 6484 /** 6485 * @brief Returns a pointer to a command in the inbox. 6486 * 6487 * @param rb DMUB inbox ringbuffer 6488 * @param cmd The inbox command to return 6489 * @param rptr The ringbuffer offset 6490 * @return true if not empty 6491 * @return false otherwise 6492 */ 6493 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6494 union dmub_rb_cmd **cmd, 6495 uint32_t rptr) 6496 { 6497 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6498 6499 if (dmub_rb_empty(rb)) 6500 return false; 6501 6502 *cmd = (union dmub_rb_cmd *)rb_cmd; 6503 6504 return true; 6505 } 6506 6507 /** 6508 * @brief Returns the next unprocessed command in the outbox. 6509 * 6510 * @param rb DMUB outbox ringbuffer 6511 * @param cmd The outbox command to return 6512 * @return true if not empty 6513 * @return false otherwise 6514 */ 6515 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6516 union dmub_rb_out_cmd *cmd) 6517 { 6518 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6519 uint64_t *dst = (uint64_t *)cmd; 6520 uint8_t i; 6521 6522 if (dmub_rb_empty(rb)) 6523 return false; 6524 6525 // copying data 6526 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6527 *dst++ = *src++; 6528 6529 return true; 6530 } 6531 6532 /** 6533 * @brief Removes the front entry in the ringbuffer. 6534 * 6535 * @param rb DMUB ringbuffer 6536 * @return true if the command was removed 6537 * @return false if there were no commands 6538 */ 6539 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6540 { 6541 if (dmub_rb_empty(rb)) 6542 return false; 6543 6544 rb->rptr += DMUB_RB_CMD_SIZE; 6545 6546 if (rb->rptr >= rb->capacity) 6547 rb->rptr %= rb->capacity; 6548 6549 return true; 6550 } 6551 6552 /** 6553 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6554 * 6555 * Avoids a race condition where DMCUB accesses memory while 6556 * there are still writes in flight to framebuffer. 6557 * 6558 * @param rb DMUB ringbuffer 6559 */ 6560 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6561 { 6562 uint32_t rptr = rb->rptr; 6563 uint32_t wptr = rb->wrpt; 6564 6565 while (rptr != wptr) { 6566 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6567 uint8_t i; 6568 6569 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6570 (void)READ_ONCE(*data++); 6571 6572 rptr += DMUB_RB_CMD_SIZE; 6573 if (rptr >= rb->capacity) 6574 rptr %= rb->capacity; 6575 } 6576 } 6577 6578 /** 6579 * @brief Initializes a DMCUB ringbuffer 6580 * 6581 * @param rb DMUB ringbuffer 6582 * @param init_params initial configuration for the ringbuffer 6583 */ 6584 static inline void dmub_rb_init(struct dmub_rb *rb, 6585 struct dmub_rb_init_params *init_params) 6586 { 6587 rb->base_address = init_params->base_address; 6588 rb->capacity = init_params->capacity; 6589 rb->rptr = init_params->read_ptr; 6590 rb->wrpt = init_params->write_ptr; 6591 } 6592 6593 /** 6594 * @brief Copies output data from in/out commands into the given command. 6595 * 6596 * @param rb DMUB ringbuffer 6597 * @param cmd Command to copy data into 6598 */ 6599 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6600 union dmub_rb_cmd *cmd) 6601 { 6602 // Copy rb entry back into command 6603 uint8_t *rd_ptr = (rb->rptr == 0) ? 6604 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6605 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6606 6607 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6608 } 6609 6610 //============================================================================== 6611 //</DMUB_RB>==================================================================== 6612 //============================================================================== 6613 #endif /* _DMUB_CMD_H_ */ 6614