1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic udelay 165 */ 166 #ifndef dmub_udelay 167 #define dmub_udelay(microseconds) udelay(microseconds) 168 #endif 169 170 #pragma pack(push, 1) 171 #define ABM_NUM_OF_ACE_SEGMENTS 5 172 173 /** 174 * Debug FW state offset 175 */ 176 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 177 178 union abm_flags { 179 struct { 180 /** 181 * @abm_enabled: Indicates if ABM is enabled. 182 */ 183 unsigned int abm_enabled : 1; 184 185 /** 186 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 187 */ 188 unsigned int disable_abm_requested : 1; 189 190 /** 191 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 192 */ 193 unsigned int disable_abm_immediately : 1; 194 195 /** 196 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 197 * to be disabled immediately and keep gain. 198 */ 199 unsigned int disable_abm_immediate_keep_gain : 1; 200 201 /** 202 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 203 */ 204 unsigned int fractional_pwm : 1; 205 206 /** 207 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 208 * of user backlight level. 209 */ 210 unsigned int abm_gradual_bl_change : 1; 211 212 /** 213 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 214 */ 215 unsigned int abm_new_frame : 1; 216 217 /** 218 * @vb_scaling_enabled: Indicates variBright Scaling Enable 219 */ 220 unsigned int vb_scaling_enabled : 1; 221 } bitfields; 222 223 unsigned int u32All; 224 }; 225 226 struct abm_save_restore { 227 /** 228 * @flags: Misc. ABM flags. 229 */ 230 union abm_flags flags; 231 232 /** 233 * @pause: true: pause ABM and get state 234 * false: unpause ABM after setting state 235 */ 236 uint32_t pause; 237 238 /** 239 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 240 */ 241 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 242 243 /** 244 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 245 */ 246 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 247 248 /** 249 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 250 */ 251 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 252 253 254 /** 255 * @knee_threshold: Current x-position of ACE knee (u0.16). 256 */ 257 uint32_t knee_threshold; 258 /** 259 * @current_gain: Current backlight reduction (u16.16). 260 */ 261 uint32_t current_gain; 262 /** 263 * @curr_bl_level: Current actual backlight level converging to target backlight level. 264 */ 265 uint16_t curr_bl_level; 266 267 /** 268 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 269 */ 270 uint16_t curr_user_bl_level; 271 272 }; 273 274 /** 275 * union dmub_addr - DMUB physical/virtual 64-bit address. 276 */ 277 union dmub_addr { 278 struct { 279 uint32_t low_part; /**< Lower 32 bits */ 280 uint32_t high_part; /**< Upper 32 bits */ 281 } u; /*<< Low/high bit access */ 282 uint64_t quad_part; /*<< 64 bit address */ 283 }; 284 #pragma pack(pop) 285 286 /** 287 * Dirty rect definition. 288 */ 289 struct dmub_rect { 290 /** 291 * Dirty rect x offset. 292 */ 293 uint32_t x; 294 295 /** 296 * Dirty rect y offset. 297 */ 298 uint32_t y; 299 300 /** 301 * Dirty rect width. 302 */ 303 uint32_t width; 304 305 /** 306 * Dirty rect height. 307 */ 308 uint32_t height; 309 }; 310 311 /** 312 * Flags that can be set by driver to change some PSR behaviour. 313 */ 314 union dmub_psr_debug_flags { 315 /** 316 * Debug flags. 317 */ 318 struct { 319 /** 320 * Enable visual confirm in FW. 321 */ 322 uint32_t visual_confirm : 1; 323 324 /** 325 * Force all selective updates to bw full frame updates. 326 */ 327 uint32_t force_full_frame_update : 1; 328 329 /** 330 * Use HW Lock Mgr object to do HW locking in FW. 331 */ 332 uint32_t use_hw_lock_mgr : 1; 333 334 /** 335 * Use TPS3 signal when restore main link. 336 */ 337 uint32_t force_wakeup_by_tps3 : 1; 338 339 /** 340 * Back to back flip, therefore cannot power down PHY 341 */ 342 uint32_t back_to_back_flip : 1; 343 344 /** 345 * Enable visual confirm for IPS 346 */ 347 uint32_t enable_ips_visual_confirm : 1; 348 } bitfields; 349 350 /** 351 * Union for debug flags. 352 */ 353 uint32_t u32All; 354 }; 355 356 /** 357 * Flags that can be set by driver to change some Replay behaviour. 358 */ 359 union replay_debug_flags { 360 struct { 361 /** 362 * 0x1 (bit 0) 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * 0x2 (bit 1) 369 * @skip_crc: Set if need to skip CRC. 370 */ 371 uint32_t skip_crc : 1; 372 373 /** 374 * 0x4 (bit 2) 375 * @force_link_power_on: Force disable ALPM control 376 */ 377 uint32_t force_link_power_on : 1; 378 379 /** 380 * 0x8 (bit 3) 381 * @force_phy_power_on: Force phy power on 382 */ 383 uint32_t force_phy_power_on : 1; 384 385 /** 386 * 0x10 (bit 4) 387 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 388 */ 389 uint32_t timing_resync_disabled : 1; 390 391 /** 392 * 0x20 (bit 5) 393 * @skip_crtc_disabled: CRTC disable skipped 394 */ 395 uint32_t skip_crtc_disabled : 1; 396 397 /** 398 * 0x40 (bit 6) 399 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 400 */ 401 uint32_t force_defer_one_frame_update : 1; 402 403 /** 404 * 0x80 (bit 7) 405 * @disable_delay_alpm_on: Force disable delay alpm on 406 */ 407 uint32_t disable_delay_alpm_on : 1; 408 409 /** 410 * 0x100 (bit 8) 411 * @disable_desync_error_check: Force disable desync error check 412 */ 413 uint32_t disable_desync_error_check : 1; 414 415 /** 416 * 0x200 (bit 9) 417 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 418 */ 419 uint32_t force_self_update_when_abm_non_steady : 1; 420 421 /** 422 * 0x400 (bit 10) 423 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 424 * If we enter IPS2, the Visual confirm bar will change to yellow 425 */ 426 uint32_t enable_ips_visual_confirm : 1; 427 428 /** 429 * 0x800 (bit 11) 430 * @enable_ips_residency_profiling: Enable IPS residency profiling 431 */ 432 uint32_t enable_ips_residency_profiling : 1; 433 434 uint32_t reserved : 20; 435 } bitfields; 436 437 uint32_t u32All; 438 }; 439 440 union replay_hw_flags { 441 struct { 442 /** 443 * @allow_alpm_fw_standby_mode: To indicate whether the 444 * ALPM FW standby mode is allowed 445 */ 446 uint32_t allow_alpm_fw_standby_mode : 1; 447 448 /* 449 * @dsc_enable_status: DSC enable status in driver 450 */ 451 uint32_t dsc_enable_status : 1; 452 453 /** 454 * @fec_enable_status: receive fec enable/disable status from driver 455 */ 456 uint32_t fec_enable_status : 1; 457 458 /* 459 * @smu_optimizations_en: SMU power optimization. 460 * Only when active display is Replay capable and display enters Replay. 461 * Trigger interrupt to SMU to powerup/down. 462 */ 463 uint32_t smu_optimizations_en : 1; 464 465 /** 466 * @phy_power_state: Indicates current phy power state 467 */ 468 uint32_t phy_power_state : 1; 469 470 /** 471 * @link_power_state: Indicates current link power state 472 */ 473 uint32_t link_power_state : 1; 474 /** 475 * Use TPS3 signal when restore main link. 476 */ 477 uint32_t force_wakeup_by_tps3 : 1; 478 } bitfields; 479 480 uint32_t u32All; 481 }; 482 483 /** 484 * DMUB feature capabilities. 485 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 486 */ 487 struct dmub_feature_caps { 488 /** 489 * Max PSR version supported by FW. 490 */ 491 uint8_t psr; 492 uint8_t fw_assisted_mclk_switch_ver; 493 uint8_t reserved[4]; 494 uint8_t subvp_psr_support; 495 uint8_t gecc_enable; 496 uint8_t replay_supported; 497 uint8_t replay_reserved[3]; 498 uint8_t abm_aux_backlight_support; 499 }; 500 501 struct dmub_visual_confirm_color { 502 /** 503 * Maximum 10 bits color value 504 */ 505 uint16_t color_r_cr; 506 uint16_t color_g_y; 507 uint16_t color_b_cb; 508 uint16_t panel_inst; 509 }; 510 511 //============================================================================== 512 //</DMUB_TYPES>================================================================= 513 //============================================================================== 514 //< DMUB_META>================================================================== 515 //============================================================================== 516 #pragma pack(push, 1) 517 518 /* Magic value for identifying dmub_fw_meta_info */ 519 #define DMUB_FW_META_MAGIC 0x444D5542 520 521 /* Offset from the end of the file to the dmub_fw_meta_info */ 522 #define DMUB_FW_META_OFFSET 0x24 523 524 /** 525 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 526 */ 527 union dmub_fw_meta_feature_bits { 528 struct { 529 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 530 uint32_t reserved : 31; 531 } bits; /**< status bits */ 532 uint32_t all; /**< 32-bit access to status bits */ 533 }; 534 535 /** 536 * struct dmub_fw_meta_info - metadata associated with fw binary 537 * 538 * NOTE: This should be considered a stable API. Fields should 539 * not be repurposed or reordered. New fields should be 540 * added instead to extend the structure. 541 * 542 * @magic_value: magic value identifying DMUB firmware meta info 543 * @fw_region_size: size of the firmware state region 544 * @trace_buffer_size: size of the tracebuffer region 545 * @fw_version: the firmware version information 546 * @dal_fw: 1 if the firmware is DAL 547 * @shared_state_size: size of the shared state region in bytes 548 * @shared_state_features: number of shared state features 549 */ 550 struct dmub_fw_meta_info { 551 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 552 uint32_t fw_region_size; /**< size of the firmware state region */ 553 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 554 uint32_t fw_version; /**< the firmware version information */ 555 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 556 uint8_t reserved[3]; /**< padding bits */ 557 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 558 uint16_t shared_state_features; /**< number of shared state features */ 559 uint16_t reserved2; /**< padding bytes */ 560 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 561 }; 562 563 /** 564 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 565 */ 566 union dmub_fw_meta { 567 struct dmub_fw_meta_info info; /**< metadata info */ 568 uint8_t reserved[64]; /**< padding bits */ 569 }; 570 571 #pragma pack(pop) 572 573 //============================================================================== 574 //< DMUB Trace Buffer>================================================================ 575 //============================================================================== 576 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 577 /** 578 * dmub_trace_code_t - firmware trace code, 32-bits 579 */ 580 typedef uint32_t dmub_trace_code_t; 581 582 /** 583 * struct dmcub_trace_buf_entry - Firmware trace entry 584 */ 585 struct dmcub_trace_buf_entry { 586 dmub_trace_code_t trace_code; /**< trace code for the event */ 587 uint32_t tick_count; /**< the tick count at time of trace */ 588 uint32_t param0; /**< trace defined parameter 0 */ 589 uint32_t param1; /**< trace defined parameter 1 */ 590 }; 591 #endif 592 593 //============================================================================== 594 //< DMUB_STATUS>================================================================ 595 //============================================================================== 596 597 /** 598 * DMCUB scratch registers can be used to determine firmware status. 599 * Current scratch register usage is as follows: 600 * 601 * SCRATCH0: FW Boot Status register 602 * SCRATCH5: LVTMA Status Register 603 * SCRATCH15: FW Boot Options register 604 */ 605 606 /** 607 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 608 */ 609 union dmub_fw_boot_status { 610 struct { 611 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 612 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 613 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 614 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 615 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 616 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 617 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 618 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 619 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 620 } bits; /**< status bits */ 621 uint32_t all; /**< 32-bit access to status bits */ 622 }; 623 624 /** 625 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 626 */ 627 enum dmub_fw_boot_status_bit { 628 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 629 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 630 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 631 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 632 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 633 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 634 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 635 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 636 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 637 }; 638 639 /* Register bit definition for SCRATCH5 */ 640 union dmub_lvtma_status { 641 struct { 642 uint32_t psp_ok : 1; 643 uint32_t edp_on : 1; 644 uint32_t reserved : 30; 645 } bits; 646 uint32_t all; 647 }; 648 649 enum dmub_lvtma_status_bit { 650 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 651 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 652 }; 653 654 enum dmub_ips_disable_type { 655 DMUB_IPS_ENABLE = 0, 656 DMUB_IPS_DISABLE_ALL = 1, 657 DMUB_IPS_DISABLE_IPS1 = 2, 658 DMUB_IPS_DISABLE_IPS2 = 3, 659 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 660 DMUB_IPS_DISABLE_DYNAMIC = 5, 661 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 662 }; 663 664 #define DMUB_IPS1_ALLOW_MASK 0x00000001 665 #define DMUB_IPS2_ALLOW_MASK 0x00000002 666 #define DMUB_IPS1_COMMIT_MASK 0x00000004 667 #define DMUB_IPS2_COMMIT_MASK 0x00000008 668 669 /** 670 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 671 */ 672 union dmub_fw_boot_options { 673 struct { 674 uint32_t pemu_env : 1; /**< 1 if PEMU */ 675 uint32_t fpga_env : 1; /**< 1 if FPGA */ 676 uint32_t optimized_init : 1; /**< 1 if optimized init */ 677 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 678 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 679 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 680 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 681 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 682 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 683 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 684 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 685 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 686 uint32_t power_optimization: 1; 687 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 688 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 689 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 690 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 691 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 692 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 693 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 694 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 695 uint32_t ips_disable: 3; /* options to disable ips support*/ 696 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 697 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 698 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 699 uint32_t reserved : 6; /**< reserved */ 700 } bits; /**< boot bits */ 701 uint32_t all; /**< 32-bit access to bits */ 702 }; 703 704 enum dmub_fw_boot_options_bit { 705 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 706 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 707 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 708 }; 709 710 //============================================================================== 711 //< DMUB_SHARED_STATE>========================================================== 712 //============================================================================== 713 714 /** 715 * Shared firmware state between driver and firmware for lockless communication 716 * in situations where the inbox/outbox may be unavailable. 717 * 718 * Each structure *must* be at most 256-bytes in size. The layout allocation is 719 * described below: 720 * 721 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 722 */ 723 724 /** 725 * enum dmub_shared_state_feature_id - List of shared state features. 726 */ 727 enum dmub_shared_state_feature_id { 728 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 729 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 730 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 731 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 732 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 733 }; 734 735 /** 736 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 737 */ 738 union dmub_shared_state_ips_fw_signals { 739 struct { 740 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 741 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 742 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 743 uint32_t detection_required : 1; /**< 1 if detection is required */ 744 uint32_t reserved_bits : 28; /**< Reversed */ 745 } bits; 746 uint32_t all; 747 }; 748 749 /** 750 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 751 */ 752 union dmub_shared_state_ips_driver_signals { 753 struct { 754 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 755 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 756 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 757 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 758 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 759 uint32_t reserved_bits : 27; /**< Reversed bits */ 760 } bits; 761 uint32_t all; 762 }; 763 764 /** 765 * IPS FW Version 766 */ 767 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 768 769 struct dmub_shared_state_debug_setup { 770 union { 771 struct { 772 uint32_t exclude_points[62]; 773 } profile_mode; 774 }; 775 }; 776 777 /** 778 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 779 */ 780 struct dmub_shared_state_ips_fw { 781 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 782 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 783 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 784 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 785 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 786 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 787 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 788 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 789 }; /* 248-bytes, fixed */ 790 791 /** 792 * IPS Driver Version 793 */ 794 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 795 796 /** 797 * struct dmub_shared_state_ips_driver - Driver state for IPS. 798 */ 799 struct dmub_shared_state_ips_driver { 800 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 801 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 802 }; /* 248-bytes, fixed */ 803 804 /** 805 * enum dmub_shared_state_feature_common - Generic payload. 806 */ 807 struct dmub_shared_state_feature_common { 808 uint32_t padding[62]; 809 }; /* 248-bytes, fixed */ 810 811 /** 812 * enum dmub_shared_state_feature_header - Feature description. 813 */ 814 struct dmub_shared_state_feature_header { 815 uint16_t id; /**< Feature ID */ 816 uint16_t version; /**< Feature version */ 817 uint32_t reserved; /**< Reserved bytes. */ 818 }; /* 8 bytes, fixed */ 819 820 /** 821 * struct dmub_shared_state_feature_block - Feature block. 822 */ 823 struct dmub_shared_state_feature_block { 824 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 825 union dmub_shared_feature_state_union { 826 struct dmub_shared_state_feature_common common; /**< Generic data */ 827 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 828 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 829 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 830 } data; /**< Shared state data. */ 831 }; /* 256-bytes, fixed */ 832 833 /** 834 * Shared state size in bytes. 835 */ 836 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 837 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 838 839 //============================================================================== 840 //</DMUB_STATUS>================================================================ 841 //============================================================================== 842 //< DMUB_VBIOS>================================================================= 843 //============================================================================== 844 845 /* 846 * enum dmub_cmd_vbios_type - VBIOS commands. 847 * 848 * Command IDs should be treated as stable ABI. 849 * Do not reuse or modify IDs. 850 */ 851 enum dmub_cmd_vbios_type { 852 /** 853 * Configures the DIG encoder. 854 */ 855 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 856 /** 857 * Controls the PHY. 858 */ 859 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 860 /** 861 * Sets the pixel clock/symbol clock. 862 */ 863 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 864 /** 865 * Enables or disables power gating. 866 */ 867 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 868 /** 869 * Controls embedded panels. 870 */ 871 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 872 /** 873 * Query DP alt status on a transmitter. 874 */ 875 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 876 /** 877 * Control PHY FSM 878 */ 879 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 880 /** 881 * Controls domain power gating 882 */ 883 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 884 }; 885 886 //============================================================================== 887 //</DMUB_VBIOS>================================================================= 888 //============================================================================== 889 //< DMUB_GPINT>================================================================= 890 //============================================================================== 891 892 /** 893 * The shifts and masks below may alternatively be used to format and read 894 * the command register bits. 895 */ 896 897 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 898 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 899 900 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 901 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 902 903 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 904 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 905 906 /** 907 * Command responses. 908 */ 909 910 /** 911 * Return response for DMUB_GPINT__STOP_FW command. 912 */ 913 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 914 915 /** 916 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 917 */ 918 union dmub_gpint_data_register { 919 struct { 920 uint32_t param : 16; /**< 16-bit parameter */ 921 uint32_t command_code : 12; /**< GPINT command */ 922 uint32_t status : 4; /**< Command status bit */ 923 } bits; /**< GPINT bit access */ 924 uint32_t all; /**< GPINT 32-bit access */ 925 }; 926 927 /* 928 * enum dmub_gpint_command - GPINT command to DMCUB FW 929 * 930 * Command IDs should be treated as stable ABI. 931 * Do not reuse or modify IDs. 932 */ 933 enum dmub_gpint_command { 934 /** 935 * Invalid command, ignored. 936 */ 937 DMUB_GPINT__INVALID_COMMAND = 0, 938 /** 939 * DESC: Queries the firmware version. 940 * RETURN: Firmware version. 941 */ 942 DMUB_GPINT__GET_FW_VERSION = 1, 943 /** 944 * DESC: Halts the firmware. 945 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 946 */ 947 DMUB_GPINT__STOP_FW = 2, 948 /** 949 * DESC: Get PSR state from FW. 950 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 951 */ 952 DMUB_GPINT__GET_PSR_STATE = 7, 953 /** 954 * DESC: Notifies DMCUB of the currently active streams. 955 * ARGS: Stream mask, 1 bit per active stream index. 956 */ 957 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 958 /** 959 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 960 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 961 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 962 * RETURN: PSR residency in milli-percent. 963 */ 964 DMUB_GPINT__PSR_RESIDENCY = 9, 965 966 /** 967 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 968 */ 969 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 970 971 /** 972 * DESC: Get REPLAY state from FW. 973 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 974 */ 975 DMUB_GPINT__GET_REPLAY_STATE = 13, 976 977 /** 978 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 979 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 980 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 981 * RETURN: REPLAY residency in milli-percent. 982 */ 983 DMUB_GPINT__REPLAY_RESIDENCY = 14, 984 985 /** 986 * DESC: Copy bounding box to the host. 987 * ARGS: Version of bounding box to copy 988 * RETURN: Result of copying bounding box 989 */ 990 DMUB_GPINT__BB_COPY = 96, 991 992 /** 993 * DESC: Updates the host addresses bit48~bit63 for bounding box. 994 * ARGS: The word3 for the 64 bit address 995 */ 996 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 997 998 /** 999 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1000 * ARGS: The word2 for the 64 bit address 1001 */ 1002 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1003 1004 /** 1005 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1006 * ARGS: The word1 for the 64 bit address 1007 */ 1008 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1009 1010 /** 1011 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1012 * ARGS: The word0 for the 64 bit address 1013 */ 1014 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1015 1016 /** 1017 * DESC: Updates the trace buffer lower 32-bit mask. 1018 * ARGS: The new mask 1019 * RETURN: Lower 32-bit mask. 1020 */ 1021 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1022 1023 /** 1024 * DESC: Updates the trace buffer mask bit0~bit15. 1025 * ARGS: The new mask 1026 * RETURN: Lower 32-bit mask. 1027 */ 1028 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1029 1030 /** 1031 * DESC: Updates the trace buffer mask bit16~bit31. 1032 * ARGS: The new mask 1033 * RETURN: Lower 32-bit mask. 1034 */ 1035 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1036 1037 /** 1038 * DESC: Updates the trace buffer mask bit32~bit47. 1039 * ARGS: The new mask 1040 * RETURN: Lower 32-bit mask. 1041 */ 1042 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1043 1044 /** 1045 * DESC: Updates the trace buffer mask bit48~bit63. 1046 * ARGS: The new mask 1047 * RETURN: Lower 32-bit mask. 1048 */ 1049 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1050 1051 /** 1052 * DESC: Read the trace buffer mask bi0~bit15. 1053 */ 1054 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1055 1056 /** 1057 * DESC: Read the trace buffer mask bit16~bit31. 1058 */ 1059 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1060 1061 /** 1062 * DESC: Read the trace buffer mask bi32~bit47. 1063 */ 1064 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1065 1066 /** 1067 * DESC: Updates the trace buffer mask bit32~bit63. 1068 */ 1069 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1070 1071 /** 1072 * DESC: Set IPS residency measurement 1073 * ARGS: 0 - Disable ips measurement 1074 * 1 - Enable ips measurement 1075 */ 1076 DMUB_GPINT__IPS_RESIDENCY = 121, 1077 1078 /** 1079 * DESC: Enable measurements for various task duration 1080 * ARGS: 0 - Disable measurement 1081 * 1 - Enable measurement 1082 */ 1083 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1084 1085 /** 1086 * DESC: Gets IPS residency in microseconds 1087 * ARGS: 0 - Return IPS1 residency 1088 * 1 - Return IPS2 residency 1089 * 2 - Return IPS1_RCG residency 1090 * 3 - Return IPS1_ONO2_ON residency 1091 * RETURN: Total residency in microseconds - lower 32 bits 1092 */ 1093 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1094 1095 /** 1096 * DESC: Gets IPS1 histogram counts 1097 * ARGS: Bucket index 1098 * RETURN: Total count for the bucket 1099 */ 1100 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1101 1102 /** 1103 * DESC: Gets IPS2 histogram counts 1104 * ARGS: Bucket index 1105 * RETURN: Total count for the bucket 1106 */ 1107 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1108 1109 /** 1110 * DESC: Gets IPS residency 1111 * ARGS: 0 - Return IPS1 residency 1112 * 1 - Return IPS2 residency 1113 * 2 - Return IPS1_RCG residency 1114 * 3 - Return IPS1_ONO2_ON residency 1115 * RETURN: Total residency in milli-percent. 1116 */ 1117 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1118 1119 /** 1120 * DESC: Gets IPS1_RCG histogram counts 1121 * ARGS: Bucket index 1122 * RETURN: Total count for the bucket 1123 */ 1124 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1125 1126 /** 1127 * DESC: Gets IPS1_ONO2_ON histogram counts 1128 * ARGS: Bucket index 1129 * RETURN: Total count for the bucket 1130 */ 1131 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1132 1133 /** 1134 * DESC: Gets IPS entry counter during residency measurement 1135 * ARGS: 0 - Return IPS1 entry counts 1136 * 1 - Return IPS2 entry counts 1137 * 2 - Return IPS1_RCG entry counts 1138 * 3 - Return IPS2_ONO2_ON entry counts 1139 * RETURN: Entry counter for selected IPS mode 1140 */ 1141 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1142 1143 /** 1144 * DESC: Gets IPS inactive residency in microseconds 1145 * ARGS: 0 - Return IPS1_MAX residency 1146 * 1 - Return IPS2 residency 1147 * 2 - Return IPS1_RCG residency 1148 * 3 - Return IPS1_ONO2_ON residency 1149 * RETURN: Total inactive residency in microseconds - lower 32 bits 1150 */ 1151 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1152 1153 /** 1154 * DESC: Gets IPS inactive residency in microseconds 1155 * ARGS: 0 - Return IPS1_MAX residency 1156 * 1 - Return IPS2 residency 1157 * 2 - Return IPS1_RCG residency 1158 * 3 - Return IPS1_ONO2_ON residency 1159 * RETURN: Total inactive residency in microseconds - upper 32 bits 1160 */ 1161 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1162 1163 /** 1164 * DESC: Gets IPS residency in microseconds 1165 * ARGS: 0 - Return IPS1 residency 1166 * 1 - Return IPS2 residency 1167 * 2 - Return IPS1_RCG residency 1168 * 3 - Return IPS1_ONO2_ON residency 1169 * RETURN: Total residency in microseconds - upper 32 bits 1170 */ 1171 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1172 /** 1173 * DESC: Setup debug configs. 1174 */ 1175 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1176 }; 1177 1178 /** 1179 * INBOX0 generic command definition 1180 */ 1181 union dmub_inbox0_cmd_common { 1182 struct { 1183 uint32_t command_code: 8; /**< INBOX0 command code */ 1184 uint32_t param: 24; /**< 24-bit parameter */ 1185 } bits; 1186 uint32_t all; 1187 }; 1188 1189 /** 1190 * INBOX0 hw_lock command definition 1191 */ 1192 union dmub_inbox0_cmd_lock_hw { 1193 struct { 1194 uint32_t command_code: 8; 1195 1196 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1197 uint32_t hw_lock_client: 2; 1198 1199 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1200 uint32_t otg_inst: 3; 1201 uint32_t opp_inst: 3; 1202 uint32_t dig_inst: 3; 1203 1204 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1205 uint32_t lock_pipe: 1; 1206 uint32_t lock_cursor: 1; 1207 uint32_t lock_dig: 1; 1208 uint32_t triple_buffer_lock: 1; 1209 1210 uint32_t lock: 1; /**< Lock */ 1211 uint32_t should_release: 1; /**< Release */ 1212 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1213 } bits; 1214 uint32_t all; 1215 }; 1216 1217 union dmub_inbox0_data_register { 1218 union dmub_inbox0_cmd_common inbox0_cmd_common; 1219 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1220 }; 1221 1222 enum dmub_inbox0_command { 1223 /** 1224 * DESC: Invalid command, ignored. 1225 */ 1226 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1227 /** 1228 * DESC: Notification to acquire/release HW lock 1229 * ARGS: 1230 */ 1231 DMUB_INBOX0_CMD__HW_LOCK = 1, 1232 }; 1233 //============================================================================== 1234 //</DMUB_GPINT>================================================================= 1235 //============================================================================== 1236 //< DMUB_CMD>=================================================================== 1237 //============================================================================== 1238 1239 /** 1240 * Size in bytes of each DMUB command. 1241 */ 1242 #define DMUB_RB_CMD_SIZE 64 1243 1244 /** 1245 * Maximum number of items in the DMUB ringbuffer. 1246 */ 1247 #define DMUB_RB_MAX_ENTRY 128 1248 1249 /** 1250 * Ringbuffer size in bytes. 1251 */ 1252 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1253 1254 /** 1255 * REG_SET mask for reg offload. 1256 */ 1257 #define REG_SET_MASK 0xFFFF 1258 1259 /* 1260 * enum dmub_cmd_type - DMUB inbox command. 1261 * 1262 * Command IDs should be treated as stable ABI. 1263 * Do not reuse or modify IDs. 1264 */ 1265 enum dmub_cmd_type { 1266 /** 1267 * Invalid command. 1268 */ 1269 DMUB_CMD__NULL = 0, 1270 /** 1271 * Read modify write register sequence offload. 1272 */ 1273 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1274 /** 1275 * Field update register sequence offload. 1276 */ 1277 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1278 /** 1279 * Burst write sequence offload. 1280 */ 1281 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1282 /** 1283 * Reg wait sequence offload. 1284 */ 1285 DMUB_CMD__REG_REG_WAIT = 4, 1286 /** 1287 * Workaround to avoid HUBP underflow during NV12 playback. 1288 */ 1289 DMUB_CMD__PLAT_54186_WA = 5, 1290 /** 1291 * Command type used to query FW feature caps. 1292 */ 1293 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1294 /** 1295 * Command type used to get visual confirm color. 1296 */ 1297 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1298 /** 1299 * Command type used for all PSR commands. 1300 */ 1301 DMUB_CMD__PSR = 64, 1302 /** 1303 * Command type used for all MALL commands. 1304 */ 1305 DMUB_CMD__MALL = 65, 1306 /** 1307 * Command type used for all ABM commands. 1308 */ 1309 DMUB_CMD__ABM = 66, 1310 /** 1311 * Command type used to update dirty rects in FW. 1312 */ 1313 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1314 /** 1315 * Command type used to update cursor info in FW. 1316 */ 1317 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1318 /** 1319 * Command type used for HW locking in FW. 1320 */ 1321 DMUB_CMD__HW_LOCK = 69, 1322 /** 1323 * Command type used to access DP AUX. 1324 */ 1325 DMUB_CMD__DP_AUX_ACCESS = 70, 1326 /** 1327 * Command type used for OUTBOX1 notification enable 1328 */ 1329 DMUB_CMD__OUTBOX1_ENABLE = 71, 1330 1331 /** 1332 * Command type used for all idle optimization commands. 1333 */ 1334 DMUB_CMD__IDLE_OPT = 72, 1335 /** 1336 * Command type used for all clock manager commands. 1337 */ 1338 DMUB_CMD__CLK_MGR = 73, 1339 /** 1340 * Command type used for all panel control commands. 1341 */ 1342 DMUB_CMD__PANEL_CNTL = 74, 1343 1344 /** 1345 * Command type used for all CAB commands. 1346 */ 1347 DMUB_CMD__CAB_FOR_SS = 75, 1348 1349 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1350 1351 /** 1352 * Command type used for interfacing with DPIA. 1353 */ 1354 DMUB_CMD__DPIA = 77, 1355 /** 1356 * Command type used for EDID CEA parsing 1357 */ 1358 DMUB_CMD__EDID_CEA = 79, 1359 /** 1360 * Command type used for getting usbc cable ID 1361 */ 1362 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1363 /** 1364 * Command type used to query HPD state. 1365 */ 1366 DMUB_CMD__QUERY_HPD_STATE = 82, 1367 /** 1368 * Command type used for all VBIOS interface commands. 1369 */ 1370 /** 1371 * Command type used for all REPLAY commands. 1372 */ 1373 DMUB_CMD__REPLAY = 83, 1374 1375 /** 1376 * Command type used for all SECURE_DISPLAY commands. 1377 */ 1378 DMUB_CMD__SECURE_DISPLAY = 85, 1379 1380 /** 1381 * Command type used to set DPIA HPD interrupt state 1382 */ 1383 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1384 1385 /** 1386 * Command type used for all PSP commands. 1387 */ 1388 DMUB_CMD__PSP = 88, 1389 1390 DMUB_CMD__VBIOS = 128, 1391 }; 1392 1393 /** 1394 * enum dmub_out_cmd_type - DMUB outbox commands. 1395 */ 1396 enum dmub_out_cmd_type { 1397 /** 1398 * Invalid outbox command, ignored. 1399 */ 1400 DMUB_OUT_CMD__NULL = 0, 1401 /** 1402 * Command type used for DP AUX Reply data notification 1403 */ 1404 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1405 /** 1406 * Command type used for DP HPD event notification 1407 */ 1408 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1409 /** 1410 * Command type used for SET_CONFIG Reply notification 1411 */ 1412 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1413 /** 1414 * Command type used for USB4 DPIA notification 1415 */ 1416 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1417 /** 1418 * Command type used for HPD redetect notification 1419 */ 1420 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1421 }; 1422 1423 /* DMUB_CMD__DPIA command sub-types. */ 1424 enum dmub_cmd_dpia_type { 1425 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1426 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1427 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1428 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1429 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1430 }; 1431 1432 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1433 enum dmub_cmd_dpia_notification_type { 1434 DPIA_NOTIFY__BW_ALLOCATION = 0, 1435 }; 1436 1437 #pragma pack(push, 1) 1438 1439 /** 1440 * struct dmub_cmd_header - Common command header fields. 1441 */ 1442 struct dmub_cmd_header { 1443 unsigned int type : 8; /**< command type */ 1444 unsigned int sub_type : 8; /**< command sub type */ 1445 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1446 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1447 unsigned int reserved0 : 6; /**< reserved bits */ 1448 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1449 unsigned int reserved1 : 2; /**< reserved bits */ 1450 }; 1451 1452 /* 1453 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1454 * 1455 * 60 payload bytes can hold up to 5 sets of read modify writes, 1456 * each take 3 dwords. 1457 * 1458 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1459 * 1460 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1461 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1462 */ 1463 struct dmub_cmd_read_modify_write_sequence { 1464 uint32_t addr; /**< register address */ 1465 uint32_t modify_mask; /**< modify mask */ 1466 uint32_t modify_value; /**< modify value */ 1467 }; 1468 1469 /** 1470 * Maximum number of ops in read modify write sequence. 1471 */ 1472 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1473 1474 /** 1475 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1476 */ 1477 struct dmub_rb_cmd_read_modify_write { 1478 struct dmub_cmd_header header; /**< command header */ 1479 /** 1480 * Read modify write sequence. 1481 */ 1482 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1483 }; 1484 1485 /* 1486 * Update a register with specified masks and values sequeunce 1487 * 1488 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1489 * 1490 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1491 * 1492 * 1493 * USE CASE: 1494 * 1. auto-increment register where additional read would update pointer and produce wrong result 1495 * 2. toggle a bit without read in the middle 1496 */ 1497 1498 struct dmub_cmd_reg_field_update_sequence { 1499 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1500 uint32_t modify_value; /**< value to update with */ 1501 }; 1502 1503 /** 1504 * Maximum number of ops in field update sequence. 1505 */ 1506 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1507 1508 /** 1509 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1510 */ 1511 struct dmub_rb_cmd_reg_field_update_sequence { 1512 struct dmub_cmd_header header; /**< command header */ 1513 uint32_t addr; /**< register address */ 1514 /** 1515 * Field update sequence. 1516 */ 1517 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1518 }; 1519 1520 1521 /** 1522 * Maximum number of burst write values. 1523 */ 1524 #define DMUB_BURST_WRITE_VALUES__MAX 14 1525 1526 /* 1527 * struct dmub_rb_cmd_burst_write - Burst write 1528 * 1529 * support use case such as writing out LUTs. 1530 * 1531 * 60 payload bytes can hold up to 14 values to write to given address 1532 * 1533 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1534 */ 1535 struct dmub_rb_cmd_burst_write { 1536 struct dmub_cmd_header header; /**< command header */ 1537 uint32_t addr; /**< register start address */ 1538 /** 1539 * Burst write register values. 1540 */ 1541 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1542 }; 1543 1544 /** 1545 * struct dmub_rb_cmd_common - Common command header 1546 */ 1547 struct dmub_rb_cmd_common { 1548 struct dmub_cmd_header header; /**< command header */ 1549 /** 1550 * Padding to RB_CMD_SIZE 1551 */ 1552 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1553 }; 1554 1555 /** 1556 * struct dmub_cmd_reg_wait_data - Register wait data 1557 */ 1558 struct dmub_cmd_reg_wait_data { 1559 uint32_t addr; /**< Register address */ 1560 uint32_t mask; /**< Mask for register bits */ 1561 uint32_t condition_field_value; /**< Value to wait for */ 1562 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1563 }; 1564 1565 /** 1566 * struct dmub_rb_cmd_reg_wait - Register wait command 1567 */ 1568 struct dmub_rb_cmd_reg_wait { 1569 struct dmub_cmd_header header; /**< Command header */ 1570 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1571 }; 1572 1573 /** 1574 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1575 * 1576 * Reprograms surface parameters to avoid underflow. 1577 */ 1578 struct dmub_cmd_PLAT_54186_wa { 1579 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1580 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1581 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1582 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1583 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1584 struct { 1585 uint32_t hubp_inst : 4; /**< HUBP instance */ 1586 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1587 uint32_t immediate :1; /**< Immediate flip */ 1588 uint32_t vmid : 4; /**< VMID */ 1589 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1590 uint32_t reserved : 21; /**< Reserved */ 1591 } flip_params; /**< Pageflip parameters */ 1592 uint32_t reserved[9]; /**< Reserved bits */ 1593 }; 1594 1595 /** 1596 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1597 */ 1598 struct dmub_rb_cmd_PLAT_54186_wa { 1599 struct dmub_cmd_header header; /**< Command header */ 1600 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1601 }; 1602 1603 /** 1604 * enum dmub_cmd_mall_type - MALL commands 1605 */ 1606 enum dmub_cmd_mall_type { 1607 /** 1608 * Allows display refresh from MALL. 1609 */ 1610 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1611 /** 1612 * Disallows display refresh from MALL. 1613 */ 1614 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1615 /** 1616 * Cursor copy for MALL. 1617 */ 1618 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1619 /** 1620 * Controls DF requests. 1621 */ 1622 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1623 }; 1624 1625 /** 1626 * struct dmub_rb_cmd_mall - MALL command data. 1627 */ 1628 struct dmub_rb_cmd_mall { 1629 struct dmub_cmd_header header; /**< Common command header */ 1630 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1631 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1632 uint32_t tmr_delay; /**< Timer delay */ 1633 uint32_t tmr_scale; /**< Timer scale */ 1634 uint16_t cursor_width; /**< Cursor width in pixels */ 1635 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1636 uint16_t cursor_height; /**< Cursor height in pixels */ 1637 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1638 uint8_t debug_bits; /**< Debug bits */ 1639 1640 uint8_t reserved1; /**< Reserved bits */ 1641 uint8_t reserved2; /**< Reserved bits */ 1642 }; 1643 1644 /** 1645 * enum dmub_cmd_cab_type - CAB command data. 1646 */ 1647 enum dmub_cmd_cab_type { 1648 /** 1649 * No idle optimizations (i.e. no CAB) 1650 */ 1651 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1652 /** 1653 * No DCN requests for memory 1654 */ 1655 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1656 /** 1657 * Fit surfaces in CAB (i.e. CAB enable) 1658 */ 1659 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1660 /** 1661 * Do not fit surfaces in CAB (i.e. no CAB) 1662 */ 1663 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1664 }; 1665 1666 /** 1667 * struct dmub_rb_cmd_cab - CAB command data. 1668 */ 1669 struct dmub_rb_cmd_cab_for_ss { 1670 struct dmub_cmd_header header; 1671 uint8_t cab_alloc_ways; /* total number of ways */ 1672 uint8_t debug_bits; /* debug bits */ 1673 }; 1674 1675 /** 1676 * Enum for indicating which MCLK switch mode per pipe 1677 */ 1678 enum mclk_switch_mode { 1679 NONE = 0, 1680 FPO = 1, 1681 SUBVP = 2, 1682 VBLANK = 3, 1683 }; 1684 1685 /* Per pipe struct which stores the MCLK switch mode 1686 * data to be sent to DMUB. 1687 * Named "v2" for now -- once FPO and SUBVP are fully merged 1688 * the type name can be updated 1689 */ 1690 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1691 union { 1692 struct { 1693 uint32_t pix_clk_100hz; 1694 uint16_t main_vblank_start; 1695 uint16_t main_vblank_end; 1696 uint16_t mall_region_lines; 1697 uint16_t prefetch_lines; 1698 uint16_t prefetch_to_mall_start_lines; 1699 uint16_t processing_delay_lines; 1700 uint16_t htotal; // required to calculate line time for multi-display cases 1701 uint16_t vtotal; 1702 uint8_t main_pipe_index; 1703 uint8_t phantom_pipe_index; 1704 /* Since the microschedule is calculated in terms of OTG lines, 1705 * include any scaling factors to make sure when we get accurate 1706 * conversion when programming MALL_START_LINE (which is in terms 1707 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1708 * is 1/2 (numerator = 1, denominator = 2). 1709 */ 1710 uint8_t scale_factor_numerator; 1711 uint8_t scale_factor_denominator; 1712 uint8_t is_drr; 1713 uint8_t main_split_pipe_index; 1714 uint8_t phantom_split_pipe_index; 1715 } subvp_data; 1716 1717 struct { 1718 uint32_t pix_clk_100hz; 1719 uint16_t vblank_start; 1720 uint16_t vblank_end; 1721 uint16_t vstartup_start; 1722 uint16_t vtotal; 1723 uint16_t htotal; 1724 uint8_t vblank_pipe_index; 1725 uint8_t padding[1]; 1726 struct { 1727 uint8_t drr_in_use; 1728 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1729 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1730 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1731 uint8_t use_ramping; // Use ramping or not 1732 uint8_t drr_vblank_start_margin; 1733 } drr_info; // DRR considered as part of SubVP + VBLANK case 1734 } vblank_data; 1735 } pipe_config; 1736 1737 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1738 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1739 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1740 */ 1741 uint8_t mode; // enum mclk_switch_mode 1742 }; 1743 1744 /** 1745 * Config data for Sub-VP and FPO 1746 * Named "v2" for now -- once FPO and SUBVP are fully merged 1747 * the type name can be updated 1748 */ 1749 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1750 uint16_t watermark_a_cache; 1751 uint8_t vertical_int_margin_us; 1752 uint8_t pstate_allow_width_us; 1753 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1754 }; 1755 1756 /** 1757 * DMUB rb command definition for Sub-VP and FPO 1758 * Named "v2" for now -- once FPO and SUBVP are fully merged 1759 * the type name can be updated 1760 */ 1761 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1762 struct dmub_cmd_header header; 1763 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1764 }; 1765 1766 struct dmub_flip_addr_info { 1767 uint32_t surf_addr_lo; 1768 uint32_t surf_addr_c_lo; 1769 uint32_t meta_addr_lo; 1770 uint32_t meta_addr_c_lo; 1771 uint16_t surf_addr_hi; 1772 uint16_t surf_addr_c_hi; 1773 uint16_t meta_addr_hi; 1774 uint16_t meta_addr_c_hi; 1775 }; 1776 1777 struct dmub_fams2_flip_info { 1778 union { 1779 struct { 1780 uint8_t is_immediate: 1; 1781 } bits; 1782 uint8_t all; 1783 } config; 1784 uint8_t otg_inst; 1785 uint8_t pipe_mask; 1786 uint8_t pad; 1787 struct dmub_flip_addr_info addr_info; 1788 }; 1789 1790 struct dmub_rb_cmd_fams2_flip { 1791 struct dmub_cmd_header header; 1792 struct dmub_fams2_flip_info flip_info; 1793 }; 1794 1795 struct dmub_optc_state_v2 { 1796 uint32_t v_total_min; 1797 uint32_t v_total_max; 1798 uint32_t v_total_mid; 1799 uint32_t v_total_mid_frame_num; 1800 uint8_t program_manual_trigger; 1801 uint8_t tg_inst; 1802 uint8_t pad[2]; 1803 }; 1804 1805 struct dmub_optc_position { 1806 uint32_t vpos; 1807 uint32_t hpos; 1808 uint32_t frame; 1809 }; 1810 1811 struct dmub_rb_cmd_fams2_drr_update { 1812 struct dmub_cmd_header header; 1813 struct dmub_optc_state_v2 dmub_optc_state_req; 1814 }; 1815 1816 /* HW and FW global configuration data for FAMS2 */ 1817 /* FAMS2 types and structs */ 1818 enum fams2_stream_type { 1819 FAMS2_STREAM_TYPE_NONE = 0, 1820 FAMS2_STREAM_TYPE_VBLANK = 1, 1821 FAMS2_STREAM_TYPE_VACTIVE = 2, 1822 FAMS2_STREAM_TYPE_DRR = 3, 1823 FAMS2_STREAM_TYPE_SUBVP = 4, 1824 }; 1825 1826 /* dynamic stream state */ 1827 struct dmub_fams2_legacy_stream_dynamic_state { 1828 uint8_t force_allow_at_vblank; 1829 uint8_t pad[3]; 1830 }; 1831 1832 struct dmub_fams2_subvp_stream_dynamic_state { 1833 uint16_t viewport_start_hubp_vline; 1834 uint16_t viewport_height_hubp_vlines; 1835 uint16_t viewport_start_c_hubp_vline; 1836 uint16_t viewport_height_c_hubp_vlines; 1837 uint16_t phantom_viewport_height_hubp_vlines; 1838 uint16_t phantom_viewport_height_c_hubp_vlines; 1839 uint16_t microschedule_start_otg_vline; 1840 uint16_t mall_start_otg_vline; 1841 uint16_t mall_start_hubp_vline; 1842 uint16_t mall_start_c_hubp_vline; 1843 uint8_t force_allow_at_vblank_only; 1844 uint8_t pad[3]; 1845 }; 1846 1847 struct dmub_fams2_drr_stream_dynamic_state { 1848 uint16_t stretched_vtotal; 1849 uint8_t use_cur_vtotal; 1850 uint8_t pad; 1851 }; 1852 1853 struct dmub_fams2_stream_dynamic_state { 1854 uint64_t ref_tick; 1855 uint32_t cur_vtotal; 1856 uint16_t adjusted_allow_end_otg_vline; 1857 uint8_t pad[2]; 1858 struct dmub_optc_position ref_otg_pos; 1859 struct dmub_optc_position target_otg_pos; 1860 union { 1861 struct dmub_fams2_legacy_stream_dynamic_state legacy; 1862 struct dmub_fams2_subvp_stream_dynamic_state subvp; 1863 struct dmub_fams2_drr_stream_dynamic_state drr; 1864 } sub_state; 1865 }; 1866 1867 /* static stream state */ 1868 struct dmub_fams2_legacy_stream_static_state { 1869 uint8_t vactive_det_fill_delay_otg_vlines; 1870 uint8_t programming_delay_otg_vlines; 1871 }; 1872 1873 struct dmub_fams2_subvp_stream_static_state { 1874 uint16_t vratio_numerator; 1875 uint16_t vratio_denominator; 1876 uint16_t phantom_vtotal; 1877 uint16_t phantom_vactive; 1878 union { 1879 struct { 1880 uint8_t is_multi_planar : 1; 1881 uint8_t is_yuv420 : 1; 1882 } bits; 1883 uint8_t all; 1884 } config; 1885 uint8_t programming_delay_otg_vlines; 1886 uint8_t prefetch_to_mall_otg_vlines; 1887 uint8_t phantom_otg_inst; 1888 uint8_t phantom_pipe_mask; 1889 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1890 }; 1891 1892 struct dmub_fams2_drr_stream_static_state { 1893 uint16_t nom_stretched_vtotal; 1894 uint8_t programming_delay_otg_vlines; 1895 uint8_t only_stretch_if_required; 1896 uint8_t pad[2]; 1897 }; 1898 1899 struct dmub_fams2_stream_static_state { 1900 enum fams2_stream_type type; 1901 uint32_t otg_vline_time_ns; 1902 uint32_t otg_vline_time_ticks; 1903 uint16_t htotal; 1904 uint16_t vtotal; // nominal vtotal 1905 uint16_t vblank_start; 1906 uint16_t vblank_end; 1907 uint16_t max_vtotal; 1908 uint16_t allow_start_otg_vline; 1909 uint16_t allow_end_otg_vline; 1910 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1911 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1912 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 1913 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1914 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1915 union { 1916 struct { 1917 uint8_t is_drr: 1; // stream is DRR enabled 1918 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 1919 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1920 } bits; 1921 uint8_t all; 1922 } config; 1923 uint8_t otg_inst; 1924 uint8_t pipe_mask; // pipe mask for the whole config 1925 uint8_t num_planes; 1926 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1927 uint8_t pad[DMUB_MAX_PLANES % 4]; 1928 union { 1929 struct dmub_fams2_legacy_stream_static_state legacy; 1930 struct dmub_fams2_subvp_stream_static_state subvp; 1931 struct dmub_fams2_drr_stream_static_state drr; 1932 } sub_state; 1933 }; 1934 1935 /** 1936 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 1937 * p-state request to allow latency 1938 */ 1939 enum dmub_fams2_allow_delay_check_mode { 1940 /* No check for request to allow delay */ 1941 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 1942 /* Check for request to allow delay */ 1943 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 1944 /* Check for prepare to allow delay */ 1945 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 1946 }; 1947 1948 union dmub_fams2_global_feature_config { 1949 struct { 1950 uint32_t enable: 1; 1951 uint32_t enable_ppt_check: 1; 1952 uint32_t enable_stall_recovery: 1; 1953 uint32_t enable_debug: 1; 1954 uint32_t enable_offload_flip: 1; 1955 uint32_t enable_visual_confirm: 1; 1956 uint32_t allow_delay_check_mode: 2; 1957 uint32_t reserved: 24; 1958 } bits; 1959 uint32_t all; 1960 }; 1961 1962 struct dmub_cmd_fams2_global_config { 1963 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 1964 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 1965 uint32_t num_streams; 1966 union dmub_fams2_global_feature_config features; 1967 uint32_t recovery_timeout_us; 1968 uint32_t hwfq_flip_programming_delay_us; 1969 }; 1970 1971 union dmub_cmd_fams2_config { 1972 struct dmub_cmd_fams2_global_config global; 1973 struct dmub_fams2_stream_static_state stream; 1974 }; 1975 1976 /** 1977 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 1978 */ 1979 struct dmub_rb_cmd_fams2 { 1980 struct dmub_cmd_header header; 1981 union dmub_cmd_fams2_config config; 1982 }; 1983 1984 /** 1985 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1986 */ 1987 enum dmub_cmd_idle_opt_type { 1988 /** 1989 * DCN hardware restore. 1990 */ 1991 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1992 1993 /** 1994 * DCN hardware save. 1995 */ 1996 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1997 1998 /** 1999 * DCN hardware notify idle. 2000 */ 2001 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2002 2003 /** 2004 * DCN hardware notify power state. 2005 */ 2006 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2007 }; 2008 2009 /** 2010 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2011 */ 2012 struct dmub_rb_cmd_idle_opt_dcn_restore { 2013 struct dmub_cmd_header header; /**< header */ 2014 }; 2015 2016 /** 2017 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2018 */ 2019 struct dmub_dcn_notify_idle_cntl_data { 2020 uint8_t driver_idle; 2021 uint8_t skip_otg_disable; 2022 uint8_t reserved[58]; 2023 }; 2024 2025 /** 2026 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2027 */ 2028 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2029 struct dmub_cmd_header header; /**< header */ 2030 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2031 }; 2032 2033 /** 2034 * enum dmub_idle_opt_dc_power_state - DC power states. 2035 */ 2036 enum dmub_idle_opt_dc_power_state { 2037 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2038 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2039 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2040 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2041 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2042 }; 2043 2044 /** 2045 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2046 */ 2047 struct dmub_idle_opt_set_dc_power_state_data { 2048 uint8_t power_state; /**< power state */ 2049 uint8_t pad[3]; /**< padding */ 2050 }; 2051 2052 /** 2053 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2054 */ 2055 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2056 struct dmub_cmd_header header; /**< header */ 2057 struct dmub_idle_opt_set_dc_power_state_data data; 2058 }; 2059 2060 /** 2061 * struct dmub_clocks - Clock update notification. 2062 */ 2063 struct dmub_clocks { 2064 uint32_t dispclk_khz; /**< dispclk kHz */ 2065 uint32_t dppclk_khz; /**< dppclk kHz */ 2066 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2067 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2068 }; 2069 2070 /** 2071 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2072 */ 2073 enum dmub_cmd_clk_mgr_type { 2074 /** 2075 * Notify DMCUB of clock update. 2076 */ 2077 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2078 }; 2079 2080 /** 2081 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2082 */ 2083 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2084 struct dmub_cmd_header header; /**< header */ 2085 struct dmub_clocks clocks; /**< clock data */ 2086 }; 2087 2088 /** 2089 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2090 */ 2091 struct dmub_cmd_digx_encoder_control_data { 2092 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2093 }; 2094 2095 /** 2096 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2097 */ 2098 struct dmub_rb_cmd_digx_encoder_control { 2099 struct dmub_cmd_header header; /**< header */ 2100 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2101 }; 2102 2103 /** 2104 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2105 */ 2106 struct dmub_cmd_set_pixel_clock_data { 2107 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2108 }; 2109 2110 /** 2111 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2112 */ 2113 struct dmub_rb_cmd_set_pixel_clock { 2114 struct dmub_cmd_header header; /**< header */ 2115 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2116 }; 2117 2118 /** 2119 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2120 */ 2121 struct dmub_cmd_enable_disp_power_gating_data { 2122 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2123 }; 2124 2125 /** 2126 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2127 */ 2128 struct dmub_rb_cmd_enable_disp_power_gating { 2129 struct dmub_cmd_header header; /**< header */ 2130 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2131 }; 2132 2133 /** 2134 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2135 */ 2136 struct dmub_dig_transmitter_control_data_v1_7 { 2137 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2138 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2139 union { 2140 uint8_t digmode; /**< enum atom_encode_mode_def */ 2141 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2142 } mode_laneset; 2143 uint8_t lanenum; /**< Number of lanes */ 2144 union { 2145 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2146 } symclk_units; 2147 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2148 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2149 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2150 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2151 uint8_t reserved1; /**< For future use */ 2152 uint8_t reserved2[3]; /**< For future use */ 2153 uint32_t reserved3[11]; /**< For future use */ 2154 }; 2155 2156 /** 2157 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2158 */ 2159 union dmub_cmd_dig1_transmitter_control_data { 2160 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2161 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2162 }; 2163 2164 /** 2165 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2166 */ 2167 struct dmub_rb_cmd_dig1_transmitter_control { 2168 struct dmub_cmd_header header; /**< header */ 2169 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2170 }; 2171 2172 /** 2173 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2174 */ 2175 struct dmub_rb_cmd_domain_control_data { 2176 uint8_t inst : 6; /**< DOMAIN instance to control */ 2177 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2178 uint8_t reserved[3]; /**< Reserved for future use */ 2179 }; 2180 2181 /** 2182 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2183 */ 2184 struct dmub_rb_cmd_domain_control { 2185 struct dmub_cmd_header header; /**< header */ 2186 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2187 }; 2188 2189 /** 2190 * DPIA tunnel command parameters. 2191 */ 2192 struct dmub_cmd_dig_dpia_control_data { 2193 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2194 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2195 union { 2196 uint8_t digmode; /** enum atom_encode_mode_def */ 2197 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2198 } mode_laneset; 2199 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2200 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2201 uint8_t hpdsel; /** =0: HPD is not assigned */ 2202 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2203 uint8_t dpia_id; /** Index of DPIA */ 2204 uint8_t fec_rdy : 1; 2205 uint8_t reserved : 7; 2206 uint32_t reserved1; 2207 }; 2208 2209 /** 2210 * DMUB command for DPIA tunnel control. 2211 */ 2212 struct dmub_rb_cmd_dig1_dpia_control { 2213 struct dmub_cmd_header header; 2214 struct dmub_cmd_dig_dpia_control_data dpia_control; 2215 }; 2216 2217 /** 2218 * SET_CONFIG Command Payload (deprecated) 2219 */ 2220 struct set_config_cmd_payload { 2221 uint8_t msg_type; /* set config message type */ 2222 uint8_t msg_data; /* set config message data */ 2223 }; 2224 2225 /** 2226 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2227 */ 2228 struct dmub_cmd_set_config_control_data { 2229 struct set_config_cmd_payload cmd_pkt; 2230 uint8_t instance; /* DPIA instance */ 2231 uint8_t immed_status; /* Immediate status returned in case of error */ 2232 }; 2233 2234 /** 2235 * SET_CONFIG Request Command Payload 2236 */ 2237 struct set_config_request_cmd_payload { 2238 uint8_t instance; /* DPIA instance */ 2239 uint8_t immed_status; /* Immediate status returned in case of error */ 2240 uint8_t msg_type; /* set config message type */ 2241 uint8_t reserved; 2242 uint32_t msg_data; /* set config message data */ 2243 }; 2244 2245 /** 2246 * DMUB command structure for SET_CONFIG command. 2247 */ 2248 struct dmub_rb_cmd_set_config_access { 2249 struct dmub_cmd_header header; /* header */ 2250 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2251 }; 2252 2253 /** 2254 * DMUB command structure for SET_CONFIG request command. 2255 */ 2256 struct dmub_rb_cmd_set_config_request { 2257 struct dmub_cmd_header header; /* header */ 2258 struct set_config_request_cmd_payload payload; /* set config request payload */ 2259 }; 2260 2261 /** 2262 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2263 */ 2264 struct dmub_cmd_mst_alloc_slots_control_data { 2265 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2266 uint8_t instance; /* DPIA instance */ 2267 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2268 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2269 }; 2270 2271 /** 2272 * DMUB command structure for SET_ command. 2273 */ 2274 struct dmub_rb_cmd_set_mst_alloc_slots { 2275 struct dmub_cmd_header header; /* header */ 2276 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2277 }; 2278 2279 /** 2280 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2281 */ 2282 struct dmub_cmd_tps_notification_data { 2283 uint8_t instance; /* DPIA instance */ 2284 uint8_t tps; /* requested training pattern */ 2285 uint8_t reserved1; 2286 uint8_t reserved2; 2287 }; 2288 2289 /** 2290 * DMUB command structure for SET_TPS_NOTIFICATION command. 2291 */ 2292 struct dmub_rb_cmd_set_tps_notification { 2293 struct dmub_cmd_header header; /* header */ 2294 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2295 }; 2296 2297 /** 2298 * DMUB command structure for DPIA HPD int enable control. 2299 */ 2300 struct dmub_rb_cmd_dpia_hpd_int_enable { 2301 struct dmub_cmd_header header; /* header */ 2302 uint32_t enable; /* dpia hpd interrupt enable */ 2303 }; 2304 2305 /** 2306 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2307 */ 2308 struct dmub_rb_cmd_dpphy_init { 2309 struct dmub_cmd_header header; /**< header */ 2310 uint8_t reserved[60]; /**< reserved bits */ 2311 }; 2312 2313 /** 2314 * enum dp_aux_request_action - DP AUX request command listing. 2315 * 2316 * 4 AUX request command bits are shifted to high nibble. 2317 */ 2318 enum dp_aux_request_action { 2319 /** I2C-over-AUX write request */ 2320 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2321 /** I2C-over-AUX read request */ 2322 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2323 /** I2C-over-AUX write status request */ 2324 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2325 /** I2C-over-AUX write request with MOT=1 */ 2326 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2327 /** I2C-over-AUX read request with MOT=1 */ 2328 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2329 /** I2C-over-AUX write status request with MOT=1 */ 2330 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2331 /** Native AUX write request */ 2332 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2333 /** Native AUX read request */ 2334 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2335 }; 2336 2337 /** 2338 * enum aux_return_code_type - DP AUX process return code listing. 2339 */ 2340 enum aux_return_code_type { 2341 /** AUX process succeeded */ 2342 AUX_RET_SUCCESS = 0, 2343 /** AUX process failed with unknown reason */ 2344 AUX_RET_ERROR_UNKNOWN, 2345 /** AUX process completed with invalid reply */ 2346 AUX_RET_ERROR_INVALID_REPLY, 2347 /** AUX process timed out */ 2348 AUX_RET_ERROR_TIMEOUT, 2349 /** HPD was low during AUX process */ 2350 AUX_RET_ERROR_HPD_DISCON, 2351 /** Failed to acquire AUX engine */ 2352 AUX_RET_ERROR_ENGINE_ACQUIRE, 2353 /** AUX request not supported */ 2354 AUX_RET_ERROR_INVALID_OPERATION, 2355 /** AUX process not available */ 2356 AUX_RET_ERROR_PROTOCOL_ERROR, 2357 }; 2358 2359 /** 2360 * enum aux_channel_type - DP AUX channel type listing. 2361 */ 2362 enum aux_channel_type { 2363 /** AUX thru Legacy DP AUX */ 2364 AUX_CHANNEL_LEGACY_DDC, 2365 /** AUX thru DPIA DP tunneling */ 2366 AUX_CHANNEL_DPIA 2367 }; 2368 2369 /** 2370 * struct aux_transaction_parameters - DP AUX request transaction data 2371 */ 2372 struct aux_transaction_parameters { 2373 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2374 uint8_t action; /**< enum dp_aux_request_action */ 2375 uint8_t length; /**< DP AUX request data length */ 2376 uint8_t reserved; /**< For future use */ 2377 uint32_t address; /**< DP AUX address */ 2378 uint8_t data[16]; /**< DP AUX write data */ 2379 }; 2380 2381 /** 2382 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2383 */ 2384 struct dmub_cmd_dp_aux_control_data { 2385 uint8_t instance; /**< AUX instance or DPIA instance */ 2386 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2387 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2388 uint8_t reserved0; /**< For future use */ 2389 uint16_t timeout; /**< timeout time in us */ 2390 uint16_t reserved1; /**< For future use */ 2391 enum aux_channel_type type; /**< enum aux_channel_type */ 2392 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2393 }; 2394 2395 /** 2396 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2397 */ 2398 struct dmub_rb_cmd_dp_aux_access { 2399 /** 2400 * Command header. 2401 */ 2402 struct dmub_cmd_header header; 2403 /** 2404 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2405 */ 2406 struct dmub_cmd_dp_aux_control_data aux_control; 2407 }; 2408 2409 /** 2410 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2411 */ 2412 struct dmub_rb_cmd_outbox1_enable { 2413 /** 2414 * Command header. 2415 */ 2416 struct dmub_cmd_header header; 2417 /** 2418 * enable: 0x0 -> disable outbox1 notification (default value) 2419 * 0x1 -> enable outbox1 notification 2420 */ 2421 uint32_t enable; 2422 }; 2423 2424 /* DP AUX Reply command - OutBox Cmd */ 2425 /** 2426 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2427 */ 2428 struct aux_reply_data { 2429 /** 2430 * Aux cmd 2431 */ 2432 uint8_t command; 2433 /** 2434 * Aux reply data length (max: 16 bytes) 2435 */ 2436 uint8_t length; 2437 /** 2438 * Alignment only 2439 */ 2440 uint8_t pad[2]; 2441 /** 2442 * Aux reply data 2443 */ 2444 uint8_t data[16]; 2445 }; 2446 2447 /** 2448 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2449 */ 2450 struct aux_reply_control_data { 2451 /** 2452 * Reserved for future use 2453 */ 2454 uint32_t handle; 2455 /** 2456 * Aux Instance 2457 */ 2458 uint8_t instance; 2459 /** 2460 * Aux transaction result: definition in enum aux_return_code_type 2461 */ 2462 uint8_t result; 2463 /** 2464 * Alignment only 2465 */ 2466 uint16_t pad; 2467 }; 2468 2469 /** 2470 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2471 */ 2472 struct dmub_rb_cmd_dp_aux_reply { 2473 /** 2474 * Command header. 2475 */ 2476 struct dmub_cmd_header header; 2477 /** 2478 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2479 */ 2480 struct aux_reply_control_data control; 2481 /** 2482 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2483 */ 2484 struct aux_reply_data reply_data; 2485 }; 2486 2487 /* DP HPD Notify command - OutBox Cmd */ 2488 /** 2489 * DP HPD Type 2490 */ 2491 enum dp_hpd_type { 2492 /** 2493 * Normal DP HPD 2494 */ 2495 DP_HPD = 0, 2496 /** 2497 * DP HPD short pulse 2498 */ 2499 DP_IRQ 2500 }; 2501 2502 /** 2503 * DP HPD Status 2504 */ 2505 enum dp_hpd_status { 2506 /** 2507 * DP_HPD status low 2508 */ 2509 DP_HPD_UNPLUG = 0, 2510 /** 2511 * DP_HPD status high 2512 */ 2513 DP_HPD_PLUG 2514 }; 2515 2516 /** 2517 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2518 */ 2519 struct dp_hpd_data { 2520 /** 2521 * DP HPD instance 2522 */ 2523 uint8_t instance; 2524 /** 2525 * HPD type 2526 */ 2527 uint8_t hpd_type; 2528 /** 2529 * HPD status: only for type: DP_HPD to indicate status 2530 */ 2531 uint8_t hpd_status; 2532 /** 2533 * Alignment only 2534 */ 2535 uint8_t pad; 2536 }; 2537 2538 /** 2539 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2540 */ 2541 struct dmub_rb_cmd_dp_hpd_notify { 2542 /** 2543 * Command header. 2544 */ 2545 struct dmub_cmd_header header; 2546 /** 2547 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2548 */ 2549 struct dp_hpd_data hpd_data; 2550 }; 2551 2552 /** 2553 * Definition of a SET_CONFIG reply from DPOA. 2554 */ 2555 enum set_config_status { 2556 SET_CONFIG_PENDING = 0, 2557 SET_CONFIG_ACK_RECEIVED, 2558 SET_CONFIG_RX_TIMEOUT, 2559 SET_CONFIG_UNKNOWN_ERROR, 2560 }; 2561 2562 /** 2563 * Definition of a set_config reply 2564 */ 2565 struct set_config_reply_control_data { 2566 uint8_t instance; /* DPIA Instance */ 2567 uint8_t status; /* Set Config reply */ 2568 uint16_t pad; /* Alignment */ 2569 }; 2570 2571 /** 2572 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2573 */ 2574 struct dmub_rb_cmd_dp_set_config_reply { 2575 struct dmub_cmd_header header; 2576 struct set_config_reply_control_data set_config_reply_control; 2577 }; 2578 2579 /** 2580 * Definition of a DPIA notification header 2581 */ 2582 struct dpia_notification_header { 2583 uint8_t instance; /**< DPIA Instance */ 2584 uint8_t reserved[3]; 2585 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2586 }; 2587 2588 /** 2589 * Definition of the common data struct of DPIA notification 2590 */ 2591 struct dpia_notification_common { 2592 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2593 - sizeof(struct dpia_notification_header)]; 2594 }; 2595 2596 /** 2597 * Definition of a DPIA notification data 2598 */ 2599 struct dpia_bw_allocation_notify_data { 2600 union { 2601 struct { 2602 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2603 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2604 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2605 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2606 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2607 uint16_t reserved: 11; /**< Reserved */ 2608 } bits; 2609 2610 uint16_t flags; 2611 }; 2612 2613 uint8_t cm_id; /**< CM ID */ 2614 uint8_t group_id; /**< Group ID */ 2615 uint8_t granularity; /**< BW Allocation Granularity */ 2616 uint8_t estimated_bw; /**< Estimated_BW */ 2617 uint8_t allocated_bw; /**< Allocated_BW */ 2618 uint8_t reserved; 2619 }; 2620 2621 /** 2622 * union dpia_notify_data_type - DPIA Notification in Outbox command 2623 */ 2624 union dpia_notification_data { 2625 /** 2626 * DPIA Notification for common data struct 2627 */ 2628 struct dpia_notification_common common_data; 2629 2630 /** 2631 * DPIA Notification for DP BW Allocation support 2632 */ 2633 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2634 }; 2635 2636 /** 2637 * Definition of a DPIA notification payload 2638 */ 2639 struct dpia_notification_payload { 2640 struct dpia_notification_header header; 2641 union dpia_notification_data data; /**< DPIA notification payload data */ 2642 }; 2643 2644 /** 2645 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2646 */ 2647 struct dmub_rb_cmd_dpia_notification { 2648 struct dmub_cmd_header header; /**< DPIA notification header */ 2649 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2650 }; 2651 2652 /** 2653 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2654 */ 2655 struct dmub_cmd_hpd_state_query_data { 2656 uint8_t instance; /**< HPD instance or DPIA instance */ 2657 uint8_t result; /**< For returning HPD state */ 2658 uint16_t pad; /** < Alignment */ 2659 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2660 enum aux_return_code_type status; /**< for returning the status of command */ 2661 }; 2662 2663 /** 2664 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2665 */ 2666 struct dmub_rb_cmd_query_hpd_state { 2667 /** 2668 * Command header. 2669 */ 2670 struct dmub_cmd_header header; 2671 /** 2672 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2673 */ 2674 struct dmub_cmd_hpd_state_query_data data; 2675 }; 2676 2677 /** 2678 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2679 */ 2680 struct dmub_rb_cmd_hpd_sense_notify_data { 2681 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2682 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2683 }; 2684 2685 /** 2686 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2687 */ 2688 struct dmub_rb_cmd_hpd_sense_notify { 2689 struct dmub_cmd_header header; /**< header */ 2690 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2691 }; 2692 2693 /* 2694 * Command IDs should be treated as stable ABI. 2695 * Do not reuse or modify IDs. 2696 */ 2697 2698 /** 2699 * PSR command sub-types. 2700 */ 2701 enum dmub_cmd_psr_type { 2702 /** 2703 * Set PSR version support. 2704 */ 2705 DMUB_CMD__PSR_SET_VERSION = 0, 2706 /** 2707 * Copy driver-calculated parameters to PSR state. 2708 */ 2709 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2710 /** 2711 * Enable PSR. 2712 */ 2713 DMUB_CMD__PSR_ENABLE = 2, 2714 2715 /** 2716 * Disable PSR. 2717 */ 2718 DMUB_CMD__PSR_DISABLE = 3, 2719 2720 /** 2721 * Set PSR level. 2722 * PSR level is a 16-bit value dicated by driver that 2723 * will enable/disable different functionality. 2724 */ 2725 DMUB_CMD__PSR_SET_LEVEL = 4, 2726 2727 /** 2728 * Forces PSR enabled until an explicit PSR disable call. 2729 */ 2730 DMUB_CMD__PSR_FORCE_STATIC = 5, 2731 /** 2732 * Set vtotal in psr active for FreeSync PSR. 2733 */ 2734 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2735 /** 2736 * Set PSR power option 2737 */ 2738 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2739 }; 2740 2741 /** 2742 * Different PSR residency modes. 2743 * Different modes change the definition of PSR residency. 2744 */ 2745 enum psr_residency_mode { 2746 PSR_RESIDENCY_MODE_PHY = 0, 2747 PSR_RESIDENCY_MODE_ALPM, 2748 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2749 /* Do not add below. */ 2750 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2751 }; 2752 2753 enum dmub_cmd_fams_type { 2754 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2755 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2756 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2757 /** 2758 * For SubVP set manual trigger in FW because it 2759 * triggers DRR_UPDATE_PENDING which SubVP relies 2760 * on (for any SubVP cases that use a DRR display) 2761 */ 2762 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2763 DMUB_CMD__FAMS2_CONFIG = 4, 2764 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2765 DMUB_CMD__FAMS2_FLIP = 6, 2766 }; 2767 2768 /** 2769 * PSR versions. 2770 */ 2771 enum psr_version { 2772 /** 2773 * PSR version 1. 2774 */ 2775 PSR_VERSION_1 = 0, 2776 /** 2777 * Freesync PSR SU. 2778 */ 2779 PSR_VERSION_SU_1 = 1, 2780 /** 2781 * PSR not supported. 2782 */ 2783 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2784 }; 2785 2786 /** 2787 * PHY Link rate for DP. 2788 */ 2789 enum phy_link_rate { 2790 /** 2791 * not supported. 2792 */ 2793 PHY_RATE_UNKNOWN = 0, 2794 /** 2795 * Rate_1 (RBR) - 1.62 Gbps/Lane 2796 */ 2797 PHY_RATE_162 = 1, 2798 /** 2799 * Rate_2 - 2.16 Gbps/Lane 2800 */ 2801 PHY_RATE_216 = 2, 2802 /** 2803 * Rate_3 - 2.43 Gbps/Lane 2804 */ 2805 PHY_RATE_243 = 3, 2806 /** 2807 * Rate_4 (HBR) - 2.70 Gbps/Lane 2808 */ 2809 PHY_RATE_270 = 4, 2810 /** 2811 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2812 */ 2813 PHY_RATE_324 = 5, 2814 /** 2815 * Rate_6 - 4.32 Gbps/Lane 2816 */ 2817 PHY_RATE_432 = 6, 2818 /** 2819 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2820 */ 2821 PHY_RATE_540 = 7, 2822 /** 2823 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2824 */ 2825 PHY_RATE_810 = 8, 2826 /** 2827 * UHBR10 - 10.0 Gbps/Lane 2828 */ 2829 PHY_RATE_1000 = 9, 2830 /** 2831 * UHBR13.5 - 13.5 Gbps/Lane 2832 */ 2833 PHY_RATE_1350 = 10, 2834 /** 2835 * UHBR10 - 20.0 Gbps/Lane 2836 */ 2837 PHY_RATE_2000 = 11, 2838 2839 PHY_RATE_675 = 12, 2840 /** 2841 * Rate 12 - 6.75 Gbps/Lane 2842 */ 2843 }; 2844 2845 /** 2846 * enum dmub_phy_fsm_state - PHY FSM states. 2847 * PHY FSM state to transit to during PSR enable/disable. 2848 */ 2849 enum dmub_phy_fsm_state { 2850 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2851 DMUB_PHY_FSM_RESET, 2852 DMUB_PHY_FSM_RESET_RELEASED, 2853 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2854 DMUB_PHY_FSM_INITIALIZED, 2855 DMUB_PHY_FSM_CALIBRATED, 2856 DMUB_PHY_FSM_CALIBRATED_LP, 2857 DMUB_PHY_FSM_CALIBRATED_PG, 2858 DMUB_PHY_FSM_POWER_DOWN, 2859 DMUB_PHY_FSM_PLL_EN, 2860 DMUB_PHY_FSM_TX_EN, 2861 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2862 DMUB_PHY_FSM_FAST_LP, 2863 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2864 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2865 DMUB_PHY_FSM_P2_PLL_OFF, 2866 DMUB_PHY_FSM_P2_PLL_ON, 2867 }; 2868 2869 /** 2870 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2871 */ 2872 struct dmub_cmd_psr_copy_settings_data { 2873 /** 2874 * Flags that can be set by driver to change some PSR behaviour. 2875 */ 2876 union dmub_psr_debug_flags debug; 2877 /** 2878 * 16-bit value dicated by driver that will enable/disable different functionality. 2879 */ 2880 uint16_t psr_level; 2881 /** 2882 * DPP HW instance. 2883 */ 2884 uint8_t dpp_inst; 2885 /** 2886 * MPCC HW instance. 2887 * Not used in dmub fw, 2888 * dmub fw will get active opp by reading odm registers. 2889 */ 2890 uint8_t mpcc_inst; 2891 /** 2892 * OPP HW instance. 2893 * Not used in dmub fw, 2894 * dmub fw will get active opp by reading odm registers. 2895 */ 2896 uint8_t opp_inst; 2897 /** 2898 * OTG HW instance. 2899 */ 2900 uint8_t otg_inst; 2901 /** 2902 * DIG FE HW instance. 2903 */ 2904 uint8_t digfe_inst; 2905 /** 2906 * DIG BE HW instance. 2907 */ 2908 uint8_t digbe_inst; 2909 /** 2910 * DP PHY HW instance. 2911 */ 2912 uint8_t dpphy_inst; 2913 /** 2914 * AUX HW instance. 2915 */ 2916 uint8_t aux_inst; 2917 /** 2918 * Determines if SMU optimzations are enabled/disabled. 2919 */ 2920 uint8_t smu_optimizations_en; 2921 /** 2922 * Unused. 2923 * TODO: Remove. 2924 */ 2925 uint8_t frame_delay; 2926 /** 2927 * If RFB setup time is greater than the total VBLANK time, 2928 * it is not possible for the sink to capture the video frame 2929 * in the same frame the SDP is sent. In this case, 2930 * the frame capture indication bit should be set and an extra 2931 * static frame should be transmitted to the sink. 2932 */ 2933 uint8_t frame_cap_ind; 2934 /** 2935 * Granularity of Y offset supported by sink. 2936 */ 2937 uint8_t su_y_granularity; 2938 /** 2939 * Indicates whether sink should start capturing 2940 * immediately following active scan line, 2941 * or starting with the 2nd active scan line. 2942 */ 2943 uint8_t line_capture_indication; 2944 /** 2945 * Multi-display optimizations are implemented on certain ASICs. 2946 */ 2947 uint8_t multi_disp_optimizations_en; 2948 /** 2949 * The last possible line SDP may be transmitted without violating 2950 * the RFB setup time or entering the active video frame. 2951 */ 2952 uint16_t init_sdp_deadline; 2953 /** 2954 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2955 */ 2956 uint8_t rate_control_caps ; 2957 /* 2958 * Force PSRSU always doing full frame update 2959 */ 2960 uint8_t force_ffu_mode; 2961 /** 2962 * Length of each horizontal line in us. 2963 */ 2964 uint32_t line_time_in_us; 2965 /** 2966 * FEC enable status in driver 2967 */ 2968 uint8_t fec_enable_status; 2969 /** 2970 * FEC re-enable delay when PSR exit. 2971 * unit is 100us, range form 0~255(0xFF). 2972 */ 2973 uint8_t fec_enable_delay_in100us; 2974 /** 2975 * PSR control version. 2976 */ 2977 uint8_t cmd_version; 2978 /** 2979 * Panel Instance. 2980 * Panel instance to identify which psr_state to use 2981 * Currently the support is only for 0 or 1 2982 */ 2983 uint8_t panel_inst; 2984 /* 2985 * DSC enable status in driver 2986 */ 2987 uint8_t dsc_enable_status; 2988 /* 2989 * Use FSM state for PSR power up/down 2990 */ 2991 uint8_t use_phy_fsm; 2992 /** 2993 * frame delay for frame re-lock 2994 */ 2995 uint8_t relock_delay_frame_cnt; 2996 /** 2997 * esd recovery indicate. 2998 */ 2999 uint8_t esd_recovery; 3000 /** 3001 * DSC Slice height. 3002 */ 3003 uint16_t dsc_slice_height; 3004 /** 3005 * Some panels request main link off before xth vertical line 3006 */ 3007 uint16_t poweroff_before_vertical_line; 3008 }; 3009 3010 /** 3011 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3012 */ 3013 struct dmub_rb_cmd_psr_copy_settings { 3014 /** 3015 * Command header. 3016 */ 3017 struct dmub_cmd_header header; 3018 /** 3019 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3020 */ 3021 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3022 }; 3023 3024 /** 3025 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3026 */ 3027 struct dmub_cmd_psr_set_level_data { 3028 /** 3029 * 16-bit value dicated by driver that will enable/disable different functionality. 3030 */ 3031 uint16_t psr_level; 3032 /** 3033 * PSR control version. 3034 */ 3035 uint8_t cmd_version; 3036 /** 3037 * Panel Instance. 3038 * Panel instance to identify which psr_state to use 3039 * Currently the support is only for 0 or 1 3040 */ 3041 uint8_t panel_inst; 3042 }; 3043 3044 /** 3045 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3046 */ 3047 struct dmub_rb_cmd_psr_set_level { 3048 /** 3049 * Command header. 3050 */ 3051 struct dmub_cmd_header header; 3052 /** 3053 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3054 */ 3055 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3056 }; 3057 3058 struct dmub_rb_cmd_psr_enable_data { 3059 /** 3060 * PSR control version. 3061 */ 3062 uint8_t cmd_version; 3063 /** 3064 * Panel Instance. 3065 * Panel instance to identify which psr_state to use 3066 * Currently the support is only for 0 or 1 3067 */ 3068 uint8_t panel_inst; 3069 /** 3070 * Phy state to enter. 3071 * Values to use are defined in dmub_phy_fsm_state 3072 */ 3073 uint8_t phy_fsm_state; 3074 /** 3075 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3076 * Set this using enum phy_link_rate. 3077 * This does not support HDMI/DP2 for now. 3078 */ 3079 uint8_t phy_rate; 3080 }; 3081 3082 /** 3083 * Definition of a DMUB_CMD__PSR_ENABLE command. 3084 * PSR enable/disable is controlled using the sub_type. 3085 */ 3086 struct dmub_rb_cmd_psr_enable { 3087 /** 3088 * Command header. 3089 */ 3090 struct dmub_cmd_header header; 3091 3092 struct dmub_rb_cmd_psr_enable_data data; 3093 }; 3094 3095 /** 3096 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3097 */ 3098 struct dmub_cmd_psr_set_version_data { 3099 /** 3100 * PSR version that FW should implement. 3101 */ 3102 enum psr_version version; 3103 /** 3104 * PSR control version. 3105 */ 3106 uint8_t cmd_version; 3107 /** 3108 * Panel Instance. 3109 * Panel instance to identify which psr_state to use 3110 * Currently the support is only for 0 or 1 3111 */ 3112 uint8_t panel_inst; 3113 /** 3114 * Explicit padding to 4 byte boundary. 3115 */ 3116 uint8_t pad[2]; 3117 }; 3118 3119 /** 3120 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3121 */ 3122 struct dmub_rb_cmd_psr_set_version { 3123 /** 3124 * Command header. 3125 */ 3126 struct dmub_cmd_header header; 3127 /** 3128 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3129 */ 3130 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3131 }; 3132 3133 struct dmub_cmd_psr_force_static_data { 3134 /** 3135 * PSR control version. 3136 */ 3137 uint8_t cmd_version; 3138 /** 3139 * Panel Instance. 3140 * Panel instance to identify which psr_state to use 3141 * Currently the support is only for 0 or 1 3142 */ 3143 uint8_t panel_inst; 3144 /** 3145 * Explicit padding to 4 byte boundary. 3146 */ 3147 uint8_t pad[2]; 3148 }; 3149 3150 /** 3151 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3152 */ 3153 struct dmub_rb_cmd_psr_force_static { 3154 /** 3155 * Command header. 3156 */ 3157 struct dmub_cmd_header header; 3158 /** 3159 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3160 */ 3161 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3162 }; 3163 3164 /** 3165 * PSR SU debug flags. 3166 */ 3167 union dmub_psr_su_debug_flags { 3168 /** 3169 * PSR SU debug flags. 3170 */ 3171 struct { 3172 /** 3173 * Update dirty rect in SW only. 3174 */ 3175 uint8_t update_dirty_rect_only : 1; 3176 /** 3177 * Reset the cursor/plane state before processing the call. 3178 */ 3179 uint8_t reset_state : 1; 3180 } bitfields; 3181 3182 /** 3183 * Union for debug flags. 3184 */ 3185 uint32_t u32All; 3186 }; 3187 3188 /** 3189 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3190 * This triggers a selective update for PSR SU. 3191 */ 3192 struct dmub_cmd_update_dirty_rect_data { 3193 /** 3194 * Dirty rects from OS. 3195 */ 3196 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3197 /** 3198 * PSR SU debug flags. 3199 */ 3200 union dmub_psr_su_debug_flags debug_flags; 3201 /** 3202 * OTG HW instance. 3203 */ 3204 uint8_t pipe_idx; 3205 /** 3206 * Number of dirty rects. 3207 */ 3208 uint8_t dirty_rect_count; 3209 /** 3210 * PSR control version. 3211 */ 3212 uint8_t cmd_version; 3213 /** 3214 * Panel Instance. 3215 * Panel instance to identify which psr_state to use 3216 * Currently the support is only for 0 or 1 3217 */ 3218 uint8_t panel_inst; 3219 }; 3220 3221 /** 3222 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3223 */ 3224 struct dmub_rb_cmd_update_dirty_rect { 3225 /** 3226 * Command header. 3227 */ 3228 struct dmub_cmd_header header; 3229 /** 3230 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3231 */ 3232 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3233 }; 3234 3235 /** 3236 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3237 */ 3238 union dmub_reg_cursor_control_cfg { 3239 struct { 3240 uint32_t cur_enable: 1; 3241 uint32_t reser0: 3; 3242 uint32_t cur_2x_magnify: 1; 3243 uint32_t reser1: 3; 3244 uint32_t mode: 3; 3245 uint32_t reser2: 5; 3246 uint32_t pitch: 2; 3247 uint32_t reser3: 6; 3248 uint32_t line_per_chunk: 5; 3249 uint32_t reser4: 3; 3250 } bits; 3251 uint32_t raw; 3252 }; 3253 struct dmub_cursor_position_cache_hubp { 3254 union dmub_reg_cursor_control_cfg cur_ctl; 3255 union dmub_reg_position_cfg { 3256 struct { 3257 uint32_t cur_x_pos: 16; 3258 uint32_t cur_y_pos: 16; 3259 } bits; 3260 uint32_t raw; 3261 } position; 3262 union dmub_reg_hot_spot_cfg { 3263 struct { 3264 uint32_t hot_x: 16; 3265 uint32_t hot_y: 16; 3266 } bits; 3267 uint32_t raw; 3268 } hot_spot; 3269 union dmub_reg_dst_offset_cfg { 3270 struct { 3271 uint32_t dst_x_offset: 13; 3272 uint32_t reserved: 19; 3273 } bits; 3274 uint32_t raw; 3275 } dst_offset; 3276 }; 3277 3278 union dmub_reg_cur0_control_cfg { 3279 struct { 3280 uint32_t cur0_enable: 1; 3281 uint32_t expansion_mode: 1; 3282 uint32_t reser0: 1; 3283 uint32_t cur0_rom_en: 1; 3284 uint32_t mode: 3; 3285 uint32_t reserved: 25; 3286 } bits; 3287 uint32_t raw; 3288 }; 3289 struct dmub_cursor_position_cache_dpp { 3290 union dmub_reg_cur0_control_cfg cur0_ctl; 3291 }; 3292 struct dmub_cursor_position_cfg { 3293 struct dmub_cursor_position_cache_hubp pHubp; 3294 struct dmub_cursor_position_cache_dpp pDpp; 3295 uint8_t pipe_idx; 3296 /* 3297 * Padding is required. To be 4 Bytes Aligned. 3298 */ 3299 uint8_t padding[3]; 3300 }; 3301 3302 struct dmub_cursor_attribute_cache_hubp { 3303 uint32_t SURFACE_ADDR_HIGH; 3304 uint32_t SURFACE_ADDR; 3305 union dmub_reg_cursor_control_cfg cur_ctl; 3306 union dmub_reg_cursor_size_cfg { 3307 struct { 3308 uint32_t width: 16; 3309 uint32_t height: 16; 3310 } bits; 3311 uint32_t raw; 3312 } size; 3313 union dmub_reg_cursor_settings_cfg { 3314 struct { 3315 uint32_t dst_y_offset: 8; 3316 uint32_t chunk_hdl_adjust: 2; 3317 uint32_t reserved: 22; 3318 } bits; 3319 uint32_t raw; 3320 } settings; 3321 }; 3322 struct dmub_cursor_attribute_cache_dpp { 3323 union dmub_reg_cur0_control_cfg cur0_ctl; 3324 }; 3325 struct dmub_cursor_attributes_cfg { 3326 struct dmub_cursor_attribute_cache_hubp aHubp; 3327 struct dmub_cursor_attribute_cache_dpp aDpp; 3328 }; 3329 3330 struct dmub_cmd_update_cursor_payload0 { 3331 /** 3332 * Cursor dirty rects. 3333 */ 3334 struct dmub_rect cursor_rect; 3335 /** 3336 * PSR SU debug flags. 3337 */ 3338 union dmub_psr_su_debug_flags debug_flags; 3339 /** 3340 * Cursor enable/disable. 3341 */ 3342 uint8_t enable; 3343 /** 3344 * OTG HW instance. 3345 */ 3346 uint8_t pipe_idx; 3347 /** 3348 * PSR control version. 3349 */ 3350 uint8_t cmd_version; 3351 /** 3352 * Panel Instance. 3353 * Panel instance to identify which psr_state to use 3354 * Currently the support is only for 0 or 1 3355 */ 3356 uint8_t panel_inst; 3357 /** 3358 * Cursor Position Register. 3359 * Registers contains Hubp & Dpp modules 3360 */ 3361 struct dmub_cursor_position_cfg position_cfg; 3362 }; 3363 3364 struct dmub_cmd_update_cursor_payload1 { 3365 struct dmub_cursor_attributes_cfg attribute_cfg; 3366 }; 3367 3368 union dmub_cmd_update_cursor_info_data { 3369 struct dmub_cmd_update_cursor_payload0 payload0; 3370 struct dmub_cmd_update_cursor_payload1 payload1; 3371 }; 3372 /** 3373 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3374 */ 3375 struct dmub_rb_cmd_update_cursor_info { 3376 /** 3377 * Command header. 3378 */ 3379 struct dmub_cmd_header header; 3380 /** 3381 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3382 */ 3383 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3384 }; 3385 3386 /** 3387 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3388 */ 3389 struct dmub_cmd_psr_set_vtotal_data { 3390 /** 3391 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3392 */ 3393 uint16_t psr_vtotal_idle; 3394 /** 3395 * PSR control version. 3396 */ 3397 uint8_t cmd_version; 3398 /** 3399 * Panel Instance. 3400 * Panel instance to identify which psr_state to use 3401 * Currently the support is only for 0 or 1 3402 */ 3403 uint8_t panel_inst; 3404 /* 3405 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3406 */ 3407 uint16_t psr_vtotal_su; 3408 /** 3409 * Explicit padding to 4 byte boundary. 3410 */ 3411 uint8_t pad2[2]; 3412 }; 3413 3414 /** 3415 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3416 */ 3417 struct dmub_rb_cmd_psr_set_vtotal { 3418 /** 3419 * Command header. 3420 */ 3421 struct dmub_cmd_header header; 3422 /** 3423 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3424 */ 3425 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3426 }; 3427 3428 /** 3429 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3430 */ 3431 struct dmub_cmd_psr_set_power_opt_data { 3432 /** 3433 * PSR control version. 3434 */ 3435 uint8_t cmd_version; 3436 /** 3437 * Panel Instance. 3438 * Panel instance to identify which psr_state to use 3439 * Currently the support is only for 0 or 1 3440 */ 3441 uint8_t panel_inst; 3442 /** 3443 * Explicit padding to 4 byte boundary. 3444 */ 3445 uint8_t pad[2]; 3446 /** 3447 * PSR power option 3448 */ 3449 uint32_t power_opt; 3450 }; 3451 3452 /** 3453 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3454 */ 3455 struct dmub_rb_cmd_psr_set_power_opt { 3456 /** 3457 * Command header. 3458 */ 3459 struct dmub_cmd_header header; 3460 /** 3461 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3462 */ 3463 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3464 }; 3465 3466 /** 3467 * Definition of Replay Residency GPINT command. 3468 * Bit[0] - Residency mode for Revision 0 3469 * Bit[1] - Enable/Disable state 3470 * Bit[2-3] - Revision number 3471 * Bit[4-7] - Residency mode for Revision 1 3472 * Bit[8] - Panel instance 3473 * Bit[9-15] - Reserved 3474 */ 3475 3476 enum pr_residency_mode { 3477 PR_RESIDENCY_MODE_PHY = 0x0, 3478 PR_RESIDENCY_MODE_ALPM, 3479 PR_RESIDENCY_MODE_IPS2, 3480 PR_RESIDENCY_MODE_FRAME_CNT, 3481 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3482 }; 3483 3484 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3485 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3486 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3487 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3488 3489 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3490 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3491 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3492 3493 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3494 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3495 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3496 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3497 3498 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3499 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3500 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3501 3502 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3503 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3504 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3505 3506 /** 3507 * Definition of a replay_state. 3508 */ 3509 enum replay_state { 3510 REPLAY_STATE_0 = 0x0, 3511 REPLAY_STATE_1 = 0x10, 3512 REPLAY_STATE_1A = 0x11, 3513 REPLAY_STATE_2 = 0x20, 3514 REPLAY_STATE_2A = 0x21, 3515 REPLAY_STATE_3 = 0x30, 3516 REPLAY_STATE_3INIT = 0x31, 3517 REPLAY_STATE_4 = 0x40, 3518 REPLAY_STATE_4A = 0x41, 3519 REPLAY_STATE_4B = 0x42, 3520 REPLAY_STATE_4C = 0x43, 3521 REPLAY_STATE_4D = 0x44, 3522 REPLAY_STATE_4E = 0x45, 3523 REPLAY_STATE_4B_LOCKED = 0x4A, 3524 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3525 REPLAY_STATE_5 = 0x50, 3526 REPLAY_STATE_5A = 0x51, 3527 REPLAY_STATE_5B = 0x52, 3528 REPLAY_STATE_5A_LOCKED = 0x5A, 3529 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3530 REPLAY_STATE_6 = 0x60, 3531 REPLAY_STATE_6A = 0x61, 3532 REPLAY_STATE_6B = 0x62, 3533 REPLAY_STATE_INVALID = 0xFF, 3534 }; 3535 3536 /** 3537 * Replay command sub-types. 3538 */ 3539 enum dmub_cmd_replay_type { 3540 /** 3541 * Copy driver-calculated parameters to REPLAY state. 3542 */ 3543 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3544 /** 3545 * Enable REPLAY. 3546 */ 3547 DMUB_CMD__REPLAY_ENABLE = 1, 3548 /** 3549 * Set Replay power option. 3550 */ 3551 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3552 /** 3553 * Set coasting vtotal. 3554 */ 3555 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3556 /** 3557 * Set power opt and coasting vtotal. 3558 */ 3559 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3560 /** 3561 * Set disabled iiming sync. 3562 */ 3563 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3564 /** 3565 * Set Residency Frameupdate Timer. 3566 */ 3567 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3568 /** 3569 * Set pseudo vtotal 3570 */ 3571 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3572 /** 3573 * Set adaptive sync sdp enabled 3574 */ 3575 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3576 /** 3577 * Set Replay General command. 3578 */ 3579 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3580 }; 3581 3582 /** 3583 * Replay general command sub-types. 3584 */ 3585 enum dmub_cmd_replay_general_subtype { 3586 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3587 /** 3588 * TODO: For backward compatible, allow new command only. 3589 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3590 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3591 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3592 */ 3593 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3594 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3595 }; 3596 3597 /** 3598 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3599 */ 3600 struct dmub_cmd_replay_copy_settings_data { 3601 /** 3602 * Flags that can be set by driver to change some replay behaviour. 3603 */ 3604 union replay_debug_flags debug; 3605 3606 /** 3607 * @flags: Flags used to determine feature functionality. 3608 */ 3609 union replay_hw_flags flags; 3610 3611 /** 3612 * DPP HW instance. 3613 */ 3614 uint8_t dpp_inst; 3615 /** 3616 * OTG HW instance. 3617 */ 3618 uint8_t otg_inst; 3619 /** 3620 * DIG FE HW instance. 3621 */ 3622 uint8_t digfe_inst; 3623 /** 3624 * DIG BE HW instance. 3625 */ 3626 uint8_t digbe_inst; 3627 /** 3628 * AUX HW instance. 3629 */ 3630 uint8_t aux_inst; 3631 /** 3632 * Panel Instance. 3633 * Panel isntance to identify which psr_state to use 3634 * Currently the support is only for 0 or 1 3635 */ 3636 uint8_t panel_inst; 3637 /** 3638 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3639 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3640 */ 3641 uint8_t pixel_deviation_per_line; 3642 /** 3643 * @max_deviation_line: The max number of deviation line that can keep the timing 3644 * synchronized between the Source and Sink during Replay normal sleep mode. 3645 */ 3646 uint8_t max_deviation_line; 3647 /** 3648 * Length of each horizontal line in ns. 3649 */ 3650 uint32_t line_time_in_ns; 3651 /** 3652 * PHY instance. 3653 */ 3654 uint8_t dpphy_inst; 3655 /** 3656 * Determines if SMU optimzations are enabled/disabled. 3657 */ 3658 uint8_t smu_optimizations_en; 3659 /** 3660 * Determines if timing sync are enabled/disabled. 3661 */ 3662 uint8_t replay_timing_sync_supported; 3663 /* 3664 * Use FSM state for Replay power up/down 3665 */ 3666 uint8_t use_phy_fsm; 3667 }; 3668 3669 /** 3670 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3671 */ 3672 struct dmub_rb_cmd_replay_copy_settings { 3673 /** 3674 * Command header. 3675 */ 3676 struct dmub_cmd_header header; 3677 /** 3678 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3679 */ 3680 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3681 }; 3682 3683 /** 3684 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3685 */ 3686 enum replay_enable { 3687 /** 3688 * Disable REPLAY. 3689 */ 3690 REPLAY_DISABLE = 0, 3691 /** 3692 * Enable REPLAY. 3693 */ 3694 REPLAY_ENABLE = 1, 3695 }; 3696 3697 /** 3698 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3699 */ 3700 struct dmub_rb_cmd_replay_enable_data { 3701 /** 3702 * Replay enable or disable. 3703 */ 3704 uint8_t enable; 3705 /** 3706 * Panel Instance. 3707 * Panel isntance to identify which replay_state to use 3708 * Currently the support is only for 0 or 1 3709 */ 3710 uint8_t panel_inst; 3711 /** 3712 * Phy state to enter. 3713 * Values to use are defined in dmub_phy_fsm_state 3714 */ 3715 uint8_t phy_fsm_state; 3716 /** 3717 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3718 * Set this using enum phy_link_rate. 3719 * This does not support HDMI/DP2 for now. 3720 */ 3721 uint8_t phy_rate; 3722 }; 3723 3724 /** 3725 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3726 * Replay enable/disable is controlled using action in data. 3727 */ 3728 struct dmub_rb_cmd_replay_enable { 3729 /** 3730 * Command header. 3731 */ 3732 struct dmub_cmd_header header; 3733 3734 struct dmub_rb_cmd_replay_enable_data data; 3735 }; 3736 3737 /** 3738 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3739 */ 3740 struct dmub_cmd_replay_set_power_opt_data { 3741 /** 3742 * Panel Instance. 3743 * Panel isntance to identify which replay_state to use 3744 * Currently the support is only for 0 or 1 3745 */ 3746 uint8_t panel_inst; 3747 /** 3748 * Explicit padding to 4 byte boundary. 3749 */ 3750 uint8_t pad[3]; 3751 /** 3752 * REPLAY power option 3753 */ 3754 uint32_t power_opt; 3755 }; 3756 3757 /** 3758 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3759 */ 3760 struct dmub_cmd_replay_set_timing_sync_data { 3761 /** 3762 * Panel Instance. 3763 * Panel isntance to identify which replay_state to use 3764 * Currently the support is only for 0 or 1 3765 */ 3766 uint8_t panel_inst; 3767 /** 3768 * REPLAY set_timing_sync 3769 */ 3770 uint8_t timing_sync_supported; 3771 /** 3772 * Explicit padding to 4 byte boundary. 3773 */ 3774 uint8_t pad[2]; 3775 }; 3776 3777 /** 3778 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3779 */ 3780 struct dmub_cmd_replay_set_pseudo_vtotal { 3781 /** 3782 * Panel Instance. 3783 * Panel isntance to identify which replay_state to use 3784 * Currently the support is only for 0 or 1 3785 */ 3786 uint8_t panel_inst; 3787 /** 3788 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3789 */ 3790 uint16_t vtotal; 3791 /** 3792 * Explicit padding to 4 byte boundary. 3793 */ 3794 uint8_t pad; 3795 }; 3796 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3797 /** 3798 * Panel Instance. 3799 * Panel isntance to identify which replay_state to use 3800 * Currently the support is only for 0 or 1 3801 */ 3802 uint8_t panel_inst; 3803 /** 3804 * enabled: set adaptive sync sdp enabled 3805 */ 3806 uint8_t force_disabled; 3807 3808 uint8_t pad[2]; 3809 }; 3810 struct dmub_cmd_replay_set_general_cmd_data { 3811 /** 3812 * Panel Instance. 3813 * Panel isntance to identify which replay_state to use 3814 * Currently the support is only for 0 or 1 3815 */ 3816 uint8_t panel_inst; 3817 /** 3818 * subtype: replay general cmd sub type 3819 */ 3820 uint8_t subtype; 3821 3822 uint8_t pad[2]; 3823 /** 3824 * config data with param1 and param2 3825 */ 3826 uint32_t param1; 3827 3828 uint32_t param2; 3829 }; 3830 3831 /** 3832 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3833 */ 3834 struct dmub_rb_cmd_replay_set_power_opt { 3835 /** 3836 * Command header. 3837 */ 3838 struct dmub_cmd_header header; 3839 /** 3840 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3841 */ 3842 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3843 }; 3844 3845 /** 3846 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3847 */ 3848 struct dmub_cmd_replay_set_coasting_vtotal_data { 3849 /** 3850 * 16-bit value dicated by driver that indicates the coasting vtotal. 3851 */ 3852 uint16_t coasting_vtotal; 3853 /** 3854 * REPLAY control version. 3855 */ 3856 uint8_t cmd_version; 3857 /** 3858 * Panel Instance. 3859 * Panel isntance to identify which replay_state to use 3860 * Currently the support is only for 0 or 1 3861 */ 3862 uint8_t panel_inst; 3863 /** 3864 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3865 */ 3866 uint16_t coasting_vtotal_high; 3867 /** 3868 * Explicit padding to 4 byte boundary. 3869 */ 3870 uint8_t pad[2]; 3871 }; 3872 3873 /** 3874 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3875 */ 3876 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3877 /** 3878 * Command header. 3879 */ 3880 struct dmub_cmd_header header; 3881 /** 3882 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3883 */ 3884 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3885 }; 3886 3887 /** 3888 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3889 */ 3890 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3891 /** 3892 * Command header. 3893 */ 3894 struct dmub_cmd_header header; 3895 /** 3896 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3897 */ 3898 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3899 /** 3900 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3901 */ 3902 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3903 }; 3904 3905 /** 3906 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3907 */ 3908 struct dmub_rb_cmd_replay_set_timing_sync { 3909 /** 3910 * Command header. 3911 */ 3912 struct dmub_cmd_header header; 3913 /** 3914 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3915 */ 3916 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3917 }; 3918 3919 /** 3920 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3921 */ 3922 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3923 /** 3924 * Command header. 3925 */ 3926 struct dmub_cmd_header header; 3927 /** 3928 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3929 */ 3930 struct dmub_cmd_replay_set_pseudo_vtotal data; 3931 }; 3932 3933 /** 3934 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3935 */ 3936 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3937 /** 3938 * Command header. 3939 */ 3940 struct dmub_cmd_header header; 3941 /** 3942 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3943 */ 3944 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3945 }; 3946 3947 /** 3948 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3949 */ 3950 struct dmub_rb_cmd_replay_set_general_cmd { 3951 /** 3952 * Command header. 3953 */ 3954 struct dmub_cmd_header header; 3955 /** 3956 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3957 */ 3958 struct dmub_cmd_replay_set_general_cmd_data data; 3959 }; 3960 3961 /** 3962 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3963 */ 3964 struct dmub_cmd_replay_frameupdate_timer_data { 3965 /** 3966 * Panel Instance. 3967 * Panel isntance to identify which replay_state to use 3968 * Currently the support is only for 0 or 1 3969 */ 3970 uint8_t panel_inst; 3971 /** 3972 * Replay Frameupdate Timer Enable or not 3973 */ 3974 uint8_t enable; 3975 /** 3976 * REPLAY force reflash frame update number 3977 */ 3978 uint16_t frameupdate_count; 3979 }; 3980 /** 3981 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3982 */ 3983 struct dmub_rb_cmd_replay_set_frameupdate_timer { 3984 /** 3985 * Command header. 3986 */ 3987 struct dmub_cmd_header header; 3988 /** 3989 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3990 */ 3991 struct dmub_cmd_replay_frameupdate_timer_data data; 3992 }; 3993 3994 /** 3995 * Definition union of replay command set 3996 */ 3997 union dmub_replay_cmd_set { 3998 /** 3999 * Panel Instance. 4000 * Panel isntance to identify which replay_state to use 4001 * Currently the support is only for 0 or 1 4002 */ 4003 uint8_t panel_inst; 4004 /** 4005 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4006 */ 4007 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4008 /** 4009 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4010 */ 4011 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4012 /** 4013 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4014 */ 4015 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4016 /** 4017 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4018 */ 4019 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4020 /** 4021 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4022 */ 4023 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4024 }; 4025 4026 /** 4027 * Set of HW components that can be locked. 4028 * 4029 * Note: If updating with more HW components, fields 4030 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4031 */ 4032 union dmub_hw_lock_flags { 4033 /** 4034 * Set of HW components that can be locked. 4035 */ 4036 struct { 4037 /** 4038 * Lock/unlock OTG master update lock. 4039 */ 4040 uint8_t lock_pipe : 1; 4041 /** 4042 * Lock/unlock cursor. 4043 */ 4044 uint8_t lock_cursor : 1; 4045 /** 4046 * Lock/unlock global update lock. 4047 */ 4048 uint8_t lock_dig : 1; 4049 /** 4050 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4051 */ 4052 uint8_t triple_buffer_lock : 1; 4053 } bits; 4054 4055 /** 4056 * Union for HW Lock flags. 4057 */ 4058 uint8_t u8All; 4059 }; 4060 4061 /** 4062 * Instances of HW to be locked. 4063 * 4064 * Note: If updating with more HW components, fields 4065 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4066 */ 4067 struct dmub_hw_lock_inst_flags { 4068 /** 4069 * OTG HW instance for OTG master update lock. 4070 */ 4071 uint8_t otg_inst; 4072 /** 4073 * OPP instance for cursor lock. 4074 */ 4075 uint8_t opp_inst; 4076 /** 4077 * OTG HW instance for global update lock. 4078 * TODO: Remove, and re-use otg_inst. 4079 */ 4080 uint8_t dig_inst; 4081 /** 4082 * Explicit pad to 4 byte boundary. 4083 */ 4084 uint8_t pad; 4085 }; 4086 4087 /** 4088 * Clients that can acquire the HW Lock Manager. 4089 * 4090 * Note: If updating with more clients, fields in 4091 * dmub_inbox0_cmd_lock_hw must be updated to match. 4092 */ 4093 enum hw_lock_client { 4094 /** 4095 * Driver is the client of HW Lock Manager. 4096 */ 4097 HW_LOCK_CLIENT_DRIVER = 0, 4098 /** 4099 * PSR SU is the client of HW Lock Manager. 4100 */ 4101 HW_LOCK_CLIENT_PSR_SU = 1, 4102 HW_LOCK_CLIENT_SUBVP = 3, 4103 /** 4104 * Replay is the client of HW Lock Manager. 4105 */ 4106 HW_LOCK_CLIENT_REPLAY = 4, 4107 HW_LOCK_CLIENT_FAMS2 = 5, 4108 /** 4109 * Invalid client. 4110 */ 4111 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4112 }; 4113 4114 /** 4115 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4116 */ 4117 struct dmub_cmd_lock_hw_data { 4118 /** 4119 * Specifies the client accessing HW Lock Manager. 4120 */ 4121 enum hw_lock_client client; 4122 /** 4123 * HW instances to be locked. 4124 */ 4125 struct dmub_hw_lock_inst_flags inst_flags; 4126 /** 4127 * Which components to be locked. 4128 */ 4129 union dmub_hw_lock_flags hw_locks; 4130 /** 4131 * Specifies lock/unlock. 4132 */ 4133 uint8_t lock; 4134 /** 4135 * HW can be unlocked separately from releasing the HW Lock Mgr. 4136 * This flag is set if the client wishes to release the object. 4137 */ 4138 uint8_t should_release; 4139 /** 4140 * Explicit padding to 4 byte boundary. 4141 */ 4142 uint8_t pad; 4143 }; 4144 4145 /** 4146 * Definition of a DMUB_CMD__HW_LOCK command. 4147 * Command is used by driver and FW. 4148 */ 4149 struct dmub_rb_cmd_lock_hw { 4150 /** 4151 * Command header. 4152 */ 4153 struct dmub_cmd_header header; 4154 /** 4155 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4156 */ 4157 struct dmub_cmd_lock_hw_data lock_hw_data; 4158 }; 4159 4160 /** 4161 * ABM command sub-types. 4162 */ 4163 enum dmub_cmd_abm_type { 4164 /** 4165 * Initialize parameters for ABM algorithm. 4166 * Data is passed through an indirect buffer. 4167 */ 4168 DMUB_CMD__ABM_INIT_CONFIG = 0, 4169 /** 4170 * Set OTG and panel HW instance. 4171 */ 4172 DMUB_CMD__ABM_SET_PIPE = 1, 4173 /** 4174 * Set user requested backklight level. 4175 */ 4176 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4177 /** 4178 * Set ABM operating/aggression level. 4179 */ 4180 DMUB_CMD__ABM_SET_LEVEL = 3, 4181 /** 4182 * Set ambient light level. 4183 */ 4184 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4185 /** 4186 * Enable/disable fractional duty cycle for backlight PWM. 4187 */ 4188 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4189 4190 /** 4191 * unregister vertical interrupt after steady state is reached 4192 */ 4193 DMUB_CMD__ABM_PAUSE = 6, 4194 4195 /** 4196 * Save and Restore ABM state. On save we save parameters, and 4197 * on restore we update state with passed in data. 4198 */ 4199 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4200 4201 /** 4202 * Query ABM caps. 4203 */ 4204 DMUB_CMD__ABM_QUERY_CAPS = 8, 4205 4206 /** 4207 * Set ABM Events 4208 */ 4209 DMUB_CMD__ABM_SET_EVENT = 9, 4210 4211 /** 4212 * Get the current ACE curve. 4213 */ 4214 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4215 }; 4216 4217 struct abm_ace_curve { 4218 /** 4219 * @offsets: ACE curve offsets. 4220 */ 4221 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4222 4223 /** 4224 * @thresholds: ACE curve thresholds. 4225 */ 4226 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4227 4228 /** 4229 * @slopes: ACE curve slopes. 4230 */ 4231 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4232 }; 4233 4234 struct fixed_pt_format { 4235 /** 4236 * @sign_bit: Indicates whether one bit is reserved for the sign. 4237 */ 4238 bool sign_bit; 4239 4240 /** 4241 * @num_int_bits: Number of bits used for integer part. 4242 */ 4243 uint8_t num_int_bits; 4244 4245 /** 4246 * @num_frac_bits: Number of bits used for fractional part. 4247 */ 4248 uint8_t num_frac_bits; 4249 4250 /** 4251 * @pad: Explicit padding to 4 byte boundary. 4252 */ 4253 uint8_t pad; 4254 }; 4255 4256 struct abm_caps { 4257 /** 4258 * @num_hg_bins: Number of histogram bins. 4259 */ 4260 uint8_t num_hg_bins; 4261 4262 /** 4263 * @num_ace_segments: Number of ACE curve segments. 4264 */ 4265 uint8_t num_ace_segments; 4266 4267 /** 4268 * @pad: Explicit padding to 4 byte boundary. 4269 */ 4270 uint8_t pad[2]; 4271 4272 /** 4273 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4274 */ 4275 struct fixed_pt_format ace_thresholds_format; 4276 4277 /** 4278 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4279 */ 4280 struct fixed_pt_format ace_offsets_format; 4281 4282 /** 4283 * @ace_slopes_format: Format of the ACE slopes. 4284 */ 4285 struct fixed_pt_format ace_slopes_format; 4286 }; 4287 4288 /** 4289 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4290 * Requirements: 4291 * - Padded explicitly to 32-bit boundary. 4292 * - Must ensure this structure matches the one on driver-side, 4293 * otherwise it won't be aligned. 4294 */ 4295 struct abm_config_table { 4296 /** 4297 * Gamma curve thresholds, used for crgb conversion. 4298 */ 4299 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4300 /** 4301 * Gamma curve offsets, used for crgb conversion. 4302 */ 4303 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4304 /** 4305 * Gamma curve slopes, used for crgb conversion. 4306 */ 4307 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4308 /** 4309 * Custom backlight curve thresholds. 4310 */ 4311 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4312 /** 4313 * Custom backlight curve offsets. 4314 */ 4315 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4316 /** 4317 * Ambient light thresholds. 4318 */ 4319 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4320 /** 4321 * Minimum programmable backlight. 4322 */ 4323 uint16_t min_abm_backlight; // 122B 4324 /** 4325 * Minimum reduction values. 4326 */ 4327 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4328 /** 4329 * Maximum reduction values. 4330 */ 4331 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4332 /** 4333 * Bright positive gain. 4334 */ 4335 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4336 /** 4337 * Dark negative gain. 4338 */ 4339 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4340 /** 4341 * Hybrid factor. 4342 */ 4343 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4344 /** 4345 * Contrast factor. 4346 */ 4347 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4348 /** 4349 * Deviation gain. 4350 */ 4351 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4352 /** 4353 * Minimum knee. 4354 */ 4355 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4356 /** 4357 * Maximum knee. 4358 */ 4359 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4360 /** 4361 * Unused. 4362 */ 4363 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4364 /** 4365 * Explicit padding to 4 byte boundary. 4366 */ 4367 uint8_t pad3[3]; // 229B 4368 /** 4369 * Backlight ramp reduction. 4370 */ 4371 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4372 /** 4373 * Backlight ramp start. 4374 */ 4375 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4376 }; 4377 4378 /** 4379 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4380 */ 4381 struct dmub_cmd_abm_set_pipe_data { 4382 /** 4383 * OTG HW instance. 4384 */ 4385 uint8_t otg_inst; 4386 4387 /** 4388 * Panel Control HW instance. 4389 */ 4390 uint8_t panel_inst; 4391 4392 /** 4393 * Controls how ABM will interpret a set pipe or set level command. 4394 */ 4395 uint8_t set_pipe_option; 4396 4397 /** 4398 * Unused. 4399 * TODO: Remove. 4400 */ 4401 uint8_t ramping_boundary; 4402 4403 /** 4404 * PwrSeq HW Instance. 4405 */ 4406 uint8_t pwrseq_inst; 4407 4408 /** 4409 * Explicit padding to 4 byte boundary. 4410 */ 4411 uint8_t pad[3]; 4412 }; 4413 4414 /** 4415 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4416 */ 4417 struct dmub_rb_cmd_abm_set_pipe { 4418 /** 4419 * Command header. 4420 */ 4421 struct dmub_cmd_header header; 4422 4423 /** 4424 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4425 */ 4426 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4427 }; 4428 4429 /** 4430 * Type of backlight control method to be used by ABM module 4431 */ 4432 enum dmub_backlight_control_type { 4433 /** 4434 * PWM Backlight control 4435 */ 4436 DMU_BACKLIGHT_CONTROL_PWM = 0, 4437 /** 4438 * VESA Aux-based backlight control 4439 */ 4440 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4441 /** 4442 * AMD DPCD Aux-based backlight control 4443 */ 4444 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4445 }; 4446 4447 /** 4448 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4449 */ 4450 struct dmub_cmd_abm_set_backlight_data { 4451 /** 4452 * Number of frames to ramp to backlight user level. 4453 */ 4454 uint32_t frame_ramp; 4455 4456 /** 4457 * Requested backlight level from user. 4458 */ 4459 uint32_t backlight_user_level; 4460 4461 /** 4462 * ABM control version. 4463 */ 4464 uint8_t version; 4465 4466 /** 4467 * Panel Control HW instance mask. 4468 * Bit 0 is Panel Control HW instance 0. 4469 * Bit 1 is Panel Control HW instance 1. 4470 */ 4471 uint8_t panel_mask; 4472 4473 /** 4474 * AUX HW Instance. 4475 */ 4476 uint8_t aux_inst; 4477 4478 /** 4479 * Explicit padding to 4 byte boundary. 4480 */ 4481 uint8_t pad[1]; 4482 4483 /** 4484 * Backlight control type. 4485 * Value 0 is PWM backlight control. 4486 * Value 1 is VAUX backlight control. 4487 * Value 2 is AMD DPCD AUX backlight control. 4488 */ 4489 enum dmub_backlight_control_type backlight_control_type; 4490 4491 /** 4492 * Minimum luminance in nits. 4493 */ 4494 uint32_t min_luminance; 4495 4496 /** 4497 * Maximum luminance in nits. 4498 */ 4499 uint32_t max_luminance; 4500 4501 /** 4502 * Minimum backlight in pwm. 4503 */ 4504 uint32_t min_backlight_pwm; 4505 4506 /** 4507 * Maximum backlight in pwm. 4508 */ 4509 uint32_t max_backlight_pwm; 4510 }; 4511 4512 /** 4513 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4514 */ 4515 struct dmub_rb_cmd_abm_set_backlight { 4516 /** 4517 * Command header. 4518 */ 4519 struct dmub_cmd_header header; 4520 4521 /** 4522 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4523 */ 4524 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4525 }; 4526 4527 /** 4528 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4529 */ 4530 struct dmub_cmd_abm_set_level_data { 4531 /** 4532 * Set current ABM operating/aggression level. 4533 */ 4534 uint32_t level; 4535 4536 /** 4537 * ABM control version. 4538 */ 4539 uint8_t version; 4540 4541 /** 4542 * Panel Control HW instance mask. 4543 * Bit 0 is Panel Control HW instance 0. 4544 * Bit 1 is Panel Control HW instance 1. 4545 */ 4546 uint8_t panel_mask; 4547 4548 /** 4549 * Explicit padding to 4 byte boundary. 4550 */ 4551 uint8_t pad[2]; 4552 }; 4553 4554 /** 4555 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4556 */ 4557 struct dmub_rb_cmd_abm_set_level { 4558 /** 4559 * Command header. 4560 */ 4561 struct dmub_cmd_header header; 4562 4563 /** 4564 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4565 */ 4566 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4567 }; 4568 4569 /** 4570 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4571 */ 4572 struct dmub_cmd_abm_set_ambient_level_data { 4573 /** 4574 * Ambient light sensor reading from OS. 4575 */ 4576 uint32_t ambient_lux; 4577 4578 /** 4579 * ABM control version. 4580 */ 4581 uint8_t version; 4582 4583 /** 4584 * Panel Control HW instance mask. 4585 * Bit 0 is Panel Control HW instance 0. 4586 * Bit 1 is Panel Control HW instance 1. 4587 */ 4588 uint8_t panel_mask; 4589 4590 /** 4591 * Explicit padding to 4 byte boundary. 4592 */ 4593 uint8_t pad[2]; 4594 }; 4595 4596 /** 4597 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4598 */ 4599 struct dmub_rb_cmd_abm_set_ambient_level { 4600 /** 4601 * Command header. 4602 */ 4603 struct dmub_cmd_header header; 4604 4605 /** 4606 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4607 */ 4608 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4609 }; 4610 4611 /** 4612 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4613 */ 4614 struct dmub_cmd_abm_set_pwm_frac_data { 4615 /** 4616 * Enable/disable fractional duty cycle for backlight PWM. 4617 * TODO: Convert to uint8_t. 4618 */ 4619 uint32_t fractional_pwm; 4620 4621 /** 4622 * ABM control version. 4623 */ 4624 uint8_t version; 4625 4626 /** 4627 * Panel Control HW instance mask. 4628 * Bit 0 is Panel Control HW instance 0. 4629 * Bit 1 is Panel Control HW instance 1. 4630 */ 4631 uint8_t panel_mask; 4632 4633 /** 4634 * Explicit padding to 4 byte boundary. 4635 */ 4636 uint8_t pad[2]; 4637 }; 4638 4639 /** 4640 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4641 */ 4642 struct dmub_rb_cmd_abm_set_pwm_frac { 4643 /** 4644 * Command header. 4645 */ 4646 struct dmub_cmd_header header; 4647 4648 /** 4649 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4650 */ 4651 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4652 }; 4653 4654 /** 4655 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4656 */ 4657 struct dmub_cmd_abm_init_config_data { 4658 /** 4659 * Location of indirect buffer used to pass init data to ABM. 4660 */ 4661 union dmub_addr src; 4662 4663 /** 4664 * Indirect buffer length. 4665 */ 4666 uint16_t bytes; 4667 4668 4669 /** 4670 * ABM control version. 4671 */ 4672 uint8_t version; 4673 4674 /** 4675 * Panel Control HW instance mask. 4676 * Bit 0 is Panel Control HW instance 0. 4677 * Bit 1 is Panel Control HW instance 1. 4678 */ 4679 uint8_t panel_mask; 4680 4681 /** 4682 * Explicit padding to 4 byte boundary. 4683 */ 4684 uint8_t pad[2]; 4685 }; 4686 4687 /** 4688 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4689 */ 4690 struct dmub_rb_cmd_abm_init_config { 4691 /** 4692 * Command header. 4693 */ 4694 struct dmub_cmd_header header; 4695 4696 /** 4697 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4698 */ 4699 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4700 }; 4701 4702 /** 4703 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4704 */ 4705 4706 struct dmub_cmd_abm_pause_data { 4707 4708 /** 4709 * Panel Control HW instance mask. 4710 * Bit 0 is Panel Control HW instance 0. 4711 * Bit 1 is Panel Control HW instance 1. 4712 */ 4713 uint8_t panel_mask; 4714 4715 /** 4716 * OTG hw instance 4717 */ 4718 uint8_t otg_inst; 4719 4720 /** 4721 * Enable or disable ABM pause 4722 */ 4723 uint8_t enable; 4724 4725 /** 4726 * Explicit padding to 4 byte boundary. 4727 */ 4728 uint8_t pad[1]; 4729 }; 4730 4731 /** 4732 * Definition of a DMUB_CMD__ABM_PAUSE command. 4733 */ 4734 struct dmub_rb_cmd_abm_pause { 4735 /** 4736 * Command header. 4737 */ 4738 struct dmub_cmd_header header; 4739 4740 /** 4741 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4742 */ 4743 struct dmub_cmd_abm_pause_data abm_pause_data; 4744 }; 4745 4746 /** 4747 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4748 */ 4749 struct dmub_cmd_abm_query_caps_in { 4750 /** 4751 * Panel instance. 4752 */ 4753 uint8_t panel_inst; 4754 4755 /** 4756 * Explicit padding to 4 byte boundary. 4757 */ 4758 uint8_t pad[3]; 4759 }; 4760 4761 /** 4762 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4763 */ 4764 struct dmub_cmd_abm_query_caps_out { 4765 /** 4766 * SW Algorithm caps. 4767 */ 4768 struct abm_caps sw_caps; 4769 4770 /** 4771 * ABM HW caps. 4772 */ 4773 struct abm_caps hw_caps; 4774 }; 4775 4776 /** 4777 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4778 */ 4779 struct dmub_rb_cmd_abm_query_caps { 4780 /** 4781 * Command header. 4782 */ 4783 struct dmub_cmd_header header; 4784 4785 /** 4786 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4787 */ 4788 union { 4789 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4790 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4791 } data; 4792 }; 4793 4794 /** 4795 * enum dmub_abm_ace_curve_type - ACE curve type. 4796 */ 4797 enum dmub_abm_ace_curve_type { 4798 /** 4799 * ACE curve as defined by the SW layer. 4800 */ 4801 ABM_ACE_CURVE_TYPE__SW = 0, 4802 /** 4803 * ACE curve as defined by the SW to HW translation interface layer. 4804 */ 4805 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4806 }; 4807 4808 /** 4809 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4810 */ 4811 struct dmub_rb_cmd_abm_get_ace_curve { 4812 /** 4813 * Command header. 4814 */ 4815 struct dmub_cmd_header header; 4816 4817 /** 4818 * Address where ACE curve should be copied. 4819 */ 4820 union dmub_addr dest; 4821 4822 /** 4823 * Type of ACE curve being queried. 4824 */ 4825 enum dmub_abm_ace_curve_type ace_type; 4826 4827 /** 4828 * Indirect buffer length. 4829 */ 4830 uint16_t bytes; 4831 4832 /** 4833 * eDP panel instance. 4834 */ 4835 uint8_t panel_inst; 4836 4837 /** 4838 * Explicit padding to 4 byte boundary. 4839 */ 4840 uint8_t pad; 4841 }; 4842 4843 /** 4844 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4845 */ 4846 struct dmub_rb_cmd_abm_save_restore { 4847 /** 4848 * Command header. 4849 */ 4850 struct dmub_cmd_header header; 4851 4852 /** 4853 * OTG hw instance 4854 */ 4855 uint8_t otg_inst; 4856 4857 /** 4858 * Enable or disable ABM pause 4859 */ 4860 uint8_t freeze; 4861 4862 /** 4863 * Explicit padding to 4 byte boundary. 4864 */ 4865 uint8_t debug; 4866 4867 /** 4868 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4869 */ 4870 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4871 }; 4872 4873 /** 4874 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4875 */ 4876 4877 struct dmub_cmd_abm_set_event_data { 4878 4879 /** 4880 * VB Scaling Init. Strength Mapping 4881 * Byte 0: 0~255 for VB level 0 4882 * Byte 1: 0~255 for VB level 1 4883 * Byte 2: 0~255 for VB level 2 4884 * Byte 3: 0~255 for VB level 3 4885 */ 4886 uint32_t vb_scaling_strength_mapping; 4887 /** 4888 * VariBright Scaling Enable 4889 */ 4890 uint8_t vb_scaling_enable; 4891 /** 4892 * Panel Control HW instance mask. 4893 * Bit 0 is Panel Control HW instance 0. 4894 * Bit 1 is Panel Control HW instance 1. 4895 */ 4896 uint8_t panel_mask; 4897 4898 /** 4899 * Explicit padding to 4 byte boundary. 4900 */ 4901 uint8_t pad[2]; 4902 }; 4903 4904 /** 4905 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 4906 */ 4907 struct dmub_rb_cmd_abm_set_event { 4908 /** 4909 * Command header. 4910 */ 4911 struct dmub_cmd_header header; 4912 4913 /** 4914 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4915 */ 4916 struct dmub_cmd_abm_set_event_data abm_set_event_data; 4917 }; 4918 4919 /** 4920 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4921 */ 4922 struct dmub_cmd_query_feature_caps_data { 4923 /** 4924 * DMUB feature capabilities. 4925 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4926 */ 4927 struct dmub_feature_caps feature_caps; 4928 }; 4929 4930 /** 4931 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4932 */ 4933 struct dmub_rb_cmd_query_feature_caps { 4934 /** 4935 * Command header. 4936 */ 4937 struct dmub_cmd_header header; 4938 /** 4939 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4940 */ 4941 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4942 }; 4943 4944 /** 4945 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4946 */ 4947 struct dmub_cmd_visual_confirm_color_data { 4948 /** 4949 * DMUB visual confirm color 4950 */ 4951 struct dmub_visual_confirm_color visual_confirm_color; 4952 }; 4953 4954 /** 4955 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4956 */ 4957 struct dmub_rb_cmd_get_visual_confirm_color { 4958 /** 4959 * Command header. 4960 */ 4961 struct dmub_cmd_header header; 4962 /** 4963 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4964 */ 4965 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4966 }; 4967 4968 /** 4969 * enum dmub_cmd_panel_cntl_type - Panel control command. 4970 */ 4971 enum dmub_cmd_panel_cntl_type { 4972 /** 4973 * Initializes embedded panel hardware blocks. 4974 */ 4975 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4976 /** 4977 * Queries backlight info for the embedded panel. 4978 */ 4979 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4980 /** 4981 * Sets the PWM Freq as per user's requirement. 4982 */ 4983 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 4984 }; 4985 4986 /** 4987 * struct dmub_cmd_panel_cntl_data - Panel control data. 4988 */ 4989 struct dmub_cmd_panel_cntl_data { 4990 uint32_t pwrseq_inst; /**< pwrseq instance */ 4991 uint32_t current_backlight; /* in/out */ 4992 uint32_t bl_pwm_cntl; /* in/out */ 4993 uint32_t bl_pwm_period_cntl; /* in/out */ 4994 uint32_t bl_pwm_ref_div1; /* in/out */ 4995 uint8_t is_backlight_on : 1; /* in/out */ 4996 uint8_t is_powered_on : 1; /* in/out */ 4997 uint8_t padding[3]; 4998 uint32_t bl_pwm_ref_div2; /* in/out */ 4999 uint8_t reserved[4]; 5000 }; 5001 5002 /** 5003 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5004 */ 5005 struct dmub_rb_cmd_panel_cntl { 5006 struct dmub_cmd_header header; /**< header */ 5007 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5008 }; 5009 5010 struct dmub_optc_state { 5011 uint32_t v_total_max; 5012 uint32_t v_total_min; 5013 uint32_t tg_inst; 5014 }; 5015 5016 struct dmub_rb_cmd_drr_update { 5017 struct dmub_cmd_header header; 5018 struct dmub_optc_state dmub_optc_state_req; 5019 }; 5020 5021 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5022 uint32_t pix_clk_100hz; 5023 uint8_t max_ramp_step; 5024 uint8_t pipes; 5025 uint8_t min_refresh_in_hz; 5026 uint8_t pipe_count; 5027 uint8_t pipe_index[4]; 5028 }; 5029 5030 struct dmub_cmd_fw_assisted_mclk_switch_config { 5031 uint8_t fams_enabled; 5032 uint8_t visual_confirm_enabled; 5033 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5034 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5035 }; 5036 5037 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5038 struct dmub_cmd_header header; 5039 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5040 }; 5041 5042 /** 5043 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5044 */ 5045 struct dmub_cmd_lvtma_control_data { 5046 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5047 uint8_t bypass_panel_control_wait; 5048 uint8_t reserved_0[2]; /**< For future use */ 5049 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5050 uint8_t reserved_1[3]; /**< For future use */ 5051 }; 5052 5053 /** 5054 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5055 */ 5056 struct dmub_rb_cmd_lvtma_control { 5057 /** 5058 * Command header. 5059 */ 5060 struct dmub_cmd_header header; 5061 /** 5062 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5063 */ 5064 struct dmub_cmd_lvtma_control_data data; 5065 }; 5066 5067 /** 5068 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5069 */ 5070 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5071 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5072 uint8_t is_usb; /**< is phy is usb */ 5073 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5074 uint8_t is_dp4; /**< is dp in 4 lane */ 5075 }; 5076 5077 /** 5078 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5079 */ 5080 struct dmub_rb_cmd_transmitter_query_dp_alt { 5081 struct dmub_cmd_header header; /**< header */ 5082 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5083 }; 5084 5085 struct phy_test_mode { 5086 uint8_t mode; 5087 uint8_t pat0; 5088 uint8_t pad[2]; 5089 }; 5090 5091 /** 5092 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5093 */ 5094 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5095 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5096 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5097 uint8_t lane_num; /**< Number of lanes */ 5098 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5099 struct phy_test_mode test_mode; 5100 enum dmub_phy_fsm_state state; 5101 uint32_t status; 5102 uint8_t pad; 5103 }; 5104 5105 /** 5106 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5107 */ 5108 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5109 struct dmub_cmd_header header; /**< header */ 5110 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5111 }; 5112 5113 /** 5114 * Maximum number of bytes a chunk sent to DMUB for parsing 5115 */ 5116 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5117 5118 /** 5119 * Represent a chunk of CEA blocks sent to DMUB for parsing 5120 */ 5121 struct dmub_cmd_send_edid_cea { 5122 uint16_t offset; /**< offset into the CEA block */ 5123 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5124 uint16_t cea_total_length; /**< total length of the CEA block */ 5125 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5126 uint8_t pad[3]; /**< padding and for future expansion */ 5127 }; 5128 5129 /** 5130 * Result of VSDB parsing from CEA block 5131 */ 5132 struct dmub_cmd_edid_cea_amd_vsdb { 5133 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5134 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5135 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5136 uint16_t min_frame_rate; /**< Maximum frame rate */ 5137 uint16_t max_frame_rate; /**< Minimum frame rate */ 5138 }; 5139 5140 /** 5141 * Result of sending a CEA chunk 5142 */ 5143 struct dmub_cmd_edid_cea_ack { 5144 uint16_t offset; /**< offset of the chunk into the CEA block */ 5145 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5146 uint8_t pad; /**< padding and for future expansion */ 5147 }; 5148 5149 /** 5150 * Specify whether the result is an ACK/NACK or the parsing has finished 5151 */ 5152 enum dmub_cmd_edid_cea_reply_type { 5153 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5154 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5155 }; 5156 5157 /** 5158 * Definition of a DMUB_CMD__EDID_CEA command. 5159 */ 5160 struct dmub_rb_cmd_edid_cea { 5161 struct dmub_cmd_header header; /**< Command header */ 5162 union dmub_cmd_edid_cea_data { 5163 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5164 struct dmub_cmd_edid_cea_output { /**< output with results */ 5165 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5166 union { 5167 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5168 struct dmub_cmd_edid_cea_ack ack; 5169 }; 5170 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5171 } data; /**< Command data */ 5172 5173 }; 5174 5175 /** 5176 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5177 */ 5178 struct dmub_cmd_cable_id_input { 5179 uint8_t phy_inst; /**< phy inst for cable id data */ 5180 }; 5181 5182 /** 5183 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5184 */ 5185 struct dmub_cmd_cable_id_output { 5186 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5187 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5188 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5189 uint8_t RESERVED :2; /**< reserved means not defined */ 5190 }; 5191 5192 /** 5193 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5194 */ 5195 struct dmub_rb_cmd_get_usbc_cable_id { 5196 struct dmub_cmd_header header; /**< Command header */ 5197 /** 5198 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5199 */ 5200 union dmub_cmd_cable_id_data { 5201 struct dmub_cmd_cable_id_input input; /**< Input */ 5202 struct dmub_cmd_cable_id_output output; /**< Output */ 5203 uint8_t output_raw; /**< Raw data output */ 5204 } data; 5205 }; 5206 5207 /** 5208 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5209 */ 5210 enum dmub_cmd_secure_display_type { 5211 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5212 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5213 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5214 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5215 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5216 }; 5217 5218 #define MAX_ROI_NUM 2 5219 5220 struct dmub_cmd_roi_info { 5221 uint16_t x_start; 5222 uint16_t x_end; 5223 uint16_t y_start; 5224 uint16_t y_end; 5225 uint8_t otg_id; 5226 uint8_t phy_id; 5227 }; 5228 5229 struct dmub_cmd_roi_window_ctl { 5230 uint16_t x_start; 5231 uint16_t x_end; 5232 uint16_t y_start; 5233 uint16_t y_end; 5234 bool enable; 5235 }; 5236 5237 struct dmub_cmd_roi_ctl_info { 5238 uint8_t otg_id; 5239 uint8_t phy_id; 5240 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5241 }; 5242 5243 /** 5244 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5245 */ 5246 struct dmub_rb_cmd_secure_display { 5247 struct dmub_cmd_header header; 5248 /** 5249 * Data passed from driver to dmub firmware. 5250 */ 5251 struct dmub_cmd_roi_info roi_info; 5252 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5253 }; 5254 5255 /** 5256 * Command type of a DMUB_CMD__PSP command 5257 */ 5258 enum dmub_cmd_psp_type { 5259 DMUB_CMD__PSP_ASSR_ENABLE = 0 5260 }; 5261 5262 /** 5263 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5264 */ 5265 struct dmub_cmd_assr_enable_data { 5266 /** 5267 * ASSR enable or disable. 5268 */ 5269 uint8_t enable; 5270 /** 5271 * PHY port type. 5272 * Indicates eDP / non-eDP port type 5273 */ 5274 uint8_t phy_port_type; 5275 /** 5276 * PHY port ID. 5277 */ 5278 uint8_t phy_port_id; 5279 /** 5280 * Link encoder index. 5281 */ 5282 uint8_t link_enc_index; 5283 /** 5284 * HPO mode. 5285 */ 5286 uint8_t hpo_mode; 5287 5288 /** 5289 * Reserved field. 5290 */ 5291 uint8_t reserved[7]; 5292 }; 5293 5294 /** 5295 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5296 */ 5297 struct dmub_rb_cmd_assr_enable { 5298 /** 5299 * Command header. 5300 */ 5301 struct dmub_cmd_header header; 5302 5303 /** 5304 * Assr data. 5305 */ 5306 struct dmub_cmd_assr_enable_data assr_data; 5307 5308 /** 5309 * Reserved field. 5310 */ 5311 uint32_t reserved[3]; 5312 }; 5313 5314 /** 5315 * union dmub_rb_cmd - DMUB inbox command. 5316 */ 5317 union dmub_rb_cmd { 5318 /** 5319 * Elements shared with all commands. 5320 */ 5321 struct dmub_rb_cmd_common cmd_common; 5322 /** 5323 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5324 */ 5325 struct dmub_rb_cmd_read_modify_write read_modify_write; 5326 /** 5327 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5328 */ 5329 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5330 /** 5331 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5332 */ 5333 struct dmub_rb_cmd_burst_write burst_write; 5334 /** 5335 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5336 */ 5337 struct dmub_rb_cmd_reg_wait reg_wait; 5338 /** 5339 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5340 */ 5341 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5342 /** 5343 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5344 */ 5345 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5346 /** 5347 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5348 */ 5349 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5350 /** 5351 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5352 */ 5353 struct dmub_rb_cmd_dpphy_init dpphy_init; 5354 /** 5355 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5356 */ 5357 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5358 /** 5359 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5360 */ 5361 struct dmub_rb_cmd_domain_control domain_control; 5362 /** 5363 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5364 */ 5365 struct dmub_rb_cmd_psr_set_version psr_set_version; 5366 /** 5367 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5368 */ 5369 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5370 /** 5371 * Definition of a DMUB_CMD__PSR_ENABLE command. 5372 */ 5373 struct dmub_rb_cmd_psr_enable psr_enable; 5374 /** 5375 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5376 */ 5377 struct dmub_rb_cmd_psr_set_level psr_set_level; 5378 /** 5379 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5380 */ 5381 struct dmub_rb_cmd_psr_force_static psr_force_static; 5382 /** 5383 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5384 */ 5385 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5386 /** 5387 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5388 */ 5389 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5390 /** 5391 * Definition of a DMUB_CMD__HW_LOCK command. 5392 * Command is used by driver and FW. 5393 */ 5394 struct dmub_rb_cmd_lock_hw lock_hw; 5395 /** 5396 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5397 */ 5398 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5399 /** 5400 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5401 */ 5402 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5403 /** 5404 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5405 */ 5406 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5407 /** 5408 * Definition of a DMUB_CMD__MALL command. 5409 */ 5410 struct dmub_rb_cmd_mall mall; 5411 5412 /** 5413 * Definition of a DMUB_CMD__CAB command. 5414 */ 5415 struct dmub_rb_cmd_cab_for_ss cab; 5416 5417 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5418 5419 /** 5420 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5421 */ 5422 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5423 5424 /** 5425 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5426 */ 5427 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5428 5429 /** 5430 * Definition of DMUB_CMD__PANEL_CNTL commands. 5431 */ 5432 struct dmub_rb_cmd_panel_cntl panel_cntl; 5433 5434 /** 5435 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5436 */ 5437 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5438 5439 /** 5440 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5441 */ 5442 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5443 5444 /** 5445 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5446 */ 5447 struct dmub_rb_cmd_abm_set_level abm_set_level; 5448 5449 /** 5450 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5451 */ 5452 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5453 5454 /** 5455 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5456 */ 5457 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5458 5459 /** 5460 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5461 */ 5462 struct dmub_rb_cmd_abm_init_config abm_init_config; 5463 5464 /** 5465 * Definition of a DMUB_CMD__ABM_PAUSE command. 5466 */ 5467 struct dmub_rb_cmd_abm_pause abm_pause; 5468 5469 /** 5470 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5471 */ 5472 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5473 5474 /** 5475 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5476 */ 5477 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5478 5479 /** 5480 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5481 */ 5482 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5483 5484 /** 5485 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5486 */ 5487 struct dmub_rb_cmd_abm_set_event abm_set_event; 5488 5489 /** 5490 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5491 */ 5492 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5493 5494 /** 5495 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5496 */ 5497 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5498 5499 /** 5500 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5501 */ 5502 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5503 5504 /** 5505 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5506 */ 5507 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5508 struct dmub_rb_cmd_drr_update drr_update; 5509 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5510 5511 /** 5512 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5513 */ 5514 struct dmub_rb_cmd_lvtma_control lvtma_control; 5515 /** 5516 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5517 */ 5518 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5519 /** 5520 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5521 */ 5522 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5523 /** 5524 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5525 */ 5526 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5527 /** 5528 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5529 */ 5530 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 5531 /** 5532 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5533 */ 5534 struct dmub_rb_cmd_set_config_request set_config_request; 5535 /** 5536 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5537 */ 5538 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5539 /** 5540 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 5541 */ 5542 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 5543 /** 5544 * Definition of a DMUB_CMD__EDID_CEA command. 5545 */ 5546 struct dmub_rb_cmd_edid_cea edid_cea; 5547 /** 5548 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5549 */ 5550 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5551 5552 /** 5553 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5554 */ 5555 struct dmub_rb_cmd_query_hpd_state query_hpd; 5556 /** 5557 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5558 */ 5559 struct dmub_rb_cmd_secure_display secure_display; 5560 5561 /** 5562 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5563 */ 5564 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5565 /** 5566 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5567 */ 5568 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5569 /** 5570 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 5571 */ 5572 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 5573 /* 5574 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5575 */ 5576 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5577 /** 5578 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5579 */ 5580 struct dmub_rb_cmd_replay_enable replay_enable; 5581 /** 5582 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5583 */ 5584 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5585 /** 5586 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5587 */ 5588 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5589 /** 5590 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5591 */ 5592 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5593 5594 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5595 /** 5596 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5597 */ 5598 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5599 /** 5600 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5601 */ 5602 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5603 /** 5604 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5605 */ 5606 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5607 /** 5608 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5609 */ 5610 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5611 /** 5612 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5613 */ 5614 struct dmub_rb_cmd_assr_enable assr_enable; 5615 struct dmub_rb_cmd_fams2 fams2_config; 5616 5617 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5618 5619 struct dmub_rb_cmd_fams2_flip fams2_flip; 5620 }; 5621 5622 /** 5623 * union dmub_rb_out_cmd - Outbox command 5624 */ 5625 union dmub_rb_out_cmd { 5626 /** 5627 * Parameters common to every command. 5628 */ 5629 struct dmub_rb_cmd_common cmd_common; 5630 /** 5631 * AUX reply command. 5632 */ 5633 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5634 /** 5635 * HPD notify command. 5636 */ 5637 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5638 /** 5639 * SET_CONFIG reply command. 5640 */ 5641 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5642 /** 5643 * DPIA notification command. 5644 */ 5645 struct dmub_rb_cmd_dpia_notification dpia_notification; 5646 /** 5647 * HPD sense notification command. 5648 */ 5649 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5650 }; 5651 #pragma pack(pop) 5652 5653 5654 //============================================================================== 5655 //</DMUB_CMD>=================================================================== 5656 //============================================================================== 5657 //< DMUB_RB>==================================================================== 5658 //============================================================================== 5659 5660 /** 5661 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5662 */ 5663 struct dmub_rb_init_params { 5664 void *ctx; /**< Caller provided context pointer */ 5665 void *base_address; /**< CPU base address for ring's data */ 5666 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5667 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5668 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5669 }; 5670 5671 /** 5672 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5673 */ 5674 struct dmub_rb { 5675 void *base_address; /**< CPU address for the ring's data */ 5676 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5677 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5678 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5679 5680 void *ctx; /**< Caller provided context pointer */ 5681 void *dmub; /**< Pointer to the DMUB interface */ 5682 }; 5683 5684 /** 5685 * @brief Checks if the ringbuffer is empty. 5686 * 5687 * @param rb DMUB Ringbuffer 5688 * @return true if empty 5689 * @return false otherwise 5690 */ 5691 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5692 { 5693 return (rb->wrpt == rb->rptr); 5694 } 5695 5696 /** 5697 * @brief Checks if the ringbuffer is full 5698 * 5699 * @param rb DMUB Ringbuffer 5700 * @return true if full 5701 * @return false otherwise 5702 */ 5703 static inline bool dmub_rb_full(struct dmub_rb *rb) 5704 { 5705 uint32_t data_count; 5706 5707 if (rb->wrpt >= rb->rptr) 5708 data_count = rb->wrpt - rb->rptr; 5709 else 5710 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5711 5712 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5713 } 5714 5715 /** 5716 * @brief Pushes a command into the ringbuffer 5717 * 5718 * @param rb DMUB ringbuffer 5719 * @param cmd The command to push 5720 * @return true if the ringbuffer was not full 5721 * @return false otherwise 5722 */ 5723 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5724 const union dmub_rb_cmd *cmd) 5725 { 5726 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5727 const uint64_t *src = (const uint64_t *)cmd; 5728 uint8_t i; 5729 5730 if (dmub_rb_full(rb)) 5731 return false; 5732 5733 // copying data 5734 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5735 *dst++ = *src++; 5736 5737 rb->wrpt += DMUB_RB_CMD_SIZE; 5738 5739 if (rb->wrpt >= rb->capacity) 5740 rb->wrpt %= rb->capacity; 5741 5742 return true; 5743 } 5744 5745 /** 5746 * @brief Pushes a command into the DMUB outbox ringbuffer 5747 * 5748 * @param rb DMUB outbox ringbuffer 5749 * @param cmd Outbox command 5750 * @return true if not full 5751 * @return false otherwise 5752 */ 5753 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5754 const union dmub_rb_out_cmd *cmd) 5755 { 5756 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 5757 const uint8_t *src = (const uint8_t *)cmd; 5758 5759 if (dmub_rb_full(rb)) 5760 return false; 5761 5762 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 5763 5764 rb->wrpt += DMUB_RB_CMD_SIZE; 5765 5766 if (rb->wrpt >= rb->capacity) 5767 rb->wrpt %= rb->capacity; 5768 5769 return true; 5770 } 5771 5772 /** 5773 * @brief Returns the next unprocessed command in the ringbuffer. 5774 * 5775 * @param rb DMUB ringbuffer 5776 * @param cmd The command to return 5777 * @return true if not empty 5778 * @return false otherwise 5779 */ 5780 static inline bool dmub_rb_front(struct dmub_rb *rb, 5781 union dmub_rb_cmd **cmd) 5782 { 5783 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 5784 5785 if (dmub_rb_empty(rb)) 5786 return false; 5787 5788 *cmd = (union dmub_rb_cmd *)rb_cmd; 5789 5790 return true; 5791 } 5792 5793 /** 5794 * @brief Determines the next ringbuffer offset. 5795 * 5796 * @param rb DMUB inbox ringbuffer 5797 * @param num_cmds Number of commands 5798 * @param next_rptr The next offset in the ringbuffer 5799 */ 5800 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 5801 uint32_t num_cmds, 5802 uint32_t *next_rptr) 5803 { 5804 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 5805 5806 if (*next_rptr >= rb->capacity) 5807 *next_rptr %= rb->capacity; 5808 } 5809 5810 /** 5811 * @brief Returns a pointer to a command in the inbox. 5812 * 5813 * @param rb DMUB inbox ringbuffer 5814 * @param cmd The inbox command to return 5815 * @param rptr The ringbuffer offset 5816 * @return true if not empty 5817 * @return false otherwise 5818 */ 5819 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 5820 union dmub_rb_cmd **cmd, 5821 uint32_t rptr) 5822 { 5823 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 5824 5825 if (dmub_rb_empty(rb)) 5826 return false; 5827 5828 *cmd = (union dmub_rb_cmd *)rb_cmd; 5829 5830 return true; 5831 } 5832 5833 /** 5834 * @brief Returns the next unprocessed command in the outbox. 5835 * 5836 * @param rb DMUB outbox ringbuffer 5837 * @param cmd The outbox command to return 5838 * @return true if not empty 5839 * @return false otherwise 5840 */ 5841 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 5842 union dmub_rb_out_cmd *cmd) 5843 { 5844 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 5845 uint64_t *dst = (uint64_t *)cmd; 5846 uint8_t i; 5847 5848 if (dmub_rb_empty(rb)) 5849 return false; 5850 5851 // copying data 5852 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5853 *dst++ = *src++; 5854 5855 return true; 5856 } 5857 5858 /** 5859 * @brief Removes the front entry in the ringbuffer. 5860 * 5861 * @param rb DMUB ringbuffer 5862 * @return true if the command was removed 5863 * @return false if there were no commands 5864 */ 5865 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 5866 { 5867 if (dmub_rb_empty(rb)) 5868 return false; 5869 5870 rb->rptr += DMUB_RB_CMD_SIZE; 5871 5872 if (rb->rptr >= rb->capacity) 5873 rb->rptr %= rb->capacity; 5874 5875 return true; 5876 } 5877 5878 /** 5879 * @brief Flushes commands in the ringbuffer to framebuffer memory. 5880 * 5881 * Avoids a race condition where DMCUB accesses memory while 5882 * there are still writes in flight to framebuffer. 5883 * 5884 * @param rb DMUB ringbuffer 5885 */ 5886 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 5887 { 5888 uint32_t rptr = rb->rptr; 5889 uint32_t wptr = rb->wrpt; 5890 5891 while (rptr != wptr) { 5892 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 5893 uint8_t i; 5894 5895 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5896 (void)READ_ONCE(*data++); 5897 5898 rptr += DMUB_RB_CMD_SIZE; 5899 if (rptr >= rb->capacity) 5900 rptr %= rb->capacity; 5901 } 5902 } 5903 5904 /** 5905 * @brief Initializes a DMCUB ringbuffer 5906 * 5907 * @param rb DMUB ringbuffer 5908 * @param init_params initial configuration for the ringbuffer 5909 */ 5910 static inline void dmub_rb_init(struct dmub_rb *rb, 5911 struct dmub_rb_init_params *init_params) 5912 { 5913 rb->base_address = init_params->base_address; 5914 rb->capacity = init_params->capacity; 5915 rb->rptr = init_params->read_ptr; 5916 rb->wrpt = init_params->write_ptr; 5917 } 5918 5919 /** 5920 * @brief Copies output data from in/out commands into the given command. 5921 * 5922 * @param rb DMUB ringbuffer 5923 * @param cmd Command to copy data into 5924 */ 5925 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5926 union dmub_rb_cmd *cmd) 5927 { 5928 // Copy rb entry back into command 5929 uint8_t *rd_ptr = (rb->rptr == 0) ? 5930 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5931 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5932 5933 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5934 } 5935 5936 //============================================================================== 5937 //</DMUB_RB>==================================================================== 5938 //============================================================================== 5939 #endif /* _DMUB_CMD_H_ */ 5940