1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic udelay 165 */ 166 #ifndef dmub_udelay 167 #define dmub_udelay(microseconds) udelay(microseconds) 168 #endif 169 170 #pragma pack(push, 1) 171 #define ABM_NUM_OF_ACE_SEGMENTS 5 172 173 union abm_flags { 174 struct { 175 /** 176 * @abm_enabled: Indicates if ABM is enabled. 177 */ 178 unsigned int abm_enabled : 1; 179 180 /** 181 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 182 */ 183 unsigned int disable_abm_requested : 1; 184 185 /** 186 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 187 */ 188 unsigned int disable_abm_immediately : 1; 189 190 /** 191 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 192 * to be disabled immediately and keep gain. 193 */ 194 unsigned int disable_abm_immediate_keep_gain : 1; 195 196 /** 197 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 198 */ 199 unsigned int fractional_pwm : 1; 200 201 /** 202 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 203 * of user backlight level. 204 */ 205 unsigned int abm_gradual_bl_change : 1; 206 207 /** 208 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 209 */ 210 unsigned int abm_new_frame : 1; 211 } bitfields; 212 213 unsigned int u32All; 214 }; 215 216 struct abm_save_restore { 217 /** 218 * @flags: Misc. ABM flags. 219 */ 220 union abm_flags flags; 221 222 /** 223 * @pause: true: pause ABM and get state 224 * false: unpause ABM after setting state 225 */ 226 uint32_t pause; 227 228 /** 229 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 230 */ 231 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 232 233 /** 234 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 235 */ 236 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 237 238 /** 239 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 240 */ 241 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 242 243 244 /** 245 * @knee_threshold: Current x-position of ACE knee (u0.16). 246 */ 247 uint32_t knee_threshold; 248 /** 249 * @current_gain: Current backlight reduction (u16.16). 250 */ 251 uint32_t current_gain; 252 /** 253 * @curr_bl_level: Current actual backlight level converging to target backlight level. 254 */ 255 uint16_t curr_bl_level; 256 257 /** 258 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 259 */ 260 uint16_t curr_user_bl_level; 261 262 }; 263 264 /** 265 * union dmub_addr - DMUB physical/virtual 64-bit address. 266 */ 267 union dmub_addr { 268 struct { 269 uint32_t low_part; /**< Lower 32 bits */ 270 uint32_t high_part; /**< Upper 32 bits */ 271 } u; /*<< Low/high bit access */ 272 uint64_t quad_part; /*<< 64 bit address */ 273 }; 274 #pragma pack(pop) 275 276 /** 277 * Dirty rect definition. 278 */ 279 struct dmub_rect { 280 /** 281 * Dirty rect x offset. 282 */ 283 uint32_t x; 284 285 /** 286 * Dirty rect y offset. 287 */ 288 uint32_t y; 289 290 /** 291 * Dirty rect width. 292 */ 293 uint32_t width; 294 295 /** 296 * Dirty rect height. 297 */ 298 uint32_t height; 299 }; 300 301 /** 302 * Flags that can be set by driver to change some PSR behaviour. 303 */ 304 union dmub_psr_debug_flags { 305 /** 306 * Debug flags. 307 */ 308 struct { 309 /** 310 * Enable visual confirm in FW. 311 */ 312 uint32_t visual_confirm : 1; 313 314 /** 315 * Force all selective updates to bw full frame updates. 316 */ 317 uint32_t force_full_frame_update : 1; 318 319 /** 320 * Use HW Lock Mgr object to do HW locking in FW. 321 */ 322 uint32_t use_hw_lock_mgr : 1; 323 324 /** 325 * Use TPS3 signal when restore main link. 326 */ 327 uint32_t force_wakeup_by_tps3 : 1; 328 329 /** 330 * Back to back flip, therefore cannot power down PHY 331 */ 332 uint32_t back_to_back_flip : 1; 333 334 } bitfields; 335 336 /** 337 * Union for debug flags. 338 */ 339 uint32_t u32All; 340 }; 341 342 /** 343 * Flags that can be set by driver to change some Replay behaviour. 344 */ 345 union replay_debug_flags { 346 struct { 347 /** 348 * 0x1 (bit 0) 349 * Enable visual confirm in FW. 350 */ 351 uint32_t visual_confirm : 1; 352 353 /** 354 * 0x2 (bit 1) 355 * @skip_crc: Set if need to skip CRC. 356 */ 357 uint32_t skip_crc : 1; 358 359 /** 360 * 0x4 (bit 2) 361 * @force_link_power_on: Force disable ALPM control 362 */ 363 uint32_t force_link_power_on : 1; 364 365 /** 366 * 0x8 (bit 3) 367 * @force_phy_power_on: Force phy power on 368 */ 369 uint32_t force_phy_power_on : 1; 370 371 /** 372 * 0x10 (bit 4) 373 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 374 */ 375 uint32_t timing_resync_disabled : 1; 376 377 /** 378 * 0x20 (bit 5) 379 * @skip_crtc_disabled: CRTC disable skipped 380 */ 381 uint32_t skip_crtc_disabled : 1; 382 383 /** 384 * 0x40 (bit 6) 385 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 386 */ 387 uint32_t force_defer_one_frame_update : 1; 388 389 /** 390 * 0x80 (bit 7) 391 * @disable_delay_alpm_on: Force disable delay alpm on 392 */ 393 uint32_t disable_delay_alpm_on : 1; 394 395 /** 396 * 0x100 (bit 8) 397 * @disable_desync_error_check: Force disable desync error check 398 */ 399 uint32_t disable_desync_error_check : 1; 400 401 /** 402 * 0x200 (bit 9) 403 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 404 */ 405 uint32_t force_self_update_when_abm_non_steady : 1; 406 407 /** 408 * 0x400 (bit 10) 409 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 410 * If we enter IPS2, the Visual confirm bar will change to yellow 411 */ 412 uint32_t enable_ips_visual_confirm : 1; 413 414 /** 415 * 0x800 (bit 11) 416 * @enable_ips_residency_profiling: Enable IPS residency profiling 417 */ 418 uint32_t enable_ips_residency_profiling : 1; 419 420 uint32_t reserved : 20; 421 } bitfields; 422 423 uint32_t u32All; 424 }; 425 426 union replay_hw_flags { 427 struct { 428 /** 429 * @allow_alpm_fw_standby_mode: To indicate whether the 430 * ALPM FW standby mode is allowed 431 */ 432 uint32_t allow_alpm_fw_standby_mode : 1; 433 434 /* 435 * @dsc_enable_status: DSC enable status in driver 436 */ 437 uint32_t dsc_enable_status : 1; 438 439 /** 440 * @fec_enable_status: receive fec enable/disable status from driver 441 */ 442 uint32_t fec_enable_status : 1; 443 444 /* 445 * @smu_optimizations_en: SMU power optimization. 446 * Only when active display is Replay capable and display enters Replay. 447 * Trigger interrupt to SMU to powerup/down. 448 */ 449 uint32_t smu_optimizations_en : 1; 450 451 /** 452 * @phy_power_state: Indicates current phy power state 453 */ 454 uint32_t phy_power_state : 1; 455 456 /** 457 * @link_power_state: Indicates current link power state 458 */ 459 uint32_t link_power_state : 1; 460 /** 461 * Use TPS3 signal when restore main link. 462 */ 463 uint32_t force_wakeup_by_tps3 : 1; 464 } bitfields; 465 466 uint32_t u32All; 467 }; 468 469 /** 470 * DMUB feature capabilities. 471 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 472 */ 473 struct dmub_feature_caps { 474 /** 475 * Max PSR version supported by FW. 476 */ 477 uint8_t psr; 478 uint8_t fw_assisted_mclk_switch_ver; 479 uint8_t reserved[4]; 480 uint8_t subvp_psr_support; 481 uint8_t gecc_enable; 482 uint8_t replay_supported; 483 uint8_t replay_reserved[3]; 484 }; 485 486 struct dmub_visual_confirm_color { 487 /** 488 * Maximum 10 bits color value 489 */ 490 uint16_t color_r_cr; 491 uint16_t color_g_y; 492 uint16_t color_b_cb; 493 uint16_t panel_inst; 494 }; 495 496 //============================================================================== 497 //</DMUB_TYPES>================================================================= 498 //============================================================================== 499 //< DMUB_META>================================================================== 500 //============================================================================== 501 #pragma pack(push, 1) 502 503 /* Magic value for identifying dmub_fw_meta_info */ 504 #define DMUB_FW_META_MAGIC 0x444D5542 505 506 /* Offset from the end of the file to the dmub_fw_meta_info */ 507 #define DMUB_FW_META_OFFSET 0x24 508 509 /** 510 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 511 */ 512 union dmub_fw_meta_feature_bits { 513 struct { 514 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 515 uint32_t reserved : 31; 516 } bits; /**< status bits */ 517 uint32_t all; /**< 32-bit access to status bits */ 518 }; 519 520 /** 521 * struct dmub_fw_meta_info - metadata associated with fw binary 522 * 523 * NOTE: This should be considered a stable API. Fields should 524 * not be repurposed or reordered. New fields should be 525 * added instead to extend the structure. 526 * 527 * @magic_value: magic value identifying DMUB firmware meta info 528 * @fw_region_size: size of the firmware state region 529 * @trace_buffer_size: size of the tracebuffer region 530 * @fw_version: the firmware version information 531 * @dal_fw: 1 if the firmware is DAL 532 * @shared_state_size: size of the shared state region in bytes 533 * @shared_state_features: number of shared state features 534 */ 535 struct dmub_fw_meta_info { 536 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 537 uint32_t fw_region_size; /**< size of the firmware state region */ 538 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 539 uint32_t fw_version; /**< the firmware version information */ 540 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 541 uint8_t reserved[3]; /**< padding bits */ 542 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 543 uint16_t shared_state_features; /**< number of shared state features */ 544 uint16_t reserved2; /**< padding bytes */ 545 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 546 }; 547 548 /** 549 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 550 */ 551 union dmub_fw_meta { 552 struct dmub_fw_meta_info info; /**< metadata info */ 553 uint8_t reserved[64]; /**< padding bits */ 554 }; 555 556 #pragma pack(pop) 557 558 //============================================================================== 559 //< DMUB Trace Buffer>================================================================ 560 //============================================================================== 561 /** 562 * dmub_trace_code_t - firmware trace code, 32-bits 563 */ 564 typedef uint32_t dmub_trace_code_t; 565 566 /** 567 * struct dmcub_trace_buf_entry - Firmware trace entry 568 */ 569 struct dmcub_trace_buf_entry { 570 dmub_trace_code_t trace_code; /**< trace code for the event */ 571 uint32_t tick_count; /**< the tick count at time of trace */ 572 uint32_t param0; /**< trace defined parameter 0 */ 573 uint32_t param1; /**< trace defined parameter 1 */ 574 }; 575 576 //============================================================================== 577 //< DMUB_STATUS>================================================================ 578 //============================================================================== 579 580 /** 581 * DMCUB scratch registers can be used to determine firmware status. 582 * Current scratch register usage is as follows: 583 * 584 * SCRATCH0: FW Boot Status register 585 * SCRATCH5: LVTMA Status Register 586 * SCRATCH15: FW Boot Options register 587 */ 588 589 /** 590 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 591 */ 592 union dmub_fw_boot_status { 593 struct { 594 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 595 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 596 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 597 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 598 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 599 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 600 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 601 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 602 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 603 } bits; /**< status bits */ 604 uint32_t all; /**< 32-bit access to status bits */ 605 }; 606 607 /** 608 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 609 */ 610 enum dmub_fw_boot_status_bit { 611 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 612 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 613 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 614 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 615 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 616 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 617 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 618 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 619 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 620 }; 621 622 /* Register bit definition for SCRATCH5 */ 623 union dmub_lvtma_status { 624 struct { 625 uint32_t psp_ok : 1; 626 uint32_t edp_on : 1; 627 uint32_t reserved : 30; 628 } bits; 629 uint32_t all; 630 }; 631 632 enum dmub_lvtma_status_bit { 633 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 634 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 635 }; 636 637 enum dmub_ips_disable_type { 638 DMUB_IPS_ENABLE = 0, 639 DMUB_IPS_DISABLE_ALL = 1, 640 DMUB_IPS_DISABLE_IPS1 = 2, 641 DMUB_IPS_DISABLE_IPS2 = 3, 642 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 643 DMUB_IPS_DISABLE_DYNAMIC = 5, 644 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 645 }; 646 647 #define DMUB_IPS1_ALLOW_MASK 0x00000001 648 #define DMUB_IPS2_ALLOW_MASK 0x00000002 649 #define DMUB_IPS1_COMMIT_MASK 0x00000004 650 #define DMUB_IPS2_COMMIT_MASK 0x00000008 651 652 /** 653 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 654 */ 655 union dmub_fw_boot_options { 656 struct { 657 uint32_t pemu_env : 1; /**< 1 if PEMU */ 658 uint32_t fpga_env : 1; /**< 1 if FPGA */ 659 uint32_t optimized_init : 1; /**< 1 if optimized init */ 660 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 661 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 662 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 663 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 664 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 665 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 666 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 667 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 668 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 669 uint32_t power_optimization: 1; 670 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 671 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 672 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 673 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 674 uint32_t reserved0: 1; 675 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 676 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 677 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 678 uint32_t ips_disable: 3; /* options to disable ips support*/ 679 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 680 uint32_t reserved : 8; /**< reserved */ 681 } bits; /**< boot bits */ 682 uint32_t all; /**< 32-bit access to bits */ 683 }; 684 685 enum dmub_fw_boot_options_bit { 686 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 687 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 688 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 689 }; 690 691 //============================================================================== 692 //< DMUB_SHARED_STATE>========================================================== 693 //============================================================================== 694 695 /** 696 * Shared firmware state between driver and firmware for lockless communication 697 * in situations where the inbox/outbox may be unavailable. 698 * 699 * Each structure *must* be at most 256-bytes in size. The layout allocation is 700 * described below: 701 * 702 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 703 */ 704 705 /** 706 * enum dmub_shared_state_feature_id - List of shared state features. 707 */ 708 enum dmub_shared_state_feature_id { 709 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 710 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 711 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 712 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 713 }; 714 715 /** 716 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 717 */ 718 union dmub_shared_state_ips_fw_signals { 719 struct { 720 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 721 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 722 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 723 uint32_t detection_required : 1; /**< 1 if detection is required */ 724 uint32_t reserved_bits : 28; /**< Reversed */ 725 } bits; 726 uint32_t all; 727 }; 728 729 /** 730 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 731 */ 732 union dmub_shared_state_ips_driver_signals { 733 struct { 734 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 735 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 736 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 737 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 738 uint32_t reserved_bits : 28; /**< Reversed bits */ 739 } bits; 740 uint32_t all; 741 }; 742 743 /** 744 * IPS FW Version 745 */ 746 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 747 748 /** 749 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 750 */ 751 struct dmub_shared_state_ips_fw { 752 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 753 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 754 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 755 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 756 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 757 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 758 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 759 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 760 }; /* 248-bytes, fixed */ 761 762 /** 763 * IPS Driver Version 764 */ 765 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 766 767 /** 768 * struct dmub_shared_state_ips_driver - Driver state for IPS. 769 */ 770 struct dmub_shared_state_ips_driver { 771 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 772 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 773 }; /* 248-bytes, fixed */ 774 775 /** 776 * enum dmub_shared_state_feature_common - Generic payload. 777 */ 778 struct dmub_shared_state_feature_common { 779 uint32_t padding[62]; 780 }; /* 248-bytes, fixed */ 781 782 /** 783 * enum dmub_shared_state_feature_header - Feature description. 784 */ 785 struct dmub_shared_state_feature_header { 786 uint16_t id; /**< Feature ID */ 787 uint16_t version; /**< Feature version */ 788 uint32_t reserved; /**< Reserved bytes. */ 789 }; /* 8 bytes, fixed */ 790 791 /** 792 * struct dmub_shared_state_feature_block - Feature block. 793 */ 794 struct dmub_shared_state_feature_block { 795 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 796 union dmub_shared_feature_state_union { 797 struct dmub_shared_state_feature_common common; /**< Generic data */ 798 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 799 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 800 } data; /**< Shared state data. */ 801 }; /* 256-bytes, fixed */ 802 803 /** 804 * Shared state size in bytes. 805 */ 806 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 807 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 808 809 //============================================================================== 810 //</DMUB_STATUS>================================================================ 811 //============================================================================== 812 //< DMUB_VBIOS>================================================================= 813 //============================================================================== 814 815 /* 816 * enum dmub_cmd_vbios_type - VBIOS commands. 817 * 818 * Command IDs should be treated as stable ABI. 819 * Do not reuse or modify IDs. 820 */ 821 enum dmub_cmd_vbios_type { 822 /** 823 * Configures the DIG encoder. 824 */ 825 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 826 /** 827 * Controls the PHY. 828 */ 829 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 830 /** 831 * Sets the pixel clock/symbol clock. 832 */ 833 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 834 /** 835 * Enables or disables power gating. 836 */ 837 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 838 /** 839 * Controls embedded panels. 840 */ 841 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 842 /** 843 * Query DP alt status on a transmitter. 844 */ 845 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 846 /** 847 * Control PHY FSM 848 */ 849 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 850 /** 851 * Controls domain power gating 852 */ 853 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 854 }; 855 856 //============================================================================== 857 //</DMUB_VBIOS>================================================================= 858 //============================================================================== 859 //< DMUB_GPINT>================================================================= 860 //============================================================================== 861 862 /** 863 * The shifts and masks below may alternatively be used to format and read 864 * the command register bits. 865 */ 866 867 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 868 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 869 870 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 871 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 872 873 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 874 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 875 876 /** 877 * Command responses. 878 */ 879 880 /** 881 * Return response for DMUB_GPINT__STOP_FW command. 882 */ 883 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 884 885 /** 886 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 887 */ 888 union dmub_gpint_data_register { 889 struct { 890 uint32_t param : 16; /**< 16-bit parameter */ 891 uint32_t command_code : 12; /**< GPINT command */ 892 uint32_t status : 4; /**< Command status bit */ 893 } bits; /**< GPINT bit access */ 894 uint32_t all; /**< GPINT 32-bit access */ 895 }; 896 897 /* 898 * enum dmub_gpint_command - GPINT command to DMCUB FW 899 * 900 * Command IDs should be treated as stable ABI. 901 * Do not reuse or modify IDs. 902 */ 903 enum dmub_gpint_command { 904 /** 905 * Invalid command, ignored. 906 */ 907 DMUB_GPINT__INVALID_COMMAND = 0, 908 /** 909 * DESC: Queries the firmware version. 910 * RETURN: Firmware version. 911 */ 912 DMUB_GPINT__GET_FW_VERSION = 1, 913 /** 914 * DESC: Halts the firmware. 915 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 916 */ 917 DMUB_GPINT__STOP_FW = 2, 918 /** 919 * DESC: Get PSR state from FW. 920 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 921 */ 922 DMUB_GPINT__GET_PSR_STATE = 7, 923 /** 924 * DESC: Notifies DMCUB of the currently active streams. 925 * ARGS: Stream mask, 1 bit per active stream index. 926 */ 927 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 928 /** 929 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 930 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 931 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 932 * RETURN: PSR residency in milli-percent. 933 */ 934 DMUB_GPINT__PSR_RESIDENCY = 9, 935 936 /** 937 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 938 */ 939 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 940 941 /** 942 * DESC: Get REPLAY state from FW. 943 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 944 */ 945 DMUB_GPINT__GET_REPLAY_STATE = 13, 946 947 /** 948 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 949 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 950 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 951 * RETURN: REPLAY residency in milli-percent. 952 */ 953 DMUB_GPINT__REPLAY_RESIDENCY = 14, 954 955 /** 956 * DESC: Updates the trace buffer lower 32-bit mask. 957 * ARGS: The new mask 958 * RETURN: Lower 32-bit mask. 959 */ 960 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 961 962 /** 963 * DESC: Updates the trace buffer mask bit0~bit15. 964 * ARGS: The new mask 965 * RETURN: Lower 32-bit mask. 966 */ 967 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 968 969 /** 970 * DESC: Updates the trace buffer mask bit16~bit31. 971 * ARGS: The new mask 972 * RETURN: Lower 32-bit mask. 973 */ 974 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 975 976 /** 977 * DESC: Updates the trace buffer mask bit32~bit47. 978 * ARGS: The new mask 979 * RETURN: Lower 32-bit mask. 980 */ 981 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 982 983 /** 984 * DESC: Updates the trace buffer mask bit48~bit63. 985 * ARGS: The new mask 986 * RETURN: Lower 32-bit mask. 987 */ 988 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 989 990 /** 991 * DESC: Read the trace buffer mask bi0~bit15. 992 */ 993 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 994 995 /** 996 * DESC: Read the trace buffer mask bit16~bit31. 997 */ 998 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 999 1000 /** 1001 * DESC: Read the trace buffer mask bi32~bit47. 1002 */ 1003 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1004 1005 /** 1006 * DESC: Updates the trace buffer mask bit32~bit63. 1007 */ 1008 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1009 1010 /** 1011 * DESC: Enable measurements for various task duration 1012 * ARGS: 0 - Disable measurement 1013 * 1 - Enable measurement 1014 */ 1015 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1016 }; 1017 1018 /** 1019 * INBOX0 generic command definition 1020 */ 1021 union dmub_inbox0_cmd_common { 1022 struct { 1023 uint32_t command_code: 8; /**< INBOX0 command code */ 1024 uint32_t param: 24; /**< 24-bit parameter */ 1025 } bits; 1026 uint32_t all; 1027 }; 1028 1029 /** 1030 * INBOX0 hw_lock command definition 1031 */ 1032 union dmub_inbox0_cmd_lock_hw { 1033 struct { 1034 uint32_t command_code: 8; 1035 1036 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1037 uint32_t hw_lock_client: 2; 1038 1039 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1040 uint32_t otg_inst: 3; 1041 uint32_t opp_inst: 3; 1042 uint32_t dig_inst: 3; 1043 1044 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1045 uint32_t lock_pipe: 1; 1046 uint32_t lock_cursor: 1; 1047 uint32_t lock_dig: 1; 1048 uint32_t triple_buffer_lock: 1; 1049 1050 uint32_t lock: 1; /**< Lock */ 1051 uint32_t should_release: 1; /**< Release */ 1052 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1053 } bits; 1054 uint32_t all; 1055 }; 1056 1057 union dmub_inbox0_data_register { 1058 union dmub_inbox0_cmd_common inbox0_cmd_common; 1059 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1060 }; 1061 1062 enum dmub_inbox0_command { 1063 /** 1064 * DESC: Invalid command, ignored. 1065 */ 1066 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1067 /** 1068 * DESC: Notification to acquire/release HW lock 1069 * ARGS: 1070 */ 1071 DMUB_INBOX0_CMD__HW_LOCK = 1, 1072 }; 1073 //============================================================================== 1074 //</DMUB_GPINT>================================================================= 1075 //============================================================================== 1076 //< DMUB_CMD>=================================================================== 1077 //============================================================================== 1078 1079 /** 1080 * Size in bytes of each DMUB command. 1081 */ 1082 #define DMUB_RB_CMD_SIZE 64 1083 1084 /** 1085 * Maximum number of items in the DMUB ringbuffer. 1086 */ 1087 #define DMUB_RB_MAX_ENTRY 128 1088 1089 /** 1090 * Ringbuffer size in bytes. 1091 */ 1092 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1093 1094 /** 1095 * REG_SET mask for reg offload. 1096 */ 1097 #define REG_SET_MASK 0xFFFF 1098 1099 /* 1100 * enum dmub_cmd_type - DMUB inbox command. 1101 * 1102 * Command IDs should be treated as stable ABI. 1103 * Do not reuse or modify IDs. 1104 */ 1105 enum dmub_cmd_type { 1106 /** 1107 * Invalid command. 1108 */ 1109 DMUB_CMD__NULL = 0, 1110 /** 1111 * Read modify write register sequence offload. 1112 */ 1113 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1114 /** 1115 * Field update register sequence offload. 1116 */ 1117 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1118 /** 1119 * Burst write sequence offload. 1120 */ 1121 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1122 /** 1123 * Reg wait sequence offload. 1124 */ 1125 DMUB_CMD__REG_REG_WAIT = 4, 1126 /** 1127 * Workaround to avoid HUBP underflow during NV12 playback. 1128 */ 1129 DMUB_CMD__PLAT_54186_WA = 5, 1130 /** 1131 * Command type used to query FW feature caps. 1132 */ 1133 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1134 /** 1135 * Command type used to get visual confirm color. 1136 */ 1137 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1138 /** 1139 * Command type used for all PSR commands. 1140 */ 1141 DMUB_CMD__PSR = 64, 1142 /** 1143 * Command type used for all MALL commands. 1144 */ 1145 DMUB_CMD__MALL = 65, 1146 /** 1147 * Command type used for all ABM commands. 1148 */ 1149 DMUB_CMD__ABM = 66, 1150 /** 1151 * Command type used to update dirty rects in FW. 1152 */ 1153 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1154 /** 1155 * Command type used to update cursor info in FW. 1156 */ 1157 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1158 /** 1159 * Command type used for HW locking in FW. 1160 */ 1161 DMUB_CMD__HW_LOCK = 69, 1162 /** 1163 * Command type used to access DP AUX. 1164 */ 1165 DMUB_CMD__DP_AUX_ACCESS = 70, 1166 /** 1167 * Command type used for OUTBOX1 notification enable 1168 */ 1169 DMUB_CMD__OUTBOX1_ENABLE = 71, 1170 1171 /** 1172 * Command type used for all idle optimization commands. 1173 */ 1174 DMUB_CMD__IDLE_OPT = 72, 1175 /** 1176 * Command type used for all clock manager commands. 1177 */ 1178 DMUB_CMD__CLK_MGR = 73, 1179 /** 1180 * Command type used for all panel control commands. 1181 */ 1182 DMUB_CMD__PANEL_CNTL = 74, 1183 1184 /** 1185 * Command type used for all CAB commands. 1186 */ 1187 DMUB_CMD__CAB_FOR_SS = 75, 1188 1189 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1190 1191 /** 1192 * Command type used for interfacing with DPIA. 1193 */ 1194 DMUB_CMD__DPIA = 77, 1195 /** 1196 * Command type used for EDID CEA parsing 1197 */ 1198 DMUB_CMD__EDID_CEA = 79, 1199 /** 1200 * Command type used for getting usbc cable ID 1201 */ 1202 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1203 /** 1204 * Command type used to query HPD state. 1205 */ 1206 DMUB_CMD__QUERY_HPD_STATE = 82, 1207 /** 1208 * Command type used for all VBIOS interface commands. 1209 */ 1210 /** 1211 * Command type used for all REPLAY commands. 1212 */ 1213 DMUB_CMD__REPLAY = 83, 1214 1215 /** 1216 * Command type used for all SECURE_DISPLAY commands. 1217 */ 1218 DMUB_CMD__SECURE_DISPLAY = 85, 1219 1220 /** 1221 * Command type used to set DPIA HPD interrupt state 1222 */ 1223 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1224 1225 /** 1226 * Command type used for all PSP commands. 1227 */ 1228 DMUB_CMD__PSP = 88, 1229 1230 DMUB_CMD__VBIOS = 128, 1231 }; 1232 1233 /** 1234 * enum dmub_out_cmd_type - DMUB outbox commands. 1235 */ 1236 enum dmub_out_cmd_type { 1237 /** 1238 * Invalid outbox command, ignored. 1239 */ 1240 DMUB_OUT_CMD__NULL = 0, 1241 /** 1242 * Command type used for DP AUX Reply data notification 1243 */ 1244 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1245 /** 1246 * Command type used for DP HPD event notification 1247 */ 1248 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1249 /** 1250 * Command type used for SET_CONFIG Reply notification 1251 */ 1252 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1253 /** 1254 * Command type used for USB4 DPIA notification 1255 */ 1256 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1257 }; 1258 1259 /* DMUB_CMD__DPIA command sub-types. */ 1260 enum dmub_cmd_dpia_type { 1261 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1262 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1263 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1264 }; 1265 1266 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1267 enum dmub_cmd_dpia_notification_type { 1268 DPIA_NOTIFY__BW_ALLOCATION = 0, 1269 }; 1270 1271 #pragma pack(push, 1) 1272 1273 /** 1274 * struct dmub_cmd_header - Common command header fields. 1275 */ 1276 struct dmub_cmd_header { 1277 unsigned int type : 8; /**< command type */ 1278 unsigned int sub_type : 8; /**< command sub type */ 1279 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1280 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1281 unsigned int reserved0 : 6; /**< reserved bits */ 1282 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1283 unsigned int reserved1 : 2; /**< reserved bits */ 1284 }; 1285 1286 /* 1287 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1288 * 1289 * 60 payload bytes can hold up to 5 sets of read modify writes, 1290 * each take 3 dwords. 1291 * 1292 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1293 * 1294 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1295 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1296 */ 1297 struct dmub_cmd_read_modify_write_sequence { 1298 uint32_t addr; /**< register address */ 1299 uint32_t modify_mask; /**< modify mask */ 1300 uint32_t modify_value; /**< modify value */ 1301 }; 1302 1303 /** 1304 * Maximum number of ops in read modify write sequence. 1305 */ 1306 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1307 1308 /** 1309 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1310 */ 1311 struct dmub_rb_cmd_read_modify_write { 1312 struct dmub_cmd_header header; /**< command header */ 1313 /** 1314 * Read modify write sequence. 1315 */ 1316 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1317 }; 1318 1319 /* 1320 * Update a register with specified masks and values sequeunce 1321 * 1322 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1323 * 1324 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1325 * 1326 * 1327 * USE CASE: 1328 * 1. auto-increment register where additional read would update pointer and produce wrong result 1329 * 2. toggle a bit without read in the middle 1330 */ 1331 1332 struct dmub_cmd_reg_field_update_sequence { 1333 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1334 uint32_t modify_value; /**< value to update with */ 1335 }; 1336 1337 /** 1338 * Maximum number of ops in field update sequence. 1339 */ 1340 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1341 1342 /** 1343 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1344 */ 1345 struct dmub_rb_cmd_reg_field_update_sequence { 1346 struct dmub_cmd_header header; /**< command header */ 1347 uint32_t addr; /**< register address */ 1348 /** 1349 * Field update sequence. 1350 */ 1351 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1352 }; 1353 1354 1355 /** 1356 * Maximum number of burst write values. 1357 */ 1358 #define DMUB_BURST_WRITE_VALUES__MAX 14 1359 1360 /* 1361 * struct dmub_rb_cmd_burst_write - Burst write 1362 * 1363 * support use case such as writing out LUTs. 1364 * 1365 * 60 payload bytes can hold up to 14 values to write to given address 1366 * 1367 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1368 */ 1369 struct dmub_rb_cmd_burst_write { 1370 struct dmub_cmd_header header; /**< command header */ 1371 uint32_t addr; /**< register start address */ 1372 /** 1373 * Burst write register values. 1374 */ 1375 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1376 }; 1377 1378 /** 1379 * struct dmub_rb_cmd_common - Common command header 1380 */ 1381 struct dmub_rb_cmd_common { 1382 struct dmub_cmd_header header; /**< command header */ 1383 /** 1384 * Padding to RB_CMD_SIZE 1385 */ 1386 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1387 }; 1388 1389 /** 1390 * struct dmub_cmd_reg_wait_data - Register wait data 1391 */ 1392 struct dmub_cmd_reg_wait_data { 1393 uint32_t addr; /**< Register address */ 1394 uint32_t mask; /**< Mask for register bits */ 1395 uint32_t condition_field_value; /**< Value to wait for */ 1396 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1397 }; 1398 1399 /** 1400 * struct dmub_rb_cmd_reg_wait - Register wait command 1401 */ 1402 struct dmub_rb_cmd_reg_wait { 1403 struct dmub_cmd_header header; /**< Command header */ 1404 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1405 }; 1406 1407 /** 1408 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1409 * 1410 * Reprograms surface parameters to avoid underflow. 1411 */ 1412 struct dmub_cmd_PLAT_54186_wa { 1413 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1414 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1415 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1416 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1417 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1418 struct { 1419 uint32_t hubp_inst : 4; /**< HUBP instance */ 1420 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1421 uint32_t immediate :1; /**< Immediate flip */ 1422 uint32_t vmid : 4; /**< VMID */ 1423 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1424 uint32_t reserved : 21; /**< Reserved */ 1425 } flip_params; /**< Pageflip parameters */ 1426 uint32_t reserved[9]; /**< Reserved bits */ 1427 }; 1428 1429 /** 1430 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1431 */ 1432 struct dmub_rb_cmd_PLAT_54186_wa { 1433 struct dmub_cmd_header header; /**< Command header */ 1434 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1435 }; 1436 1437 /** 1438 * enum dmub_cmd_mall_type - MALL commands 1439 */ 1440 enum dmub_cmd_mall_type { 1441 /** 1442 * Allows display refresh from MALL. 1443 */ 1444 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1445 /** 1446 * Disallows display refresh from MALL. 1447 */ 1448 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1449 /** 1450 * Cursor copy for MALL. 1451 */ 1452 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1453 /** 1454 * Controls DF requests. 1455 */ 1456 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1457 }; 1458 1459 /** 1460 * struct dmub_rb_cmd_mall - MALL command data. 1461 */ 1462 struct dmub_rb_cmd_mall { 1463 struct dmub_cmd_header header; /**< Common command header */ 1464 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1465 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1466 uint32_t tmr_delay; /**< Timer delay */ 1467 uint32_t tmr_scale; /**< Timer scale */ 1468 uint16_t cursor_width; /**< Cursor width in pixels */ 1469 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1470 uint16_t cursor_height; /**< Cursor height in pixels */ 1471 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1472 uint8_t debug_bits; /**< Debug bits */ 1473 1474 uint8_t reserved1; /**< Reserved bits */ 1475 uint8_t reserved2; /**< Reserved bits */ 1476 }; 1477 1478 /** 1479 * enum dmub_cmd_cab_type - CAB command data. 1480 */ 1481 enum dmub_cmd_cab_type { 1482 /** 1483 * No idle optimizations (i.e. no CAB) 1484 */ 1485 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1486 /** 1487 * No DCN requests for memory 1488 */ 1489 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1490 /** 1491 * Fit surfaces in CAB (i.e. CAB enable) 1492 */ 1493 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1494 /** 1495 * Do not fit surfaces in CAB (i.e. no CAB) 1496 */ 1497 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1498 }; 1499 1500 /** 1501 * struct dmub_rb_cmd_cab - CAB command data. 1502 */ 1503 struct dmub_rb_cmd_cab_for_ss { 1504 struct dmub_cmd_header header; 1505 uint8_t cab_alloc_ways; /* total number of ways */ 1506 uint8_t debug_bits; /* debug bits */ 1507 }; 1508 1509 /** 1510 * Enum for indicating which MCLK switch mode per pipe 1511 */ 1512 enum mclk_switch_mode { 1513 NONE = 0, 1514 FPO = 1, 1515 SUBVP = 2, 1516 VBLANK = 3, 1517 }; 1518 1519 /* Per pipe struct which stores the MCLK switch mode 1520 * data to be sent to DMUB. 1521 * Named "v2" for now -- once FPO and SUBVP are fully merged 1522 * the type name can be updated 1523 */ 1524 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1525 union { 1526 struct { 1527 uint32_t pix_clk_100hz; 1528 uint16_t main_vblank_start; 1529 uint16_t main_vblank_end; 1530 uint16_t mall_region_lines; 1531 uint16_t prefetch_lines; 1532 uint16_t prefetch_to_mall_start_lines; 1533 uint16_t processing_delay_lines; 1534 uint16_t htotal; // required to calculate line time for multi-display cases 1535 uint16_t vtotal; 1536 uint8_t main_pipe_index; 1537 uint8_t phantom_pipe_index; 1538 /* Since the microschedule is calculated in terms of OTG lines, 1539 * include any scaling factors to make sure when we get accurate 1540 * conversion when programming MALL_START_LINE (which is in terms 1541 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1542 * is 1/2 (numerator = 1, denominator = 2). 1543 */ 1544 uint8_t scale_factor_numerator; 1545 uint8_t scale_factor_denominator; 1546 uint8_t is_drr; 1547 uint8_t main_split_pipe_index; 1548 uint8_t phantom_split_pipe_index; 1549 } subvp_data; 1550 1551 struct { 1552 uint32_t pix_clk_100hz; 1553 uint16_t vblank_start; 1554 uint16_t vblank_end; 1555 uint16_t vstartup_start; 1556 uint16_t vtotal; 1557 uint16_t htotal; 1558 uint8_t vblank_pipe_index; 1559 uint8_t padding[1]; 1560 struct { 1561 uint8_t drr_in_use; 1562 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1563 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1564 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1565 uint8_t use_ramping; // Use ramping or not 1566 uint8_t drr_vblank_start_margin; 1567 } drr_info; // DRR considered as part of SubVP + VBLANK case 1568 } vblank_data; 1569 } pipe_config; 1570 1571 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1572 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1573 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1574 */ 1575 uint8_t mode; // enum mclk_switch_mode 1576 }; 1577 1578 /** 1579 * Config data for Sub-VP and FPO 1580 * Named "v2" for now -- once FPO and SUBVP are fully merged 1581 * the type name can be updated 1582 */ 1583 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1584 uint16_t watermark_a_cache; 1585 uint8_t vertical_int_margin_us; 1586 uint8_t pstate_allow_width_us; 1587 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1588 }; 1589 1590 /** 1591 * DMUB rb command definition for Sub-VP and FPO 1592 * Named "v2" for now -- once FPO and SUBVP are fully merged 1593 * the type name can be updated 1594 */ 1595 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1596 struct dmub_cmd_header header; 1597 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1598 }; 1599 1600 struct dmub_flip_addr_info { 1601 uint32_t surf_addr_lo; 1602 uint32_t surf_addr_c_lo; 1603 uint32_t meta_addr_lo; 1604 uint32_t meta_addr_c_lo; 1605 uint16_t surf_addr_hi; 1606 uint16_t surf_addr_c_hi; 1607 uint16_t meta_addr_hi; 1608 uint16_t meta_addr_c_hi; 1609 }; 1610 1611 struct dmub_fams2_flip_info { 1612 union { 1613 struct { 1614 uint8_t is_immediate: 1; 1615 } bits; 1616 uint8_t all; 1617 } config; 1618 uint8_t otg_inst; 1619 uint8_t pipe_mask; 1620 uint8_t pad; 1621 struct dmub_flip_addr_info addr_info; 1622 }; 1623 1624 struct dmub_rb_cmd_fams2_flip { 1625 struct dmub_cmd_header header; 1626 struct dmub_fams2_flip_info flip_info; 1627 }; 1628 1629 struct dmub_optc_state_v2 { 1630 uint32_t v_total_min; 1631 uint32_t v_total_max; 1632 uint32_t v_total_mid; 1633 uint32_t v_total_mid_frame_num; 1634 uint8_t program_manual_trigger; 1635 uint8_t tg_inst; 1636 uint8_t pad[2]; 1637 }; 1638 1639 struct dmub_optc_position { 1640 uint32_t vpos; 1641 uint32_t hpos; 1642 uint32_t frame; 1643 }; 1644 1645 struct dmub_rb_cmd_fams2_drr_update { 1646 struct dmub_cmd_header header; 1647 struct dmub_optc_state_v2 dmub_optc_state_req; 1648 }; 1649 1650 /* HW and FW global configuration data for FAMS2 */ 1651 /* FAMS2 types and structs */ 1652 enum fams2_stream_type { 1653 FAMS2_STREAM_TYPE_NONE = 0, 1654 FAMS2_STREAM_TYPE_VBLANK = 1, 1655 FAMS2_STREAM_TYPE_VACTIVE = 2, 1656 FAMS2_STREAM_TYPE_DRR = 3, 1657 FAMS2_STREAM_TYPE_SUBVP = 4, 1658 }; 1659 1660 /* dynamic stream state */ 1661 struct dmub_fams2_legacy_stream_dynamic_state { 1662 uint8_t force_allow_at_vblank; 1663 uint8_t pad[3]; 1664 }; 1665 1666 struct dmub_fams2_subvp_stream_dynamic_state { 1667 uint16_t viewport_start_hubp_vline; 1668 uint16_t viewport_height_hubp_vlines; 1669 uint16_t viewport_start_c_hubp_vline; 1670 uint16_t viewport_height_c_hubp_vlines; 1671 uint16_t phantom_viewport_height_hubp_vlines; 1672 uint16_t phantom_viewport_height_c_hubp_vlines; 1673 uint16_t microschedule_start_otg_vline; 1674 uint16_t mall_start_otg_vline; 1675 uint16_t mall_start_hubp_vline; 1676 uint16_t mall_start_c_hubp_vline; 1677 uint8_t force_allow_at_vblank_only; 1678 uint8_t pad[3]; 1679 }; 1680 1681 struct dmub_fams2_drr_stream_dynamic_state { 1682 uint16_t stretched_vtotal; 1683 uint8_t use_cur_vtotal; 1684 uint8_t pad; 1685 }; 1686 1687 struct dmub_fams2_stream_dynamic_state { 1688 uint64_t ref_tick; 1689 uint32_t cur_vtotal; 1690 uint16_t adjusted_allow_end_otg_vline; 1691 uint8_t pad[2]; 1692 struct dmub_optc_position ref_otg_pos; 1693 struct dmub_optc_position target_otg_pos; 1694 union { 1695 struct dmub_fams2_legacy_stream_dynamic_state legacy; 1696 struct dmub_fams2_subvp_stream_dynamic_state subvp; 1697 struct dmub_fams2_drr_stream_dynamic_state drr; 1698 } sub_state; 1699 }; 1700 1701 /* static stream state */ 1702 struct dmub_fams2_legacy_stream_static_state { 1703 uint8_t vactive_det_fill_delay_otg_vlines; 1704 uint8_t programming_delay_otg_vlines; 1705 }; 1706 1707 struct dmub_fams2_subvp_stream_static_state { 1708 uint16_t vratio_numerator; 1709 uint16_t vratio_denominator; 1710 uint16_t phantom_vtotal; 1711 uint16_t phantom_vactive; 1712 union { 1713 struct { 1714 uint8_t is_multi_planar : 1; 1715 uint8_t is_yuv420 : 1; 1716 } bits; 1717 uint8_t all; 1718 } config; 1719 uint8_t programming_delay_otg_vlines; 1720 uint8_t prefetch_to_mall_otg_vlines; 1721 uint8_t phantom_otg_inst; 1722 uint8_t phantom_pipe_mask; 1723 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1724 }; 1725 1726 struct dmub_fams2_drr_stream_static_state { 1727 uint16_t nom_stretched_vtotal; 1728 uint8_t programming_delay_otg_vlines; 1729 uint8_t only_stretch_if_required; 1730 uint8_t pad[2]; 1731 }; 1732 1733 struct dmub_fams2_stream_static_state { 1734 enum fams2_stream_type type; 1735 uint32_t otg_vline_time_ns; 1736 uint32_t otg_vline_time_ticks; 1737 uint16_t htotal; 1738 uint16_t vtotal; // nominal vtotal 1739 uint16_t vblank_start; 1740 uint16_t vblank_end; 1741 uint16_t max_vtotal; 1742 uint16_t allow_start_otg_vline; 1743 uint16_t allow_end_otg_vline; 1744 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1745 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1746 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 1747 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1748 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1749 union { 1750 struct { 1751 uint8_t is_drr: 1; // stream is DRR enabled 1752 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 1753 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1754 } bits; 1755 uint8_t all; 1756 } config; 1757 uint8_t otg_inst; 1758 uint8_t pipe_mask; // pipe mask for the whole config 1759 uint8_t num_planes; 1760 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1761 uint8_t pad[DMUB_MAX_PLANES % 4]; 1762 union { 1763 struct dmub_fams2_legacy_stream_static_state legacy; 1764 struct dmub_fams2_subvp_stream_static_state subvp; 1765 struct dmub_fams2_drr_stream_static_state drr; 1766 } sub_state; 1767 }; 1768 1769 /** 1770 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 1771 * p-state request to allow latency 1772 */ 1773 enum dmub_fams2_allow_delay_check_mode { 1774 /* No check for request to allow delay */ 1775 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 1776 /* Check for request to allow delay */ 1777 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 1778 /* Check for prepare to allow delay */ 1779 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 1780 }; 1781 1782 union dmub_fams2_global_feature_config { 1783 struct { 1784 uint32_t enable: 1; 1785 uint32_t enable_ppt_check: 1; 1786 uint32_t enable_stall_recovery: 1; 1787 uint32_t enable_debug: 1; 1788 uint32_t enable_offload_flip: 1; 1789 uint32_t enable_visual_confirm: 1; 1790 uint32_t allow_delay_check_mode: 2; 1791 uint32_t reserved: 24; 1792 } bits; 1793 uint32_t all; 1794 }; 1795 1796 struct dmub_cmd_fams2_global_config { 1797 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 1798 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 1799 uint32_t num_streams; 1800 union dmub_fams2_global_feature_config features; 1801 uint8_t pad[3]; 1802 }; 1803 1804 union dmub_cmd_fams2_config { 1805 struct dmub_cmd_fams2_global_config global; 1806 struct dmub_fams2_stream_static_state stream; 1807 }; 1808 1809 /** 1810 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 1811 */ 1812 struct dmub_rb_cmd_fams2 { 1813 struct dmub_cmd_header header; 1814 union dmub_cmd_fams2_config config; 1815 }; 1816 1817 /** 1818 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1819 */ 1820 enum dmub_cmd_idle_opt_type { 1821 /** 1822 * DCN hardware restore. 1823 */ 1824 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1825 1826 /** 1827 * DCN hardware save. 1828 */ 1829 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1830 1831 /** 1832 * DCN hardware notify idle. 1833 */ 1834 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1835 }; 1836 1837 /** 1838 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1839 */ 1840 struct dmub_rb_cmd_idle_opt_dcn_restore { 1841 struct dmub_cmd_header header; /**< header */ 1842 }; 1843 1844 /** 1845 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1846 */ 1847 struct dmub_dcn_notify_idle_cntl_data { 1848 uint8_t driver_idle; 1849 uint8_t reserved[59]; 1850 }; 1851 1852 /** 1853 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1854 */ 1855 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1856 struct dmub_cmd_header header; /**< header */ 1857 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1858 }; 1859 1860 /** 1861 * struct dmub_clocks - Clock update notification. 1862 */ 1863 struct dmub_clocks { 1864 uint32_t dispclk_khz; /**< dispclk kHz */ 1865 uint32_t dppclk_khz; /**< dppclk kHz */ 1866 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1867 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1868 }; 1869 1870 /** 1871 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1872 */ 1873 enum dmub_cmd_clk_mgr_type { 1874 /** 1875 * Notify DMCUB of clock update. 1876 */ 1877 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1878 }; 1879 1880 /** 1881 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1882 */ 1883 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1884 struct dmub_cmd_header header; /**< header */ 1885 struct dmub_clocks clocks; /**< clock data */ 1886 }; 1887 1888 /** 1889 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1890 */ 1891 struct dmub_cmd_digx_encoder_control_data { 1892 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1893 }; 1894 1895 /** 1896 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1897 */ 1898 struct dmub_rb_cmd_digx_encoder_control { 1899 struct dmub_cmd_header header; /**< header */ 1900 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1901 }; 1902 1903 /** 1904 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1905 */ 1906 struct dmub_cmd_set_pixel_clock_data { 1907 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1908 }; 1909 1910 /** 1911 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1912 */ 1913 struct dmub_rb_cmd_set_pixel_clock { 1914 struct dmub_cmd_header header; /**< header */ 1915 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1916 }; 1917 1918 /** 1919 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1920 */ 1921 struct dmub_cmd_enable_disp_power_gating_data { 1922 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1923 }; 1924 1925 /** 1926 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1927 */ 1928 struct dmub_rb_cmd_enable_disp_power_gating { 1929 struct dmub_cmd_header header; /**< header */ 1930 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1931 }; 1932 1933 /** 1934 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1935 */ 1936 struct dmub_dig_transmitter_control_data_v1_7 { 1937 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1938 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1939 union { 1940 uint8_t digmode; /**< enum atom_encode_mode_def */ 1941 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1942 } mode_laneset; 1943 uint8_t lanenum; /**< Number of lanes */ 1944 union { 1945 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1946 } symclk_units; 1947 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1948 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1949 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1950 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1951 uint8_t reserved1; /**< For future use */ 1952 uint8_t reserved2[3]; /**< For future use */ 1953 uint32_t reserved3[11]; /**< For future use */ 1954 }; 1955 1956 /** 1957 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1958 */ 1959 union dmub_cmd_dig1_transmitter_control_data { 1960 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1961 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1962 }; 1963 1964 /** 1965 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1966 */ 1967 struct dmub_rb_cmd_dig1_transmitter_control { 1968 struct dmub_cmd_header header; /**< header */ 1969 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1970 }; 1971 1972 /** 1973 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1974 */ 1975 struct dmub_rb_cmd_domain_control_data { 1976 uint8_t inst : 6; /**< DOMAIN instance to control */ 1977 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1978 uint8_t reserved[3]; /**< Reserved for future use */ 1979 }; 1980 1981 /** 1982 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1983 */ 1984 struct dmub_rb_cmd_domain_control { 1985 struct dmub_cmd_header header; /**< header */ 1986 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1987 }; 1988 1989 /** 1990 * DPIA tunnel command parameters. 1991 */ 1992 struct dmub_cmd_dig_dpia_control_data { 1993 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1994 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1995 union { 1996 uint8_t digmode; /** enum atom_encode_mode_def */ 1997 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1998 } mode_laneset; 1999 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2000 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2001 uint8_t hpdsel; /** =0: HPD is not assigned */ 2002 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2003 uint8_t dpia_id; /** Index of DPIA */ 2004 uint8_t fec_rdy : 1; 2005 uint8_t reserved : 7; 2006 uint32_t reserved1; 2007 }; 2008 2009 /** 2010 * DMUB command for DPIA tunnel control. 2011 */ 2012 struct dmub_rb_cmd_dig1_dpia_control { 2013 struct dmub_cmd_header header; 2014 struct dmub_cmd_dig_dpia_control_data dpia_control; 2015 }; 2016 2017 /** 2018 * SET_CONFIG Command Payload 2019 */ 2020 struct set_config_cmd_payload { 2021 uint8_t msg_type; /* set config message type */ 2022 uint8_t msg_data; /* set config message data */ 2023 }; 2024 2025 /** 2026 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2027 */ 2028 struct dmub_cmd_set_config_control_data { 2029 struct set_config_cmd_payload cmd_pkt; 2030 uint8_t instance; /* DPIA instance */ 2031 uint8_t immed_status; /* Immediate status returned in case of error */ 2032 }; 2033 2034 /** 2035 * DMUB command structure for SET_CONFIG command. 2036 */ 2037 struct dmub_rb_cmd_set_config_access { 2038 struct dmub_cmd_header header; /* header */ 2039 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2040 }; 2041 2042 /** 2043 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2044 */ 2045 struct dmub_cmd_mst_alloc_slots_control_data { 2046 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2047 uint8_t instance; /* DPIA instance */ 2048 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2049 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2050 }; 2051 2052 /** 2053 * DMUB command structure for SET_ command. 2054 */ 2055 struct dmub_rb_cmd_set_mst_alloc_slots { 2056 struct dmub_cmd_header header; /* header */ 2057 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2058 }; 2059 2060 /** 2061 * DMUB command structure for DPIA HPD int enable control. 2062 */ 2063 struct dmub_rb_cmd_dpia_hpd_int_enable { 2064 struct dmub_cmd_header header; /* header */ 2065 uint32_t enable; /* dpia hpd interrupt enable */ 2066 }; 2067 2068 /** 2069 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2070 */ 2071 struct dmub_rb_cmd_dpphy_init { 2072 struct dmub_cmd_header header; /**< header */ 2073 uint8_t reserved[60]; /**< reserved bits */ 2074 }; 2075 2076 /** 2077 * enum dp_aux_request_action - DP AUX request command listing. 2078 * 2079 * 4 AUX request command bits are shifted to high nibble. 2080 */ 2081 enum dp_aux_request_action { 2082 /** I2C-over-AUX write request */ 2083 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2084 /** I2C-over-AUX read request */ 2085 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2086 /** I2C-over-AUX write status request */ 2087 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2088 /** I2C-over-AUX write request with MOT=1 */ 2089 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2090 /** I2C-over-AUX read request with MOT=1 */ 2091 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2092 /** I2C-over-AUX write status request with MOT=1 */ 2093 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2094 /** Native AUX write request */ 2095 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2096 /** Native AUX read request */ 2097 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2098 }; 2099 2100 /** 2101 * enum aux_return_code_type - DP AUX process return code listing. 2102 */ 2103 enum aux_return_code_type { 2104 /** AUX process succeeded */ 2105 AUX_RET_SUCCESS = 0, 2106 /** AUX process failed with unknown reason */ 2107 AUX_RET_ERROR_UNKNOWN, 2108 /** AUX process completed with invalid reply */ 2109 AUX_RET_ERROR_INVALID_REPLY, 2110 /** AUX process timed out */ 2111 AUX_RET_ERROR_TIMEOUT, 2112 /** HPD was low during AUX process */ 2113 AUX_RET_ERROR_HPD_DISCON, 2114 /** Failed to acquire AUX engine */ 2115 AUX_RET_ERROR_ENGINE_ACQUIRE, 2116 /** AUX request not supported */ 2117 AUX_RET_ERROR_INVALID_OPERATION, 2118 /** AUX process not available */ 2119 AUX_RET_ERROR_PROTOCOL_ERROR, 2120 }; 2121 2122 /** 2123 * enum aux_channel_type - DP AUX channel type listing. 2124 */ 2125 enum aux_channel_type { 2126 /** AUX thru Legacy DP AUX */ 2127 AUX_CHANNEL_LEGACY_DDC, 2128 /** AUX thru DPIA DP tunneling */ 2129 AUX_CHANNEL_DPIA 2130 }; 2131 2132 /** 2133 * struct aux_transaction_parameters - DP AUX request transaction data 2134 */ 2135 struct aux_transaction_parameters { 2136 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2137 uint8_t action; /**< enum dp_aux_request_action */ 2138 uint8_t length; /**< DP AUX request data length */ 2139 uint8_t reserved; /**< For future use */ 2140 uint32_t address; /**< DP AUX address */ 2141 uint8_t data[16]; /**< DP AUX write data */ 2142 }; 2143 2144 /** 2145 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2146 */ 2147 struct dmub_cmd_dp_aux_control_data { 2148 uint8_t instance; /**< AUX instance or DPIA instance */ 2149 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2150 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2151 uint8_t reserved0; /**< For future use */ 2152 uint16_t timeout; /**< timeout time in us */ 2153 uint16_t reserved1; /**< For future use */ 2154 enum aux_channel_type type; /**< enum aux_channel_type */ 2155 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2156 }; 2157 2158 /** 2159 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2160 */ 2161 struct dmub_rb_cmd_dp_aux_access { 2162 /** 2163 * Command header. 2164 */ 2165 struct dmub_cmd_header header; 2166 /** 2167 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2168 */ 2169 struct dmub_cmd_dp_aux_control_data aux_control; 2170 }; 2171 2172 /** 2173 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2174 */ 2175 struct dmub_rb_cmd_outbox1_enable { 2176 /** 2177 * Command header. 2178 */ 2179 struct dmub_cmd_header header; 2180 /** 2181 * enable: 0x0 -> disable outbox1 notification (default value) 2182 * 0x1 -> enable outbox1 notification 2183 */ 2184 uint32_t enable; 2185 }; 2186 2187 /* DP AUX Reply command - OutBox Cmd */ 2188 /** 2189 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2190 */ 2191 struct aux_reply_data { 2192 /** 2193 * Aux cmd 2194 */ 2195 uint8_t command; 2196 /** 2197 * Aux reply data length (max: 16 bytes) 2198 */ 2199 uint8_t length; 2200 /** 2201 * Alignment only 2202 */ 2203 uint8_t pad[2]; 2204 /** 2205 * Aux reply data 2206 */ 2207 uint8_t data[16]; 2208 }; 2209 2210 /** 2211 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2212 */ 2213 struct aux_reply_control_data { 2214 /** 2215 * Reserved for future use 2216 */ 2217 uint32_t handle; 2218 /** 2219 * Aux Instance 2220 */ 2221 uint8_t instance; 2222 /** 2223 * Aux transaction result: definition in enum aux_return_code_type 2224 */ 2225 uint8_t result; 2226 /** 2227 * Alignment only 2228 */ 2229 uint16_t pad; 2230 }; 2231 2232 /** 2233 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2234 */ 2235 struct dmub_rb_cmd_dp_aux_reply { 2236 /** 2237 * Command header. 2238 */ 2239 struct dmub_cmd_header header; 2240 /** 2241 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2242 */ 2243 struct aux_reply_control_data control; 2244 /** 2245 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2246 */ 2247 struct aux_reply_data reply_data; 2248 }; 2249 2250 /* DP HPD Notify command - OutBox Cmd */ 2251 /** 2252 * DP HPD Type 2253 */ 2254 enum dp_hpd_type { 2255 /** 2256 * Normal DP HPD 2257 */ 2258 DP_HPD = 0, 2259 /** 2260 * DP HPD short pulse 2261 */ 2262 DP_IRQ 2263 }; 2264 2265 /** 2266 * DP HPD Status 2267 */ 2268 enum dp_hpd_status { 2269 /** 2270 * DP_HPD status low 2271 */ 2272 DP_HPD_UNPLUG = 0, 2273 /** 2274 * DP_HPD status high 2275 */ 2276 DP_HPD_PLUG 2277 }; 2278 2279 /** 2280 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2281 */ 2282 struct dp_hpd_data { 2283 /** 2284 * DP HPD instance 2285 */ 2286 uint8_t instance; 2287 /** 2288 * HPD type 2289 */ 2290 uint8_t hpd_type; 2291 /** 2292 * HPD status: only for type: DP_HPD to indicate status 2293 */ 2294 uint8_t hpd_status; 2295 /** 2296 * Alignment only 2297 */ 2298 uint8_t pad; 2299 }; 2300 2301 /** 2302 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2303 */ 2304 struct dmub_rb_cmd_dp_hpd_notify { 2305 /** 2306 * Command header. 2307 */ 2308 struct dmub_cmd_header header; 2309 /** 2310 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2311 */ 2312 struct dp_hpd_data hpd_data; 2313 }; 2314 2315 /** 2316 * Definition of a SET_CONFIG reply from DPOA. 2317 */ 2318 enum set_config_status { 2319 SET_CONFIG_PENDING = 0, 2320 SET_CONFIG_ACK_RECEIVED, 2321 SET_CONFIG_RX_TIMEOUT, 2322 SET_CONFIG_UNKNOWN_ERROR, 2323 }; 2324 2325 /** 2326 * Definition of a set_config reply 2327 */ 2328 struct set_config_reply_control_data { 2329 uint8_t instance; /* DPIA Instance */ 2330 uint8_t status; /* Set Config reply */ 2331 uint16_t pad; /* Alignment */ 2332 }; 2333 2334 /** 2335 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2336 */ 2337 struct dmub_rb_cmd_dp_set_config_reply { 2338 struct dmub_cmd_header header; 2339 struct set_config_reply_control_data set_config_reply_control; 2340 }; 2341 2342 /** 2343 * Definition of a DPIA notification header 2344 */ 2345 struct dpia_notification_header { 2346 uint8_t instance; /**< DPIA Instance */ 2347 uint8_t reserved[3]; 2348 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2349 }; 2350 2351 /** 2352 * Definition of the common data struct of DPIA notification 2353 */ 2354 struct dpia_notification_common { 2355 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2356 - sizeof(struct dpia_notification_header)]; 2357 }; 2358 2359 /** 2360 * Definition of a DPIA notification data 2361 */ 2362 struct dpia_bw_allocation_notify_data { 2363 union { 2364 struct { 2365 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2366 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2367 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2368 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2369 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2370 uint16_t reserved: 11; /**< Reserved */ 2371 } bits; 2372 2373 uint16_t flags; 2374 }; 2375 2376 uint8_t cm_id; /**< CM ID */ 2377 uint8_t group_id; /**< Group ID */ 2378 uint8_t granularity; /**< BW Allocation Granularity */ 2379 uint8_t estimated_bw; /**< Estimated_BW */ 2380 uint8_t allocated_bw; /**< Allocated_BW */ 2381 uint8_t reserved; 2382 }; 2383 2384 /** 2385 * union dpia_notify_data_type - DPIA Notification in Outbox command 2386 */ 2387 union dpia_notification_data { 2388 /** 2389 * DPIA Notification for common data struct 2390 */ 2391 struct dpia_notification_common common_data; 2392 2393 /** 2394 * DPIA Notification for DP BW Allocation support 2395 */ 2396 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2397 }; 2398 2399 /** 2400 * Definition of a DPIA notification payload 2401 */ 2402 struct dpia_notification_payload { 2403 struct dpia_notification_header header; 2404 union dpia_notification_data data; /**< DPIA notification payload data */ 2405 }; 2406 2407 /** 2408 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2409 */ 2410 struct dmub_rb_cmd_dpia_notification { 2411 struct dmub_cmd_header header; /**< DPIA notification header */ 2412 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2413 }; 2414 2415 /** 2416 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2417 */ 2418 struct dmub_cmd_hpd_state_query_data { 2419 uint8_t instance; /**< HPD instance or DPIA instance */ 2420 uint8_t result; /**< For returning HPD state */ 2421 uint16_t pad; /** < Alignment */ 2422 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2423 enum aux_return_code_type status; /**< for returning the status of command */ 2424 }; 2425 2426 /** 2427 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2428 */ 2429 struct dmub_rb_cmd_query_hpd_state { 2430 /** 2431 * Command header. 2432 */ 2433 struct dmub_cmd_header header; 2434 /** 2435 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2436 */ 2437 struct dmub_cmd_hpd_state_query_data data; 2438 }; 2439 2440 /* 2441 * Command IDs should be treated as stable ABI. 2442 * Do not reuse or modify IDs. 2443 */ 2444 2445 /** 2446 * PSR command sub-types. 2447 */ 2448 enum dmub_cmd_psr_type { 2449 /** 2450 * Set PSR version support. 2451 */ 2452 DMUB_CMD__PSR_SET_VERSION = 0, 2453 /** 2454 * Copy driver-calculated parameters to PSR state. 2455 */ 2456 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2457 /** 2458 * Enable PSR. 2459 */ 2460 DMUB_CMD__PSR_ENABLE = 2, 2461 2462 /** 2463 * Disable PSR. 2464 */ 2465 DMUB_CMD__PSR_DISABLE = 3, 2466 2467 /** 2468 * Set PSR level. 2469 * PSR level is a 16-bit value dicated by driver that 2470 * will enable/disable different functionality. 2471 */ 2472 DMUB_CMD__PSR_SET_LEVEL = 4, 2473 2474 /** 2475 * Forces PSR enabled until an explicit PSR disable call. 2476 */ 2477 DMUB_CMD__PSR_FORCE_STATIC = 5, 2478 /** 2479 * Set vtotal in psr active for FreeSync PSR. 2480 */ 2481 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2482 /** 2483 * Set PSR power option 2484 */ 2485 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2486 }; 2487 2488 enum dmub_cmd_fams_type { 2489 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2490 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2491 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2492 /** 2493 * For SubVP set manual trigger in FW because it 2494 * triggers DRR_UPDATE_PENDING which SubVP relies 2495 * on (for any SubVP cases that use a DRR display) 2496 */ 2497 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2498 DMUB_CMD__FAMS2_CONFIG = 4, 2499 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2500 DMUB_CMD__FAMS2_FLIP = 6, 2501 }; 2502 2503 /** 2504 * PSR versions. 2505 */ 2506 enum psr_version { 2507 /** 2508 * PSR version 1. 2509 */ 2510 PSR_VERSION_1 = 0, 2511 /** 2512 * Freesync PSR SU. 2513 */ 2514 PSR_VERSION_SU_1 = 1, 2515 /** 2516 * PSR not supported. 2517 */ 2518 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2519 }; 2520 2521 /** 2522 * PHY Link rate for DP. 2523 */ 2524 enum phy_link_rate { 2525 /** 2526 * not supported. 2527 */ 2528 PHY_RATE_UNKNOWN = 0, 2529 /** 2530 * Rate_1 (RBR) - 1.62 Gbps/Lane 2531 */ 2532 PHY_RATE_162 = 1, 2533 /** 2534 * Rate_2 - 2.16 Gbps/Lane 2535 */ 2536 PHY_RATE_216 = 2, 2537 /** 2538 * Rate_3 - 2.43 Gbps/Lane 2539 */ 2540 PHY_RATE_243 = 3, 2541 /** 2542 * Rate_4 (HBR) - 2.70 Gbps/Lane 2543 */ 2544 PHY_RATE_270 = 4, 2545 /** 2546 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2547 */ 2548 PHY_RATE_324 = 5, 2549 /** 2550 * Rate_6 - 4.32 Gbps/Lane 2551 */ 2552 PHY_RATE_432 = 6, 2553 /** 2554 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2555 */ 2556 PHY_RATE_540 = 7, 2557 /** 2558 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2559 */ 2560 PHY_RATE_810 = 8, 2561 /** 2562 * UHBR10 - 10.0 Gbps/Lane 2563 */ 2564 PHY_RATE_1000 = 9, 2565 /** 2566 * UHBR13.5 - 13.5 Gbps/Lane 2567 */ 2568 PHY_RATE_1350 = 10, 2569 /** 2570 * UHBR10 - 20.0 Gbps/Lane 2571 */ 2572 PHY_RATE_2000 = 11, 2573 2574 PHY_RATE_675 = 12, 2575 /** 2576 * Rate 12 - 6.75 Gbps/Lane 2577 */ 2578 }; 2579 2580 /** 2581 * enum dmub_phy_fsm_state - PHY FSM states. 2582 * PHY FSM state to transit to during PSR enable/disable. 2583 */ 2584 enum dmub_phy_fsm_state { 2585 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2586 DMUB_PHY_FSM_RESET, 2587 DMUB_PHY_FSM_RESET_RELEASED, 2588 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2589 DMUB_PHY_FSM_INITIALIZED, 2590 DMUB_PHY_FSM_CALIBRATED, 2591 DMUB_PHY_FSM_CALIBRATED_LP, 2592 DMUB_PHY_FSM_CALIBRATED_PG, 2593 DMUB_PHY_FSM_POWER_DOWN, 2594 DMUB_PHY_FSM_PLL_EN, 2595 DMUB_PHY_FSM_TX_EN, 2596 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2597 DMUB_PHY_FSM_FAST_LP, 2598 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2599 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2600 DMUB_PHY_FSM_P2_PLL_OFF, 2601 DMUB_PHY_FSM_P2_PLL_ON, 2602 }; 2603 2604 /** 2605 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2606 */ 2607 struct dmub_cmd_psr_copy_settings_data { 2608 /** 2609 * Flags that can be set by driver to change some PSR behaviour. 2610 */ 2611 union dmub_psr_debug_flags debug; 2612 /** 2613 * 16-bit value dicated by driver that will enable/disable different functionality. 2614 */ 2615 uint16_t psr_level; 2616 /** 2617 * DPP HW instance. 2618 */ 2619 uint8_t dpp_inst; 2620 /** 2621 * MPCC HW instance. 2622 * Not used in dmub fw, 2623 * dmub fw will get active opp by reading odm registers. 2624 */ 2625 uint8_t mpcc_inst; 2626 /** 2627 * OPP HW instance. 2628 * Not used in dmub fw, 2629 * dmub fw will get active opp by reading odm registers. 2630 */ 2631 uint8_t opp_inst; 2632 /** 2633 * OTG HW instance. 2634 */ 2635 uint8_t otg_inst; 2636 /** 2637 * DIG FE HW instance. 2638 */ 2639 uint8_t digfe_inst; 2640 /** 2641 * DIG BE HW instance. 2642 */ 2643 uint8_t digbe_inst; 2644 /** 2645 * DP PHY HW instance. 2646 */ 2647 uint8_t dpphy_inst; 2648 /** 2649 * AUX HW instance. 2650 */ 2651 uint8_t aux_inst; 2652 /** 2653 * Determines if SMU optimzations are enabled/disabled. 2654 */ 2655 uint8_t smu_optimizations_en; 2656 /** 2657 * Unused. 2658 * TODO: Remove. 2659 */ 2660 uint8_t frame_delay; 2661 /** 2662 * If RFB setup time is greater than the total VBLANK time, 2663 * it is not possible for the sink to capture the video frame 2664 * in the same frame the SDP is sent. In this case, 2665 * the frame capture indication bit should be set and an extra 2666 * static frame should be transmitted to the sink. 2667 */ 2668 uint8_t frame_cap_ind; 2669 /** 2670 * Granularity of Y offset supported by sink. 2671 */ 2672 uint8_t su_y_granularity; 2673 /** 2674 * Indicates whether sink should start capturing 2675 * immediately following active scan line, 2676 * or starting with the 2nd active scan line. 2677 */ 2678 uint8_t line_capture_indication; 2679 /** 2680 * Multi-display optimizations are implemented on certain ASICs. 2681 */ 2682 uint8_t multi_disp_optimizations_en; 2683 /** 2684 * The last possible line SDP may be transmitted without violating 2685 * the RFB setup time or entering the active video frame. 2686 */ 2687 uint16_t init_sdp_deadline; 2688 /** 2689 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2690 */ 2691 uint8_t rate_control_caps ; 2692 /* 2693 * Force PSRSU always doing full frame update 2694 */ 2695 uint8_t force_ffu_mode; 2696 /** 2697 * Length of each horizontal line in us. 2698 */ 2699 uint32_t line_time_in_us; 2700 /** 2701 * FEC enable status in driver 2702 */ 2703 uint8_t fec_enable_status; 2704 /** 2705 * FEC re-enable delay when PSR exit. 2706 * unit is 100us, range form 0~255(0xFF). 2707 */ 2708 uint8_t fec_enable_delay_in100us; 2709 /** 2710 * PSR control version. 2711 */ 2712 uint8_t cmd_version; 2713 /** 2714 * Panel Instance. 2715 * Panel instance to identify which psr_state to use 2716 * Currently the support is only for 0 or 1 2717 */ 2718 uint8_t panel_inst; 2719 /* 2720 * DSC enable status in driver 2721 */ 2722 uint8_t dsc_enable_status; 2723 /* 2724 * Use FSM state for PSR power up/down 2725 */ 2726 uint8_t use_phy_fsm; 2727 /** 2728 * frame delay for frame re-lock 2729 */ 2730 uint8_t relock_delay_frame_cnt; 2731 /** 2732 * Explicit padding to 4 byte boundary. 2733 */ 2734 uint8_t pad3; 2735 /** 2736 * DSC Slice height. 2737 */ 2738 uint16_t dsc_slice_height; 2739 /** 2740 * Some panels request main link off before xth vertical line 2741 */ 2742 uint16_t poweroff_before_vertical_line; 2743 }; 2744 2745 /** 2746 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2747 */ 2748 struct dmub_rb_cmd_psr_copy_settings { 2749 /** 2750 * Command header. 2751 */ 2752 struct dmub_cmd_header header; 2753 /** 2754 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2755 */ 2756 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2757 }; 2758 2759 /** 2760 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2761 */ 2762 struct dmub_cmd_psr_set_level_data { 2763 /** 2764 * 16-bit value dicated by driver that will enable/disable different functionality. 2765 */ 2766 uint16_t psr_level; 2767 /** 2768 * PSR control version. 2769 */ 2770 uint8_t cmd_version; 2771 /** 2772 * Panel Instance. 2773 * Panel instance to identify which psr_state to use 2774 * Currently the support is only for 0 or 1 2775 */ 2776 uint8_t panel_inst; 2777 }; 2778 2779 /** 2780 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2781 */ 2782 struct dmub_rb_cmd_psr_set_level { 2783 /** 2784 * Command header. 2785 */ 2786 struct dmub_cmd_header header; 2787 /** 2788 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2789 */ 2790 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2791 }; 2792 2793 struct dmub_rb_cmd_psr_enable_data { 2794 /** 2795 * PSR control version. 2796 */ 2797 uint8_t cmd_version; 2798 /** 2799 * Panel Instance. 2800 * Panel instance to identify which psr_state to use 2801 * Currently the support is only for 0 or 1 2802 */ 2803 uint8_t panel_inst; 2804 /** 2805 * Phy state to enter. 2806 * Values to use are defined in dmub_phy_fsm_state 2807 */ 2808 uint8_t phy_fsm_state; 2809 /** 2810 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2811 * Set this using enum phy_link_rate. 2812 * This does not support HDMI/DP2 for now. 2813 */ 2814 uint8_t phy_rate; 2815 }; 2816 2817 /** 2818 * Definition of a DMUB_CMD__PSR_ENABLE command. 2819 * PSR enable/disable is controlled using the sub_type. 2820 */ 2821 struct dmub_rb_cmd_psr_enable { 2822 /** 2823 * Command header. 2824 */ 2825 struct dmub_cmd_header header; 2826 2827 struct dmub_rb_cmd_psr_enable_data data; 2828 }; 2829 2830 /** 2831 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2832 */ 2833 struct dmub_cmd_psr_set_version_data { 2834 /** 2835 * PSR version that FW should implement. 2836 */ 2837 enum psr_version version; 2838 /** 2839 * PSR control version. 2840 */ 2841 uint8_t cmd_version; 2842 /** 2843 * Panel Instance. 2844 * Panel instance to identify which psr_state to use 2845 * Currently the support is only for 0 or 1 2846 */ 2847 uint8_t panel_inst; 2848 /** 2849 * Explicit padding to 4 byte boundary. 2850 */ 2851 uint8_t pad[2]; 2852 }; 2853 2854 /** 2855 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2856 */ 2857 struct dmub_rb_cmd_psr_set_version { 2858 /** 2859 * Command header. 2860 */ 2861 struct dmub_cmd_header header; 2862 /** 2863 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2864 */ 2865 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2866 }; 2867 2868 struct dmub_cmd_psr_force_static_data { 2869 /** 2870 * PSR control version. 2871 */ 2872 uint8_t cmd_version; 2873 /** 2874 * Panel Instance. 2875 * Panel instance to identify which psr_state to use 2876 * Currently the support is only for 0 or 1 2877 */ 2878 uint8_t panel_inst; 2879 /** 2880 * Explicit padding to 4 byte boundary. 2881 */ 2882 uint8_t pad[2]; 2883 }; 2884 2885 /** 2886 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2887 */ 2888 struct dmub_rb_cmd_psr_force_static { 2889 /** 2890 * Command header. 2891 */ 2892 struct dmub_cmd_header header; 2893 /** 2894 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2895 */ 2896 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2897 }; 2898 2899 /** 2900 * PSR SU debug flags. 2901 */ 2902 union dmub_psr_su_debug_flags { 2903 /** 2904 * PSR SU debug flags. 2905 */ 2906 struct { 2907 /** 2908 * Update dirty rect in SW only. 2909 */ 2910 uint8_t update_dirty_rect_only : 1; 2911 /** 2912 * Reset the cursor/plane state before processing the call. 2913 */ 2914 uint8_t reset_state : 1; 2915 } bitfields; 2916 2917 /** 2918 * Union for debug flags. 2919 */ 2920 uint32_t u32All; 2921 }; 2922 2923 /** 2924 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2925 * This triggers a selective update for PSR SU. 2926 */ 2927 struct dmub_cmd_update_dirty_rect_data { 2928 /** 2929 * Dirty rects from OS. 2930 */ 2931 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2932 /** 2933 * PSR SU debug flags. 2934 */ 2935 union dmub_psr_su_debug_flags debug_flags; 2936 /** 2937 * OTG HW instance. 2938 */ 2939 uint8_t pipe_idx; 2940 /** 2941 * Number of dirty rects. 2942 */ 2943 uint8_t dirty_rect_count; 2944 /** 2945 * PSR control version. 2946 */ 2947 uint8_t cmd_version; 2948 /** 2949 * Panel Instance. 2950 * Panel instance to identify which psr_state to use 2951 * Currently the support is only for 0 or 1 2952 */ 2953 uint8_t panel_inst; 2954 }; 2955 2956 /** 2957 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2958 */ 2959 struct dmub_rb_cmd_update_dirty_rect { 2960 /** 2961 * Command header. 2962 */ 2963 struct dmub_cmd_header header; 2964 /** 2965 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2966 */ 2967 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2968 }; 2969 2970 /** 2971 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2972 */ 2973 union dmub_reg_cursor_control_cfg { 2974 struct { 2975 uint32_t cur_enable: 1; 2976 uint32_t reser0: 3; 2977 uint32_t cur_2x_magnify: 1; 2978 uint32_t reser1: 3; 2979 uint32_t mode: 3; 2980 uint32_t reser2: 5; 2981 uint32_t pitch: 2; 2982 uint32_t reser3: 6; 2983 uint32_t line_per_chunk: 5; 2984 uint32_t reser4: 3; 2985 } bits; 2986 uint32_t raw; 2987 }; 2988 struct dmub_cursor_position_cache_hubp { 2989 union dmub_reg_cursor_control_cfg cur_ctl; 2990 union dmub_reg_position_cfg { 2991 struct { 2992 uint32_t cur_x_pos: 16; 2993 uint32_t cur_y_pos: 16; 2994 } bits; 2995 uint32_t raw; 2996 } position; 2997 union dmub_reg_hot_spot_cfg { 2998 struct { 2999 uint32_t hot_x: 16; 3000 uint32_t hot_y: 16; 3001 } bits; 3002 uint32_t raw; 3003 } hot_spot; 3004 union dmub_reg_dst_offset_cfg { 3005 struct { 3006 uint32_t dst_x_offset: 13; 3007 uint32_t reserved: 19; 3008 } bits; 3009 uint32_t raw; 3010 } dst_offset; 3011 }; 3012 3013 union dmub_reg_cur0_control_cfg { 3014 struct { 3015 uint32_t cur0_enable: 1; 3016 uint32_t expansion_mode: 1; 3017 uint32_t reser0: 1; 3018 uint32_t cur0_rom_en: 1; 3019 uint32_t mode: 3; 3020 uint32_t reserved: 25; 3021 } bits; 3022 uint32_t raw; 3023 }; 3024 struct dmub_cursor_position_cache_dpp { 3025 union dmub_reg_cur0_control_cfg cur0_ctl; 3026 }; 3027 struct dmub_cursor_position_cfg { 3028 struct dmub_cursor_position_cache_hubp pHubp; 3029 struct dmub_cursor_position_cache_dpp pDpp; 3030 uint8_t pipe_idx; 3031 /* 3032 * Padding is required. To be 4 Bytes Aligned. 3033 */ 3034 uint8_t padding[3]; 3035 }; 3036 3037 struct dmub_cursor_attribute_cache_hubp { 3038 uint32_t SURFACE_ADDR_HIGH; 3039 uint32_t SURFACE_ADDR; 3040 union dmub_reg_cursor_control_cfg cur_ctl; 3041 union dmub_reg_cursor_size_cfg { 3042 struct { 3043 uint32_t width: 16; 3044 uint32_t height: 16; 3045 } bits; 3046 uint32_t raw; 3047 } size; 3048 union dmub_reg_cursor_settings_cfg { 3049 struct { 3050 uint32_t dst_y_offset: 8; 3051 uint32_t chunk_hdl_adjust: 2; 3052 uint32_t reserved: 22; 3053 } bits; 3054 uint32_t raw; 3055 } settings; 3056 }; 3057 struct dmub_cursor_attribute_cache_dpp { 3058 union dmub_reg_cur0_control_cfg cur0_ctl; 3059 }; 3060 struct dmub_cursor_attributes_cfg { 3061 struct dmub_cursor_attribute_cache_hubp aHubp; 3062 struct dmub_cursor_attribute_cache_dpp aDpp; 3063 }; 3064 3065 struct dmub_cmd_update_cursor_payload0 { 3066 /** 3067 * Cursor dirty rects. 3068 */ 3069 struct dmub_rect cursor_rect; 3070 /** 3071 * PSR SU debug flags. 3072 */ 3073 union dmub_psr_su_debug_flags debug_flags; 3074 /** 3075 * Cursor enable/disable. 3076 */ 3077 uint8_t enable; 3078 /** 3079 * OTG HW instance. 3080 */ 3081 uint8_t pipe_idx; 3082 /** 3083 * PSR control version. 3084 */ 3085 uint8_t cmd_version; 3086 /** 3087 * Panel Instance. 3088 * Panel instance to identify which psr_state to use 3089 * Currently the support is only for 0 or 1 3090 */ 3091 uint8_t panel_inst; 3092 /** 3093 * Cursor Position Register. 3094 * Registers contains Hubp & Dpp modules 3095 */ 3096 struct dmub_cursor_position_cfg position_cfg; 3097 }; 3098 3099 struct dmub_cmd_update_cursor_payload1 { 3100 struct dmub_cursor_attributes_cfg attribute_cfg; 3101 }; 3102 3103 union dmub_cmd_update_cursor_info_data { 3104 struct dmub_cmd_update_cursor_payload0 payload0; 3105 struct dmub_cmd_update_cursor_payload1 payload1; 3106 }; 3107 /** 3108 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3109 */ 3110 struct dmub_rb_cmd_update_cursor_info { 3111 /** 3112 * Command header. 3113 */ 3114 struct dmub_cmd_header header; 3115 /** 3116 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3117 */ 3118 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3119 }; 3120 3121 /** 3122 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3123 */ 3124 struct dmub_cmd_psr_set_vtotal_data { 3125 /** 3126 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3127 */ 3128 uint16_t psr_vtotal_idle; 3129 /** 3130 * PSR control version. 3131 */ 3132 uint8_t cmd_version; 3133 /** 3134 * Panel Instance. 3135 * Panel instance to identify which psr_state to use 3136 * Currently the support is only for 0 or 1 3137 */ 3138 uint8_t panel_inst; 3139 /* 3140 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3141 */ 3142 uint16_t psr_vtotal_su; 3143 /** 3144 * Explicit padding to 4 byte boundary. 3145 */ 3146 uint8_t pad2[2]; 3147 }; 3148 3149 /** 3150 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3151 */ 3152 struct dmub_rb_cmd_psr_set_vtotal { 3153 /** 3154 * Command header. 3155 */ 3156 struct dmub_cmd_header header; 3157 /** 3158 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3159 */ 3160 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3161 }; 3162 3163 /** 3164 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3165 */ 3166 struct dmub_cmd_psr_set_power_opt_data { 3167 /** 3168 * PSR control version. 3169 */ 3170 uint8_t cmd_version; 3171 /** 3172 * Panel Instance. 3173 * Panel instance to identify which psr_state to use 3174 * Currently the support is only for 0 or 1 3175 */ 3176 uint8_t panel_inst; 3177 /** 3178 * Explicit padding to 4 byte boundary. 3179 */ 3180 uint8_t pad[2]; 3181 /** 3182 * PSR power option 3183 */ 3184 uint32_t power_opt; 3185 }; 3186 3187 /** 3188 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3189 */ 3190 struct dmub_rb_cmd_psr_set_power_opt { 3191 /** 3192 * Command header. 3193 */ 3194 struct dmub_cmd_header header; 3195 /** 3196 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3197 */ 3198 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3199 }; 3200 3201 /** 3202 * Definition of Replay Residency GPINT command. 3203 * Bit[0] - Residency mode for Revision 0 3204 * Bit[1] - Enable/Disable state 3205 * Bit[2-3] - Revision number 3206 * Bit[4-7] - Residency mode for Revision 1 3207 * Bit[8] - Panel instance 3208 * Bit[9-15] - Reserved 3209 */ 3210 3211 enum pr_residency_mode { 3212 PR_RESIDENCY_MODE_PHY = 0x0, 3213 PR_RESIDENCY_MODE_ALPM, 3214 PR_RESIDENCY_MODE_IPS2, 3215 PR_RESIDENCY_MODE_FRAME_CNT, 3216 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3217 }; 3218 3219 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3220 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3221 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3222 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3223 3224 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3225 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3226 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3227 3228 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3229 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3230 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3231 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3232 3233 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3234 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3235 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3236 3237 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3238 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3239 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3240 3241 /** 3242 * Definition of a replay_state. 3243 */ 3244 enum replay_state { 3245 REPLAY_STATE_0 = 0x0, 3246 REPLAY_STATE_1 = 0x10, 3247 REPLAY_STATE_1A = 0x11, 3248 REPLAY_STATE_2 = 0x20, 3249 REPLAY_STATE_3 = 0x30, 3250 REPLAY_STATE_3INIT = 0x31, 3251 REPLAY_STATE_4 = 0x40, 3252 REPLAY_STATE_4A = 0x41, 3253 REPLAY_STATE_4B = 0x42, 3254 REPLAY_STATE_4C = 0x43, 3255 REPLAY_STATE_4D = 0x44, 3256 REPLAY_STATE_4B_LOCKED = 0x4A, 3257 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3258 REPLAY_STATE_5 = 0x50, 3259 REPLAY_STATE_5A = 0x51, 3260 REPLAY_STATE_5B = 0x52, 3261 REPLAY_STATE_5A_LOCKED = 0x5A, 3262 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3263 REPLAY_STATE_6 = 0x60, 3264 REPLAY_STATE_6A = 0x61, 3265 REPLAY_STATE_6B = 0x62, 3266 REPLAY_STATE_INVALID = 0xFF, 3267 }; 3268 3269 /** 3270 * Replay command sub-types. 3271 */ 3272 enum dmub_cmd_replay_type { 3273 /** 3274 * Copy driver-calculated parameters to REPLAY state. 3275 */ 3276 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3277 /** 3278 * Enable REPLAY. 3279 */ 3280 DMUB_CMD__REPLAY_ENABLE = 1, 3281 /** 3282 * Set Replay power option. 3283 */ 3284 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3285 /** 3286 * Set coasting vtotal. 3287 */ 3288 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3289 /** 3290 * Set power opt and coasting vtotal. 3291 */ 3292 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3293 /** 3294 * Set disabled iiming sync. 3295 */ 3296 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3297 /** 3298 * Set Residency Frameupdate Timer. 3299 */ 3300 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3301 /** 3302 * Set pseudo vtotal 3303 */ 3304 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3305 /** 3306 * Set adaptive sync sdp enabled 3307 */ 3308 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3309 3310 }; 3311 3312 /** 3313 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3314 */ 3315 struct dmub_cmd_replay_copy_settings_data { 3316 /** 3317 * Flags that can be set by driver to change some replay behaviour. 3318 */ 3319 union replay_debug_flags debug; 3320 3321 /** 3322 * @flags: Flags used to determine feature functionality. 3323 */ 3324 union replay_hw_flags flags; 3325 3326 /** 3327 * DPP HW instance. 3328 */ 3329 uint8_t dpp_inst; 3330 /** 3331 * OTG HW instance. 3332 */ 3333 uint8_t otg_inst; 3334 /** 3335 * DIG FE HW instance. 3336 */ 3337 uint8_t digfe_inst; 3338 /** 3339 * DIG BE HW instance. 3340 */ 3341 uint8_t digbe_inst; 3342 /** 3343 * AUX HW instance. 3344 */ 3345 uint8_t aux_inst; 3346 /** 3347 * Panel Instance. 3348 * Panel isntance to identify which psr_state to use 3349 * Currently the support is only for 0 or 1 3350 */ 3351 uint8_t panel_inst; 3352 /** 3353 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3354 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3355 */ 3356 uint8_t pixel_deviation_per_line; 3357 /** 3358 * @max_deviation_line: The max number of deviation line that can keep the timing 3359 * synchronized between the Source and Sink during Replay normal sleep mode. 3360 */ 3361 uint8_t max_deviation_line; 3362 /** 3363 * Length of each horizontal line in ns. 3364 */ 3365 uint32_t line_time_in_ns; 3366 /** 3367 * PHY instance. 3368 */ 3369 uint8_t dpphy_inst; 3370 /** 3371 * Determines if SMU optimzations are enabled/disabled. 3372 */ 3373 uint8_t smu_optimizations_en; 3374 /** 3375 * Determines if timing sync are enabled/disabled. 3376 */ 3377 uint8_t replay_timing_sync_supported; 3378 /* 3379 * Use FSM state for Replay power up/down 3380 */ 3381 uint8_t use_phy_fsm; 3382 }; 3383 3384 /** 3385 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3386 */ 3387 struct dmub_rb_cmd_replay_copy_settings { 3388 /** 3389 * Command header. 3390 */ 3391 struct dmub_cmd_header header; 3392 /** 3393 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3394 */ 3395 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3396 }; 3397 3398 /** 3399 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3400 */ 3401 enum replay_enable { 3402 /** 3403 * Disable REPLAY. 3404 */ 3405 REPLAY_DISABLE = 0, 3406 /** 3407 * Enable REPLAY. 3408 */ 3409 REPLAY_ENABLE = 1, 3410 }; 3411 3412 /** 3413 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3414 */ 3415 struct dmub_rb_cmd_replay_enable_data { 3416 /** 3417 * Replay enable or disable. 3418 */ 3419 uint8_t enable; 3420 /** 3421 * Panel Instance. 3422 * Panel isntance to identify which replay_state to use 3423 * Currently the support is only for 0 or 1 3424 */ 3425 uint8_t panel_inst; 3426 /** 3427 * Phy state to enter. 3428 * Values to use are defined in dmub_phy_fsm_state 3429 */ 3430 uint8_t phy_fsm_state; 3431 /** 3432 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3433 * Set this using enum phy_link_rate. 3434 * This does not support HDMI/DP2 for now. 3435 */ 3436 uint8_t phy_rate; 3437 }; 3438 3439 /** 3440 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3441 * Replay enable/disable is controlled using action in data. 3442 */ 3443 struct dmub_rb_cmd_replay_enable { 3444 /** 3445 * Command header. 3446 */ 3447 struct dmub_cmd_header header; 3448 3449 struct dmub_rb_cmd_replay_enable_data data; 3450 }; 3451 3452 /** 3453 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3454 */ 3455 struct dmub_cmd_replay_set_power_opt_data { 3456 /** 3457 * Panel Instance. 3458 * Panel isntance to identify which replay_state to use 3459 * Currently the support is only for 0 or 1 3460 */ 3461 uint8_t panel_inst; 3462 /** 3463 * Explicit padding to 4 byte boundary. 3464 */ 3465 uint8_t pad[3]; 3466 /** 3467 * REPLAY power option 3468 */ 3469 uint32_t power_opt; 3470 }; 3471 3472 /** 3473 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3474 */ 3475 struct dmub_cmd_replay_set_timing_sync_data { 3476 /** 3477 * Panel Instance. 3478 * Panel isntance to identify which replay_state to use 3479 * Currently the support is only for 0 or 1 3480 */ 3481 uint8_t panel_inst; 3482 /** 3483 * REPLAY set_timing_sync 3484 */ 3485 uint8_t timing_sync_supported; 3486 /** 3487 * Explicit padding to 4 byte boundary. 3488 */ 3489 uint8_t pad[2]; 3490 }; 3491 3492 /** 3493 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3494 */ 3495 struct dmub_cmd_replay_set_pseudo_vtotal { 3496 /** 3497 * Panel Instance. 3498 * Panel isntance to identify which replay_state to use 3499 * Currently the support is only for 0 or 1 3500 */ 3501 uint8_t panel_inst; 3502 /** 3503 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3504 */ 3505 uint16_t vtotal; 3506 /** 3507 * Explicit padding to 4 byte boundary. 3508 */ 3509 uint8_t pad; 3510 }; 3511 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3512 /** 3513 * Panel Instance. 3514 * Panel isntance to identify which replay_state to use 3515 * Currently the support is only for 0 or 1 3516 */ 3517 uint8_t panel_inst; 3518 /** 3519 * enabled: set adaptive sync sdp enabled 3520 */ 3521 uint8_t force_disabled; 3522 3523 uint8_t pad[2]; 3524 }; 3525 3526 /** 3527 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3528 */ 3529 struct dmub_rb_cmd_replay_set_power_opt { 3530 /** 3531 * Command header. 3532 */ 3533 struct dmub_cmd_header header; 3534 /** 3535 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3536 */ 3537 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3538 }; 3539 3540 /** 3541 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3542 */ 3543 struct dmub_cmd_replay_set_coasting_vtotal_data { 3544 /** 3545 * 16-bit value dicated by driver that indicates the coasting vtotal. 3546 */ 3547 uint16_t coasting_vtotal; 3548 /** 3549 * REPLAY control version. 3550 */ 3551 uint8_t cmd_version; 3552 /** 3553 * Panel Instance. 3554 * Panel isntance to identify which replay_state to use 3555 * Currently the support is only for 0 or 1 3556 */ 3557 uint8_t panel_inst; 3558 /** 3559 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3560 */ 3561 uint16_t coasting_vtotal_high; 3562 /** 3563 * Explicit padding to 4 byte boundary. 3564 */ 3565 uint8_t pad[2]; 3566 }; 3567 3568 /** 3569 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3570 */ 3571 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3572 /** 3573 * Command header. 3574 */ 3575 struct dmub_cmd_header header; 3576 /** 3577 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3578 */ 3579 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3580 }; 3581 3582 /** 3583 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3584 */ 3585 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3586 /** 3587 * Command header. 3588 */ 3589 struct dmub_cmd_header header; 3590 /** 3591 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3592 */ 3593 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3594 /** 3595 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3596 */ 3597 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3598 }; 3599 3600 /** 3601 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3602 */ 3603 struct dmub_rb_cmd_replay_set_timing_sync { 3604 /** 3605 * Command header. 3606 */ 3607 struct dmub_cmd_header header; 3608 /** 3609 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3610 */ 3611 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3612 }; 3613 3614 /** 3615 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3616 */ 3617 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3618 /** 3619 * Command header. 3620 */ 3621 struct dmub_cmd_header header; 3622 /** 3623 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3624 */ 3625 struct dmub_cmd_replay_set_pseudo_vtotal data; 3626 }; 3627 3628 /** 3629 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3630 */ 3631 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3632 /** 3633 * Command header. 3634 */ 3635 struct dmub_cmd_header header; 3636 /** 3637 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3638 */ 3639 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3640 }; 3641 3642 /** 3643 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3644 */ 3645 struct dmub_cmd_replay_frameupdate_timer_data { 3646 /** 3647 * Panel Instance. 3648 * Panel isntance to identify which replay_state to use 3649 * Currently the support is only for 0 or 1 3650 */ 3651 uint8_t panel_inst; 3652 /** 3653 * Replay Frameupdate Timer Enable or not 3654 */ 3655 uint8_t enable; 3656 /** 3657 * REPLAY force reflash frame update number 3658 */ 3659 uint16_t frameupdate_count; 3660 }; 3661 /** 3662 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3663 */ 3664 struct dmub_rb_cmd_replay_set_frameupdate_timer { 3665 /** 3666 * Command header. 3667 */ 3668 struct dmub_cmd_header header; 3669 /** 3670 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3671 */ 3672 struct dmub_cmd_replay_frameupdate_timer_data data; 3673 }; 3674 3675 /** 3676 * Definition union of replay command set 3677 */ 3678 union dmub_replay_cmd_set { 3679 /** 3680 * Panel Instance. 3681 * Panel isntance to identify which replay_state to use 3682 * Currently the support is only for 0 or 1 3683 */ 3684 uint8_t panel_inst; 3685 /** 3686 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 3687 */ 3688 struct dmub_cmd_replay_set_timing_sync_data sync_data; 3689 /** 3690 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 3691 */ 3692 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 3693 /** 3694 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 3695 */ 3696 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 3697 /** 3698 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 3699 */ 3700 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 3701 3702 }; 3703 3704 /** 3705 * Set of HW components that can be locked. 3706 * 3707 * Note: If updating with more HW components, fields 3708 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3709 */ 3710 union dmub_hw_lock_flags { 3711 /** 3712 * Set of HW components that can be locked. 3713 */ 3714 struct { 3715 /** 3716 * Lock/unlock OTG master update lock. 3717 */ 3718 uint8_t lock_pipe : 1; 3719 /** 3720 * Lock/unlock cursor. 3721 */ 3722 uint8_t lock_cursor : 1; 3723 /** 3724 * Lock/unlock global update lock. 3725 */ 3726 uint8_t lock_dig : 1; 3727 /** 3728 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3729 */ 3730 uint8_t triple_buffer_lock : 1; 3731 } bits; 3732 3733 /** 3734 * Union for HW Lock flags. 3735 */ 3736 uint8_t u8All; 3737 }; 3738 3739 /** 3740 * Instances of HW to be locked. 3741 * 3742 * Note: If updating with more HW components, fields 3743 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3744 */ 3745 struct dmub_hw_lock_inst_flags { 3746 /** 3747 * OTG HW instance for OTG master update lock. 3748 */ 3749 uint8_t otg_inst; 3750 /** 3751 * OPP instance for cursor lock. 3752 */ 3753 uint8_t opp_inst; 3754 /** 3755 * OTG HW instance for global update lock. 3756 * TODO: Remove, and re-use otg_inst. 3757 */ 3758 uint8_t dig_inst; 3759 /** 3760 * Explicit pad to 4 byte boundary. 3761 */ 3762 uint8_t pad; 3763 }; 3764 3765 /** 3766 * Clients that can acquire the HW Lock Manager. 3767 * 3768 * Note: If updating with more clients, fields in 3769 * dmub_inbox0_cmd_lock_hw must be updated to match. 3770 */ 3771 enum hw_lock_client { 3772 /** 3773 * Driver is the client of HW Lock Manager. 3774 */ 3775 HW_LOCK_CLIENT_DRIVER = 0, 3776 /** 3777 * PSR SU is the client of HW Lock Manager. 3778 */ 3779 HW_LOCK_CLIENT_PSR_SU = 1, 3780 HW_LOCK_CLIENT_SUBVP = 3, 3781 /** 3782 * Replay is the client of HW Lock Manager. 3783 */ 3784 HW_LOCK_CLIENT_REPLAY = 4, 3785 HW_LOCK_CLIENT_FAMS2 = 5, 3786 /** 3787 * Invalid client. 3788 */ 3789 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3790 }; 3791 3792 /** 3793 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3794 */ 3795 struct dmub_cmd_lock_hw_data { 3796 /** 3797 * Specifies the client accessing HW Lock Manager. 3798 */ 3799 enum hw_lock_client client; 3800 /** 3801 * HW instances to be locked. 3802 */ 3803 struct dmub_hw_lock_inst_flags inst_flags; 3804 /** 3805 * Which components to be locked. 3806 */ 3807 union dmub_hw_lock_flags hw_locks; 3808 /** 3809 * Specifies lock/unlock. 3810 */ 3811 uint8_t lock; 3812 /** 3813 * HW can be unlocked separately from releasing the HW Lock Mgr. 3814 * This flag is set if the client wishes to release the object. 3815 */ 3816 uint8_t should_release; 3817 /** 3818 * Explicit padding to 4 byte boundary. 3819 */ 3820 uint8_t pad; 3821 }; 3822 3823 /** 3824 * Definition of a DMUB_CMD__HW_LOCK command. 3825 * Command is used by driver and FW. 3826 */ 3827 struct dmub_rb_cmd_lock_hw { 3828 /** 3829 * Command header. 3830 */ 3831 struct dmub_cmd_header header; 3832 /** 3833 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3834 */ 3835 struct dmub_cmd_lock_hw_data lock_hw_data; 3836 }; 3837 3838 /** 3839 * ABM command sub-types. 3840 */ 3841 enum dmub_cmd_abm_type { 3842 /** 3843 * Initialize parameters for ABM algorithm. 3844 * Data is passed through an indirect buffer. 3845 */ 3846 DMUB_CMD__ABM_INIT_CONFIG = 0, 3847 /** 3848 * Set OTG and panel HW instance. 3849 */ 3850 DMUB_CMD__ABM_SET_PIPE = 1, 3851 /** 3852 * Set user requested backklight level. 3853 */ 3854 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3855 /** 3856 * Set ABM operating/aggression level. 3857 */ 3858 DMUB_CMD__ABM_SET_LEVEL = 3, 3859 /** 3860 * Set ambient light level. 3861 */ 3862 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 3863 /** 3864 * Enable/disable fractional duty cycle for backlight PWM. 3865 */ 3866 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 3867 3868 /** 3869 * unregister vertical interrupt after steady state is reached 3870 */ 3871 DMUB_CMD__ABM_PAUSE = 6, 3872 3873 /** 3874 * Save and Restore ABM state. On save we save parameters, and 3875 * on restore we update state with passed in data. 3876 */ 3877 DMUB_CMD__ABM_SAVE_RESTORE = 7, 3878 3879 /** 3880 * Query ABM caps. 3881 */ 3882 DMUB_CMD__ABM_QUERY_CAPS = 8, 3883 }; 3884 3885 struct abm_ace_curve { 3886 /** 3887 * @offsets: ACE curve offsets. 3888 */ 3889 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 3890 3891 /** 3892 * @thresholds: ACE curve thresholds. 3893 */ 3894 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 3895 3896 /** 3897 * @slopes: ACE curve slopes. 3898 */ 3899 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 3900 }; 3901 3902 struct fixed_pt_format { 3903 /** 3904 * @sign_bit: Indicates whether one bit is reserved for the sign. 3905 */ 3906 bool sign_bit; 3907 3908 /** 3909 * @num_int_bits: Number of bits used for integer part. 3910 */ 3911 uint8_t num_int_bits; 3912 3913 /** 3914 * @num_frac_bits: Number of bits used for fractional part. 3915 */ 3916 uint8_t num_frac_bits; 3917 3918 /** 3919 * @pad: Explicit padding to 4 byte boundary. 3920 */ 3921 uint8_t pad; 3922 }; 3923 3924 struct abm_caps { 3925 /** 3926 * @num_hg_bins: Number of histogram bins. 3927 */ 3928 uint8_t num_hg_bins; 3929 3930 /** 3931 * @num_ace_segments: Number of ACE curve segments. 3932 */ 3933 uint8_t num_ace_segments; 3934 3935 /** 3936 * @pad: Explicit padding to 4 byte boundary. 3937 */ 3938 uint8_t pad[2]; 3939 3940 /** 3941 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 3942 */ 3943 struct fixed_pt_format ace_thresholds_format; 3944 3945 /** 3946 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 3947 */ 3948 struct fixed_pt_format ace_offsets_format; 3949 3950 /** 3951 * @ace_slopes_format: Format of the ACE slopes. 3952 */ 3953 struct fixed_pt_format ace_slopes_format; 3954 }; 3955 3956 /** 3957 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 3958 * Requirements: 3959 * - Padded explicitly to 32-bit boundary. 3960 * - Must ensure this structure matches the one on driver-side, 3961 * otherwise it won't be aligned. 3962 */ 3963 struct abm_config_table { 3964 /** 3965 * Gamma curve thresholds, used for crgb conversion. 3966 */ 3967 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 3968 /** 3969 * Gamma curve offsets, used for crgb conversion. 3970 */ 3971 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 3972 /** 3973 * Gamma curve slopes, used for crgb conversion. 3974 */ 3975 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 3976 /** 3977 * Custom backlight curve thresholds. 3978 */ 3979 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 3980 /** 3981 * Custom backlight curve offsets. 3982 */ 3983 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 3984 /** 3985 * Ambient light thresholds. 3986 */ 3987 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 3988 /** 3989 * Minimum programmable backlight. 3990 */ 3991 uint16_t min_abm_backlight; // 122B 3992 /** 3993 * Minimum reduction values. 3994 */ 3995 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 3996 /** 3997 * Maximum reduction values. 3998 */ 3999 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4000 /** 4001 * Bright positive gain. 4002 */ 4003 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4004 /** 4005 * Dark negative gain. 4006 */ 4007 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4008 /** 4009 * Hybrid factor. 4010 */ 4011 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4012 /** 4013 * Contrast factor. 4014 */ 4015 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4016 /** 4017 * Deviation gain. 4018 */ 4019 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4020 /** 4021 * Minimum knee. 4022 */ 4023 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4024 /** 4025 * Maximum knee. 4026 */ 4027 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4028 /** 4029 * Unused. 4030 */ 4031 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4032 /** 4033 * Explicit padding to 4 byte boundary. 4034 */ 4035 uint8_t pad3[3]; // 229B 4036 /** 4037 * Backlight ramp reduction. 4038 */ 4039 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4040 /** 4041 * Backlight ramp start. 4042 */ 4043 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4044 }; 4045 4046 /** 4047 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4048 */ 4049 struct dmub_cmd_abm_set_pipe_data { 4050 /** 4051 * OTG HW instance. 4052 */ 4053 uint8_t otg_inst; 4054 4055 /** 4056 * Panel Control HW instance. 4057 */ 4058 uint8_t panel_inst; 4059 4060 /** 4061 * Controls how ABM will interpret a set pipe or set level command. 4062 */ 4063 uint8_t set_pipe_option; 4064 4065 /** 4066 * Unused. 4067 * TODO: Remove. 4068 */ 4069 uint8_t ramping_boundary; 4070 4071 /** 4072 * PwrSeq HW Instance. 4073 */ 4074 uint8_t pwrseq_inst; 4075 4076 /** 4077 * Explicit padding to 4 byte boundary. 4078 */ 4079 uint8_t pad[3]; 4080 }; 4081 4082 /** 4083 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4084 */ 4085 struct dmub_rb_cmd_abm_set_pipe { 4086 /** 4087 * Command header. 4088 */ 4089 struct dmub_cmd_header header; 4090 4091 /** 4092 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4093 */ 4094 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4095 }; 4096 4097 /** 4098 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4099 */ 4100 struct dmub_cmd_abm_set_backlight_data { 4101 /** 4102 * Number of frames to ramp to backlight user level. 4103 */ 4104 uint32_t frame_ramp; 4105 4106 /** 4107 * Requested backlight level from user. 4108 */ 4109 uint32_t backlight_user_level; 4110 4111 /** 4112 * ABM control version. 4113 */ 4114 uint8_t version; 4115 4116 /** 4117 * Panel Control HW instance mask. 4118 * Bit 0 is Panel Control HW instance 0. 4119 * Bit 1 is Panel Control HW instance 1. 4120 */ 4121 uint8_t panel_mask; 4122 4123 /** 4124 * Explicit padding to 4 byte boundary. 4125 */ 4126 uint8_t pad[2]; 4127 }; 4128 4129 /** 4130 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4131 */ 4132 struct dmub_rb_cmd_abm_set_backlight { 4133 /** 4134 * Command header. 4135 */ 4136 struct dmub_cmd_header header; 4137 4138 /** 4139 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4140 */ 4141 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4142 }; 4143 4144 /** 4145 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4146 */ 4147 struct dmub_cmd_abm_set_level_data { 4148 /** 4149 * Set current ABM operating/aggression level. 4150 */ 4151 uint32_t level; 4152 4153 /** 4154 * ABM control version. 4155 */ 4156 uint8_t version; 4157 4158 /** 4159 * Panel Control HW instance mask. 4160 * Bit 0 is Panel Control HW instance 0. 4161 * Bit 1 is Panel Control HW instance 1. 4162 */ 4163 uint8_t panel_mask; 4164 4165 /** 4166 * Explicit padding to 4 byte boundary. 4167 */ 4168 uint8_t pad[2]; 4169 }; 4170 4171 /** 4172 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4173 */ 4174 struct dmub_rb_cmd_abm_set_level { 4175 /** 4176 * Command header. 4177 */ 4178 struct dmub_cmd_header header; 4179 4180 /** 4181 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4182 */ 4183 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4184 }; 4185 4186 /** 4187 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4188 */ 4189 struct dmub_cmd_abm_set_ambient_level_data { 4190 /** 4191 * Ambient light sensor reading from OS. 4192 */ 4193 uint32_t ambient_lux; 4194 4195 /** 4196 * ABM control version. 4197 */ 4198 uint8_t version; 4199 4200 /** 4201 * Panel Control HW instance mask. 4202 * Bit 0 is Panel Control HW instance 0. 4203 * Bit 1 is Panel Control HW instance 1. 4204 */ 4205 uint8_t panel_mask; 4206 4207 /** 4208 * Explicit padding to 4 byte boundary. 4209 */ 4210 uint8_t pad[2]; 4211 }; 4212 4213 /** 4214 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4215 */ 4216 struct dmub_rb_cmd_abm_set_ambient_level { 4217 /** 4218 * Command header. 4219 */ 4220 struct dmub_cmd_header header; 4221 4222 /** 4223 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4224 */ 4225 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4226 }; 4227 4228 /** 4229 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4230 */ 4231 struct dmub_cmd_abm_set_pwm_frac_data { 4232 /** 4233 * Enable/disable fractional duty cycle for backlight PWM. 4234 * TODO: Convert to uint8_t. 4235 */ 4236 uint32_t fractional_pwm; 4237 4238 /** 4239 * ABM control version. 4240 */ 4241 uint8_t version; 4242 4243 /** 4244 * Panel Control HW instance mask. 4245 * Bit 0 is Panel Control HW instance 0. 4246 * Bit 1 is Panel Control HW instance 1. 4247 */ 4248 uint8_t panel_mask; 4249 4250 /** 4251 * Explicit padding to 4 byte boundary. 4252 */ 4253 uint8_t pad[2]; 4254 }; 4255 4256 /** 4257 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4258 */ 4259 struct dmub_rb_cmd_abm_set_pwm_frac { 4260 /** 4261 * Command header. 4262 */ 4263 struct dmub_cmd_header header; 4264 4265 /** 4266 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4267 */ 4268 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4269 }; 4270 4271 /** 4272 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4273 */ 4274 struct dmub_cmd_abm_init_config_data { 4275 /** 4276 * Location of indirect buffer used to pass init data to ABM. 4277 */ 4278 union dmub_addr src; 4279 4280 /** 4281 * Indirect buffer length. 4282 */ 4283 uint16_t bytes; 4284 4285 4286 /** 4287 * ABM control version. 4288 */ 4289 uint8_t version; 4290 4291 /** 4292 * Panel Control HW instance mask. 4293 * Bit 0 is Panel Control HW instance 0. 4294 * Bit 1 is Panel Control HW instance 1. 4295 */ 4296 uint8_t panel_mask; 4297 4298 /** 4299 * Explicit padding to 4 byte boundary. 4300 */ 4301 uint8_t pad[2]; 4302 }; 4303 4304 /** 4305 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4306 */ 4307 struct dmub_rb_cmd_abm_init_config { 4308 /** 4309 * Command header. 4310 */ 4311 struct dmub_cmd_header header; 4312 4313 /** 4314 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4315 */ 4316 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4317 }; 4318 4319 /** 4320 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4321 */ 4322 4323 struct dmub_cmd_abm_pause_data { 4324 4325 /** 4326 * Panel Control HW instance mask. 4327 * Bit 0 is Panel Control HW instance 0. 4328 * Bit 1 is Panel Control HW instance 1. 4329 */ 4330 uint8_t panel_mask; 4331 4332 /** 4333 * OTG hw instance 4334 */ 4335 uint8_t otg_inst; 4336 4337 /** 4338 * Enable or disable ABM pause 4339 */ 4340 uint8_t enable; 4341 4342 /** 4343 * Explicit padding to 4 byte boundary. 4344 */ 4345 uint8_t pad[1]; 4346 }; 4347 4348 /** 4349 * Definition of a DMUB_CMD__ABM_PAUSE command. 4350 */ 4351 struct dmub_rb_cmd_abm_pause { 4352 /** 4353 * Command header. 4354 */ 4355 struct dmub_cmd_header header; 4356 4357 /** 4358 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4359 */ 4360 struct dmub_cmd_abm_pause_data abm_pause_data; 4361 }; 4362 4363 /** 4364 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4365 */ 4366 struct dmub_cmd_abm_query_caps_in { 4367 /** 4368 * Panel instance. 4369 */ 4370 uint8_t panel_inst; 4371 4372 /** 4373 * Explicit padding to 4 byte boundary. 4374 */ 4375 uint8_t pad[3]; 4376 }; 4377 4378 /** 4379 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4380 */ 4381 struct dmub_cmd_abm_query_caps_out { 4382 /** 4383 * SW Algorithm caps. 4384 */ 4385 struct abm_caps sw_caps; 4386 4387 /** 4388 * ABM HW caps. 4389 */ 4390 struct abm_caps hw_caps; 4391 }; 4392 4393 /** 4394 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4395 */ 4396 struct dmub_rb_cmd_abm_query_caps { 4397 /** 4398 * Command header. 4399 */ 4400 struct dmub_cmd_header header; 4401 4402 /** 4403 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4404 */ 4405 union { 4406 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4407 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4408 } data; 4409 }; 4410 4411 /** 4412 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4413 */ 4414 struct dmub_rb_cmd_abm_save_restore { 4415 /** 4416 * Command header. 4417 */ 4418 struct dmub_cmd_header header; 4419 4420 /** 4421 * OTG hw instance 4422 */ 4423 uint8_t otg_inst; 4424 4425 /** 4426 * Enable or disable ABM pause 4427 */ 4428 uint8_t freeze; 4429 4430 /** 4431 * Explicit padding to 4 byte boundary. 4432 */ 4433 uint8_t debug; 4434 4435 /** 4436 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4437 */ 4438 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4439 }; 4440 4441 /** 4442 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4443 */ 4444 struct dmub_cmd_query_feature_caps_data { 4445 /** 4446 * DMUB feature capabilities. 4447 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4448 */ 4449 struct dmub_feature_caps feature_caps; 4450 }; 4451 4452 /** 4453 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4454 */ 4455 struct dmub_rb_cmd_query_feature_caps { 4456 /** 4457 * Command header. 4458 */ 4459 struct dmub_cmd_header header; 4460 /** 4461 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4462 */ 4463 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4464 }; 4465 4466 /** 4467 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4468 */ 4469 struct dmub_cmd_visual_confirm_color_data { 4470 /** 4471 * DMUB visual confirm color 4472 */ 4473 struct dmub_visual_confirm_color visual_confirm_color; 4474 }; 4475 4476 /** 4477 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4478 */ 4479 struct dmub_rb_cmd_get_visual_confirm_color { 4480 /** 4481 * Command header. 4482 */ 4483 struct dmub_cmd_header header; 4484 /** 4485 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4486 */ 4487 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4488 }; 4489 4490 /** 4491 * enum dmub_cmd_panel_cntl_type - Panel control command. 4492 */ 4493 enum dmub_cmd_panel_cntl_type { 4494 /** 4495 * Initializes embedded panel hardware blocks. 4496 */ 4497 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4498 /** 4499 * Queries backlight info for the embedded panel. 4500 */ 4501 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4502 /** 4503 * Sets the PWM Freq as per user's requirement. 4504 */ 4505 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 4506 }; 4507 4508 /** 4509 * struct dmub_cmd_panel_cntl_data - Panel control data. 4510 */ 4511 struct dmub_cmd_panel_cntl_data { 4512 uint32_t pwrseq_inst; /**< pwrseq instance */ 4513 uint32_t current_backlight; /* in/out */ 4514 uint32_t bl_pwm_cntl; /* in/out */ 4515 uint32_t bl_pwm_period_cntl; /* in/out */ 4516 uint32_t bl_pwm_ref_div1; /* in/out */ 4517 uint8_t is_backlight_on : 1; /* in/out */ 4518 uint8_t is_powered_on : 1; /* in/out */ 4519 uint8_t padding[3]; 4520 uint32_t bl_pwm_ref_div2; /* in/out */ 4521 uint8_t reserved[4]; 4522 }; 4523 4524 /** 4525 * struct dmub_rb_cmd_panel_cntl - Panel control command. 4526 */ 4527 struct dmub_rb_cmd_panel_cntl { 4528 struct dmub_cmd_header header; /**< header */ 4529 struct dmub_cmd_panel_cntl_data data; /**< payload */ 4530 }; 4531 4532 struct dmub_optc_state { 4533 uint32_t v_total_max; 4534 uint32_t v_total_min; 4535 uint32_t tg_inst; 4536 }; 4537 4538 struct dmub_rb_cmd_drr_update { 4539 struct dmub_cmd_header header; 4540 struct dmub_optc_state dmub_optc_state_req; 4541 }; 4542 4543 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 4544 uint32_t pix_clk_100hz; 4545 uint8_t max_ramp_step; 4546 uint8_t pipes; 4547 uint8_t min_refresh_in_hz; 4548 uint8_t pipe_count; 4549 uint8_t pipe_index[4]; 4550 }; 4551 4552 struct dmub_cmd_fw_assisted_mclk_switch_config { 4553 uint8_t fams_enabled; 4554 uint8_t visual_confirm_enabled; 4555 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 4556 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 4557 }; 4558 4559 struct dmub_rb_cmd_fw_assisted_mclk_switch { 4560 struct dmub_cmd_header header; 4561 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 4562 }; 4563 4564 /** 4565 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4566 */ 4567 struct dmub_cmd_lvtma_control_data { 4568 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 4569 uint8_t bypass_panel_control_wait; 4570 uint8_t reserved_0[2]; /**< For future use */ 4571 uint8_t pwrseq_inst; /**< LVTMA control instance */ 4572 uint8_t reserved_1[3]; /**< For future use */ 4573 }; 4574 4575 /** 4576 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4577 */ 4578 struct dmub_rb_cmd_lvtma_control { 4579 /** 4580 * Command header. 4581 */ 4582 struct dmub_cmd_header header; 4583 /** 4584 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4585 */ 4586 struct dmub_cmd_lvtma_control_data data; 4587 }; 4588 4589 /** 4590 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4591 */ 4592 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 4593 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4594 uint8_t is_usb; /**< is phy is usb */ 4595 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 4596 uint8_t is_dp4; /**< is dp in 4 lane */ 4597 }; 4598 4599 /** 4600 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4601 */ 4602 struct dmub_rb_cmd_transmitter_query_dp_alt { 4603 struct dmub_cmd_header header; /**< header */ 4604 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 4605 }; 4606 4607 struct phy_test_mode { 4608 uint8_t mode; 4609 uint8_t pat0; 4610 uint8_t pad[2]; 4611 }; 4612 4613 /** 4614 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4615 */ 4616 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 4617 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4618 uint8_t mode; /**< HDMI/DP/DP2 etc */ 4619 uint8_t lane_num; /**< Number of lanes */ 4620 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 4621 struct phy_test_mode test_mode; 4622 enum dmub_phy_fsm_state state; 4623 uint32_t status; 4624 uint8_t pad; 4625 }; 4626 4627 /** 4628 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4629 */ 4630 struct dmub_rb_cmd_transmitter_set_phy_fsm { 4631 struct dmub_cmd_header header; /**< header */ 4632 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 4633 }; 4634 4635 /** 4636 * Maximum number of bytes a chunk sent to DMUB for parsing 4637 */ 4638 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 4639 4640 /** 4641 * Represent a chunk of CEA blocks sent to DMUB for parsing 4642 */ 4643 struct dmub_cmd_send_edid_cea { 4644 uint16_t offset; /**< offset into the CEA block */ 4645 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 4646 uint16_t cea_total_length; /**< total length of the CEA block */ 4647 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 4648 uint8_t pad[3]; /**< padding and for future expansion */ 4649 }; 4650 4651 /** 4652 * Result of VSDB parsing from CEA block 4653 */ 4654 struct dmub_cmd_edid_cea_amd_vsdb { 4655 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 4656 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 4657 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 4658 uint16_t min_frame_rate; /**< Maximum frame rate */ 4659 uint16_t max_frame_rate; /**< Minimum frame rate */ 4660 }; 4661 4662 /** 4663 * Result of sending a CEA chunk 4664 */ 4665 struct dmub_cmd_edid_cea_ack { 4666 uint16_t offset; /**< offset of the chunk into the CEA block */ 4667 uint8_t success; /**< 1 if this sending of chunk succeeded */ 4668 uint8_t pad; /**< padding and for future expansion */ 4669 }; 4670 4671 /** 4672 * Specify whether the result is an ACK/NACK or the parsing has finished 4673 */ 4674 enum dmub_cmd_edid_cea_reply_type { 4675 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 4676 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 4677 }; 4678 4679 /** 4680 * Definition of a DMUB_CMD__EDID_CEA command. 4681 */ 4682 struct dmub_rb_cmd_edid_cea { 4683 struct dmub_cmd_header header; /**< Command header */ 4684 union dmub_cmd_edid_cea_data { 4685 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 4686 struct dmub_cmd_edid_cea_output { /**< output with results */ 4687 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 4688 union { 4689 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 4690 struct dmub_cmd_edid_cea_ack ack; 4691 }; 4692 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 4693 } data; /**< Command data */ 4694 4695 }; 4696 4697 /** 4698 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 4699 */ 4700 struct dmub_cmd_cable_id_input { 4701 uint8_t phy_inst; /**< phy inst for cable id data */ 4702 }; 4703 4704 /** 4705 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 4706 */ 4707 struct dmub_cmd_cable_id_output { 4708 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 4709 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 4710 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 4711 uint8_t RESERVED :2; /**< reserved means not defined */ 4712 }; 4713 4714 /** 4715 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 4716 */ 4717 struct dmub_rb_cmd_get_usbc_cable_id { 4718 struct dmub_cmd_header header; /**< Command header */ 4719 /** 4720 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 4721 */ 4722 union dmub_cmd_cable_id_data { 4723 struct dmub_cmd_cable_id_input input; /**< Input */ 4724 struct dmub_cmd_cable_id_output output; /**< Output */ 4725 uint8_t output_raw; /**< Raw data output */ 4726 } data; 4727 }; 4728 4729 /** 4730 * Command type of a DMUB_CMD__SECURE_DISPLAY command 4731 */ 4732 enum dmub_cmd_secure_display_type { 4733 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 4734 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 4735 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 4736 }; 4737 4738 /** 4739 * Definition of a DMUB_CMD__SECURE_DISPLAY command 4740 */ 4741 struct dmub_rb_cmd_secure_display { 4742 struct dmub_cmd_header header; 4743 /** 4744 * Data passed from driver to dmub firmware. 4745 */ 4746 struct dmub_cmd_roi_info { 4747 uint16_t x_start; 4748 uint16_t x_end; 4749 uint16_t y_start; 4750 uint16_t y_end; 4751 uint8_t otg_id; 4752 uint8_t phy_id; 4753 } roi_info; 4754 }; 4755 4756 /** 4757 * Command type of a DMUB_CMD__PSP command 4758 */ 4759 enum dmub_cmd_psp_type { 4760 DMUB_CMD__PSP_ASSR_ENABLE = 0 4761 }; 4762 4763 /** 4764 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 4765 */ 4766 struct dmub_cmd_assr_enable_data { 4767 /** 4768 * ASSR enable or disable. 4769 */ 4770 uint8_t enable; 4771 /** 4772 * PHY port type. 4773 * Indicates eDP / non-eDP port type 4774 */ 4775 uint8_t phy_port_type; 4776 /** 4777 * PHY port ID. 4778 */ 4779 uint8_t phy_port_id; 4780 /** 4781 * Link encoder index. 4782 */ 4783 uint8_t link_enc_index; 4784 /** 4785 * HPO mode. 4786 */ 4787 uint8_t hpo_mode; 4788 4789 /** 4790 * Reserved field. 4791 */ 4792 uint8_t reserved[7]; 4793 }; 4794 4795 /** 4796 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 4797 */ 4798 struct dmub_rb_cmd_assr_enable { 4799 /** 4800 * Command header. 4801 */ 4802 struct dmub_cmd_header header; 4803 4804 /** 4805 * Assr data. 4806 */ 4807 struct dmub_cmd_assr_enable_data assr_data; 4808 4809 /** 4810 * Reserved field. 4811 */ 4812 uint32_t reserved[3]; 4813 }; 4814 4815 /** 4816 * union dmub_rb_cmd - DMUB inbox command. 4817 */ 4818 union dmub_rb_cmd { 4819 /** 4820 * Elements shared with all commands. 4821 */ 4822 struct dmub_rb_cmd_common cmd_common; 4823 /** 4824 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 4825 */ 4826 struct dmub_rb_cmd_read_modify_write read_modify_write; 4827 /** 4828 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 4829 */ 4830 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 4831 /** 4832 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 4833 */ 4834 struct dmub_rb_cmd_burst_write burst_write; 4835 /** 4836 * Definition of a DMUB_CMD__REG_REG_WAIT command. 4837 */ 4838 struct dmub_rb_cmd_reg_wait reg_wait; 4839 /** 4840 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 4841 */ 4842 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 4843 /** 4844 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 4845 */ 4846 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 4847 /** 4848 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 4849 */ 4850 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 4851 /** 4852 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 4853 */ 4854 struct dmub_rb_cmd_dpphy_init dpphy_init; 4855 /** 4856 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 4857 */ 4858 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 4859 /** 4860 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 4861 */ 4862 struct dmub_rb_cmd_domain_control domain_control; 4863 /** 4864 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 4865 */ 4866 struct dmub_rb_cmd_psr_set_version psr_set_version; 4867 /** 4868 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 4869 */ 4870 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 4871 /** 4872 * Definition of a DMUB_CMD__PSR_ENABLE command. 4873 */ 4874 struct dmub_rb_cmd_psr_enable psr_enable; 4875 /** 4876 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 4877 */ 4878 struct dmub_rb_cmd_psr_set_level psr_set_level; 4879 /** 4880 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 4881 */ 4882 struct dmub_rb_cmd_psr_force_static psr_force_static; 4883 /** 4884 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 4885 */ 4886 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 4887 /** 4888 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4889 */ 4890 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 4891 /** 4892 * Definition of a DMUB_CMD__HW_LOCK command. 4893 * Command is used by driver and FW. 4894 */ 4895 struct dmub_rb_cmd_lock_hw lock_hw; 4896 /** 4897 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4898 */ 4899 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 4900 /** 4901 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4902 */ 4903 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 4904 /** 4905 * Definition of a DMUB_CMD__PLAT_54186_WA command. 4906 */ 4907 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 4908 /** 4909 * Definition of a DMUB_CMD__MALL command. 4910 */ 4911 struct dmub_rb_cmd_mall mall; 4912 4913 /** 4914 * Definition of a DMUB_CMD__CAB command. 4915 */ 4916 struct dmub_rb_cmd_cab_for_ss cab; 4917 4918 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 4919 4920 /** 4921 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 4922 */ 4923 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 4924 4925 /** 4926 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 4927 */ 4928 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 4929 4930 /** 4931 * Definition of DMUB_CMD__PANEL_CNTL commands. 4932 */ 4933 struct dmub_rb_cmd_panel_cntl panel_cntl; 4934 4935 /** 4936 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4937 */ 4938 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 4939 4940 /** 4941 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4942 */ 4943 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 4944 4945 /** 4946 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4947 */ 4948 struct dmub_rb_cmd_abm_set_level abm_set_level; 4949 4950 /** 4951 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4952 */ 4953 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 4954 4955 /** 4956 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4957 */ 4958 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 4959 4960 /** 4961 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4962 */ 4963 struct dmub_rb_cmd_abm_init_config abm_init_config; 4964 4965 /** 4966 * Definition of a DMUB_CMD__ABM_PAUSE command. 4967 */ 4968 struct dmub_rb_cmd_abm_pause abm_pause; 4969 4970 /** 4971 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4972 */ 4973 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 4974 4975 /** 4976 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4977 */ 4978 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 4979 4980 /** 4981 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 4982 */ 4983 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 4984 4985 /** 4986 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 4987 */ 4988 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 4989 4990 /** 4991 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4992 */ 4993 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 4994 4995 /** 4996 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4997 */ 4998 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 4999 struct dmub_rb_cmd_drr_update drr_update; 5000 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5001 5002 /** 5003 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5004 */ 5005 struct dmub_rb_cmd_lvtma_control lvtma_control; 5006 /** 5007 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5008 */ 5009 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5010 /** 5011 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5012 */ 5013 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5014 /** 5015 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5016 */ 5017 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5018 /** 5019 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5020 */ 5021 struct dmub_rb_cmd_set_config_access set_config_access; 5022 /** 5023 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5024 */ 5025 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5026 /** 5027 * Definition of a DMUB_CMD__EDID_CEA command. 5028 */ 5029 struct dmub_rb_cmd_edid_cea edid_cea; 5030 /** 5031 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5032 */ 5033 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5034 5035 /** 5036 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5037 */ 5038 struct dmub_rb_cmd_query_hpd_state query_hpd; 5039 /** 5040 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5041 */ 5042 struct dmub_rb_cmd_secure_display secure_display; 5043 5044 /** 5045 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5046 */ 5047 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5048 /** 5049 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5050 */ 5051 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5052 /* 5053 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5054 */ 5055 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5056 /** 5057 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5058 */ 5059 struct dmub_rb_cmd_replay_enable replay_enable; 5060 /** 5061 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5062 */ 5063 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5064 /** 5065 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5066 */ 5067 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5068 /** 5069 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5070 */ 5071 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5072 5073 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5074 /** 5075 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5076 */ 5077 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5078 /** 5079 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5080 */ 5081 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5082 /** 5083 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5084 */ 5085 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5086 /** 5087 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5088 */ 5089 struct dmub_rb_cmd_assr_enable assr_enable; 5090 struct dmub_rb_cmd_fams2 fams2_config; 5091 5092 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5093 5094 struct dmub_rb_cmd_fams2_flip fams2_flip; 5095 }; 5096 5097 /** 5098 * union dmub_rb_out_cmd - Outbox command 5099 */ 5100 union dmub_rb_out_cmd { 5101 /** 5102 * Parameters common to every command. 5103 */ 5104 struct dmub_rb_cmd_common cmd_common; 5105 /** 5106 * AUX reply command. 5107 */ 5108 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5109 /** 5110 * HPD notify command. 5111 */ 5112 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5113 /** 5114 * SET_CONFIG reply command. 5115 */ 5116 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5117 /** 5118 * DPIA notification command. 5119 */ 5120 struct dmub_rb_cmd_dpia_notification dpia_notification; 5121 }; 5122 #pragma pack(pop) 5123 5124 5125 //============================================================================== 5126 //</DMUB_CMD>=================================================================== 5127 //============================================================================== 5128 //< DMUB_RB>==================================================================== 5129 //============================================================================== 5130 5131 /** 5132 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5133 */ 5134 struct dmub_rb_init_params { 5135 void *ctx; /**< Caller provided context pointer */ 5136 void *base_address; /**< CPU base address for ring's data */ 5137 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5138 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5139 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5140 }; 5141 5142 /** 5143 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5144 */ 5145 struct dmub_rb { 5146 void *base_address; /**< CPU address for the ring's data */ 5147 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5148 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5149 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5150 5151 void *ctx; /**< Caller provided context pointer */ 5152 void *dmub; /**< Pointer to the DMUB interface */ 5153 }; 5154 5155 /** 5156 * @brief Checks if the ringbuffer is empty. 5157 * 5158 * @param rb DMUB Ringbuffer 5159 * @return true if empty 5160 * @return false otherwise 5161 */ 5162 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5163 { 5164 return (rb->wrpt == rb->rptr); 5165 } 5166 5167 /** 5168 * @brief Checks if the ringbuffer is full 5169 * 5170 * @param rb DMUB Ringbuffer 5171 * @return true if full 5172 * @return false otherwise 5173 */ 5174 static inline bool dmub_rb_full(struct dmub_rb *rb) 5175 { 5176 uint32_t data_count; 5177 5178 if (rb->wrpt >= rb->rptr) 5179 data_count = rb->wrpt - rb->rptr; 5180 else 5181 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5182 5183 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5184 } 5185 5186 /** 5187 * @brief Pushes a command into the ringbuffer 5188 * 5189 * @param rb DMUB ringbuffer 5190 * @param cmd The command to push 5191 * @return true if the ringbuffer was not full 5192 * @return false otherwise 5193 */ 5194 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5195 const union dmub_rb_cmd *cmd) 5196 { 5197 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5198 const uint64_t *src = (const uint64_t *)cmd; 5199 uint8_t i; 5200 5201 if (dmub_rb_full(rb)) 5202 return false; 5203 5204 // copying data 5205 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5206 *dst++ = *src++; 5207 5208 rb->wrpt += DMUB_RB_CMD_SIZE; 5209 5210 if (rb->wrpt >= rb->capacity) 5211 rb->wrpt %= rb->capacity; 5212 5213 return true; 5214 } 5215 5216 /** 5217 * @brief Pushes a command into the DMUB outbox ringbuffer 5218 * 5219 * @param rb DMUB outbox ringbuffer 5220 * @param cmd Outbox command 5221 * @return true if not full 5222 * @return false otherwise 5223 */ 5224 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5225 const union dmub_rb_out_cmd *cmd) 5226 { 5227 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 5228 const uint8_t *src = (const uint8_t *)cmd; 5229 5230 if (dmub_rb_full(rb)) 5231 return false; 5232 5233 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 5234 5235 rb->wrpt += DMUB_RB_CMD_SIZE; 5236 5237 if (rb->wrpt >= rb->capacity) 5238 rb->wrpt %= rb->capacity; 5239 5240 return true; 5241 } 5242 5243 /** 5244 * @brief Returns the next unprocessed command in the ringbuffer. 5245 * 5246 * @param rb DMUB ringbuffer 5247 * @param cmd The command to return 5248 * @return true if not empty 5249 * @return false otherwise 5250 */ 5251 static inline bool dmub_rb_front(struct dmub_rb *rb, 5252 union dmub_rb_cmd **cmd) 5253 { 5254 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 5255 5256 if (dmub_rb_empty(rb)) 5257 return false; 5258 5259 *cmd = (union dmub_rb_cmd *)rb_cmd; 5260 5261 return true; 5262 } 5263 5264 /** 5265 * @brief Determines the next ringbuffer offset. 5266 * 5267 * @param rb DMUB inbox ringbuffer 5268 * @param num_cmds Number of commands 5269 * @param next_rptr The next offset in the ringbuffer 5270 */ 5271 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 5272 uint32_t num_cmds, 5273 uint32_t *next_rptr) 5274 { 5275 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 5276 5277 if (*next_rptr >= rb->capacity) 5278 *next_rptr %= rb->capacity; 5279 } 5280 5281 /** 5282 * @brief Returns a pointer to a command in the inbox. 5283 * 5284 * @param rb DMUB inbox ringbuffer 5285 * @param cmd The inbox command to return 5286 * @param rptr The ringbuffer offset 5287 * @return true if not empty 5288 * @return false otherwise 5289 */ 5290 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 5291 union dmub_rb_cmd **cmd, 5292 uint32_t rptr) 5293 { 5294 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 5295 5296 if (dmub_rb_empty(rb)) 5297 return false; 5298 5299 *cmd = (union dmub_rb_cmd *)rb_cmd; 5300 5301 return true; 5302 } 5303 5304 /** 5305 * @brief Returns the next unprocessed command in the outbox. 5306 * 5307 * @param rb DMUB outbox ringbuffer 5308 * @param cmd The outbox command to return 5309 * @return true if not empty 5310 * @return false otherwise 5311 */ 5312 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 5313 union dmub_rb_out_cmd *cmd) 5314 { 5315 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 5316 uint64_t *dst = (uint64_t *)cmd; 5317 uint8_t i; 5318 5319 if (dmub_rb_empty(rb)) 5320 return false; 5321 5322 // copying data 5323 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5324 *dst++ = *src++; 5325 5326 return true; 5327 } 5328 5329 /** 5330 * @brief Removes the front entry in the ringbuffer. 5331 * 5332 * @param rb DMUB ringbuffer 5333 * @return true if the command was removed 5334 * @return false if there were no commands 5335 */ 5336 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 5337 { 5338 if (dmub_rb_empty(rb)) 5339 return false; 5340 5341 rb->rptr += DMUB_RB_CMD_SIZE; 5342 5343 if (rb->rptr >= rb->capacity) 5344 rb->rptr %= rb->capacity; 5345 5346 return true; 5347 } 5348 5349 /** 5350 * @brief Flushes commands in the ringbuffer to framebuffer memory. 5351 * 5352 * Avoids a race condition where DMCUB accesses memory while 5353 * there are still writes in flight to framebuffer. 5354 * 5355 * @param rb DMUB ringbuffer 5356 */ 5357 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 5358 { 5359 uint32_t rptr = rb->rptr; 5360 uint32_t wptr = rb->wrpt; 5361 5362 while (rptr != wptr) { 5363 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 5364 uint8_t i; 5365 5366 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5367 (void)READ_ONCE(*data++); 5368 5369 rptr += DMUB_RB_CMD_SIZE; 5370 if (rptr >= rb->capacity) 5371 rptr %= rb->capacity; 5372 } 5373 } 5374 5375 /** 5376 * @brief Initializes a DMCUB ringbuffer 5377 * 5378 * @param rb DMUB ringbuffer 5379 * @param init_params initial configuration for the ringbuffer 5380 */ 5381 static inline void dmub_rb_init(struct dmub_rb *rb, 5382 struct dmub_rb_init_params *init_params) 5383 { 5384 rb->base_address = init_params->base_address; 5385 rb->capacity = init_params->capacity; 5386 rb->rptr = init_params->read_ptr; 5387 rb->wrpt = init_params->write_ptr; 5388 } 5389 5390 /** 5391 * @brief Copies output data from in/out commands into the given command. 5392 * 5393 * @param rb DMUB ringbuffer 5394 * @param cmd Command to copy data into 5395 */ 5396 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5397 union dmub_rb_cmd *cmd) 5398 { 5399 // Copy rb entry back into command 5400 uint8_t *rd_ptr = (rb->rptr == 0) ? 5401 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5402 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5403 5404 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5405 } 5406 5407 //============================================================================== 5408 //</DMUB_RB>==================================================================== 5409 //============================================================================== 5410 #endif /* _DMUB_CMD_H_ */ 5411