1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic udelay 165 */ 166 #ifndef dmub_udelay 167 #define dmub_udelay(microseconds) udelay(microseconds) 168 #endif 169 170 #pragma pack(push, 1) 171 #define ABM_NUM_OF_ACE_SEGMENTS 5 172 173 /** 174 * Debug FW state offset 175 */ 176 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 177 178 union abm_flags { 179 struct { 180 /** 181 * @abm_enabled: Indicates if ABM is enabled. 182 */ 183 unsigned int abm_enabled : 1; 184 185 /** 186 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 187 */ 188 unsigned int disable_abm_requested : 1; 189 190 /** 191 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 192 */ 193 unsigned int disable_abm_immediately : 1; 194 195 /** 196 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 197 * to be disabled immediately and keep gain. 198 */ 199 unsigned int disable_abm_immediate_keep_gain : 1; 200 201 /** 202 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 203 */ 204 unsigned int fractional_pwm : 1; 205 206 /** 207 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 208 * of user backlight level. 209 */ 210 unsigned int abm_gradual_bl_change : 1; 211 212 /** 213 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 214 */ 215 unsigned int abm_new_frame : 1; 216 217 /** 218 * @vb_scaling_enabled: Indicates variBright Scaling Enable 219 */ 220 unsigned int vb_scaling_enabled : 1; 221 } bitfields; 222 223 unsigned int u32All; 224 }; 225 226 struct abm_save_restore { 227 /** 228 * @flags: Misc. ABM flags. 229 */ 230 union abm_flags flags; 231 232 /** 233 * @pause: true: pause ABM and get state 234 * false: unpause ABM after setting state 235 */ 236 uint32_t pause; 237 238 /** 239 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 240 */ 241 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 242 243 /** 244 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 245 */ 246 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 247 248 /** 249 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 250 */ 251 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 252 253 254 /** 255 * @knee_threshold: Current x-position of ACE knee (u0.16). 256 */ 257 uint32_t knee_threshold; 258 /** 259 * @current_gain: Current backlight reduction (u16.16). 260 */ 261 uint32_t current_gain; 262 /** 263 * @curr_bl_level: Current actual backlight level converging to target backlight level. 264 */ 265 uint16_t curr_bl_level; 266 267 /** 268 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 269 */ 270 uint16_t curr_user_bl_level; 271 272 }; 273 274 /** 275 * union dmub_addr - DMUB physical/virtual 64-bit address. 276 */ 277 union dmub_addr { 278 struct { 279 uint32_t low_part; /**< Lower 32 bits */ 280 uint32_t high_part; /**< Upper 32 bits */ 281 } u; /*<< Low/high bit access */ 282 uint64_t quad_part; /*<< 64 bit address */ 283 }; 284 #pragma pack(pop) 285 286 /** 287 * Dirty rect definition. 288 */ 289 struct dmub_rect { 290 /** 291 * Dirty rect x offset. 292 */ 293 uint32_t x; 294 295 /** 296 * Dirty rect y offset. 297 */ 298 uint32_t y; 299 300 /** 301 * Dirty rect width. 302 */ 303 uint32_t width; 304 305 /** 306 * Dirty rect height. 307 */ 308 uint32_t height; 309 }; 310 311 /** 312 * Flags that can be set by driver to change some PSR behaviour. 313 */ 314 union dmub_psr_debug_flags { 315 /** 316 * Debug flags. 317 */ 318 struct { 319 /** 320 * Enable visual confirm in FW. 321 */ 322 uint32_t visual_confirm : 1; 323 324 /** 325 * Force all selective updates to bw full frame updates. 326 */ 327 uint32_t force_full_frame_update : 1; 328 329 /** 330 * Use HW Lock Mgr object to do HW locking in FW. 331 */ 332 uint32_t use_hw_lock_mgr : 1; 333 334 /** 335 * Use TPS3 signal when restore main link. 336 */ 337 uint32_t force_wakeup_by_tps3 : 1; 338 339 /** 340 * Back to back flip, therefore cannot power down PHY 341 */ 342 uint32_t back_to_back_flip : 1; 343 344 /** 345 * Enable visual confirm for IPS 346 */ 347 uint32_t enable_ips_visual_confirm : 1; 348 } bitfields; 349 350 /** 351 * Union for debug flags. 352 */ 353 uint32_t u32All; 354 }; 355 356 /** 357 * Flags that can be set by driver to change some Replay behaviour. 358 */ 359 union replay_debug_flags { 360 struct { 361 /** 362 * 0x1 (bit 0) 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * 0x2 (bit 1) 369 * @skip_crc: Set if need to skip CRC. 370 */ 371 uint32_t skip_crc : 1; 372 373 /** 374 * 0x4 (bit 2) 375 * @force_link_power_on: Force disable ALPM control 376 */ 377 uint32_t force_link_power_on : 1; 378 379 /** 380 * 0x8 (bit 3) 381 * @force_phy_power_on: Force phy power on 382 */ 383 uint32_t force_phy_power_on : 1; 384 385 /** 386 * 0x10 (bit 4) 387 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 388 */ 389 uint32_t timing_resync_disabled : 1; 390 391 /** 392 * 0x20 (bit 5) 393 * @skip_crtc_disabled: CRTC disable skipped 394 */ 395 uint32_t skip_crtc_disabled : 1; 396 397 /** 398 * 0x40 (bit 6) 399 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 400 */ 401 uint32_t force_defer_one_frame_update : 1; 402 403 /** 404 * 0x80 (bit 7) 405 * @disable_delay_alpm_on: Force disable delay alpm on 406 */ 407 uint32_t disable_delay_alpm_on : 1; 408 409 /** 410 * 0x100 (bit 8) 411 * @disable_desync_error_check: Force disable desync error check 412 */ 413 uint32_t disable_desync_error_check : 1; 414 415 /** 416 * 0x200 (bit 9) 417 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 418 */ 419 uint32_t force_self_update_when_abm_non_steady : 1; 420 421 /** 422 * 0x400 (bit 10) 423 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 424 * If we enter IPS2, the Visual confirm bar will change to yellow 425 */ 426 uint32_t enable_ips_visual_confirm : 1; 427 428 /** 429 * 0x800 (bit 11) 430 * @enable_ips_residency_profiling: Enable IPS residency profiling 431 */ 432 uint32_t enable_ips_residency_profiling : 1; 433 434 uint32_t reserved : 20; 435 } bitfields; 436 437 uint32_t u32All; 438 }; 439 440 union replay_hw_flags { 441 struct { 442 /** 443 * @allow_alpm_fw_standby_mode: To indicate whether the 444 * ALPM FW standby mode is allowed 445 */ 446 uint32_t allow_alpm_fw_standby_mode : 1; 447 448 /* 449 * @dsc_enable_status: DSC enable status in driver 450 */ 451 uint32_t dsc_enable_status : 1; 452 453 /** 454 * @fec_enable_status: receive fec enable/disable status from driver 455 */ 456 uint32_t fec_enable_status : 1; 457 458 /* 459 * @smu_optimizations_en: SMU power optimization. 460 * Only when active display is Replay capable and display enters Replay. 461 * Trigger interrupt to SMU to powerup/down. 462 */ 463 uint32_t smu_optimizations_en : 1; 464 465 /** 466 * @phy_power_state: Indicates current phy power state 467 */ 468 uint32_t phy_power_state : 1; 469 470 /** 471 * @link_power_state: Indicates current link power state 472 */ 473 uint32_t link_power_state : 1; 474 /** 475 * Use TPS3 signal when restore main link. 476 */ 477 uint32_t force_wakeup_by_tps3 : 1; 478 } bitfields; 479 480 uint32_t u32All; 481 }; 482 483 /** 484 * DMUB feature capabilities. 485 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 486 */ 487 struct dmub_feature_caps { 488 /** 489 * Max PSR version supported by FW. 490 */ 491 uint8_t psr; 492 uint8_t fw_assisted_mclk_switch_ver; 493 uint8_t reserved[4]; 494 uint8_t subvp_psr_support; 495 uint8_t gecc_enable; 496 uint8_t replay_supported; 497 uint8_t replay_reserved[3]; 498 }; 499 500 struct dmub_visual_confirm_color { 501 /** 502 * Maximum 10 bits color value 503 */ 504 uint16_t color_r_cr; 505 uint16_t color_g_y; 506 uint16_t color_b_cb; 507 uint16_t panel_inst; 508 }; 509 510 //============================================================================== 511 //</DMUB_TYPES>================================================================= 512 //============================================================================== 513 //< DMUB_META>================================================================== 514 //============================================================================== 515 #pragma pack(push, 1) 516 517 /* Magic value for identifying dmub_fw_meta_info */ 518 #define DMUB_FW_META_MAGIC 0x444D5542 519 520 /* Offset from the end of the file to the dmub_fw_meta_info */ 521 #define DMUB_FW_META_OFFSET 0x24 522 523 /** 524 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 525 */ 526 union dmub_fw_meta_feature_bits { 527 struct { 528 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 529 uint32_t reserved : 31; 530 } bits; /**< status bits */ 531 uint32_t all; /**< 32-bit access to status bits */ 532 }; 533 534 /** 535 * struct dmub_fw_meta_info - metadata associated with fw binary 536 * 537 * NOTE: This should be considered a stable API. Fields should 538 * not be repurposed or reordered. New fields should be 539 * added instead to extend the structure. 540 * 541 * @magic_value: magic value identifying DMUB firmware meta info 542 * @fw_region_size: size of the firmware state region 543 * @trace_buffer_size: size of the tracebuffer region 544 * @fw_version: the firmware version information 545 * @dal_fw: 1 if the firmware is DAL 546 * @shared_state_size: size of the shared state region in bytes 547 * @shared_state_features: number of shared state features 548 */ 549 struct dmub_fw_meta_info { 550 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 551 uint32_t fw_region_size; /**< size of the firmware state region */ 552 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 553 uint32_t fw_version; /**< the firmware version information */ 554 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 555 uint8_t reserved[3]; /**< padding bits */ 556 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 557 uint16_t shared_state_features; /**< number of shared state features */ 558 uint16_t reserved2; /**< padding bytes */ 559 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 560 }; 561 562 /** 563 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 564 */ 565 union dmub_fw_meta { 566 struct dmub_fw_meta_info info; /**< metadata info */ 567 uint8_t reserved[64]; /**< padding bits */ 568 }; 569 570 #pragma pack(pop) 571 572 //============================================================================== 573 //< DMUB Trace Buffer>================================================================ 574 //============================================================================== 575 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 576 /** 577 * dmub_trace_code_t - firmware trace code, 32-bits 578 */ 579 typedef uint32_t dmub_trace_code_t; 580 581 /** 582 * struct dmcub_trace_buf_entry - Firmware trace entry 583 */ 584 struct dmcub_trace_buf_entry { 585 dmub_trace_code_t trace_code; /**< trace code for the event */ 586 uint32_t tick_count; /**< the tick count at time of trace */ 587 uint32_t param0; /**< trace defined parameter 0 */ 588 uint32_t param1; /**< trace defined parameter 1 */ 589 }; 590 #endif 591 592 //============================================================================== 593 //< DMUB_STATUS>================================================================ 594 //============================================================================== 595 596 /** 597 * DMCUB scratch registers can be used to determine firmware status. 598 * Current scratch register usage is as follows: 599 * 600 * SCRATCH0: FW Boot Status register 601 * SCRATCH5: LVTMA Status Register 602 * SCRATCH15: FW Boot Options register 603 */ 604 605 /** 606 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 607 */ 608 union dmub_fw_boot_status { 609 struct { 610 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 611 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 612 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 613 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 614 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 615 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 616 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 617 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 618 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 619 } bits; /**< status bits */ 620 uint32_t all; /**< 32-bit access to status bits */ 621 }; 622 623 /** 624 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 625 */ 626 enum dmub_fw_boot_status_bit { 627 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 628 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 629 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 630 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 631 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 632 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 633 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 634 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 635 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 636 }; 637 638 /* Register bit definition for SCRATCH5 */ 639 union dmub_lvtma_status { 640 struct { 641 uint32_t psp_ok : 1; 642 uint32_t edp_on : 1; 643 uint32_t reserved : 30; 644 } bits; 645 uint32_t all; 646 }; 647 648 enum dmub_lvtma_status_bit { 649 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 650 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 651 }; 652 653 enum dmub_ips_disable_type { 654 DMUB_IPS_ENABLE = 0, 655 DMUB_IPS_DISABLE_ALL = 1, 656 DMUB_IPS_DISABLE_IPS1 = 2, 657 DMUB_IPS_DISABLE_IPS2 = 3, 658 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 659 DMUB_IPS_DISABLE_DYNAMIC = 5, 660 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 661 }; 662 663 #define DMUB_IPS1_ALLOW_MASK 0x00000001 664 #define DMUB_IPS2_ALLOW_MASK 0x00000002 665 #define DMUB_IPS1_COMMIT_MASK 0x00000004 666 #define DMUB_IPS2_COMMIT_MASK 0x00000008 667 668 /** 669 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 670 */ 671 union dmub_fw_boot_options { 672 struct { 673 uint32_t pemu_env : 1; /**< 1 if PEMU */ 674 uint32_t fpga_env : 1; /**< 1 if FPGA */ 675 uint32_t optimized_init : 1; /**< 1 if optimized init */ 676 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 677 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 678 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 679 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 680 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 681 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 682 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 683 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 684 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 685 uint32_t power_optimization: 1; 686 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 687 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 688 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 689 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 690 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 691 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 692 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 693 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 694 uint32_t ips_disable: 3; /* options to disable ips support*/ 695 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 696 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 697 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 698 uint32_t reserved : 6; /**< reserved */ 699 } bits; /**< boot bits */ 700 uint32_t all; /**< 32-bit access to bits */ 701 }; 702 703 enum dmub_fw_boot_options_bit { 704 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 705 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 706 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 707 }; 708 709 //============================================================================== 710 //< DMUB_SHARED_STATE>========================================================== 711 //============================================================================== 712 713 /** 714 * Shared firmware state between driver and firmware for lockless communication 715 * in situations where the inbox/outbox may be unavailable. 716 * 717 * Each structure *must* be at most 256-bytes in size. The layout allocation is 718 * described below: 719 * 720 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 721 */ 722 723 /** 724 * enum dmub_shared_state_feature_id - List of shared state features. 725 */ 726 enum dmub_shared_state_feature_id { 727 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 728 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 729 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 730 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 731 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 732 }; 733 734 /** 735 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 736 */ 737 union dmub_shared_state_ips_fw_signals { 738 struct { 739 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 740 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 741 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 742 uint32_t detection_required : 1; /**< 1 if detection is required */ 743 uint32_t reserved_bits : 28; /**< Reversed */ 744 } bits; 745 uint32_t all; 746 }; 747 748 /** 749 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 750 */ 751 union dmub_shared_state_ips_driver_signals { 752 struct { 753 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 754 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 755 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 756 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 757 uint32_t allow_idle : 1; /**< 1 if driver is allowing idle */ 758 uint32_t reserved_bits : 27; /**< Reversed bits */ 759 } bits; 760 uint32_t all; 761 }; 762 763 /** 764 * IPS FW Version 765 */ 766 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 767 768 struct dmub_shared_state_debug_setup { 769 union { 770 struct { 771 uint32_t exclude_points[62]; 772 } profile_mode; 773 }; 774 }; 775 776 /** 777 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 778 */ 779 struct dmub_shared_state_ips_fw { 780 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 781 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 782 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 783 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 784 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 785 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 786 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 787 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 788 }; /* 248-bytes, fixed */ 789 790 /** 791 * IPS Driver Version 792 */ 793 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 794 795 /** 796 * struct dmub_shared_state_ips_driver - Driver state for IPS. 797 */ 798 struct dmub_shared_state_ips_driver { 799 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 800 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 801 }; /* 248-bytes, fixed */ 802 803 /** 804 * enum dmub_shared_state_feature_common - Generic payload. 805 */ 806 struct dmub_shared_state_feature_common { 807 uint32_t padding[62]; 808 }; /* 248-bytes, fixed */ 809 810 /** 811 * enum dmub_shared_state_feature_header - Feature description. 812 */ 813 struct dmub_shared_state_feature_header { 814 uint16_t id; /**< Feature ID */ 815 uint16_t version; /**< Feature version */ 816 uint32_t reserved; /**< Reserved bytes. */ 817 }; /* 8 bytes, fixed */ 818 819 /** 820 * struct dmub_shared_state_feature_block - Feature block. 821 */ 822 struct dmub_shared_state_feature_block { 823 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 824 union dmub_shared_feature_state_union { 825 struct dmub_shared_state_feature_common common; /**< Generic data */ 826 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 827 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 828 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 829 } data; /**< Shared state data. */ 830 }; /* 256-bytes, fixed */ 831 832 /** 833 * Shared state size in bytes. 834 */ 835 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 836 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 837 838 //============================================================================== 839 //</DMUB_STATUS>================================================================ 840 //============================================================================== 841 //< DMUB_VBIOS>================================================================= 842 //============================================================================== 843 844 /* 845 * enum dmub_cmd_vbios_type - VBIOS commands. 846 * 847 * Command IDs should be treated as stable ABI. 848 * Do not reuse or modify IDs. 849 */ 850 enum dmub_cmd_vbios_type { 851 /** 852 * Configures the DIG encoder. 853 */ 854 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 855 /** 856 * Controls the PHY. 857 */ 858 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 859 /** 860 * Sets the pixel clock/symbol clock. 861 */ 862 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 863 /** 864 * Enables or disables power gating. 865 */ 866 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 867 /** 868 * Controls embedded panels. 869 */ 870 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 871 /** 872 * Query DP alt status on a transmitter. 873 */ 874 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 875 /** 876 * Control PHY FSM 877 */ 878 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 879 /** 880 * Controls domain power gating 881 */ 882 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 883 }; 884 885 //============================================================================== 886 //</DMUB_VBIOS>================================================================= 887 //============================================================================== 888 //< DMUB_GPINT>================================================================= 889 //============================================================================== 890 891 /** 892 * The shifts and masks below may alternatively be used to format and read 893 * the command register bits. 894 */ 895 896 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 897 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 898 899 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 900 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 901 902 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 903 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 904 905 /** 906 * Command responses. 907 */ 908 909 /** 910 * Return response for DMUB_GPINT__STOP_FW command. 911 */ 912 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 913 914 /** 915 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 916 */ 917 union dmub_gpint_data_register { 918 struct { 919 uint32_t param : 16; /**< 16-bit parameter */ 920 uint32_t command_code : 12; /**< GPINT command */ 921 uint32_t status : 4; /**< Command status bit */ 922 } bits; /**< GPINT bit access */ 923 uint32_t all; /**< GPINT 32-bit access */ 924 }; 925 926 /* 927 * enum dmub_gpint_command - GPINT command to DMCUB FW 928 * 929 * Command IDs should be treated as stable ABI. 930 * Do not reuse or modify IDs. 931 */ 932 enum dmub_gpint_command { 933 /** 934 * Invalid command, ignored. 935 */ 936 DMUB_GPINT__INVALID_COMMAND = 0, 937 /** 938 * DESC: Queries the firmware version. 939 * RETURN: Firmware version. 940 */ 941 DMUB_GPINT__GET_FW_VERSION = 1, 942 /** 943 * DESC: Halts the firmware. 944 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 945 */ 946 DMUB_GPINT__STOP_FW = 2, 947 /** 948 * DESC: Get PSR state from FW. 949 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 950 */ 951 DMUB_GPINT__GET_PSR_STATE = 7, 952 /** 953 * DESC: Notifies DMCUB of the currently active streams. 954 * ARGS: Stream mask, 1 bit per active stream index. 955 */ 956 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 957 /** 958 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 959 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 960 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 961 * RETURN: PSR residency in milli-percent. 962 */ 963 DMUB_GPINT__PSR_RESIDENCY = 9, 964 965 /** 966 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 967 */ 968 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 969 970 /** 971 * DESC: Get REPLAY state from FW. 972 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 973 */ 974 DMUB_GPINT__GET_REPLAY_STATE = 13, 975 976 /** 977 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 978 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 979 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 980 * RETURN: REPLAY residency in milli-percent. 981 */ 982 DMUB_GPINT__REPLAY_RESIDENCY = 14, 983 984 /** 985 * DESC: Copy bounding box to the host. 986 * ARGS: Version of bounding box to copy 987 * RETURN: Result of copying bounding box 988 */ 989 DMUB_GPINT__BB_COPY = 96, 990 991 /** 992 * DESC: Updates the host addresses bit48~bit63 for bounding box. 993 * ARGS: The word3 for the 64 bit address 994 */ 995 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 996 997 /** 998 * DESC: Updates the host addresses bit32~bit47 for bounding box. 999 * ARGS: The word2 for the 64 bit address 1000 */ 1001 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1002 1003 /** 1004 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1005 * ARGS: The word1 for the 64 bit address 1006 */ 1007 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1008 1009 /** 1010 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1011 * ARGS: The word0 for the 64 bit address 1012 */ 1013 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1014 1015 /** 1016 * DESC: Updates the trace buffer lower 32-bit mask. 1017 * ARGS: The new mask 1018 * RETURN: Lower 32-bit mask. 1019 */ 1020 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1021 1022 /** 1023 * DESC: Updates the trace buffer mask bit0~bit15. 1024 * ARGS: The new mask 1025 * RETURN: Lower 32-bit mask. 1026 */ 1027 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1028 1029 /** 1030 * DESC: Updates the trace buffer mask bit16~bit31. 1031 * ARGS: The new mask 1032 * RETURN: Lower 32-bit mask. 1033 */ 1034 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1035 1036 /** 1037 * DESC: Updates the trace buffer mask bit32~bit47. 1038 * ARGS: The new mask 1039 * RETURN: Lower 32-bit mask. 1040 */ 1041 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1042 1043 /** 1044 * DESC: Updates the trace buffer mask bit48~bit63. 1045 * ARGS: The new mask 1046 * RETURN: Lower 32-bit mask. 1047 */ 1048 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1049 1050 /** 1051 * DESC: Read the trace buffer mask bi0~bit15. 1052 */ 1053 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1054 1055 /** 1056 * DESC: Read the trace buffer mask bit16~bit31. 1057 */ 1058 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1059 1060 /** 1061 * DESC: Read the trace buffer mask bi32~bit47. 1062 */ 1063 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1064 1065 /** 1066 * DESC: Updates the trace buffer mask bit32~bit63. 1067 */ 1068 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1069 1070 /** 1071 * DESC: Set IPS residency measurement 1072 * ARGS: 0 - Disable ips measurement 1073 * 1 - Enable ips measurement 1074 */ 1075 DMUB_GPINT__IPS_RESIDENCY = 121, 1076 1077 /** 1078 * DESC: Enable measurements for various task duration 1079 * ARGS: 0 - Disable measurement 1080 * 1 - Enable measurement 1081 */ 1082 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1083 1084 /** 1085 * DESC: Gets IPS residency in microseconds 1086 * ARGS: 0 - Return IPS1 residency 1087 * 1 - Return IPS2 residency 1088 * 2 - Return IPS1_RCG residency 1089 * 3 - Return IPS1_ONO2_ON residency 1090 * RETURN: Total residency in microseconds - lower 32 bits 1091 */ 1092 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1093 1094 /** 1095 * DESC: Gets IPS1 histogram counts 1096 * ARGS: Bucket index 1097 * RETURN: Total count for the bucket 1098 */ 1099 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1100 1101 /** 1102 * DESC: Gets IPS2 histogram counts 1103 * ARGS: Bucket index 1104 * RETURN: Total count for the bucket 1105 */ 1106 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1107 1108 /** 1109 * DESC: Gets IPS residency 1110 * ARGS: 0 - Return IPS1 residency 1111 * 1 - Return IPS2 residency 1112 * 2 - Return IPS1_RCG residency 1113 * 3 - Return IPS1_ONO2_ON residency 1114 * RETURN: Total residency in milli-percent. 1115 */ 1116 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1117 1118 /** 1119 * DESC: Gets IPS1_RCG histogram counts 1120 * ARGS: Bucket index 1121 * RETURN: Total count for the bucket 1122 */ 1123 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1124 1125 /** 1126 * DESC: Gets IPS1_ONO2_ON histogram counts 1127 * ARGS: Bucket index 1128 * RETURN: Total count for the bucket 1129 */ 1130 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1131 1132 /** 1133 * DESC: Gets IPS entry counter during residency measurement 1134 * ARGS: 0 - Return IPS1 entry counts 1135 * 1 - Return IPS2 entry counts 1136 * 2 - Return IPS1_RCG entry counts 1137 * 3 - Return IPS2_ONO2_ON entry counts 1138 * RETURN: Entry counter for selected IPS mode 1139 */ 1140 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1141 1142 /** 1143 * DESC: Gets IPS inactive residency in microseconds 1144 * ARGS: 0 - Return IPS1_MAX residency 1145 * 1 - Return IPS2 residency 1146 * 2 - Return IPS1_RCG residency 1147 * 3 - Return IPS1_ONO2_ON residency 1148 * RETURN: Total inactive residency in microseconds - lower 32 bits 1149 */ 1150 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1151 1152 /** 1153 * DESC: Gets IPS inactive residency in microseconds 1154 * ARGS: 0 - Return IPS1_MAX residency 1155 * 1 - Return IPS2 residency 1156 * 2 - Return IPS1_RCG residency 1157 * 3 - Return IPS1_ONO2_ON residency 1158 * RETURN: Total inactive residency in microseconds - upper 32 bits 1159 */ 1160 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1161 1162 /** 1163 * DESC: Gets IPS residency in microseconds 1164 * ARGS: 0 - Return IPS1 residency 1165 * 1 - Return IPS2 residency 1166 * 2 - Return IPS1_RCG residency 1167 * 3 - Return IPS1_ONO2_ON residency 1168 * RETURN: Total residency in microseconds - upper 32 bits 1169 */ 1170 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1171 /** 1172 * DESC: Setup debug configs. 1173 */ 1174 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1175 }; 1176 1177 /** 1178 * INBOX0 generic command definition 1179 */ 1180 union dmub_inbox0_cmd_common { 1181 struct { 1182 uint32_t command_code: 8; /**< INBOX0 command code */ 1183 uint32_t param: 24; /**< 24-bit parameter */ 1184 } bits; 1185 uint32_t all; 1186 }; 1187 1188 /** 1189 * INBOX0 hw_lock command definition 1190 */ 1191 union dmub_inbox0_cmd_lock_hw { 1192 struct { 1193 uint32_t command_code: 8; 1194 1195 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1196 uint32_t hw_lock_client: 2; 1197 1198 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1199 uint32_t otg_inst: 3; 1200 uint32_t opp_inst: 3; 1201 uint32_t dig_inst: 3; 1202 1203 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1204 uint32_t lock_pipe: 1; 1205 uint32_t lock_cursor: 1; 1206 uint32_t lock_dig: 1; 1207 uint32_t triple_buffer_lock: 1; 1208 1209 uint32_t lock: 1; /**< Lock */ 1210 uint32_t should_release: 1; /**< Release */ 1211 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1212 } bits; 1213 uint32_t all; 1214 }; 1215 1216 union dmub_inbox0_data_register { 1217 union dmub_inbox0_cmd_common inbox0_cmd_common; 1218 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1219 }; 1220 1221 enum dmub_inbox0_command { 1222 /** 1223 * DESC: Invalid command, ignored. 1224 */ 1225 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1226 /** 1227 * DESC: Notification to acquire/release HW lock 1228 * ARGS: 1229 */ 1230 DMUB_INBOX0_CMD__HW_LOCK = 1, 1231 }; 1232 //============================================================================== 1233 //</DMUB_GPINT>================================================================= 1234 //============================================================================== 1235 //< DMUB_CMD>=================================================================== 1236 //============================================================================== 1237 1238 /** 1239 * Size in bytes of each DMUB command. 1240 */ 1241 #define DMUB_RB_CMD_SIZE 64 1242 1243 /** 1244 * Maximum number of items in the DMUB ringbuffer. 1245 */ 1246 #define DMUB_RB_MAX_ENTRY 128 1247 1248 /** 1249 * Ringbuffer size in bytes. 1250 */ 1251 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1252 1253 /** 1254 * REG_SET mask for reg offload. 1255 */ 1256 #define REG_SET_MASK 0xFFFF 1257 1258 /* 1259 * enum dmub_cmd_type - DMUB inbox command. 1260 * 1261 * Command IDs should be treated as stable ABI. 1262 * Do not reuse or modify IDs. 1263 */ 1264 enum dmub_cmd_type { 1265 /** 1266 * Invalid command. 1267 */ 1268 DMUB_CMD__NULL = 0, 1269 /** 1270 * Read modify write register sequence offload. 1271 */ 1272 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1273 /** 1274 * Field update register sequence offload. 1275 */ 1276 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1277 /** 1278 * Burst write sequence offload. 1279 */ 1280 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1281 /** 1282 * Reg wait sequence offload. 1283 */ 1284 DMUB_CMD__REG_REG_WAIT = 4, 1285 /** 1286 * Workaround to avoid HUBP underflow during NV12 playback. 1287 */ 1288 DMUB_CMD__PLAT_54186_WA = 5, 1289 /** 1290 * Command type used to query FW feature caps. 1291 */ 1292 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1293 /** 1294 * Command type used to get visual confirm color. 1295 */ 1296 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1297 /** 1298 * Command type used for all PSR commands. 1299 */ 1300 DMUB_CMD__PSR = 64, 1301 /** 1302 * Command type used for all MALL commands. 1303 */ 1304 DMUB_CMD__MALL = 65, 1305 /** 1306 * Command type used for all ABM commands. 1307 */ 1308 DMUB_CMD__ABM = 66, 1309 /** 1310 * Command type used to update dirty rects in FW. 1311 */ 1312 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1313 /** 1314 * Command type used to update cursor info in FW. 1315 */ 1316 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1317 /** 1318 * Command type used for HW locking in FW. 1319 */ 1320 DMUB_CMD__HW_LOCK = 69, 1321 /** 1322 * Command type used to access DP AUX. 1323 */ 1324 DMUB_CMD__DP_AUX_ACCESS = 70, 1325 /** 1326 * Command type used for OUTBOX1 notification enable 1327 */ 1328 DMUB_CMD__OUTBOX1_ENABLE = 71, 1329 1330 /** 1331 * Command type used for all idle optimization commands. 1332 */ 1333 DMUB_CMD__IDLE_OPT = 72, 1334 /** 1335 * Command type used for all clock manager commands. 1336 */ 1337 DMUB_CMD__CLK_MGR = 73, 1338 /** 1339 * Command type used for all panel control commands. 1340 */ 1341 DMUB_CMD__PANEL_CNTL = 74, 1342 1343 /** 1344 * Command type used for all CAB commands. 1345 */ 1346 DMUB_CMD__CAB_FOR_SS = 75, 1347 1348 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1349 1350 /** 1351 * Command type used for interfacing with DPIA. 1352 */ 1353 DMUB_CMD__DPIA = 77, 1354 /** 1355 * Command type used for EDID CEA parsing 1356 */ 1357 DMUB_CMD__EDID_CEA = 79, 1358 /** 1359 * Command type used for getting usbc cable ID 1360 */ 1361 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1362 /** 1363 * Command type used to query HPD state. 1364 */ 1365 DMUB_CMD__QUERY_HPD_STATE = 82, 1366 /** 1367 * Command type used for all VBIOS interface commands. 1368 */ 1369 /** 1370 * Command type used for all REPLAY commands. 1371 */ 1372 DMUB_CMD__REPLAY = 83, 1373 1374 /** 1375 * Command type used for all SECURE_DISPLAY commands. 1376 */ 1377 DMUB_CMD__SECURE_DISPLAY = 85, 1378 1379 /** 1380 * Command type used to set DPIA HPD interrupt state 1381 */ 1382 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1383 1384 /** 1385 * Command type used for all PSP commands. 1386 */ 1387 DMUB_CMD__PSP = 88, 1388 1389 DMUB_CMD__VBIOS = 128, 1390 }; 1391 1392 /** 1393 * enum dmub_out_cmd_type - DMUB outbox commands. 1394 */ 1395 enum dmub_out_cmd_type { 1396 /** 1397 * Invalid outbox command, ignored. 1398 */ 1399 DMUB_OUT_CMD__NULL = 0, 1400 /** 1401 * Command type used for DP AUX Reply data notification 1402 */ 1403 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1404 /** 1405 * Command type used for DP HPD event notification 1406 */ 1407 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1408 /** 1409 * Command type used for SET_CONFIG Reply notification 1410 */ 1411 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1412 /** 1413 * Command type used for USB4 DPIA notification 1414 */ 1415 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1416 /** 1417 * Command type used for HPD redetect notification 1418 */ 1419 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1420 }; 1421 1422 /* DMUB_CMD__DPIA command sub-types. */ 1423 enum dmub_cmd_dpia_type { 1424 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1425 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1426 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1427 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1428 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1429 }; 1430 1431 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1432 enum dmub_cmd_dpia_notification_type { 1433 DPIA_NOTIFY__BW_ALLOCATION = 0, 1434 }; 1435 1436 #pragma pack(push, 1) 1437 1438 /** 1439 * struct dmub_cmd_header - Common command header fields. 1440 */ 1441 struct dmub_cmd_header { 1442 unsigned int type : 8; /**< command type */ 1443 unsigned int sub_type : 8; /**< command sub type */ 1444 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1445 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1446 unsigned int reserved0 : 6; /**< reserved bits */ 1447 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1448 unsigned int reserved1 : 2; /**< reserved bits */ 1449 }; 1450 1451 /* 1452 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1453 * 1454 * 60 payload bytes can hold up to 5 sets of read modify writes, 1455 * each take 3 dwords. 1456 * 1457 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1458 * 1459 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1460 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1461 */ 1462 struct dmub_cmd_read_modify_write_sequence { 1463 uint32_t addr; /**< register address */ 1464 uint32_t modify_mask; /**< modify mask */ 1465 uint32_t modify_value; /**< modify value */ 1466 }; 1467 1468 /** 1469 * Maximum number of ops in read modify write sequence. 1470 */ 1471 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1472 1473 /** 1474 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1475 */ 1476 struct dmub_rb_cmd_read_modify_write { 1477 struct dmub_cmd_header header; /**< command header */ 1478 /** 1479 * Read modify write sequence. 1480 */ 1481 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1482 }; 1483 1484 /* 1485 * Update a register with specified masks and values sequeunce 1486 * 1487 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1488 * 1489 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1490 * 1491 * 1492 * USE CASE: 1493 * 1. auto-increment register where additional read would update pointer and produce wrong result 1494 * 2. toggle a bit without read in the middle 1495 */ 1496 1497 struct dmub_cmd_reg_field_update_sequence { 1498 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1499 uint32_t modify_value; /**< value to update with */ 1500 }; 1501 1502 /** 1503 * Maximum number of ops in field update sequence. 1504 */ 1505 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1506 1507 /** 1508 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1509 */ 1510 struct dmub_rb_cmd_reg_field_update_sequence { 1511 struct dmub_cmd_header header; /**< command header */ 1512 uint32_t addr; /**< register address */ 1513 /** 1514 * Field update sequence. 1515 */ 1516 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1517 }; 1518 1519 1520 /** 1521 * Maximum number of burst write values. 1522 */ 1523 #define DMUB_BURST_WRITE_VALUES__MAX 14 1524 1525 /* 1526 * struct dmub_rb_cmd_burst_write - Burst write 1527 * 1528 * support use case such as writing out LUTs. 1529 * 1530 * 60 payload bytes can hold up to 14 values to write to given address 1531 * 1532 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1533 */ 1534 struct dmub_rb_cmd_burst_write { 1535 struct dmub_cmd_header header; /**< command header */ 1536 uint32_t addr; /**< register start address */ 1537 /** 1538 * Burst write register values. 1539 */ 1540 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1541 }; 1542 1543 /** 1544 * struct dmub_rb_cmd_common - Common command header 1545 */ 1546 struct dmub_rb_cmd_common { 1547 struct dmub_cmd_header header; /**< command header */ 1548 /** 1549 * Padding to RB_CMD_SIZE 1550 */ 1551 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1552 }; 1553 1554 /** 1555 * struct dmub_cmd_reg_wait_data - Register wait data 1556 */ 1557 struct dmub_cmd_reg_wait_data { 1558 uint32_t addr; /**< Register address */ 1559 uint32_t mask; /**< Mask for register bits */ 1560 uint32_t condition_field_value; /**< Value to wait for */ 1561 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1562 }; 1563 1564 /** 1565 * struct dmub_rb_cmd_reg_wait - Register wait command 1566 */ 1567 struct dmub_rb_cmd_reg_wait { 1568 struct dmub_cmd_header header; /**< Command header */ 1569 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1570 }; 1571 1572 /** 1573 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1574 * 1575 * Reprograms surface parameters to avoid underflow. 1576 */ 1577 struct dmub_cmd_PLAT_54186_wa { 1578 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1579 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1580 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1581 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1582 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1583 struct { 1584 uint32_t hubp_inst : 4; /**< HUBP instance */ 1585 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1586 uint32_t immediate :1; /**< Immediate flip */ 1587 uint32_t vmid : 4; /**< VMID */ 1588 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1589 uint32_t reserved : 21; /**< Reserved */ 1590 } flip_params; /**< Pageflip parameters */ 1591 uint32_t reserved[9]; /**< Reserved bits */ 1592 }; 1593 1594 /** 1595 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1596 */ 1597 struct dmub_rb_cmd_PLAT_54186_wa { 1598 struct dmub_cmd_header header; /**< Command header */ 1599 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1600 }; 1601 1602 /** 1603 * enum dmub_cmd_mall_type - MALL commands 1604 */ 1605 enum dmub_cmd_mall_type { 1606 /** 1607 * Allows display refresh from MALL. 1608 */ 1609 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1610 /** 1611 * Disallows display refresh from MALL. 1612 */ 1613 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1614 /** 1615 * Cursor copy for MALL. 1616 */ 1617 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1618 /** 1619 * Controls DF requests. 1620 */ 1621 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1622 }; 1623 1624 /** 1625 * struct dmub_rb_cmd_mall - MALL command data. 1626 */ 1627 struct dmub_rb_cmd_mall { 1628 struct dmub_cmd_header header; /**< Common command header */ 1629 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1630 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1631 uint32_t tmr_delay; /**< Timer delay */ 1632 uint32_t tmr_scale; /**< Timer scale */ 1633 uint16_t cursor_width; /**< Cursor width in pixels */ 1634 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1635 uint16_t cursor_height; /**< Cursor height in pixels */ 1636 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1637 uint8_t debug_bits; /**< Debug bits */ 1638 1639 uint8_t reserved1; /**< Reserved bits */ 1640 uint8_t reserved2; /**< Reserved bits */ 1641 }; 1642 1643 /** 1644 * enum dmub_cmd_cab_type - CAB command data. 1645 */ 1646 enum dmub_cmd_cab_type { 1647 /** 1648 * No idle optimizations (i.e. no CAB) 1649 */ 1650 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1651 /** 1652 * No DCN requests for memory 1653 */ 1654 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1655 /** 1656 * Fit surfaces in CAB (i.e. CAB enable) 1657 */ 1658 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1659 /** 1660 * Do not fit surfaces in CAB (i.e. no CAB) 1661 */ 1662 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1663 }; 1664 1665 /** 1666 * struct dmub_rb_cmd_cab - CAB command data. 1667 */ 1668 struct dmub_rb_cmd_cab_for_ss { 1669 struct dmub_cmd_header header; 1670 uint8_t cab_alloc_ways; /* total number of ways */ 1671 uint8_t debug_bits; /* debug bits */ 1672 }; 1673 1674 /** 1675 * Enum for indicating which MCLK switch mode per pipe 1676 */ 1677 enum mclk_switch_mode { 1678 NONE = 0, 1679 FPO = 1, 1680 SUBVP = 2, 1681 VBLANK = 3, 1682 }; 1683 1684 /* Per pipe struct which stores the MCLK switch mode 1685 * data to be sent to DMUB. 1686 * Named "v2" for now -- once FPO and SUBVP are fully merged 1687 * the type name can be updated 1688 */ 1689 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1690 union { 1691 struct { 1692 uint32_t pix_clk_100hz; 1693 uint16_t main_vblank_start; 1694 uint16_t main_vblank_end; 1695 uint16_t mall_region_lines; 1696 uint16_t prefetch_lines; 1697 uint16_t prefetch_to_mall_start_lines; 1698 uint16_t processing_delay_lines; 1699 uint16_t htotal; // required to calculate line time for multi-display cases 1700 uint16_t vtotal; 1701 uint8_t main_pipe_index; 1702 uint8_t phantom_pipe_index; 1703 /* Since the microschedule is calculated in terms of OTG lines, 1704 * include any scaling factors to make sure when we get accurate 1705 * conversion when programming MALL_START_LINE (which is in terms 1706 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1707 * is 1/2 (numerator = 1, denominator = 2). 1708 */ 1709 uint8_t scale_factor_numerator; 1710 uint8_t scale_factor_denominator; 1711 uint8_t is_drr; 1712 uint8_t main_split_pipe_index; 1713 uint8_t phantom_split_pipe_index; 1714 } subvp_data; 1715 1716 struct { 1717 uint32_t pix_clk_100hz; 1718 uint16_t vblank_start; 1719 uint16_t vblank_end; 1720 uint16_t vstartup_start; 1721 uint16_t vtotal; 1722 uint16_t htotal; 1723 uint8_t vblank_pipe_index; 1724 uint8_t padding[1]; 1725 struct { 1726 uint8_t drr_in_use; 1727 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1728 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1729 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1730 uint8_t use_ramping; // Use ramping or not 1731 uint8_t drr_vblank_start_margin; 1732 } drr_info; // DRR considered as part of SubVP + VBLANK case 1733 } vblank_data; 1734 } pipe_config; 1735 1736 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1737 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1738 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1739 */ 1740 uint8_t mode; // enum mclk_switch_mode 1741 }; 1742 1743 /** 1744 * Config data for Sub-VP and FPO 1745 * Named "v2" for now -- once FPO and SUBVP are fully merged 1746 * the type name can be updated 1747 */ 1748 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1749 uint16_t watermark_a_cache; 1750 uint8_t vertical_int_margin_us; 1751 uint8_t pstate_allow_width_us; 1752 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1753 }; 1754 1755 /** 1756 * DMUB rb command definition for Sub-VP and FPO 1757 * Named "v2" for now -- once FPO and SUBVP are fully merged 1758 * the type name can be updated 1759 */ 1760 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1761 struct dmub_cmd_header header; 1762 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1763 }; 1764 1765 struct dmub_flip_addr_info { 1766 uint32_t surf_addr_lo; 1767 uint32_t surf_addr_c_lo; 1768 uint32_t meta_addr_lo; 1769 uint32_t meta_addr_c_lo; 1770 uint16_t surf_addr_hi; 1771 uint16_t surf_addr_c_hi; 1772 uint16_t meta_addr_hi; 1773 uint16_t meta_addr_c_hi; 1774 }; 1775 1776 struct dmub_fams2_flip_info { 1777 union { 1778 struct { 1779 uint8_t is_immediate: 1; 1780 } bits; 1781 uint8_t all; 1782 } config; 1783 uint8_t otg_inst; 1784 uint8_t pipe_mask; 1785 uint8_t pad; 1786 struct dmub_flip_addr_info addr_info; 1787 }; 1788 1789 struct dmub_rb_cmd_fams2_flip { 1790 struct dmub_cmd_header header; 1791 struct dmub_fams2_flip_info flip_info; 1792 }; 1793 1794 struct dmub_optc_state_v2 { 1795 uint32_t v_total_min; 1796 uint32_t v_total_max; 1797 uint32_t v_total_mid; 1798 uint32_t v_total_mid_frame_num; 1799 uint8_t program_manual_trigger; 1800 uint8_t tg_inst; 1801 uint8_t pad[2]; 1802 }; 1803 1804 struct dmub_optc_position { 1805 uint32_t vpos; 1806 uint32_t hpos; 1807 uint32_t frame; 1808 }; 1809 1810 struct dmub_rb_cmd_fams2_drr_update { 1811 struct dmub_cmd_header header; 1812 struct dmub_optc_state_v2 dmub_optc_state_req; 1813 }; 1814 1815 /* HW and FW global configuration data for FAMS2 */ 1816 /* FAMS2 types and structs */ 1817 enum fams2_stream_type { 1818 FAMS2_STREAM_TYPE_NONE = 0, 1819 FAMS2_STREAM_TYPE_VBLANK = 1, 1820 FAMS2_STREAM_TYPE_VACTIVE = 2, 1821 FAMS2_STREAM_TYPE_DRR = 3, 1822 FAMS2_STREAM_TYPE_SUBVP = 4, 1823 }; 1824 1825 /* dynamic stream state */ 1826 struct dmub_fams2_legacy_stream_dynamic_state { 1827 uint8_t force_allow_at_vblank; 1828 uint8_t pad[3]; 1829 }; 1830 1831 struct dmub_fams2_subvp_stream_dynamic_state { 1832 uint16_t viewport_start_hubp_vline; 1833 uint16_t viewport_height_hubp_vlines; 1834 uint16_t viewport_start_c_hubp_vline; 1835 uint16_t viewport_height_c_hubp_vlines; 1836 uint16_t phantom_viewport_height_hubp_vlines; 1837 uint16_t phantom_viewport_height_c_hubp_vlines; 1838 uint16_t microschedule_start_otg_vline; 1839 uint16_t mall_start_otg_vline; 1840 uint16_t mall_start_hubp_vline; 1841 uint16_t mall_start_c_hubp_vline; 1842 uint8_t force_allow_at_vblank_only; 1843 uint8_t pad[3]; 1844 }; 1845 1846 struct dmub_fams2_drr_stream_dynamic_state { 1847 uint16_t stretched_vtotal; 1848 uint8_t use_cur_vtotal; 1849 uint8_t pad; 1850 }; 1851 1852 struct dmub_fams2_stream_dynamic_state { 1853 uint64_t ref_tick; 1854 uint32_t cur_vtotal; 1855 uint16_t adjusted_allow_end_otg_vline; 1856 uint8_t pad[2]; 1857 struct dmub_optc_position ref_otg_pos; 1858 struct dmub_optc_position target_otg_pos; 1859 union { 1860 struct dmub_fams2_legacy_stream_dynamic_state legacy; 1861 struct dmub_fams2_subvp_stream_dynamic_state subvp; 1862 struct dmub_fams2_drr_stream_dynamic_state drr; 1863 } sub_state; 1864 }; 1865 1866 /* static stream state */ 1867 struct dmub_fams2_legacy_stream_static_state { 1868 uint8_t vactive_det_fill_delay_otg_vlines; 1869 uint8_t programming_delay_otg_vlines; 1870 }; 1871 1872 struct dmub_fams2_subvp_stream_static_state { 1873 uint16_t vratio_numerator; 1874 uint16_t vratio_denominator; 1875 uint16_t phantom_vtotal; 1876 uint16_t phantom_vactive; 1877 union { 1878 struct { 1879 uint8_t is_multi_planar : 1; 1880 uint8_t is_yuv420 : 1; 1881 } bits; 1882 uint8_t all; 1883 } config; 1884 uint8_t programming_delay_otg_vlines; 1885 uint8_t prefetch_to_mall_otg_vlines; 1886 uint8_t phantom_otg_inst; 1887 uint8_t phantom_pipe_mask; 1888 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1889 }; 1890 1891 struct dmub_fams2_drr_stream_static_state { 1892 uint16_t nom_stretched_vtotal; 1893 uint8_t programming_delay_otg_vlines; 1894 uint8_t only_stretch_if_required; 1895 uint8_t pad[2]; 1896 }; 1897 1898 struct dmub_fams2_stream_static_state { 1899 enum fams2_stream_type type; 1900 uint32_t otg_vline_time_ns; 1901 uint32_t otg_vline_time_ticks; 1902 uint16_t htotal; 1903 uint16_t vtotal; // nominal vtotal 1904 uint16_t vblank_start; 1905 uint16_t vblank_end; 1906 uint16_t max_vtotal; 1907 uint16_t allow_start_otg_vline; 1908 uint16_t allow_end_otg_vline; 1909 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1910 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1911 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 1912 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1913 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1914 union { 1915 struct { 1916 uint8_t is_drr: 1; // stream is DRR enabled 1917 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 1918 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1919 } bits; 1920 uint8_t all; 1921 } config; 1922 uint8_t otg_inst; 1923 uint8_t pipe_mask; // pipe mask for the whole config 1924 uint8_t num_planes; 1925 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1926 uint8_t pad[DMUB_MAX_PLANES % 4]; 1927 union { 1928 struct dmub_fams2_legacy_stream_static_state legacy; 1929 struct dmub_fams2_subvp_stream_static_state subvp; 1930 struct dmub_fams2_drr_stream_static_state drr; 1931 } sub_state; 1932 }; 1933 1934 /** 1935 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 1936 * p-state request to allow latency 1937 */ 1938 enum dmub_fams2_allow_delay_check_mode { 1939 /* No check for request to allow delay */ 1940 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 1941 /* Check for request to allow delay */ 1942 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 1943 /* Check for prepare to allow delay */ 1944 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 1945 }; 1946 1947 union dmub_fams2_global_feature_config { 1948 struct { 1949 uint32_t enable: 1; 1950 uint32_t enable_ppt_check: 1; 1951 uint32_t enable_stall_recovery: 1; 1952 uint32_t enable_debug: 1; 1953 uint32_t enable_offload_flip: 1; 1954 uint32_t enable_visual_confirm: 1; 1955 uint32_t allow_delay_check_mode: 2; 1956 uint32_t reserved: 24; 1957 } bits; 1958 uint32_t all; 1959 }; 1960 1961 struct dmub_cmd_fams2_global_config { 1962 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 1963 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 1964 uint32_t num_streams; 1965 union dmub_fams2_global_feature_config features; 1966 uint32_t recovery_timeout_us; 1967 uint32_t hwfq_flip_programming_delay_us; 1968 }; 1969 1970 union dmub_cmd_fams2_config { 1971 struct dmub_cmd_fams2_global_config global; 1972 struct dmub_fams2_stream_static_state stream; 1973 }; 1974 1975 /** 1976 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 1977 */ 1978 struct dmub_rb_cmd_fams2 { 1979 struct dmub_cmd_header header; 1980 union dmub_cmd_fams2_config config; 1981 }; 1982 1983 /** 1984 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1985 */ 1986 enum dmub_cmd_idle_opt_type { 1987 /** 1988 * DCN hardware restore. 1989 */ 1990 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1991 1992 /** 1993 * DCN hardware save. 1994 */ 1995 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1996 1997 /** 1998 * DCN hardware notify idle. 1999 */ 2000 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2001 2002 /** 2003 * DCN hardware notify power state. 2004 */ 2005 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2006 }; 2007 2008 /** 2009 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2010 */ 2011 struct dmub_rb_cmd_idle_opt_dcn_restore { 2012 struct dmub_cmd_header header; /**< header */ 2013 }; 2014 2015 /** 2016 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2017 */ 2018 struct dmub_dcn_notify_idle_cntl_data { 2019 uint8_t driver_idle; 2020 uint8_t skip_otg_disable; 2021 uint8_t reserved[58]; 2022 }; 2023 2024 /** 2025 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2026 */ 2027 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2028 struct dmub_cmd_header header; /**< header */ 2029 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2030 }; 2031 2032 /** 2033 * enum dmub_idle_opt_dc_power_state - DC power states. 2034 */ 2035 enum dmub_idle_opt_dc_power_state { 2036 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2037 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2038 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2039 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2040 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2041 }; 2042 2043 /** 2044 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2045 */ 2046 struct dmub_idle_opt_set_dc_power_state_data { 2047 uint8_t power_state; /**< power state */ 2048 uint8_t pad[3]; /**< padding */ 2049 }; 2050 2051 /** 2052 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2053 */ 2054 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2055 struct dmub_cmd_header header; /**< header */ 2056 struct dmub_idle_opt_set_dc_power_state_data data; 2057 }; 2058 2059 /** 2060 * struct dmub_clocks - Clock update notification. 2061 */ 2062 struct dmub_clocks { 2063 uint32_t dispclk_khz; /**< dispclk kHz */ 2064 uint32_t dppclk_khz; /**< dppclk kHz */ 2065 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2066 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2067 }; 2068 2069 /** 2070 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2071 */ 2072 enum dmub_cmd_clk_mgr_type { 2073 /** 2074 * Notify DMCUB of clock update. 2075 */ 2076 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2077 }; 2078 2079 /** 2080 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2081 */ 2082 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2083 struct dmub_cmd_header header; /**< header */ 2084 struct dmub_clocks clocks; /**< clock data */ 2085 }; 2086 2087 /** 2088 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2089 */ 2090 struct dmub_cmd_digx_encoder_control_data { 2091 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2092 }; 2093 2094 /** 2095 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2096 */ 2097 struct dmub_rb_cmd_digx_encoder_control { 2098 struct dmub_cmd_header header; /**< header */ 2099 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2100 }; 2101 2102 /** 2103 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2104 */ 2105 struct dmub_cmd_set_pixel_clock_data { 2106 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2107 }; 2108 2109 /** 2110 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2111 */ 2112 struct dmub_rb_cmd_set_pixel_clock { 2113 struct dmub_cmd_header header; /**< header */ 2114 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2115 }; 2116 2117 /** 2118 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2119 */ 2120 struct dmub_cmd_enable_disp_power_gating_data { 2121 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2122 }; 2123 2124 /** 2125 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2126 */ 2127 struct dmub_rb_cmd_enable_disp_power_gating { 2128 struct dmub_cmd_header header; /**< header */ 2129 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2130 }; 2131 2132 /** 2133 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2134 */ 2135 struct dmub_dig_transmitter_control_data_v1_7 { 2136 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2137 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2138 union { 2139 uint8_t digmode; /**< enum atom_encode_mode_def */ 2140 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2141 } mode_laneset; 2142 uint8_t lanenum; /**< Number of lanes */ 2143 union { 2144 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2145 } symclk_units; 2146 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2147 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2148 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2149 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2150 uint8_t reserved1; /**< For future use */ 2151 uint8_t reserved2[3]; /**< For future use */ 2152 uint32_t reserved3[11]; /**< For future use */ 2153 }; 2154 2155 /** 2156 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2157 */ 2158 union dmub_cmd_dig1_transmitter_control_data { 2159 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2160 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2161 }; 2162 2163 /** 2164 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2165 */ 2166 struct dmub_rb_cmd_dig1_transmitter_control { 2167 struct dmub_cmd_header header; /**< header */ 2168 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2169 }; 2170 2171 /** 2172 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2173 */ 2174 struct dmub_rb_cmd_domain_control_data { 2175 uint8_t inst : 6; /**< DOMAIN instance to control */ 2176 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2177 uint8_t reserved[3]; /**< Reserved for future use */ 2178 }; 2179 2180 /** 2181 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2182 */ 2183 struct dmub_rb_cmd_domain_control { 2184 struct dmub_cmd_header header; /**< header */ 2185 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2186 }; 2187 2188 /** 2189 * DPIA tunnel command parameters. 2190 */ 2191 struct dmub_cmd_dig_dpia_control_data { 2192 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2193 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2194 union { 2195 uint8_t digmode; /** enum atom_encode_mode_def */ 2196 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2197 } mode_laneset; 2198 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2199 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2200 uint8_t hpdsel; /** =0: HPD is not assigned */ 2201 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2202 uint8_t dpia_id; /** Index of DPIA */ 2203 uint8_t fec_rdy : 1; 2204 uint8_t reserved : 7; 2205 uint32_t reserved1; 2206 }; 2207 2208 /** 2209 * DMUB command for DPIA tunnel control. 2210 */ 2211 struct dmub_rb_cmd_dig1_dpia_control { 2212 struct dmub_cmd_header header; 2213 struct dmub_cmd_dig_dpia_control_data dpia_control; 2214 }; 2215 2216 /** 2217 * SET_CONFIG Command Payload (deprecated) 2218 */ 2219 struct set_config_cmd_payload { 2220 uint8_t msg_type; /* set config message type */ 2221 uint8_t msg_data; /* set config message data */ 2222 }; 2223 2224 /** 2225 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2226 */ 2227 struct dmub_cmd_set_config_control_data { 2228 struct set_config_cmd_payload cmd_pkt; 2229 uint8_t instance; /* DPIA instance */ 2230 uint8_t immed_status; /* Immediate status returned in case of error */ 2231 }; 2232 2233 /** 2234 * SET_CONFIG Request Command Payload 2235 */ 2236 struct set_config_request_cmd_payload { 2237 uint8_t instance; /* DPIA instance */ 2238 uint8_t immed_status; /* Immediate status returned in case of error */ 2239 uint8_t msg_type; /* set config message type */ 2240 uint8_t reserved; 2241 uint32_t msg_data; /* set config message data */ 2242 }; 2243 2244 /** 2245 * DMUB command structure for SET_CONFIG command. 2246 */ 2247 struct dmub_rb_cmd_set_config_access { 2248 struct dmub_cmd_header header; /* header */ 2249 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2250 }; 2251 2252 /** 2253 * DMUB command structure for SET_CONFIG request command. 2254 */ 2255 struct dmub_rb_cmd_set_config_request { 2256 struct dmub_cmd_header header; /* header */ 2257 struct set_config_request_cmd_payload payload; /* set config request payload */ 2258 }; 2259 2260 /** 2261 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2262 */ 2263 struct dmub_cmd_mst_alloc_slots_control_data { 2264 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2265 uint8_t instance; /* DPIA instance */ 2266 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2267 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2268 }; 2269 2270 /** 2271 * DMUB command structure for SET_ command. 2272 */ 2273 struct dmub_rb_cmd_set_mst_alloc_slots { 2274 struct dmub_cmd_header header; /* header */ 2275 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2276 }; 2277 2278 /** 2279 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2280 */ 2281 struct dmub_cmd_tps_notification_data { 2282 uint8_t instance; /* DPIA instance */ 2283 uint8_t tps; /* requested training pattern */ 2284 uint8_t reserved1; 2285 uint8_t reserved2; 2286 }; 2287 2288 /** 2289 * DMUB command structure for SET_TPS_NOTIFICATION command. 2290 */ 2291 struct dmub_rb_cmd_set_tps_notification { 2292 struct dmub_cmd_header header; /* header */ 2293 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2294 }; 2295 2296 /** 2297 * DMUB command structure for DPIA HPD int enable control. 2298 */ 2299 struct dmub_rb_cmd_dpia_hpd_int_enable { 2300 struct dmub_cmd_header header; /* header */ 2301 uint32_t enable; /* dpia hpd interrupt enable */ 2302 }; 2303 2304 /** 2305 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2306 */ 2307 struct dmub_rb_cmd_dpphy_init { 2308 struct dmub_cmd_header header; /**< header */ 2309 uint8_t reserved[60]; /**< reserved bits */ 2310 }; 2311 2312 /** 2313 * enum dp_aux_request_action - DP AUX request command listing. 2314 * 2315 * 4 AUX request command bits are shifted to high nibble. 2316 */ 2317 enum dp_aux_request_action { 2318 /** I2C-over-AUX write request */ 2319 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2320 /** I2C-over-AUX read request */ 2321 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2322 /** I2C-over-AUX write status request */ 2323 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2324 /** I2C-over-AUX write request with MOT=1 */ 2325 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2326 /** I2C-over-AUX read request with MOT=1 */ 2327 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2328 /** I2C-over-AUX write status request with MOT=1 */ 2329 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2330 /** Native AUX write request */ 2331 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2332 /** Native AUX read request */ 2333 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2334 }; 2335 2336 /** 2337 * enum aux_return_code_type - DP AUX process return code listing. 2338 */ 2339 enum aux_return_code_type { 2340 /** AUX process succeeded */ 2341 AUX_RET_SUCCESS = 0, 2342 /** AUX process failed with unknown reason */ 2343 AUX_RET_ERROR_UNKNOWN, 2344 /** AUX process completed with invalid reply */ 2345 AUX_RET_ERROR_INVALID_REPLY, 2346 /** AUX process timed out */ 2347 AUX_RET_ERROR_TIMEOUT, 2348 /** HPD was low during AUX process */ 2349 AUX_RET_ERROR_HPD_DISCON, 2350 /** Failed to acquire AUX engine */ 2351 AUX_RET_ERROR_ENGINE_ACQUIRE, 2352 /** AUX request not supported */ 2353 AUX_RET_ERROR_INVALID_OPERATION, 2354 /** AUX process not available */ 2355 AUX_RET_ERROR_PROTOCOL_ERROR, 2356 }; 2357 2358 /** 2359 * enum aux_channel_type - DP AUX channel type listing. 2360 */ 2361 enum aux_channel_type { 2362 /** AUX thru Legacy DP AUX */ 2363 AUX_CHANNEL_LEGACY_DDC, 2364 /** AUX thru DPIA DP tunneling */ 2365 AUX_CHANNEL_DPIA 2366 }; 2367 2368 /** 2369 * struct aux_transaction_parameters - DP AUX request transaction data 2370 */ 2371 struct aux_transaction_parameters { 2372 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2373 uint8_t action; /**< enum dp_aux_request_action */ 2374 uint8_t length; /**< DP AUX request data length */ 2375 uint8_t reserved; /**< For future use */ 2376 uint32_t address; /**< DP AUX address */ 2377 uint8_t data[16]; /**< DP AUX write data */ 2378 }; 2379 2380 /** 2381 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2382 */ 2383 struct dmub_cmd_dp_aux_control_data { 2384 uint8_t instance; /**< AUX instance or DPIA instance */ 2385 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2386 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2387 uint8_t reserved0; /**< For future use */ 2388 uint16_t timeout; /**< timeout time in us */ 2389 uint16_t reserved1; /**< For future use */ 2390 enum aux_channel_type type; /**< enum aux_channel_type */ 2391 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2392 }; 2393 2394 /** 2395 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2396 */ 2397 struct dmub_rb_cmd_dp_aux_access { 2398 /** 2399 * Command header. 2400 */ 2401 struct dmub_cmd_header header; 2402 /** 2403 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2404 */ 2405 struct dmub_cmd_dp_aux_control_data aux_control; 2406 }; 2407 2408 /** 2409 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2410 */ 2411 struct dmub_rb_cmd_outbox1_enable { 2412 /** 2413 * Command header. 2414 */ 2415 struct dmub_cmd_header header; 2416 /** 2417 * enable: 0x0 -> disable outbox1 notification (default value) 2418 * 0x1 -> enable outbox1 notification 2419 */ 2420 uint32_t enable; 2421 }; 2422 2423 /* DP AUX Reply command - OutBox Cmd */ 2424 /** 2425 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2426 */ 2427 struct aux_reply_data { 2428 /** 2429 * Aux cmd 2430 */ 2431 uint8_t command; 2432 /** 2433 * Aux reply data length (max: 16 bytes) 2434 */ 2435 uint8_t length; 2436 /** 2437 * Alignment only 2438 */ 2439 uint8_t pad[2]; 2440 /** 2441 * Aux reply data 2442 */ 2443 uint8_t data[16]; 2444 }; 2445 2446 /** 2447 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2448 */ 2449 struct aux_reply_control_data { 2450 /** 2451 * Reserved for future use 2452 */ 2453 uint32_t handle; 2454 /** 2455 * Aux Instance 2456 */ 2457 uint8_t instance; 2458 /** 2459 * Aux transaction result: definition in enum aux_return_code_type 2460 */ 2461 uint8_t result; 2462 /** 2463 * Alignment only 2464 */ 2465 uint16_t pad; 2466 }; 2467 2468 /** 2469 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2470 */ 2471 struct dmub_rb_cmd_dp_aux_reply { 2472 /** 2473 * Command header. 2474 */ 2475 struct dmub_cmd_header header; 2476 /** 2477 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2478 */ 2479 struct aux_reply_control_data control; 2480 /** 2481 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2482 */ 2483 struct aux_reply_data reply_data; 2484 }; 2485 2486 /* DP HPD Notify command - OutBox Cmd */ 2487 /** 2488 * DP HPD Type 2489 */ 2490 enum dp_hpd_type { 2491 /** 2492 * Normal DP HPD 2493 */ 2494 DP_HPD = 0, 2495 /** 2496 * DP HPD short pulse 2497 */ 2498 DP_IRQ 2499 }; 2500 2501 /** 2502 * DP HPD Status 2503 */ 2504 enum dp_hpd_status { 2505 /** 2506 * DP_HPD status low 2507 */ 2508 DP_HPD_UNPLUG = 0, 2509 /** 2510 * DP_HPD status high 2511 */ 2512 DP_HPD_PLUG 2513 }; 2514 2515 /** 2516 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2517 */ 2518 struct dp_hpd_data { 2519 /** 2520 * DP HPD instance 2521 */ 2522 uint8_t instance; 2523 /** 2524 * HPD type 2525 */ 2526 uint8_t hpd_type; 2527 /** 2528 * HPD status: only for type: DP_HPD to indicate status 2529 */ 2530 uint8_t hpd_status; 2531 /** 2532 * Alignment only 2533 */ 2534 uint8_t pad; 2535 }; 2536 2537 /** 2538 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2539 */ 2540 struct dmub_rb_cmd_dp_hpd_notify { 2541 /** 2542 * Command header. 2543 */ 2544 struct dmub_cmd_header header; 2545 /** 2546 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2547 */ 2548 struct dp_hpd_data hpd_data; 2549 }; 2550 2551 /** 2552 * Definition of a SET_CONFIG reply from DPOA. 2553 */ 2554 enum set_config_status { 2555 SET_CONFIG_PENDING = 0, 2556 SET_CONFIG_ACK_RECEIVED, 2557 SET_CONFIG_RX_TIMEOUT, 2558 SET_CONFIG_UNKNOWN_ERROR, 2559 }; 2560 2561 /** 2562 * Definition of a set_config reply 2563 */ 2564 struct set_config_reply_control_data { 2565 uint8_t instance; /* DPIA Instance */ 2566 uint8_t status; /* Set Config reply */ 2567 uint16_t pad; /* Alignment */ 2568 }; 2569 2570 /** 2571 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2572 */ 2573 struct dmub_rb_cmd_dp_set_config_reply { 2574 struct dmub_cmd_header header; 2575 struct set_config_reply_control_data set_config_reply_control; 2576 }; 2577 2578 /** 2579 * Definition of a DPIA notification header 2580 */ 2581 struct dpia_notification_header { 2582 uint8_t instance; /**< DPIA Instance */ 2583 uint8_t reserved[3]; 2584 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2585 }; 2586 2587 /** 2588 * Definition of the common data struct of DPIA notification 2589 */ 2590 struct dpia_notification_common { 2591 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2592 - sizeof(struct dpia_notification_header)]; 2593 }; 2594 2595 /** 2596 * Definition of a DPIA notification data 2597 */ 2598 struct dpia_bw_allocation_notify_data { 2599 union { 2600 struct { 2601 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2602 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2603 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2604 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2605 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2606 uint16_t reserved: 11; /**< Reserved */ 2607 } bits; 2608 2609 uint16_t flags; 2610 }; 2611 2612 uint8_t cm_id; /**< CM ID */ 2613 uint8_t group_id; /**< Group ID */ 2614 uint8_t granularity; /**< BW Allocation Granularity */ 2615 uint8_t estimated_bw; /**< Estimated_BW */ 2616 uint8_t allocated_bw; /**< Allocated_BW */ 2617 uint8_t reserved; 2618 }; 2619 2620 /** 2621 * union dpia_notify_data_type - DPIA Notification in Outbox command 2622 */ 2623 union dpia_notification_data { 2624 /** 2625 * DPIA Notification for common data struct 2626 */ 2627 struct dpia_notification_common common_data; 2628 2629 /** 2630 * DPIA Notification for DP BW Allocation support 2631 */ 2632 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2633 }; 2634 2635 /** 2636 * Definition of a DPIA notification payload 2637 */ 2638 struct dpia_notification_payload { 2639 struct dpia_notification_header header; 2640 union dpia_notification_data data; /**< DPIA notification payload data */ 2641 }; 2642 2643 /** 2644 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2645 */ 2646 struct dmub_rb_cmd_dpia_notification { 2647 struct dmub_cmd_header header; /**< DPIA notification header */ 2648 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2649 }; 2650 2651 /** 2652 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2653 */ 2654 struct dmub_cmd_hpd_state_query_data { 2655 uint8_t instance; /**< HPD instance or DPIA instance */ 2656 uint8_t result; /**< For returning HPD state */ 2657 uint16_t pad; /** < Alignment */ 2658 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2659 enum aux_return_code_type status; /**< for returning the status of command */ 2660 }; 2661 2662 /** 2663 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2664 */ 2665 struct dmub_rb_cmd_query_hpd_state { 2666 /** 2667 * Command header. 2668 */ 2669 struct dmub_cmd_header header; 2670 /** 2671 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2672 */ 2673 struct dmub_cmd_hpd_state_query_data data; 2674 }; 2675 2676 /** 2677 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2678 */ 2679 struct dmub_rb_cmd_hpd_sense_notify_data { 2680 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2681 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2682 }; 2683 2684 /** 2685 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2686 */ 2687 struct dmub_rb_cmd_hpd_sense_notify { 2688 struct dmub_cmd_header header; /**< header */ 2689 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2690 }; 2691 2692 /* 2693 * Command IDs should be treated as stable ABI. 2694 * Do not reuse or modify IDs. 2695 */ 2696 2697 /** 2698 * PSR command sub-types. 2699 */ 2700 enum dmub_cmd_psr_type { 2701 /** 2702 * Set PSR version support. 2703 */ 2704 DMUB_CMD__PSR_SET_VERSION = 0, 2705 /** 2706 * Copy driver-calculated parameters to PSR state. 2707 */ 2708 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2709 /** 2710 * Enable PSR. 2711 */ 2712 DMUB_CMD__PSR_ENABLE = 2, 2713 2714 /** 2715 * Disable PSR. 2716 */ 2717 DMUB_CMD__PSR_DISABLE = 3, 2718 2719 /** 2720 * Set PSR level. 2721 * PSR level is a 16-bit value dicated by driver that 2722 * will enable/disable different functionality. 2723 */ 2724 DMUB_CMD__PSR_SET_LEVEL = 4, 2725 2726 /** 2727 * Forces PSR enabled until an explicit PSR disable call. 2728 */ 2729 DMUB_CMD__PSR_FORCE_STATIC = 5, 2730 /** 2731 * Set vtotal in psr active for FreeSync PSR. 2732 */ 2733 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2734 /** 2735 * Set PSR power option 2736 */ 2737 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2738 }; 2739 2740 /** 2741 * Different PSR residency modes. 2742 * Different modes change the definition of PSR residency. 2743 */ 2744 enum psr_residency_mode { 2745 PSR_RESIDENCY_MODE_PHY = 0, 2746 PSR_RESIDENCY_MODE_ALPM, 2747 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2748 /* Do not add below. */ 2749 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2750 }; 2751 2752 enum dmub_cmd_fams_type { 2753 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2754 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2755 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2756 /** 2757 * For SubVP set manual trigger in FW because it 2758 * triggers DRR_UPDATE_PENDING which SubVP relies 2759 * on (for any SubVP cases that use a DRR display) 2760 */ 2761 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2762 DMUB_CMD__FAMS2_CONFIG = 4, 2763 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2764 DMUB_CMD__FAMS2_FLIP = 6, 2765 }; 2766 2767 /** 2768 * PSR versions. 2769 */ 2770 enum psr_version { 2771 /** 2772 * PSR version 1. 2773 */ 2774 PSR_VERSION_1 = 0, 2775 /** 2776 * Freesync PSR SU. 2777 */ 2778 PSR_VERSION_SU_1 = 1, 2779 /** 2780 * PSR not supported. 2781 */ 2782 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2783 }; 2784 2785 /** 2786 * PHY Link rate for DP. 2787 */ 2788 enum phy_link_rate { 2789 /** 2790 * not supported. 2791 */ 2792 PHY_RATE_UNKNOWN = 0, 2793 /** 2794 * Rate_1 (RBR) - 1.62 Gbps/Lane 2795 */ 2796 PHY_RATE_162 = 1, 2797 /** 2798 * Rate_2 - 2.16 Gbps/Lane 2799 */ 2800 PHY_RATE_216 = 2, 2801 /** 2802 * Rate_3 - 2.43 Gbps/Lane 2803 */ 2804 PHY_RATE_243 = 3, 2805 /** 2806 * Rate_4 (HBR) - 2.70 Gbps/Lane 2807 */ 2808 PHY_RATE_270 = 4, 2809 /** 2810 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2811 */ 2812 PHY_RATE_324 = 5, 2813 /** 2814 * Rate_6 - 4.32 Gbps/Lane 2815 */ 2816 PHY_RATE_432 = 6, 2817 /** 2818 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2819 */ 2820 PHY_RATE_540 = 7, 2821 /** 2822 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2823 */ 2824 PHY_RATE_810 = 8, 2825 /** 2826 * UHBR10 - 10.0 Gbps/Lane 2827 */ 2828 PHY_RATE_1000 = 9, 2829 /** 2830 * UHBR13.5 - 13.5 Gbps/Lane 2831 */ 2832 PHY_RATE_1350 = 10, 2833 /** 2834 * UHBR10 - 20.0 Gbps/Lane 2835 */ 2836 PHY_RATE_2000 = 11, 2837 2838 PHY_RATE_675 = 12, 2839 /** 2840 * Rate 12 - 6.75 Gbps/Lane 2841 */ 2842 }; 2843 2844 /** 2845 * enum dmub_phy_fsm_state - PHY FSM states. 2846 * PHY FSM state to transit to during PSR enable/disable. 2847 */ 2848 enum dmub_phy_fsm_state { 2849 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2850 DMUB_PHY_FSM_RESET, 2851 DMUB_PHY_FSM_RESET_RELEASED, 2852 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2853 DMUB_PHY_FSM_INITIALIZED, 2854 DMUB_PHY_FSM_CALIBRATED, 2855 DMUB_PHY_FSM_CALIBRATED_LP, 2856 DMUB_PHY_FSM_CALIBRATED_PG, 2857 DMUB_PHY_FSM_POWER_DOWN, 2858 DMUB_PHY_FSM_PLL_EN, 2859 DMUB_PHY_FSM_TX_EN, 2860 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2861 DMUB_PHY_FSM_FAST_LP, 2862 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2863 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2864 DMUB_PHY_FSM_P2_PLL_OFF, 2865 DMUB_PHY_FSM_P2_PLL_ON, 2866 }; 2867 2868 /** 2869 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2870 */ 2871 struct dmub_cmd_psr_copy_settings_data { 2872 /** 2873 * Flags that can be set by driver to change some PSR behaviour. 2874 */ 2875 union dmub_psr_debug_flags debug; 2876 /** 2877 * 16-bit value dicated by driver that will enable/disable different functionality. 2878 */ 2879 uint16_t psr_level; 2880 /** 2881 * DPP HW instance. 2882 */ 2883 uint8_t dpp_inst; 2884 /** 2885 * MPCC HW instance. 2886 * Not used in dmub fw, 2887 * dmub fw will get active opp by reading odm registers. 2888 */ 2889 uint8_t mpcc_inst; 2890 /** 2891 * OPP HW instance. 2892 * Not used in dmub fw, 2893 * dmub fw will get active opp by reading odm registers. 2894 */ 2895 uint8_t opp_inst; 2896 /** 2897 * OTG HW instance. 2898 */ 2899 uint8_t otg_inst; 2900 /** 2901 * DIG FE HW instance. 2902 */ 2903 uint8_t digfe_inst; 2904 /** 2905 * DIG BE HW instance. 2906 */ 2907 uint8_t digbe_inst; 2908 /** 2909 * DP PHY HW instance. 2910 */ 2911 uint8_t dpphy_inst; 2912 /** 2913 * AUX HW instance. 2914 */ 2915 uint8_t aux_inst; 2916 /** 2917 * Determines if SMU optimzations are enabled/disabled. 2918 */ 2919 uint8_t smu_optimizations_en; 2920 /** 2921 * Unused. 2922 * TODO: Remove. 2923 */ 2924 uint8_t frame_delay; 2925 /** 2926 * If RFB setup time is greater than the total VBLANK time, 2927 * it is not possible for the sink to capture the video frame 2928 * in the same frame the SDP is sent. In this case, 2929 * the frame capture indication bit should be set and an extra 2930 * static frame should be transmitted to the sink. 2931 */ 2932 uint8_t frame_cap_ind; 2933 /** 2934 * Granularity of Y offset supported by sink. 2935 */ 2936 uint8_t su_y_granularity; 2937 /** 2938 * Indicates whether sink should start capturing 2939 * immediately following active scan line, 2940 * or starting with the 2nd active scan line. 2941 */ 2942 uint8_t line_capture_indication; 2943 /** 2944 * Multi-display optimizations are implemented on certain ASICs. 2945 */ 2946 uint8_t multi_disp_optimizations_en; 2947 /** 2948 * The last possible line SDP may be transmitted without violating 2949 * the RFB setup time or entering the active video frame. 2950 */ 2951 uint16_t init_sdp_deadline; 2952 /** 2953 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2954 */ 2955 uint8_t rate_control_caps ; 2956 /* 2957 * Force PSRSU always doing full frame update 2958 */ 2959 uint8_t force_ffu_mode; 2960 /** 2961 * Length of each horizontal line in us. 2962 */ 2963 uint32_t line_time_in_us; 2964 /** 2965 * FEC enable status in driver 2966 */ 2967 uint8_t fec_enable_status; 2968 /** 2969 * FEC re-enable delay when PSR exit. 2970 * unit is 100us, range form 0~255(0xFF). 2971 */ 2972 uint8_t fec_enable_delay_in100us; 2973 /** 2974 * PSR control version. 2975 */ 2976 uint8_t cmd_version; 2977 /** 2978 * Panel Instance. 2979 * Panel instance to identify which psr_state to use 2980 * Currently the support is only for 0 or 1 2981 */ 2982 uint8_t panel_inst; 2983 /* 2984 * DSC enable status in driver 2985 */ 2986 uint8_t dsc_enable_status; 2987 /* 2988 * Use FSM state for PSR power up/down 2989 */ 2990 uint8_t use_phy_fsm; 2991 /** 2992 * frame delay for frame re-lock 2993 */ 2994 uint8_t relock_delay_frame_cnt; 2995 /** 2996 * esd recovery indicate. 2997 */ 2998 uint8_t esd_recovery; 2999 /** 3000 * DSC Slice height. 3001 */ 3002 uint16_t dsc_slice_height; 3003 /** 3004 * Some panels request main link off before xth vertical line 3005 */ 3006 uint16_t poweroff_before_vertical_line; 3007 }; 3008 3009 /** 3010 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3011 */ 3012 struct dmub_rb_cmd_psr_copy_settings { 3013 /** 3014 * Command header. 3015 */ 3016 struct dmub_cmd_header header; 3017 /** 3018 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3019 */ 3020 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3021 }; 3022 3023 /** 3024 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3025 */ 3026 struct dmub_cmd_psr_set_level_data { 3027 /** 3028 * 16-bit value dicated by driver that will enable/disable different functionality. 3029 */ 3030 uint16_t psr_level; 3031 /** 3032 * PSR control version. 3033 */ 3034 uint8_t cmd_version; 3035 /** 3036 * Panel Instance. 3037 * Panel instance to identify which psr_state to use 3038 * Currently the support is only for 0 or 1 3039 */ 3040 uint8_t panel_inst; 3041 }; 3042 3043 /** 3044 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3045 */ 3046 struct dmub_rb_cmd_psr_set_level { 3047 /** 3048 * Command header. 3049 */ 3050 struct dmub_cmd_header header; 3051 /** 3052 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3053 */ 3054 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3055 }; 3056 3057 struct dmub_rb_cmd_psr_enable_data { 3058 /** 3059 * PSR control version. 3060 */ 3061 uint8_t cmd_version; 3062 /** 3063 * Panel Instance. 3064 * Panel instance to identify which psr_state to use 3065 * Currently the support is only for 0 or 1 3066 */ 3067 uint8_t panel_inst; 3068 /** 3069 * Phy state to enter. 3070 * Values to use are defined in dmub_phy_fsm_state 3071 */ 3072 uint8_t phy_fsm_state; 3073 /** 3074 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3075 * Set this using enum phy_link_rate. 3076 * This does not support HDMI/DP2 for now. 3077 */ 3078 uint8_t phy_rate; 3079 }; 3080 3081 /** 3082 * Definition of a DMUB_CMD__PSR_ENABLE command. 3083 * PSR enable/disable is controlled using the sub_type. 3084 */ 3085 struct dmub_rb_cmd_psr_enable { 3086 /** 3087 * Command header. 3088 */ 3089 struct dmub_cmd_header header; 3090 3091 struct dmub_rb_cmd_psr_enable_data data; 3092 }; 3093 3094 /** 3095 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3096 */ 3097 struct dmub_cmd_psr_set_version_data { 3098 /** 3099 * PSR version that FW should implement. 3100 */ 3101 enum psr_version version; 3102 /** 3103 * PSR control version. 3104 */ 3105 uint8_t cmd_version; 3106 /** 3107 * Panel Instance. 3108 * Panel instance to identify which psr_state to use 3109 * Currently the support is only for 0 or 1 3110 */ 3111 uint8_t panel_inst; 3112 /** 3113 * Explicit padding to 4 byte boundary. 3114 */ 3115 uint8_t pad[2]; 3116 }; 3117 3118 /** 3119 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3120 */ 3121 struct dmub_rb_cmd_psr_set_version { 3122 /** 3123 * Command header. 3124 */ 3125 struct dmub_cmd_header header; 3126 /** 3127 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3128 */ 3129 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3130 }; 3131 3132 struct dmub_cmd_psr_force_static_data { 3133 /** 3134 * PSR control version. 3135 */ 3136 uint8_t cmd_version; 3137 /** 3138 * Panel Instance. 3139 * Panel instance to identify which psr_state to use 3140 * Currently the support is only for 0 or 1 3141 */ 3142 uint8_t panel_inst; 3143 /** 3144 * Explicit padding to 4 byte boundary. 3145 */ 3146 uint8_t pad[2]; 3147 }; 3148 3149 /** 3150 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3151 */ 3152 struct dmub_rb_cmd_psr_force_static { 3153 /** 3154 * Command header. 3155 */ 3156 struct dmub_cmd_header header; 3157 /** 3158 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3159 */ 3160 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3161 }; 3162 3163 /** 3164 * PSR SU debug flags. 3165 */ 3166 union dmub_psr_su_debug_flags { 3167 /** 3168 * PSR SU debug flags. 3169 */ 3170 struct { 3171 /** 3172 * Update dirty rect in SW only. 3173 */ 3174 uint8_t update_dirty_rect_only : 1; 3175 /** 3176 * Reset the cursor/plane state before processing the call. 3177 */ 3178 uint8_t reset_state : 1; 3179 } bitfields; 3180 3181 /** 3182 * Union for debug flags. 3183 */ 3184 uint32_t u32All; 3185 }; 3186 3187 /** 3188 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3189 * This triggers a selective update for PSR SU. 3190 */ 3191 struct dmub_cmd_update_dirty_rect_data { 3192 /** 3193 * Dirty rects from OS. 3194 */ 3195 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3196 /** 3197 * PSR SU debug flags. 3198 */ 3199 union dmub_psr_su_debug_flags debug_flags; 3200 /** 3201 * OTG HW instance. 3202 */ 3203 uint8_t pipe_idx; 3204 /** 3205 * Number of dirty rects. 3206 */ 3207 uint8_t dirty_rect_count; 3208 /** 3209 * PSR control version. 3210 */ 3211 uint8_t cmd_version; 3212 /** 3213 * Panel Instance. 3214 * Panel instance to identify which psr_state to use 3215 * Currently the support is only for 0 or 1 3216 */ 3217 uint8_t panel_inst; 3218 }; 3219 3220 /** 3221 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3222 */ 3223 struct dmub_rb_cmd_update_dirty_rect { 3224 /** 3225 * Command header. 3226 */ 3227 struct dmub_cmd_header header; 3228 /** 3229 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3230 */ 3231 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3232 }; 3233 3234 /** 3235 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3236 */ 3237 union dmub_reg_cursor_control_cfg { 3238 struct { 3239 uint32_t cur_enable: 1; 3240 uint32_t reser0: 3; 3241 uint32_t cur_2x_magnify: 1; 3242 uint32_t reser1: 3; 3243 uint32_t mode: 3; 3244 uint32_t reser2: 5; 3245 uint32_t pitch: 2; 3246 uint32_t reser3: 6; 3247 uint32_t line_per_chunk: 5; 3248 uint32_t reser4: 3; 3249 } bits; 3250 uint32_t raw; 3251 }; 3252 struct dmub_cursor_position_cache_hubp { 3253 union dmub_reg_cursor_control_cfg cur_ctl; 3254 union dmub_reg_position_cfg { 3255 struct { 3256 uint32_t cur_x_pos: 16; 3257 uint32_t cur_y_pos: 16; 3258 } bits; 3259 uint32_t raw; 3260 } position; 3261 union dmub_reg_hot_spot_cfg { 3262 struct { 3263 uint32_t hot_x: 16; 3264 uint32_t hot_y: 16; 3265 } bits; 3266 uint32_t raw; 3267 } hot_spot; 3268 union dmub_reg_dst_offset_cfg { 3269 struct { 3270 uint32_t dst_x_offset: 13; 3271 uint32_t reserved: 19; 3272 } bits; 3273 uint32_t raw; 3274 } dst_offset; 3275 }; 3276 3277 union dmub_reg_cur0_control_cfg { 3278 struct { 3279 uint32_t cur0_enable: 1; 3280 uint32_t expansion_mode: 1; 3281 uint32_t reser0: 1; 3282 uint32_t cur0_rom_en: 1; 3283 uint32_t mode: 3; 3284 uint32_t reserved: 25; 3285 } bits; 3286 uint32_t raw; 3287 }; 3288 struct dmub_cursor_position_cache_dpp { 3289 union dmub_reg_cur0_control_cfg cur0_ctl; 3290 }; 3291 struct dmub_cursor_position_cfg { 3292 struct dmub_cursor_position_cache_hubp pHubp; 3293 struct dmub_cursor_position_cache_dpp pDpp; 3294 uint8_t pipe_idx; 3295 /* 3296 * Padding is required. To be 4 Bytes Aligned. 3297 */ 3298 uint8_t padding[3]; 3299 }; 3300 3301 struct dmub_cursor_attribute_cache_hubp { 3302 uint32_t SURFACE_ADDR_HIGH; 3303 uint32_t SURFACE_ADDR; 3304 union dmub_reg_cursor_control_cfg cur_ctl; 3305 union dmub_reg_cursor_size_cfg { 3306 struct { 3307 uint32_t width: 16; 3308 uint32_t height: 16; 3309 } bits; 3310 uint32_t raw; 3311 } size; 3312 union dmub_reg_cursor_settings_cfg { 3313 struct { 3314 uint32_t dst_y_offset: 8; 3315 uint32_t chunk_hdl_adjust: 2; 3316 uint32_t reserved: 22; 3317 } bits; 3318 uint32_t raw; 3319 } settings; 3320 }; 3321 struct dmub_cursor_attribute_cache_dpp { 3322 union dmub_reg_cur0_control_cfg cur0_ctl; 3323 }; 3324 struct dmub_cursor_attributes_cfg { 3325 struct dmub_cursor_attribute_cache_hubp aHubp; 3326 struct dmub_cursor_attribute_cache_dpp aDpp; 3327 }; 3328 3329 struct dmub_cmd_update_cursor_payload0 { 3330 /** 3331 * Cursor dirty rects. 3332 */ 3333 struct dmub_rect cursor_rect; 3334 /** 3335 * PSR SU debug flags. 3336 */ 3337 union dmub_psr_su_debug_flags debug_flags; 3338 /** 3339 * Cursor enable/disable. 3340 */ 3341 uint8_t enable; 3342 /** 3343 * OTG HW instance. 3344 */ 3345 uint8_t pipe_idx; 3346 /** 3347 * PSR control version. 3348 */ 3349 uint8_t cmd_version; 3350 /** 3351 * Panel Instance. 3352 * Panel instance to identify which psr_state to use 3353 * Currently the support is only for 0 or 1 3354 */ 3355 uint8_t panel_inst; 3356 /** 3357 * Cursor Position Register. 3358 * Registers contains Hubp & Dpp modules 3359 */ 3360 struct dmub_cursor_position_cfg position_cfg; 3361 }; 3362 3363 struct dmub_cmd_update_cursor_payload1 { 3364 struct dmub_cursor_attributes_cfg attribute_cfg; 3365 }; 3366 3367 union dmub_cmd_update_cursor_info_data { 3368 struct dmub_cmd_update_cursor_payload0 payload0; 3369 struct dmub_cmd_update_cursor_payload1 payload1; 3370 }; 3371 /** 3372 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3373 */ 3374 struct dmub_rb_cmd_update_cursor_info { 3375 /** 3376 * Command header. 3377 */ 3378 struct dmub_cmd_header header; 3379 /** 3380 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3381 */ 3382 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3383 }; 3384 3385 /** 3386 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3387 */ 3388 struct dmub_cmd_psr_set_vtotal_data { 3389 /** 3390 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3391 */ 3392 uint16_t psr_vtotal_idle; 3393 /** 3394 * PSR control version. 3395 */ 3396 uint8_t cmd_version; 3397 /** 3398 * Panel Instance. 3399 * Panel instance to identify which psr_state to use 3400 * Currently the support is only for 0 or 1 3401 */ 3402 uint8_t panel_inst; 3403 /* 3404 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3405 */ 3406 uint16_t psr_vtotal_su; 3407 /** 3408 * Explicit padding to 4 byte boundary. 3409 */ 3410 uint8_t pad2[2]; 3411 }; 3412 3413 /** 3414 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3415 */ 3416 struct dmub_rb_cmd_psr_set_vtotal { 3417 /** 3418 * Command header. 3419 */ 3420 struct dmub_cmd_header header; 3421 /** 3422 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3423 */ 3424 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3425 }; 3426 3427 /** 3428 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3429 */ 3430 struct dmub_cmd_psr_set_power_opt_data { 3431 /** 3432 * PSR control version. 3433 */ 3434 uint8_t cmd_version; 3435 /** 3436 * Panel Instance. 3437 * Panel instance to identify which psr_state to use 3438 * Currently the support is only for 0 or 1 3439 */ 3440 uint8_t panel_inst; 3441 /** 3442 * Explicit padding to 4 byte boundary. 3443 */ 3444 uint8_t pad[2]; 3445 /** 3446 * PSR power option 3447 */ 3448 uint32_t power_opt; 3449 }; 3450 3451 /** 3452 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3453 */ 3454 struct dmub_rb_cmd_psr_set_power_opt { 3455 /** 3456 * Command header. 3457 */ 3458 struct dmub_cmd_header header; 3459 /** 3460 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3461 */ 3462 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3463 }; 3464 3465 /** 3466 * Definition of Replay Residency GPINT command. 3467 * Bit[0] - Residency mode for Revision 0 3468 * Bit[1] - Enable/Disable state 3469 * Bit[2-3] - Revision number 3470 * Bit[4-7] - Residency mode for Revision 1 3471 * Bit[8] - Panel instance 3472 * Bit[9-15] - Reserved 3473 */ 3474 3475 enum pr_residency_mode { 3476 PR_RESIDENCY_MODE_PHY = 0x0, 3477 PR_RESIDENCY_MODE_ALPM, 3478 PR_RESIDENCY_MODE_IPS2, 3479 PR_RESIDENCY_MODE_FRAME_CNT, 3480 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3481 }; 3482 3483 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3484 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3485 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3486 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3487 3488 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3489 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3490 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3491 3492 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3493 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3494 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3495 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3496 3497 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3498 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3499 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3500 3501 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3502 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3503 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3504 3505 /** 3506 * Definition of a replay_state. 3507 */ 3508 enum replay_state { 3509 REPLAY_STATE_0 = 0x0, 3510 REPLAY_STATE_1 = 0x10, 3511 REPLAY_STATE_1A = 0x11, 3512 REPLAY_STATE_2 = 0x20, 3513 REPLAY_STATE_2A = 0x21, 3514 REPLAY_STATE_3 = 0x30, 3515 REPLAY_STATE_3INIT = 0x31, 3516 REPLAY_STATE_4 = 0x40, 3517 REPLAY_STATE_4A = 0x41, 3518 REPLAY_STATE_4B = 0x42, 3519 REPLAY_STATE_4C = 0x43, 3520 REPLAY_STATE_4D = 0x44, 3521 REPLAY_STATE_4E = 0x45, 3522 REPLAY_STATE_4B_LOCKED = 0x4A, 3523 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3524 REPLAY_STATE_5 = 0x50, 3525 REPLAY_STATE_5A = 0x51, 3526 REPLAY_STATE_5B = 0x52, 3527 REPLAY_STATE_5A_LOCKED = 0x5A, 3528 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3529 REPLAY_STATE_6 = 0x60, 3530 REPLAY_STATE_6A = 0x61, 3531 REPLAY_STATE_6B = 0x62, 3532 REPLAY_STATE_INVALID = 0xFF, 3533 }; 3534 3535 /** 3536 * Replay command sub-types. 3537 */ 3538 enum dmub_cmd_replay_type { 3539 /** 3540 * Copy driver-calculated parameters to REPLAY state. 3541 */ 3542 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3543 /** 3544 * Enable REPLAY. 3545 */ 3546 DMUB_CMD__REPLAY_ENABLE = 1, 3547 /** 3548 * Set Replay power option. 3549 */ 3550 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3551 /** 3552 * Set coasting vtotal. 3553 */ 3554 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3555 /** 3556 * Set power opt and coasting vtotal. 3557 */ 3558 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3559 /** 3560 * Set disabled iiming sync. 3561 */ 3562 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3563 /** 3564 * Set Residency Frameupdate Timer. 3565 */ 3566 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3567 /** 3568 * Set pseudo vtotal 3569 */ 3570 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3571 /** 3572 * Set adaptive sync sdp enabled 3573 */ 3574 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3575 /** 3576 * Set Replay General command. 3577 */ 3578 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3579 }; 3580 3581 /** 3582 * Replay general command sub-types. 3583 */ 3584 enum dmub_cmd_replay_general_subtype { 3585 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3586 /** 3587 * TODO: For backward compatible, allow new command only. 3588 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3589 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3590 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3591 */ 3592 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3593 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3594 }; 3595 3596 /** 3597 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3598 */ 3599 struct dmub_cmd_replay_copy_settings_data { 3600 /** 3601 * Flags that can be set by driver to change some replay behaviour. 3602 */ 3603 union replay_debug_flags debug; 3604 3605 /** 3606 * @flags: Flags used to determine feature functionality. 3607 */ 3608 union replay_hw_flags flags; 3609 3610 /** 3611 * DPP HW instance. 3612 */ 3613 uint8_t dpp_inst; 3614 /** 3615 * OTG HW instance. 3616 */ 3617 uint8_t otg_inst; 3618 /** 3619 * DIG FE HW instance. 3620 */ 3621 uint8_t digfe_inst; 3622 /** 3623 * DIG BE HW instance. 3624 */ 3625 uint8_t digbe_inst; 3626 /** 3627 * AUX HW instance. 3628 */ 3629 uint8_t aux_inst; 3630 /** 3631 * Panel Instance. 3632 * Panel isntance to identify which psr_state to use 3633 * Currently the support is only for 0 or 1 3634 */ 3635 uint8_t panel_inst; 3636 /** 3637 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3638 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3639 */ 3640 uint8_t pixel_deviation_per_line; 3641 /** 3642 * @max_deviation_line: The max number of deviation line that can keep the timing 3643 * synchronized between the Source and Sink during Replay normal sleep mode. 3644 */ 3645 uint8_t max_deviation_line; 3646 /** 3647 * Length of each horizontal line in ns. 3648 */ 3649 uint32_t line_time_in_ns; 3650 /** 3651 * PHY instance. 3652 */ 3653 uint8_t dpphy_inst; 3654 /** 3655 * Determines if SMU optimzations are enabled/disabled. 3656 */ 3657 uint8_t smu_optimizations_en; 3658 /** 3659 * Determines if timing sync are enabled/disabled. 3660 */ 3661 uint8_t replay_timing_sync_supported; 3662 /* 3663 * Use FSM state for Replay power up/down 3664 */ 3665 uint8_t use_phy_fsm; 3666 }; 3667 3668 /** 3669 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3670 */ 3671 struct dmub_rb_cmd_replay_copy_settings { 3672 /** 3673 * Command header. 3674 */ 3675 struct dmub_cmd_header header; 3676 /** 3677 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3678 */ 3679 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3680 }; 3681 3682 /** 3683 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3684 */ 3685 enum replay_enable { 3686 /** 3687 * Disable REPLAY. 3688 */ 3689 REPLAY_DISABLE = 0, 3690 /** 3691 * Enable REPLAY. 3692 */ 3693 REPLAY_ENABLE = 1, 3694 }; 3695 3696 /** 3697 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3698 */ 3699 struct dmub_rb_cmd_replay_enable_data { 3700 /** 3701 * Replay enable or disable. 3702 */ 3703 uint8_t enable; 3704 /** 3705 * Panel Instance. 3706 * Panel isntance to identify which replay_state to use 3707 * Currently the support is only for 0 or 1 3708 */ 3709 uint8_t panel_inst; 3710 /** 3711 * Phy state to enter. 3712 * Values to use are defined in dmub_phy_fsm_state 3713 */ 3714 uint8_t phy_fsm_state; 3715 /** 3716 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3717 * Set this using enum phy_link_rate. 3718 * This does not support HDMI/DP2 for now. 3719 */ 3720 uint8_t phy_rate; 3721 }; 3722 3723 /** 3724 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3725 * Replay enable/disable is controlled using action in data. 3726 */ 3727 struct dmub_rb_cmd_replay_enable { 3728 /** 3729 * Command header. 3730 */ 3731 struct dmub_cmd_header header; 3732 3733 struct dmub_rb_cmd_replay_enable_data data; 3734 }; 3735 3736 /** 3737 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3738 */ 3739 struct dmub_cmd_replay_set_power_opt_data { 3740 /** 3741 * Panel Instance. 3742 * Panel isntance to identify which replay_state to use 3743 * Currently the support is only for 0 or 1 3744 */ 3745 uint8_t panel_inst; 3746 /** 3747 * Explicit padding to 4 byte boundary. 3748 */ 3749 uint8_t pad[3]; 3750 /** 3751 * REPLAY power option 3752 */ 3753 uint32_t power_opt; 3754 }; 3755 3756 /** 3757 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3758 */ 3759 struct dmub_cmd_replay_set_timing_sync_data { 3760 /** 3761 * Panel Instance. 3762 * Panel isntance to identify which replay_state to use 3763 * Currently the support is only for 0 or 1 3764 */ 3765 uint8_t panel_inst; 3766 /** 3767 * REPLAY set_timing_sync 3768 */ 3769 uint8_t timing_sync_supported; 3770 /** 3771 * Explicit padding to 4 byte boundary. 3772 */ 3773 uint8_t pad[2]; 3774 }; 3775 3776 /** 3777 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3778 */ 3779 struct dmub_cmd_replay_set_pseudo_vtotal { 3780 /** 3781 * Panel Instance. 3782 * Panel isntance to identify which replay_state to use 3783 * Currently the support is only for 0 or 1 3784 */ 3785 uint8_t panel_inst; 3786 /** 3787 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3788 */ 3789 uint16_t vtotal; 3790 /** 3791 * Explicit padding to 4 byte boundary. 3792 */ 3793 uint8_t pad; 3794 }; 3795 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3796 /** 3797 * Panel Instance. 3798 * Panel isntance to identify which replay_state to use 3799 * Currently the support is only for 0 or 1 3800 */ 3801 uint8_t panel_inst; 3802 /** 3803 * enabled: set adaptive sync sdp enabled 3804 */ 3805 uint8_t force_disabled; 3806 3807 uint8_t pad[2]; 3808 }; 3809 struct dmub_cmd_replay_set_general_cmd_data { 3810 /** 3811 * Panel Instance. 3812 * Panel isntance to identify which replay_state to use 3813 * Currently the support is only for 0 or 1 3814 */ 3815 uint8_t panel_inst; 3816 /** 3817 * subtype: replay general cmd sub type 3818 */ 3819 uint8_t subtype; 3820 3821 uint8_t pad[2]; 3822 /** 3823 * config data with param1 and param2 3824 */ 3825 uint32_t param1; 3826 3827 uint32_t param2; 3828 }; 3829 3830 /** 3831 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3832 */ 3833 struct dmub_rb_cmd_replay_set_power_opt { 3834 /** 3835 * Command header. 3836 */ 3837 struct dmub_cmd_header header; 3838 /** 3839 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3840 */ 3841 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3842 }; 3843 3844 /** 3845 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3846 */ 3847 struct dmub_cmd_replay_set_coasting_vtotal_data { 3848 /** 3849 * 16-bit value dicated by driver that indicates the coasting vtotal. 3850 */ 3851 uint16_t coasting_vtotal; 3852 /** 3853 * REPLAY control version. 3854 */ 3855 uint8_t cmd_version; 3856 /** 3857 * Panel Instance. 3858 * Panel isntance to identify which replay_state to use 3859 * Currently the support is only for 0 or 1 3860 */ 3861 uint8_t panel_inst; 3862 /** 3863 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3864 */ 3865 uint16_t coasting_vtotal_high; 3866 /** 3867 * Explicit padding to 4 byte boundary. 3868 */ 3869 uint8_t pad[2]; 3870 }; 3871 3872 /** 3873 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3874 */ 3875 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3876 /** 3877 * Command header. 3878 */ 3879 struct dmub_cmd_header header; 3880 /** 3881 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3882 */ 3883 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3884 }; 3885 3886 /** 3887 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3888 */ 3889 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3890 /** 3891 * Command header. 3892 */ 3893 struct dmub_cmd_header header; 3894 /** 3895 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3896 */ 3897 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3898 /** 3899 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3900 */ 3901 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3902 }; 3903 3904 /** 3905 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3906 */ 3907 struct dmub_rb_cmd_replay_set_timing_sync { 3908 /** 3909 * Command header. 3910 */ 3911 struct dmub_cmd_header header; 3912 /** 3913 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3914 */ 3915 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3916 }; 3917 3918 /** 3919 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3920 */ 3921 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3922 /** 3923 * Command header. 3924 */ 3925 struct dmub_cmd_header header; 3926 /** 3927 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3928 */ 3929 struct dmub_cmd_replay_set_pseudo_vtotal data; 3930 }; 3931 3932 /** 3933 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3934 */ 3935 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3936 /** 3937 * Command header. 3938 */ 3939 struct dmub_cmd_header header; 3940 /** 3941 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3942 */ 3943 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3944 }; 3945 3946 /** 3947 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3948 */ 3949 struct dmub_rb_cmd_replay_set_general_cmd { 3950 /** 3951 * Command header. 3952 */ 3953 struct dmub_cmd_header header; 3954 /** 3955 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3956 */ 3957 struct dmub_cmd_replay_set_general_cmd_data data; 3958 }; 3959 3960 /** 3961 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3962 */ 3963 struct dmub_cmd_replay_frameupdate_timer_data { 3964 /** 3965 * Panel Instance. 3966 * Panel isntance to identify which replay_state to use 3967 * Currently the support is only for 0 or 1 3968 */ 3969 uint8_t panel_inst; 3970 /** 3971 * Replay Frameupdate Timer Enable or not 3972 */ 3973 uint8_t enable; 3974 /** 3975 * REPLAY force reflash frame update number 3976 */ 3977 uint16_t frameupdate_count; 3978 }; 3979 /** 3980 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3981 */ 3982 struct dmub_rb_cmd_replay_set_frameupdate_timer { 3983 /** 3984 * Command header. 3985 */ 3986 struct dmub_cmd_header header; 3987 /** 3988 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3989 */ 3990 struct dmub_cmd_replay_frameupdate_timer_data data; 3991 }; 3992 3993 /** 3994 * Definition union of replay command set 3995 */ 3996 union dmub_replay_cmd_set { 3997 /** 3998 * Panel Instance. 3999 * Panel isntance to identify which replay_state to use 4000 * Currently the support is only for 0 or 1 4001 */ 4002 uint8_t panel_inst; 4003 /** 4004 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4005 */ 4006 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4007 /** 4008 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4009 */ 4010 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4011 /** 4012 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4013 */ 4014 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4015 /** 4016 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4017 */ 4018 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4019 /** 4020 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4021 */ 4022 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4023 }; 4024 4025 /** 4026 * Set of HW components that can be locked. 4027 * 4028 * Note: If updating with more HW components, fields 4029 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4030 */ 4031 union dmub_hw_lock_flags { 4032 /** 4033 * Set of HW components that can be locked. 4034 */ 4035 struct { 4036 /** 4037 * Lock/unlock OTG master update lock. 4038 */ 4039 uint8_t lock_pipe : 1; 4040 /** 4041 * Lock/unlock cursor. 4042 */ 4043 uint8_t lock_cursor : 1; 4044 /** 4045 * Lock/unlock global update lock. 4046 */ 4047 uint8_t lock_dig : 1; 4048 /** 4049 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4050 */ 4051 uint8_t triple_buffer_lock : 1; 4052 } bits; 4053 4054 /** 4055 * Union for HW Lock flags. 4056 */ 4057 uint8_t u8All; 4058 }; 4059 4060 /** 4061 * Instances of HW to be locked. 4062 * 4063 * Note: If updating with more HW components, fields 4064 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4065 */ 4066 struct dmub_hw_lock_inst_flags { 4067 /** 4068 * OTG HW instance for OTG master update lock. 4069 */ 4070 uint8_t otg_inst; 4071 /** 4072 * OPP instance for cursor lock. 4073 */ 4074 uint8_t opp_inst; 4075 /** 4076 * OTG HW instance for global update lock. 4077 * TODO: Remove, and re-use otg_inst. 4078 */ 4079 uint8_t dig_inst; 4080 /** 4081 * Explicit pad to 4 byte boundary. 4082 */ 4083 uint8_t pad; 4084 }; 4085 4086 /** 4087 * Clients that can acquire the HW Lock Manager. 4088 * 4089 * Note: If updating with more clients, fields in 4090 * dmub_inbox0_cmd_lock_hw must be updated to match. 4091 */ 4092 enum hw_lock_client { 4093 /** 4094 * Driver is the client of HW Lock Manager. 4095 */ 4096 HW_LOCK_CLIENT_DRIVER = 0, 4097 /** 4098 * PSR SU is the client of HW Lock Manager. 4099 */ 4100 HW_LOCK_CLIENT_PSR_SU = 1, 4101 HW_LOCK_CLIENT_SUBVP = 3, 4102 /** 4103 * Replay is the client of HW Lock Manager. 4104 */ 4105 HW_LOCK_CLIENT_REPLAY = 4, 4106 HW_LOCK_CLIENT_FAMS2 = 5, 4107 /** 4108 * Invalid client. 4109 */ 4110 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4111 }; 4112 4113 /** 4114 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4115 */ 4116 struct dmub_cmd_lock_hw_data { 4117 /** 4118 * Specifies the client accessing HW Lock Manager. 4119 */ 4120 enum hw_lock_client client; 4121 /** 4122 * HW instances to be locked. 4123 */ 4124 struct dmub_hw_lock_inst_flags inst_flags; 4125 /** 4126 * Which components to be locked. 4127 */ 4128 union dmub_hw_lock_flags hw_locks; 4129 /** 4130 * Specifies lock/unlock. 4131 */ 4132 uint8_t lock; 4133 /** 4134 * HW can be unlocked separately from releasing the HW Lock Mgr. 4135 * This flag is set if the client wishes to release the object. 4136 */ 4137 uint8_t should_release; 4138 /** 4139 * Explicit padding to 4 byte boundary. 4140 */ 4141 uint8_t pad; 4142 }; 4143 4144 /** 4145 * Definition of a DMUB_CMD__HW_LOCK command. 4146 * Command is used by driver and FW. 4147 */ 4148 struct dmub_rb_cmd_lock_hw { 4149 /** 4150 * Command header. 4151 */ 4152 struct dmub_cmd_header header; 4153 /** 4154 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4155 */ 4156 struct dmub_cmd_lock_hw_data lock_hw_data; 4157 }; 4158 4159 /** 4160 * ABM command sub-types. 4161 */ 4162 enum dmub_cmd_abm_type { 4163 /** 4164 * Initialize parameters for ABM algorithm. 4165 * Data is passed through an indirect buffer. 4166 */ 4167 DMUB_CMD__ABM_INIT_CONFIG = 0, 4168 /** 4169 * Set OTG and panel HW instance. 4170 */ 4171 DMUB_CMD__ABM_SET_PIPE = 1, 4172 /** 4173 * Set user requested backklight level. 4174 */ 4175 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4176 /** 4177 * Set ABM operating/aggression level. 4178 */ 4179 DMUB_CMD__ABM_SET_LEVEL = 3, 4180 /** 4181 * Set ambient light level. 4182 */ 4183 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4184 /** 4185 * Enable/disable fractional duty cycle for backlight PWM. 4186 */ 4187 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4188 4189 /** 4190 * unregister vertical interrupt after steady state is reached 4191 */ 4192 DMUB_CMD__ABM_PAUSE = 6, 4193 4194 /** 4195 * Save and Restore ABM state. On save we save parameters, and 4196 * on restore we update state with passed in data. 4197 */ 4198 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4199 4200 /** 4201 * Query ABM caps. 4202 */ 4203 DMUB_CMD__ABM_QUERY_CAPS = 8, 4204 4205 /** 4206 * Set ABM Events 4207 */ 4208 DMUB_CMD__ABM_SET_EVENT = 9, 4209 4210 /** 4211 * Get the current ACE curve. 4212 */ 4213 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4214 }; 4215 4216 struct abm_ace_curve { 4217 /** 4218 * @offsets: ACE curve offsets. 4219 */ 4220 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4221 4222 /** 4223 * @thresholds: ACE curve thresholds. 4224 */ 4225 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4226 4227 /** 4228 * @slopes: ACE curve slopes. 4229 */ 4230 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4231 }; 4232 4233 struct fixed_pt_format { 4234 /** 4235 * @sign_bit: Indicates whether one bit is reserved for the sign. 4236 */ 4237 bool sign_bit; 4238 4239 /** 4240 * @num_int_bits: Number of bits used for integer part. 4241 */ 4242 uint8_t num_int_bits; 4243 4244 /** 4245 * @num_frac_bits: Number of bits used for fractional part. 4246 */ 4247 uint8_t num_frac_bits; 4248 4249 /** 4250 * @pad: Explicit padding to 4 byte boundary. 4251 */ 4252 uint8_t pad; 4253 }; 4254 4255 struct abm_caps { 4256 /** 4257 * @num_hg_bins: Number of histogram bins. 4258 */ 4259 uint8_t num_hg_bins; 4260 4261 /** 4262 * @num_ace_segments: Number of ACE curve segments. 4263 */ 4264 uint8_t num_ace_segments; 4265 4266 /** 4267 * @pad: Explicit padding to 4 byte boundary. 4268 */ 4269 uint8_t pad[2]; 4270 4271 /** 4272 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4273 */ 4274 struct fixed_pt_format ace_thresholds_format; 4275 4276 /** 4277 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4278 */ 4279 struct fixed_pt_format ace_offsets_format; 4280 4281 /** 4282 * @ace_slopes_format: Format of the ACE slopes. 4283 */ 4284 struct fixed_pt_format ace_slopes_format; 4285 }; 4286 4287 /** 4288 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4289 * Requirements: 4290 * - Padded explicitly to 32-bit boundary. 4291 * - Must ensure this structure matches the one on driver-side, 4292 * otherwise it won't be aligned. 4293 */ 4294 struct abm_config_table { 4295 /** 4296 * Gamma curve thresholds, used for crgb conversion. 4297 */ 4298 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4299 /** 4300 * Gamma curve offsets, used for crgb conversion. 4301 */ 4302 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4303 /** 4304 * Gamma curve slopes, used for crgb conversion. 4305 */ 4306 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4307 /** 4308 * Custom backlight curve thresholds. 4309 */ 4310 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4311 /** 4312 * Custom backlight curve offsets. 4313 */ 4314 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4315 /** 4316 * Ambient light thresholds. 4317 */ 4318 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4319 /** 4320 * Minimum programmable backlight. 4321 */ 4322 uint16_t min_abm_backlight; // 122B 4323 /** 4324 * Minimum reduction values. 4325 */ 4326 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4327 /** 4328 * Maximum reduction values. 4329 */ 4330 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4331 /** 4332 * Bright positive gain. 4333 */ 4334 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4335 /** 4336 * Dark negative gain. 4337 */ 4338 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4339 /** 4340 * Hybrid factor. 4341 */ 4342 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4343 /** 4344 * Contrast factor. 4345 */ 4346 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4347 /** 4348 * Deviation gain. 4349 */ 4350 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4351 /** 4352 * Minimum knee. 4353 */ 4354 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4355 /** 4356 * Maximum knee. 4357 */ 4358 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4359 /** 4360 * Unused. 4361 */ 4362 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4363 /** 4364 * Explicit padding to 4 byte boundary. 4365 */ 4366 uint8_t pad3[3]; // 229B 4367 /** 4368 * Backlight ramp reduction. 4369 */ 4370 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4371 /** 4372 * Backlight ramp start. 4373 */ 4374 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4375 }; 4376 4377 /** 4378 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4379 */ 4380 struct dmub_cmd_abm_set_pipe_data { 4381 /** 4382 * OTG HW instance. 4383 */ 4384 uint8_t otg_inst; 4385 4386 /** 4387 * Panel Control HW instance. 4388 */ 4389 uint8_t panel_inst; 4390 4391 /** 4392 * Controls how ABM will interpret a set pipe or set level command. 4393 */ 4394 uint8_t set_pipe_option; 4395 4396 /** 4397 * Unused. 4398 * TODO: Remove. 4399 */ 4400 uint8_t ramping_boundary; 4401 4402 /** 4403 * PwrSeq HW Instance. 4404 */ 4405 uint8_t pwrseq_inst; 4406 4407 /** 4408 * Explicit padding to 4 byte boundary. 4409 */ 4410 uint8_t pad[3]; 4411 }; 4412 4413 /** 4414 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4415 */ 4416 struct dmub_rb_cmd_abm_set_pipe { 4417 /** 4418 * Command header. 4419 */ 4420 struct dmub_cmd_header header; 4421 4422 /** 4423 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4424 */ 4425 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4426 }; 4427 4428 /** 4429 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4430 */ 4431 struct dmub_cmd_abm_set_backlight_data { 4432 /** 4433 * Number of frames to ramp to backlight user level. 4434 */ 4435 uint32_t frame_ramp; 4436 4437 /** 4438 * Requested backlight level from user. 4439 */ 4440 uint32_t backlight_user_level; 4441 4442 /** 4443 * ABM control version. 4444 */ 4445 uint8_t version; 4446 4447 /** 4448 * Panel Control HW instance mask. 4449 * Bit 0 is Panel Control HW instance 0. 4450 * Bit 1 is Panel Control HW instance 1. 4451 */ 4452 uint8_t panel_mask; 4453 4454 /** 4455 * Backlight control type. 4456 * Value 0 is PWM backlight control. 4457 * Value 1 is VAUX backlight control. 4458 * Value 2 is AMD DPCD AUX backlight control. 4459 */ 4460 uint8_t backlight_control_type; 4461 4462 /** 4463 * Explicit padding to 4 byte boundary. 4464 */ 4465 uint8_t pad[1]; 4466 4467 /** 4468 * Minimum luminance in nits. 4469 */ 4470 uint32_t min_luminance; 4471 4472 /** 4473 * Maximum luminance in nits. 4474 */ 4475 uint32_t max_luminance; 4476 4477 /** 4478 * Minimum backlight in pwm. 4479 */ 4480 uint32_t min_backlight_pwm; 4481 4482 /** 4483 * Maximum backlight in pwm. 4484 */ 4485 uint32_t max_backlight_pwm; 4486 }; 4487 4488 /** 4489 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4490 */ 4491 struct dmub_rb_cmd_abm_set_backlight { 4492 /** 4493 * Command header. 4494 */ 4495 struct dmub_cmd_header header; 4496 4497 /** 4498 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4499 */ 4500 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4501 }; 4502 4503 /** 4504 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4505 */ 4506 struct dmub_cmd_abm_set_level_data { 4507 /** 4508 * Set current ABM operating/aggression level. 4509 */ 4510 uint32_t level; 4511 4512 /** 4513 * ABM control version. 4514 */ 4515 uint8_t version; 4516 4517 /** 4518 * Panel Control HW instance mask. 4519 * Bit 0 is Panel Control HW instance 0. 4520 * Bit 1 is Panel Control HW instance 1. 4521 */ 4522 uint8_t panel_mask; 4523 4524 /** 4525 * Explicit padding to 4 byte boundary. 4526 */ 4527 uint8_t pad[2]; 4528 }; 4529 4530 /** 4531 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4532 */ 4533 struct dmub_rb_cmd_abm_set_level { 4534 /** 4535 * Command header. 4536 */ 4537 struct dmub_cmd_header header; 4538 4539 /** 4540 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4541 */ 4542 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4543 }; 4544 4545 /** 4546 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4547 */ 4548 struct dmub_cmd_abm_set_ambient_level_data { 4549 /** 4550 * Ambient light sensor reading from OS. 4551 */ 4552 uint32_t ambient_lux; 4553 4554 /** 4555 * ABM control version. 4556 */ 4557 uint8_t version; 4558 4559 /** 4560 * Panel Control HW instance mask. 4561 * Bit 0 is Panel Control HW instance 0. 4562 * Bit 1 is Panel Control HW instance 1. 4563 */ 4564 uint8_t panel_mask; 4565 4566 /** 4567 * Explicit padding to 4 byte boundary. 4568 */ 4569 uint8_t pad[2]; 4570 }; 4571 4572 /** 4573 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4574 */ 4575 struct dmub_rb_cmd_abm_set_ambient_level { 4576 /** 4577 * Command header. 4578 */ 4579 struct dmub_cmd_header header; 4580 4581 /** 4582 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4583 */ 4584 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4585 }; 4586 4587 /** 4588 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4589 */ 4590 struct dmub_cmd_abm_set_pwm_frac_data { 4591 /** 4592 * Enable/disable fractional duty cycle for backlight PWM. 4593 * TODO: Convert to uint8_t. 4594 */ 4595 uint32_t fractional_pwm; 4596 4597 /** 4598 * ABM control version. 4599 */ 4600 uint8_t version; 4601 4602 /** 4603 * Panel Control HW instance mask. 4604 * Bit 0 is Panel Control HW instance 0. 4605 * Bit 1 is Panel Control HW instance 1. 4606 */ 4607 uint8_t panel_mask; 4608 4609 /** 4610 * Explicit padding to 4 byte boundary. 4611 */ 4612 uint8_t pad[2]; 4613 }; 4614 4615 /** 4616 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4617 */ 4618 struct dmub_rb_cmd_abm_set_pwm_frac { 4619 /** 4620 * Command header. 4621 */ 4622 struct dmub_cmd_header header; 4623 4624 /** 4625 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4626 */ 4627 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4628 }; 4629 4630 /** 4631 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4632 */ 4633 struct dmub_cmd_abm_init_config_data { 4634 /** 4635 * Location of indirect buffer used to pass init data to ABM. 4636 */ 4637 union dmub_addr src; 4638 4639 /** 4640 * Indirect buffer length. 4641 */ 4642 uint16_t bytes; 4643 4644 4645 /** 4646 * ABM control version. 4647 */ 4648 uint8_t version; 4649 4650 /** 4651 * Panel Control HW instance mask. 4652 * Bit 0 is Panel Control HW instance 0. 4653 * Bit 1 is Panel Control HW instance 1. 4654 */ 4655 uint8_t panel_mask; 4656 4657 /** 4658 * Explicit padding to 4 byte boundary. 4659 */ 4660 uint8_t pad[2]; 4661 }; 4662 4663 /** 4664 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4665 */ 4666 struct dmub_rb_cmd_abm_init_config { 4667 /** 4668 * Command header. 4669 */ 4670 struct dmub_cmd_header header; 4671 4672 /** 4673 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4674 */ 4675 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4676 }; 4677 4678 /** 4679 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4680 */ 4681 4682 struct dmub_cmd_abm_pause_data { 4683 4684 /** 4685 * Panel Control HW instance mask. 4686 * Bit 0 is Panel Control HW instance 0. 4687 * Bit 1 is Panel Control HW instance 1. 4688 */ 4689 uint8_t panel_mask; 4690 4691 /** 4692 * OTG hw instance 4693 */ 4694 uint8_t otg_inst; 4695 4696 /** 4697 * Enable or disable ABM pause 4698 */ 4699 uint8_t enable; 4700 4701 /** 4702 * Explicit padding to 4 byte boundary. 4703 */ 4704 uint8_t pad[1]; 4705 }; 4706 4707 /** 4708 * Definition of a DMUB_CMD__ABM_PAUSE command. 4709 */ 4710 struct dmub_rb_cmd_abm_pause { 4711 /** 4712 * Command header. 4713 */ 4714 struct dmub_cmd_header header; 4715 4716 /** 4717 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4718 */ 4719 struct dmub_cmd_abm_pause_data abm_pause_data; 4720 }; 4721 4722 /** 4723 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4724 */ 4725 struct dmub_cmd_abm_query_caps_in { 4726 /** 4727 * Panel instance. 4728 */ 4729 uint8_t panel_inst; 4730 4731 /** 4732 * Explicit padding to 4 byte boundary. 4733 */ 4734 uint8_t pad[3]; 4735 }; 4736 4737 /** 4738 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4739 */ 4740 struct dmub_cmd_abm_query_caps_out { 4741 /** 4742 * SW Algorithm caps. 4743 */ 4744 struct abm_caps sw_caps; 4745 4746 /** 4747 * ABM HW caps. 4748 */ 4749 struct abm_caps hw_caps; 4750 }; 4751 4752 /** 4753 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4754 */ 4755 struct dmub_rb_cmd_abm_query_caps { 4756 /** 4757 * Command header. 4758 */ 4759 struct dmub_cmd_header header; 4760 4761 /** 4762 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4763 */ 4764 union { 4765 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4766 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4767 } data; 4768 }; 4769 4770 /** 4771 * enum dmub_abm_ace_curve_type - ACE curve type. 4772 */ 4773 enum dmub_abm_ace_curve_type { 4774 /** 4775 * ACE curve as defined by the SW layer. 4776 */ 4777 ABM_ACE_CURVE_TYPE__SW = 0, 4778 /** 4779 * ACE curve as defined by the SW to HW translation interface layer. 4780 */ 4781 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4782 }; 4783 4784 /** 4785 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4786 */ 4787 struct dmub_rb_cmd_abm_get_ace_curve { 4788 /** 4789 * Command header. 4790 */ 4791 struct dmub_cmd_header header; 4792 4793 /** 4794 * Address where ACE curve should be copied. 4795 */ 4796 union dmub_addr dest; 4797 4798 /** 4799 * Type of ACE curve being queried. 4800 */ 4801 enum dmub_abm_ace_curve_type ace_type; 4802 4803 /** 4804 * Indirect buffer length. 4805 */ 4806 uint16_t bytes; 4807 4808 /** 4809 * eDP panel instance. 4810 */ 4811 uint8_t panel_inst; 4812 4813 /** 4814 * Explicit padding to 4 byte boundary. 4815 */ 4816 uint8_t pad; 4817 }; 4818 4819 /** 4820 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4821 */ 4822 struct dmub_rb_cmd_abm_save_restore { 4823 /** 4824 * Command header. 4825 */ 4826 struct dmub_cmd_header header; 4827 4828 /** 4829 * OTG hw instance 4830 */ 4831 uint8_t otg_inst; 4832 4833 /** 4834 * Enable or disable ABM pause 4835 */ 4836 uint8_t freeze; 4837 4838 /** 4839 * Explicit padding to 4 byte boundary. 4840 */ 4841 uint8_t debug; 4842 4843 /** 4844 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4845 */ 4846 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4847 }; 4848 4849 /** 4850 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4851 */ 4852 4853 struct dmub_cmd_abm_set_event_data { 4854 4855 /** 4856 * VB Scaling Init. Strength Mapping 4857 * Byte 0: 0~255 for VB level 0 4858 * Byte 1: 0~255 for VB level 1 4859 * Byte 2: 0~255 for VB level 2 4860 * Byte 3: 0~255 for VB level 3 4861 */ 4862 uint32_t vb_scaling_strength_mapping; 4863 /** 4864 * VariBright Scaling Enable 4865 */ 4866 uint8_t vb_scaling_enable; 4867 /** 4868 * Panel Control HW instance mask. 4869 * Bit 0 is Panel Control HW instance 0. 4870 * Bit 1 is Panel Control HW instance 1. 4871 */ 4872 uint8_t panel_mask; 4873 4874 /** 4875 * Explicit padding to 4 byte boundary. 4876 */ 4877 uint8_t pad[2]; 4878 }; 4879 4880 /** 4881 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 4882 */ 4883 struct dmub_rb_cmd_abm_set_event { 4884 /** 4885 * Command header. 4886 */ 4887 struct dmub_cmd_header header; 4888 4889 /** 4890 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4891 */ 4892 struct dmub_cmd_abm_set_event_data abm_set_event_data; 4893 }; 4894 4895 /** 4896 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4897 */ 4898 struct dmub_cmd_query_feature_caps_data { 4899 /** 4900 * DMUB feature capabilities. 4901 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4902 */ 4903 struct dmub_feature_caps feature_caps; 4904 }; 4905 4906 /** 4907 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4908 */ 4909 struct dmub_rb_cmd_query_feature_caps { 4910 /** 4911 * Command header. 4912 */ 4913 struct dmub_cmd_header header; 4914 /** 4915 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4916 */ 4917 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4918 }; 4919 4920 /** 4921 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4922 */ 4923 struct dmub_cmd_visual_confirm_color_data { 4924 /** 4925 * DMUB visual confirm color 4926 */ 4927 struct dmub_visual_confirm_color visual_confirm_color; 4928 }; 4929 4930 /** 4931 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4932 */ 4933 struct dmub_rb_cmd_get_visual_confirm_color { 4934 /** 4935 * Command header. 4936 */ 4937 struct dmub_cmd_header header; 4938 /** 4939 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4940 */ 4941 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4942 }; 4943 4944 /** 4945 * enum dmub_cmd_panel_cntl_type - Panel control command. 4946 */ 4947 enum dmub_cmd_panel_cntl_type { 4948 /** 4949 * Initializes embedded panel hardware blocks. 4950 */ 4951 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4952 /** 4953 * Queries backlight info for the embedded panel. 4954 */ 4955 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4956 /** 4957 * Sets the PWM Freq as per user's requirement. 4958 */ 4959 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 4960 }; 4961 4962 /** 4963 * struct dmub_cmd_panel_cntl_data - Panel control data. 4964 */ 4965 struct dmub_cmd_panel_cntl_data { 4966 uint32_t pwrseq_inst; /**< pwrseq instance */ 4967 uint32_t current_backlight; /* in/out */ 4968 uint32_t bl_pwm_cntl; /* in/out */ 4969 uint32_t bl_pwm_period_cntl; /* in/out */ 4970 uint32_t bl_pwm_ref_div1; /* in/out */ 4971 uint8_t is_backlight_on : 1; /* in/out */ 4972 uint8_t is_powered_on : 1; /* in/out */ 4973 uint8_t padding[3]; 4974 uint32_t bl_pwm_ref_div2; /* in/out */ 4975 uint8_t reserved[4]; 4976 }; 4977 4978 /** 4979 * struct dmub_rb_cmd_panel_cntl - Panel control command. 4980 */ 4981 struct dmub_rb_cmd_panel_cntl { 4982 struct dmub_cmd_header header; /**< header */ 4983 struct dmub_cmd_panel_cntl_data data; /**< payload */ 4984 }; 4985 4986 struct dmub_optc_state { 4987 uint32_t v_total_max; 4988 uint32_t v_total_min; 4989 uint32_t tg_inst; 4990 }; 4991 4992 struct dmub_rb_cmd_drr_update { 4993 struct dmub_cmd_header header; 4994 struct dmub_optc_state dmub_optc_state_req; 4995 }; 4996 4997 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 4998 uint32_t pix_clk_100hz; 4999 uint8_t max_ramp_step; 5000 uint8_t pipes; 5001 uint8_t min_refresh_in_hz; 5002 uint8_t pipe_count; 5003 uint8_t pipe_index[4]; 5004 }; 5005 5006 struct dmub_cmd_fw_assisted_mclk_switch_config { 5007 uint8_t fams_enabled; 5008 uint8_t visual_confirm_enabled; 5009 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5010 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5011 }; 5012 5013 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5014 struct dmub_cmd_header header; 5015 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5016 }; 5017 5018 /** 5019 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5020 */ 5021 struct dmub_cmd_lvtma_control_data { 5022 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5023 uint8_t bypass_panel_control_wait; 5024 uint8_t reserved_0[2]; /**< For future use */ 5025 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5026 uint8_t reserved_1[3]; /**< For future use */ 5027 }; 5028 5029 /** 5030 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5031 */ 5032 struct dmub_rb_cmd_lvtma_control { 5033 /** 5034 * Command header. 5035 */ 5036 struct dmub_cmd_header header; 5037 /** 5038 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5039 */ 5040 struct dmub_cmd_lvtma_control_data data; 5041 }; 5042 5043 /** 5044 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5045 */ 5046 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5047 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5048 uint8_t is_usb; /**< is phy is usb */ 5049 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5050 uint8_t is_dp4; /**< is dp in 4 lane */ 5051 }; 5052 5053 /** 5054 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5055 */ 5056 struct dmub_rb_cmd_transmitter_query_dp_alt { 5057 struct dmub_cmd_header header; /**< header */ 5058 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5059 }; 5060 5061 struct phy_test_mode { 5062 uint8_t mode; 5063 uint8_t pat0; 5064 uint8_t pad[2]; 5065 }; 5066 5067 /** 5068 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5069 */ 5070 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5071 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5072 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5073 uint8_t lane_num; /**< Number of lanes */ 5074 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5075 struct phy_test_mode test_mode; 5076 enum dmub_phy_fsm_state state; 5077 uint32_t status; 5078 uint8_t pad; 5079 }; 5080 5081 /** 5082 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5083 */ 5084 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5085 struct dmub_cmd_header header; /**< header */ 5086 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5087 }; 5088 5089 /** 5090 * Maximum number of bytes a chunk sent to DMUB for parsing 5091 */ 5092 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5093 5094 /** 5095 * Represent a chunk of CEA blocks sent to DMUB for parsing 5096 */ 5097 struct dmub_cmd_send_edid_cea { 5098 uint16_t offset; /**< offset into the CEA block */ 5099 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5100 uint16_t cea_total_length; /**< total length of the CEA block */ 5101 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5102 uint8_t pad[3]; /**< padding and for future expansion */ 5103 }; 5104 5105 /** 5106 * Result of VSDB parsing from CEA block 5107 */ 5108 struct dmub_cmd_edid_cea_amd_vsdb { 5109 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5110 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5111 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5112 uint16_t min_frame_rate; /**< Maximum frame rate */ 5113 uint16_t max_frame_rate; /**< Minimum frame rate */ 5114 }; 5115 5116 /** 5117 * Result of sending a CEA chunk 5118 */ 5119 struct dmub_cmd_edid_cea_ack { 5120 uint16_t offset; /**< offset of the chunk into the CEA block */ 5121 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5122 uint8_t pad; /**< padding and for future expansion */ 5123 }; 5124 5125 /** 5126 * Specify whether the result is an ACK/NACK or the parsing has finished 5127 */ 5128 enum dmub_cmd_edid_cea_reply_type { 5129 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5130 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5131 }; 5132 5133 /** 5134 * Definition of a DMUB_CMD__EDID_CEA command. 5135 */ 5136 struct dmub_rb_cmd_edid_cea { 5137 struct dmub_cmd_header header; /**< Command header */ 5138 union dmub_cmd_edid_cea_data { 5139 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5140 struct dmub_cmd_edid_cea_output { /**< output with results */ 5141 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5142 union { 5143 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5144 struct dmub_cmd_edid_cea_ack ack; 5145 }; 5146 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5147 } data; /**< Command data */ 5148 5149 }; 5150 5151 /** 5152 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5153 */ 5154 struct dmub_cmd_cable_id_input { 5155 uint8_t phy_inst; /**< phy inst for cable id data */ 5156 }; 5157 5158 /** 5159 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5160 */ 5161 struct dmub_cmd_cable_id_output { 5162 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5163 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5164 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5165 uint8_t RESERVED :2; /**< reserved means not defined */ 5166 }; 5167 5168 /** 5169 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5170 */ 5171 struct dmub_rb_cmd_get_usbc_cable_id { 5172 struct dmub_cmd_header header; /**< Command header */ 5173 /** 5174 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5175 */ 5176 union dmub_cmd_cable_id_data { 5177 struct dmub_cmd_cable_id_input input; /**< Input */ 5178 struct dmub_cmd_cable_id_output output; /**< Output */ 5179 uint8_t output_raw; /**< Raw data output */ 5180 } data; 5181 }; 5182 5183 /** 5184 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5185 */ 5186 enum dmub_cmd_secure_display_type { 5187 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5188 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5189 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5190 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5191 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5192 }; 5193 5194 #define MAX_ROI_NUM 2 5195 5196 struct dmub_cmd_roi_info { 5197 uint16_t x_start; 5198 uint16_t x_end; 5199 uint16_t y_start; 5200 uint16_t y_end; 5201 uint8_t otg_id; 5202 uint8_t phy_id; 5203 }; 5204 5205 struct dmub_cmd_roi_window_ctl { 5206 uint16_t x_start; 5207 uint16_t x_end; 5208 uint16_t y_start; 5209 uint16_t y_end; 5210 bool enable; 5211 }; 5212 5213 struct dmub_cmd_roi_ctl_info { 5214 uint8_t otg_id; 5215 uint8_t phy_id; 5216 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5217 }; 5218 5219 /** 5220 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5221 */ 5222 struct dmub_rb_cmd_secure_display { 5223 struct dmub_cmd_header header; 5224 /** 5225 * Data passed from driver to dmub firmware. 5226 */ 5227 struct dmub_cmd_roi_info roi_info; 5228 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5229 }; 5230 5231 /** 5232 * Command type of a DMUB_CMD__PSP command 5233 */ 5234 enum dmub_cmd_psp_type { 5235 DMUB_CMD__PSP_ASSR_ENABLE = 0 5236 }; 5237 5238 /** 5239 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5240 */ 5241 struct dmub_cmd_assr_enable_data { 5242 /** 5243 * ASSR enable or disable. 5244 */ 5245 uint8_t enable; 5246 /** 5247 * PHY port type. 5248 * Indicates eDP / non-eDP port type 5249 */ 5250 uint8_t phy_port_type; 5251 /** 5252 * PHY port ID. 5253 */ 5254 uint8_t phy_port_id; 5255 /** 5256 * Link encoder index. 5257 */ 5258 uint8_t link_enc_index; 5259 /** 5260 * HPO mode. 5261 */ 5262 uint8_t hpo_mode; 5263 5264 /** 5265 * Reserved field. 5266 */ 5267 uint8_t reserved[7]; 5268 }; 5269 5270 /** 5271 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5272 */ 5273 struct dmub_rb_cmd_assr_enable { 5274 /** 5275 * Command header. 5276 */ 5277 struct dmub_cmd_header header; 5278 5279 /** 5280 * Assr data. 5281 */ 5282 struct dmub_cmd_assr_enable_data assr_data; 5283 5284 /** 5285 * Reserved field. 5286 */ 5287 uint32_t reserved[3]; 5288 }; 5289 5290 /** 5291 * union dmub_rb_cmd - DMUB inbox command. 5292 */ 5293 union dmub_rb_cmd { 5294 /** 5295 * Elements shared with all commands. 5296 */ 5297 struct dmub_rb_cmd_common cmd_common; 5298 /** 5299 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5300 */ 5301 struct dmub_rb_cmd_read_modify_write read_modify_write; 5302 /** 5303 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5304 */ 5305 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5306 /** 5307 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5308 */ 5309 struct dmub_rb_cmd_burst_write burst_write; 5310 /** 5311 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5312 */ 5313 struct dmub_rb_cmd_reg_wait reg_wait; 5314 /** 5315 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5316 */ 5317 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5318 /** 5319 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5320 */ 5321 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5322 /** 5323 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5324 */ 5325 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5326 /** 5327 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5328 */ 5329 struct dmub_rb_cmd_dpphy_init dpphy_init; 5330 /** 5331 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5332 */ 5333 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5334 /** 5335 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5336 */ 5337 struct dmub_rb_cmd_domain_control domain_control; 5338 /** 5339 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5340 */ 5341 struct dmub_rb_cmd_psr_set_version psr_set_version; 5342 /** 5343 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5344 */ 5345 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5346 /** 5347 * Definition of a DMUB_CMD__PSR_ENABLE command. 5348 */ 5349 struct dmub_rb_cmd_psr_enable psr_enable; 5350 /** 5351 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5352 */ 5353 struct dmub_rb_cmd_psr_set_level psr_set_level; 5354 /** 5355 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5356 */ 5357 struct dmub_rb_cmd_psr_force_static psr_force_static; 5358 /** 5359 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5360 */ 5361 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5362 /** 5363 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5364 */ 5365 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5366 /** 5367 * Definition of a DMUB_CMD__HW_LOCK command. 5368 * Command is used by driver and FW. 5369 */ 5370 struct dmub_rb_cmd_lock_hw lock_hw; 5371 /** 5372 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5373 */ 5374 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5375 /** 5376 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5377 */ 5378 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5379 /** 5380 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5381 */ 5382 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5383 /** 5384 * Definition of a DMUB_CMD__MALL command. 5385 */ 5386 struct dmub_rb_cmd_mall mall; 5387 5388 /** 5389 * Definition of a DMUB_CMD__CAB command. 5390 */ 5391 struct dmub_rb_cmd_cab_for_ss cab; 5392 5393 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5394 5395 /** 5396 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5397 */ 5398 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5399 5400 /** 5401 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5402 */ 5403 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5404 5405 /** 5406 * Definition of DMUB_CMD__PANEL_CNTL commands. 5407 */ 5408 struct dmub_rb_cmd_panel_cntl panel_cntl; 5409 5410 /** 5411 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5412 */ 5413 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5414 5415 /** 5416 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5417 */ 5418 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5419 5420 /** 5421 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5422 */ 5423 struct dmub_rb_cmd_abm_set_level abm_set_level; 5424 5425 /** 5426 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5427 */ 5428 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5429 5430 /** 5431 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5432 */ 5433 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5434 5435 /** 5436 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5437 */ 5438 struct dmub_rb_cmd_abm_init_config abm_init_config; 5439 5440 /** 5441 * Definition of a DMUB_CMD__ABM_PAUSE command. 5442 */ 5443 struct dmub_rb_cmd_abm_pause abm_pause; 5444 5445 /** 5446 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5447 */ 5448 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5449 5450 /** 5451 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5452 */ 5453 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5454 5455 /** 5456 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5457 */ 5458 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5459 5460 /** 5461 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5462 */ 5463 struct dmub_rb_cmd_abm_set_event abm_set_event; 5464 5465 /** 5466 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5467 */ 5468 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5469 5470 /** 5471 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5472 */ 5473 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5474 5475 /** 5476 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5477 */ 5478 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5479 5480 /** 5481 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5482 */ 5483 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5484 struct dmub_rb_cmd_drr_update drr_update; 5485 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5486 5487 /** 5488 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5489 */ 5490 struct dmub_rb_cmd_lvtma_control lvtma_control; 5491 /** 5492 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5493 */ 5494 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5495 /** 5496 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5497 */ 5498 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5499 /** 5500 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5501 */ 5502 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5503 /** 5504 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5505 */ 5506 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 5507 /** 5508 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5509 */ 5510 struct dmub_rb_cmd_set_config_request set_config_request; 5511 /** 5512 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5513 */ 5514 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5515 /** 5516 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 5517 */ 5518 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 5519 /** 5520 * Definition of a DMUB_CMD__EDID_CEA command. 5521 */ 5522 struct dmub_rb_cmd_edid_cea edid_cea; 5523 /** 5524 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5525 */ 5526 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5527 5528 /** 5529 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5530 */ 5531 struct dmub_rb_cmd_query_hpd_state query_hpd; 5532 /** 5533 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5534 */ 5535 struct dmub_rb_cmd_secure_display secure_display; 5536 5537 /** 5538 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5539 */ 5540 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5541 /** 5542 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5543 */ 5544 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5545 /** 5546 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 5547 */ 5548 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 5549 /* 5550 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5551 */ 5552 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5553 /** 5554 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5555 */ 5556 struct dmub_rb_cmd_replay_enable replay_enable; 5557 /** 5558 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5559 */ 5560 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5561 /** 5562 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5563 */ 5564 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5565 /** 5566 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5567 */ 5568 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5569 5570 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5571 /** 5572 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5573 */ 5574 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5575 /** 5576 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5577 */ 5578 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5579 /** 5580 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5581 */ 5582 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5583 /** 5584 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5585 */ 5586 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5587 /** 5588 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5589 */ 5590 struct dmub_rb_cmd_assr_enable assr_enable; 5591 struct dmub_rb_cmd_fams2 fams2_config; 5592 5593 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5594 5595 struct dmub_rb_cmd_fams2_flip fams2_flip; 5596 }; 5597 5598 /** 5599 * union dmub_rb_out_cmd - Outbox command 5600 */ 5601 union dmub_rb_out_cmd { 5602 /** 5603 * Parameters common to every command. 5604 */ 5605 struct dmub_rb_cmd_common cmd_common; 5606 /** 5607 * AUX reply command. 5608 */ 5609 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5610 /** 5611 * HPD notify command. 5612 */ 5613 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5614 /** 5615 * SET_CONFIG reply command. 5616 */ 5617 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5618 /** 5619 * DPIA notification command. 5620 */ 5621 struct dmub_rb_cmd_dpia_notification dpia_notification; 5622 /** 5623 * HPD sense notification command. 5624 */ 5625 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5626 }; 5627 #pragma pack(pop) 5628 5629 5630 //============================================================================== 5631 //</DMUB_CMD>=================================================================== 5632 //============================================================================== 5633 //< DMUB_RB>==================================================================== 5634 //============================================================================== 5635 5636 /** 5637 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5638 */ 5639 struct dmub_rb_init_params { 5640 void *ctx; /**< Caller provided context pointer */ 5641 void *base_address; /**< CPU base address for ring's data */ 5642 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5643 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5644 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5645 }; 5646 5647 /** 5648 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5649 */ 5650 struct dmub_rb { 5651 void *base_address; /**< CPU address for the ring's data */ 5652 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5653 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5654 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5655 5656 void *ctx; /**< Caller provided context pointer */ 5657 void *dmub; /**< Pointer to the DMUB interface */ 5658 }; 5659 5660 /** 5661 * @brief Checks if the ringbuffer is empty. 5662 * 5663 * @param rb DMUB Ringbuffer 5664 * @return true if empty 5665 * @return false otherwise 5666 */ 5667 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5668 { 5669 return (rb->wrpt == rb->rptr); 5670 } 5671 5672 /** 5673 * @brief Checks if the ringbuffer is full 5674 * 5675 * @param rb DMUB Ringbuffer 5676 * @return true if full 5677 * @return false otherwise 5678 */ 5679 static inline bool dmub_rb_full(struct dmub_rb *rb) 5680 { 5681 uint32_t data_count; 5682 5683 if (rb->wrpt >= rb->rptr) 5684 data_count = rb->wrpt - rb->rptr; 5685 else 5686 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5687 5688 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5689 } 5690 5691 /** 5692 * @brief Pushes a command into the ringbuffer 5693 * 5694 * @param rb DMUB ringbuffer 5695 * @param cmd The command to push 5696 * @return true if the ringbuffer was not full 5697 * @return false otherwise 5698 */ 5699 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5700 const union dmub_rb_cmd *cmd) 5701 { 5702 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5703 const uint64_t *src = (const uint64_t *)cmd; 5704 uint8_t i; 5705 5706 if (dmub_rb_full(rb)) 5707 return false; 5708 5709 // copying data 5710 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5711 *dst++ = *src++; 5712 5713 rb->wrpt += DMUB_RB_CMD_SIZE; 5714 5715 if (rb->wrpt >= rb->capacity) 5716 rb->wrpt %= rb->capacity; 5717 5718 return true; 5719 } 5720 5721 /** 5722 * @brief Pushes a command into the DMUB outbox ringbuffer 5723 * 5724 * @param rb DMUB outbox ringbuffer 5725 * @param cmd Outbox command 5726 * @return true if not full 5727 * @return false otherwise 5728 */ 5729 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5730 const union dmub_rb_out_cmd *cmd) 5731 { 5732 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 5733 const uint8_t *src = (const uint8_t *)cmd; 5734 5735 if (dmub_rb_full(rb)) 5736 return false; 5737 5738 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 5739 5740 rb->wrpt += DMUB_RB_CMD_SIZE; 5741 5742 if (rb->wrpt >= rb->capacity) 5743 rb->wrpt %= rb->capacity; 5744 5745 return true; 5746 } 5747 5748 /** 5749 * @brief Returns the next unprocessed command in the ringbuffer. 5750 * 5751 * @param rb DMUB ringbuffer 5752 * @param cmd The command to return 5753 * @return true if not empty 5754 * @return false otherwise 5755 */ 5756 static inline bool dmub_rb_front(struct dmub_rb *rb, 5757 union dmub_rb_cmd **cmd) 5758 { 5759 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 5760 5761 if (dmub_rb_empty(rb)) 5762 return false; 5763 5764 *cmd = (union dmub_rb_cmd *)rb_cmd; 5765 5766 return true; 5767 } 5768 5769 /** 5770 * @brief Determines the next ringbuffer offset. 5771 * 5772 * @param rb DMUB inbox ringbuffer 5773 * @param num_cmds Number of commands 5774 * @param next_rptr The next offset in the ringbuffer 5775 */ 5776 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 5777 uint32_t num_cmds, 5778 uint32_t *next_rptr) 5779 { 5780 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 5781 5782 if (*next_rptr >= rb->capacity) 5783 *next_rptr %= rb->capacity; 5784 } 5785 5786 /** 5787 * @brief Returns a pointer to a command in the inbox. 5788 * 5789 * @param rb DMUB inbox ringbuffer 5790 * @param cmd The inbox command to return 5791 * @param rptr The ringbuffer offset 5792 * @return true if not empty 5793 * @return false otherwise 5794 */ 5795 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 5796 union dmub_rb_cmd **cmd, 5797 uint32_t rptr) 5798 { 5799 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 5800 5801 if (dmub_rb_empty(rb)) 5802 return false; 5803 5804 *cmd = (union dmub_rb_cmd *)rb_cmd; 5805 5806 return true; 5807 } 5808 5809 /** 5810 * @brief Returns the next unprocessed command in the outbox. 5811 * 5812 * @param rb DMUB outbox ringbuffer 5813 * @param cmd The outbox command to return 5814 * @return true if not empty 5815 * @return false otherwise 5816 */ 5817 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 5818 union dmub_rb_out_cmd *cmd) 5819 { 5820 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 5821 uint64_t *dst = (uint64_t *)cmd; 5822 uint8_t i; 5823 5824 if (dmub_rb_empty(rb)) 5825 return false; 5826 5827 // copying data 5828 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5829 *dst++ = *src++; 5830 5831 return true; 5832 } 5833 5834 /** 5835 * @brief Removes the front entry in the ringbuffer. 5836 * 5837 * @param rb DMUB ringbuffer 5838 * @return true if the command was removed 5839 * @return false if there were no commands 5840 */ 5841 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 5842 { 5843 if (dmub_rb_empty(rb)) 5844 return false; 5845 5846 rb->rptr += DMUB_RB_CMD_SIZE; 5847 5848 if (rb->rptr >= rb->capacity) 5849 rb->rptr %= rb->capacity; 5850 5851 return true; 5852 } 5853 5854 /** 5855 * @brief Flushes commands in the ringbuffer to framebuffer memory. 5856 * 5857 * Avoids a race condition where DMCUB accesses memory while 5858 * there are still writes in flight to framebuffer. 5859 * 5860 * @param rb DMUB ringbuffer 5861 */ 5862 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 5863 { 5864 uint32_t rptr = rb->rptr; 5865 uint32_t wptr = rb->wrpt; 5866 5867 while (rptr != wptr) { 5868 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 5869 uint8_t i; 5870 5871 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5872 (void)READ_ONCE(*data++); 5873 5874 rptr += DMUB_RB_CMD_SIZE; 5875 if (rptr >= rb->capacity) 5876 rptr %= rb->capacity; 5877 } 5878 } 5879 5880 /** 5881 * @brief Initializes a DMCUB ringbuffer 5882 * 5883 * @param rb DMUB ringbuffer 5884 * @param init_params initial configuration for the ringbuffer 5885 */ 5886 static inline void dmub_rb_init(struct dmub_rb *rb, 5887 struct dmub_rb_init_params *init_params) 5888 { 5889 rb->base_address = init_params->base_address; 5890 rb->capacity = init_params->capacity; 5891 rb->rptr = init_params->read_ptr; 5892 rb->wrpt = init_params->write_ptr; 5893 } 5894 5895 /** 5896 * @brief Copies output data from in/out commands into the given command. 5897 * 5898 * @param rb DMUB ringbuffer 5899 * @param cmd Command to copy data into 5900 */ 5901 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5902 union dmub_rb_cmd *cmd) 5903 { 5904 // Copy rb entry back into command 5905 uint8_t *rd_ptr = (rb->rptr == 0) ? 5906 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5907 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5908 5909 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5910 } 5911 5912 //============================================================================== 5913 //</DMUB_RB>==================================================================== 5914 //============================================================================== 5915 #endif /* _DMUB_CMD_H_ */ 5916