1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 /** 148 * OS/FW agnostic memcpy 149 */ 150 #ifndef dmub_memcpy 151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 152 #endif 153 154 /** 155 * OS/FW agnostic memset 156 */ 157 #ifndef dmub_memset 158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 159 #endif 160 161 #if defined(__cplusplus) 162 extern "C" { 163 #endif 164 165 /** 166 * OS/FW agnostic udelay 167 */ 168 #ifndef dmub_udelay 169 #define dmub_udelay(microseconds) udelay(microseconds) 170 #endif 171 172 #pragma pack(push, 1) 173 #define ABM_NUM_OF_ACE_SEGMENTS 5 174 175 union abm_flags { 176 struct { 177 /** 178 * @abm_enabled: Indicates if ABM is enabled. 179 */ 180 unsigned int abm_enabled : 1; 181 182 /** 183 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 184 */ 185 unsigned int disable_abm_requested : 1; 186 187 /** 188 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled 189 * immediately. 190 */ 191 unsigned int disable_abm_immediately : 1; 192 193 /** 194 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 195 * to be disabled immediately and keep gain. 196 */ 197 unsigned int disable_abm_immediate_keep_gain : 1; 198 199 /** 200 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 201 */ 202 unsigned int fractional_pwm : 1; 203 204 /** 205 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 206 * of user backlight level. 207 */ 208 unsigned int abm_gradual_bl_change : 1; 209 } bitfields; 210 211 unsigned int u32All; 212 }; 213 214 struct abm_save_restore { 215 /** 216 * @flags: Misc. ABM flags. 217 */ 218 union abm_flags flags; 219 220 /** 221 * @pause: true: pause ABM and get state 222 * false: unpause ABM after setting state 223 */ 224 uint32_t pause; 225 226 /** 227 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 228 */ 229 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 230 231 /** 232 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 233 */ 234 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 235 236 /** 237 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 238 */ 239 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 240 241 242 /** 243 * @knee_threshold: Current x-position of ACE knee (u0.16). 244 */ 245 uint32_t knee_threshold; 246 /** 247 * @current_gain: Current backlight reduction (u16.16). 248 */ 249 uint32_t current_gain; 250 /** 251 * @curr_bl_level: Current actual backlight level converging to target backlight level. 252 */ 253 uint16_t curr_bl_level; 254 255 /** 256 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 257 */ 258 uint16_t curr_user_bl_level; 259 260 }; 261 262 /** 263 * union dmub_addr - DMUB physical/virtual 64-bit address. 264 */ 265 union dmub_addr { 266 struct { 267 uint32_t low_part; /**< Lower 32 bits */ 268 uint32_t high_part; /**< Upper 32 bits */ 269 } u; /*<< Low/high bit access */ 270 uint64_t quad_part; /*<< 64 bit address */ 271 }; 272 #pragma pack(pop) 273 274 /** 275 * Dirty rect definition. 276 */ 277 struct dmub_rect { 278 /** 279 * Dirty rect x offset. 280 */ 281 uint32_t x; 282 283 /** 284 * Dirty rect y offset. 285 */ 286 uint32_t y; 287 288 /** 289 * Dirty rect width. 290 */ 291 uint32_t width; 292 293 /** 294 * Dirty rect height. 295 */ 296 uint32_t height; 297 }; 298 299 /** 300 * Flags that can be set by driver to change some PSR behaviour. 301 */ 302 union dmub_psr_debug_flags { 303 /** 304 * Debug flags. 305 */ 306 struct { 307 /** 308 * Enable visual confirm in FW. 309 */ 310 uint32_t visual_confirm : 1; 311 312 /** 313 * Force all selective updates to bw full frame updates. 314 */ 315 uint32_t force_full_frame_update : 1; 316 317 /** 318 * Use HW Lock Mgr object to do HW locking in FW. 319 */ 320 uint32_t use_hw_lock_mgr : 1; 321 322 /** 323 * Use TPS3 signal when restore main link. 324 */ 325 uint32_t force_wakeup_by_tps3 : 1; 326 327 /** 328 * Back to back flip, therefore cannot power down PHY 329 */ 330 uint32_t back_to_back_flip : 1; 331 332 } bitfields; 333 334 /** 335 * Union for debug flags. 336 */ 337 uint32_t u32All; 338 }; 339 340 /** 341 * Flags that can be set by driver to change some Replay behaviour. 342 */ 343 union replay_debug_flags { 344 struct { 345 /** 346 * 0x1 (bit 0) 347 * Enable visual confirm in FW. 348 */ 349 uint32_t visual_confirm : 1; 350 351 /** 352 * 0x2 (bit 1) 353 * @skip_crc: Set if need to skip CRC. 354 */ 355 uint32_t skip_crc : 1; 356 357 /** 358 * 0x4 (bit 2) 359 * @force_link_power_on: Force disable ALPM control 360 */ 361 uint32_t force_link_power_on : 1; 362 363 /** 364 * 0x8 (bit 3) 365 * @force_phy_power_on: Force phy power on 366 */ 367 uint32_t force_phy_power_on : 1; 368 369 /** 370 * 0x10 (bit 4) 371 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 372 */ 373 uint32_t timing_resync_disabled : 1; 374 375 /** 376 * 0x20 (bit 5) 377 * @skip_crtc_disabled: CRTC disable skipped 378 */ 379 uint32_t skip_crtc_disabled : 1; 380 381 /** 382 * 0x40 (bit 6) 383 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 384 */ 385 uint32_t force_defer_one_frame_update : 1; 386 387 /** 388 * 0x80 (bit 7) 389 * @disable_delay_alpm_on: Force disable delay alpm on 390 */ 391 uint32_t disable_delay_alpm_on : 1; 392 393 /** 394 * 0x100 (bit 8) 395 * @disable_desync_error_check: Force disable desync error check 396 */ 397 uint32_t disable_desync_error_check : 1; 398 399 /** 400 * 0x200 (bit 9) 401 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 402 */ 403 uint32_t force_self_update_when_abm_non_steady : 1; 404 405 /** 406 * 0x400 (bit 10) 407 * @force_disable_ips1: Force disable IPS1 state 408 */ 409 uint32_t force_disable_ips1 : 1; 410 411 /** 412 * 0x800 (bit 11) 413 * @force_disable_ips2: Force disable IPS2 state 414 */ 415 uint32_t force_disable_ips2 : 1; 416 417 uint32_t reserved : 20; 418 } bitfields; 419 420 uint32_t u32All; 421 }; 422 423 union replay_hw_flags { 424 struct { 425 /** 426 * @allow_alpm_fw_standby_mode: To indicate whether the 427 * ALPM FW standby mode is allowed 428 */ 429 uint32_t allow_alpm_fw_standby_mode : 1; 430 431 /* 432 * @dsc_enable_status: DSC enable status in driver 433 */ 434 uint32_t dsc_enable_status : 1; 435 436 /** 437 * @fec_enable_status: receive fec enable/disable status from driver 438 */ 439 uint32_t fec_enable_status : 1; 440 441 /* 442 * @smu_optimizations_en: SMU power optimization. 443 * Only when active display is Replay capable and display enters Replay. 444 * Trigger interrupt to SMU to powerup/down. 445 */ 446 uint32_t smu_optimizations_en : 1; 447 448 /** 449 * @phy_power_state: Indicates current phy power state 450 */ 451 uint32_t phy_power_state : 1; 452 453 /** 454 * @link_power_state: Indicates current link power state 455 */ 456 uint32_t link_power_state : 1; 457 /** 458 * Use TPS3 signal when restore main link. 459 */ 460 uint32_t force_wakeup_by_tps3 : 1; 461 } bitfields; 462 463 uint32_t u32All; 464 }; 465 466 /** 467 * DMUB feature capabilities. 468 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 469 */ 470 struct dmub_feature_caps { 471 /** 472 * Max PSR version supported by FW. 473 */ 474 uint8_t psr; 475 uint8_t fw_assisted_mclk_switch; 476 uint8_t reserved[4]; 477 uint8_t subvp_psr_support; 478 uint8_t gecc_enable; 479 uint8_t replay_supported; 480 uint8_t replay_reserved[3]; 481 }; 482 483 struct dmub_visual_confirm_color { 484 /** 485 * Maximum 10 bits color value 486 */ 487 uint16_t color_r_cr; 488 uint16_t color_g_y; 489 uint16_t color_b_cb; 490 uint16_t panel_inst; 491 }; 492 493 #if defined(__cplusplus) 494 } 495 #endif 496 497 //============================================================================== 498 //</DMUB_TYPES>================================================================= 499 //============================================================================== 500 //< DMUB_META>================================================================== 501 //============================================================================== 502 #pragma pack(push, 1) 503 504 /* Magic value for identifying dmub_fw_meta_info */ 505 #define DMUB_FW_META_MAGIC 0x444D5542 506 507 /* Offset from the end of the file to the dmub_fw_meta_info */ 508 #define DMUB_FW_META_OFFSET 0x24 509 510 /** 511 * struct dmub_fw_meta_info - metadata associated with fw binary 512 * 513 * NOTE: This should be considered a stable API. Fields should 514 * not be repurposed or reordered. New fields should be 515 * added instead to extend the structure. 516 * 517 * @magic_value: magic value identifying DMUB firmware meta info 518 * @fw_region_size: size of the firmware state region 519 * @trace_buffer_size: size of the tracebuffer region 520 * @fw_version: the firmware version information 521 * @dal_fw: 1 if the firmware is DAL 522 */ 523 struct dmub_fw_meta_info { 524 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 525 uint32_t fw_region_size; /**< size of the firmware state region */ 526 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 527 uint32_t fw_version; /**< the firmware version information */ 528 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 529 uint8_t reserved[3]; /**< padding bits */ 530 }; 531 532 /** 533 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 534 */ 535 union dmub_fw_meta { 536 struct dmub_fw_meta_info info; /**< metadata info */ 537 uint8_t reserved[64]; /**< padding bits */ 538 }; 539 540 #pragma pack(pop) 541 542 //============================================================================== 543 //< DMUB Trace Buffer>================================================================ 544 //============================================================================== 545 /** 546 * dmub_trace_code_t - firmware trace code, 32-bits 547 */ 548 typedef uint32_t dmub_trace_code_t; 549 550 /** 551 * struct dmcub_trace_buf_entry - Firmware trace entry 552 */ 553 struct dmcub_trace_buf_entry { 554 dmub_trace_code_t trace_code; /**< trace code for the event */ 555 uint32_t tick_count; /**< the tick count at time of trace */ 556 uint32_t param0; /**< trace defined parameter 0 */ 557 uint32_t param1; /**< trace defined parameter 1 */ 558 }; 559 560 //============================================================================== 561 //< DMUB_STATUS>================================================================ 562 //============================================================================== 563 564 /** 565 * DMCUB scratch registers can be used to determine firmware status. 566 * Current scratch register usage is as follows: 567 * 568 * SCRATCH0: FW Boot Status register 569 * SCRATCH5: LVTMA Status Register 570 * SCRATCH15: FW Boot Options register 571 */ 572 573 /** 574 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 575 */ 576 union dmub_fw_boot_status { 577 struct { 578 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 579 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 580 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 581 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 582 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 583 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 584 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 585 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 586 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 587 } bits; /**< status bits */ 588 uint32_t all; /**< 32-bit access to status bits */ 589 }; 590 591 /** 592 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 593 */ 594 enum dmub_fw_boot_status_bit { 595 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 596 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 597 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 598 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 599 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 600 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 601 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 602 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 603 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 604 }; 605 606 /* Register bit definition for SCRATCH5 */ 607 union dmub_lvtma_status { 608 struct { 609 uint32_t psp_ok : 1; 610 uint32_t edp_on : 1; 611 uint32_t reserved : 30; 612 } bits; 613 uint32_t all; 614 }; 615 616 enum dmub_lvtma_status_bit { 617 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 618 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 619 }; 620 621 enum dmub_ips_disable_type { 622 DMUB_IPS_ENABLE = 0, 623 DMUB_IPS_DISABLE_ALL = 1, 624 DMUB_IPS_DISABLE_IPS1 = 2, 625 DMUB_IPS_DISABLE_IPS2 = 3, 626 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 627 DMUB_IPS_DISABLE_DYNAMIC = 5, 628 }; 629 630 #define DMUB_IPS1_ALLOW_MASK 0x00000001 631 #define DMUB_IPS2_ALLOW_MASK 0x00000002 632 #define DMUB_IPS1_COMMIT_MASK 0x00000004 633 #define DMUB_IPS2_COMMIT_MASK 0x00000008 634 635 /** 636 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 637 */ 638 union dmub_fw_boot_options { 639 struct { 640 uint32_t pemu_env : 1; /**< 1 if PEMU */ 641 uint32_t fpga_env : 1; /**< 1 if FPGA */ 642 uint32_t optimized_init : 1; /**< 1 if optimized init */ 643 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 644 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 645 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 646 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 647 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 648 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 649 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 650 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 651 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 652 uint32_t power_optimization: 1; 653 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 654 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 655 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 656 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 657 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 658 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 659 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 660 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 661 uint32_t ips_disable: 3; /* options to disable ips support*/ 662 uint32_t reserved : 9; /**< reserved */ 663 } bits; /**< boot bits */ 664 uint32_t all; /**< 32-bit access to bits */ 665 }; 666 667 enum dmub_fw_boot_options_bit { 668 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 669 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 670 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 671 }; 672 673 //============================================================================== 674 //</DMUB_STATUS>================================================================ 675 //============================================================================== 676 //< DMUB_VBIOS>================================================================= 677 //============================================================================== 678 679 /* 680 * enum dmub_cmd_vbios_type - VBIOS commands. 681 * 682 * Command IDs should be treated as stable ABI. 683 * Do not reuse or modify IDs. 684 */ 685 enum dmub_cmd_vbios_type { 686 /** 687 * Configures the DIG encoder. 688 */ 689 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 690 /** 691 * Controls the PHY. 692 */ 693 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 694 /** 695 * Sets the pixel clock/symbol clock. 696 */ 697 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 698 /** 699 * Enables or disables power gating. 700 */ 701 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 702 /** 703 * Controls embedded panels. 704 */ 705 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 706 /** 707 * Query DP alt status on a transmitter. 708 */ 709 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 710 /** 711 * Controls domain power gating 712 */ 713 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 714 }; 715 716 //============================================================================== 717 //</DMUB_VBIOS>================================================================= 718 //============================================================================== 719 //< DMUB_GPINT>================================================================= 720 //============================================================================== 721 722 /** 723 * The shifts and masks below may alternatively be used to format and read 724 * the command register bits. 725 */ 726 727 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 728 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 729 730 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 731 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 732 733 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 734 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 735 736 /** 737 * Command responses. 738 */ 739 740 /** 741 * Return response for DMUB_GPINT__STOP_FW command. 742 */ 743 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 744 745 /** 746 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 747 */ 748 union dmub_gpint_data_register { 749 struct { 750 uint32_t param : 16; /**< 16-bit parameter */ 751 uint32_t command_code : 12; /**< GPINT command */ 752 uint32_t status : 4; /**< Command status bit */ 753 } bits; /**< GPINT bit access */ 754 uint32_t all; /**< GPINT 32-bit access */ 755 }; 756 757 /* 758 * enum dmub_gpint_command - GPINT command to DMCUB FW 759 * 760 * Command IDs should be treated as stable ABI. 761 * Do not reuse or modify IDs. 762 */ 763 enum dmub_gpint_command { 764 /** 765 * Invalid command, ignored. 766 */ 767 DMUB_GPINT__INVALID_COMMAND = 0, 768 /** 769 * DESC: Queries the firmware version. 770 * RETURN: Firmware version. 771 */ 772 DMUB_GPINT__GET_FW_VERSION = 1, 773 /** 774 * DESC: Halts the firmware. 775 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 776 */ 777 DMUB_GPINT__STOP_FW = 2, 778 /** 779 * DESC: Get PSR state from FW. 780 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 781 */ 782 DMUB_GPINT__GET_PSR_STATE = 7, 783 /** 784 * DESC: Notifies DMCUB of the currently active streams. 785 * ARGS: Stream mask, 1 bit per active stream index. 786 */ 787 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 788 /** 789 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 790 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 791 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 792 * RETURN: PSR residency in milli-percent. 793 */ 794 DMUB_GPINT__PSR_RESIDENCY = 9, 795 796 /** 797 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 798 */ 799 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 800 801 /** 802 * DESC: Get REPLAY state from FW. 803 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 804 */ 805 DMUB_GPINT__GET_REPLAY_STATE = 13, 806 807 /** 808 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 809 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 810 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 811 * RETURN: REPLAY residency in milli-percent. 812 */ 813 DMUB_GPINT__REPLAY_RESIDENCY = 14, 814 815 /** 816 * DESC: Updates the trace buffer lower 32-bit mask. 817 * ARGS: The new mask 818 * RETURN: Lower 32-bit mask. 819 */ 820 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 821 /** 822 * DESC: Updates the trace buffer lower 32-bit mask. 823 * ARGS: The new mask 824 * RETURN: Lower 32-bit mask. 825 */ 826 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 827 /** 828 * DESC: Updates the trace buffer mask bi0~bit15. 829 * ARGS: The new mask 830 * RETURN: Lower 32-bit mask. 831 */ 832 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 833 }; 834 835 /** 836 * INBOX0 generic command definition 837 */ 838 union dmub_inbox0_cmd_common { 839 struct { 840 uint32_t command_code: 8; /**< INBOX0 command code */ 841 uint32_t param: 24; /**< 24-bit parameter */ 842 } bits; 843 uint32_t all; 844 }; 845 846 /** 847 * INBOX0 hw_lock command definition 848 */ 849 union dmub_inbox0_cmd_lock_hw { 850 struct { 851 uint32_t command_code: 8; 852 853 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 854 uint32_t hw_lock_client: 2; 855 856 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 857 uint32_t otg_inst: 3; 858 uint32_t opp_inst: 3; 859 uint32_t dig_inst: 3; 860 861 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 862 uint32_t lock_pipe: 1; 863 uint32_t lock_cursor: 1; 864 uint32_t lock_dig: 1; 865 uint32_t triple_buffer_lock: 1; 866 867 uint32_t lock: 1; /**< Lock */ 868 uint32_t should_release: 1; /**< Release */ 869 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 870 } bits; 871 uint32_t all; 872 }; 873 874 union dmub_inbox0_data_register { 875 union dmub_inbox0_cmd_common inbox0_cmd_common; 876 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 877 }; 878 879 enum dmub_inbox0_command { 880 /** 881 * DESC: Invalid command, ignored. 882 */ 883 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 884 /** 885 * DESC: Notification to acquire/release HW lock 886 * ARGS: 887 */ 888 DMUB_INBOX0_CMD__HW_LOCK = 1, 889 }; 890 //============================================================================== 891 //</DMUB_GPINT>================================================================= 892 //============================================================================== 893 //< DMUB_CMD>=================================================================== 894 //============================================================================== 895 896 /** 897 * Size in bytes of each DMUB command. 898 */ 899 #define DMUB_RB_CMD_SIZE 64 900 901 /** 902 * Maximum number of items in the DMUB ringbuffer. 903 */ 904 #define DMUB_RB_MAX_ENTRY 128 905 906 /** 907 * Ringbuffer size in bytes. 908 */ 909 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 910 911 /** 912 * REG_SET mask for reg offload. 913 */ 914 #define REG_SET_MASK 0xFFFF 915 916 /* 917 * enum dmub_cmd_type - DMUB inbox command. 918 * 919 * Command IDs should be treated as stable ABI. 920 * Do not reuse or modify IDs. 921 */ 922 enum dmub_cmd_type { 923 /** 924 * Invalid command. 925 */ 926 DMUB_CMD__NULL = 0, 927 /** 928 * Read modify write register sequence offload. 929 */ 930 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 931 /** 932 * Field update register sequence offload. 933 */ 934 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 935 /** 936 * Burst write sequence offload. 937 */ 938 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 939 /** 940 * Reg wait sequence offload. 941 */ 942 DMUB_CMD__REG_REG_WAIT = 4, 943 /** 944 * Workaround to avoid HUBP underflow during NV12 playback. 945 */ 946 DMUB_CMD__PLAT_54186_WA = 5, 947 /** 948 * Command type used to query FW feature caps. 949 */ 950 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 951 /** 952 * Command type used to get visual confirm color. 953 */ 954 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 955 /** 956 * Command type used for all PSR commands. 957 */ 958 DMUB_CMD__PSR = 64, 959 /** 960 * Command type used for all MALL commands. 961 */ 962 DMUB_CMD__MALL = 65, 963 /** 964 * Command type used for all ABM commands. 965 */ 966 DMUB_CMD__ABM = 66, 967 /** 968 * Command type used to update dirty rects in FW. 969 */ 970 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 971 /** 972 * Command type used to update cursor info in FW. 973 */ 974 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 975 /** 976 * Command type used for HW locking in FW. 977 */ 978 DMUB_CMD__HW_LOCK = 69, 979 /** 980 * Command type used to access DP AUX. 981 */ 982 DMUB_CMD__DP_AUX_ACCESS = 70, 983 /** 984 * Command type used for OUTBOX1 notification enable 985 */ 986 DMUB_CMD__OUTBOX1_ENABLE = 71, 987 988 /** 989 * Command type used for all idle optimization commands. 990 */ 991 DMUB_CMD__IDLE_OPT = 72, 992 /** 993 * Command type used for all clock manager commands. 994 */ 995 DMUB_CMD__CLK_MGR = 73, 996 /** 997 * Command type used for all panel control commands. 998 */ 999 DMUB_CMD__PANEL_CNTL = 74, 1000 1001 /** 1002 * Command type used for all CAB commands. 1003 */ 1004 DMUB_CMD__CAB_FOR_SS = 75, 1005 1006 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1007 1008 /** 1009 * Command type used for interfacing with DPIA. 1010 */ 1011 DMUB_CMD__DPIA = 77, 1012 /** 1013 * Command type used for EDID CEA parsing 1014 */ 1015 DMUB_CMD__EDID_CEA = 79, 1016 /** 1017 * Command type used for getting usbc cable ID 1018 */ 1019 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1020 /** 1021 * Command type used to query HPD state. 1022 */ 1023 DMUB_CMD__QUERY_HPD_STATE = 82, 1024 /** 1025 * Command type used for all VBIOS interface commands. 1026 */ 1027 /** 1028 * Command type used for all REPLAY commands. 1029 */ 1030 DMUB_CMD__REPLAY = 83, 1031 1032 /** 1033 * Command type used for all SECURE_DISPLAY commands. 1034 */ 1035 DMUB_CMD__SECURE_DISPLAY = 85, 1036 1037 /** 1038 * Command type used to set DPIA HPD interrupt state 1039 */ 1040 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1041 1042 DMUB_CMD__VBIOS = 128, 1043 }; 1044 1045 /** 1046 * enum dmub_out_cmd_type - DMUB outbox commands. 1047 */ 1048 enum dmub_out_cmd_type { 1049 /** 1050 * Invalid outbox command, ignored. 1051 */ 1052 DMUB_OUT_CMD__NULL = 0, 1053 /** 1054 * Command type used for DP AUX Reply data notification 1055 */ 1056 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1057 /** 1058 * Command type used for DP HPD event notification 1059 */ 1060 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1061 /** 1062 * Command type used for SET_CONFIG Reply notification 1063 */ 1064 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1065 /** 1066 * Command type used for USB4 DPIA notification 1067 */ 1068 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1069 }; 1070 1071 /* DMUB_CMD__DPIA command sub-types. */ 1072 enum dmub_cmd_dpia_type { 1073 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1074 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1075 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1076 }; 1077 1078 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1079 enum dmub_cmd_dpia_notification_type { 1080 DPIA_NOTIFY__BW_ALLOCATION = 0, 1081 }; 1082 1083 #pragma pack(push, 1) 1084 1085 /** 1086 * struct dmub_cmd_header - Common command header fields. 1087 */ 1088 struct dmub_cmd_header { 1089 unsigned int type : 8; /**< command type */ 1090 unsigned int sub_type : 8; /**< command sub type */ 1091 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1092 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1093 unsigned int reserved0 : 6; /**< reserved bits */ 1094 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1095 unsigned int reserved1 : 2; /**< reserved bits */ 1096 }; 1097 1098 /* 1099 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1100 * 1101 * 60 payload bytes can hold up to 5 sets of read modify writes, 1102 * each take 3 dwords. 1103 * 1104 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1105 * 1106 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1107 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1108 */ 1109 struct dmub_cmd_read_modify_write_sequence { 1110 uint32_t addr; /**< register address */ 1111 uint32_t modify_mask; /**< modify mask */ 1112 uint32_t modify_value; /**< modify value */ 1113 }; 1114 1115 /** 1116 * Maximum number of ops in read modify write sequence. 1117 */ 1118 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1119 1120 /** 1121 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1122 */ 1123 struct dmub_rb_cmd_read_modify_write { 1124 struct dmub_cmd_header header; /**< command header */ 1125 /** 1126 * Read modify write sequence. 1127 */ 1128 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1129 }; 1130 1131 /* 1132 * Update a register with specified masks and values sequeunce 1133 * 1134 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1135 * 1136 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1137 * 1138 * 1139 * USE CASE: 1140 * 1. auto-increment register where additional read would update pointer and produce wrong result 1141 * 2. toggle a bit without read in the middle 1142 */ 1143 1144 struct dmub_cmd_reg_field_update_sequence { 1145 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1146 uint32_t modify_value; /**< value to update with */ 1147 }; 1148 1149 /** 1150 * Maximum number of ops in field update sequence. 1151 */ 1152 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1153 1154 /** 1155 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1156 */ 1157 struct dmub_rb_cmd_reg_field_update_sequence { 1158 struct dmub_cmd_header header; /**< command header */ 1159 uint32_t addr; /**< register address */ 1160 /** 1161 * Field update sequence. 1162 */ 1163 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1164 }; 1165 1166 1167 /** 1168 * Maximum number of burst write values. 1169 */ 1170 #define DMUB_BURST_WRITE_VALUES__MAX 14 1171 1172 /* 1173 * struct dmub_rb_cmd_burst_write - Burst write 1174 * 1175 * support use case such as writing out LUTs. 1176 * 1177 * 60 payload bytes can hold up to 14 values to write to given address 1178 * 1179 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1180 */ 1181 struct dmub_rb_cmd_burst_write { 1182 struct dmub_cmd_header header; /**< command header */ 1183 uint32_t addr; /**< register start address */ 1184 /** 1185 * Burst write register values. 1186 */ 1187 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1188 }; 1189 1190 /** 1191 * struct dmub_rb_cmd_common - Common command header 1192 */ 1193 struct dmub_rb_cmd_common { 1194 struct dmub_cmd_header header; /**< command header */ 1195 /** 1196 * Padding to RB_CMD_SIZE 1197 */ 1198 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1199 }; 1200 1201 /** 1202 * struct dmub_cmd_reg_wait_data - Register wait data 1203 */ 1204 struct dmub_cmd_reg_wait_data { 1205 uint32_t addr; /**< Register address */ 1206 uint32_t mask; /**< Mask for register bits */ 1207 uint32_t condition_field_value; /**< Value to wait for */ 1208 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1209 }; 1210 1211 /** 1212 * struct dmub_rb_cmd_reg_wait - Register wait command 1213 */ 1214 struct dmub_rb_cmd_reg_wait { 1215 struct dmub_cmd_header header; /**< Command header */ 1216 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1217 }; 1218 1219 /** 1220 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1221 * 1222 * Reprograms surface parameters to avoid underflow. 1223 */ 1224 struct dmub_cmd_PLAT_54186_wa { 1225 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1226 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1227 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1228 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1229 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1230 struct { 1231 uint8_t hubp_inst : 4; /**< HUBP instance */ 1232 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 1233 uint8_t immediate :1; /**< Immediate flip */ 1234 uint8_t vmid : 4; /**< VMID */ 1235 uint8_t grph_stereo : 1; /**< 1 if stereo */ 1236 uint32_t reserved : 21; /**< Reserved */ 1237 } flip_params; /**< Pageflip parameters */ 1238 uint32_t reserved[9]; /**< Reserved bits */ 1239 }; 1240 1241 /** 1242 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1243 */ 1244 struct dmub_rb_cmd_PLAT_54186_wa { 1245 struct dmub_cmd_header header; /**< Command header */ 1246 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1247 }; 1248 1249 /** 1250 * enum dmub_cmd_mall_type - MALL commands 1251 */ 1252 enum dmub_cmd_mall_type { 1253 /** 1254 * Allows display refresh from MALL. 1255 */ 1256 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1257 /** 1258 * Disallows display refresh from MALL. 1259 */ 1260 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1261 /** 1262 * Cursor copy for MALL. 1263 */ 1264 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1265 /** 1266 * Controls DF requests. 1267 */ 1268 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1269 }; 1270 1271 /** 1272 * struct dmub_rb_cmd_mall - MALL command data. 1273 */ 1274 struct dmub_rb_cmd_mall { 1275 struct dmub_cmd_header header; /**< Common command header */ 1276 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1277 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1278 uint32_t tmr_delay; /**< Timer delay */ 1279 uint32_t tmr_scale; /**< Timer scale */ 1280 uint16_t cursor_width; /**< Cursor width in pixels */ 1281 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1282 uint16_t cursor_height; /**< Cursor height in pixels */ 1283 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1284 uint8_t debug_bits; /**< Debug bits */ 1285 1286 uint8_t reserved1; /**< Reserved bits */ 1287 uint8_t reserved2; /**< Reserved bits */ 1288 }; 1289 1290 /** 1291 * enum dmub_cmd_cab_type - CAB command data. 1292 */ 1293 enum dmub_cmd_cab_type { 1294 /** 1295 * No idle optimizations (i.e. no CAB) 1296 */ 1297 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1298 /** 1299 * No DCN requests for memory 1300 */ 1301 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1302 /** 1303 * Fit surfaces in CAB (i.e. CAB enable) 1304 */ 1305 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1306 }; 1307 1308 /** 1309 * struct dmub_rb_cmd_cab - CAB command data. 1310 */ 1311 struct dmub_rb_cmd_cab_for_ss { 1312 struct dmub_cmd_header header; 1313 uint8_t cab_alloc_ways; /* total number of ways */ 1314 uint8_t debug_bits; /* debug bits */ 1315 }; 1316 1317 /** 1318 * Enum for indicating which MCLK switch mode per pipe 1319 */ 1320 enum mclk_switch_mode { 1321 NONE = 0, 1322 FPO = 1, 1323 SUBVP = 2, 1324 VBLANK = 3, 1325 }; 1326 1327 /* Per pipe struct which stores the MCLK switch mode 1328 * data to be sent to DMUB. 1329 * Named "v2" for now -- once FPO and SUBVP are fully merged 1330 * the type name can be updated 1331 */ 1332 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1333 union { 1334 struct { 1335 uint32_t pix_clk_100hz; 1336 uint16_t main_vblank_start; 1337 uint16_t main_vblank_end; 1338 uint16_t mall_region_lines; 1339 uint16_t prefetch_lines; 1340 uint16_t prefetch_to_mall_start_lines; 1341 uint16_t processing_delay_lines; 1342 uint16_t htotal; // required to calculate line time for multi-display cases 1343 uint16_t vtotal; 1344 uint8_t main_pipe_index; 1345 uint8_t phantom_pipe_index; 1346 /* Since the microschedule is calculated in terms of OTG lines, 1347 * include any scaling factors to make sure when we get accurate 1348 * conversion when programming MALL_START_LINE (which is in terms 1349 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1350 * is 1/2 (numerator = 1, denominator = 2). 1351 */ 1352 uint8_t scale_factor_numerator; 1353 uint8_t scale_factor_denominator; 1354 uint8_t is_drr; 1355 uint8_t main_split_pipe_index; 1356 uint8_t phantom_split_pipe_index; 1357 } subvp_data; 1358 1359 struct { 1360 uint32_t pix_clk_100hz; 1361 uint16_t vblank_start; 1362 uint16_t vblank_end; 1363 uint16_t vstartup_start; 1364 uint16_t vtotal; 1365 uint16_t htotal; 1366 uint8_t vblank_pipe_index; 1367 uint8_t padding[1]; 1368 struct { 1369 uint8_t drr_in_use; 1370 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1371 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1372 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1373 uint8_t use_ramping; // Use ramping or not 1374 uint8_t drr_vblank_start_margin; 1375 } drr_info; // DRR considered as part of SubVP + VBLANK case 1376 } vblank_data; 1377 } pipe_config; 1378 1379 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1380 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1381 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1382 */ 1383 uint8_t mode; // enum mclk_switch_mode 1384 }; 1385 1386 /** 1387 * Config data for Sub-VP and FPO 1388 * Named "v2" for now -- once FPO and SUBVP are fully merged 1389 * the type name can be updated 1390 */ 1391 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1392 uint16_t watermark_a_cache; 1393 uint8_t vertical_int_margin_us; 1394 uint8_t pstate_allow_width_us; 1395 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1396 }; 1397 1398 /** 1399 * DMUB rb command definition for Sub-VP and FPO 1400 * Named "v2" for now -- once FPO and SUBVP are fully merged 1401 * the type name can be updated 1402 */ 1403 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1404 struct dmub_cmd_header header; 1405 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1406 }; 1407 1408 /** 1409 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1410 */ 1411 enum dmub_cmd_idle_opt_type { 1412 /** 1413 * DCN hardware restore. 1414 */ 1415 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1416 1417 /** 1418 * DCN hardware save. 1419 */ 1420 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1421 1422 /** 1423 * DCN hardware notify idle. 1424 */ 1425 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1426 }; 1427 1428 /** 1429 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1430 */ 1431 struct dmub_rb_cmd_idle_opt_dcn_restore { 1432 struct dmub_cmd_header header; /**< header */ 1433 }; 1434 1435 /** 1436 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1437 */ 1438 struct dmub_dcn_notify_idle_cntl_data { 1439 uint8_t driver_idle; 1440 uint8_t pad[1]; 1441 }; 1442 1443 /** 1444 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1445 */ 1446 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1447 struct dmub_cmd_header header; /**< header */ 1448 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1449 }; 1450 1451 /** 1452 * struct dmub_clocks - Clock update notification. 1453 */ 1454 struct dmub_clocks { 1455 uint32_t dispclk_khz; /**< dispclk kHz */ 1456 uint32_t dppclk_khz; /**< dppclk kHz */ 1457 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1458 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1459 }; 1460 1461 /** 1462 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1463 */ 1464 enum dmub_cmd_clk_mgr_type { 1465 /** 1466 * Notify DMCUB of clock update. 1467 */ 1468 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1469 }; 1470 1471 /** 1472 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1473 */ 1474 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1475 struct dmub_cmd_header header; /**< header */ 1476 struct dmub_clocks clocks; /**< clock data */ 1477 }; 1478 1479 /** 1480 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1481 */ 1482 struct dmub_cmd_digx_encoder_control_data { 1483 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1484 }; 1485 1486 /** 1487 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1488 */ 1489 struct dmub_rb_cmd_digx_encoder_control { 1490 struct dmub_cmd_header header; /**< header */ 1491 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1492 }; 1493 1494 /** 1495 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1496 */ 1497 struct dmub_cmd_set_pixel_clock_data { 1498 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1499 }; 1500 1501 /** 1502 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1503 */ 1504 struct dmub_rb_cmd_set_pixel_clock { 1505 struct dmub_cmd_header header; /**< header */ 1506 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1507 }; 1508 1509 /** 1510 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1511 */ 1512 struct dmub_cmd_enable_disp_power_gating_data { 1513 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1514 }; 1515 1516 /** 1517 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1518 */ 1519 struct dmub_rb_cmd_enable_disp_power_gating { 1520 struct dmub_cmd_header header; /**< header */ 1521 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1522 }; 1523 1524 /** 1525 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1526 */ 1527 struct dmub_dig_transmitter_control_data_v1_7 { 1528 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1529 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1530 union { 1531 uint8_t digmode; /**< enum atom_encode_mode_def */ 1532 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1533 } mode_laneset; 1534 uint8_t lanenum; /**< Number of lanes */ 1535 union { 1536 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1537 } symclk_units; 1538 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1539 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1540 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1541 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1542 uint8_t reserved1; /**< For future use */ 1543 uint8_t reserved2[3]; /**< For future use */ 1544 uint32_t reserved3[11]; /**< For future use */ 1545 }; 1546 1547 /** 1548 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1549 */ 1550 union dmub_cmd_dig1_transmitter_control_data { 1551 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1552 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1553 }; 1554 1555 /** 1556 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1557 */ 1558 struct dmub_rb_cmd_dig1_transmitter_control { 1559 struct dmub_cmd_header header; /**< header */ 1560 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1561 }; 1562 1563 /** 1564 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1565 */ 1566 struct dmub_rb_cmd_domain_control_data { 1567 uint8_t inst : 6; /**< DOMAIN instance to control */ 1568 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1569 uint8_t reserved[3]; /**< Reserved for future use */ 1570 }; 1571 1572 /** 1573 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1574 */ 1575 struct dmub_rb_cmd_domain_control { 1576 struct dmub_cmd_header header; /**< header */ 1577 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1578 }; 1579 1580 /** 1581 * DPIA tunnel command parameters. 1582 */ 1583 struct dmub_cmd_dig_dpia_control_data { 1584 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1585 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1586 union { 1587 uint8_t digmode; /** enum atom_encode_mode_def */ 1588 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1589 } mode_laneset; 1590 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1591 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1592 uint8_t hpdsel; /** =0: HPD is not assigned */ 1593 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1594 uint8_t dpia_id; /** Index of DPIA */ 1595 uint8_t fec_rdy : 1; 1596 uint8_t reserved : 7; 1597 uint32_t reserved1; 1598 }; 1599 1600 /** 1601 * DMUB command for DPIA tunnel control. 1602 */ 1603 struct dmub_rb_cmd_dig1_dpia_control { 1604 struct dmub_cmd_header header; 1605 struct dmub_cmd_dig_dpia_control_data dpia_control; 1606 }; 1607 1608 /** 1609 * SET_CONFIG Command Payload 1610 */ 1611 struct set_config_cmd_payload { 1612 uint8_t msg_type; /* set config message type */ 1613 uint8_t msg_data; /* set config message data */ 1614 }; 1615 1616 /** 1617 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1618 */ 1619 struct dmub_cmd_set_config_control_data { 1620 struct set_config_cmd_payload cmd_pkt; 1621 uint8_t instance; /* DPIA instance */ 1622 uint8_t immed_status; /* Immediate status returned in case of error */ 1623 }; 1624 1625 /** 1626 * DMUB command structure for SET_CONFIG command. 1627 */ 1628 struct dmub_rb_cmd_set_config_access { 1629 struct dmub_cmd_header header; /* header */ 1630 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1631 }; 1632 1633 /** 1634 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1635 */ 1636 struct dmub_cmd_mst_alloc_slots_control_data { 1637 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1638 uint8_t instance; /* DPIA instance */ 1639 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1640 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1641 }; 1642 1643 /** 1644 * DMUB command structure for SET_ command. 1645 */ 1646 struct dmub_rb_cmd_set_mst_alloc_slots { 1647 struct dmub_cmd_header header; /* header */ 1648 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1649 }; 1650 1651 /** 1652 * DMUB command structure for DPIA HPD int enable control. 1653 */ 1654 struct dmub_rb_cmd_dpia_hpd_int_enable { 1655 struct dmub_cmd_header header; /* header */ 1656 uint32_t enable; /* dpia hpd interrupt enable */ 1657 }; 1658 1659 /** 1660 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1661 */ 1662 struct dmub_rb_cmd_dpphy_init { 1663 struct dmub_cmd_header header; /**< header */ 1664 uint8_t reserved[60]; /**< reserved bits */ 1665 }; 1666 1667 /** 1668 * enum dp_aux_request_action - DP AUX request command listing. 1669 * 1670 * 4 AUX request command bits are shifted to high nibble. 1671 */ 1672 enum dp_aux_request_action { 1673 /** I2C-over-AUX write request */ 1674 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1675 /** I2C-over-AUX read request */ 1676 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1677 /** I2C-over-AUX write status request */ 1678 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1679 /** I2C-over-AUX write request with MOT=1 */ 1680 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1681 /** I2C-over-AUX read request with MOT=1 */ 1682 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1683 /** I2C-over-AUX write status request with MOT=1 */ 1684 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1685 /** Native AUX write request */ 1686 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1687 /** Native AUX read request */ 1688 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1689 }; 1690 1691 /** 1692 * enum aux_return_code_type - DP AUX process return code listing. 1693 */ 1694 enum aux_return_code_type { 1695 /** AUX process succeeded */ 1696 AUX_RET_SUCCESS = 0, 1697 /** AUX process failed with unknown reason */ 1698 AUX_RET_ERROR_UNKNOWN, 1699 /** AUX process completed with invalid reply */ 1700 AUX_RET_ERROR_INVALID_REPLY, 1701 /** AUX process timed out */ 1702 AUX_RET_ERROR_TIMEOUT, 1703 /** HPD was low during AUX process */ 1704 AUX_RET_ERROR_HPD_DISCON, 1705 /** Failed to acquire AUX engine */ 1706 AUX_RET_ERROR_ENGINE_ACQUIRE, 1707 /** AUX request not supported */ 1708 AUX_RET_ERROR_INVALID_OPERATION, 1709 /** AUX process not available */ 1710 AUX_RET_ERROR_PROTOCOL_ERROR, 1711 }; 1712 1713 /** 1714 * enum aux_channel_type - DP AUX channel type listing. 1715 */ 1716 enum aux_channel_type { 1717 /** AUX thru Legacy DP AUX */ 1718 AUX_CHANNEL_LEGACY_DDC, 1719 /** AUX thru DPIA DP tunneling */ 1720 AUX_CHANNEL_DPIA 1721 }; 1722 1723 /** 1724 * struct aux_transaction_parameters - DP AUX request transaction data 1725 */ 1726 struct aux_transaction_parameters { 1727 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1728 uint8_t action; /**< enum dp_aux_request_action */ 1729 uint8_t length; /**< DP AUX request data length */ 1730 uint8_t reserved; /**< For future use */ 1731 uint32_t address; /**< DP AUX address */ 1732 uint8_t data[16]; /**< DP AUX write data */ 1733 }; 1734 1735 /** 1736 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1737 */ 1738 struct dmub_cmd_dp_aux_control_data { 1739 uint8_t instance; /**< AUX instance or DPIA instance */ 1740 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1741 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1742 uint8_t reserved0; /**< For future use */ 1743 uint16_t timeout; /**< timeout time in us */ 1744 uint16_t reserved1; /**< For future use */ 1745 enum aux_channel_type type; /**< enum aux_channel_type */ 1746 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1747 }; 1748 1749 /** 1750 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1751 */ 1752 struct dmub_rb_cmd_dp_aux_access { 1753 /** 1754 * Command header. 1755 */ 1756 struct dmub_cmd_header header; 1757 /** 1758 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1759 */ 1760 struct dmub_cmd_dp_aux_control_data aux_control; 1761 }; 1762 1763 /** 1764 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1765 */ 1766 struct dmub_rb_cmd_outbox1_enable { 1767 /** 1768 * Command header. 1769 */ 1770 struct dmub_cmd_header header; 1771 /** 1772 * enable: 0x0 -> disable outbox1 notification (default value) 1773 * 0x1 -> enable outbox1 notification 1774 */ 1775 uint32_t enable; 1776 }; 1777 1778 /* DP AUX Reply command - OutBox Cmd */ 1779 /** 1780 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1781 */ 1782 struct aux_reply_data { 1783 /** 1784 * Aux cmd 1785 */ 1786 uint8_t command; 1787 /** 1788 * Aux reply data length (max: 16 bytes) 1789 */ 1790 uint8_t length; 1791 /** 1792 * Alignment only 1793 */ 1794 uint8_t pad[2]; 1795 /** 1796 * Aux reply data 1797 */ 1798 uint8_t data[16]; 1799 }; 1800 1801 /** 1802 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1803 */ 1804 struct aux_reply_control_data { 1805 /** 1806 * Reserved for future use 1807 */ 1808 uint32_t handle; 1809 /** 1810 * Aux Instance 1811 */ 1812 uint8_t instance; 1813 /** 1814 * Aux transaction result: definition in enum aux_return_code_type 1815 */ 1816 uint8_t result; 1817 /** 1818 * Alignment only 1819 */ 1820 uint16_t pad; 1821 }; 1822 1823 /** 1824 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1825 */ 1826 struct dmub_rb_cmd_dp_aux_reply { 1827 /** 1828 * Command header. 1829 */ 1830 struct dmub_cmd_header header; 1831 /** 1832 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1833 */ 1834 struct aux_reply_control_data control; 1835 /** 1836 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1837 */ 1838 struct aux_reply_data reply_data; 1839 }; 1840 1841 /* DP HPD Notify command - OutBox Cmd */ 1842 /** 1843 * DP HPD Type 1844 */ 1845 enum dp_hpd_type { 1846 /** 1847 * Normal DP HPD 1848 */ 1849 DP_HPD = 0, 1850 /** 1851 * DP HPD short pulse 1852 */ 1853 DP_IRQ 1854 }; 1855 1856 /** 1857 * DP HPD Status 1858 */ 1859 enum dp_hpd_status { 1860 /** 1861 * DP_HPD status low 1862 */ 1863 DP_HPD_UNPLUG = 0, 1864 /** 1865 * DP_HPD status high 1866 */ 1867 DP_HPD_PLUG 1868 }; 1869 1870 /** 1871 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1872 */ 1873 struct dp_hpd_data { 1874 /** 1875 * DP HPD instance 1876 */ 1877 uint8_t instance; 1878 /** 1879 * HPD type 1880 */ 1881 uint8_t hpd_type; 1882 /** 1883 * HPD status: only for type: DP_HPD to indicate status 1884 */ 1885 uint8_t hpd_status; 1886 /** 1887 * Alignment only 1888 */ 1889 uint8_t pad; 1890 }; 1891 1892 /** 1893 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1894 */ 1895 struct dmub_rb_cmd_dp_hpd_notify { 1896 /** 1897 * Command header. 1898 */ 1899 struct dmub_cmd_header header; 1900 /** 1901 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1902 */ 1903 struct dp_hpd_data hpd_data; 1904 }; 1905 1906 /** 1907 * Definition of a SET_CONFIG reply from DPOA. 1908 */ 1909 enum set_config_status { 1910 SET_CONFIG_PENDING = 0, 1911 SET_CONFIG_ACK_RECEIVED, 1912 SET_CONFIG_RX_TIMEOUT, 1913 SET_CONFIG_UNKNOWN_ERROR, 1914 }; 1915 1916 /** 1917 * Definition of a set_config reply 1918 */ 1919 struct set_config_reply_control_data { 1920 uint8_t instance; /* DPIA Instance */ 1921 uint8_t status; /* Set Config reply */ 1922 uint16_t pad; /* Alignment */ 1923 }; 1924 1925 /** 1926 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1927 */ 1928 struct dmub_rb_cmd_dp_set_config_reply { 1929 struct dmub_cmd_header header; 1930 struct set_config_reply_control_data set_config_reply_control; 1931 }; 1932 1933 /** 1934 * Definition of a DPIA notification header 1935 */ 1936 struct dpia_notification_header { 1937 uint8_t instance; /**< DPIA Instance */ 1938 uint8_t reserved[3]; 1939 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1940 }; 1941 1942 /** 1943 * Definition of the common data struct of DPIA notification 1944 */ 1945 struct dpia_notification_common { 1946 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1947 - sizeof(struct dpia_notification_header)]; 1948 }; 1949 1950 /** 1951 * Definition of a DPIA notification data 1952 */ 1953 struct dpia_bw_allocation_notify_data { 1954 union { 1955 struct { 1956 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1957 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1958 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1959 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1960 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1961 uint16_t reserved: 11; /**< Reserved */ 1962 } bits; 1963 1964 uint16_t flags; 1965 }; 1966 1967 uint8_t cm_id; /**< CM ID */ 1968 uint8_t group_id; /**< Group ID */ 1969 uint8_t granularity; /**< BW Allocation Granularity */ 1970 uint8_t estimated_bw; /**< Estimated_BW */ 1971 uint8_t allocated_bw; /**< Allocated_BW */ 1972 uint8_t reserved; 1973 }; 1974 1975 /** 1976 * union dpia_notify_data_type - DPIA Notification in Outbox command 1977 */ 1978 union dpia_notification_data { 1979 /** 1980 * DPIA Notification for common data struct 1981 */ 1982 struct dpia_notification_common common_data; 1983 1984 /** 1985 * DPIA Notification for DP BW Allocation support 1986 */ 1987 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1988 }; 1989 1990 /** 1991 * Definition of a DPIA notification payload 1992 */ 1993 struct dpia_notification_payload { 1994 struct dpia_notification_header header; 1995 union dpia_notification_data data; /**< DPIA notification payload data */ 1996 }; 1997 1998 /** 1999 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2000 */ 2001 struct dmub_rb_cmd_dpia_notification { 2002 struct dmub_cmd_header header; /**< DPIA notification header */ 2003 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2004 }; 2005 2006 /** 2007 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2008 */ 2009 struct dmub_cmd_hpd_state_query_data { 2010 uint8_t instance; /**< HPD instance or DPIA instance */ 2011 uint8_t result; /**< For returning HPD state */ 2012 uint16_t pad; /** < Alignment */ 2013 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2014 enum aux_return_code_type status; /**< for returning the status of command */ 2015 }; 2016 2017 /** 2018 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2019 */ 2020 struct dmub_rb_cmd_query_hpd_state { 2021 /** 2022 * Command header. 2023 */ 2024 struct dmub_cmd_header header; 2025 /** 2026 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2027 */ 2028 struct dmub_cmd_hpd_state_query_data data; 2029 }; 2030 2031 /* 2032 * Command IDs should be treated as stable ABI. 2033 * Do not reuse or modify IDs. 2034 */ 2035 2036 /** 2037 * PSR command sub-types. 2038 */ 2039 enum dmub_cmd_psr_type { 2040 /** 2041 * Set PSR version support. 2042 */ 2043 DMUB_CMD__PSR_SET_VERSION = 0, 2044 /** 2045 * Copy driver-calculated parameters to PSR state. 2046 */ 2047 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2048 /** 2049 * Enable PSR. 2050 */ 2051 DMUB_CMD__PSR_ENABLE = 2, 2052 2053 /** 2054 * Disable PSR. 2055 */ 2056 DMUB_CMD__PSR_DISABLE = 3, 2057 2058 /** 2059 * Set PSR level. 2060 * PSR level is a 16-bit value dicated by driver that 2061 * will enable/disable different functionality. 2062 */ 2063 DMUB_CMD__PSR_SET_LEVEL = 4, 2064 2065 /** 2066 * Forces PSR enabled until an explicit PSR disable call. 2067 */ 2068 DMUB_CMD__PSR_FORCE_STATIC = 5, 2069 /** 2070 * Set vtotal in psr active for FreeSync PSR. 2071 */ 2072 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2073 /** 2074 * Set PSR power option 2075 */ 2076 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2077 }; 2078 2079 enum dmub_cmd_fams_type { 2080 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2081 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2082 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2083 /** 2084 * For SubVP set manual trigger in FW because it 2085 * triggers DRR_UPDATE_PENDING which SubVP relies 2086 * on (for any SubVP cases that use a DRR display) 2087 */ 2088 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2089 }; 2090 2091 /** 2092 * PSR versions. 2093 */ 2094 enum psr_version { 2095 /** 2096 * PSR version 1. 2097 */ 2098 PSR_VERSION_1 = 0, 2099 /** 2100 * Freesync PSR SU. 2101 */ 2102 PSR_VERSION_SU_1 = 1, 2103 /** 2104 * PSR not supported. 2105 */ 2106 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2107 }; 2108 2109 /** 2110 * PHY Link rate for DP. 2111 */ 2112 enum phy_link_rate { 2113 /** 2114 * not supported. 2115 */ 2116 PHY_RATE_UNKNOWN = 0, 2117 /** 2118 * Rate_1 (RBR) - 1.62 Gbps/Lane 2119 */ 2120 PHY_RATE_162 = 1, 2121 /** 2122 * Rate_2 - 2.16 Gbps/Lane 2123 */ 2124 PHY_RATE_216 = 2, 2125 /** 2126 * Rate_3 - 2.43 Gbps/Lane 2127 */ 2128 PHY_RATE_243 = 3, 2129 /** 2130 * Rate_4 (HBR) - 2.70 Gbps/Lane 2131 */ 2132 PHY_RATE_270 = 4, 2133 /** 2134 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2135 */ 2136 PHY_RATE_324 = 5, 2137 /** 2138 * Rate_6 - 4.32 Gbps/Lane 2139 */ 2140 PHY_RATE_432 = 6, 2141 /** 2142 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2143 */ 2144 PHY_RATE_540 = 7, 2145 /** 2146 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2147 */ 2148 PHY_RATE_810 = 8, 2149 /** 2150 * UHBR10 - 10.0 Gbps/Lane 2151 */ 2152 PHY_RATE_1000 = 9, 2153 /** 2154 * UHBR13.5 - 13.5 Gbps/Lane 2155 */ 2156 PHY_RATE_1350 = 10, 2157 /** 2158 * UHBR10 - 20.0 Gbps/Lane 2159 */ 2160 PHY_RATE_2000 = 11, 2161 }; 2162 2163 /** 2164 * enum dmub_phy_fsm_state - PHY FSM states. 2165 * PHY FSM state to transit to during PSR enable/disable. 2166 */ 2167 enum dmub_phy_fsm_state { 2168 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2169 DMUB_PHY_FSM_RESET, 2170 DMUB_PHY_FSM_RESET_RELEASED, 2171 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2172 DMUB_PHY_FSM_INITIALIZED, 2173 DMUB_PHY_FSM_CALIBRATED, 2174 DMUB_PHY_FSM_CALIBRATED_LP, 2175 DMUB_PHY_FSM_CALIBRATED_PG, 2176 DMUB_PHY_FSM_POWER_DOWN, 2177 DMUB_PHY_FSM_PLL_EN, 2178 DMUB_PHY_FSM_TX_EN, 2179 DMUB_PHY_FSM_FAST_LP, 2180 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2181 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2182 DMUB_PHY_FSM_P2_PLL_OFF, 2183 DMUB_PHY_FSM_P2_PLL_ON, 2184 }; 2185 2186 /** 2187 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2188 */ 2189 struct dmub_cmd_psr_copy_settings_data { 2190 /** 2191 * Flags that can be set by driver to change some PSR behaviour. 2192 */ 2193 union dmub_psr_debug_flags debug; 2194 /** 2195 * 16-bit value dicated by driver that will enable/disable different functionality. 2196 */ 2197 uint16_t psr_level; 2198 /** 2199 * DPP HW instance. 2200 */ 2201 uint8_t dpp_inst; 2202 /** 2203 * MPCC HW instance. 2204 * Not used in dmub fw, 2205 * dmub fw will get active opp by reading odm registers. 2206 */ 2207 uint8_t mpcc_inst; 2208 /** 2209 * OPP HW instance. 2210 * Not used in dmub fw, 2211 * dmub fw will get active opp by reading odm registers. 2212 */ 2213 uint8_t opp_inst; 2214 /** 2215 * OTG HW instance. 2216 */ 2217 uint8_t otg_inst; 2218 /** 2219 * DIG FE HW instance. 2220 */ 2221 uint8_t digfe_inst; 2222 /** 2223 * DIG BE HW instance. 2224 */ 2225 uint8_t digbe_inst; 2226 /** 2227 * DP PHY HW instance. 2228 */ 2229 uint8_t dpphy_inst; 2230 /** 2231 * AUX HW instance. 2232 */ 2233 uint8_t aux_inst; 2234 /** 2235 * Determines if SMU optimzations are enabled/disabled. 2236 */ 2237 uint8_t smu_optimizations_en; 2238 /** 2239 * Unused. 2240 * TODO: Remove. 2241 */ 2242 uint8_t frame_delay; 2243 /** 2244 * If RFB setup time is greater than the total VBLANK time, 2245 * it is not possible for the sink to capture the video frame 2246 * in the same frame the SDP is sent. In this case, 2247 * the frame capture indication bit should be set and an extra 2248 * static frame should be transmitted to the sink. 2249 */ 2250 uint8_t frame_cap_ind; 2251 /** 2252 * Granularity of Y offset supported by sink. 2253 */ 2254 uint8_t su_y_granularity; 2255 /** 2256 * Indicates whether sink should start capturing 2257 * immediately following active scan line, 2258 * or starting with the 2nd active scan line. 2259 */ 2260 uint8_t line_capture_indication; 2261 /** 2262 * Multi-display optimizations are implemented on certain ASICs. 2263 */ 2264 uint8_t multi_disp_optimizations_en; 2265 /** 2266 * The last possible line SDP may be transmitted without violating 2267 * the RFB setup time or entering the active video frame. 2268 */ 2269 uint16_t init_sdp_deadline; 2270 /** 2271 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2272 */ 2273 uint8_t rate_control_caps ; 2274 /* 2275 * Force PSRSU always doing full frame update 2276 */ 2277 uint8_t force_ffu_mode; 2278 /** 2279 * Length of each horizontal line in us. 2280 */ 2281 uint32_t line_time_in_us; 2282 /** 2283 * FEC enable status in driver 2284 */ 2285 uint8_t fec_enable_status; 2286 /** 2287 * FEC re-enable delay when PSR exit. 2288 * unit is 100us, range form 0~255(0xFF). 2289 */ 2290 uint8_t fec_enable_delay_in100us; 2291 /** 2292 * PSR control version. 2293 */ 2294 uint8_t cmd_version; 2295 /** 2296 * Panel Instance. 2297 * Panel instance to identify which psr_state to use 2298 * Currently the support is only for 0 or 1 2299 */ 2300 uint8_t panel_inst; 2301 /* 2302 * DSC enable status in driver 2303 */ 2304 uint8_t dsc_enable_status; 2305 /* 2306 * Use FSM state for PSR power up/down 2307 */ 2308 uint8_t use_phy_fsm; 2309 /** 2310 * frame delay for frame re-lock 2311 */ 2312 uint8_t relock_delay_frame_cnt; 2313 /** 2314 * Explicit padding to 4 byte boundary. 2315 */ 2316 uint8_t pad3; 2317 /** 2318 * DSC Slice height. 2319 */ 2320 uint16_t dsc_slice_height; 2321 /** 2322 * Some panels request main link off before xth vertical line 2323 */ 2324 uint16_t poweroff_before_vertical_line; 2325 }; 2326 2327 /** 2328 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2329 */ 2330 struct dmub_rb_cmd_psr_copy_settings { 2331 /** 2332 * Command header. 2333 */ 2334 struct dmub_cmd_header header; 2335 /** 2336 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2337 */ 2338 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2339 }; 2340 2341 /** 2342 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2343 */ 2344 struct dmub_cmd_psr_set_level_data { 2345 /** 2346 * 16-bit value dicated by driver that will enable/disable different functionality. 2347 */ 2348 uint16_t psr_level; 2349 /** 2350 * PSR control version. 2351 */ 2352 uint8_t cmd_version; 2353 /** 2354 * Panel Instance. 2355 * Panel instance to identify which psr_state to use 2356 * Currently the support is only for 0 or 1 2357 */ 2358 uint8_t panel_inst; 2359 }; 2360 2361 /** 2362 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2363 */ 2364 struct dmub_rb_cmd_psr_set_level { 2365 /** 2366 * Command header. 2367 */ 2368 struct dmub_cmd_header header; 2369 /** 2370 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2371 */ 2372 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2373 }; 2374 2375 struct dmub_rb_cmd_psr_enable_data { 2376 /** 2377 * PSR control version. 2378 */ 2379 uint8_t cmd_version; 2380 /** 2381 * Panel Instance. 2382 * Panel instance to identify which psr_state to use 2383 * Currently the support is only for 0 or 1 2384 */ 2385 uint8_t panel_inst; 2386 /** 2387 * Phy state to enter. 2388 * Values to use are defined in dmub_phy_fsm_state 2389 */ 2390 uint8_t phy_fsm_state; 2391 /** 2392 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2393 * Set this using enum phy_link_rate. 2394 * This does not support HDMI/DP2 for now. 2395 */ 2396 uint8_t phy_rate; 2397 }; 2398 2399 /** 2400 * Definition of a DMUB_CMD__PSR_ENABLE command. 2401 * PSR enable/disable is controlled using the sub_type. 2402 */ 2403 struct dmub_rb_cmd_psr_enable { 2404 /** 2405 * Command header. 2406 */ 2407 struct dmub_cmd_header header; 2408 2409 struct dmub_rb_cmd_psr_enable_data data; 2410 }; 2411 2412 /** 2413 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2414 */ 2415 struct dmub_cmd_psr_set_version_data { 2416 /** 2417 * PSR version that FW should implement. 2418 */ 2419 enum psr_version version; 2420 /** 2421 * PSR control version. 2422 */ 2423 uint8_t cmd_version; 2424 /** 2425 * Panel Instance. 2426 * Panel instance to identify which psr_state to use 2427 * Currently the support is only for 0 or 1 2428 */ 2429 uint8_t panel_inst; 2430 /** 2431 * Explicit padding to 4 byte boundary. 2432 */ 2433 uint8_t pad[2]; 2434 }; 2435 2436 /** 2437 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2438 */ 2439 struct dmub_rb_cmd_psr_set_version { 2440 /** 2441 * Command header. 2442 */ 2443 struct dmub_cmd_header header; 2444 /** 2445 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2446 */ 2447 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2448 }; 2449 2450 struct dmub_cmd_psr_force_static_data { 2451 /** 2452 * PSR control version. 2453 */ 2454 uint8_t cmd_version; 2455 /** 2456 * Panel Instance. 2457 * Panel instance to identify which psr_state to use 2458 * Currently the support is only for 0 or 1 2459 */ 2460 uint8_t panel_inst; 2461 /** 2462 * Explicit padding to 4 byte boundary. 2463 */ 2464 uint8_t pad[2]; 2465 }; 2466 2467 /** 2468 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2469 */ 2470 struct dmub_rb_cmd_psr_force_static { 2471 /** 2472 * Command header. 2473 */ 2474 struct dmub_cmd_header header; 2475 /** 2476 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2477 */ 2478 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2479 }; 2480 2481 /** 2482 * PSR SU debug flags. 2483 */ 2484 union dmub_psr_su_debug_flags { 2485 /** 2486 * PSR SU debug flags. 2487 */ 2488 struct { 2489 /** 2490 * Update dirty rect in SW only. 2491 */ 2492 uint8_t update_dirty_rect_only : 1; 2493 /** 2494 * Reset the cursor/plane state before processing the call. 2495 */ 2496 uint8_t reset_state : 1; 2497 } bitfields; 2498 2499 /** 2500 * Union for debug flags. 2501 */ 2502 uint32_t u32All; 2503 }; 2504 2505 /** 2506 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2507 * This triggers a selective update for PSR SU. 2508 */ 2509 struct dmub_cmd_update_dirty_rect_data { 2510 /** 2511 * Dirty rects from OS. 2512 */ 2513 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2514 /** 2515 * PSR SU debug flags. 2516 */ 2517 union dmub_psr_su_debug_flags debug_flags; 2518 /** 2519 * OTG HW instance. 2520 */ 2521 uint8_t pipe_idx; 2522 /** 2523 * Number of dirty rects. 2524 */ 2525 uint8_t dirty_rect_count; 2526 /** 2527 * PSR control version. 2528 */ 2529 uint8_t cmd_version; 2530 /** 2531 * Panel Instance. 2532 * Panel instance to identify which psr_state to use 2533 * Currently the support is only for 0 or 1 2534 */ 2535 uint8_t panel_inst; 2536 }; 2537 2538 /** 2539 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2540 */ 2541 struct dmub_rb_cmd_update_dirty_rect { 2542 /** 2543 * Command header. 2544 */ 2545 struct dmub_cmd_header header; 2546 /** 2547 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2548 */ 2549 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2550 }; 2551 2552 /** 2553 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2554 */ 2555 union dmub_reg_cursor_control_cfg { 2556 struct { 2557 uint32_t cur_enable: 1; 2558 uint32_t reser0: 3; 2559 uint32_t cur_2x_magnify: 1; 2560 uint32_t reser1: 3; 2561 uint32_t mode: 3; 2562 uint32_t reser2: 5; 2563 uint32_t pitch: 2; 2564 uint32_t reser3: 6; 2565 uint32_t line_per_chunk: 5; 2566 uint32_t reser4: 3; 2567 } bits; 2568 uint32_t raw; 2569 }; 2570 struct dmub_cursor_position_cache_hubp { 2571 union dmub_reg_cursor_control_cfg cur_ctl; 2572 union dmub_reg_position_cfg { 2573 struct { 2574 uint32_t cur_x_pos: 16; 2575 uint32_t cur_y_pos: 16; 2576 } bits; 2577 uint32_t raw; 2578 } position; 2579 union dmub_reg_hot_spot_cfg { 2580 struct { 2581 uint32_t hot_x: 16; 2582 uint32_t hot_y: 16; 2583 } bits; 2584 uint32_t raw; 2585 } hot_spot; 2586 union dmub_reg_dst_offset_cfg { 2587 struct { 2588 uint32_t dst_x_offset: 13; 2589 uint32_t reserved: 19; 2590 } bits; 2591 uint32_t raw; 2592 } dst_offset; 2593 }; 2594 2595 union dmub_reg_cur0_control_cfg { 2596 struct { 2597 uint32_t cur0_enable: 1; 2598 uint32_t expansion_mode: 1; 2599 uint32_t reser0: 1; 2600 uint32_t cur0_rom_en: 1; 2601 uint32_t mode: 3; 2602 uint32_t reserved: 25; 2603 } bits; 2604 uint32_t raw; 2605 }; 2606 struct dmub_cursor_position_cache_dpp { 2607 union dmub_reg_cur0_control_cfg cur0_ctl; 2608 }; 2609 struct dmub_cursor_position_cfg { 2610 struct dmub_cursor_position_cache_hubp pHubp; 2611 struct dmub_cursor_position_cache_dpp pDpp; 2612 uint8_t pipe_idx; 2613 /* 2614 * Padding is required. To be 4 Bytes Aligned. 2615 */ 2616 uint8_t padding[3]; 2617 }; 2618 2619 struct dmub_cursor_attribute_cache_hubp { 2620 uint32_t SURFACE_ADDR_HIGH; 2621 uint32_t SURFACE_ADDR; 2622 union dmub_reg_cursor_control_cfg cur_ctl; 2623 union dmub_reg_cursor_size_cfg { 2624 struct { 2625 uint32_t width: 16; 2626 uint32_t height: 16; 2627 } bits; 2628 uint32_t raw; 2629 } size; 2630 union dmub_reg_cursor_settings_cfg { 2631 struct { 2632 uint32_t dst_y_offset: 8; 2633 uint32_t chunk_hdl_adjust: 2; 2634 uint32_t reserved: 22; 2635 } bits; 2636 uint32_t raw; 2637 } settings; 2638 }; 2639 struct dmub_cursor_attribute_cache_dpp { 2640 union dmub_reg_cur0_control_cfg cur0_ctl; 2641 }; 2642 struct dmub_cursor_attributes_cfg { 2643 struct dmub_cursor_attribute_cache_hubp aHubp; 2644 struct dmub_cursor_attribute_cache_dpp aDpp; 2645 }; 2646 2647 struct dmub_cmd_update_cursor_payload0 { 2648 /** 2649 * Cursor dirty rects. 2650 */ 2651 struct dmub_rect cursor_rect; 2652 /** 2653 * PSR SU debug flags. 2654 */ 2655 union dmub_psr_su_debug_flags debug_flags; 2656 /** 2657 * Cursor enable/disable. 2658 */ 2659 uint8_t enable; 2660 /** 2661 * OTG HW instance. 2662 */ 2663 uint8_t pipe_idx; 2664 /** 2665 * PSR control version. 2666 */ 2667 uint8_t cmd_version; 2668 /** 2669 * Panel Instance. 2670 * Panel instance to identify which psr_state to use 2671 * Currently the support is only for 0 or 1 2672 */ 2673 uint8_t panel_inst; 2674 /** 2675 * Cursor Position Register. 2676 * Registers contains Hubp & Dpp modules 2677 */ 2678 struct dmub_cursor_position_cfg position_cfg; 2679 }; 2680 2681 struct dmub_cmd_update_cursor_payload1 { 2682 struct dmub_cursor_attributes_cfg attribute_cfg; 2683 }; 2684 2685 union dmub_cmd_update_cursor_info_data { 2686 struct dmub_cmd_update_cursor_payload0 payload0; 2687 struct dmub_cmd_update_cursor_payload1 payload1; 2688 }; 2689 /** 2690 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2691 */ 2692 struct dmub_rb_cmd_update_cursor_info { 2693 /** 2694 * Command header. 2695 */ 2696 struct dmub_cmd_header header; 2697 /** 2698 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2699 */ 2700 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2701 }; 2702 2703 /** 2704 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2705 */ 2706 struct dmub_cmd_psr_set_vtotal_data { 2707 /** 2708 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2709 */ 2710 uint16_t psr_vtotal_idle; 2711 /** 2712 * PSR control version. 2713 */ 2714 uint8_t cmd_version; 2715 /** 2716 * Panel Instance. 2717 * Panel instance to identify which psr_state to use 2718 * Currently the support is only for 0 or 1 2719 */ 2720 uint8_t panel_inst; 2721 /* 2722 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2723 */ 2724 uint16_t psr_vtotal_su; 2725 /** 2726 * Explicit padding to 4 byte boundary. 2727 */ 2728 uint8_t pad2[2]; 2729 }; 2730 2731 /** 2732 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2733 */ 2734 struct dmub_rb_cmd_psr_set_vtotal { 2735 /** 2736 * Command header. 2737 */ 2738 struct dmub_cmd_header header; 2739 /** 2740 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2741 */ 2742 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2743 }; 2744 2745 /** 2746 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2747 */ 2748 struct dmub_cmd_psr_set_power_opt_data { 2749 /** 2750 * PSR control version. 2751 */ 2752 uint8_t cmd_version; 2753 /** 2754 * Panel Instance. 2755 * Panel instance to identify which psr_state to use 2756 * Currently the support is only for 0 or 1 2757 */ 2758 uint8_t panel_inst; 2759 /** 2760 * Explicit padding to 4 byte boundary. 2761 */ 2762 uint8_t pad[2]; 2763 /** 2764 * PSR power option 2765 */ 2766 uint32_t power_opt; 2767 }; 2768 2769 /** 2770 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2771 */ 2772 struct dmub_rb_cmd_psr_set_power_opt { 2773 /** 2774 * Command header. 2775 */ 2776 struct dmub_cmd_header header; 2777 /** 2778 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2779 */ 2780 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2781 }; 2782 2783 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 2784 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 2785 2786 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2787 # define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 2788 # define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2789 2790 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2791 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2792 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2793 2794 enum replay_state { 2795 REPLAY_STATE_0 = 0x0, 2796 REPLAY_STATE_1 = 0x10, 2797 REPLAY_STATE_1A = 0x11, 2798 REPLAY_STATE_2 = 0x20, 2799 REPLAY_STATE_3 = 0x30, 2800 REPLAY_STATE_3INIT = 0x31, 2801 REPLAY_STATE_4 = 0x40, 2802 REPLAY_STATE_4A = 0x41, 2803 REPLAY_STATE_4B = 0x42, 2804 REPLAY_STATE_4C = 0x43, 2805 REPLAY_STATE_4D = 0x44, 2806 REPLAY_STATE_4B_LOCKED = 0x4A, 2807 REPLAY_STATE_4C_UNLOCKED = 0x4B, 2808 REPLAY_STATE_5 = 0x50, 2809 REPLAY_STATE_5A = 0x51, 2810 REPLAY_STATE_5B = 0x52, 2811 REPLAY_STATE_5A_LOCKED = 0x5A, 2812 REPLAY_STATE_5B_UNLOCKED = 0x5B, 2813 REPLAY_STATE_6 = 0x60, 2814 REPLAY_STATE_6A = 0x61, 2815 REPLAY_STATE_6B = 0x62, 2816 REPLAY_STATE_INVALID = 0xFF, 2817 }; 2818 2819 /** 2820 * Replay command sub-types. 2821 */ 2822 enum dmub_cmd_replay_type { 2823 /** 2824 * Copy driver-calculated parameters to REPLAY state. 2825 */ 2826 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 2827 /** 2828 * Enable REPLAY. 2829 */ 2830 DMUB_CMD__REPLAY_ENABLE = 1, 2831 /** 2832 * Set Replay power option. 2833 */ 2834 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 2835 /** 2836 * Set coasting vtotal. 2837 */ 2838 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 2839 /** 2840 * Set power opt and coasting vtotal. 2841 */ 2842 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 2843 }; 2844 2845 /** 2846 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2847 */ 2848 struct dmub_cmd_replay_copy_settings_data { 2849 /** 2850 * Flags that can be set by driver to change some replay behaviour. 2851 */ 2852 union replay_debug_flags debug; 2853 2854 /** 2855 * @flags: Flags used to determine feature functionality. 2856 */ 2857 union replay_hw_flags flags; 2858 2859 /** 2860 * DPP HW instance. 2861 */ 2862 uint8_t dpp_inst; 2863 /** 2864 * OTG HW instance. 2865 */ 2866 uint8_t otg_inst; 2867 /** 2868 * DIG FE HW instance. 2869 */ 2870 uint8_t digfe_inst; 2871 /** 2872 * DIG BE HW instance. 2873 */ 2874 uint8_t digbe_inst; 2875 /** 2876 * AUX HW instance. 2877 */ 2878 uint8_t aux_inst; 2879 /** 2880 * Panel Instance. 2881 * Panel isntance to identify which psr_state to use 2882 * Currently the support is only for 0 or 1 2883 */ 2884 uint8_t panel_inst; 2885 /** 2886 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 2887 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 2888 */ 2889 uint8_t pixel_deviation_per_line; 2890 /** 2891 * @max_deviation_line: The max number of deviation line that can keep the timing 2892 * synchronized between the Source and Sink during Replay normal sleep mode. 2893 */ 2894 uint8_t max_deviation_line; 2895 /** 2896 * Length of each horizontal line in ns. 2897 */ 2898 uint32_t line_time_in_ns; 2899 /** 2900 * PHY instance. 2901 */ 2902 uint8_t dpphy_inst; 2903 /** 2904 * Determines if SMU optimzations are enabled/disabled. 2905 */ 2906 uint8_t smu_optimizations_en; 2907 /** 2908 * Determines if timing sync are enabled/disabled. 2909 */ 2910 uint8_t replay_timing_sync_supported; 2911 /* 2912 * Use FSM state for Replay power up/down 2913 */ 2914 uint8_t use_phy_fsm; 2915 }; 2916 2917 /** 2918 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2919 */ 2920 struct dmub_rb_cmd_replay_copy_settings { 2921 /** 2922 * Command header. 2923 */ 2924 struct dmub_cmd_header header; 2925 /** 2926 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2927 */ 2928 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 2929 }; 2930 2931 /** 2932 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 2933 */ 2934 enum replay_enable { 2935 /** 2936 * Disable REPLAY. 2937 */ 2938 REPLAY_DISABLE = 0, 2939 /** 2940 * Enable REPLAY. 2941 */ 2942 REPLAY_ENABLE = 1, 2943 }; 2944 2945 /** 2946 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 2947 */ 2948 struct dmub_rb_cmd_replay_enable_data { 2949 /** 2950 * Replay enable or disable. 2951 */ 2952 uint8_t enable; 2953 /** 2954 * Panel Instance. 2955 * Panel isntance to identify which replay_state to use 2956 * Currently the support is only for 0 or 1 2957 */ 2958 uint8_t panel_inst; 2959 /** 2960 * Phy state to enter. 2961 * Values to use are defined in dmub_phy_fsm_state 2962 */ 2963 uint8_t phy_fsm_state; 2964 /** 2965 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2966 * Set this using enum phy_link_rate. 2967 * This does not support HDMI/DP2 for now. 2968 */ 2969 uint8_t phy_rate; 2970 }; 2971 2972 /** 2973 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 2974 * Replay enable/disable is controlled using action in data. 2975 */ 2976 struct dmub_rb_cmd_replay_enable { 2977 /** 2978 * Command header. 2979 */ 2980 struct dmub_cmd_header header; 2981 2982 struct dmub_rb_cmd_replay_enable_data data; 2983 }; 2984 2985 /** 2986 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 2987 */ 2988 struct dmub_cmd_replay_set_power_opt_data { 2989 /** 2990 * Panel Instance. 2991 * Panel isntance to identify which replay_state to use 2992 * Currently the support is only for 0 or 1 2993 */ 2994 uint8_t panel_inst; 2995 /** 2996 * Explicit padding to 4 byte boundary. 2997 */ 2998 uint8_t pad[3]; 2999 /** 3000 * REPLAY power option 3001 */ 3002 uint32_t power_opt; 3003 }; 3004 3005 /** 3006 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3007 */ 3008 struct dmub_rb_cmd_replay_set_power_opt { 3009 /** 3010 * Command header. 3011 */ 3012 struct dmub_cmd_header header; 3013 /** 3014 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3015 */ 3016 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3017 }; 3018 3019 /** 3020 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3021 */ 3022 struct dmub_cmd_replay_set_coasting_vtotal_data { 3023 /** 3024 * 16-bit value dicated by driver that indicates the coasting vtotal. 3025 */ 3026 uint16_t coasting_vtotal; 3027 /** 3028 * REPLAY control version. 3029 */ 3030 uint8_t cmd_version; 3031 /** 3032 * Panel Instance. 3033 * Panel isntance to identify which replay_state to use 3034 * Currently the support is only for 0 or 1 3035 */ 3036 uint8_t panel_inst; 3037 }; 3038 3039 /** 3040 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3041 */ 3042 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3043 /** 3044 * Command header. 3045 */ 3046 struct dmub_cmd_header header; 3047 /** 3048 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3049 */ 3050 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3051 }; 3052 3053 /** 3054 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3055 */ 3056 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3057 /** 3058 * Command header. 3059 */ 3060 struct dmub_cmd_header header; 3061 /** 3062 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3063 */ 3064 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3065 /** 3066 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3067 */ 3068 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3069 }; 3070 3071 /** 3072 * Set of HW components that can be locked. 3073 * 3074 * Note: If updating with more HW components, fields 3075 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3076 */ 3077 union dmub_hw_lock_flags { 3078 /** 3079 * Set of HW components that can be locked. 3080 */ 3081 struct { 3082 /** 3083 * Lock/unlock OTG master update lock. 3084 */ 3085 uint8_t lock_pipe : 1; 3086 /** 3087 * Lock/unlock cursor. 3088 */ 3089 uint8_t lock_cursor : 1; 3090 /** 3091 * Lock/unlock global update lock. 3092 */ 3093 uint8_t lock_dig : 1; 3094 /** 3095 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3096 */ 3097 uint8_t triple_buffer_lock : 1; 3098 } bits; 3099 3100 /** 3101 * Union for HW Lock flags. 3102 */ 3103 uint8_t u8All; 3104 }; 3105 3106 /** 3107 * Instances of HW to be locked. 3108 * 3109 * Note: If updating with more HW components, fields 3110 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3111 */ 3112 struct dmub_hw_lock_inst_flags { 3113 /** 3114 * OTG HW instance for OTG master update lock. 3115 */ 3116 uint8_t otg_inst; 3117 /** 3118 * OPP instance for cursor lock. 3119 */ 3120 uint8_t opp_inst; 3121 /** 3122 * OTG HW instance for global update lock. 3123 * TODO: Remove, and re-use otg_inst. 3124 */ 3125 uint8_t dig_inst; 3126 /** 3127 * Explicit pad to 4 byte boundary. 3128 */ 3129 uint8_t pad; 3130 }; 3131 3132 /** 3133 * Clients that can acquire the HW Lock Manager. 3134 * 3135 * Note: If updating with more clients, fields in 3136 * dmub_inbox0_cmd_lock_hw must be updated to match. 3137 */ 3138 enum hw_lock_client { 3139 /** 3140 * Driver is the client of HW Lock Manager. 3141 */ 3142 HW_LOCK_CLIENT_DRIVER = 0, 3143 /** 3144 * PSR SU is the client of HW Lock Manager. 3145 */ 3146 HW_LOCK_CLIENT_PSR_SU = 1, 3147 HW_LOCK_CLIENT_SUBVP = 3, 3148 /** 3149 * Replay is the client of HW Lock Manager. 3150 */ 3151 HW_LOCK_CLIENT_REPLAY = 4, 3152 /** 3153 * Invalid client. 3154 */ 3155 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3156 }; 3157 3158 /** 3159 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3160 */ 3161 struct dmub_cmd_lock_hw_data { 3162 /** 3163 * Specifies the client accessing HW Lock Manager. 3164 */ 3165 enum hw_lock_client client; 3166 /** 3167 * HW instances to be locked. 3168 */ 3169 struct dmub_hw_lock_inst_flags inst_flags; 3170 /** 3171 * Which components to be locked. 3172 */ 3173 union dmub_hw_lock_flags hw_locks; 3174 /** 3175 * Specifies lock/unlock. 3176 */ 3177 uint8_t lock; 3178 /** 3179 * HW can be unlocked separately from releasing the HW Lock Mgr. 3180 * This flag is set if the client wishes to release the object. 3181 */ 3182 uint8_t should_release; 3183 /** 3184 * Explicit padding to 4 byte boundary. 3185 */ 3186 uint8_t pad; 3187 }; 3188 3189 /** 3190 * Definition of a DMUB_CMD__HW_LOCK command. 3191 * Command is used by driver and FW. 3192 */ 3193 struct dmub_rb_cmd_lock_hw { 3194 /** 3195 * Command header. 3196 */ 3197 struct dmub_cmd_header header; 3198 /** 3199 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3200 */ 3201 struct dmub_cmd_lock_hw_data lock_hw_data; 3202 }; 3203 3204 /** 3205 * ABM command sub-types. 3206 */ 3207 enum dmub_cmd_abm_type { 3208 /** 3209 * Initialize parameters for ABM algorithm. 3210 * Data is passed through an indirect buffer. 3211 */ 3212 DMUB_CMD__ABM_INIT_CONFIG = 0, 3213 /** 3214 * Set OTG and panel HW instance. 3215 */ 3216 DMUB_CMD__ABM_SET_PIPE = 1, 3217 /** 3218 * Set user requested backklight level. 3219 */ 3220 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3221 /** 3222 * Set ABM operating/aggression level. 3223 */ 3224 DMUB_CMD__ABM_SET_LEVEL = 3, 3225 /** 3226 * Set ambient light level. 3227 */ 3228 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 3229 /** 3230 * Enable/disable fractional duty cycle for backlight PWM. 3231 */ 3232 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 3233 3234 /** 3235 * unregister vertical interrupt after steady state is reached 3236 */ 3237 DMUB_CMD__ABM_PAUSE = 6, 3238 3239 /** 3240 * Save and Restore ABM state. On save we save parameters, and 3241 * on restore we update state with passed in data. 3242 */ 3243 DMUB_CMD__ABM_SAVE_RESTORE = 7, 3244 }; 3245 3246 /** 3247 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 3248 * Requirements: 3249 * - Padded explicitly to 32-bit boundary. 3250 * - Must ensure this structure matches the one on driver-side, 3251 * otherwise it won't be aligned. 3252 */ 3253 struct abm_config_table { 3254 /** 3255 * Gamma curve thresholds, used for crgb conversion. 3256 */ 3257 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 3258 /** 3259 * Gamma curve offsets, used for crgb conversion. 3260 */ 3261 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 3262 /** 3263 * Gamma curve slopes, used for crgb conversion. 3264 */ 3265 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 3266 /** 3267 * Custom backlight curve thresholds. 3268 */ 3269 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 3270 /** 3271 * Custom backlight curve offsets. 3272 */ 3273 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 3274 /** 3275 * Ambient light thresholds. 3276 */ 3277 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 3278 /** 3279 * Minimum programmable backlight. 3280 */ 3281 uint16_t min_abm_backlight; // 122B 3282 /** 3283 * Minimum reduction values. 3284 */ 3285 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 3286 /** 3287 * Maximum reduction values. 3288 */ 3289 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 3290 /** 3291 * Bright positive gain. 3292 */ 3293 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 3294 /** 3295 * Dark negative gain. 3296 */ 3297 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 3298 /** 3299 * Hybrid factor. 3300 */ 3301 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 3302 /** 3303 * Contrast factor. 3304 */ 3305 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 3306 /** 3307 * Deviation gain. 3308 */ 3309 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 3310 /** 3311 * Minimum knee. 3312 */ 3313 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 3314 /** 3315 * Maximum knee. 3316 */ 3317 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 3318 /** 3319 * Unused. 3320 */ 3321 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 3322 /** 3323 * Explicit padding to 4 byte boundary. 3324 */ 3325 uint8_t pad3[3]; // 229B 3326 /** 3327 * Backlight ramp reduction. 3328 */ 3329 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 3330 /** 3331 * Backlight ramp start. 3332 */ 3333 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 3334 }; 3335 3336 /** 3337 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3338 */ 3339 struct dmub_cmd_abm_set_pipe_data { 3340 /** 3341 * OTG HW instance. 3342 */ 3343 uint8_t otg_inst; 3344 3345 /** 3346 * Panel Control HW instance. 3347 */ 3348 uint8_t panel_inst; 3349 3350 /** 3351 * Controls how ABM will interpret a set pipe or set level command. 3352 */ 3353 uint8_t set_pipe_option; 3354 3355 /** 3356 * Unused. 3357 * TODO: Remove. 3358 */ 3359 uint8_t ramping_boundary; 3360 }; 3361 3362 /** 3363 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3364 */ 3365 struct dmub_rb_cmd_abm_set_pipe { 3366 /** 3367 * Command header. 3368 */ 3369 struct dmub_cmd_header header; 3370 3371 /** 3372 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3373 */ 3374 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 3375 }; 3376 3377 /** 3378 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3379 */ 3380 struct dmub_cmd_abm_set_backlight_data { 3381 /** 3382 * Number of frames to ramp to backlight user level. 3383 */ 3384 uint32_t frame_ramp; 3385 3386 /** 3387 * Requested backlight level from user. 3388 */ 3389 uint32_t backlight_user_level; 3390 3391 /** 3392 * ABM control version. 3393 */ 3394 uint8_t version; 3395 3396 /** 3397 * Panel Control HW instance mask. 3398 * Bit 0 is Panel Control HW instance 0. 3399 * Bit 1 is Panel Control HW instance 1. 3400 */ 3401 uint8_t panel_mask; 3402 3403 /** 3404 * Explicit padding to 4 byte boundary. 3405 */ 3406 uint8_t pad[2]; 3407 }; 3408 3409 /** 3410 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3411 */ 3412 struct dmub_rb_cmd_abm_set_backlight { 3413 /** 3414 * Command header. 3415 */ 3416 struct dmub_cmd_header header; 3417 3418 /** 3419 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3420 */ 3421 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 3422 }; 3423 3424 /** 3425 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3426 */ 3427 struct dmub_cmd_abm_set_level_data { 3428 /** 3429 * Set current ABM operating/aggression level. 3430 */ 3431 uint32_t level; 3432 3433 /** 3434 * ABM control version. 3435 */ 3436 uint8_t version; 3437 3438 /** 3439 * Panel Control HW instance mask. 3440 * Bit 0 is Panel Control HW instance 0. 3441 * Bit 1 is Panel Control HW instance 1. 3442 */ 3443 uint8_t panel_mask; 3444 3445 /** 3446 * Explicit padding to 4 byte boundary. 3447 */ 3448 uint8_t pad[2]; 3449 }; 3450 3451 /** 3452 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3453 */ 3454 struct dmub_rb_cmd_abm_set_level { 3455 /** 3456 * Command header. 3457 */ 3458 struct dmub_cmd_header header; 3459 3460 /** 3461 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3462 */ 3463 struct dmub_cmd_abm_set_level_data abm_set_level_data; 3464 }; 3465 3466 /** 3467 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3468 */ 3469 struct dmub_cmd_abm_set_ambient_level_data { 3470 /** 3471 * Ambient light sensor reading from OS. 3472 */ 3473 uint32_t ambient_lux; 3474 3475 /** 3476 * ABM control version. 3477 */ 3478 uint8_t version; 3479 3480 /** 3481 * Panel Control HW instance mask. 3482 * Bit 0 is Panel Control HW instance 0. 3483 * Bit 1 is Panel Control HW instance 1. 3484 */ 3485 uint8_t panel_mask; 3486 3487 /** 3488 * Explicit padding to 4 byte boundary. 3489 */ 3490 uint8_t pad[2]; 3491 }; 3492 3493 /** 3494 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3495 */ 3496 struct dmub_rb_cmd_abm_set_ambient_level { 3497 /** 3498 * Command header. 3499 */ 3500 struct dmub_cmd_header header; 3501 3502 /** 3503 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3504 */ 3505 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 3506 }; 3507 3508 /** 3509 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3510 */ 3511 struct dmub_cmd_abm_set_pwm_frac_data { 3512 /** 3513 * Enable/disable fractional duty cycle for backlight PWM. 3514 * TODO: Convert to uint8_t. 3515 */ 3516 uint32_t fractional_pwm; 3517 3518 /** 3519 * ABM control version. 3520 */ 3521 uint8_t version; 3522 3523 /** 3524 * Panel Control HW instance mask. 3525 * Bit 0 is Panel Control HW instance 0. 3526 * Bit 1 is Panel Control HW instance 1. 3527 */ 3528 uint8_t panel_mask; 3529 3530 /** 3531 * Explicit padding to 4 byte boundary. 3532 */ 3533 uint8_t pad[2]; 3534 }; 3535 3536 /** 3537 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3538 */ 3539 struct dmub_rb_cmd_abm_set_pwm_frac { 3540 /** 3541 * Command header. 3542 */ 3543 struct dmub_cmd_header header; 3544 3545 /** 3546 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3547 */ 3548 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 3549 }; 3550 3551 /** 3552 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3553 */ 3554 struct dmub_cmd_abm_init_config_data { 3555 /** 3556 * Location of indirect buffer used to pass init data to ABM. 3557 */ 3558 union dmub_addr src; 3559 3560 /** 3561 * Indirect buffer length. 3562 */ 3563 uint16_t bytes; 3564 3565 3566 /** 3567 * ABM control version. 3568 */ 3569 uint8_t version; 3570 3571 /** 3572 * Panel Control HW instance mask. 3573 * Bit 0 is Panel Control HW instance 0. 3574 * Bit 1 is Panel Control HW instance 1. 3575 */ 3576 uint8_t panel_mask; 3577 3578 /** 3579 * Explicit padding to 4 byte boundary. 3580 */ 3581 uint8_t pad[2]; 3582 }; 3583 3584 /** 3585 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3586 */ 3587 struct dmub_rb_cmd_abm_init_config { 3588 /** 3589 * Command header. 3590 */ 3591 struct dmub_cmd_header header; 3592 3593 /** 3594 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3595 */ 3596 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3597 }; 3598 3599 /** 3600 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3601 */ 3602 3603 struct dmub_cmd_abm_pause_data { 3604 3605 /** 3606 * Panel Control HW instance mask. 3607 * Bit 0 is Panel Control HW instance 0. 3608 * Bit 1 is Panel Control HW instance 1. 3609 */ 3610 uint8_t panel_mask; 3611 3612 /** 3613 * OTG hw instance 3614 */ 3615 uint8_t otg_inst; 3616 3617 /** 3618 * Enable or disable ABM pause 3619 */ 3620 uint8_t enable; 3621 3622 /** 3623 * Explicit padding to 4 byte boundary. 3624 */ 3625 uint8_t pad[1]; 3626 }; 3627 3628 /** 3629 * Definition of a DMUB_CMD__ABM_PAUSE command. 3630 */ 3631 struct dmub_rb_cmd_abm_pause { 3632 /** 3633 * Command header. 3634 */ 3635 struct dmub_cmd_header header; 3636 3637 /** 3638 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3639 */ 3640 struct dmub_cmd_abm_pause_data abm_pause_data; 3641 }; 3642 3643 /** 3644 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 3645 */ 3646 struct dmub_rb_cmd_abm_save_restore { 3647 /** 3648 * Command header. 3649 */ 3650 struct dmub_cmd_header header; 3651 3652 /** 3653 * OTG hw instance 3654 */ 3655 uint8_t otg_inst; 3656 3657 /** 3658 * Enable or disable ABM pause 3659 */ 3660 uint8_t freeze; 3661 3662 /** 3663 * Explicit padding to 4 byte boundary. 3664 */ 3665 uint8_t debug; 3666 3667 /** 3668 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3669 */ 3670 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3671 }; 3672 3673 /** 3674 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3675 */ 3676 struct dmub_cmd_query_feature_caps_data { 3677 /** 3678 * DMUB feature capabilities. 3679 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3680 */ 3681 struct dmub_feature_caps feature_caps; 3682 }; 3683 3684 /** 3685 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3686 */ 3687 struct dmub_rb_cmd_query_feature_caps { 3688 /** 3689 * Command header. 3690 */ 3691 struct dmub_cmd_header header; 3692 /** 3693 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3694 */ 3695 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3696 }; 3697 3698 /** 3699 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3700 */ 3701 struct dmub_cmd_visual_confirm_color_data { 3702 /** 3703 * DMUB visual confirm color 3704 */ 3705 struct dmub_visual_confirm_color visual_confirm_color; 3706 }; 3707 3708 /** 3709 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3710 */ 3711 struct dmub_rb_cmd_get_visual_confirm_color { 3712 /** 3713 * Command header. 3714 */ 3715 struct dmub_cmd_header header; 3716 /** 3717 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3718 */ 3719 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3720 }; 3721 3722 /** 3723 * enum dmub_cmd_panel_cntl_type - Panel control command. 3724 */ 3725 enum dmub_cmd_panel_cntl_type { 3726 /** 3727 * Initializes embedded panel hardware blocks. 3728 */ 3729 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3730 /** 3731 * Queries backlight info for the embedded panel. 3732 */ 3733 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3734 }; 3735 3736 /** 3737 * struct dmub_cmd_panel_cntl_data - Panel control data. 3738 */ 3739 struct dmub_cmd_panel_cntl_data { 3740 uint32_t inst; /**< panel instance */ 3741 uint32_t current_backlight; /* in/out */ 3742 uint32_t bl_pwm_cntl; /* in/out */ 3743 uint32_t bl_pwm_period_cntl; /* in/out */ 3744 uint32_t bl_pwm_ref_div1; /* in/out */ 3745 uint8_t is_backlight_on : 1; /* in/out */ 3746 uint8_t is_powered_on : 1; /* in/out */ 3747 uint8_t padding[3]; 3748 uint32_t bl_pwm_ref_div2; /* in/out */ 3749 uint8_t reserved[4]; 3750 }; 3751 3752 /** 3753 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3754 */ 3755 struct dmub_rb_cmd_panel_cntl { 3756 struct dmub_cmd_header header; /**< header */ 3757 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3758 }; 3759 3760 struct dmub_optc_state { 3761 uint32_t v_total_max; 3762 uint32_t v_total_min; 3763 uint32_t tg_inst; 3764 }; 3765 3766 struct dmub_rb_cmd_drr_update { 3767 struct dmub_cmd_header header; 3768 struct dmub_optc_state dmub_optc_state_req; 3769 }; 3770 3771 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3772 uint32_t pix_clk_100hz; 3773 uint8_t max_ramp_step; 3774 uint8_t pipes; 3775 uint8_t min_refresh_in_hz; 3776 uint8_t pipe_count; 3777 uint8_t pipe_index[4]; 3778 }; 3779 3780 struct dmub_cmd_fw_assisted_mclk_switch_config { 3781 uint8_t fams_enabled; 3782 uint8_t visual_confirm_enabled; 3783 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3784 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3785 }; 3786 3787 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3788 struct dmub_cmd_header header; 3789 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3790 }; 3791 3792 /** 3793 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3794 */ 3795 struct dmub_cmd_lvtma_control_data { 3796 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3797 uint8_t bypass_panel_control_wait; 3798 uint8_t reserved_0[2]; /**< For future use */ 3799 uint8_t panel_inst; /**< LVTMA control instance */ 3800 uint8_t reserved_1[3]; /**< For future use */ 3801 }; 3802 3803 /** 3804 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3805 */ 3806 struct dmub_rb_cmd_lvtma_control { 3807 /** 3808 * Command header. 3809 */ 3810 struct dmub_cmd_header header; 3811 /** 3812 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3813 */ 3814 struct dmub_cmd_lvtma_control_data data; 3815 }; 3816 3817 /** 3818 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3819 */ 3820 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3821 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3822 uint8_t is_usb; /**< is phy is usb */ 3823 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3824 uint8_t is_dp4; /**< is dp in 4 lane */ 3825 }; 3826 3827 /** 3828 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3829 */ 3830 struct dmub_rb_cmd_transmitter_query_dp_alt { 3831 struct dmub_cmd_header header; /**< header */ 3832 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3833 }; 3834 3835 /** 3836 * Maximum number of bytes a chunk sent to DMUB for parsing 3837 */ 3838 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3839 3840 /** 3841 * Represent a chunk of CEA blocks sent to DMUB for parsing 3842 */ 3843 struct dmub_cmd_send_edid_cea { 3844 uint16_t offset; /**< offset into the CEA block */ 3845 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3846 uint16_t cea_total_length; /**< total length of the CEA block */ 3847 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3848 uint8_t pad[3]; /**< padding and for future expansion */ 3849 }; 3850 3851 /** 3852 * Result of VSDB parsing from CEA block 3853 */ 3854 struct dmub_cmd_edid_cea_amd_vsdb { 3855 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3856 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3857 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3858 uint16_t min_frame_rate; /**< Maximum frame rate */ 3859 uint16_t max_frame_rate; /**< Minimum frame rate */ 3860 }; 3861 3862 /** 3863 * Result of sending a CEA chunk 3864 */ 3865 struct dmub_cmd_edid_cea_ack { 3866 uint16_t offset; /**< offset of the chunk into the CEA block */ 3867 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3868 uint8_t pad; /**< padding and for future expansion */ 3869 }; 3870 3871 /** 3872 * Specify whether the result is an ACK/NACK or the parsing has finished 3873 */ 3874 enum dmub_cmd_edid_cea_reply_type { 3875 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3876 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3877 }; 3878 3879 /** 3880 * Definition of a DMUB_CMD__EDID_CEA command. 3881 */ 3882 struct dmub_rb_cmd_edid_cea { 3883 struct dmub_cmd_header header; /**< Command header */ 3884 union dmub_cmd_edid_cea_data { 3885 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3886 struct dmub_cmd_edid_cea_output { /**< output with results */ 3887 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3888 union { 3889 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3890 struct dmub_cmd_edid_cea_ack ack; 3891 }; 3892 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3893 } data; /**< Command data */ 3894 3895 }; 3896 3897 /** 3898 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3899 */ 3900 struct dmub_cmd_cable_id_input { 3901 uint8_t phy_inst; /**< phy inst for cable id data */ 3902 }; 3903 3904 /** 3905 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3906 */ 3907 struct dmub_cmd_cable_id_output { 3908 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3909 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3910 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3911 uint8_t RESERVED :2; /**< reserved means not defined */ 3912 }; 3913 3914 /** 3915 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3916 */ 3917 struct dmub_rb_cmd_get_usbc_cable_id { 3918 struct dmub_cmd_header header; /**< Command header */ 3919 /** 3920 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3921 */ 3922 union dmub_cmd_cable_id_data { 3923 struct dmub_cmd_cable_id_input input; /**< Input */ 3924 struct dmub_cmd_cable_id_output output; /**< Output */ 3925 uint8_t output_raw; /**< Raw data output */ 3926 } data; 3927 }; 3928 3929 /** 3930 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3931 */ 3932 enum dmub_cmd_secure_display_type { 3933 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3934 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3935 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3936 }; 3937 3938 /** 3939 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3940 */ 3941 struct dmub_rb_cmd_secure_display { 3942 struct dmub_cmd_header header; 3943 /** 3944 * Data passed from driver to dmub firmware. 3945 */ 3946 struct dmub_cmd_roi_info { 3947 uint16_t x_start; 3948 uint16_t x_end; 3949 uint16_t y_start; 3950 uint16_t y_end; 3951 uint8_t otg_id; 3952 uint8_t phy_id; 3953 } roi_info; 3954 }; 3955 3956 /** 3957 * union dmub_rb_cmd - DMUB inbox command. 3958 */ 3959 union dmub_rb_cmd { 3960 /** 3961 * Elements shared with all commands. 3962 */ 3963 struct dmub_rb_cmd_common cmd_common; 3964 /** 3965 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3966 */ 3967 struct dmub_rb_cmd_read_modify_write read_modify_write; 3968 /** 3969 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3970 */ 3971 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3972 /** 3973 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3974 */ 3975 struct dmub_rb_cmd_burst_write burst_write; 3976 /** 3977 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3978 */ 3979 struct dmub_rb_cmd_reg_wait reg_wait; 3980 /** 3981 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3982 */ 3983 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3984 /** 3985 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3986 */ 3987 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3988 /** 3989 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3990 */ 3991 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3992 /** 3993 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3994 */ 3995 struct dmub_rb_cmd_dpphy_init dpphy_init; 3996 /** 3997 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3998 */ 3999 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 4000 /** 4001 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 4002 */ 4003 struct dmub_rb_cmd_domain_control domain_control; 4004 /** 4005 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 4006 */ 4007 struct dmub_rb_cmd_psr_set_version psr_set_version; 4008 /** 4009 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 4010 */ 4011 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 4012 /** 4013 * Definition of a DMUB_CMD__PSR_ENABLE command. 4014 */ 4015 struct dmub_rb_cmd_psr_enable psr_enable; 4016 /** 4017 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 4018 */ 4019 struct dmub_rb_cmd_psr_set_level psr_set_level; 4020 /** 4021 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 4022 */ 4023 struct dmub_rb_cmd_psr_force_static psr_force_static; 4024 /** 4025 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 4026 */ 4027 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 4028 /** 4029 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4030 */ 4031 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 4032 /** 4033 * Definition of a DMUB_CMD__HW_LOCK command. 4034 * Command is used by driver and FW. 4035 */ 4036 struct dmub_rb_cmd_lock_hw lock_hw; 4037 /** 4038 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4039 */ 4040 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 4041 /** 4042 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4043 */ 4044 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 4045 /** 4046 * Definition of a DMUB_CMD__PLAT_54186_WA command. 4047 */ 4048 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 4049 /** 4050 * Definition of a DMUB_CMD__MALL command. 4051 */ 4052 struct dmub_rb_cmd_mall mall; 4053 4054 /** 4055 * Definition of a DMUB_CMD__CAB command. 4056 */ 4057 struct dmub_rb_cmd_cab_for_ss cab; 4058 4059 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 4060 4061 /** 4062 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 4063 */ 4064 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 4065 4066 /** 4067 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 4068 */ 4069 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 4070 4071 /** 4072 * Definition of DMUB_CMD__PANEL_CNTL commands. 4073 */ 4074 struct dmub_rb_cmd_panel_cntl panel_cntl; 4075 4076 /** 4077 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4078 */ 4079 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 4080 4081 /** 4082 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4083 */ 4084 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 4085 4086 /** 4087 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4088 */ 4089 struct dmub_rb_cmd_abm_set_level abm_set_level; 4090 4091 /** 4092 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4093 */ 4094 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 4095 4096 /** 4097 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4098 */ 4099 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 4100 4101 /** 4102 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4103 */ 4104 struct dmub_rb_cmd_abm_init_config abm_init_config; 4105 4106 /** 4107 * Definition of a DMUB_CMD__ABM_PAUSE command. 4108 */ 4109 struct dmub_rb_cmd_abm_pause abm_pause; 4110 4111 /** 4112 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4113 */ 4114 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 4115 4116 /** 4117 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 4118 */ 4119 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 4120 4121 /** 4122 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 4123 */ 4124 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 4125 4126 /** 4127 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4128 */ 4129 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 4130 4131 /** 4132 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4133 */ 4134 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 4135 struct dmub_rb_cmd_drr_update drr_update; 4136 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 4137 4138 /** 4139 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4140 */ 4141 struct dmub_rb_cmd_lvtma_control lvtma_control; 4142 /** 4143 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4144 */ 4145 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 4146 /** 4147 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 4148 */ 4149 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 4150 /** 4151 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 4152 */ 4153 struct dmub_rb_cmd_set_config_access set_config_access; 4154 /** 4155 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 4156 */ 4157 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 4158 /** 4159 * Definition of a DMUB_CMD__EDID_CEA command. 4160 */ 4161 struct dmub_rb_cmd_edid_cea edid_cea; 4162 /** 4163 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 4164 */ 4165 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 4166 4167 /** 4168 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 4169 */ 4170 struct dmub_rb_cmd_query_hpd_state query_hpd; 4171 /** 4172 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 4173 */ 4174 struct dmub_rb_cmd_secure_display secure_display; 4175 4176 /** 4177 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 4178 */ 4179 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 4180 /** 4181 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 4182 */ 4183 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 4184 /* 4185 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4186 */ 4187 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 4188 /** 4189 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4190 */ 4191 struct dmub_rb_cmd_replay_enable replay_enable; 4192 /** 4193 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4194 */ 4195 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 4196 /** 4197 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4198 */ 4199 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 4200 /** 4201 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4202 */ 4203 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 4204 }; 4205 4206 /** 4207 * union dmub_rb_out_cmd - Outbox command 4208 */ 4209 union dmub_rb_out_cmd { 4210 /** 4211 * Parameters common to every command. 4212 */ 4213 struct dmub_rb_cmd_common cmd_common; 4214 /** 4215 * AUX reply command. 4216 */ 4217 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 4218 /** 4219 * HPD notify command. 4220 */ 4221 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 4222 /** 4223 * SET_CONFIG reply command. 4224 */ 4225 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 4226 /** 4227 * DPIA notification command. 4228 */ 4229 struct dmub_rb_cmd_dpia_notification dpia_notification; 4230 }; 4231 #pragma pack(pop) 4232 4233 4234 //============================================================================== 4235 //</DMUB_CMD>=================================================================== 4236 //============================================================================== 4237 //< DMUB_RB>==================================================================== 4238 //============================================================================== 4239 4240 #if defined(__cplusplus) 4241 extern "C" { 4242 #endif 4243 4244 /** 4245 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 4246 */ 4247 struct dmub_rb_init_params { 4248 void *ctx; /**< Caller provided context pointer */ 4249 void *base_address; /**< CPU base address for ring's data */ 4250 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4251 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 4252 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 4253 }; 4254 4255 /** 4256 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 4257 */ 4258 struct dmub_rb { 4259 void *base_address; /**< CPU address for the ring's data */ 4260 uint32_t rptr; /**< Read pointer for consumer in bytes */ 4261 uint32_t wrpt; /**< Write pointer for producer in bytes */ 4262 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4263 4264 void *ctx; /**< Caller provided context pointer */ 4265 void *dmub; /**< Pointer to the DMUB interface */ 4266 }; 4267 4268 /** 4269 * @brief Checks if the ringbuffer is empty. 4270 * 4271 * @param rb DMUB Ringbuffer 4272 * @return true if empty 4273 * @return false otherwise 4274 */ 4275 static inline bool dmub_rb_empty(struct dmub_rb *rb) 4276 { 4277 return (rb->wrpt == rb->rptr); 4278 } 4279 4280 /** 4281 * @brief Checks if the ringbuffer is full 4282 * 4283 * @param rb DMUB Ringbuffer 4284 * @return true if full 4285 * @return false otherwise 4286 */ 4287 static inline bool dmub_rb_full(struct dmub_rb *rb) 4288 { 4289 uint32_t data_count; 4290 4291 if (rb->wrpt >= rb->rptr) 4292 data_count = rb->wrpt - rb->rptr; 4293 else 4294 data_count = rb->capacity - (rb->rptr - rb->wrpt); 4295 4296 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 4297 } 4298 4299 /** 4300 * @brief Pushes a command into the ringbuffer 4301 * 4302 * @param rb DMUB ringbuffer 4303 * @param cmd The command to push 4304 * @return true if the ringbuffer was not full 4305 * @return false otherwise 4306 */ 4307 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 4308 const union dmub_rb_cmd *cmd) 4309 { 4310 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 4311 const uint64_t *src = (const uint64_t *)cmd; 4312 uint8_t i; 4313 4314 if (dmub_rb_full(rb)) 4315 return false; 4316 4317 // copying data 4318 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4319 *dst++ = *src++; 4320 4321 rb->wrpt += DMUB_RB_CMD_SIZE; 4322 4323 if (rb->wrpt >= rb->capacity) 4324 rb->wrpt %= rb->capacity; 4325 4326 return true; 4327 } 4328 4329 /** 4330 * @brief Pushes a command into the DMUB outbox ringbuffer 4331 * 4332 * @param rb DMUB outbox ringbuffer 4333 * @param cmd Outbox command 4334 * @return true if not full 4335 * @return false otherwise 4336 */ 4337 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 4338 const union dmub_rb_out_cmd *cmd) 4339 { 4340 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 4341 const uint8_t *src = (const uint8_t *)cmd; 4342 4343 if (dmub_rb_full(rb)) 4344 return false; 4345 4346 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 4347 4348 rb->wrpt += DMUB_RB_CMD_SIZE; 4349 4350 if (rb->wrpt >= rb->capacity) 4351 rb->wrpt %= rb->capacity; 4352 4353 return true; 4354 } 4355 4356 /** 4357 * @brief Returns the next unprocessed command in the ringbuffer. 4358 * 4359 * @param rb DMUB ringbuffer 4360 * @param cmd The command to return 4361 * @return true if not empty 4362 * @return false otherwise 4363 */ 4364 static inline bool dmub_rb_front(struct dmub_rb *rb, 4365 union dmub_rb_cmd **cmd) 4366 { 4367 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 4368 4369 if (dmub_rb_empty(rb)) 4370 return false; 4371 4372 *cmd = (union dmub_rb_cmd *)rb_cmd; 4373 4374 return true; 4375 } 4376 4377 /** 4378 * @brief Determines the next ringbuffer offset. 4379 * 4380 * @param rb DMUB inbox ringbuffer 4381 * @param num_cmds Number of commands 4382 * @param next_rptr The next offset in the ringbuffer 4383 */ 4384 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 4385 uint32_t num_cmds, 4386 uint32_t *next_rptr) 4387 { 4388 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 4389 4390 if (*next_rptr >= rb->capacity) 4391 *next_rptr %= rb->capacity; 4392 } 4393 4394 /** 4395 * @brief Returns a pointer to a command in the inbox. 4396 * 4397 * @param rb DMUB inbox ringbuffer 4398 * @param cmd The inbox command to return 4399 * @param rptr The ringbuffer offset 4400 * @return true if not empty 4401 * @return false otherwise 4402 */ 4403 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 4404 union dmub_rb_cmd **cmd, 4405 uint32_t rptr) 4406 { 4407 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 4408 4409 if (dmub_rb_empty(rb)) 4410 return false; 4411 4412 *cmd = (union dmub_rb_cmd *)rb_cmd; 4413 4414 return true; 4415 } 4416 4417 /** 4418 * @brief Returns the next unprocessed command in the outbox. 4419 * 4420 * @param rb DMUB outbox ringbuffer 4421 * @param cmd The outbox command to return 4422 * @return true if not empty 4423 * @return false otherwise 4424 */ 4425 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 4426 union dmub_rb_out_cmd *cmd) 4427 { 4428 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 4429 uint64_t *dst = (uint64_t *)cmd; 4430 uint8_t i; 4431 4432 if (dmub_rb_empty(rb)) 4433 return false; 4434 4435 // copying data 4436 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4437 *dst++ = *src++; 4438 4439 return true; 4440 } 4441 4442 /** 4443 * @brief Removes the front entry in the ringbuffer. 4444 * 4445 * @param rb DMUB ringbuffer 4446 * @return true if the command was removed 4447 * @return false if there were no commands 4448 */ 4449 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 4450 { 4451 if (dmub_rb_empty(rb)) 4452 return false; 4453 4454 rb->rptr += DMUB_RB_CMD_SIZE; 4455 4456 if (rb->rptr >= rb->capacity) 4457 rb->rptr %= rb->capacity; 4458 4459 return true; 4460 } 4461 4462 /** 4463 * @brief Flushes commands in the ringbuffer to framebuffer memory. 4464 * 4465 * Avoids a race condition where DMCUB accesses memory while 4466 * there are still writes in flight to framebuffer. 4467 * 4468 * @param rb DMUB ringbuffer 4469 */ 4470 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 4471 { 4472 uint32_t rptr = rb->rptr; 4473 uint32_t wptr = rb->wrpt; 4474 4475 while (rptr != wptr) { 4476 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 4477 uint8_t i; 4478 4479 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4480 (void)READ_ONCE(*data++); 4481 4482 rptr += DMUB_RB_CMD_SIZE; 4483 if (rptr >= rb->capacity) 4484 rptr %= rb->capacity; 4485 } 4486 } 4487 4488 /** 4489 * @brief Initializes a DMCUB ringbuffer 4490 * 4491 * @param rb DMUB ringbuffer 4492 * @param init_params initial configuration for the ringbuffer 4493 */ 4494 static inline void dmub_rb_init(struct dmub_rb *rb, 4495 struct dmub_rb_init_params *init_params) 4496 { 4497 rb->base_address = init_params->base_address; 4498 rb->capacity = init_params->capacity; 4499 rb->rptr = init_params->read_ptr; 4500 rb->wrpt = init_params->write_ptr; 4501 } 4502 4503 /** 4504 * @brief Copies output data from in/out commands into the given command. 4505 * 4506 * @param rb DMUB ringbuffer 4507 * @param cmd Command to copy data into 4508 */ 4509 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 4510 union dmub_rb_cmd *cmd) 4511 { 4512 // Copy rb entry back into command 4513 uint8_t *rd_ptr = (rb->rptr == 0) ? 4514 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 4515 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 4516 4517 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 4518 } 4519 4520 #if defined(__cplusplus) 4521 } 4522 #endif 4523 4524 //============================================================================== 4525 //</DMUB_RB>==================================================================== 4526 //============================================================================== 4527 #endif /* _DMUB_CMD_H_ */ 4528