1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic udelay 165 */ 166 #ifndef dmub_udelay 167 #define dmub_udelay(microseconds) udelay(microseconds) 168 #endif 169 170 #pragma pack(push, 1) 171 #define ABM_NUM_OF_ACE_SEGMENTS 5 172 173 /** 174 * Debug FW state offset 175 */ 176 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 177 178 union abm_flags { 179 struct { 180 /** 181 * @abm_enabled: Indicates if ABM is enabled. 182 */ 183 unsigned int abm_enabled : 1; 184 185 /** 186 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 187 */ 188 unsigned int disable_abm_requested : 1; 189 190 /** 191 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 192 */ 193 unsigned int disable_abm_immediately : 1; 194 195 /** 196 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 197 * to be disabled immediately and keep gain. 198 */ 199 unsigned int disable_abm_immediate_keep_gain : 1; 200 201 /** 202 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 203 */ 204 unsigned int fractional_pwm : 1; 205 206 /** 207 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 208 * of user backlight level. 209 */ 210 unsigned int abm_gradual_bl_change : 1; 211 212 /** 213 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 214 */ 215 unsigned int abm_new_frame : 1; 216 217 /** 218 * @vb_scaling_enabled: Indicates variBright Scaling Enable 219 */ 220 unsigned int vb_scaling_enabled : 1; 221 } bitfields; 222 223 unsigned int u32All; 224 }; 225 226 struct abm_save_restore { 227 /** 228 * @flags: Misc. ABM flags. 229 */ 230 union abm_flags flags; 231 232 /** 233 * @pause: true: pause ABM and get state 234 * false: unpause ABM after setting state 235 */ 236 uint32_t pause; 237 238 /** 239 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 240 */ 241 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 242 243 /** 244 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 245 */ 246 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 247 248 /** 249 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 250 */ 251 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 252 253 254 /** 255 * @knee_threshold: Current x-position of ACE knee (u0.16). 256 */ 257 uint32_t knee_threshold; 258 /** 259 * @current_gain: Current backlight reduction (u16.16). 260 */ 261 uint32_t current_gain; 262 /** 263 * @curr_bl_level: Current actual backlight level converging to target backlight level. 264 */ 265 uint16_t curr_bl_level; 266 267 /** 268 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 269 */ 270 uint16_t curr_user_bl_level; 271 272 }; 273 274 /** 275 * union dmub_addr - DMUB physical/virtual 64-bit address. 276 */ 277 union dmub_addr { 278 struct { 279 uint32_t low_part; /**< Lower 32 bits */ 280 uint32_t high_part; /**< Upper 32 bits */ 281 } u; /*<< Low/high bit access */ 282 uint64_t quad_part; /*<< 64 bit address */ 283 }; 284 #pragma pack(pop) 285 286 /** 287 * Dirty rect definition. 288 */ 289 struct dmub_rect { 290 /** 291 * Dirty rect x offset. 292 */ 293 uint32_t x; 294 295 /** 296 * Dirty rect y offset. 297 */ 298 uint32_t y; 299 300 /** 301 * Dirty rect width. 302 */ 303 uint32_t width; 304 305 /** 306 * Dirty rect height. 307 */ 308 uint32_t height; 309 }; 310 311 /** 312 * Flags that can be set by driver to change some PSR behaviour. 313 */ 314 union dmub_psr_debug_flags { 315 /** 316 * Debug flags. 317 */ 318 struct { 319 /** 320 * Enable visual confirm in FW. 321 */ 322 uint32_t visual_confirm : 1; 323 324 /** 325 * Force all selective updates to bw full frame updates. 326 */ 327 uint32_t force_full_frame_update : 1; 328 329 /** 330 * Use HW Lock Mgr object to do HW locking in FW. 331 */ 332 uint32_t use_hw_lock_mgr : 1; 333 334 /** 335 * Use TPS3 signal when restore main link. 336 */ 337 uint32_t force_wakeup_by_tps3 : 1; 338 339 /** 340 * Back to back flip, therefore cannot power down PHY 341 */ 342 uint32_t back_to_back_flip : 1; 343 344 /** 345 * Enable visual confirm for IPS 346 */ 347 uint32_t enable_ips_visual_confirm : 1; 348 } bitfields; 349 350 /** 351 * Union for debug flags. 352 */ 353 uint32_t u32All; 354 }; 355 356 /** 357 * Flags that can be set by driver to change some Replay behaviour. 358 */ 359 union replay_debug_flags { 360 struct { 361 /** 362 * 0x1 (bit 0) 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * 0x2 (bit 1) 369 * @skip_crc: Set if need to skip CRC. 370 */ 371 uint32_t skip_crc : 1; 372 373 /** 374 * 0x4 (bit 2) 375 * @force_link_power_on: Force disable ALPM control 376 */ 377 uint32_t force_link_power_on : 1; 378 379 /** 380 * 0x8 (bit 3) 381 * @force_phy_power_on: Force phy power on 382 */ 383 uint32_t force_phy_power_on : 1; 384 385 /** 386 * 0x10 (bit 4) 387 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 388 */ 389 uint32_t timing_resync_disabled : 1; 390 391 /** 392 * 0x20 (bit 5) 393 * @skip_crtc_disabled: CRTC disable skipped 394 */ 395 uint32_t skip_crtc_disabled : 1; 396 397 /** 398 * 0x40 (bit 6) 399 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 400 */ 401 uint32_t force_defer_one_frame_update : 1; 402 403 /** 404 * 0x80 (bit 7) 405 * @disable_delay_alpm_on: Force disable delay alpm on 406 */ 407 uint32_t disable_delay_alpm_on : 1; 408 409 /** 410 * 0x100 (bit 8) 411 * @disable_desync_error_check: Force disable desync error check 412 */ 413 uint32_t disable_desync_error_check : 1; 414 415 /** 416 * 0x200 (bit 9) 417 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 418 */ 419 uint32_t force_self_update_when_abm_non_steady : 1; 420 421 /** 422 * 0x400 (bit 10) 423 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 424 * If we enter IPS2, the Visual confirm bar will change to yellow 425 */ 426 uint32_t enable_ips_visual_confirm : 1; 427 428 /** 429 * 0x800 (bit 11) 430 * @enable_ips_residency_profiling: Enable IPS residency profiling 431 */ 432 uint32_t enable_ips_residency_profiling : 1; 433 434 uint32_t reserved : 20; 435 } bitfields; 436 437 uint32_t u32All; 438 }; 439 440 union replay_hw_flags { 441 struct { 442 /** 443 * @allow_alpm_fw_standby_mode: To indicate whether the 444 * ALPM FW standby mode is allowed 445 */ 446 uint32_t allow_alpm_fw_standby_mode : 1; 447 448 /* 449 * @dsc_enable_status: DSC enable status in driver 450 */ 451 uint32_t dsc_enable_status : 1; 452 453 /** 454 * @fec_enable_status: receive fec enable/disable status from driver 455 */ 456 uint32_t fec_enable_status : 1; 457 458 /* 459 * @smu_optimizations_en: SMU power optimization. 460 * Only when active display is Replay capable and display enters Replay. 461 * Trigger interrupt to SMU to powerup/down. 462 */ 463 uint32_t smu_optimizations_en : 1; 464 465 /** 466 * @phy_power_state: Indicates current phy power state 467 */ 468 uint32_t phy_power_state : 1; 469 470 /** 471 * @link_power_state: Indicates current link power state 472 */ 473 uint32_t link_power_state : 1; 474 /** 475 * Use TPS3 signal when restore main link. 476 */ 477 uint32_t force_wakeup_by_tps3 : 1; 478 } bitfields; 479 480 uint32_t u32All; 481 }; 482 483 /** 484 * DMUB feature capabilities. 485 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 486 */ 487 struct dmub_feature_caps { 488 /** 489 * Max PSR version supported by FW. 490 */ 491 uint8_t psr; 492 uint8_t fw_assisted_mclk_switch_ver; 493 uint8_t reserved[4]; 494 uint8_t subvp_psr_support; 495 uint8_t gecc_enable; 496 uint8_t replay_supported; 497 uint8_t replay_reserved[3]; 498 }; 499 500 struct dmub_visual_confirm_color { 501 /** 502 * Maximum 10 bits color value 503 */ 504 uint16_t color_r_cr; 505 uint16_t color_g_y; 506 uint16_t color_b_cb; 507 uint16_t panel_inst; 508 }; 509 510 //============================================================================== 511 //</DMUB_TYPES>================================================================= 512 //============================================================================== 513 //< DMUB_META>================================================================== 514 //============================================================================== 515 #pragma pack(push, 1) 516 517 /* Magic value for identifying dmub_fw_meta_info */ 518 #define DMUB_FW_META_MAGIC 0x444D5542 519 520 /* Offset from the end of the file to the dmub_fw_meta_info */ 521 #define DMUB_FW_META_OFFSET 0x24 522 523 /** 524 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 525 */ 526 union dmub_fw_meta_feature_bits { 527 struct { 528 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 529 uint32_t reserved : 31; 530 } bits; /**< status bits */ 531 uint32_t all; /**< 32-bit access to status bits */ 532 }; 533 534 /** 535 * struct dmub_fw_meta_info - metadata associated with fw binary 536 * 537 * NOTE: This should be considered a stable API. Fields should 538 * not be repurposed or reordered. New fields should be 539 * added instead to extend the structure. 540 * 541 * @magic_value: magic value identifying DMUB firmware meta info 542 * @fw_region_size: size of the firmware state region 543 * @trace_buffer_size: size of the tracebuffer region 544 * @fw_version: the firmware version information 545 * @dal_fw: 1 if the firmware is DAL 546 * @shared_state_size: size of the shared state region in bytes 547 * @shared_state_features: number of shared state features 548 */ 549 struct dmub_fw_meta_info { 550 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 551 uint32_t fw_region_size; /**< size of the firmware state region */ 552 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 553 uint32_t fw_version; /**< the firmware version information */ 554 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 555 uint8_t reserved[3]; /**< padding bits */ 556 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 557 uint16_t shared_state_features; /**< number of shared state features */ 558 uint16_t reserved2; /**< padding bytes */ 559 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 560 }; 561 562 /** 563 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 564 */ 565 union dmub_fw_meta { 566 struct dmub_fw_meta_info info; /**< metadata info */ 567 uint8_t reserved[64]; /**< padding bits */ 568 }; 569 570 #pragma pack(pop) 571 572 //============================================================================== 573 //< DMUB Trace Buffer>================================================================ 574 //============================================================================== 575 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 576 /** 577 * dmub_trace_code_t - firmware trace code, 32-bits 578 */ 579 typedef uint32_t dmub_trace_code_t; 580 581 /** 582 * struct dmcub_trace_buf_entry - Firmware trace entry 583 */ 584 struct dmcub_trace_buf_entry { 585 dmub_trace_code_t trace_code; /**< trace code for the event */ 586 uint32_t tick_count; /**< the tick count at time of trace */ 587 uint32_t param0; /**< trace defined parameter 0 */ 588 uint32_t param1; /**< trace defined parameter 1 */ 589 }; 590 #endif 591 592 //============================================================================== 593 //< DMUB_STATUS>================================================================ 594 //============================================================================== 595 596 /** 597 * DMCUB scratch registers can be used to determine firmware status. 598 * Current scratch register usage is as follows: 599 * 600 * SCRATCH0: FW Boot Status register 601 * SCRATCH5: LVTMA Status Register 602 * SCRATCH15: FW Boot Options register 603 */ 604 605 /** 606 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 607 */ 608 union dmub_fw_boot_status { 609 struct { 610 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 611 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 612 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 613 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 614 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 615 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 616 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 617 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 618 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 619 } bits; /**< status bits */ 620 uint32_t all; /**< 32-bit access to status bits */ 621 }; 622 623 /** 624 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 625 */ 626 enum dmub_fw_boot_status_bit { 627 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 628 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 629 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 630 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 631 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 632 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 633 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 634 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 635 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 636 }; 637 638 /* Register bit definition for SCRATCH5 */ 639 union dmub_lvtma_status { 640 struct { 641 uint32_t psp_ok : 1; 642 uint32_t edp_on : 1; 643 uint32_t reserved : 30; 644 } bits; 645 uint32_t all; 646 }; 647 648 enum dmub_lvtma_status_bit { 649 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 650 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 651 }; 652 653 enum dmub_ips_disable_type { 654 DMUB_IPS_ENABLE = 0, 655 DMUB_IPS_DISABLE_ALL = 1, 656 DMUB_IPS_DISABLE_IPS1 = 2, 657 DMUB_IPS_DISABLE_IPS2 = 3, 658 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 659 DMUB_IPS_DISABLE_DYNAMIC = 5, 660 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 661 }; 662 663 #define DMUB_IPS1_ALLOW_MASK 0x00000001 664 #define DMUB_IPS2_ALLOW_MASK 0x00000002 665 #define DMUB_IPS1_COMMIT_MASK 0x00000004 666 #define DMUB_IPS2_COMMIT_MASK 0x00000008 667 668 /** 669 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 670 */ 671 union dmub_fw_boot_options { 672 struct { 673 uint32_t pemu_env : 1; /**< 1 if PEMU */ 674 uint32_t fpga_env : 1; /**< 1 if FPGA */ 675 uint32_t optimized_init : 1; /**< 1 if optimized init */ 676 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 677 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 678 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 679 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 680 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 681 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 682 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 683 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 684 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 685 uint32_t power_optimization: 1; 686 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 687 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 688 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 689 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 690 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 691 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 692 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 693 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 694 uint32_t ips_disable: 3; /* options to disable ips support*/ 695 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 696 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 697 uint32_t reserved : 7; /**< reserved */ 698 } bits; /**< boot bits */ 699 uint32_t all; /**< 32-bit access to bits */ 700 }; 701 702 enum dmub_fw_boot_options_bit { 703 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 704 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 705 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 706 }; 707 708 //============================================================================== 709 //< DMUB_SHARED_STATE>========================================================== 710 //============================================================================== 711 712 /** 713 * Shared firmware state between driver and firmware for lockless communication 714 * in situations where the inbox/outbox may be unavailable. 715 * 716 * Each structure *must* be at most 256-bytes in size. The layout allocation is 717 * described below: 718 * 719 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 720 */ 721 722 /** 723 * enum dmub_shared_state_feature_id - List of shared state features. 724 */ 725 enum dmub_shared_state_feature_id { 726 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 727 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 728 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 729 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 730 }; 731 732 /** 733 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 734 */ 735 union dmub_shared_state_ips_fw_signals { 736 struct { 737 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 738 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 739 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 740 uint32_t detection_required : 1; /**< 1 if detection is required */ 741 uint32_t reserved_bits : 28; /**< Reversed */ 742 } bits; 743 uint32_t all; 744 }; 745 746 /** 747 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 748 */ 749 union dmub_shared_state_ips_driver_signals { 750 struct { 751 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 752 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 753 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 754 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 755 uint32_t reserved_bits : 28; /**< Reversed bits */ 756 } bits; 757 uint32_t all; 758 }; 759 760 /** 761 * IPS FW Version 762 */ 763 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 764 765 /** 766 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 767 */ 768 struct dmub_shared_state_ips_fw { 769 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 770 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 771 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 772 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 773 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 774 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 775 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 776 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 777 }; /* 248-bytes, fixed */ 778 779 /** 780 * IPS Driver Version 781 */ 782 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 783 784 /** 785 * struct dmub_shared_state_ips_driver - Driver state for IPS. 786 */ 787 struct dmub_shared_state_ips_driver { 788 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 789 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 790 }; /* 248-bytes, fixed */ 791 792 /** 793 * enum dmub_shared_state_feature_common - Generic payload. 794 */ 795 struct dmub_shared_state_feature_common { 796 uint32_t padding[62]; 797 }; /* 248-bytes, fixed */ 798 799 /** 800 * enum dmub_shared_state_feature_header - Feature description. 801 */ 802 struct dmub_shared_state_feature_header { 803 uint16_t id; /**< Feature ID */ 804 uint16_t version; /**< Feature version */ 805 uint32_t reserved; /**< Reserved bytes. */ 806 }; /* 8 bytes, fixed */ 807 808 /** 809 * struct dmub_shared_state_feature_block - Feature block. 810 */ 811 struct dmub_shared_state_feature_block { 812 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 813 union dmub_shared_feature_state_union { 814 struct dmub_shared_state_feature_common common; /**< Generic data */ 815 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 816 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 817 } data; /**< Shared state data. */ 818 }; /* 256-bytes, fixed */ 819 820 /** 821 * Shared state size in bytes. 822 */ 823 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 824 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 825 826 //============================================================================== 827 //</DMUB_STATUS>================================================================ 828 //============================================================================== 829 //< DMUB_VBIOS>================================================================= 830 //============================================================================== 831 832 /* 833 * enum dmub_cmd_vbios_type - VBIOS commands. 834 * 835 * Command IDs should be treated as stable ABI. 836 * Do not reuse or modify IDs. 837 */ 838 enum dmub_cmd_vbios_type { 839 /** 840 * Configures the DIG encoder. 841 */ 842 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 843 /** 844 * Controls the PHY. 845 */ 846 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 847 /** 848 * Sets the pixel clock/symbol clock. 849 */ 850 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 851 /** 852 * Enables or disables power gating. 853 */ 854 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 855 /** 856 * Controls embedded panels. 857 */ 858 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 859 /** 860 * Query DP alt status on a transmitter. 861 */ 862 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 863 /** 864 * Control PHY FSM 865 */ 866 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 867 /** 868 * Controls domain power gating 869 */ 870 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 871 }; 872 873 //============================================================================== 874 //</DMUB_VBIOS>================================================================= 875 //============================================================================== 876 //< DMUB_GPINT>================================================================= 877 //============================================================================== 878 879 /** 880 * The shifts and masks below may alternatively be used to format and read 881 * the command register bits. 882 */ 883 884 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 885 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 886 887 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 888 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 889 890 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 891 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 892 893 /** 894 * Command responses. 895 */ 896 897 /** 898 * Return response for DMUB_GPINT__STOP_FW command. 899 */ 900 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 901 902 /** 903 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 904 */ 905 union dmub_gpint_data_register { 906 struct { 907 uint32_t param : 16; /**< 16-bit parameter */ 908 uint32_t command_code : 12; /**< GPINT command */ 909 uint32_t status : 4; /**< Command status bit */ 910 } bits; /**< GPINT bit access */ 911 uint32_t all; /**< GPINT 32-bit access */ 912 }; 913 914 /* 915 * enum dmub_gpint_command - GPINT command to DMCUB FW 916 * 917 * Command IDs should be treated as stable ABI. 918 * Do not reuse or modify IDs. 919 */ 920 enum dmub_gpint_command { 921 /** 922 * Invalid command, ignored. 923 */ 924 DMUB_GPINT__INVALID_COMMAND = 0, 925 /** 926 * DESC: Queries the firmware version. 927 * RETURN: Firmware version. 928 */ 929 DMUB_GPINT__GET_FW_VERSION = 1, 930 /** 931 * DESC: Halts the firmware. 932 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 933 */ 934 DMUB_GPINT__STOP_FW = 2, 935 /** 936 * DESC: Get PSR state from FW. 937 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 938 */ 939 DMUB_GPINT__GET_PSR_STATE = 7, 940 /** 941 * DESC: Notifies DMCUB of the currently active streams. 942 * ARGS: Stream mask, 1 bit per active stream index. 943 */ 944 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 945 /** 946 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 947 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 948 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 949 * RETURN: PSR residency in milli-percent. 950 */ 951 DMUB_GPINT__PSR_RESIDENCY = 9, 952 953 /** 954 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 955 */ 956 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 957 958 /** 959 * DESC: Get REPLAY state from FW. 960 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 961 */ 962 DMUB_GPINT__GET_REPLAY_STATE = 13, 963 964 /** 965 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 966 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 967 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 968 * RETURN: REPLAY residency in milli-percent. 969 */ 970 DMUB_GPINT__REPLAY_RESIDENCY = 14, 971 972 /** 973 * DESC: Copy bounding box to the host. 974 * ARGS: Version of bounding box to copy 975 * RETURN: Result of copying bounding box 976 */ 977 DMUB_GPINT__BB_COPY = 96, 978 979 /** 980 * DESC: Updates the host addresses bit48~bit63 for bounding box. 981 * ARGS: The word3 for the 64 bit address 982 */ 983 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 984 985 /** 986 * DESC: Updates the host addresses bit32~bit47 for bounding box. 987 * ARGS: The word2 for the 64 bit address 988 */ 989 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 990 991 /** 992 * DESC: Updates the host addresses bit16~bit31 for bounding box. 993 * ARGS: The word1 for the 64 bit address 994 */ 995 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 996 997 /** 998 * DESC: Updates the host addresses bit0~bit15 for bounding box. 999 * ARGS: The word0 for the 64 bit address 1000 */ 1001 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1002 1003 /** 1004 * DESC: Updates the trace buffer lower 32-bit mask. 1005 * ARGS: The new mask 1006 * RETURN: Lower 32-bit mask. 1007 */ 1008 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1009 1010 /** 1011 * DESC: Updates the trace buffer mask bit0~bit15. 1012 * ARGS: The new mask 1013 * RETURN: Lower 32-bit mask. 1014 */ 1015 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1016 1017 /** 1018 * DESC: Updates the trace buffer mask bit16~bit31. 1019 * ARGS: The new mask 1020 * RETURN: Lower 32-bit mask. 1021 */ 1022 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1023 1024 /** 1025 * DESC: Updates the trace buffer mask bit32~bit47. 1026 * ARGS: The new mask 1027 * RETURN: Lower 32-bit mask. 1028 */ 1029 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1030 1031 /** 1032 * DESC: Updates the trace buffer mask bit48~bit63. 1033 * ARGS: The new mask 1034 * RETURN: Lower 32-bit mask. 1035 */ 1036 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1037 1038 /** 1039 * DESC: Read the trace buffer mask bi0~bit15. 1040 */ 1041 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1042 1043 /** 1044 * DESC: Read the trace buffer mask bit16~bit31. 1045 */ 1046 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1047 1048 /** 1049 * DESC: Read the trace buffer mask bi32~bit47. 1050 */ 1051 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1052 1053 /** 1054 * DESC: Updates the trace buffer mask bit32~bit63. 1055 */ 1056 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1057 1058 /** 1059 * DESC: Set IPS residency measurement 1060 * ARGS: 0 - Disable ips measurement 1061 * 1 - Enable ips measurement 1062 */ 1063 DMUB_GPINT__IPS_RESIDENCY = 121, 1064 1065 /** 1066 * DESC: Enable measurements for various task duration 1067 * ARGS: 0 - Disable measurement 1068 * 1 - Enable measurement 1069 */ 1070 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1071 1072 /** 1073 * DESC: Gets IPS residency in microseconds 1074 * ARGS: 0 - Return IPS1 residency 1075 * 1 - Return IPS2 residency 1076 * 2 - Return IPS1_RCG residency 1077 * 3 - Return IPS1_ONO2_ON residency 1078 * RETURN: Total residency in microseconds - lower 32 bits 1079 */ 1080 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1081 1082 /** 1083 * DESC: Gets IPS1 histogram counts 1084 * ARGS: Bucket index 1085 * RETURN: Total count for the bucket 1086 */ 1087 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1088 1089 /** 1090 * DESC: Gets IPS2 histogram counts 1091 * ARGS: Bucket index 1092 * RETURN: Total count for the bucket 1093 */ 1094 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1095 1096 /** 1097 * DESC: Gets IPS residency 1098 * ARGS: 0 - Return IPS1 residency 1099 * 1 - Return IPS2 residency 1100 * 2 - Return IPS1_RCG residency 1101 * 3 - Return IPS1_ONO2_ON residency 1102 * RETURN: Total residency in milli-percent. 1103 */ 1104 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1105 1106 /** 1107 * DESC: Gets IPS1_RCG histogram counts 1108 * ARGS: Bucket index 1109 * RETURN: Total count for the bucket 1110 */ 1111 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1112 1113 /** 1114 * DESC: Gets IPS1_ONO2_ON histogram counts 1115 * ARGS: Bucket index 1116 * RETURN: Total count for the bucket 1117 */ 1118 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1119 1120 /** 1121 * DESC: Gets IPS entry counter during residency measurement 1122 * ARGS: 0 - Return IPS1 entry counts 1123 * 1 - Return IPS2 entry counts 1124 * 2 - Return IPS1_RCG entry counts 1125 * 3 - Return IPS2_ONO2_ON entry counts 1126 * RETURN: Entry counter for selected IPS mode 1127 */ 1128 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1129 1130 /** 1131 * DESC: Gets IPS inactive residency in microseconds 1132 * ARGS: 0 - Return IPS1_MAX residency 1133 * 1 - Return IPS2 residency 1134 * 2 - Return IPS1_RCG residency 1135 * 3 - Return IPS1_ONO2_ON residency 1136 * RETURN: Total inactive residency in microseconds - lower 32 bits 1137 */ 1138 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1139 1140 /** 1141 * DESC: Gets IPS inactive residency in microseconds 1142 * ARGS: 0 - Return IPS1_MAX residency 1143 * 1 - Return IPS2 residency 1144 * 2 - Return IPS1_RCG residency 1145 * 3 - Return IPS1_ONO2_ON residency 1146 * RETURN: Total inactive residency in microseconds - upper 32 bits 1147 */ 1148 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1149 1150 /** 1151 * DESC: Gets IPS residency in microseconds 1152 * ARGS: 0 - Return IPS1 residency 1153 * 1 - Return IPS2 residency 1154 * 2 - Return IPS1_RCG residency 1155 * 3 - Return IPS1_ONO2_ON residency 1156 * RETURN: Total residency in microseconds - upper 32 bits 1157 */ 1158 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1159 }; 1160 1161 /** 1162 * INBOX0 generic command definition 1163 */ 1164 union dmub_inbox0_cmd_common { 1165 struct { 1166 uint32_t command_code: 8; /**< INBOX0 command code */ 1167 uint32_t param: 24; /**< 24-bit parameter */ 1168 } bits; 1169 uint32_t all; 1170 }; 1171 1172 /** 1173 * INBOX0 hw_lock command definition 1174 */ 1175 union dmub_inbox0_cmd_lock_hw { 1176 struct { 1177 uint32_t command_code: 8; 1178 1179 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1180 uint32_t hw_lock_client: 2; 1181 1182 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1183 uint32_t otg_inst: 3; 1184 uint32_t opp_inst: 3; 1185 uint32_t dig_inst: 3; 1186 1187 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1188 uint32_t lock_pipe: 1; 1189 uint32_t lock_cursor: 1; 1190 uint32_t lock_dig: 1; 1191 uint32_t triple_buffer_lock: 1; 1192 1193 uint32_t lock: 1; /**< Lock */ 1194 uint32_t should_release: 1; /**< Release */ 1195 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1196 } bits; 1197 uint32_t all; 1198 }; 1199 1200 union dmub_inbox0_data_register { 1201 union dmub_inbox0_cmd_common inbox0_cmd_common; 1202 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1203 }; 1204 1205 enum dmub_inbox0_command { 1206 /** 1207 * DESC: Invalid command, ignored. 1208 */ 1209 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1210 /** 1211 * DESC: Notification to acquire/release HW lock 1212 * ARGS: 1213 */ 1214 DMUB_INBOX0_CMD__HW_LOCK = 1, 1215 }; 1216 //============================================================================== 1217 //</DMUB_GPINT>================================================================= 1218 //============================================================================== 1219 //< DMUB_CMD>=================================================================== 1220 //============================================================================== 1221 1222 /** 1223 * Size in bytes of each DMUB command. 1224 */ 1225 #define DMUB_RB_CMD_SIZE 64 1226 1227 /** 1228 * Maximum number of items in the DMUB ringbuffer. 1229 */ 1230 #define DMUB_RB_MAX_ENTRY 128 1231 1232 /** 1233 * Ringbuffer size in bytes. 1234 */ 1235 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1236 1237 /** 1238 * REG_SET mask for reg offload. 1239 */ 1240 #define REG_SET_MASK 0xFFFF 1241 1242 /* 1243 * enum dmub_cmd_type - DMUB inbox command. 1244 * 1245 * Command IDs should be treated as stable ABI. 1246 * Do not reuse or modify IDs. 1247 */ 1248 enum dmub_cmd_type { 1249 /** 1250 * Invalid command. 1251 */ 1252 DMUB_CMD__NULL = 0, 1253 /** 1254 * Read modify write register sequence offload. 1255 */ 1256 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1257 /** 1258 * Field update register sequence offload. 1259 */ 1260 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1261 /** 1262 * Burst write sequence offload. 1263 */ 1264 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1265 /** 1266 * Reg wait sequence offload. 1267 */ 1268 DMUB_CMD__REG_REG_WAIT = 4, 1269 /** 1270 * Workaround to avoid HUBP underflow during NV12 playback. 1271 */ 1272 DMUB_CMD__PLAT_54186_WA = 5, 1273 /** 1274 * Command type used to query FW feature caps. 1275 */ 1276 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1277 /** 1278 * Command type used to get visual confirm color. 1279 */ 1280 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1281 /** 1282 * Command type used for all PSR commands. 1283 */ 1284 DMUB_CMD__PSR = 64, 1285 /** 1286 * Command type used for all MALL commands. 1287 */ 1288 DMUB_CMD__MALL = 65, 1289 /** 1290 * Command type used for all ABM commands. 1291 */ 1292 DMUB_CMD__ABM = 66, 1293 /** 1294 * Command type used to update dirty rects in FW. 1295 */ 1296 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1297 /** 1298 * Command type used to update cursor info in FW. 1299 */ 1300 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1301 /** 1302 * Command type used for HW locking in FW. 1303 */ 1304 DMUB_CMD__HW_LOCK = 69, 1305 /** 1306 * Command type used to access DP AUX. 1307 */ 1308 DMUB_CMD__DP_AUX_ACCESS = 70, 1309 /** 1310 * Command type used for OUTBOX1 notification enable 1311 */ 1312 DMUB_CMD__OUTBOX1_ENABLE = 71, 1313 1314 /** 1315 * Command type used for all idle optimization commands. 1316 */ 1317 DMUB_CMD__IDLE_OPT = 72, 1318 /** 1319 * Command type used for all clock manager commands. 1320 */ 1321 DMUB_CMD__CLK_MGR = 73, 1322 /** 1323 * Command type used for all panel control commands. 1324 */ 1325 DMUB_CMD__PANEL_CNTL = 74, 1326 1327 /** 1328 * Command type used for all CAB commands. 1329 */ 1330 DMUB_CMD__CAB_FOR_SS = 75, 1331 1332 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1333 1334 /** 1335 * Command type used for interfacing with DPIA. 1336 */ 1337 DMUB_CMD__DPIA = 77, 1338 /** 1339 * Command type used for EDID CEA parsing 1340 */ 1341 DMUB_CMD__EDID_CEA = 79, 1342 /** 1343 * Command type used for getting usbc cable ID 1344 */ 1345 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1346 /** 1347 * Command type used to query HPD state. 1348 */ 1349 DMUB_CMD__QUERY_HPD_STATE = 82, 1350 /** 1351 * Command type used for all VBIOS interface commands. 1352 */ 1353 /** 1354 * Command type used for all REPLAY commands. 1355 */ 1356 DMUB_CMD__REPLAY = 83, 1357 1358 /** 1359 * Command type used for all SECURE_DISPLAY commands. 1360 */ 1361 DMUB_CMD__SECURE_DISPLAY = 85, 1362 1363 /** 1364 * Command type used to set DPIA HPD interrupt state 1365 */ 1366 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1367 1368 /** 1369 * Command type used for all PSP commands. 1370 */ 1371 DMUB_CMD__PSP = 88, 1372 1373 DMUB_CMD__VBIOS = 128, 1374 }; 1375 1376 /** 1377 * enum dmub_out_cmd_type - DMUB outbox commands. 1378 */ 1379 enum dmub_out_cmd_type { 1380 /** 1381 * Invalid outbox command, ignored. 1382 */ 1383 DMUB_OUT_CMD__NULL = 0, 1384 /** 1385 * Command type used for DP AUX Reply data notification 1386 */ 1387 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1388 /** 1389 * Command type used for DP HPD event notification 1390 */ 1391 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1392 /** 1393 * Command type used for SET_CONFIG Reply notification 1394 */ 1395 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1396 /** 1397 * Command type used for USB4 DPIA notification 1398 */ 1399 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1400 /** 1401 * Command type used for HPD redetect notification 1402 */ 1403 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1404 }; 1405 1406 /* DMUB_CMD__DPIA command sub-types. */ 1407 enum dmub_cmd_dpia_type { 1408 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1409 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1410 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1411 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1412 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1413 }; 1414 1415 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1416 enum dmub_cmd_dpia_notification_type { 1417 DPIA_NOTIFY__BW_ALLOCATION = 0, 1418 }; 1419 1420 #pragma pack(push, 1) 1421 1422 /** 1423 * struct dmub_cmd_header - Common command header fields. 1424 */ 1425 struct dmub_cmd_header { 1426 unsigned int type : 8; /**< command type */ 1427 unsigned int sub_type : 8; /**< command sub type */ 1428 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1429 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1430 unsigned int reserved0 : 6; /**< reserved bits */ 1431 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1432 unsigned int reserved1 : 2; /**< reserved bits */ 1433 }; 1434 1435 /* 1436 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1437 * 1438 * 60 payload bytes can hold up to 5 sets of read modify writes, 1439 * each take 3 dwords. 1440 * 1441 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1442 * 1443 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1444 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1445 */ 1446 struct dmub_cmd_read_modify_write_sequence { 1447 uint32_t addr; /**< register address */ 1448 uint32_t modify_mask; /**< modify mask */ 1449 uint32_t modify_value; /**< modify value */ 1450 }; 1451 1452 /** 1453 * Maximum number of ops in read modify write sequence. 1454 */ 1455 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1456 1457 /** 1458 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1459 */ 1460 struct dmub_rb_cmd_read_modify_write { 1461 struct dmub_cmd_header header; /**< command header */ 1462 /** 1463 * Read modify write sequence. 1464 */ 1465 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1466 }; 1467 1468 /* 1469 * Update a register with specified masks and values sequeunce 1470 * 1471 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1472 * 1473 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1474 * 1475 * 1476 * USE CASE: 1477 * 1. auto-increment register where additional read would update pointer and produce wrong result 1478 * 2. toggle a bit without read in the middle 1479 */ 1480 1481 struct dmub_cmd_reg_field_update_sequence { 1482 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1483 uint32_t modify_value; /**< value to update with */ 1484 }; 1485 1486 /** 1487 * Maximum number of ops in field update sequence. 1488 */ 1489 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1490 1491 /** 1492 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1493 */ 1494 struct dmub_rb_cmd_reg_field_update_sequence { 1495 struct dmub_cmd_header header; /**< command header */ 1496 uint32_t addr; /**< register address */ 1497 /** 1498 * Field update sequence. 1499 */ 1500 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1501 }; 1502 1503 1504 /** 1505 * Maximum number of burst write values. 1506 */ 1507 #define DMUB_BURST_WRITE_VALUES__MAX 14 1508 1509 /* 1510 * struct dmub_rb_cmd_burst_write - Burst write 1511 * 1512 * support use case such as writing out LUTs. 1513 * 1514 * 60 payload bytes can hold up to 14 values to write to given address 1515 * 1516 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1517 */ 1518 struct dmub_rb_cmd_burst_write { 1519 struct dmub_cmd_header header; /**< command header */ 1520 uint32_t addr; /**< register start address */ 1521 /** 1522 * Burst write register values. 1523 */ 1524 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1525 }; 1526 1527 /** 1528 * struct dmub_rb_cmd_common - Common command header 1529 */ 1530 struct dmub_rb_cmd_common { 1531 struct dmub_cmd_header header; /**< command header */ 1532 /** 1533 * Padding to RB_CMD_SIZE 1534 */ 1535 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1536 }; 1537 1538 /** 1539 * struct dmub_cmd_reg_wait_data - Register wait data 1540 */ 1541 struct dmub_cmd_reg_wait_data { 1542 uint32_t addr; /**< Register address */ 1543 uint32_t mask; /**< Mask for register bits */ 1544 uint32_t condition_field_value; /**< Value to wait for */ 1545 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1546 }; 1547 1548 /** 1549 * struct dmub_rb_cmd_reg_wait - Register wait command 1550 */ 1551 struct dmub_rb_cmd_reg_wait { 1552 struct dmub_cmd_header header; /**< Command header */ 1553 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1554 }; 1555 1556 /** 1557 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1558 * 1559 * Reprograms surface parameters to avoid underflow. 1560 */ 1561 struct dmub_cmd_PLAT_54186_wa { 1562 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1563 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1564 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1565 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1566 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1567 struct { 1568 uint32_t hubp_inst : 4; /**< HUBP instance */ 1569 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1570 uint32_t immediate :1; /**< Immediate flip */ 1571 uint32_t vmid : 4; /**< VMID */ 1572 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1573 uint32_t reserved : 21; /**< Reserved */ 1574 } flip_params; /**< Pageflip parameters */ 1575 uint32_t reserved[9]; /**< Reserved bits */ 1576 }; 1577 1578 /** 1579 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1580 */ 1581 struct dmub_rb_cmd_PLAT_54186_wa { 1582 struct dmub_cmd_header header; /**< Command header */ 1583 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1584 }; 1585 1586 /** 1587 * enum dmub_cmd_mall_type - MALL commands 1588 */ 1589 enum dmub_cmd_mall_type { 1590 /** 1591 * Allows display refresh from MALL. 1592 */ 1593 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1594 /** 1595 * Disallows display refresh from MALL. 1596 */ 1597 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1598 /** 1599 * Cursor copy for MALL. 1600 */ 1601 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1602 /** 1603 * Controls DF requests. 1604 */ 1605 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1606 }; 1607 1608 /** 1609 * struct dmub_rb_cmd_mall - MALL command data. 1610 */ 1611 struct dmub_rb_cmd_mall { 1612 struct dmub_cmd_header header; /**< Common command header */ 1613 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1614 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1615 uint32_t tmr_delay; /**< Timer delay */ 1616 uint32_t tmr_scale; /**< Timer scale */ 1617 uint16_t cursor_width; /**< Cursor width in pixels */ 1618 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1619 uint16_t cursor_height; /**< Cursor height in pixels */ 1620 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1621 uint8_t debug_bits; /**< Debug bits */ 1622 1623 uint8_t reserved1; /**< Reserved bits */ 1624 uint8_t reserved2; /**< Reserved bits */ 1625 }; 1626 1627 /** 1628 * enum dmub_cmd_cab_type - CAB command data. 1629 */ 1630 enum dmub_cmd_cab_type { 1631 /** 1632 * No idle optimizations (i.e. no CAB) 1633 */ 1634 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1635 /** 1636 * No DCN requests for memory 1637 */ 1638 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1639 /** 1640 * Fit surfaces in CAB (i.e. CAB enable) 1641 */ 1642 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1643 /** 1644 * Do not fit surfaces in CAB (i.e. no CAB) 1645 */ 1646 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1647 }; 1648 1649 /** 1650 * struct dmub_rb_cmd_cab - CAB command data. 1651 */ 1652 struct dmub_rb_cmd_cab_for_ss { 1653 struct dmub_cmd_header header; 1654 uint8_t cab_alloc_ways; /* total number of ways */ 1655 uint8_t debug_bits; /* debug bits */ 1656 }; 1657 1658 /** 1659 * Enum for indicating which MCLK switch mode per pipe 1660 */ 1661 enum mclk_switch_mode { 1662 NONE = 0, 1663 FPO = 1, 1664 SUBVP = 2, 1665 VBLANK = 3, 1666 }; 1667 1668 /* Per pipe struct which stores the MCLK switch mode 1669 * data to be sent to DMUB. 1670 * Named "v2" for now -- once FPO and SUBVP are fully merged 1671 * the type name can be updated 1672 */ 1673 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1674 union { 1675 struct { 1676 uint32_t pix_clk_100hz; 1677 uint16_t main_vblank_start; 1678 uint16_t main_vblank_end; 1679 uint16_t mall_region_lines; 1680 uint16_t prefetch_lines; 1681 uint16_t prefetch_to_mall_start_lines; 1682 uint16_t processing_delay_lines; 1683 uint16_t htotal; // required to calculate line time for multi-display cases 1684 uint16_t vtotal; 1685 uint8_t main_pipe_index; 1686 uint8_t phantom_pipe_index; 1687 /* Since the microschedule is calculated in terms of OTG lines, 1688 * include any scaling factors to make sure when we get accurate 1689 * conversion when programming MALL_START_LINE (which is in terms 1690 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1691 * is 1/2 (numerator = 1, denominator = 2). 1692 */ 1693 uint8_t scale_factor_numerator; 1694 uint8_t scale_factor_denominator; 1695 uint8_t is_drr; 1696 uint8_t main_split_pipe_index; 1697 uint8_t phantom_split_pipe_index; 1698 } subvp_data; 1699 1700 struct { 1701 uint32_t pix_clk_100hz; 1702 uint16_t vblank_start; 1703 uint16_t vblank_end; 1704 uint16_t vstartup_start; 1705 uint16_t vtotal; 1706 uint16_t htotal; 1707 uint8_t vblank_pipe_index; 1708 uint8_t padding[1]; 1709 struct { 1710 uint8_t drr_in_use; 1711 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1712 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1713 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1714 uint8_t use_ramping; // Use ramping or not 1715 uint8_t drr_vblank_start_margin; 1716 } drr_info; // DRR considered as part of SubVP + VBLANK case 1717 } vblank_data; 1718 } pipe_config; 1719 1720 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1721 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1722 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1723 */ 1724 uint8_t mode; // enum mclk_switch_mode 1725 }; 1726 1727 /** 1728 * Config data for Sub-VP and FPO 1729 * Named "v2" for now -- once FPO and SUBVP are fully merged 1730 * the type name can be updated 1731 */ 1732 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1733 uint16_t watermark_a_cache; 1734 uint8_t vertical_int_margin_us; 1735 uint8_t pstate_allow_width_us; 1736 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1737 }; 1738 1739 /** 1740 * DMUB rb command definition for Sub-VP and FPO 1741 * Named "v2" for now -- once FPO and SUBVP are fully merged 1742 * the type name can be updated 1743 */ 1744 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1745 struct dmub_cmd_header header; 1746 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1747 }; 1748 1749 struct dmub_flip_addr_info { 1750 uint32_t surf_addr_lo; 1751 uint32_t surf_addr_c_lo; 1752 uint32_t meta_addr_lo; 1753 uint32_t meta_addr_c_lo; 1754 uint16_t surf_addr_hi; 1755 uint16_t surf_addr_c_hi; 1756 uint16_t meta_addr_hi; 1757 uint16_t meta_addr_c_hi; 1758 }; 1759 1760 struct dmub_fams2_flip_info { 1761 union { 1762 struct { 1763 uint8_t is_immediate: 1; 1764 } bits; 1765 uint8_t all; 1766 } config; 1767 uint8_t otg_inst; 1768 uint8_t pipe_mask; 1769 uint8_t pad; 1770 struct dmub_flip_addr_info addr_info; 1771 }; 1772 1773 struct dmub_rb_cmd_fams2_flip { 1774 struct dmub_cmd_header header; 1775 struct dmub_fams2_flip_info flip_info; 1776 }; 1777 1778 struct dmub_optc_state_v2 { 1779 uint32_t v_total_min; 1780 uint32_t v_total_max; 1781 uint32_t v_total_mid; 1782 uint32_t v_total_mid_frame_num; 1783 uint8_t program_manual_trigger; 1784 uint8_t tg_inst; 1785 uint8_t pad[2]; 1786 }; 1787 1788 struct dmub_optc_position { 1789 uint32_t vpos; 1790 uint32_t hpos; 1791 uint32_t frame; 1792 }; 1793 1794 struct dmub_rb_cmd_fams2_drr_update { 1795 struct dmub_cmd_header header; 1796 struct dmub_optc_state_v2 dmub_optc_state_req; 1797 }; 1798 1799 /* HW and FW global configuration data for FAMS2 */ 1800 /* FAMS2 types and structs */ 1801 enum fams2_stream_type { 1802 FAMS2_STREAM_TYPE_NONE = 0, 1803 FAMS2_STREAM_TYPE_VBLANK = 1, 1804 FAMS2_STREAM_TYPE_VACTIVE = 2, 1805 FAMS2_STREAM_TYPE_DRR = 3, 1806 FAMS2_STREAM_TYPE_SUBVP = 4, 1807 }; 1808 1809 /* dynamic stream state */ 1810 struct dmub_fams2_legacy_stream_dynamic_state { 1811 uint8_t force_allow_at_vblank; 1812 uint8_t pad[3]; 1813 }; 1814 1815 struct dmub_fams2_subvp_stream_dynamic_state { 1816 uint16_t viewport_start_hubp_vline; 1817 uint16_t viewport_height_hubp_vlines; 1818 uint16_t viewport_start_c_hubp_vline; 1819 uint16_t viewport_height_c_hubp_vlines; 1820 uint16_t phantom_viewport_height_hubp_vlines; 1821 uint16_t phantom_viewport_height_c_hubp_vlines; 1822 uint16_t microschedule_start_otg_vline; 1823 uint16_t mall_start_otg_vline; 1824 uint16_t mall_start_hubp_vline; 1825 uint16_t mall_start_c_hubp_vline; 1826 uint8_t force_allow_at_vblank_only; 1827 uint8_t pad[3]; 1828 }; 1829 1830 struct dmub_fams2_drr_stream_dynamic_state { 1831 uint16_t stretched_vtotal; 1832 uint8_t use_cur_vtotal; 1833 uint8_t pad; 1834 }; 1835 1836 struct dmub_fams2_stream_dynamic_state { 1837 uint64_t ref_tick; 1838 uint32_t cur_vtotal; 1839 uint16_t adjusted_allow_end_otg_vline; 1840 uint8_t pad[2]; 1841 struct dmub_optc_position ref_otg_pos; 1842 struct dmub_optc_position target_otg_pos; 1843 union { 1844 struct dmub_fams2_legacy_stream_dynamic_state legacy; 1845 struct dmub_fams2_subvp_stream_dynamic_state subvp; 1846 struct dmub_fams2_drr_stream_dynamic_state drr; 1847 } sub_state; 1848 }; 1849 1850 /* static stream state */ 1851 struct dmub_fams2_legacy_stream_static_state { 1852 uint8_t vactive_det_fill_delay_otg_vlines; 1853 uint8_t programming_delay_otg_vlines; 1854 }; 1855 1856 struct dmub_fams2_subvp_stream_static_state { 1857 uint16_t vratio_numerator; 1858 uint16_t vratio_denominator; 1859 uint16_t phantom_vtotal; 1860 uint16_t phantom_vactive; 1861 union { 1862 struct { 1863 uint8_t is_multi_planar : 1; 1864 uint8_t is_yuv420 : 1; 1865 } bits; 1866 uint8_t all; 1867 } config; 1868 uint8_t programming_delay_otg_vlines; 1869 uint8_t prefetch_to_mall_otg_vlines; 1870 uint8_t phantom_otg_inst; 1871 uint8_t phantom_pipe_mask; 1872 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1873 }; 1874 1875 struct dmub_fams2_drr_stream_static_state { 1876 uint16_t nom_stretched_vtotal; 1877 uint8_t programming_delay_otg_vlines; 1878 uint8_t only_stretch_if_required; 1879 uint8_t pad[2]; 1880 }; 1881 1882 struct dmub_fams2_stream_static_state { 1883 enum fams2_stream_type type; 1884 uint32_t otg_vline_time_ns; 1885 uint32_t otg_vline_time_ticks; 1886 uint16_t htotal; 1887 uint16_t vtotal; // nominal vtotal 1888 uint16_t vblank_start; 1889 uint16_t vblank_end; 1890 uint16_t max_vtotal; 1891 uint16_t allow_start_otg_vline; 1892 uint16_t allow_end_otg_vline; 1893 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1894 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1895 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 1896 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1897 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1898 union { 1899 struct { 1900 uint8_t is_drr: 1; // stream is DRR enabled 1901 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 1902 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1903 } bits; 1904 uint8_t all; 1905 } config; 1906 uint8_t otg_inst; 1907 uint8_t pipe_mask; // pipe mask for the whole config 1908 uint8_t num_planes; 1909 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1910 uint8_t pad[DMUB_MAX_PLANES % 4]; 1911 union { 1912 struct dmub_fams2_legacy_stream_static_state legacy; 1913 struct dmub_fams2_subvp_stream_static_state subvp; 1914 struct dmub_fams2_drr_stream_static_state drr; 1915 } sub_state; 1916 }; 1917 1918 /** 1919 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 1920 * p-state request to allow latency 1921 */ 1922 enum dmub_fams2_allow_delay_check_mode { 1923 /* No check for request to allow delay */ 1924 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 1925 /* Check for request to allow delay */ 1926 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 1927 /* Check for prepare to allow delay */ 1928 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 1929 }; 1930 1931 union dmub_fams2_global_feature_config { 1932 struct { 1933 uint32_t enable: 1; 1934 uint32_t enable_ppt_check: 1; 1935 uint32_t enable_stall_recovery: 1; 1936 uint32_t enable_debug: 1; 1937 uint32_t enable_offload_flip: 1; 1938 uint32_t enable_visual_confirm: 1; 1939 uint32_t allow_delay_check_mode: 2; 1940 uint32_t reserved: 24; 1941 } bits; 1942 uint32_t all; 1943 }; 1944 1945 struct dmub_cmd_fams2_global_config { 1946 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 1947 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 1948 uint32_t num_streams; 1949 union dmub_fams2_global_feature_config features; 1950 uint32_t recovery_timeout_us; 1951 uint32_t hwfq_flip_programming_delay_us; 1952 }; 1953 1954 union dmub_cmd_fams2_config { 1955 struct dmub_cmd_fams2_global_config global; 1956 struct dmub_fams2_stream_static_state stream; 1957 }; 1958 1959 /** 1960 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 1961 */ 1962 struct dmub_rb_cmd_fams2 { 1963 struct dmub_cmd_header header; 1964 union dmub_cmd_fams2_config config; 1965 }; 1966 1967 /** 1968 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1969 */ 1970 enum dmub_cmd_idle_opt_type { 1971 /** 1972 * DCN hardware restore. 1973 */ 1974 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1975 1976 /** 1977 * DCN hardware save. 1978 */ 1979 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1980 1981 /** 1982 * DCN hardware notify idle. 1983 */ 1984 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 1985 1986 /** 1987 * DCN hardware notify power state. 1988 */ 1989 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 1990 }; 1991 1992 /** 1993 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1994 */ 1995 struct dmub_rb_cmd_idle_opt_dcn_restore { 1996 struct dmub_cmd_header header; /**< header */ 1997 }; 1998 1999 /** 2000 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2001 */ 2002 struct dmub_dcn_notify_idle_cntl_data { 2003 uint8_t driver_idle; 2004 uint8_t skip_otg_disable; 2005 uint8_t reserved[58]; 2006 }; 2007 2008 /** 2009 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2010 */ 2011 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2012 struct dmub_cmd_header header; /**< header */ 2013 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2014 }; 2015 2016 /** 2017 * enum dmub_idle_opt_dc_power_state - DC power states. 2018 */ 2019 enum dmub_idle_opt_dc_power_state { 2020 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2021 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2022 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2023 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2024 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2025 }; 2026 2027 /** 2028 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2029 */ 2030 struct dmub_idle_opt_set_dc_power_state_data { 2031 uint8_t power_state; /**< power state */ 2032 uint8_t pad[3]; /**< padding */ 2033 }; 2034 2035 /** 2036 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2037 */ 2038 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2039 struct dmub_cmd_header header; /**< header */ 2040 struct dmub_idle_opt_set_dc_power_state_data data; 2041 }; 2042 2043 /** 2044 * struct dmub_clocks - Clock update notification. 2045 */ 2046 struct dmub_clocks { 2047 uint32_t dispclk_khz; /**< dispclk kHz */ 2048 uint32_t dppclk_khz; /**< dppclk kHz */ 2049 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2050 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2051 }; 2052 2053 /** 2054 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2055 */ 2056 enum dmub_cmd_clk_mgr_type { 2057 /** 2058 * Notify DMCUB of clock update. 2059 */ 2060 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2061 }; 2062 2063 /** 2064 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2065 */ 2066 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2067 struct dmub_cmd_header header; /**< header */ 2068 struct dmub_clocks clocks; /**< clock data */ 2069 }; 2070 2071 /** 2072 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2073 */ 2074 struct dmub_cmd_digx_encoder_control_data { 2075 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2076 }; 2077 2078 /** 2079 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2080 */ 2081 struct dmub_rb_cmd_digx_encoder_control { 2082 struct dmub_cmd_header header; /**< header */ 2083 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2084 }; 2085 2086 /** 2087 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2088 */ 2089 struct dmub_cmd_set_pixel_clock_data { 2090 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2091 }; 2092 2093 /** 2094 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2095 */ 2096 struct dmub_rb_cmd_set_pixel_clock { 2097 struct dmub_cmd_header header; /**< header */ 2098 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2099 }; 2100 2101 /** 2102 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2103 */ 2104 struct dmub_cmd_enable_disp_power_gating_data { 2105 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2106 }; 2107 2108 /** 2109 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2110 */ 2111 struct dmub_rb_cmd_enable_disp_power_gating { 2112 struct dmub_cmd_header header; /**< header */ 2113 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2114 }; 2115 2116 /** 2117 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2118 */ 2119 struct dmub_dig_transmitter_control_data_v1_7 { 2120 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2121 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2122 union { 2123 uint8_t digmode; /**< enum atom_encode_mode_def */ 2124 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2125 } mode_laneset; 2126 uint8_t lanenum; /**< Number of lanes */ 2127 union { 2128 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2129 } symclk_units; 2130 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2131 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2132 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2133 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2134 uint8_t reserved1; /**< For future use */ 2135 uint8_t reserved2[3]; /**< For future use */ 2136 uint32_t reserved3[11]; /**< For future use */ 2137 }; 2138 2139 /** 2140 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2141 */ 2142 union dmub_cmd_dig1_transmitter_control_data { 2143 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2144 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2145 }; 2146 2147 /** 2148 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2149 */ 2150 struct dmub_rb_cmd_dig1_transmitter_control { 2151 struct dmub_cmd_header header; /**< header */ 2152 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2153 }; 2154 2155 /** 2156 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2157 */ 2158 struct dmub_rb_cmd_domain_control_data { 2159 uint8_t inst : 6; /**< DOMAIN instance to control */ 2160 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2161 uint8_t reserved[3]; /**< Reserved for future use */ 2162 }; 2163 2164 /** 2165 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2166 */ 2167 struct dmub_rb_cmd_domain_control { 2168 struct dmub_cmd_header header; /**< header */ 2169 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2170 }; 2171 2172 /** 2173 * DPIA tunnel command parameters. 2174 */ 2175 struct dmub_cmd_dig_dpia_control_data { 2176 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2177 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2178 union { 2179 uint8_t digmode; /** enum atom_encode_mode_def */ 2180 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2181 } mode_laneset; 2182 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2183 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2184 uint8_t hpdsel; /** =0: HPD is not assigned */ 2185 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2186 uint8_t dpia_id; /** Index of DPIA */ 2187 uint8_t fec_rdy : 1; 2188 uint8_t reserved : 7; 2189 uint32_t reserved1; 2190 }; 2191 2192 /** 2193 * DMUB command for DPIA tunnel control. 2194 */ 2195 struct dmub_rb_cmd_dig1_dpia_control { 2196 struct dmub_cmd_header header; 2197 struct dmub_cmd_dig_dpia_control_data dpia_control; 2198 }; 2199 2200 /** 2201 * SET_CONFIG Command Payload (deprecated) 2202 */ 2203 struct set_config_cmd_payload { 2204 uint8_t msg_type; /* set config message type */ 2205 uint8_t msg_data; /* set config message data */ 2206 }; 2207 2208 /** 2209 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2210 */ 2211 struct dmub_cmd_set_config_control_data { 2212 struct set_config_cmd_payload cmd_pkt; 2213 uint8_t instance; /* DPIA instance */ 2214 uint8_t immed_status; /* Immediate status returned in case of error */ 2215 }; 2216 2217 /** 2218 * SET_CONFIG Request Command Payload 2219 */ 2220 struct set_config_request_cmd_payload { 2221 uint8_t instance; /* DPIA instance */ 2222 uint8_t immed_status; /* Immediate status returned in case of error */ 2223 uint8_t msg_type; /* set config message type */ 2224 uint8_t reserved; 2225 uint32_t msg_data; /* set config message data */ 2226 }; 2227 2228 /** 2229 * DMUB command structure for SET_CONFIG command. 2230 */ 2231 struct dmub_rb_cmd_set_config_access { 2232 struct dmub_cmd_header header; /* header */ 2233 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2234 }; 2235 2236 /** 2237 * DMUB command structure for SET_CONFIG request command. 2238 */ 2239 struct dmub_rb_cmd_set_config_request { 2240 struct dmub_cmd_header header; /* header */ 2241 struct set_config_request_cmd_payload payload; /* set config request payload */ 2242 }; 2243 2244 /** 2245 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2246 */ 2247 struct dmub_cmd_mst_alloc_slots_control_data { 2248 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2249 uint8_t instance; /* DPIA instance */ 2250 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2251 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2252 }; 2253 2254 /** 2255 * DMUB command structure for SET_ command. 2256 */ 2257 struct dmub_rb_cmd_set_mst_alloc_slots { 2258 struct dmub_cmd_header header; /* header */ 2259 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2260 }; 2261 2262 /** 2263 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2264 */ 2265 struct dmub_cmd_tps_notification_data { 2266 uint8_t instance; /* DPIA instance */ 2267 uint8_t tps; /* requested training pattern */ 2268 uint8_t reserved1; 2269 uint8_t reserved2; 2270 }; 2271 2272 /** 2273 * DMUB command structure for SET_TPS_NOTIFICATION command. 2274 */ 2275 struct dmub_rb_cmd_set_tps_notification { 2276 struct dmub_cmd_header header; /* header */ 2277 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2278 }; 2279 2280 /** 2281 * DMUB command structure for DPIA HPD int enable control. 2282 */ 2283 struct dmub_rb_cmd_dpia_hpd_int_enable { 2284 struct dmub_cmd_header header; /* header */ 2285 uint32_t enable; /* dpia hpd interrupt enable */ 2286 }; 2287 2288 /** 2289 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2290 */ 2291 struct dmub_rb_cmd_dpphy_init { 2292 struct dmub_cmd_header header; /**< header */ 2293 uint8_t reserved[60]; /**< reserved bits */ 2294 }; 2295 2296 /** 2297 * enum dp_aux_request_action - DP AUX request command listing. 2298 * 2299 * 4 AUX request command bits are shifted to high nibble. 2300 */ 2301 enum dp_aux_request_action { 2302 /** I2C-over-AUX write request */ 2303 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2304 /** I2C-over-AUX read request */ 2305 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2306 /** I2C-over-AUX write status request */ 2307 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2308 /** I2C-over-AUX write request with MOT=1 */ 2309 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2310 /** I2C-over-AUX read request with MOT=1 */ 2311 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2312 /** I2C-over-AUX write status request with MOT=1 */ 2313 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2314 /** Native AUX write request */ 2315 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2316 /** Native AUX read request */ 2317 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2318 }; 2319 2320 /** 2321 * enum aux_return_code_type - DP AUX process return code listing. 2322 */ 2323 enum aux_return_code_type { 2324 /** AUX process succeeded */ 2325 AUX_RET_SUCCESS = 0, 2326 /** AUX process failed with unknown reason */ 2327 AUX_RET_ERROR_UNKNOWN, 2328 /** AUX process completed with invalid reply */ 2329 AUX_RET_ERROR_INVALID_REPLY, 2330 /** AUX process timed out */ 2331 AUX_RET_ERROR_TIMEOUT, 2332 /** HPD was low during AUX process */ 2333 AUX_RET_ERROR_HPD_DISCON, 2334 /** Failed to acquire AUX engine */ 2335 AUX_RET_ERROR_ENGINE_ACQUIRE, 2336 /** AUX request not supported */ 2337 AUX_RET_ERROR_INVALID_OPERATION, 2338 /** AUX process not available */ 2339 AUX_RET_ERROR_PROTOCOL_ERROR, 2340 }; 2341 2342 /** 2343 * enum aux_channel_type - DP AUX channel type listing. 2344 */ 2345 enum aux_channel_type { 2346 /** AUX thru Legacy DP AUX */ 2347 AUX_CHANNEL_LEGACY_DDC, 2348 /** AUX thru DPIA DP tunneling */ 2349 AUX_CHANNEL_DPIA 2350 }; 2351 2352 /** 2353 * struct aux_transaction_parameters - DP AUX request transaction data 2354 */ 2355 struct aux_transaction_parameters { 2356 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2357 uint8_t action; /**< enum dp_aux_request_action */ 2358 uint8_t length; /**< DP AUX request data length */ 2359 uint8_t reserved; /**< For future use */ 2360 uint32_t address; /**< DP AUX address */ 2361 uint8_t data[16]; /**< DP AUX write data */ 2362 }; 2363 2364 /** 2365 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2366 */ 2367 struct dmub_cmd_dp_aux_control_data { 2368 uint8_t instance; /**< AUX instance or DPIA instance */ 2369 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2370 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2371 uint8_t reserved0; /**< For future use */ 2372 uint16_t timeout; /**< timeout time in us */ 2373 uint16_t reserved1; /**< For future use */ 2374 enum aux_channel_type type; /**< enum aux_channel_type */ 2375 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2376 }; 2377 2378 /** 2379 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2380 */ 2381 struct dmub_rb_cmd_dp_aux_access { 2382 /** 2383 * Command header. 2384 */ 2385 struct dmub_cmd_header header; 2386 /** 2387 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2388 */ 2389 struct dmub_cmd_dp_aux_control_data aux_control; 2390 }; 2391 2392 /** 2393 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2394 */ 2395 struct dmub_rb_cmd_outbox1_enable { 2396 /** 2397 * Command header. 2398 */ 2399 struct dmub_cmd_header header; 2400 /** 2401 * enable: 0x0 -> disable outbox1 notification (default value) 2402 * 0x1 -> enable outbox1 notification 2403 */ 2404 uint32_t enable; 2405 }; 2406 2407 /* DP AUX Reply command - OutBox Cmd */ 2408 /** 2409 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2410 */ 2411 struct aux_reply_data { 2412 /** 2413 * Aux cmd 2414 */ 2415 uint8_t command; 2416 /** 2417 * Aux reply data length (max: 16 bytes) 2418 */ 2419 uint8_t length; 2420 /** 2421 * Alignment only 2422 */ 2423 uint8_t pad[2]; 2424 /** 2425 * Aux reply data 2426 */ 2427 uint8_t data[16]; 2428 }; 2429 2430 /** 2431 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2432 */ 2433 struct aux_reply_control_data { 2434 /** 2435 * Reserved for future use 2436 */ 2437 uint32_t handle; 2438 /** 2439 * Aux Instance 2440 */ 2441 uint8_t instance; 2442 /** 2443 * Aux transaction result: definition in enum aux_return_code_type 2444 */ 2445 uint8_t result; 2446 /** 2447 * Alignment only 2448 */ 2449 uint16_t pad; 2450 }; 2451 2452 /** 2453 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2454 */ 2455 struct dmub_rb_cmd_dp_aux_reply { 2456 /** 2457 * Command header. 2458 */ 2459 struct dmub_cmd_header header; 2460 /** 2461 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2462 */ 2463 struct aux_reply_control_data control; 2464 /** 2465 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2466 */ 2467 struct aux_reply_data reply_data; 2468 }; 2469 2470 /* DP HPD Notify command - OutBox Cmd */ 2471 /** 2472 * DP HPD Type 2473 */ 2474 enum dp_hpd_type { 2475 /** 2476 * Normal DP HPD 2477 */ 2478 DP_HPD = 0, 2479 /** 2480 * DP HPD short pulse 2481 */ 2482 DP_IRQ 2483 }; 2484 2485 /** 2486 * DP HPD Status 2487 */ 2488 enum dp_hpd_status { 2489 /** 2490 * DP_HPD status low 2491 */ 2492 DP_HPD_UNPLUG = 0, 2493 /** 2494 * DP_HPD status high 2495 */ 2496 DP_HPD_PLUG 2497 }; 2498 2499 /** 2500 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2501 */ 2502 struct dp_hpd_data { 2503 /** 2504 * DP HPD instance 2505 */ 2506 uint8_t instance; 2507 /** 2508 * HPD type 2509 */ 2510 uint8_t hpd_type; 2511 /** 2512 * HPD status: only for type: DP_HPD to indicate status 2513 */ 2514 uint8_t hpd_status; 2515 /** 2516 * Alignment only 2517 */ 2518 uint8_t pad; 2519 }; 2520 2521 /** 2522 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2523 */ 2524 struct dmub_rb_cmd_dp_hpd_notify { 2525 /** 2526 * Command header. 2527 */ 2528 struct dmub_cmd_header header; 2529 /** 2530 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2531 */ 2532 struct dp_hpd_data hpd_data; 2533 }; 2534 2535 /** 2536 * Definition of a SET_CONFIG reply from DPOA. 2537 */ 2538 enum set_config_status { 2539 SET_CONFIG_PENDING = 0, 2540 SET_CONFIG_ACK_RECEIVED, 2541 SET_CONFIG_RX_TIMEOUT, 2542 SET_CONFIG_UNKNOWN_ERROR, 2543 }; 2544 2545 /** 2546 * Definition of a set_config reply 2547 */ 2548 struct set_config_reply_control_data { 2549 uint8_t instance; /* DPIA Instance */ 2550 uint8_t status; /* Set Config reply */ 2551 uint16_t pad; /* Alignment */ 2552 }; 2553 2554 /** 2555 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2556 */ 2557 struct dmub_rb_cmd_dp_set_config_reply { 2558 struct dmub_cmd_header header; 2559 struct set_config_reply_control_data set_config_reply_control; 2560 }; 2561 2562 /** 2563 * Definition of a DPIA notification header 2564 */ 2565 struct dpia_notification_header { 2566 uint8_t instance; /**< DPIA Instance */ 2567 uint8_t reserved[3]; 2568 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2569 }; 2570 2571 /** 2572 * Definition of the common data struct of DPIA notification 2573 */ 2574 struct dpia_notification_common { 2575 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2576 - sizeof(struct dpia_notification_header)]; 2577 }; 2578 2579 /** 2580 * Definition of a DPIA notification data 2581 */ 2582 struct dpia_bw_allocation_notify_data { 2583 union { 2584 struct { 2585 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2586 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2587 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2588 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2589 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2590 uint16_t reserved: 11; /**< Reserved */ 2591 } bits; 2592 2593 uint16_t flags; 2594 }; 2595 2596 uint8_t cm_id; /**< CM ID */ 2597 uint8_t group_id; /**< Group ID */ 2598 uint8_t granularity; /**< BW Allocation Granularity */ 2599 uint8_t estimated_bw; /**< Estimated_BW */ 2600 uint8_t allocated_bw; /**< Allocated_BW */ 2601 uint8_t reserved; 2602 }; 2603 2604 /** 2605 * union dpia_notify_data_type - DPIA Notification in Outbox command 2606 */ 2607 union dpia_notification_data { 2608 /** 2609 * DPIA Notification for common data struct 2610 */ 2611 struct dpia_notification_common common_data; 2612 2613 /** 2614 * DPIA Notification for DP BW Allocation support 2615 */ 2616 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2617 }; 2618 2619 /** 2620 * Definition of a DPIA notification payload 2621 */ 2622 struct dpia_notification_payload { 2623 struct dpia_notification_header header; 2624 union dpia_notification_data data; /**< DPIA notification payload data */ 2625 }; 2626 2627 /** 2628 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2629 */ 2630 struct dmub_rb_cmd_dpia_notification { 2631 struct dmub_cmd_header header; /**< DPIA notification header */ 2632 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2633 }; 2634 2635 /** 2636 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2637 */ 2638 struct dmub_cmd_hpd_state_query_data { 2639 uint8_t instance; /**< HPD instance or DPIA instance */ 2640 uint8_t result; /**< For returning HPD state */ 2641 uint16_t pad; /** < Alignment */ 2642 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2643 enum aux_return_code_type status; /**< for returning the status of command */ 2644 }; 2645 2646 /** 2647 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2648 */ 2649 struct dmub_rb_cmd_query_hpd_state { 2650 /** 2651 * Command header. 2652 */ 2653 struct dmub_cmd_header header; 2654 /** 2655 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2656 */ 2657 struct dmub_cmd_hpd_state_query_data data; 2658 }; 2659 2660 /** 2661 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2662 */ 2663 struct dmub_rb_cmd_hpd_sense_notify_data { 2664 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2665 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2666 }; 2667 2668 /** 2669 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2670 */ 2671 struct dmub_rb_cmd_hpd_sense_notify { 2672 struct dmub_cmd_header header; /**< header */ 2673 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2674 }; 2675 2676 /* 2677 * Command IDs should be treated as stable ABI. 2678 * Do not reuse or modify IDs. 2679 */ 2680 2681 /** 2682 * PSR command sub-types. 2683 */ 2684 enum dmub_cmd_psr_type { 2685 /** 2686 * Set PSR version support. 2687 */ 2688 DMUB_CMD__PSR_SET_VERSION = 0, 2689 /** 2690 * Copy driver-calculated parameters to PSR state. 2691 */ 2692 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2693 /** 2694 * Enable PSR. 2695 */ 2696 DMUB_CMD__PSR_ENABLE = 2, 2697 2698 /** 2699 * Disable PSR. 2700 */ 2701 DMUB_CMD__PSR_DISABLE = 3, 2702 2703 /** 2704 * Set PSR level. 2705 * PSR level is a 16-bit value dicated by driver that 2706 * will enable/disable different functionality. 2707 */ 2708 DMUB_CMD__PSR_SET_LEVEL = 4, 2709 2710 /** 2711 * Forces PSR enabled until an explicit PSR disable call. 2712 */ 2713 DMUB_CMD__PSR_FORCE_STATIC = 5, 2714 /** 2715 * Set vtotal in psr active for FreeSync PSR. 2716 */ 2717 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2718 /** 2719 * Set PSR power option 2720 */ 2721 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2722 }; 2723 2724 /** 2725 * Different PSR residency modes. 2726 * Different modes change the definition of PSR residency. 2727 */ 2728 enum psr_residency_mode { 2729 PSR_RESIDENCY_MODE_PHY = 0, 2730 PSR_RESIDENCY_MODE_ALPM, 2731 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2732 /* Do not add below. */ 2733 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2734 }; 2735 2736 enum dmub_cmd_fams_type { 2737 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2738 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2739 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2740 /** 2741 * For SubVP set manual trigger in FW because it 2742 * triggers DRR_UPDATE_PENDING which SubVP relies 2743 * on (for any SubVP cases that use a DRR display) 2744 */ 2745 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2746 DMUB_CMD__FAMS2_CONFIG = 4, 2747 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2748 DMUB_CMD__FAMS2_FLIP = 6, 2749 }; 2750 2751 /** 2752 * PSR versions. 2753 */ 2754 enum psr_version { 2755 /** 2756 * PSR version 1. 2757 */ 2758 PSR_VERSION_1 = 0, 2759 /** 2760 * Freesync PSR SU. 2761 */ 2762 PSR_VERSION_SU_1 = 1, 2763 /** 2764 * PSR not supported. 2765 */ 2766 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2767 }; 2768 2769 /** 2770 * PHY Link rate for DP. 2771 */ 2772 enum phy_link_rate { 2773 /** 2774 * not supported. 2775 */ 2776 PHY_RATE_UNKNOWN = 0, 2777 /** 2778 * Rate_1 (RBR) - 1.62 Gbps/Lane 2779 */ 2780 PHY_RATE_162 = 1, 2781 /** 2782 * Rate_2 - 2.16 Gbps/Lane 2783 */ 2784 PHY_RATE_216 = 2, 2785 /** 2786 * Rate_3 - 2.43 Gbps/Lane 2787 */ 2788 PHY_RATE_243 = 3, 2789 /** 2790 * Rate_4 (HBR) - 2.70 Gbps/Lane 2791 */ 2792 PHY_RATE_270 = 4, 2793 /** 2794 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2795 */ 2796 PHY_RATE_324 = 5, 2797 /** 2798 * Rate_6 - 4.32 Gbps/Lane 2799 */ 2800 PHY_RATE_432 = 6, 2801 /** 2802 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2803 */ 2804 PHY_RATE_540 = 7, 2805 /** 2806 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2807 */ 2808 PHY_RATE_810 = 8, 2809 /** 2810 * UHBR10 - 10.0 Gbps/Lane 2811 */ 2812 PHY_RATE_1000 = 9, 2813 /** 2814 * UHBR13.5 - 13.5 Gbps/Lane 2815 */ 2816 PHY_RATE_1350 = 10, 2817 /** 2818 * UHBR10 - 20.0 Gbps/Lane 2819 */ 2820 PHY_RATE_2000 = 11, 2821 2822 PHY_RATE_675 = 12, 2823 /** 2824 * Rate 12 - 6.75 Gbps/Lane 2825 */ 2826 }; 2827 2828 /** 2829 * enum dmub_phy_fsm_state - PHY FSM states. 2830 * PHY FSM state to transit to during PSR enable/disable. 2831 */ 2832 enum dmub_phy_fsm_state { 2833 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2834 DMUB_PHY_FSM_RESET, 2835 DMUB_PHY_FSM_RESET_RELEASED, 2836 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2837 DMUB_PHY_FSM_INITIALIZED, 2838 DMUB_PHY_FSM_CALIBRATED, 2839 DMUB_PHY_FSM_CALIBRATED_LP, 2840 DMUB_PHY_FSM_CALIBRATED_PG, 2841 DMUB_PHY_FSM_POWER_DOWN, 2842 DMUB_PHY_FSM_PLL_EN, 2843 DMUB_PHY_FSM_TX_EN, 2844 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2845 DMUB_PHY_FSM_FAST_LP, 2846 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2847 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2848 DMUB_PHY_FSM_P2_PLL_OFF, 2849 DMUB_PHY_FSM_P2_PLL_ON, 2850 }; 2851 2852 /** 2853 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2854 */ 2855 struct dmub_cmd_psr_copy_settings_data { 2856 /** 2857 * Flags that can be set by driver to change some PSR behaviour. 2858 */ 2859 union dmub_psr_debug_flags debug; 2860 /** 2861 * 16-bit value dicated by driver that will enable/disable different functionality. 2862 */ 2863 uint16_t psr_level; 2864 /** 2865 * DPP HW instance. 2866 */ 2867 uint8_t dpp_inst; 2868 /** 2869 * MPCC HW instance. 2870 * Not used in dmub fw, 2871 * dmub fw will get active opp by reading odm registers. 2872 */ 2873 uint8_t mpcc_inst; 2874 /** 2875 * OPP HW instance. 2876 * Not used in dmub fw, 2877 * dmub fw will get active opp by reading odm registers. 2878 */ 2879 uint8_t opp_inst; 2880 /** 2881 * OTG HW instance. 2882 */ 2883 uint8_t otg_inst; 2884 /** 2885 * DIG FE HW instance. 2886 */ 2887 uint8_t digfe_inst; 2888 /** 2889 * DIG BE HW instance. 2890 */ 2891 uint8_t digbe_inst; 2892 /** 2893 * DP PHY HW instance. 2894 */ 2895 uint8_t dpphy_inst; 2896 /** 2897 * AUX HW instance. 2898 */ 2899 uint8_t aux_inst; 2900 /** 2901 * Determines if SMU optimzations are enabled/disabled. 2902 */ 2903 uint8_t smu_optimizations_en; 2904 /** 2905 * Unused. 2906 * TODO: Remove. 2907 */ 2908 uint8_t frame_delay; 2909 /** 2910 * If RFB setup time is greater than the total VBLANK time, 2911 * it is not possible for the sink to capture the video frame 2912 * in the same frame the SDP is sent. In this case, 2913 * the frame capture indication bit should be set and an extra 2914 * static frame should be transmitted to the sink. 2915 */ 2916 uint8_t frame_cap_ind; 2917 /** 2918 * Granularity of Y offset supported by sink. 2919 */ 2920 uint8_t su_y_granularity; 2921 /** 2922 * Indicates whether sink should start capturing 2923 * immediately following active scan line, 2924 * or starting with the 2nd active scan line. 2925 */ 2926 uint8_t line_capture_indication; 2927 /** 2928 * Multi-display optimizations are implemented on certain ASICs. 2929 */ 2930 uint8_t multi_disp_optimizations_en; 2931 /** 2932 * The last possible line SDP may be transmitted without violating 2933 * the RFB setup time or entering the active video frame. 2934 */ 2935 uint16_t init_sdp_deadline; 2936 /** 2937 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2938 */ 2939 uint8_t rate_control_caps ; 2940 /* 2941 * Force PSRSU always doing full frame update 2942 */ 2943 uint8_t force_ffu_mode; 2944 /** 2945 * Length of each horizontal line in us. 2946 */ 2947 uint32_t line_time_in_us; 2948 /** 2949 * FEC enable status in driver 2950 */ 2951 uint8_t fec_enable_status; 2952 /** 2953 * FEC re-enable delay when PSR exit. 2954 * unit is 100us, range form 0~255(0xFF). 2955 */ 2956 uint8_t fec_enable_delay_in100us; 2957 /** 2958 * PSR control version. 2959 */ 2960 uint8_t cmd_version; 2961 /** 2962 * Panel Instance. 2963 * Panel instance to identify which psr_state to use 2964 * Currently the support is only for 0 or 1 2965 */ 2966 uint8_t panel_inst; 2967 /* 2968 * DSC enable status in driver 2969 */ 2970 uint8_t dsc_enable_status; 2971 /* 2972 * Use FSM state for PSR power up/down 2973 */ 2974 uint8_t use_phy_fsm; 2975 /** 2976 * frame delay for frame re-lock 2977 */ 2978 uint8_t relock_delay_frame_cnt; 2979 /** 2980 * esd recovery indicate. 2981 */ 2982 uint8_t esd_recovery; 2983 /** 2984 * DSC Slice height. 2985 */ 2986 uint16_t dsc_slice_height; 2987 /** 2988 * Some panels request main link off before xth vertical line 2989 */ 2990 uint16_t poweroff_before_vertical_line; 2991 }; 2992 2993 /** 2994 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2995 */ 2996 struct dmub_rb_cmd_psr_copy_settings { 2997 /** 2998 * Command header. 2999 */ 3000 struct dmub_cmd_header header; 3001 /** 3002 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3003 */ 3004 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3005 }; 3006 3007 /** 3008 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3009 */ 3010 struct dmub_cmd_psr_set_level_data { 3011 /** 3012 * 16-bit value dicated by driver that will enable/disable different functionality. 3013 */ 3014 uint16_t psr_level; 3015 /** 3016 * PSR control version. 3017 */ 3018 uint8_t cmd_version; 3019 /** 3020 * Panel Instance. 3021 * Panel instance to identify which psr_state to use 3022 * Currently the support is only for 0 or 1 3023 */ 3024 uint8_t panel_inst; 3025 }; 3026 3027 /** 3028 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3029 */ 3030 struct dmub_rb_cmd_psr_set_level { 3031 /** 3032 * Command header. 3033 */ 3034 struct dmub_cmd_header header; 3035 /** 3036 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3037 */ 3038 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3039 }; 3040 3041 struct dmub_rb_cmd_psr_enable_data { 3042 /** 3043 * PSR control version. 3044 */ 3045 uint8_t cmd_version; 3046 /** 3047 * Panel Instance. 3048 * Panel instance to identify which psr_state to use 3049 * Currently the support is only for 0 or 1 3050 */ 3051 uint8_t panel_inst; 3052 /** 3053 * Phy state to enter. 3054 * Values to use are defined in dmub_phy_fsm_state 3055 */ 3056 uint8_t phy_fsm_state; 3057 /** 3058 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3059 * Set this using enum phy_link_rate. 3060 * This does not support HDMI/DP2 for now. 3061 */ 3062 uint8_t phy_rate; 3063 }; 3064 3065 /** 3066 * Definition of a DMUB_CMD__PSR_ENABLE command. 3067 * PSR enable/disable is controlled using the sub_type. 3068 */ 3069 struct dmub_rb_cmd_psr_enable { 3070 /** 3071 * Command header. 3072 */ 3073 struct dmub_cmd_header header; 3074 3075 struct dmub_rb_cmd_psr_enable_data data; 3076 }; 3077 3078 /** 3079 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3080 */ 3081 struct dmub_cmd_psr_set_version_data { 3082 /** 3083 * PSR version that FW should implement. 3084 */ 3085 enum psr_version version; 3086 /** 3087 * PSR control version. 3088 */ 3089 uint8_t cmd_version; 3090 /** 3091 * Panel Instance. 3092 * Panel instance to identify which psr_state to use 3093 * Currently the support is only for 0 or 1 3094 */ 3095 uint8_t panel_inst; 3096 /** 3097 * Explicit padding to 4 byte boundary. 3098 */ 3099 uint8_t pad[2]; 3100 }; 3101 3102 /** 3103 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3104 */ 3105 struct dmub_rb_cmd_psr_set_version { 3106 /** 3107 * Command header. 3108 */ 3109 struct dmub_cmd_header header; 3110 /** 3111 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3112 */ 3113 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3114 }; 3115 3116 struct dmub_cmd_psr_force_static_data { 3117 /** 3118 * PSR control version. 3119 */ 3120 uint8_t cmd_version; 3121 /** 3122 * Panel Instance. 3123 * Panel instance to identify which psr_state to use 3124 * Currently the support is only for 0 or 1 3125 */ 3126 uint8_t panel_inst; 3127 /** 3128 * Explicit padding to 4 byte boundary. 3129 */ 3130 uint8_t pad[2]; 3131 }; 3132 3133 /** 3134 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3135 */ 3136 struct dmub_rb_cmd_psr_force_static { 3137 /** 3138 * Command header. 3139 */ 3140 struct dmub_cmd_header header; 3141 /** 3142 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3143 */ 3144 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3145 }; 3146 3147 /** 3148 * PSR SU debug flags. 3149 */ 3150 union dmub_psr_su_debug_flags { 3151 /** 3152 * PSR SU debug flags. 3153 */ 3154 struct { 3155 /** 3156 * Update dirty rect in SW only. 3157 */ 3158 uint8_t update_dirty_rect_only : 1; 3159 /** 3160 * Reset the cursor/plane state before processing the call. 3161 */ 3162 uint8_t reset_state : 1; 3163 } bitfields; 3164 3165 /** 3166 * Union for debug flags. 3167 */ 3168 uint32_t u32All; 3169 }; 3170 3171 /** 3172 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3173 * This triggers a selective update for PSR SU. 3174 */ 3175 struct dmub_cmd_update_dirty_rect_data { 3176 /** 3177 * Dirty rects from OS. 3178 */ 3179 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3180 /** 3181 * PSR SU debug flags. 3182 */ 3183 union dmub_psr_su_debug_flags debug_flags; 3184 /** 3185 * OTG HW instance. 3186 */ 3187 uint8_t pipe_idx; 3188 /** 3189 * Number of dirty rects. 3190 */ 3191 uint8_t dirty_rect_count; 3192 /** 3193 * PSR control version. 3194 */ 3195 uint8_t cmd_version; 3196 /** 3197 * Panel Instance. 3198 * Panel instance to identify which psr_state to use 3199 * Currently the support is only for 0 or 1 3200 */ 3201 uint8_t panel_inst; 3202 }; 3203 3204 /** 3205 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3206 */ 3207 struct dmub_rb_cmd_update_dirty_rect { 3208 /** 3209 * Command header. 3210 */ 3211 struct dmub_cmd_header header; 3212 /** 3213 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3214 */ 3215 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3216 }; 3217 3218 /** 3219 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3220 */ 3221 union dmub_reg_cursor_control_cfg { 3222 struct { 3223 uint32_t cur_enable: 1; 3224 uint32_t reser0: 3; 3225 uint32_t cur_2x_magnify: 1; 3226 uint32_t reser1: 3; 3227 uint32_t mode: 3; 3228 uint32_t reser2: 5; 3229 uint32_t pitch: 2; 3230 uint32_t reser3: 6; 3231 uint32_t line_per_chunk: 5; 3232 uint32_t reser4: 3; 3233 } bits; 3234 uint32_t raw; 3235 }; 3236 struct dmub_cursor_position_cache_hubp { 3237 union dmub_reg_cursor_control_cfg cur_ctl; 3238 union dmub_reg_position_cfg { 3239 struct { 3240 uint32_t cur_x_pos: 16; 3241 uint32_t cur_y_pos: 16; 3242 } bits; 3243 uint32_t raw; 3244 } position; 3245 union dmub_reg_hot_spot_cfg { 3246 struct { 3247 uint32_t hot_x: 16; 3248 uint32_t hot_y: 16; 3249 } bits; 3250 uint32_t raw; 3251 } hot_spot; 3252 union dmub_reg_dst_offset_cfg { 3253 struct { 3254 uint32_t dst_x_offset: 13; 3255 uint32_t reserved: 19; 3256 } bits; 3257 uint32_t raw; 3258 } dst_offset; 3259 }; 3260 3261 union dmub_reg_cur0_control_cfg { 3262 struct { 3263 uint32_t cur0_enable: 1; 3264 uint32_t expansion_mode: 1; 3265 uint32_t reser0: 1; 3266 uint32_t cur0_rom_en: 1; 3267 uint32_t mode: 3; 3268 uint32_t reserved: 25; 3269 } bits; 3270 uint32_t raw; 3271 }; 3272 struct dmub_cursor_position_cache_dpp { 3273 union dmub_reg_cur0_control_cfg cur0_ctl; 3274 }; 3275 struct dmub_cursor_position_cfg { 3276 struct dmub_cursor_position_cache_hubp pHubp; 3277 struct dmub_cursor_position_cache_dpp pDpp; 3278 uint8_t pipe_idx; 3279 /* 3280 * Padding is required. To be 4 Bytes Aligned. 3281 */ 3282 uint8_t padding[3]; 3283 }; 3284 3285 struct dmub_cursor_attribute_cache_hubp { 3286 uint32_t SURFACE_ADDR_HIGH; 3287 uint32_t SURFACE_ADDR; 3288 union dmub_reg_cursor_control_cfg cur_ctl; 3289 union dmub_reg_cursor_size_cfg { 3290 struct { 3291 uint32_t width: 16; 3292 uint32_t height: 16; 3293 } bits; 3294 uint32_t raw; 3295 } size; 3296 union dmub_reg_cursor_settings_cfg { 3297 struct { 3298 uint32_t dst_y_offset: 8; 3299 uint32_t chunk_hdl_adjust: 2; 3300 uint32_t reserved: 22; 3301 } bits; 3302 uint32_t raw; 3303 } settings; 3304 }; 3305 struct dmub_cursor_attribute_cache_dpp { 3306 union dmub_reg_cur0_control_cfg cur0_ctl; 3307 }; 3308 struct dmub_cursor_attributes_cfg { 3309 struct dmub_cursor_attribute_cache_hubp aHubp; 3310 struct dmub_cursor_attribute_cache_dpp aDpp; 3311 }; 3312 3313 struct dmub_cmd_update_cursor_payload0 { 3314 /** 3315 * Cursor dirty rects. 3316 */ 3317 struct dmub_rect cursor_rect; 3318 /** 3319 * PSR SU debug flags. 3320 */ 3321 union dmub_psr_su_debug_flags debug_flags; 3322 /** 3323 * Cursor enable/disable. 3324 */ 3325 uint8_t enable; 3326 /** 3327 * OTG HW instance. 3328 */ 3329 uint8_t pipe_idx; 3330 /** 3331 * PSR control version. 3332 */ 3333 uint8_t cmd_version; 3334 /** 3335 * Panel Instance. 3336 * Panel instance to identify which psr_state to use 3337 * Currently the support is only for 0 or 1 3338 */ 3339 uint8_t panel_inst; 3340 /** 3341 * Cursor Position Register. 3342 * Registers contains Hubp & Dpp modules 3343 */ 3344 struct dmub_cursor_position_cfg position_cfg; 3345 }; 3346 3347 struct dmub_cmd_update_cursor_payload1 { 3348 struct dmub_cursor_attributes_cfg attribute_cfg; 3349 }; 3350 3351 union dmub_cmd_update_cursor_info_data { 3352 struct dmub_cmd_update_cursor_payload0 payload0; 3353 struct dmub_cmd_update_cursor_payload1 payload1; 3354 }; 3355 /** 3356 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3357 */ 3358 struct dmub_rb_cmd_update_cursor_info { 3359 /** 3360 * Command header. 3361 */ 3362 struct dmub_cmd_header header; 3363 /** 3364 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3365 */ 3366 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3367 }; 3368 3369 /** 3370 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3371 */ 3372 struct dmub_cmd_psr_set_vtotal_data { 3373 /** 3374 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3375 */ 3376 uint16_t psr_vtotal_idle; 3377 /** 3378 * PSR control version. 3379 */ 3380 uint8_t cmd_version; 3381 /** 3382 * Panel Instance. 3383 * Panel instance to identify which psr_state to use 3384 * Currently the support is only for 0 or 1 3385 */ 3386 uint8_t panel_inst; 3387 /* 3388 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3389 */ 3390 uint16_t psr_vtotal_su; 3391 /** 3392 * Explicit padding to 4 byte boundary. 3393 */ 3394 uint8_t pad2[2]; 3395 }; 3396 3397 /** 3398 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3399 */ 3400 struct dmub_rb_cmd_psr_set_vtotal { 3401 /** 3402 * Command header. 3403 */ 3404 struct dmub_cmd_header header; 3405 /** 3406 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3407 */ 3408 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3409 }; 3410 3411 /** 3412 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3413 */ 3414 struct dmub_cmd_psr_set_power_opt_data { 3415 /** 3416 * PSR control version. 3417 */ 3418 uint8_t cmd_version; 3419 /** 3420 * Panel Instance. 3421 * Panel instance to identify which psr_state to use 3422 * Currently the support is only for 0 or 1 3423 */ 3424 uint8_t panel_inst; 3425 /** 3426 * Explicit padding to 4 byte boundary. 3427 */ 3428 uint8_t pad[2]; 3429 /** 3430 * PSR power option 3431 */ 3432 uint32_t power_opt; 3433 }; 3434 3435 /** 3436 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3437 */ 3438 struct dmub_rb_cmd_psr_set_power_opt { 3439 /** 3440 * Command header. 3441 */ 3442 struct dmub_cmd_header header; 3443 /** 3444 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3445 */ 3446 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3447 }; 3448 3449 /** 3450 * Definition of Replay Residency GPINT command. 3451 * Bit[0] - Residency mode for Revision 0 3452 * Bit[1] - Enable/Disable state 3453 * Bit[2-3] - Revision number 3454 * Bit[4-7] - Residency mode for Revision 1 3455 * Bit[8] - Panel instance 3456 * Bit[9-15] - Reserved 3457 */ 3458 3459 enum pr_residency_mode { 3460 PR_RESIDENCY_MODE_PHY = 0x0, 3461 PR_RESIDENCY_MODE_ALPM, 3462 PR_RESIDENCY_MODE_IPS2, 3463 PR_RESIDENCY_MODE_FRAME_CNT, 3464 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3465 }; 3466 3467 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3468 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3469 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3470 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3471 3472 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3473 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3474 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3475 3476 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3477 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3478 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3479 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3480 3481 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3482 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3483 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3484 3485 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3486 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3487 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3488 3489 /** 3490 * Definition of a replay_state. 3491 */ 3492 enum replay_state { 3493 REPLAY_STATE_0 = 0x0, 3494 REPLAY_STATE_1 = 0x10, 3495 REPLAY_STATE_1A = 0x11, 3496 REPLAY_STATE_2 = 0x20, 3497 REPLAY_STATE_2A = 0x21, 3498 REPLAY_STATE_3 = 0x30, 3499 REPLAY_STATE_3INIT = 0x31, 3500 REPLAY_STATE_4 = 0x40, 3501 REPLAY_STATE_4A = 0x41, 3502 REPLAY_STATE_4B = 0x42, 3503 REPLAY_STATE_4C = 0x43, 3504 REPLAY_STATE_4D = 0x44, 3505 REPLAY_STATE_4E = 0x45, 3506 REPLAY_STATE_4B_LOCKED = 0x4A, 3507 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3508 REPLAY_STATE_5 = 0x50, 3509 REPLAY_STATE_5A = 0x51, 3510 REPLAY_STATE_5B = 0x52, 3511 REPLAY_STATE_5A_LOCKED = 0x5A, 3512 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3513 REPLAY_STATE_6 = 0x60, 3514 REPLAY_STATE_6A = 0x61, 3515 REPLAY_STATE_6B = 0x62, 3516 REPLAY_STATE_INVALID = 0xFF, 3517 }; 3518 3519 /** 3520 * Replay command sub-types. 3521 */ 3522 enum dmub_cmd_replay_type { 3523 /** 3524 * Copy driver-calculated parameters to REPLAY state. 3525 */ 3526 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3527 /** 3528 * Enable REPLAY. 3529 */ 3530 DMUB_CMD__REPLAY_ENABLE = 1, 3531 /** 3532 * Set Replay power option. 3533 */ 3534 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3535 /** 3536 * Set coasting vtotal. 3537 */ 3538 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3539 /** 3540 * Set power opt and coasting vtotal. 3541 */ 3542 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3543 /** 3544 * Set disabled iiming sync. 3545 */ 3546 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3547 /** 3548 * Set Residency Frameupdate Timer. 3549 */ 3550 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3551 /** 3552 * Set pseudo vtotal 3553 */ 3554 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3555 /** 3556 * Set adaptive sync sdp enabled 3557 */ 3558 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3559 /** 3560 * Set Replay General command. 3561 */ 3562 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3563 }; 3564 3565 /** 3566 * Replay general command sub-types. 3567 */ 3568 enum dmub_cmd_replay_general_subtype { 3569 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3570 /** 3571 * TODO: For backward compatible, allow new command only. 3572 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3573 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3574 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3575 */ 3576 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3577 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3578 }; 3579 3580 /** 3581 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3582 */ 3583 struct dmub_cmd_replay_copy_settings_data { 3584 /** 3585 * Flags that can be set by driver to change some replay behaviour. 3586 */ 3587 union replay_debug_flags debug; 3588 3589 /** 3590 * @flags: Flags used to determine feature functionality. 3591 */ 3592 union replay_hw_flags flags; 3593 3594 /** 3595 * DPP HW instance. 3596 */ 3597 uint8_t dpp_inst; 3598 /** 3599 * OTG HW instance. 3600 */ 3601 uint8_t otg_inst; 3602 /** 3603 * DIG FE HW instance. 3604 */ 3605 uint8_t digfe_inst; 3606 /** 3607 * DIG BE HW instance. 3608 */ 3609 uint8_t digbe_inst; 3610 /** 3611 * AUX HW instance. 3612 */ 3613 uint8_t aux_inst; 3614 /** 3615 * Panel Instance. 3616 * Panel isntance to identify which psr_state to use 3617 * Currently the support is only for 0 or 1 3618 */ 3619 uint8_t panel_inst; 3620 /** 3621 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3622 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3623 */ 3624 uint8_t pixel_deviation_per_line; 3625 /** 3626 * @max_deviation_line: The max number of deviation line that can keep the timing 3627 * synchronized between the Source and Sink during Replay normal sleep mode. 3628 */ 3629 uint8_t max_deviation_line; 3630 /** 3631 * Length of each horizontal line in ns. 3632 */ 3633 uint32_t line_time_in_ns; 3634 /** 3635 * PHY instance. 3636 */ 3637 uint8_t dpphy_inst; 3638 /** 3639 * Determines if SMU optimzations are enabled/disabled. 3640 */ 3641 uint8_t smu_optimizations_en; 3642 /** 3643 * Determines if timing sync are enabled/disabled. 3644 */ 3645 uint8_t replay_timing_sync_supported; 3646 /* 3647 * Use FSM state for Replay power up/down 3648 */ 3649 uint8_t use_phy_fsm; 3650 }; 3651 3652 /** 3653 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3654 */ 3655 struct dmub_rb_cmd_replay_copy_settings { 3656 /** 3657 * Command header. 3658 */ 3659 struct dmub_cmd_header header; 3660 /** 3661 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3662 */ 3663 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3664 }; 3665 3666 /** 3667 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3668 */ 3669 enum replay_enable { 3670 /** 3671 * Disable REPLAY. 3672 */ 3673 REPLAY_DISABLE = 0, 3674 /** 3675 * Enable REPLAY. 3676 */ 3677 REPLAY_ENABLE = 1, 3678 }; 3679 3680 /** 3681 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3682 */ 3683 struct dmub_rb_cmd_replay_enable_data { 3684 /** 3685 * Replay enable or disable. 3686 */ 3687 uint8_t enable; 3688 /** 3689 * Panel Instance. 3690 * Panel isntance to identify which replay_state to use 3691 * Currently the support is only for 0 or 1 3692 */ 3693 uint8_t panel_inst; 3694 /** 3695 * Phy state to enter. 3696 * Values to use are defined in dmub_phy_fsm_state 3697 */ 3698 uint8_t phy_fsm_state; 3699 /** 3700 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3701 * Set this using enum phy_link_rate. 3702 * This does not support HDMI/DP2 for now. 3703 */ 3704 uint8_t phy_rate; 3705 }; 3706 3707 /** 3708 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3709 * Replay enable/disable is controlled using action in data. 3710 */ 3711 struct dmub_rb_cmd_replay_enable { 3712 /** 3713 * Command header. 3714 */ 3715 struct dmub_cmd_header header; 3716 3717 struct dmub_rb_cmd_replay_enable_data data; 3718 }; 3719 3720 /** 3721 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3722 */ 3723 struct dmub_cmd_replay_set_power_opt_data { 3724 /** 3725 * Panel Instance. 3726 * Panel isntance to identify which replay_state to use 3727 * Currently the support is only for 0 or 1 3728 */ 3729 uint8_t panel_inst; 3730 /** 3731 * Explicit padding to 4 byte boundary. 3732 */ 3733 uint8_t pad[3]; 3734 /** 3735 * REPLAY power option 3736 */ 3737 uint32_t power_opt; 3738 }; 3739 3740 /** 3741 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3742 */ 3743 struct dmub_cmd_replay_set_timing_sync_data { 3744 /** 3745 * Panel Instance. 3746 * Panel isntance to identify which replay_state to use 3747 * Currently the support is only for 0 or 1 3748 */ 3749 uint8_t panel_inst; 3750 /** 3751 * REPLAY set_timing_sync 3752 */ 3753 uint8_t timing_sync_supported; 3754 /** 3755 * Explicit padding to 4 byte boundary. 3756 */ 3757 uint8_t pad[2]; 3758 }; 3759 3760 /** 3761 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3762 */ 3763 struct dmub_cmd_replay_set_pseudo_vtotal { 3764 /** 3765 * Panel Instance. 3766 * Panel isntance to identify which replay_state to use 3767 * Currently the support is only for 0 or 1 3768 */ 3769 uint8_t panel_inst; 3770 /** 3771 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3772 */ 3773 uint16_t vtotal; 3774 /** 3775 * Explicit padding to 4 byte boundary. 3776 */ 3777 uint8_t pad; 3778 }; 3779 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3780 /** 3781 * Panel Instance. 3782 * Panel isntance to identify which replay_state to use 3783 * Currently the support is only for 0 or 1 3784 */ 3785 uint8_t panel_inst; 3786 /** 3787 * enabled: set adaptive sync sdp enabled 3788 */ 3789 uint8_t force_disabled; 3790 3791 uint8_t pad[2]; 3792 }; 3793 struct dmub_cmd_replay_set_general_cmd_data { 3794 /** 3795 * Panel Instance. 3796 * Panel isntance to identify which replay_state to use 3797 * Currently the support is only for 0 or 1 3798 */ 3799 uint8_t panel_inst; 3800 /** 3801 * subtype: replay general cmd sub type 3802 */ 3803 uint8_t subtype; 3804 3805 uint8_t pad[2]; 3806 /** 3807 * config data with param1 and param2 3808 */ 3809 uint32_t param1; 3810 3811 uint32_t param2; 3812 }; 3813 3814 /** 3815 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3816 */ 3817 struct dmub_rb_cmd_replay_set_power_opt { 3818 /** 3819 * Command header. 3820 */ 3821 struct dmub_cmd_header header; 3822 /** 3823 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3824 */ 3825 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3826 }; 3827 3828 /** 3829 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3830 */ 3831 struct dmub_cmd_replay_set_coasting_vtotal_data { 3832 /** 3833 * 16-bit value dicated by driver that indicates the coasting vtotal. 3834 */ 3835 uint16_t coasting_vtotal; 3836 /** 3837 * REPLAY control version. 3838 */ 3839 uint8_t cmd_version; 3840 /** 3841 * Panel Instance. 3842 * Panel isntance to identify which replay_state to use 3843 * Currently the support is only for 0 or 1 3844 */ 3845 uint8_t panel_inst; 3846 /** 3847 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3848 */ 3849 uint16_t coasting_vtotal_high; 3850 /** 3851 * Explicit padding to 4 byte boundary. 3852 */ 3853 uint8_t pad[2]; 3854 }; 3855 3856 /** 3857 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3858 */ 3859 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3860 /** 3861 * Command header. 3862 */ 3863 struct dmub_cmd_header header; 3864 /** 3865 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3866 */ 3867 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3868 }; 3869 3870 /** 3871 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3872 */ 3873 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3874 /** 3875 * Command header. 3876 */ 3877 struct dmub_cmd_header header; 3878 /** 3879 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3880 */ 3881 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3882 /** 3883 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3884 */ 3885 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3886 }; 3887 3888 /** 3889 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3890 */ 3891 struct dmub_rb_cmd_replay_set_timing_sync { 3892 /** 3893 * Command header. 3894 */ 3895 struct dmub_cmd_header header; 3896 /** 3897 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3898 */ 3899 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3900 }; 3901 3902 /** 3903 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3904 */ 3905 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3906 /** 3907 * Command header. 3908 */ 3909 struct dmub_cmd_header header; 3910 /** 3911 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3912 */ 3913 struct dmub_cmd_replay_set_pseudo_vtotal data; 3914 }; 3915 3916 /** 3917 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3918 */ 3919 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3920 /** 3921 * Command header. 3922 */ 3923 struct dmub_cmd_header header; 3924 /** 3925 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3926 */ 3927 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3928 }; 3929 3930 /** 3931 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3932 */ 3933 struct dmub_rb_cmd_replay_set_general_cmd { 3934 /** 3935 * Command header. 3936 */ 3937 struct dmub_cmd_header header; 3938 /** 3939 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3940 */ 3941 struct dmub_cmd_replay_set_general_cmd_data data; 3942 }; 3943 3944 /** 3945 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3946 */ 3947 struct dmub_cmd_replay_frameupdate_timer_data { 3948 /** 3949 * Panel Instance. 3950 * Panel isntance to identify which replay_state to use 3951 * Currently the support is only for 0 or 1 3952 */ 3953 uint8_t panel_inst; 3954 /** 3955 * Replay Frameupdate Timer Enable or not 3956 */ 3957 uint8_t enable; 3958 /** 3959 * REPLAY force reflash frame update number 3960 */ 3961 uint16_t frameupdate_count; 3962 }; 3963 /** 3964 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3965 */ 3966 struct dmub_rb_cmd_replay_set_frameupdate_timer { 3967 /** 3968 * Command header. 3969 */ 3970 struct dmub_cmd_header header; 3971 /** 3972 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3973 */ 3974 struct dmub_cmd_replay_frameupdate_timer_data data; 3975 }; 3976 3977 /** 3978 * Definition union of replay command set 3979 */ 3980 union dmub_replay_cmd_set { 3981 /** 3982 * Panel Instance. 3983 * Panel isntance to identify which replay_state to use 3984 * Currently the support is only for 0 or 1 3985 */ 3986 uint8_t panel_inst; 3987 /** 3988 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 3989 */ 3990 struct dmub_cmd_replay_set_timing_sync_data sync_data; 3991 /** 3992 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 3993 */ 3994 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 3995 /** 3996 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 3997 */ 3998 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 3999 /** 4000 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4001 */ 4002 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4003 /** 4004 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4005 */ 4006 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4007 }; 4008 4009 /** 4010 * Set of HW components that can be locked. 4011 * 4012 * Note: If updating with more HW components, fields 4013 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4014 */ 4015 union dmub_hw_lock_flags { 4016 /** 4017 * Set of HW components that can be locked. 4018 */ 4019 struct { 4020 /** 4021 * Lock/unlock OTG master update lock. 4022 */ 4023 uint8_t lock_pipe : 1; 4024 /** 4025 * Lock/unlock cursor. 4026 */ 4027 uint8_t lock_cursor : 1; 4028 /** 4029 * Lock/unlock global update lock. 4030 */ 4031 uint8_t lock_dig : 1; 4032 /** 4033 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4034 */ 4035 uint8_t triple_buffer_lock : 1; 4036 } bits; 4037 4038 /** 4039 * Union for HW Lock flags. 4040 */ 4041 uint8_t u8All; 4042 }; 4043 4044 /** 4045 * Instances of HW to be locked. 4046 * 4047 * Note: If updating with more HW components, fields 4048 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4049 */ 4050 struct dmub_hw_lock_inst_flags { 4051 /** 4052 * OTG HW instance for OTG master update lock. 4053 */ 4054 uint8_t otg_inst; 4055 /** 4056 * OPP instance for cursor lock. 4057 */ 4058 uint8_t opp_inst; 4059 /** 4060 * OTG HW instance for global update lock. 4061 * TODO: Remove, and re-use otg_inst. 4062 */ 4063 uint8_t dig_inst; 4064 /** 4065 * Explicit pad to 4 byte boundary. 4066 */ 4067 uint8_t pad; 4068 }; 4069 4070 /** 4071 * Clients that can acquire the HW Lock Manager. 4072 * 4073 * Note: If updating with more clients, fields in 4074 * dmub_inbox0_cmd_lock_hw must be updated to match. 4075 */ 4076 enum hw_lock_client { 4077 /** 4078 * Driver is the client of HW Lock Manager. 4079 */ 4080 HW_LOCK_CLIENT_DRIVER = 0, 4081 /** 4082 * PSR SU is the client of HW Lock Manager. 4083 */ 4084 HW_LOCK_CLIENT_PSR_SU = 1, 4085 HW_LOCK_CLIENT_SUBVP = 3, 4086 /** 4087 * Replay is the client of HW Lock Manager. 4088 */ 4089 HW_LOCK_CLIENT_REPLAY = 4, 4090 HW_LOCK_CLIENT_FAMS2 = 5, 4091 /** 4092 * Invalid client. 4093 */ 4094 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4095 }; 4096 4097 /** 4098 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4099 */ 4100 struct dmub_cmd_lock_hw_data { 4101 /** 4102 * Specifies the client accessing HW Lock Manager. 4103 */ 4104 enum hw_lock_client client; 4105 /** 4106 * HW instances to be locked. 4107 */ 4108 struct dmub_hw_lock_inst_flags inst_flags; 4109 /** 4110 * Which components to be locked. 4111 */ 4112 union dmub_hw_lock_flags hw_locks; 4113 /** 4114 * Specifies lock/unlock. 4115 */ 4116 uint8_t lock; 4117 /** 4118 * HW can be unlocked separately from releasing the HW Lock Mgr. 4119 * This flag is set if the client wishes to release the object. 4120 */ 4121 uint8_t should_release; 4122 /** 4123 * Explicit padding to 4 byte boundary. 4124 */ 4125 uint8_t pad; 4126 }; 4127 4128 /** 4129 * Definition of a DMUB_CMD__HW_LOCK command. 4130 * Command is used by driver and FW. 4131 */ 4132 struct dmub_rb_cmd_lock_hw { 4133 /** 4134 * Command header. 4135 */ 4136 struct dmub_cmd_header header; 4137 /** 4138 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4139 */ 4140 struct dmub_cmd_lock_hw_data lock_hw_data; 4141 }; 4142 4143 /** 4144 * ABM command sub-types. 4145 */ 4146 enum dmub_cmd_abm_type { 4147 /** 4148 * Initialize parameters for ABM algorithm. 4149 * Data is passed through an indirect buffer. 4150 */ 4151 DMUB_CMD__ABM_INIT_CONFIG = 0, 4152 /** 4153 * Set OTG and panel HW instance. 4154 */ 4155 DMUB_CMD__ABM_SET_PIPE = 1, 4156 /** 4157 * Set user requested backklight level. 4158 */ 4159 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4160 /** 4161 * Set ABM operating/aggression level. 4162 */ 4163 DMUB_CMD__ABM_SET_LEVEL = 3, 4164 /** 4165 * Set ambient light level. 4166 */ 4167 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4168 /** 4169 * Enable/disable fractional duty cycle for backlight PWM. 4170 */ 4171 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4172 4173 /** 4174 * unregister vertical interrupt after steady state is reached 4175 */ 4176 DMUB_CMD__ABM_PAUSE = 6, 4177 4178 /** 4179 * Save and Restore ABM state. On save we save parameters, and 4180 * on restore we update state with passed in data. 4181 */ 4182 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4183 4184 /** 4185 * Query ABM caps. 4186 */ 4187 DMUB_CMD__ABM_QUERY_CAPS = 8, 4188 4189 /** 4190 * Set ABM Events 4191 */ 4192 DMUB_CMD__ABM_SET_EVENT = 9, 4193 4194 /** 4195 * Get the current ACE curve. 4196 */ 4197 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4198 }; 4199 4200 struct abm_ace_curve { 4201 /** 4202 * @offsets: ACE curve offsets. 4203 */ 4204 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4205 4206 /** 4207 * @thresholds: ACE curve thresholds. 4208 */ 4209 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4210 4211 /** 4212 * @slopes: ACE curve slopes. 4213 */ 4214 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4215 }; 4216 4217 struct fixed_pt_format { 4218 /** 4219 * @sign_bit: Indicates whether one bit is reserved for the sign. 4220 */ 4221 bool sign_bit; 4222 4223 /** 4224 * @num_int_bits: Number of bits used for integer part. 4225 */ 4226 uint8_t num_int_bits; 4227 4228 /** 4229 * @num_frac_bits: Number of bits used for fractional part. 4230 */ 4231 uint8_t num_frac_bits; 4232 4233 /** 4234 * @pad: Explicit padding to 4 byte boundary. 4235 */ 4236 uint8_t pad; 4237 }; 4238 4239 struct abm_caps { 4240 /** 4241 * @num_hg_bins: Number of histogram bins. 4242 */ 4243 uint8_t num_hg_bins; 4244 4245 /** 4246 * @num_ace_segments: Number of ACE curve segments. 4247 */ 4248 uint8_t num_ace_segments; 4249 4250 /** 4251 * @pad: Explicit padding to 4 byte boundary. 4252 */ 4253 uint8_t pad[2]; 4254 4255 /** 4256 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4257 */ 4258 struct fixed_pt_format ace_thresholds_format; 4259 4260 /** 4261 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4262 */ 4263 struct fixed_pt_format ace_offsets_format; 4264 4265 /** 4266 * @ace_slopes_format: Format of the ACE slopes. 4267 */ 4268 struct fixed_pt_format ace_slopes_format; 4269 }; 4270 4271 /** 4272 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4273 * Requirements: 4274 * - Padded explicitly to 32-bit boundary. 4275 * - Must ensure this structure matches the one on driver-side, 4276 * otherwise it won't be aligned. 4277 */ 4278 struct abm_config_table { 4279 /** 4280 * Gamma curve thresholds, used for crgb conversion. 4281 */ 4282 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4283 /** 4284 * Gamma curve offsets, used for crgb conversion. 4285 */ 4286 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4287 /** 4288 * Gamma curve slopes, used for crgb conversion. 4289 */ 4290 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4291 /** 4292 * Custom backlight curve thresholds. 4293 */ 4294 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4295 /** 4296 * Custom backlight curve offsets. 4297 */ 4298 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4299 /** 4300 * Ambient light thresholds. 4301 */ 4302 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4303 /** 4304 * Minimum programmable backlight. 4305 */ 4306 uint16_t min_abm_backlight; // 122B 4307 /** 4308 * Minimum reduction values. 4309 */ 4310 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4311 /** 4312 * Maximum reduction values. 4313 */ 4314 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4315 /** 4316 * Bright positive gain. 4317 */ 4318 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4319 /** 4320 * Dark negative gain. 4321 */ 4322 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4323 /** 4324 * Hybrid factor. 4325 */ 4326 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4327 /** 4328 * Contrast factor. 4329 */ 4330 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4331 /** 4332 * Deviation gain. 4333 */ 4334 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4335 /** 4336 * Minimum knee. 4337 */ 4338 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4339 /** 4340 * Maximum knee. 4341 */ 4342 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4343 /** 4344 * Unused. 4345 */ 4346 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4347 /** 4348 * Explicit padding to 4 byte boundary. 4349 */ 4350 uint8_t pad3[3]; // 229B 4351 /** 4352 * Backlight ramp reduction. 4353 */ 4354 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4355 /** 4356 * Backlight ramp start. 4357 */ 4358 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4359 }; 4360 4361 /** 4362 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4363 */ 4364 struct dmub_cmd_abm_set_pipe_data { 4365 /** 4366 * OTG HW instance. 4367 */ 4368 uint8_t otg_inst; 4369 4370 /** 4371 * Panel Control HW instance. 4372 */ 4373 uint8_t panel_inst; 4374 4375 /** 4376 * Controls how ABM will interpret a set pipe or set level command. 4377 */ 4378 uint8_t set_pipe_option; 4379 4380 /** 4381 * Unused. 4382 * TODO: Remove. 4383 */ 4384 uint8_t ramping_boundary; 4385 4386 /** 4387 * PwrSeq HW Instance. 4388 */ 4389 uint8_t pwrseq_inst; 4390 4391 /** 4392 * Explicit padding to 4 byte boundary. 4393 */ 4394 uint8_t pad[3]; 4395 }; 4396 4397 /** 4398 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4399 */ 4400 struct dmub_rb_cmd_abm_set_pipe { 4401 /** 4402 * Command header. 4403 */ 4404 struct dmub_cmd_header header; 4405 4406 /** 4407 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4408 */ 4409 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4410 }; 4411 4412 /** 4413 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4414 */ 4415 struct dmub_cmd_abm_set_backlight_data { 4416 /** 4417 * Number of frames to ramp to backlight user level. 4418 */ 4419 uint32_t frame_ramp; 4420 4421 /** 4422 * Requested backlight level from user. 4423 */ 4424 uint32_t backlight_user_level; 4425 4426 /** 4427 * ABM control version. 4428 */ 4429 uint8_t version; 4430 4431 /** 4432 * Panel Control HW instance mask. 4433 * Bit 0 is Panel Control HW instance 0. 4434 * Bit 1 is Panel Control HW instance 1. 4435 */ 4436 uint8_t panel_mask; 4437 4438 /** 4439 * Backlight control type. 4440 * Value 0 is PWM backlight control. 4441 * Value 1 is VAUX backlight control. 4442 * Value 2 is AMD DPCD AUX backlight control. 4443 */ 4444 uint8_t backlight_control_type; 4445 4446 /** 4447 * Explicit padding to 4 byte boundary. 4448 */ 4449 uint8_t pad[1]; 4450 4451 /** 4452 * Minimum luminance in nits. 4453 */ 4454 uint32_t min_luminance; 4455 4456 /** 4457 * Maximum luminance in nits. 4458 */ 4459 uint32_t max_luminance; 4460 4461 /** 4462 * Minimum backlight in pwm. 4463 */ 4464 uint32_t min_backlight_pwm; 4465 4466 /** 4467 * Maximum backlight in pwm. 4468 */ 4469 uint32_t max_backlight_pwm; 4470 }; 4471 4472 /** 4473 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4474 */ 4475 struct dmub_rb_cmd_abm_set_backlight { 4476 /** 4477 * Command header. 4478 */ 4479 struct dmub_cmd_header header; 4480 4481 /** 4482 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4483 */ 4484 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4485 }; 4486 4487 /** 4488 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4489 */ 4490 struct dmub_cmd_abm_set_level_data { 4491 /** 4492 * Set current ABM operating/aggression level. 4493 */ 4494 uint32_t level; 4495 4496 /** 4497 * ABM control version. 4498 */ 4499 uint8_t version; 4500 4501 /** 4502 * Panel Control HW instance mask. 4503 * Bit 0 is Panel Control HW instance 0. 4504 * Bit 1 is Panel Control HW instance 1. 4505 */ 4506 uint8_t panel_mask; 4507 4508 /** 4509 * Explicit padding to 4 byte boundary. 4510 */ 4511 uint8_t pad[2]; 4512 }; 4513 4514 /** 4515 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4516 */ 4517 struct dmub_rb_cmd_abm_set_level { 4518 /** 4519 * Command header. 4520 */ 4521 struct dmub_cmd_header header; 4522 4523 /** 4524 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4525 */ 4526 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4527 }; 4528 4529 /** 4530 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4531 */ 4532 struct dmub_cmd_abm_set_ambient_level_data { 4533 /** 4534 * Ambient light sensor reading from OS. 4535 */ 4536 uint32_t ambient_lux; 4537 4538 /** 4539 * ABM control version. 4540 */ 4541 uint8_t version; 4542 4543 /** 4544 * Panel Control HW instance mask. 4545 * Bit 0 is Panel Control HW instance 0. 4546 * Bit 1 is Panel Control HW instance 1. 4547 */ 4548 uint8_t panel_mask; 4549 4550 /** 4551 * Explicit padding to 4 byte boundary. 4552 */ 4553 uint8_t pad[2]; 4554 }; 4555 4556 /** 4557 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4558 */ 4559 struct dmub_rb_cmd_abm_set_ambient_level { 4560 /** 4561 * Command header. 4562 */ 4563 struct dmub_cmd_header header; 4564 4565 /** 4566 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4567 */ 4568 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4569 }; 4570 4571 /** 4572 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4573 */ 4574 struct dmub_cmd_abm_set_pwm_frac_data { 4575 /** 4576 * Enable/disable fractional duty cycle for backlight PWM. 4577 * TODO: Convert to uint8_t. 4578 */ 4579 uint32_t fractional_pwm; 4580 4581 /** 4582 * ABM control version. 4583 */ 4584 uint8_t version; 4585 4586 /** 4587 * Panel Control HW instance mask. 4588 * Bit 0 is Panel Control HW instance 0. 4589 * Bit 1 is Panel Control HW instance 1. 4590 */ 4591 uint8_t panel_mask; 4592 4593 /** 4594 * Explicit padding to 4 byte boundary. 4595 */ 4596 uint8_t pad[2]; 4597 }; 4598 4599 /** 4600 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4601 */ 4602 struct dmub_rb_cmd_abm_set_pwm_frac { 4603 /** 4604 * Command header. 4605 */ 4606 struct dmub_cmd_header header; 4607 4608 /** 4609 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4610 */ 4611 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4612 }; 4613 4614 /** 4615 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4616 */ 4617 struct dmub_cmd_abm_init_config_data { 4618 /** 4619 * Location of indirect buffer used to pass init data to ABM. 4620 */ 4621 union dmub_addr src; 4622 4623 /** 4624 * Indirect buffer length. 4625 */ 4626 uint16_t bytes; 4627 4628 4629 /** 4630 * ABM control version. 4631 */ 4632 uint8_t version; 4633 4634 /** 4635 * Panel Control HW instance mask. 4636 * Bit 0 is Panel Control HW instance 0. 4637 * Bit 1 is Panel Control HW instance 1. 4638 */ 4639 uint8_t panel_mask; 4640 4641 /** 4642 * Explicit padding to 4 byte boundary. 4643 */ 4644 uint8_t pad[2]; 4645 }; 4646 4647 /** 4648 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4649 */ 4650 struct dmub_rb_cmd_abm_init_config { 4651 /** 4652 * Command header. 4653 */ 4654 struct dmub_cmd_header header; 4655 4656 /** 4657 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4658 */ 4659 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4660 }; 4661 4662 /** 4663 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4664 */ 4665 4666 struct dmub_cmd_abm_pause_data { 4667 4668 /** 4669 * Panel Control HW instance mask. 4670 * Bit 0 is Panel Control HW instance 0. 4671 * Bit 1 is Panel Control HW instance 1. 4672 */ 4673 uint8_t panel_mask; 4674 4675 /** 4676 * OTG hw instance 4677 */ 4678 uint8_t otg_inst; 4679 4680 /** 4681 * Enable or disable ABM pause 4682 */ 4683 uint8_t enable; 4684 4685 /** 4686 * Explicit padding to 4 byte boundary. 4687 */ 4688 uint8_t pad[1]; 4689 }; 4690 4691 /** 4692 * Definition of a DMUB_CMD__ABM_PAUSE command. 4693 */ 4694 struct dmub_rb_cmd_abm_pause { 4695 /** 4696 * Command header. 4697 */ 4698 struct dmub_cmd_header header; 4699 4700 /** 4701 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4702 */ 4703 struct dmub_cmd_abm_pause_data abm_pause_data; 4704 }; 4705 4706 /** 4707 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4708 */ 4709 struct dmub_cmd_abm_query_caps_in { 4710 /** 4711 * Panel instance. 4712 */ 4713 uint8_t panel_inst; 4714 4715 /** 4716 * Explicit padding to 4 byte boundary. 4717 */ 4718 uint8_t pad[3]; 4719 }; 4720 4721 /** 4722 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4723 */ 4724 struct dmub_cmd_abm_query_caps_out { 4725 /** 4726 * SW Algorithm caps. 4727 */ 4728 struct abm_caps sw_caps; 4729 4730 /** 4731 * ABM HW caps. 4732 */ 4733 struct abm_caps hw_caps; 4734 }; 4735 4736 /** 4737 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4738 */ 4739 struct dmub_rb_cmd_abm_query_caps { 4740 /** 4741 * Command header. 4742 */ 4743 struct dmub_cmd_header header; 4744 4745 /** 4746 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4747 */ 4748 union { 4749 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4750 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4751 } data; 4752 }; 4753 4754 /** 4755 * enum dmub_abm_ace_curve_type - ACE curve type. 4756 */ 4757 enum dmub_abm_ace_curve_type { 4758 /** 4759 * ACE curve as defined by the SW layer. 4760 */ 4761 ABM_ACE_CURVE_TYPE__SW = 0, 4762 /** 4763 * ACE curve as defined by the SW to HW translation interface layer. 4764 */ 4765 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4766 }; 4767 4768 /** 4769 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4770 */ 4771 struct dmub_rb_cmd_abm_get_ace_curve { 4772 /** 4773 * Command header. 4774 */ 4775 struct dmub_cmd_header header; 4776 4777 /** 4778 * Address where ACE curve should be copied. 4779 */ 4780 union dmub_addr dest; 4781 4782 /** 4783 * Type of ACE curve being queried. 4784 */ 4785 enum dmub_abm_ace_curve_type ace_type; 4786 4787 /** 4788 * Indirect buffer length. 4789 */ 4790 uint16_t bytes; 4791 4792 /** 4793 * eDP panel instance. 4794 */ 4795 uint8_t panel_inst; 4796 4797 /** 4798 * Explicit padding to 4 byte boundary. 4799 */ 4800 uint8_t pad; 4801 }; 4802 4803 /** 4804 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4805 */ 4806 struct dmub_rb_cmd_abm_save_restore { 4807 /** 4808 * Command header. 4809 */ 4810 struct dmub_cmd_header header; 4811 4812 /** 4813 * OTG hw instance 4814 */ 4815 uint8_t otg_inst; 4816 4817 /** 4818 * Enable or disable ABM pause 4819 */ 4820 uint8_t freeze; 4821 4822 /** 4823 * Explicit padding to 4 byte boundary. 4824 */ 4825 uint8_t debug; 4826 4827 /** 4828 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4829 */ 4830 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4831 }; 4832 4833 /** 4834 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4835 */ 4836 4837 struct dmub_cmd_abm_set_event_data { 4838 4839 /** 4840 * VB Scaling Init. Strength Mapping 4841 * Byte 0: 0~255 for VB level 0 4842 * Byte 1: 0~255 for VB level 1 4843 * Byte 2: 0~255 for VB level 2 4844 * Byte 3: 0~255 for VB level 3 4845 */ 4846 uint32_t vb_scaling_strength_mapping; 4847 /** 4848 * VariBright Scaling Enable 4849 */ 4850 uint8_t vb_scaling_enable; 4851 /** 4852 * Panel Control HW instance mask. 4853 * Bit 0 is Panel Control HW instance 0. 4854 * Bit 1 is Panel Control HW instance 1. 4855 */ 4856 uint8_t panel_mask; 4857 4858 /** 4859 * Explicit padding to 4 byte boundary. 4860 */ 4861 uint8_t pad[2]; 4862 }; 4863 4864 /** 4865 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 4866 */ 4867 struct dmub_rb_cmd_abm_set_event { 4868 /** 4869 * Command header. 4870 */ 4871 struct dmub_cmd_header header; 4872 4873 /** 4874 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4875 */ 4876 struct dmub_cmd_abm_set_event_data abm_set_event_data; 4877 }; 4878 4879 /** 4880 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4881 */ 4882 struct dmub_cmd_query_feature_caps_data { 4883 /** 4884 * DMUB feature capabilities. 4885 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4886 */ 4887 struct dmub_feature_caps feature_caps; 4888 }; 4889 4890 /** 4891 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4892 */ 4893 struct dmub_rb_cmd_query_feature_caps { 4894 /** 4895 * Command header. 4896 */ 4897 struct dmub_cmd_header header; 4898 /** 4899 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4900 */ 4901 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4902 }; 4903 4904 /** 4905 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4906 */ 4907 struct dmub_cmd_visual_confirm_color_data { 4908 /** 4909 * DMUB visual confirm color 4910 */ 4911 struct dmub_visual_confirm_color visual_confirm_color; 4912 }; 4913 4914 /** 4915 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4916 */ 4917 struct dmub_rb_cmd_get_visual_confirm_color { 4918 /** 4919 * Command header. 4920 */ 4921 struct dmub_cmd_header header; 4922 /** 4923 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4924 */ 4925 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4926 }; 4927 4928 /** 4929 * enum dmub_cmd_panel_cntl_type - Panel control command. 4930 */ 4931 enum dmub_cmd_panel_cntl_type { 4932 /** 4933 * Initializes embedded panel hardware blocks. 4934 */ 4935 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4936 /** 4937 * Queries backlight info for the embedded panel. 4938 */ 4939 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4940 /** 4941 * Sets the PWM Freq as per user's requirement. 4942 */ 4943 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 4944 }; 4945 4946 /** 4947 * struct dmub_cmd_panel_cntl_data - Panel control data. 4948 */ 4949 struct dmub_cmd_panel_cntl_data { 4950 uint32_t pwrseq_inst; /**< pwrseq instance */ 4951 uint32_t current_backlight; /* in/out */ 4952 uint32_t bl_pwm_cntl; /* in/out */ 4953 uint32_t bl_pwm_period_cntl; /* in/out */ 4954 uint32_t bl_pwm_ref_div1; /* in/out */ 4955 uint8_t is_backlight_on : 1; /* in/out */ 4956 uint8_t is_powered_on : 1; /* in/out */ 4957 uint8_t padding[3]; 4958 uint32_t bl_pwm_ref_div2; /* in/out */ 4959 uint8_t reserved[4]; 4960 }; 4961 4962 /** 4963 * struct dmub_rb_cmd_panel_cntl - Panel control command. 4964 */ 4965 struct dmub_rb_cmd_panel_cntl { 4966 struct dmub_cmd_header header; /**< header */ 4967 struct dmub_cmd_panel_cntl_data data; /**< payload */ 4968 }; 4969 4970 struct dmub_optc_state { 4971 uint32_t v_total_max; 4972 uint32_t v_total_min; 4973 uint32_t tg_inst; 4974 }; 4975 4976 struct dmub_rb_cmd_drr_update { 4977 struct dmub_cmd_header header; 4978 struct dmub_optc_state dmub_optc_state_req; 4979 }; 4980 4981 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 4982 uint32_t pix_clk_100hz; 4983 uint8_t max_ramp_step; 4984 uint8_t pipes; 4985 uint8_t min_refresh_in_hz; 4986 uint8_t pipe_count; 4987 uint8_t pipe_index[4]; 4988 }; 4989 4990 struct dmub_cmd_fw_assisted_mclk_switch_config { 4991 uint8_t fams_enabled; 4992 uint8_t visual_confirm_enabled; 4993 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 4994 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 4995 }; 4996 4997 struct dmub_rb_cmd_fw_assisted_mclk_switch { 4998 struct dmub_cmd_header header; 4999 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5000 }; 5001 5002 /** 5003 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5004 */ 5005 struct dmub_cmd_lvtma_control_data { 5006 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5007 uint8_t bypass_panel_control_wait; 5008 uint8_t reserved_0[2]; /**< For future use */ 5009 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5010 uint8_t reserved_1[3]; /**< For future use */ 5011 }; 5012 5013 /** 5014 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5015 */ 5016 struct dmub_rb_cmd_lvtma_control { 5017 /** 5018 * Command header. 5019 */ 5020 struct dmub_cmd_header header; 5021 /** 5022 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5023 */ 5024 struct dmub_cmd_lvtma_control_data data; 5025 }; 5026 5027 /** 5028 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5029 */ 5030 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5031 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5032 uint8_t is_usb; /**< is phy is usb */ 5033 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5034 uint8_t is_dp4; /**< is dp in 4 lane */ 5035 }; 5036 5037 /** 5038 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5039 */ 5040 struct dmub_rb_cmd_transmitter_query_dp_alt { 5041 struct dmub_cmd_header header; /**< header */ 5042 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5043 }; 5044 5045 struct phy_test_mode { 5046 uint8_t mode; 5047 uint8_t pat0; 5048 uint8_t pad[2]; 5049 }; 5050 5051 /** 5052 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5053 */ 5054 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5055 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5056 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5057 uint8_t lane_num; /**< Number of lanes */ 5058 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5059 struct phy_test_mode test_mode; 5060 enum dmub_phy_fsm_state state; 5061 uint32_t status; 5062 uint8_t pad; 5063 }; 5064 5065 /** 5066 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5067 */ 5068 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5069 struct dmub_cmd_header header; /**< header */ 5070 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5071 }; 5072 5073 /** 5074 * Maximum number of bytes a chunk sent to DMUB for parsing 5075 */ 5076 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5077 5078 /** 5079 * Represent a chunk of CEA blocks sent to DMUB for parsing 5080 */ 5081 struct dmub_cmd_send_edid_cea { 5082 uint16_t offset; /**< offset into the CEA block */ 5083 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5084 uint16_t cea_total_length; /**< total length of the CEA block */ 5085 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5086 uint8_t pad[3]; /**< padding and for future expansion */ 5087 }; 5088 5089 /** 5090 * Result of VSDB parsing from CEA block 5091 */ 5092 struct dmub_cmd_edid_cea_amd_vsdb { 5093 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5094 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5095 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5096 uint16_t min_frame_rate; /**< Maximum frame rate */ 5097 uint16_t max_frame_rate; /**< Minimum frame rate */ 5098 }; 5099 5100 /** 5101 * Result of sending a CEA chunk 5102 */ 5103 struct dmub_cmd_edid_cea_ack { 5104 uint16_t offset; /**< offset of the chunk into the CEA block */ 5105 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5106 uint8_t pad; /**< padding and for future expansion */ 5107 }; 5108 5109 /** 5110 * Specify whether the result is an ACK/NACK or the parsing has finished 5111 */ 5112 enum dmub_cmd_edid_cea_reply_type { 5113 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5114 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5115 }; 5116 5117 /** 5118 * Definition of a DMUB_CMD__EDID_CEA command. 5119 */ 5120 struct dmub_rb_cmd_edid_cea { 5121 struct dmub_cmd_header header; /**< Command header */ 5122 union dmub_cmd_edid_cea_data { 5123 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5124 struct dmub_cmd_edid_cea_output { /**< output with results */ 5125 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5126 union { 5127 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5128 struct dmub_cmd_edid_cea_ack ack; 5129 }; 5130 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5131 } data; /**< Command data */ 5132 5133 }; 5134 5135 /** 5136 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5137 */ 5138 struct dmub_cmd_cable_id_input { 5139 uint8_t phy_inst; /**< phy inst for cable id data */ 5140 }; 5141 5142 /** 5143 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5144 */ 5145 struct dmub_cmd_cable_id_output { 5146 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5147 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5148 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5149 uint8_t RESERVED :2; /**< reserved means not defined */ 5150 }; 5151 5152 /** 5153 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5154 */ 5155 struct dmub_rb_cmd_get_usbc_cable_id { 5156 struct dmub_cmd_header header; /**< Command header */ 5157 /** 5158 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5159 */ 5160 union dmub_cmd_cable_id_data { 5161 struct dmub_cmd_cable_id_input input; /**< Input */ 5162 struct dmub_cmd_cable_id_output output; /**< Output */ 5163 uint8_t output_raw; /**< Raw data output */ 5164 } data; 5165 }; 5166 5167 /** 5168 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5169 */ 5170 enum dmub_cmd_secure_display_type { 5171 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5172 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5173 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 5174 }; 5175 5176 /** 5177 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5178 */ 5179 struct dmub_rb_cmd_secure_display { 5180 struct dmub_cmd_header header; 5181 /** 5182 * Data passed from driver to dmub firmware. 5183 */ 5184 struct dmub_cmd_roi_info { 5185 uint16_t x_start; 5186 uint16_t x_end; 5187 uint16_t y_start; 5188 uint16_t y_end; 5189 uint8_t otg_id; 5190 uint8_t phy_id; 5191 } roi_info; 5192 }; 5193 5194 /** 5195 * Command type of a DMUB_CMD__PSP command 5196 */ 5197 enum dmub_cmd_psp_type { 5198 DMUB_CMD__PSP_ASSR_ENABLE = 0 5199 }; 5200 5201 /** 5202 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5203 */ 5204 struct dmub_cmd_assr_enable_data { 5205 /** 5206 * ASSR enable or disable. 5207 */ 5208 uint8_t enable; 5209 /** 5210 * PHY port type. 5211 * Indicates eDP / non-eDP port type 5212 */ 5213 uint8_t phy_port_type; 5214 /** 5215 * PHY port ID. 5216 */ 5217 uint8_t phy_port_id; 5218 /** 5219 * Link encoder index. 5220 */ 5221 uint8_t link_enc_index; 5222 /** 5223 * HPO mode. 5224 */ 5225 uint8_t hpo_mode; 5226 5227 /** 5228 * Reserved field. 5229 */ 5230 uint8_t reserved[7]; 5231 }; 5232 5233 /** 5234 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5235 */ 5236 struct dmub_rb_cmd_assr_enable { 5237 /** 5238 * Command header. 5239 */ 5240 struct dmub_cmd_header header; 5241 5242 /** 5243 * Assr data. 5244 */ 5245 struct dmub_cmd_assr_enable_data assr_data; 5246 5247 /** 5248 * Reserved field. 5249 */ 5250 uint32_t reserved[3]; 5251 }; 5252 5253 /** 5254 * union dmub_rb_cmd - DMUB inbox command. 5255 */ 5256 union dmub_rb_cmd { 5257 /** 5258 * Elements shared with all commands. 5259 */ 5260 struct dmub_rb_cmd_common cmd_common; 5261 /** 5262 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5263 */ 5264 struct dmub_rb_cmd_read_modify_write read_modify_write; 5265 /** 5266 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5267 */ 5268 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5269 /** 5270 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5271 */ 5272 struct dmub_rb_cmd_burst_write burst_write; 5273 /** 5274 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5275 */ 5276 struct dmub_rb_cmd_reg_wait reg_wait; 5277 /** 5278 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5279 */ 5280 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5281 /** 5282 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5283 */ 5284 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5285 /** 5286 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5287 */ 5288 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5289 /** 5290 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5291 */ 5292 struct dmub_rb_cmd_dpphy_init dpphy_init; 5293 /** 5294 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5295 */ 5296 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5297 /** 5298 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5299 */ 5300 struct dmub_rb_cmd_domain_control domain_control; 5301 /** 5302 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5303 */ 5304 struct dmub_rb_cmd_psr_set_version psr_set_version; 5305 /** 5306 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5307 */ 5308 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5309 /** 5310 * Definition of a DMUB_CMD__PSR_ENABLE command. 5311 */ 5312 struct dmub_rb_cmd_psr_enable psr_enable; 5313 /** 5314 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5315 */ 5316 struct dmub_rb_cmd_psr_set_level psr_set_level; 5317 /** 5318 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5319 */ 5320 struct dmub_rb_cmd_psr_force_static psr_force_static; 5321 /** 5322 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5323 */ 5324 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5325 /** 5326 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5327 */ 5328 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5329 /** 5330 * Definition of a DMUB_CMD__HW_LOCK command. 5331 * Command is used by driver and FW. 5332 */ 5333 struct dmub_rb_cmd_lock_hw lock_hw; 5334 /** 5335 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5336 */ 5337 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5338 /** 5339 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5340 */ 5341 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5342 /** 5343 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5344 */ 5345 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5346 /** 5347 * Definition of a DMUB_CMD__MALL command. 5348 */ 5349 struct dmub_rb_cmd_mall mall; 5350 5351 /** 5352 * Definition of a DMUB_CMD__CAB command. 5353 */ 5354 struct dmub_rb_cmd_cab_for_ss cab; 5355 5356 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5357 5358 /** 5359 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5360 */ 5361 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5362 5363 /** 5364 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5365 */ 5366 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5367 5368 /** 5369 * Definition of DMUB_CMD__PANEL_CNTL commands. 5370 */ 5371 struct dmub_rb_cmd_panel_cntl panel_cntl; 5372 5373 /** 5374 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5375 */ 5376 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5377 5378 /** 5379 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5380 */ 5381 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5382 5383 /** 5384 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5385 */ 5386 struct dmub_rb_cmd_abm_set_level abm_set_level; 5387 5388 /** 5389 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5390 */ 5391 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5392 5393 /** 5394 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5395 */ 5396 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5397 5398 /** 5399 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5400 */ 5401 struct dmub_rb_cmd_abm_init_config abm_init_config; 5402 5403 /** 5404 * Definition of a DMUB_CMD__ABM_PAUSE command. 5405 */ 5406 struct dmub_rb_cmd_abm_pause abm_pause; 5407 5408 /** 5409 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5410 */ 5411 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5412 5413 /** 5414 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5415 */ 5416 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5417 5418 /** 5419 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5420 */ 5421 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5422 5423 /** 5424 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5425 */ 5426 struct dmub_rb_cmd_abm_set_event abm_set_event; 5427 5428 /** 5429 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5430 */ 5431 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5432 5433 /** 5434 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5435 */ 5436 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5437 5438 /** 5439 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5440 */ 5441 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5442 5443 /** 5444 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5445 */ 5446 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5447 struct dmub_rb_cmd_drr_update drr_update; 5448 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5449 5450 /** 5451 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5452 */ 5453 struct dmub_rb_cmd_lvtma_control lvtma_control; 5454 /** 5455 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5456 */ 5457 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5458 /** 5459 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5460 */ 5461 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5462 /** 5463 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5464 */ 5465 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5466 /** 5467 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5468 */ 5469 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 5470 /** 5471 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5472 */ 5473 struct dmub_rb_cmd_set_config_request set_config_request; 5474 /** 5475 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5476 */ 5477 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5478 /** 5479 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 5480 */ 5481 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 5482 /** 5483 * Definition of a DMUB_CMD__EDID_CEA command. 5484 */ 5485 struct dmub_rb_cmd_edid_cea edid_cea; 5486 /** 5487 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5488 */ 5489 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5490 5491 /** 5492 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5493 */ 5494 struct dmub_rb_cmd_query_hpd_state query_hpd; 5495 /** 5496 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5497 */ 5498 struct dmub_rb_cmd_secure_display secure_display; 5499 5500 /** 5501 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5502 */ 5503 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5504 /** 5505 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5506 */ 5507 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5508 /** 5509 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 5510 */ 5511 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 5512 /* 5513 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5514 */ 5515 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5516 /** 5517 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5518 */ 5519 struct dmub_rb_cmd_replay_enable replay_enable; 5520 /** 5521 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5522 */ 5523 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5524 /** 5525 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5526 */ 5527 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5528 /** 5529 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5530 */ 5531 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5532 5533 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5534 /** 5535 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5536 */ 5537 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5538 /** 5539 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5540 */ 5541 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5542 /** 5543 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5544 */ 5545 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5546 /** 5547 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5548 */ 5549 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5550 /** 5551 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5552 */ 5553 struct dmub_rb_cmd_assr_enable assr_enable; 5554 struct dmub_rb_cmd_fams2 fams2_config; 5555 5556 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5557 5558 struct dmub_rb_cmd_fams2_flip fams2_flip; 5559 }; 5560 5561 /** 5562 * union dmub_rb_out_cmd - Outbox command 5563 */ 5564 union dmub_rb_out_cmd { 5565 /** 5566 * Parameters common to every command. 5567 */ 5568 struct dmub_rb_cmd_common cmd_common; 5569 /** 5570 * AUX reply command. 5571 */ 5572 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5573 /** 5574 * HPD notify command. 5575 */ 5576 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5577 /** 5578 * SET_CONFIG reply command. 5579 */ 5580 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5581 /** 5582 * DPIA notification command. 5583 */ 5584 struct dmub_rb_cmd_dpia_notification dpia_notification; 5585 /** 5586 * HPD sense notification command. 5587 */ 5588 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5589 }; 5590 #pragma pack(pop) 5591 5592 5593 //============================================================================== 5594 //</DMUB_CMD>=================================================================== 5595 //============================================================================== 5596 //< DMUB_RB>==================================================================== 5597 //============================================================================== 5598 5599 /** 5600 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5601 */ 5602 struct dmub_rb_init_params { 5603 void *ctx; /**< Caller provided context pointer */ 5604 void *base_address; /**< CPU base address for ring's data */ 5605 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5606 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5607 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5608 }; 5609 5610 /** 5611 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5612 */ 5613 struct dmub_rb { 5614 void *base_address; /**< CPU address for the ring's data */ 5615 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5616 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5617 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5618 5619 void *ctx; /**< Caller provided context pointer */ 5620 void *dmub; /**< Pointer to the DMUB interface */ 5621 }; 5622 5623 /** 5624 * @brief Checks if the ringbuffer is empty. 5625 * 5626 * @param rb DMUB Ringbuffer 5627 * @return true if empty 5628 * @return false otherwise 5629 */ 5630 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5631 { 5632 return (rb->wrpt == rb->rptr); 5633 } 5634 5635 /** 5636 * @brief Checks if the ringbuffer is full 5637 * 5638 * @param rb DMUB Ringbuffer 5639 * @return true if full 5640 * @return false otherwise 5641 */ 5642 static inline bool dmub_rb_full(struct dmub_rb *rb) 5643 { 5644 uint32_t data_count; 5645 5646 if (rb->wrpt >= rb->rptr) 5647 data_count = rb->wrpt - rb->rptr; 5648 else 5649 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5650 5651 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5652 } 5653 5654 /** 5655 * @brief Pushes a command into the ringbuffer 5656 * 5657 * @param rb DMUB ringbuffer 5658 * @param cmd The command to push 5659 * @return true if the ringbuffer was not full 5660 * @return false otherwise 5661 */ 5662 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5663 const union dmub_rb_cmd *cmd) 5664 { 5665 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5666 const uint64_t *src = (const uint64_t *)cmd; 5667 uint8_t i; 5668 5669 if (dmub_rb_full(rb)) 5670 return false; 5671 5672 // copying data 5673 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5674 *dst++ = *src++; 5675 5676 rb->wrpt += DMUB_RB_CMD_SIZE; 5677 5678 if (rb->wrpt >= rb->capacity) 5679 rb->wrpt %= rb->capacity; 5680 5681 return true; 5682 } 5683 5684 /** 5685 * @brief Pushes a command into the DMUB outbox ringbuffer 5686 * 5687 * @param rb DMUB outbox ringbuffer 5688 * @param cmd Outbox command 5689 * @return true if not full 5690 * @return false otherwise 5691 */ 5692 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5693 const union dmub_rb_out_cmd *cmd) 5694 { 5695 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 5696 const uint8_t *src = (const uint8_t *)cmd; 5697 5698 if (dmub_rb_full(rb)) 5699 return false; 5700 5701 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 5702 5703 rb->wrpt += DMUB_RB_CMD_SIZE; 5704 5705 if (rb->wrpt >= rb->capacity) 5706 rb->wrpt %= rb->capacity; 5707 5708 return true; 5709 } 5710 5711 /** 5712 * @brief Returns the next unprocessed command in the ringbuffer. 5713 * 5714 * @param rb DMUB ringbuffer 5715 * @param cmd The command to return 5716 * @return true if not empty 5717 * @return false otherwise 5718 */ 5719 static inline bool dmub_rb_front(struct dmub_rb *rb, 5720 union dmub_rb_cmd **cmd) 5721 { 5722 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 5723 5724 if (dmub_rb_empty(rb)) 5725 return false; 5726 5727 *cmd = (union dmub_rb_cmd *)rb_cmd; 5728 5729 return true; 5730 } 5731 5732 /** 5733 * @brief Determines the next ringbuffer offset. 5734 * 5735 * @param rb DMUB inbox ringbuffer 5736 * @param num_cmds Number of commands 5737 * @param next_rptr The next offset in the ringbuffer 5738 */ 5739 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 5740 uint32_t num_cmds, 5741 uint32_t *next_rptr) 5742 { 5743 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 5744 5745 if (*next_rptr >= rb->capacity) 5746 *next_rptr %= rb->capacity; 5747 } 5748 5749 /** 5750 * @brief Returns a pointer to a command in the inbox. 5751 * 5752 * @param rb DMUB inbox ringbuffer 5753 * @param cmd The inbox command to return 5754 * @param rptr The ringbuffer offset 5755 * @return true if not empty 5756 * @return false otherwise 5757 */ 5758 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 5759 union dmub_rb_cmd **cmd, 5760 uint32_t rptr) 5761 { 5762 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 5763 5764 if (dmub_rb_empty(rb)) 5765 return false; 5766 5767 *cmd = (union dmub_rb_cmd *)rb_cmd; 5768 5769 return true; 5770 } 5771 5772 /** 5773 * @brief Returns the next unprocessed command in the outbox. 5774 * 5775 * @param rb DMUB outbox ringbuffer 5776 * @param cmd The outbox command to return 5777 * @return true if not empty 5778 * @return false otherwise 5779 */ 5780 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 5781 union dmub_rb_out_cmd *cmd) 5782 { 5783 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 5784 uint64_t *dst = (uint64_t *)cmd; 5785 uint8_t i; 5786 5787 if (dmub_rb_empty(rb)) 5788 return false; 5789 5790 // copying data 5791 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5792 *dst++ = *src++; 5793 5794 return true; 5795 } 5796 5797 /** 5798 * @brief Removes the front entry in the ringbuffer. 5799 * 5800 * @param rb DMUB ringbuffer 5801 * @return true if the command was removed 5802 * @return false if there were no commands 5803 */ 5804 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 5805 { 5806 if (dmub_rb_empty(rb)) 5807 return false; 5808 5809 rb->rptr += DMUB_RB_CMD_SIZE; 5810 5811 if (rb->rptr >= rb->capacity) 5812 rb->rptr %= rb->capacity; 5813 5814 return true; 5815 } 5816 5817 /** 5818 * @brief Flushes commands in the ringbuffer to framebuffer memory. 5819 * 5820 * Avoids a race condition where DMCUB accesses memory while 5821 * there are still writes in flight to framebuffer. 5822 * 5823 * @param rb DMUB ringbuffer 5824 */ 5825 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 5826 { 5827 uint32_t rptr = rb->rptr; 5828 uint32_t wptr = rb->wrpt; 5829 5830 while (rptr != wptr) { 5831 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 5832 uint8_t i; 5833 5834 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5835 (void)READ_ONCE(*data++); 5836 5837 rptr += DMUB_RB_CMD_SIZE; 5838 if (rptr >= rb->capacity) 5839 rptr %= rb->capacity; 5840 } 5841 } 5842 5843 /** 5844 * @brief Initializes a DMCUB ringbuffer 5845 * 5846 * @param rb DMUB ringbuffer 5847 * @param init_params initial configuration for the ringbuffer 5848 */ 5849 static inline void dmub_rb_init(struct dmub_rb *rb, 5850 struct dmub_rb_init_params *init_params) 5851 { 5852 rb->base_address = init_params->base_address; 5853 rb->capacity = init_params->capacity; 5854 rb->rptr = init_params->read_ptr; 5855 rb->wrpt = init_params->write_ptr; 5856 } 5857 5858 /** 5859 * @brief Copies output data from in/out commands into the given command. 5860 * 5861 * @param rb DMUB ringbuffer 5862 * @param cmd Command to copy data into 5863 */ 5864 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5865 union dmub_rb_cmd *cmd) 5866 { 5867 // Copy rb entry back into command 5868 uint8_t *rd_ptr = (rb->rptr == 0) ? 5869 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5870 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5871 5872 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5873 } 5874 5875 //============================================================================== 5876 //</DMUB_RB>==================================================================== 5877 //============================================================================== 5878 #endif /* _DMUB_CMD_H_ */ 5879