1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310 struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326 }; 327 #pragma pack(pop) 328 329 /** 330 * Dirty rect definition. 331 */ 332 struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352 }; 353 354 /** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357 union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397 }; 398 399 /** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402 union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 uint32_t reserved : 18; 489 } bitfields; 490 491 uint32_t u32All; 492 }; 493 494 /** 495 * Flags record error state. 496 */ 497 union replay_visual_confirm_error_state_flags { 498 struct { 499 /** 500 * 0x1 (bit 0) - Desync Error flag. 501 */ 502 uint32_t desync_error : 1; 503 504 /** 505 * 0x2 (bit 1) - State Transition Error flag. 506 */ 507 uint32_t state_transition_error : 1; 508 509 /** 510 * 0x4 (bit 2) - Crc Error flag 511 */ 512 uint32_t crc_error : 1; 513 514 /** 515 * 0x8 (bit 3) - Reserved 516 */ 517 uint32_t reserved_3 : 1; 518 519 /** 520 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 521 * Added new debug flag to control DPCD. 522 */ 523 uint32_t incorrect_vtotal_in_static_screen : 1; 524 525 /** 526 * 0x20 (bit 5) - No doubled Refresh Rate. 527 */ 528 uint32_t no_double_rr : 1; 529 530 /** 531 * Reserved bit 6-7 532 */ 533 uint32_t reserved_6_7 : 2; 534 535 /** 536 * Reserved bit 9-31 537 */ 538 uint32_t reserved_9_31 : 24; 539 } bitfields; 540 541 uint32_t u32All; 542 }; 543 544 union replay_hw_flags { 545 struct { 546 /** 547 * @allow_alpm_fw_standby_mode: To indicate whether the 548 * ALPM FW standby mode is allowed 549 */ 550 uint32_t allow_alpm_fw_standby_mode : 1; 551 552 /* 553 * @dsc_enable_status: DSC enable status in driver 554 */ 555 uint32_t dsc_enable_status : 1; 556 557 /** 558 * @fec_enable_status: receive fec enable/disable status from driver 559 */ 560 uint32_t fec_enable_status : 1; 561 562 /* 563 * @smu_optimizations_en: SMU power optimization. 564 * Only when active display is Replay capable and display enters Replay. 565 * Trigger interrupt to SMU to powerup/down. 566 */ 567 uint32_t smu_optimizations_en : 1; 568 569 /** 570 * @phy_power_state: Indicates current phy power state 571 */ 572 uint32_t phy_power_state : 1; 573 574 /** 575 * @link_power_state: Indicates current link power state 576 */ 577 uint32_t link_power_state : 1; 578 /** 579 * Use TPS3 signal when restore main link. 580 */ 581 uint32_t force_wakeup_by_tps3 : 1; 582 /** 583 * @is_alpm_initialized: Indicates whether ALPM is initialized 584 */ 585 uint32_t is_alpm_initialized : 1; 586 587 /** 588 * @alpm_mode: Indicates ALPM mode selected 589 */ 590 uint32_t alpm_mode : 2; 591 } bitfields; 592 593 uint32_t u32All; 594 }; 595 596 union fw_assisted_mclk_switch_version { 597 struct { 598 uint8_t minor : 5; 599 uint8_t major : 3; 600 }; 601 uint8_t ver; 602 }; 603 604 /** 605 * DMUB feature capabilities. 606 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 607 */ 608 struct dmub_feature_caps { 609 /** 610 * Max PSR version supported by FW. 611 */ 612 uint8_t psr; 613 uint8_t fw_assisted_mclk_switch_ver; 614 uint8_t reserved[4]; 615 uint8_t subvp_psr_support; 616 uint8_t gecc_enable; 617 uint8_t replay_supported; 618 uint8_t replay_reserved[3]; 619 uint8_t abm_aux_backlight_support; 620 }; 621 622 struct dmub_visual_confirm_color { 623 /** 624 * Maximum 10 bits color value 625 */ 626 uint16_t color_r_cr; 627 uint16_t color_g_y; 628 uint16_t color_b_cb; 629 uint16_t panel_inst; 630 }; 631 632 //============================================================================== 633 //</DMUB_TYPES>================================================================= 634 //============================================================================== 635 //< DMUB_META>================================================================== 636 //============================================================================== 637 #pragma pack(push, 1) 638 639 /* Magic value for identifying dmub_fw_meta_info */ 640 #define DMUB_FW_META_MAGIC 0x444D5542 641 642 /* Offset from the end of the file to the dmub_fw_meta_info */ 643 #define DMUB_FW_META_OFFSET 0x24 644 645 /** 646 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 647 */ 648 union dmub_fw_meta_feature_bits { 649 struct { 650 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 651 uint32_t reserved : 31; 652 } bits; /**< status bits */ 653 uint32_t all; /**< 32-bit access to status bits */ 654 }; 655 656 /** 657 * struct dmub_fw_meta_info - metadata associated with fw binary 658 * 659 * NOTE: This should be considered a stable API. Fields should 660 * not be repurposed or reordered. New fields should be 661 * added instead to extend the structure. 662 * 663 * @magic_value: magic value identifying DMUB firmware meta info 664 * @fw_region_size: size of the firmware state region 665 * @trace_buffer_size: size of the tracebuffer region 666 * @fw_version: the firmware version information 667 * @dal_fw: 1 if the firmware is DAL 668 * @shared_state_size: size of the shared state region in bytes 669 * @shared_state_features: number of shared state features 670 */ 671 struct dmub_fw_meta_info { 672 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 673 uint32_t fw_region_size; /**< size of the firmware state region */ 674 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 675 uint32_t fw_version; /**< the firmware version information */ 676 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 677 uint8_t reserved[3]; /**< padding bits */ 678 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 679 uint16_t shared_state_features; /**< number of shared state features */ 680 uint16_t reserved2; /**< padding bytes */ 681 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 682 }; 683 684 /** 685 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 686 */ 687 union dmub_fw_meta { 688 struct dmub_fw_meta_info info; /**< metadata info */ 689 uint8_t reserved[64]; /**< padding bits */ 690 }; 691 692 #pragma pack(pop) 693 694 //============================================================================== 695 //< DMUB Trace Buffer>================================================================ 696 //============================================================================== 697 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 698 /** 699 * dmub_trace_code_t - firmware trace code, 32-bits 700 */ 701 typedef uint32_t dmub_trace_code_t; 702 703 /** 704 * struct dmcub_trace_buf_entry - Firmware trace entry 705 */ 706 struct dmcub_trace_buf_entry { 707 dmub_trace_code_t trace_code; /**< trace code for the event */ 708 uint32_t tick_count; /**< the tick count at time of trace */ 709 uint32_t param0; /**< trace defined parameter 0 */ 710 uint32_t param1; /**< trace defined parameter 1 */ 711 }; 712 #endif 713 714 //============================================================================== 715 //< DMUB_STATUS>================================================================ 716 //============================================================================== 717 718 /** 719 * DMCUB scratch registers can be used to determine firmware status. 720 * Current scratch register usage is as follows: 721 * 722 * SCRATCH0: FW Boot Status register 723 * SCRATCH5: LVTMA Status Register 724 * SCRATCH15: FW Boot Options register 725 */ 726 727 /** 728 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 729 */ 730 union dmub_fw_boot_status { 731 struct { 732 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 733 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 734 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 735 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 736 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 737 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 738 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 739 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 740 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 741 } bits; /**< status bits */ 742 uint32_t all; /**< 32-bit access to status bits */ 743 }; 744 745 /** 746 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 747 */ 748 enum dmub_fw_boot_status_bit { 749 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 750 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 751 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 752 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 753 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 754 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 755 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 756 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 757 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 758 }; 759 760 /* Register bit definition for SCRATCH5 */ 761 union dmub_lvtma_status { 762 struct { 763 uint32_t psp_ok : 1; 764 uint32_t edp_on : 1; 765 uint32_t reserved : 30; 766 } bits; 767 uint32_t all; 768 }; 769 770 enum dmub_lvtma_status_bit { 771 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 772 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 773 }; 774 775 enum dmub_ips_disable_type { 776 DMUB_IPS_ENABLE = 0, 777 DMUB_IPS_DISABLE_ALL = 1, 778 DMUB_IPS_DISABLE_IPS1 = 2, 779 DMUB_IPS_DISABLE_IPS2 = 3, 780 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 781 DMUB_IPS_DISABLE_DYNAMIC = 5, 782 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 783 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 784 }; 785 786 enum dmub_ips_rcg_disable_type { 787 DMUB_IPS_RCG_ENABLE = 0, 788 DMUB_IPS0_RCG_DISABLE = 1, 789 DMUB_IPS1_RCG_DISABLE = 2, 790 DMUB_IPS_RCG_DISABLE = 3 791 }; 792 793 enum dmub_ips_in_vpb_disable_type { 794 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 795 DMUB_IPS_VPB_DISABLE_ALL = 1, 796 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 797 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 798 }; 799 800 #define DMUB_IPS1_ALLOW_MASK 0x00000001 801 #define DMUB_IPS2_ALLOW_MASK 0x00000002 802 #define DMUB_IPS1_COMMIT_MASK 0x00000004 803 #define DMUB_IPS2_COMMIT_MASK 0x00000008 804 805 enum dmub_ips_comand_type { 806 /** 807 * Start/stop IPS residency measurements for a given IPS mode 808 */ 809 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 810 /** 811 * Query IPS residency information for a given IPS mode 812 */ 813 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 814 }; 815 816 /** 817 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 818 */ 819 union dmub_fw_boot_options { 820 struct { 821 uint32_t pemu_env : 1; /**< 1 if PEMU */ 822 uint32_t fpga_env : 1; /**< 1 if FPGA */ 823 uint32_t optimized_init : 1; /**< 1 if optimized init */ 824 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 825 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 826 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 827 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 828 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 829 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 830 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 831 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 832 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 833 uint32_t power_optimization: 1; 834 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 835 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 836 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 837 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 838 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 839 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 840 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 841 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 842 uint32_t ips_disable: 3; /* options to disable ips support*/ 843 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 844 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 845 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 846 uint32_t reserved : 6; /**< reserved */ 847 } bits; /**< boot bits */ 848 uint32_t all; /**< 32-bit access to bits */ 849 }; 850 851 enum dmub_fw_boot_options_bit { 852 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 853 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 854 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 855 }; 856 857 //============================================================================== 858 //< DMUB_SHARED_STATE>========================================================== 859 //============================================================================== 860 861 /** 862 * Shared firmware state between driver and firmware for lockless communication 863 * in situations where the inbox/outbox may be unavailable. 864 * 865 * Each structure *must* be at most 256-bytes in size. The layout allocation is 866 * described below: 867 * 868 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 869 */ 870 871 /** 872 * enum dmub_shared_state_feature_id - List of shared state features. 873 */ 874 enum dmub_shared_state_feature_id { 875 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 876 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 877 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 878 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 879 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 880 }; 881 882 /** 883 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 884 */ 885 union dmub_shared_state_ips_fw_signals { 886 struct { 887 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 888 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 889 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 890 uint32_t detection_required : 1; /**< 1 if detection is required */ 891 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 892 uint32_t reserved_bits : 27; /**< Reversed */ 893 } bits; 894 uint32_t all; 895 }; 896 897 /** 898 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 899 */ 900 union dmub_shared_state_ips_driver_signals { 901 struct { 902 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 903 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 904 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 905 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 906 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 907 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 908 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 909 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 910 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 911 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 912 uint32_t reserved_bits : 22; /**< Reversed bits */ 913 } bits; 914 uint32_t all; 915 }; 916 917 /** 918 * IPS FW Version 919 */ 920 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 921 922 struct dmub_shared_state_debug_setup { 923 union { 924 struct { 925 uint32_t exclude_points[62]; 926 } profile_mode; 927 }; 928 }; 929 930 /** 931 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 932 */ 933 struct dmub_shared_state_ips_fw { 934 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 935 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 936 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 937 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 938 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 939 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 940 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 941 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 942 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 943 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 944 }; /* 248-bytes, fixed */ 945 946 /** 947 * IPS Driver Version 948 */ 949 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 950 951 /** 952 * struct dmub_shared_state_ips_driver - Driver state for IPS. 953 */ 954 struct dmub_shared_state_ips_driver { 955 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 956 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 957 }; /* 248-bytes, fixed */ 958 959 /** 960 * enum dmub_shared_state_feature_common - Generic payload. 961 */ 962 struct dmub_shared_state_feature_common { 963 uint32_t padding[62]; 964 }; /* 248-bytes, fixed */ 965 966 /** 967 * enum dmub_shared_state_feature_header - Feature description. 968 */ 969 struct dmub_shared_state_feature_header { 970 uint16_t id; /**< Feature ID */ 971 uint16_t version; /**< Feature version */ 972 uint32_t reserved; /**< Reserved bytes. */ 973 }; /* 8 bytes, fixed */ 974 975 /** 976 * struct dmub_shared_state_feature_block - Feature block. 977 */ 978 struct dmub_shared_state_feature_block { 979 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 980 union dmub_shared_feature_state_union { 981 struct dmub_shared_state_feature_common common; /**< Generic data */ 982 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 983 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 984 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 985 } data; /**< Shared state data. */ 986 }; /* 256-bytes, fixed */ 987 988 /** 989 * Shared state size in bytes. 990 */ 991 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 992 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 993 994 //============================================================================== 995 //</DMUB_STATUS>================================================================ 996 //============================================================================== 997 //< DMUB_VBIOS>================================================================= 998 //============================================================================== 999 1000 /* 1001 * enum dmub_cmd_vbios_type - VBIOS commands. 1002 * 1003 * Command IDs should be treated as stable ABI. 1004 * Do not reuse or modify IDs. 1005 */ 1006 enum dmub_cmd_vbios_type { 1007 /** 1008 * Configures the DIG encoder. 1009 */ 1010 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1011 /** 1012 * Controls the PHY. 1013 */ 1014 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1015 /** 1016 * Sets the pixel clock/symbol clock. 1017 */ 1018 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1019 /** 1020 * Enables or disables power gating. 1021 */ 1022 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1023 /** 1024 * Controls embedded panels. 1025 */ 1026 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1027 /** 1028 * Query DP alt status on a transmitter. 1029 */ 1030 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1031 /** 1032 * Control PHY FSM 1033 */ 1034 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1035 /** 1036 * Controls domain power gating 1037 */ 1038 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1039 }; 1040 1041 //============================================================================== 1042 //</DMUB_VBIOS>================================================================= 1043 //============================================================================== 1044 //< DMUB_GPINT>================================================================= 1045 //============================================================================== 1046 1047 /** 1048 * The shifts and masks below may alternatively be used to format and read 1049 * the command register bits. 1050 */ 1051 1052 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1053 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1054 1055 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1056 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1057 1058 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1059 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1060 1061 /** 1062 * Command responses. 1063 */ 1064 1065 /** 1066 * Return response for DMUB_GPINT__STOP_FW command. 1067 */ 1068 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1069 1070 /** 1071 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1072 */ 1073 union dmub_gpint_data_register { 1074 struct { 1075 uint32_t param : 16; /**< 16-bit parameter */ 1076 uint32_t command_code : 12; /**< GPINT command */ 1077 uint32_t status : 4; /**< Command status bit */ 1078 } bits; /**< GPINT bit access */ 1079 uint32_t all; /**< GPINT 32-bit access */ 1080 }; 1081 1082 /* 1083 * enum dmub_gpint_command - GPINT command to DMCUB FW 1084 * 1085 * Command IDs should be treated as stable ABI. 1086 * Do not reuse or modify IDs. 1087 */ 1088 enum dmub_gpint_command { 1089 /** 1090 * Invalid command, ignored. 1091 */ 1092 DMUB_GPINT__INVALID_COMMAND = 0, 1093 /** 1094 * DESC: Queries the firmware version. 1095 * RETURN: Firmware version. 1096 */ 1097 DMUB_GPINT__GET_FW_VERSION = 1, 1098 /** 1099 * DESC: Halts the firmware. 1100 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1101 */ 1102 DMUB_GPINT__STOP_FW = 2, 1103 /** 1104 * DESC: Get PSR state from FW. 1105 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1106 */ 1107 DMUB_GPINT__GET_PSR_STATE = 7, 1108 /** 1109 * DESC: Notifies DMCUB of the currently active streams. 1110 * ARGS: Stream mask, 1 bit per active stream index. 1111 */ 1112 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1113 /** 1114 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1115 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1116 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1117 * RETURN: PSR residency in milli-percent. 1118 */ 1119 DMUB_GPINT__PSR_RESIDENCY = 9, 1120 1121 /** 1122 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1123 */ 1124 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1125 1126 /** 1127 * DESC: Get REPLAY state from FW. 1128 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1129 */ 1130 DMUB_GPINT__GET_REPLAY_STATE = 13, 1131 1132 /** 1133 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1134 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1135 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1136 * RETURN: REPLAY residency in milli-percent. 1137 */ 1138 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1139 1140 /** 1141 * DESC: Copy bounding box to the host. 1142 * ARGS: Version of bounding box to copy 1143 * RETURN: Result of copying bounding box 1144 */ 1145 DMUB_GPINT__BB_COPY = 96, 1146 1147 /** 1148 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1149 * ARGS: The word3 for the 64 bit address 1150 */ 1151 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1152 1153 /** 1154 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1155 * ARGS: The word2 for the 64 bit address 1156 */ 1157 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1158 1159 /** 1160 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1161 * ARGS: The word1 for the 64 bit address 1162 */ 1163 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1164 1165 /** 1166 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1167 * ARGS: The word0 for the 64 bit address 1168 */ 1169 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1170 1171 /** 1172 * DESC: Updates the trace buffer lower 32-bit mask. 1173 * ARGS: The new mask 1174 * RETURN: Lower 32-bit mask. 1175 */ 1176 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1177 1178 /** 1179 * DESC: Updates the trace buffer mask bit0~bit15. 1180 * ARGS: The new mask 1181 * RETURN: Lower 32-bit mask. 1182 */ 1183 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1184 1185 /** 1186 * DESC: Updates the trace buffer mask bit16~bit31. 1187 * ARGS: The new mask 1188 * RETURN: Lower 32-bit mask. 1189 */ 1190 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1191 1192 /** 1193 * DESC: Updates the trace buffer mask bit32~bit47. 1194 * ARGS: The new mask 1195 * RETURN: Lower 32-bit mask. 1196 */ 1197 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1198 1199 /** 1200 * DESC: Updates the trace buffer mask bit48~bit63. 1201 * ARGS: The new mask 1202 * RETURN: Lower 32-bit mask. 1203 */ 1204 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1205 1206 /** 1207 * DESC: Read the trace buffer mask bi0~bit15. 1208 */ 1209 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1210 1211 /** 1212 * DESC: Read the trace buffer mask bit16~bit31. 1213 */ 1214 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1215 1216 /** 1217 * DESC: Read the trace buffer mask bi32~bit47. 1218 */ 1219 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1220 1221 /** 1222 * DESC: Updates the trace buffer mask bit32~bit63. 1223 */ 1224 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1225 1226 /** 1227 * DESC: Set IPS residency measurement 1228 * ARGS: 0 - Disable ips measurement 1229 * 1 - Enable ips measurement 1230 */ 1231 DMUB_GPINT__IPS_RESIDENCY = 121, 1232 1233 /** 1234 * DESC: Enable measurements for various task duration 1235 * ARGS: 0 - Disable measurement 1236 * 1 - Enable measurement 1237 */ 1238 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1239 1240 /** 1241 * DESC: Gets IPS residency in microseconds 1242 * ARGS: 0 - Return IPS1 residency 1243 * 1 - Return IPS2 residency 1244 * 2 - Return IPS1_RCG residency 1245 * 3 - Return IPS1_ONO2_ON residency 1246 * RETURN: Total residency in microseconds - lower 32 bits 1247 */ 1248 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1249 1250 /** 1251 * DESC: Gets IPS1 histogram counts 1252 * ARGS: Bucket index 1253 * RETURN: Total count for the bucket 1254 */ 1255 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1256 1257 /** 1258 * DESC: Gets IPS2 histogram counts 1259 * ARGS: Bucket index 1260 * RETURN: Total count for the bucket 1261 */ 1262 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1263 1264 /** 1265 * DESC: Gets IPS residency 1266 * ARGS: 0 - Return IPS1 residency 1267 * 1 - Return IPS2 residency 1268 * 2 - Return IPS1_RCG residency 1269 * 3 - Return IPS1_ONO2_ON residency 1270 * RETURN: Total residency in milli-percent. 1271 */ 1272 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1273 1274 /** 1275 * DESC: Gets IPS1_RCG histogram counts 1276 * ARGS: Bucket index 1277 * RETURN: Total count for the bucket 1278 */ 1279 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1280 1281 /** 1282 * DESC: Gets IPS1_ONO2_ON histogram counts 1283 * ARGS: Bucket index 1284 * RETURN: Total count for the bucket 1285 */ 1286 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1287 1288 /** 1289 * DESC: Gets IPS entry counter during residency measurement 1290 * ARGS: 0 - Return IPS1 entry counts 1291 * 1 - Return IPS2 entry counts 1292 * 2 - Return IPS1_RCG entry counts 1293 * 3 - Return IPS2_ONO2_ON entry counts 1294 * RETURN: Entry counter for selected IPS mode 1295 */ 1296 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1297 1298 /** 1299 * DESC: Gets IPS inactive residency in microseconds 1300 * ARGS: 0 - Return IPS1_MAX residency 1301 * 1 - Return IPS2 residency 1302 * 2 - Return IPS1_RCG residency 1303 * 3 - Return IPS1_ONO2_ON residency 1304 * RETURN: Total inactive residency in microseconds - lower 32 bits 1305 */ 1306 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1307 1308 /** 1309 * DESC: Gets IPS inactive residency in microseconds 1310 * ARGS: 0 - Return IPS1_MAX residency 1311 * 1 - Return IPS2 residency 1312 * 2 - Return IPS1_RCG residency 1313 * 3 - Return IPS1_ONO2_ON residency 1314 * RETURN: Total inactive residency in microseconds - upper 32 bits 1315 */ 1316 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1317 1318 /** 1319 * DESC: Gets IPS residency in microseconds 1320 * ARGS: 0 - Return IPS1 residency 1321 * 1 - Return IPS2 residency 1322 * 2 - Return IPS1_RCG residency 1323 * 3 - Return IPS1_ONO2_ON residency 1324 * RETURN: Total residency in microseconds - upper 32 bits 1325 */ 1326 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1327 /** 1328 * DESC: Setup debug configs. 1329 */ 1330 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1331 /** 1332 * DESC: Initiates IPS wake sequence. 1333 */ 1334 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1335 }; 1336 1337 /** 1338 * INBOX0 generic command definition 1339 */ 1340 union dmub_inbox0_cmd_common { 1341 struct { 1342 uint32_t command_code: 8; /**< INBOX0 command code */ 1343 uint32_t param: 24; /**< 24-bit parameter */ 1344 } bits; 1345 uint32_t all; 1346 }; 1347 1348 /** 1349 * INBOX0 hw_lock command definition 1350 */ 1351 union dmub_inbox0_cmd_lock_hw { 1352 struct { 1353 uint32_t command_code: 8; 1354 1355 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1356 uint32_t hw_lock_client: 2; 1357 1358 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1359 uint32_t otg_inst: 3; 1360 uint32_t opp_inst: 3; 1361 uint32_t dig_inst: 3; 1362 1363 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1364 uint32_t lock_pipe: 1; 1365 uint32_t lock_cursor: 1; 1366 uint32_t lock_dig: 1; 1367 uint32_t triple_buffer_lock: 1; 1368 1369 uint32_t lock: 1; /**< Lock */ 1370 uint32_t should_release: 1; /**< Release */ 1371 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1372 } bits; 1373 uint32_t all; 1374 }; 1375 1376 union dmub_inbox0_data_register { 1377 union dmub_inbox0_cmd_common inbox0_cmd_common; 1378 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1379 }; 1380 1381 enum dmub_inbox0_command { 1382 /** 1383 * DESC: Invalid command, ignored. 1384 */ 1385 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1386 /** 1387 * DESC: Notification to acquire/release HW lock 1388 * ARGS: 1389 */ 1390 DMUB_INBOX0_CMD__HW_LOCK = 1, 1391 }; 1392 //============================================================================== 1393 //</DMUB_GPINT>================================================================= 1394 //============================================================================== 1395 //< DMUB_CMD>=================================================================== 1396 //============================================================================== 1397 1398 /** 1399 * Size in bytes of each DMUB command. 1400 */ 1401 #define DMUB_RB_CMD_SIZE 64 1402 1403 /** 1404 * Maximum number of items in the DMUB ringbuffer. 1405 */ 1406 #define DMUB_RB_MAX_ENTRY 128 1407 1408 /** 1409 * Ringbuffer size in bytes. 1410 */ 1411 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1412 1413 /** 1414 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1415 */ 1416 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1417 1418 /** 1419 * Ringbuffer size in bytes. 1420 */ 1421 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1422 1423 /** 1424 * REG_SET mask for reg offload. 1425 */ 1426 #define REG_SET_MASK 0xFFFF 1427 1428 /* 1429 * enum dmub_cmd_type - DMUB inbox command. 1430 * 1431 * Command IDs should be treated as stable ABI. 1432 * Do not reuse or modify IDs. 1433 */ 1434 enum dmub_cmd_type { 1435 /** 1436 * Invalid command. 1437 */ 1438 DMUB_CMD__NULL = 0, 1439 /** 1440 * Read modify write register sequence offload. 1441 */ 1442 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1443 /** 1444 * Field update register sequence offload. 1445 */ 1446 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1447 /** 1448 * Burst write sequence offload. 1449 */ 1450 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1451 /** 1452 * Reg wait sequence offload. 1453 */ 1454 DMUB_CMD__REG_REG_WAIT = 4, 1455 /** 1456 * Workaround to avoid HUBP underflow during NV12 playback. 1457 */ 1458 DMUB_CMD__PLAT_54186_WA = 5, 1459 /** 1460 * Command type used to query FW feature caps. 1461 */ 1462 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1463 /** 1464 * Command type used to get visual confirm color. 1465 */ 1466 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1467 /** 1468 * Command type used for all PSR commands. 1469 */ 1470 DMUB_CMD__PSR = 64, 1471 /** 1472 * Command type used for all MALL commands. 1473 */ 1474 DMUB_CMD__MALL = 65, 1475 /** 1476 * Command type used for all ABM commands. 1477 */ 1478 DMUB_CMD__ABM = 66, 1479 /** 1480 * Command type used to update dirty rects in FW. 1481 */ 1482 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1483 /** 1484 * Command type used to update cursor info in FW. 1485 */ 1486 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1487 /** 1488 * Command type used for HW locking in FW. 1489 */ 1490 DMUB_CMD__HW_LOCK = 69, 1491 /** 1492 * Command type used to access DP AUX. 1493 */ 1494 DMUB_CMD__DP_AUX_ACCESS = 70, 1495 /** 1496 * Command type used for OUTBOX1 notification enable 1497 */ 1498 DMUB_CMD__OUTBOX1_ENABLE = 71, 1499 1500 /** 1501 * Command type used for all idle optimization commands. 1502 */ 1503 DMUB_CMD__IDLE_OPT = 72, 1504 /** 1505 * Command type used for all clock manager commands. 1506 */ 1507 DMUB_CMD__CLK_MGR = 73, 1508 /** 1509 * Command type used for all panel control commands. 1510 */ 1511 DMUB_CMD__PANEL_CNTL = 74, 1512 1513 /** 1514 * Command type used for all CAB commands. 1515 */ 1516 DMUB_CMD__CAB_FOR_SS = 75, 1517 1518 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1519 1520 /** 1521 * Command type used for interfacing with DPIA. 1522 */ 1523 DMUB_CMD__DPIA = 77, 1524 /** 1525 * Command type used for EDID CEA parsing 1526 */ 1527 DMUB_CMD__EDID_CEA = 79, 1528 /** 1529 * Command type used for getting usbc cable ID 1530 */ 1531 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1532 /** 1533 * Command type used to query HPD state. 1534 */ 1535 DMUB_CMD__QUERY_HPD_STATE = 82, 1536 /** 1537 * Command type used for all VBIOS interface commands. 1538 */ 1539 /** 1540 * Command type used for all REPLAY commands. 1541 */ 1542 DMUB_CMD__REPLAY = 83, 1543 1544 /** 1545 * Command type used for all SECURE_DISPLAY commands. 1546 */ 1547 DMUB_CMD__SECURE_DISPLAY = 85, 1548 1549 /** 1550 * Command type used to set DPIA HPD interrupt state 1551 */ 1552 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1553 1554 /** 1555 * Command type used for all PSP commands. 1556 */ 1557 DMUB_CMD__PSP = 88, 1558 1559 /** 1560 * Command type used for all Fused IO commands. 1561 */ 1562 DMUB_CMD__FUSED_IO = 89, 1563 1564 /** 1565 * Command type used for all LSDMA commands. 1566 */ 1567 DMUB_CMD__LSDMA = 90, 1568 1569 /** 1570 * Command type use for all IPS commands. 1571 */ 1572 DMUB_CMD__IPS = 91, 1573 1574 DMUB_CMD__VBIOS = 128, 1575 }; 1576 1577 /** 1578 * enum dmub_out_cmd_type - DMUB outbox commands. 1579 */ 1580 enum dmub_out_cmd_type { 1581 /** 1582 * Invalid outbox command, ignored. 1583 */ 1584 DMUB_OUT_CMD__NULL = 0, 1585 /** 1586 * Command type used for DP AUX Reply data notification 1587 */ 1588 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1589 /** 1590 * Command type used for DP HPD event notification 1591 */ 1592 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1593 /** 1594 * Command type used for SET_CONFIG Reply notification 1595 */ 1596 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1597 /** 1598 * Command type used for USB4 DPIA notification 1599 */ 1600 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1601 /** 1602 * Command type used for HPD redetect notification 1603 */ 1604 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1605 /** 1606 * Command type used for Fused IO notification 1607 */ 1608 DMUB_OUT_CMD__FUSED_IO = 7, 1609 }; 1610 1611 /* DMUB_CMD__DPIA command sub-types. */ 1612 enum dmub_cmd_dpia_type { 1613 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1614 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1615 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1616 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1617 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1618 }; 1619 1620 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1621 enum dmub_cmd_dpia_notification_type { 1622 DPIA_NOTIFY__BW_ALLOCATION = 0, 1623 }; 1624 1625 #pragma pack(push, 1) 1626 1627 /** 1628 * struct dmub_cmd_header - Common command header fields. 1629 */ 1630 struct dmub_cmd_header { 1631 unsigned int type : 8; /**< command type */ 1632 unsigned int sub_type : 8; /**< command sub type */ 1633 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1634 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1635 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1636 unsigned int reserved0 : 5; /**< reserved bits */ 1637 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1638 unsigned int reserved1 : 2; /**< reserved bits */ 1639 }; 1640 1641 /* 1642 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1643 * 1644 * 60 payload bytes can hold up to 5 sets of read modify writes, 1645 * each take 3 dwords. 1646 * 1647 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1648 * 1649 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1650 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1651 */ 1652 struct dmub_cmd_read_modify_write_sequence { 1653 uint32_t addr; /**< register address */ 1654 uint32_t modify_mask; /**< modify mask */ 1655 uint32_t modify_value; /**< modify value */ 1656 }; 1657 1658 /** 1659 * Maximum number of ops in read modify write sequence. 1660 */ 1661 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1662 1663 /** 1664 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1665 */ 1666 struct dmub_rb_cmd_read_modify_write { 1667 struct dmub_cmd_header header; /**< command header */ 1668 /** 1669 * Read modify write sequence. 1670 */ 1671 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1672 }; 1673 1674 /* 1675 * Update a register with specified masks and values sequeunce 1676 * 1677 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1678 * 1679 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1680 * 1681 * 1682 * USE CASE: 1683 * 1. auto-increment register where additional read would update pointer and produce wrong result 1684 * 2. toggle a bit without read in the middle 1685 */ 1686 1687 struct dmub_cmd_reg_field_update_sequence { 1688 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1689 uint32_t modify_value; /**< value to update with */ 1690 }; 1691 1692 /** 1693 * Maximum number of ops in field update sequence. 1694 */ 1695 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1696 1697 /** 1698 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1699 */ 1700 struct dmub_rb_cmd_reg_field_update_sequence { 1701 struct dmub_cmd_header header; /**< command header */ 1702 uint32_t addr; /**< register address */ 1703 /** 1704 * Field update sequence. 1705 */ 1706 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1707 }; 1708 1709 1710 /** 1711 * Maximum number of burst write values. 1712 */ 1713 #define DMUB_BURST_WRITE_VALUES__MAX 14 1714 1715 /* 1716 * struct dmub_rb_cmd_burst_write - Burst write 1717 * 1718 * support use case such as writing out LUTs. 1719 * 1720 * 60 payload bytes can hold up to 14 values to write to given address 1721 * 1722 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1723 */ 1724 struct dmub_rb_cmd_burst_write { 1725 struct dmub_cmd_header header; /**< command header */ 1726 uint32_t addr; /**< register start address */ 1727 /** 1728 * Burst write register values. 1729 */ 1730 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1731 }; 1732 1733 /** 1734 * struct dmub_rb_cmd_common - Common command header 1735 */ 1736 struct dmub_rb_cmd_common { 1737 struct dmub_cmd_header header; /**< command header */ 1738 /** 1739 * Padding to RB_CMD_SIZE 1740 */ 1741 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1742 }; 1743 1744 /** 1745 * struct dmub_cmd_reg_wait_data - Register wait data 1746 */ 1747 struct dmub_cmd_reg_wait_data { 1748 uint32_t addr; /**< Register address */ 1749 uint32_t mask; /**< Mask for register bits */ 1750 uint32_t condition_field_value; /**< Value to wait for */ 1751 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1752 }; 1753 1754 /** 1755 * struct dmub_rb_cmd_reg_wait - Register wait command 1756 */ 1757 struct dmub_rb_cmd_reg_wait { 1758 struct dmub_cmd_header header; /**< Command header */ 1759 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1760 }; 1761 1762 /** 1763 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1764 * 1765 * Reprograms surface parameters to avoid underflow. 1766 */ 1767 struct dmub_cmd_PLAT_54186_wa { 1768 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1769 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1770 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1771 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1772 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1773 struct { 1774 uint32_t hubp_inst : 4; /**< HUBP instance */ 1775 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1776 uint32_t immediate :1; /**< Immediate flip */ 1777 uint32_t vmid : 4; /**< VMID */ 1778 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1779 uint32_t reserved : 21; /**< Reserved */ 1780 } flip_params; /**< Pageflip parameters */ 1781 uint32_t reserved[9]; /**< Reserved bits */ 1782 }; 1783 1784 /** 1785 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1786 */ 1787 struct dmub_rb_cmd_PLAT_54186_wa { 1788 struct dmub_cmd_header header; /**< Command header */ 1789 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1790 }; 1791 1792 /** 1793 * enum dmub_cmd_mall_type - MALL commands 1794 */ 1795 enum dmub_cmd_mall_type { 1796 /** 1797 * Allows display refresh from MALL. 1798 */ 1799 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1800 /** 1801 * Disallows display refresh from MALL. 1802 */ 1803 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1804 /** 1805 * Cursor copy for MALL. 1806 */ 1807 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1808 /** 1809 * Controls DF requests. 1810 */ 1811 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1812 }; 1813 1814 /** 1815 * struct dmub_rb_cmd_mall - MALL command data. 1816 */ 1817 struct dmub_rb_cmd_mall { 1818 struct dmub_cmd_header header; /**< Common command header */ 1819 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1820 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1821 uint32_t tmr_delay; /**< Timer delay */ 1822 uint32_t tmr_scale; /**< Timer scale */ 1823 uint16_t cursor_width; /**< Cursor width in pixels */ 1824 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1825 uint16_t cursor_height; /**< Cursor height in pixels */ 1826 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1827 uint8_t debug_bits; /**< Debug bits */ 1828 1829 uint8_t reserved1; /**< Reserved bits */ 1830 uint8_t reserved2; /**< Reserved bits */ 1831 }; 1832 1833 /** 1834 * enum dmub_cmd_cab_type - CAB command data. 1835 */ 1836 enum dmub_cmd_cab_type { 1837 /** 1838 * No idle optimizations (i.e. no CAB) 1839 */ 1840 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1841 /** 1842 * No DCN requests for memory 1843 */ 1844 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1845 /** 1846 * Fit surfaces in CAB (i.e. CAB enable) 1847 */ 1848 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1849 /** 1850 * Do not fit surfaces in CAB (i.e. no CAB) 1851 */ 1852 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1853 }; 1854 1855 /** 1856 * struct dmub_rb_cmd_cab - CAB command data. 1857 */ 1858 struct dmub_rb_cmd_cab_for_ss { 1859 struct dmub_cmd_header header; 1860 uint8_t cab_alloc_ways; /* total number of ways */ 1861 uint8_t debug_bits; /* debug bits */ 1862 }; 1863 1864 /** 1865 * Enum for indicating which MCLK switch mode per pipe 1866 */ 1867 enum mclk_switch_mode { 1868 NONE = 0, 1869 FPO = 1, 1870 SUBVP = 2, 1871 VBLANK = 3, 1872 }; 1873 1874 /* Per pipe struct which stores the MCLK switch mode 1875 * data to be sent to DMUB. 1876 * Named "v2" for now -- once FPO and SUBVP are fully merged 1877 * the type name can be updated 1878 */ 1879 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1880 union { 1881 struct { 1882 uint32_t pix_clk_100hz; 1883 uint16_t main_vblank_start; 1884 uint16_t main_vblank_end; 1885 uint16_t mall_region_lines; 1886 uint16_t prefetch_lines; 1887 uint16_t prefetch_to_mall_start_lines; 1888 uint16_t processing_delay_lines; 1889 uint16_t htotal; // required to calculate line time for multi-display cases 1890 uint16_t vtotal; 1891 uint8_t main_pipe_index; 1892 uint8_t phantom_pipe_index; 1893 /* Since the microschedule is calculated in terms of OTG lines, 1894 * include any scaling factors to make sure when we get accurate 1895 * conversion when programming MALL_START_LINE (which is in terms 1896 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1897 * is 1/2 (numerator = 1, denominator = 2). 1898 */ 1899 uint8_t scale_factor_numerator; 1900 uint8_t scale_factor_denominator; 1901 uint8_t is_drr; 1902 uint8_t main_split_pipe_index; 1903 uint8_t phantom_split_pipe_index; 1904 } subvp_data; 1905 1906 struct { 1907 uint32_t pix_clk_100hz; 1908 uint16_t vblank_start; 1909 uint16_t vblank_end; 1910 uint16_t vstartup_start; 1911 uint16_t vtotal; 1912 uint16_t htotal; 1913 uint8_t vblank_pipe_index; 1914 uint8_t padding[1]; 1915 struct { 1916 uint8_t drr_in_use; 1917 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1918 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1919 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1920 uint8_t use_ramping; // Use ramping or not 1921 uint8_t drr_vblank_start_margin; 1922 } drr_info; // DRR considered as part of SubVP + VBLANK case 1923 } vblank_data; 1924 } pipe_config; 1925 1926 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1927 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1928 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1929 */ 1930 uint8_t mode; // enum mclk_switch_mode 1931 }; 1932 1933 /** 1934 * Config data for Sub-VP and FPO 1935 * Named "v2" for now -- once FPO and SUBVP are fully merged 1936 * the type name can be updated 1937 */ 1938 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1939 uint16_t watermark_a_cache; 1940 uint8_t vertical_int_margin_us; 1941 uint8_t pstate_allow_width_us; 1942 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1943 }; 1944 1945 /** 1946 * DMUB rb command definition for Sub-VP and FPO 1947 * Named "v2" for now -- once FPO and SUBVP are fully merged 1948 * the type name can be updated 1949 */ 1950 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1951 struct dmub_cmd_header header; 1952 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1953 }; 1954 1955 struct dmub_flip_addr_info { 1956 uint32_t surf_addr_lo; 1957 uint32_t surf_addr_c_lo; 1958 uint32_t meta_addr_lo; 1959 uint32_t meta_addr_c_lo; 1960 uint16_t surf_addr_hi; 1961 uint16_t surf_addr_c_hi; 1962 uint16_t meta_addr_hi; 1963 uint16_t meta_addr_c_hi; 1964 }; 1965 1966 struct dmub_fams2_flip_info { 1967 union { 1968 struct { 1969 uint8_t is_immediate: 1; 1970 } bits; 1971 uint8_t all; 1972 } config; 1973 uint8_t otg_inst; 1974 uint8_t pipe_mask; 1975 uint8_t pad; 1976 struct dmub_flip_addr_info addr_info; 1977 }; 1978 1979 struct dmub_rb_cmd_fams2_flip { 1980 struct dmub_cmd_header header; 1981 struct dmub_fams2_flip_info flip_info; 1982 }; 1983 1984 struct dmub_cmd_lsdma_data { 1985 union { 1986 struct lsdma_init_data { 1987 union dmub_addr gpu_addr_base; 1988 uint32_t ring_size; 1989 } init_data; 1990 struct lsdma_tiled_copy_data { 1991 uint32_t src_addr_lo; 1992 uint32_t src_addr_hi; 1993 uint32_t dst_addr_lo; 1994 uint32_t dst_addr_hi; 1995 1996 uint32_t src_x : 16; 1997 uint32_t src_y : 16; 1998 1999 uint32_t src_width : 16; 2000 uint32_t src_height : 16; 2001 2002 uint32_t dst_x : 16; 2003 uint32_t dst_y : 16; 2004 2005 uint32_t dst_width : 16; 2006 uint32_t dst_height : 16; 2007 2008 uint32_t rect_x : 16; 2009 uint32_t rect_y : 16; 2010 2011 uint32_t src_swizzle_mode : 5; 2012 uint32_t src_mip_max : 5; 2013 uint32_t src_mip_id : 5; 2014 uint32_t dst_mip_max : 5; 2015 uint32_t dst_swizzle_mode : 5; 2016 uint32_t dst_mip_id : 5; 2017 uint32_t tmz : 1; 2018 uint32_t dcc : 1; 2019 2020 uint32_t data_format : 6; 2021 uint32_t padding1 : 4; 2022 uint32_t dst_element_size : 3; 2023 uint32_t num_type : 3; 2024 uint32_t src_element_size : 3; 2025 uint32_t write_compress : 2; 2026 uint32_t cache_policy_dst : 2; 2027 uint32_t cache_policy_src : 2; 2028 uint32_t read_compress : 2; 2029 uint32_t src_dim : 2; 2030 uint32_t dst_dim : 2; 2031 uint32_t max_uncom : 1; 2032 2033 uint32_t max_com : 2; 2034 uint32_t padding : 30; 2035 } tiled_copy_data; 2036 struct lsdma_linear_copy_data { 2037 uint32_t count : 30; 2038 uint32_t cache_policy_dst : 2; 2039 2040 uint32_t tmz : 1; 2041 uint32_t cache_policy_src : 2; 2042 uint32_t padding : 29; 2043 2044 uint32_t src_lo; 2045 uint32_t src_hi; 2046 uint32_t dst_lo; 2047 uint32_t dst_hi; 2048 } linear_copy_data; 2049 struct lsdma_reg_write_data { 2050 uint32_t reg_addr; 2051 uint32_t reg_data; 2052 } reg_write_data; 2053 struct lsdma_pio_copy_data { 2054 union { 2055 struct { 2056 uint32_t byte_count : 26; 2057 uint32_t src_loc : 1; 2058 uint32_t dst_loc : 1; 2059 uint32_t src_addr_inc : 1; 2060 uint32_t dst_addr_inc : 1; 2061 uint32_t overlap_disable : 1; 2062 uint32_t constant_fill : 1; 2063 } fields; 2064 uint32_t raw; 2065 } packet; 2066 uint32_t src_lo; 2067 uint32_t src_hi; 2068 uint32_t dst_lo; 2069 uint32_t dst_hi; 2070 } pio_copy_data; 2071 struct lsdma_pio_constfill_data { 2072 union { 2073 struct { 2074 uint32_t byte_count : 26; 2075 uint32_t src_loc : 1; 2076 uint32_t dst_loc : 1; 2077 uint32_t src_addr_inc : 1; 2078 uint32_t dst_addr_inc : 1; 2079 uint32_t overlap_disable : 1; 2080 uint32_t constant_fill : 1; 2081 } fields; 2082 uint32_t raw; 2083 } packet; 2084 uint32_t dst_lo; 2085 uint32_t dst_hi; 2086 uint32_t data; 2087 } pio_constfill_data; 2088 2089 uint32_t all[14]; 2090 } u; 2091 2092 }; 2093 2094 struct dmub_rb_cmd_lsdma { 2095 struct dmub_cmd_header header; 2096 struct dmub_cmd_lsdma_data lsdma_data; 2097 }; 2098 2099 struct dmub_optc_state_v2 { 2100 uint32_t v_total_min; 2101 uint32_t v_total_max; 2102 uint32_t v_total_mid; 2103 uint32_t v_total_mid_frame_num; 2104 uint8_t program_manual_trigger; 2105 uint8_t tg_inst; 2106 uint8_t pad[2]; 2107 }; 2108 2109 struct dmub_optc_position { 2110 uint32_t vpos; 2111 uint32_t hpos; 2112 uint32_t frame; 2113 }; 2114 2115 struct dmub_rb_cmd_fams2_drr_update { 2116 struct dmub_cmd_header header; 2117 struct dmub_optc_state_v2 dmub_optc_state_req; 2118 }; 2119 2120 /* HW and FW global configuration data for FAMS2 */ 2121 /* FAMS2 types and structs */ 2122 enum fams2_stream_type { 2123 FAMS2_STREAM_TYPE_NONE = 0, 2124 FAMS2_STREAM_TYPE_VBLANK = 1, 2125 FAMS2_STREAM_TYPE_VACTIVE = 2, 2126 FAMS2_STREAM_TYPE_DRR = 3, 2127 FAMS2_STREAM_TYPE_SUBVP = 4, 2128 }; 2129 2130 struct dmub_rect16 { 2131 /** 2132 * Dirty rect x offset. 2133 */ 2134 uint16_t x; 2135 2136 /** 2137 * Dirty rect y offset. 2138 */ 2139 uint16_t y; 2140 2141 /** 2142 * Dirty rect width. 2143 */ 2144 uint16_t width; 2145 2146 /** 2147 * Dirty rect height. 2148 */ 2149 uint16_t height; 2150 }; 2151 2152 /* static stream state */ 2153 struct dmub_fams2_legacy_stream_static_state { 2154 uint8_t vactive_det_fill_delay_otg_vlines; 2155 uint8_t programming_delay_otg_vlines; 2156 }; //v0 2157 2158 struct dmub_fams2_subvp_stream_static_state { 2159 uint16_t vratio_numerator; 2160 uint16_t vratio_denominator; 2161 uint16_t phantom_vtotal; 2162 uint16_t phantom_vactive; 2163 union { 2164 struct { 2165 uint8_t is_multi_planar : 1; 2166 uint8_t is_yuv420 : 1; 2167 } bits; 2168 uint8_t all; 2169 } config; 2170 uint8_t programming_delay_otg_vlines; 2171 uint8_t prefetch_to_mall_otg_vlines; 2172 uint8_t phantom_otg_inst; 2173 uint8_t phantom_pipe_mask; 2174 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2175 }; //v0 2176 2177 struct dmub_fams2_drr_stream_static_state { 2178 uint16_t nom_stretched_vtotal; 2179 uint8_t programming_delay_otg_vlines; 2180 uint8_t only_stretch_if_required; 2181 uint8_t pad[2]; 2182 }; //v0 2183 2184 struct dmub_fams2_cmd_legacy_stream_static_state { 2185 uint16_t vactive_det_fill_delay_otg_vlines; 2186 uint16_t programming_delay_otg_vlines; 2187 }; //v1 2188 2189 struct dmub_fams2_cmd_subvp_stream_static_state { 2190 uint16_t vratio_numerator; 2191 uint16_t vratio_denominator; 2192 uint16_t phantom_vtotal; 2193 uint16_t phantom_vactive; 2194 uint16_t programming_delay_otg_vlines; 2195 uint16_t prefetch_to_mall_otg_vlines; 2196 union { 2197 struct { 2198 uint8_t is_multi_planar : 1; 2199 uint8_t is_yuv420 : 1; 2200 } bits; 2201 uint8_t all; 2202 } config; 2203 uint8_t phantom_otg_inst; 2204 uint8_t phantom_pipe_mask; 2205 uint8_t pad0; 2206 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2207 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2208 }; //v1 2209 2210 struct dmub_fams2_cmd_drr_stream_static_state { 2211 uint16_t nom_stretched_vtotal; 2212 uint16_t programming_delay_otg_vlines; 2213 uint8_t only_stretch_if_required; 2214 uint8_t pad[3]; 2215 }; //v1 2216 2217 union dmub_fams2_stream_static_sub_state { 2218 struct dmub_fams2_legacy_stream_static_state legacy; 2219 struct dmub_fams2_subvp_stream_static_state subvp; 2220 struct dmub_fams2_drr_stream_static_state drr; 2221 }; //v0 2222 2223 union dmub_fams2_cmd_stream_static_sub_state { 2224 COMMON_STREAM_STATIC_SUB_STATE 2225 }; //v1 2226 2227 union dmub_fams2_stream_static_sub_state_v2 { 2228 COMMON_STREAM_STATIC_SUB_STATE 2229 }; //v2 2230 2231 struct dmub_fams2_stream_static_state { 2232 enum fams2_stream_type type; 2233 uint32_t otg_vline_time_ns; 2234 uint32_t otg_vline_time_ticks; 2235 uint16_t htotal; 2236 uint16_t vtotal; // nominal vtotal 2237 uint16_t vblank_start; 2238 uint16_t vblank_end; 2239 uint16_t max_vtotal; 2240 uint16_t allow_start_otg_vline; 2241 uint16_t allow_end_otg_vline; 2242 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2243 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2244 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2245 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2246 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2247 union { 2248 struct { 2249 uint8_t is_drr: 1; // stream is DRR enabled 2250 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2251 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2252 } bits; 2253 uint8_t all; 2254 } config; 2255 uint8_t otg_inst; 2256 uint8_t pipe_mask; // pipe mask for the whole config 2257 uint8_t num_planes; 2258 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2259 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2260 union dmub_fams2_stream_static_sub_state sub_state; 2261 }; //v0 2262 2263 struct dmub_fams2_cmd_stream_static_base_state { 2264 enum fams2_stream_type type; 2265 uint32_t otg_vline_time_ns; 2266 uint32_t otg_vline_time_ticks; 2267 uint16_t htotal; 2268 uint16_t vtotal; // nominal vtotal 2269 uint16_t vblank_start; 2270 uint16_t vblank_end; 2271 uint16_t max_vtotal; 2272 uint16_t allow_start_otg_vline; 2273 uint16_t allow_end_otg_vline; 2274 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2275 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2276 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2277 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2278 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2279 union { 2280 struct { 2281 uint8_t is_drr : 1; // stream is DRR enabled 2282 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2283 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2284 } bits; 2285 uint8_t all; 2286 } config; 2287 uint8_t otg_inst; 2288 uint8_t pipe_mask; // pipe mask for the whole config 2289 uint8_t num_planes; 2290 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2291 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2292 }; //v1 2293 2294 struct dmub_fams2_stream_static_state_v1 { 2295 struct dmub_fams2_cmd_stream_static_base_state base; 2296 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2297 }; //v1 2298 2299 /** 2300 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2301 * p-state request to allow latency 2302 */ 2303 enum dmub_fams2_allow_delay_check_mode { 2304 /* No check for request to allow delay */ 2305 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2306 /* Check for request to allow delay */ 2307 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2308 /* Check for prepare to allow delay */ 2309 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2310 }; 2311 2312 union dmub_fams2_global_feature_config { 2313 struct { 2314 uint32_t enable: 1; 2315 uint32_t enable_ppt_check: 1; 2316 uint32_t enable_stall_recovery: 1; 2317 uint32_t enable_debug: 1; 2318 uint32_t enable_offload_flip: 1; 2319 uint32_t enable_visual_confirm: 1; 2320 uint32_t allow_delay_check_mode: 2; 2321 uint32_t reserved: 24; 2322 } bits; 2323 uint32_t all; 2324 }; 2325 2326 struct dmub_cmd_fams2_global_config { 2327 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2328 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2329 uint32_t num_streams; 2330 union dmub_fams2_global_feature_config features; 2331 uint32_t recovery_timeout_us; 2332 uint32_t hwfq_flip_programming_delay_us; 2333 }; 2334 2335 union dmub_cmd_fams2_config { 2336 struct dmub_cmd_fams2_global_config global; 2337 struct dmub_fams2_stream_static_state stream; //v0 2338 union { 2339 struct dmub_fams2_cmd_stream_static_base_state base; 2340 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2341 } stream_v1; //v1 2342 }; 2343 2344 struct dmub_fams2_config_v2 { 2345 struct dmub_cmd_fams2_global_config global; 2346 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2347 }; 2348 2349 /** 2350 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2351 */ 2352 struct dmub_rb_cmd_fams2 { 2353 struct dmub_cmd_header header; 2354 union dmub_cmd_fams2_config config; 2355 }; 2356 2357 /** 2358 * Indirect buffer descriptor 2359 */ 2360 struct dmub_ib_data { 2361 union dmub_addr src; // location of indirect buffer in memory 2362 uint16_t size; // indirect buffer size in bytes 2363 }; 2364 2365 /** 2366 * DMUB rb command definition for commands passed over indirect buffer 2367 */ 2368 struct dmub_rb_cmd_ib { 2369 struct dmub_cmd_header header; 2370 struct dmub_ib_data ib_data; 2371 }; 2372 2373 /** 2374 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2375 */ 2376 enum dmub_cmd_idle_opt_type { 2377 /** 2378 * DCN hardware restore. 2379 */ 2380 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2381 2382 /** 2383 * DCN hardware save. 2384 */ 2385 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2386 2387 /** 2388 * DCN hardware notify idle. 2389 */ 2390 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2391 2392 /** 2393 * DCN hardware notify power state. 2394 */ 2395 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2396 2397 /** 2398 * DCN notify to release HW. 2399 */ 2400 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2401 }; 2402 2403 /** 2404 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2405 */ 2406 struct dmub_rb_cmd_idle_opt_dcn_restore { 2407 struct dmub_cmd_header header; /**< header */ 2408 }; 2409 2410 /** 2411 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2412 */ 2413 struct dmub_dcn_notify_idle_cntl_data { 2414 uint8_t driver_idle; 2415 uint8_t skip_otg_disable; 2416 uint8_t reserved[58]; 2417 }; 2418 2419 /** 2420 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2421 */ 2422 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2423 struct dmub_cmd_header header; /**< header */ 2424 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2425 }; 2426 2427 /** 2428 * enum dmub_idle_opt_dc_power_state - DC power states. 2429 */ 2430 enum dmub_idle_opt_dc_power_state { 2431 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2432 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2433 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2434 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2435 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2436 }; 2437 2438 /** 2439 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2440 */ 2441 struct dmub_idle_opt_set_dc_power_state_data { 2442 uint8_t power_state; /**< power state */ 2443 uint8_t pad[3]; /**< padding */ 2444 }; 2445 2446 /** 2447 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2448 */ 2449 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2450 struct dmub_cmd_header header; /**< header */ 2451 struct dmub_idle_opt_set_dc_power_state_data data; 2452 }; 2453 2454 /** 2455 * struct dmub_clocks - Clock update notification. 2456 */ 2457 struct dmub_clocks { 2458 uint32_t dispclk_khz; /**< dispclk kHz */ 2459 uint32_t dppclk_khz; /**< dppclk kHz */ 2460 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2461 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2462 }; 2463 2464 /** 2465 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2466 */ 2467 enum dmub_cmd_clk_mgr_type { 2468 /** 2469 * Notify DMCUB of clock update. 2470 */ 2471 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2472 }; 2473 2474 /** 2475 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2476 */ 2477 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2478 struct dmub_cmd_header header; /**< header */ 2479 struct dmub_clocks clocks; /**< clock data */ 2480 }; 2481 2482 /** 2483 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2484 */ 2485 struct dmub_cmd_digx_encoder_control_data { 2486 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2487 }; 2488 2489 /** 2490 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2491 */ 2492 struct dmub_rb_cmd_digx_encoder_control { 2493 struct dmub_cmd_header header; /**< header */ 2494 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2495 }; 2496 2497 /** 2498 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2499 */ 2500 struct dmub_cmd_set_pixel_clock_data { 2501 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2502 }; 2503 2504 /** 2505 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2506 */ 2507 struct dmub_rb_cmd_set_pixel_clock { 2508 struct dmub_cmd_header header; /**< header */ 2509 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2510 }; 2511 2512 /** 2513 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2514 */ 2515 struct dmub_cmd_enable_disp_power_gating_data { 2516 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2517 }; 2518 2519 /** 2520 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2521 */ 2522 struct dmub_rb_cmd_enable_disp_power_gating { 2523 struct dmub_cmd_header header; /**< header */ 2524 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2525 }; 2526 2527 /** 2528 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2529 */ 2530 struct dmub_dig_transmitter_control_data_v1_7 { 2531 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2532 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2533 union { 2534 uint8_t digmode; /**< enum atom_encode_mode_def */ 2535 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2536 } mode_laneset; 2537 uint8_t lanenum; /**< Number of lanes */ 2538 union { 2539 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2540 } symclk_units; 2541 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2542 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2543 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2544 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2545 uint8_t reserved1; /**< For future use */ 2546 uint8_t skip_phy_ssc_reduction; 2547 uint8_t reserved2[2]; /**< For future use */ 2548 uint32_t reserved3[11]; /**< For future use */ 2549 }; 2550 2551 /** 2552 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2553 */ 2554 union dmub_cmd_dig1_transmitter_control_data { 2555 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2556 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2557 }; 2558 2559 /** 2560 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2561 */ 2562 struct dmub_rb_cmd_dig1_transmitter_control { 2563 struct dmub_cmd_header header; /**< header */ 2564 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2565 }; 2566 2567 /** 2568 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2569 */ 2570 struct dmub_rb_cmd_domain_control_data { 2571 uint8_t inst : 6; /**< DOMAIN instance to control */ 2572 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2573 uint8_t reserved[3]; /**< Reserved for future use */ 2574 }; 2575 2576 /** 2577 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2578 */ 2579 struct dmub_rb_cmd_domain_control { 2580 struct dmub_cmd_header header; /**< header */ 2581 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2582 }; 2583 2584 /** 2585 * DPIA tunnel command parameters. 2586 */ 2587 struct dmub_cmd_dig_dpia_control_data { 2588 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2589 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2590 union { 2591 uint8_t digmode; /** enum atom_encode_mode_def */ 2592 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2593 } mode_laneset; 2594 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2595 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2596 uint8_t hpdsel; /** =0: HPD is not assigned */ 2597 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2598 uint8_t dpia_id; /** Index of DPIA */ 2599 uint8_t fec_rdy : 1; 2600 uint8_t reserved : 7; 2601 uint32_t reserved1; 2602 }; 2603 2604 /** 2605 * DMUB command for DPIA tunnel control. 2606 */ 2607 struct dmub_rb_cmd_dig1_dpia_control { 2608 struct dmub_cmd_header header; 2609 struct dmub_cmd_dig_dpia_control_data dpia_control; 2610 }; 2611 2612 /** 2613 * SET_CONFIG Command Payload (deprecated) 2614 */ 2615 struct set_config_cmd_payload { 2616 uint8_t msg_type; /* set config message type */ 2617 uint8_t msg_data; /* set config message data */ 2618 }; 2619 2620 /** 2621 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2622 */ 2623 struct dmub_cmd_set_config_control_data { 2624 struct set_config_cmd_payload cmd_pkt; 2625 uint8_t instance; /* DPIA instance */ 2626 uint8_t immed_status; /* Immediate status returned in case of error */ 2627 }; 2628 2629 /** 2630 * SET_CONFIG Request Command Payload 2631 */ 2632 struct set_config_request_cmd_payload { 2633 uint8_t instance; /* DPIA instance */ 2634 uint8_t immed_status; /* Immediate status returned in case of error */ 2635 uint8_t msg_type; /* set config message type */ 2636 uint8_t reserved; 2637 uint32_t msg_data; /* set config message data */ 2638 }; 2639 2640 /** 2641 * DMUB command structure for SET_CONFIG command. 2642 */ 2643 struct dmub_rb_cmd_set_config_access { 2644 struct dmub_cmd_header header; /* header */ 2645 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2646 }; 2647 2648 /** 2649 * DMUB command structure for SET_CONFIG request command. 2650 */ 2651 struct dmub_rb_cmd_set_config_request { 2652 struct dmub_cmd_header header; /* header */ 2653 struct set_config_request_cmd_payload payload; /* set config request payload */ 2654 }; 2655 2656 /** 2657 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2658 */ 2659 struct dmub_cmd_mst_alloc_slots_control_data { 2660 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2661 uint8_t instance; /* DPIA instance */ 2662 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2663 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2664 }; 2665 2666 /** 2667 * DMUB command structure for SET_ command. 2668 */ 2669 struct dmub_rb_cmd_set_mst_alloc_slots { 2670 struct dmub_cmd_header header; /* header */ 2671 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2672 }; 2673 2674 /** 2675 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2676 */ 2677 struct dmub_cmd_tps_notification_data { 2678 uint8_t instance; /* DPIA instance */ 2679 uint8_t tps; /* requested training pattern */ 2680 uint8_t reserved1; 2681 uint8_t reserved2; 2682 }; 2683 2684 /** 2685 * DMUB command structure for SET_TPS_NOTIFICATION command. 2686 */ 2687 struct dmub_rb_cmd_set_tps_notification { 2688 struct dmub_cmd_header header; /* header */ 2689 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2690 }; 2691 2692 /** 2693 * DMUB command structure for DPIA HPD int enable control. 2694 */ 2695 struct dmub_rb_cmd_dpia_hpd_int_enable { 2696 struct dmub_cmd_header header; /* header */ 2697 uint32_t enable; /* dpia hpd interrupt enable */ 2698 }; 2699 2700 /** 2701 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2702 */ 2703 struct dmub_rb_cmd_dpphy_init { 2704 struct dmub_cmd_header header; /**< header */ 2705 uint8_t reserved[60]; /**< reserved bits */ 2706 }; 2707 2708 /** 2709 * enum dp_aux_request_action - DP AUX request command listing. 2710 * 2711 * 4 AUX request command bits are shifted to high nibble. 2712 */ 2713 enum dp_aux_request_action { 2714 /** I2C-over-AUX write request */ 2715 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2716 /** I2C-over-AUX read request */ 2717 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2718 /** I2C-over-AUX write status request */ 2719 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2720 /** I2C-over-AUX write request with MOT=1 */ 2721 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2722 /** I2C-over-AUX read request with MOT=1 */ 2723 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2724 /** I2C-over-AUX write status request with MOT=1 */ 2725 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2726 /** Native AUX write request */ 2727 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2728 /** Native AUX read request */ 2729 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2730 }; 2731 2732 /** 2733 * enum aux_return_code_type - DP AUX process return code listing. 2734 */ 2735 enum aux_return_code_type { 2736 /** AUX process succeeded */ 2737 AUX_RET_SUCCESS = 0, 2738 /** AUX process failed with unknown reason */ 2739 AUX_RET_ERROR_UNKNOWN, 2740 /** AUX process completed with invalid reply */ 2741 AUX_RET_ERROR_INVALID_REPLY, 2742 /** AUX process timed out */ 2743 AUX_RET_ERROR_TIMEOUT, 2744 /** HPD was low during AUX process */ 2745 AUX_RET_ERROR_HPD_DISCON, 2746 /** Failed to acquire AUX engine */ 2747 AUX_RET_ERROR_ENGINE_ACQUIRE, 2748 /** AUX request not supported */ 2749 AUX_RET_ERROR_INVALID_OPERATION, 2750 /** AUX process not available */ 2751 AUX_RET_ERROR_PROTOCOL_ERROR, 2752 }; 2753 2754 /** 2755 * enum aux_channel_type - DP AUX channel type listing. 2756 */ 2757 enum aux_channel_type { 2758 /** AUX thru Legacy DP AUX */ 2759 AUX_CHANNEL_LEGACY_DDC, 2760 /** AUX thru DPIA DP tunneling */ 2761 AUX_CHANNEL_DPIA 2762 }; 2763 2764 /** 2765 * struct aux_transaction_parameters - DP AUX request transaction data 2766 */ 2767 struct aux_transaction_parameters { 2768 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2769 uint8_t action; /**< enum dp_aux_request_action */ 2770 uint8_t length; /**< DP AUX request data length */ 2771 uint8_t reserved; /**< For future use */ 2772 uint32_t address; /**< DP AUX address */ 2773 uint8_t data[16]; /**< DP AUX write data */ 2774 }; 2775 2776 /** 2777 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2778 */ 2779 struct dmub_cmd_dp_aux_control_data { 2780 uint8_t instance; /**< AUX instance or DPIA instance */ 2781 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2782 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2783 uint8_t reserved0; /**< For future use */ 2784 uint16_t timeout; /**< timeout time in us */ 2785 uint16_t reserved1; /**< For future use */ 2786 enum aux_channel_type type; /**< enum aux_channel_type */ 2787 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2788 }; 2789 2790 /** 2791 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2792 */ 2793 struct dmub_rb_cmd_dp_aux_access { 2794 /** 2795 * Command header. 2796 */ 2797 struct dmub_cmd_header header; 2798 /** 2799 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2800 */ 2801 struct dmub_cmd_dp_aux_control_data aux_control; 2802 }; 2803 2804 /** 2805 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2806 */ 2807 struct dmub_rb_cmd_outbox1_enable { 2808 /** 2809 * Command header. 2810 */ 2811 struct dmub_cmd_header header; 2812 /** 2813 * enable: 0x0 -> disable outbox1 notification (default value) 2814 * 0x1 -> enable outbox1 notification 2815 */ 2816 uint32_t enable; 2817 }; 2818 2819 /* DP AUX Reply command - OutBox Cmd */ 2820 /** 2821 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2822 */ 2823 struct aux_reply_data { 2824 /** 2825 * Aux cmd 2826 */ 2827 uint8_t command; 2828 /** 2829 * Aux reply data length (max: 16 bytes) 2830 */ 2831 uint8_t length; 2832 /** 2833 * Alignment only 2834 */ 2835 uint8_t pad[2]; 2836 /** 2837 * Aux reply data 2838 */ 2839 uint8_t data[16]; 2840 }; 2841 2842 /** 2843 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2844 */ 2845 struct aux_reply_control_data { 2846 /** 2847 * Reserved for future use 2848 */ 2849 uint32_t handle; 2850 /** 2851 * Aux Instance 2852 */ 2853 uint8_t instance; 2854 /** 2855 * Aux transaction result: definition in enum aux_return_code_type 2856 */ 2857 uint8_t result; 2858 /** 2859 * Alignment only 2860 */ 2861 uint16_t pad; 2862 }; 2863 2864 /** 2865 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2866 */ 2867 struct dmub_rb_cmd_dp_aux_reply { 2868 /** 2869 * Command header. 2870 */ 2871 struct dmub_cmd_header header; 2872 /** 2873 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2874 */ 2875 struct aux_reply_control_data control; 2876 /** 2877 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2878 */ 2879 struct aux_reply_data reply_data; 2880 }; 2881 2882 /* DP HPD Notify command - OutBox Cmd */ 2883 /** 2884 * DP HPD Type 2885 */ 2886 enum dp_hpd_type { 2887 /** 2888 * Normal DP HPD 2889 */ 2890 DP_HPD = 0, 2891 /** 2892 * DP HPD short pulse 2893 */ 2894 DP_IRQ = 1, 2895 /** 2896 * Failure to acquire DP HPD state 2897 */ 2898 DP_NONE_HPD = 2 2899 }; 2900 2901 /** 2902 * DP HPD Status 2903 */ 2904 enum dp_hpd_status { 2905 /** 2906 * DP_HPD status low 2907 */ 2908 DP_HPD_UNPLUG = 0, 2909 /** 2910 * DP_HPD status high 2911 */ 2912 DP_HPD_PLUG 2913 }; 2914 2915 /** 2916 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2917 */ 2918 struct dp_hpd_data { 2919 /** 2920 * DP HPD instance 2921 */ 2922 uint8_t instance; 2923 /** 2924 * HPD type 2925 */ 2926 uint8_t hpd_type; 2927 /** 2928 * HPD status: only for type: DP_HPD to indicate status 2929 */ 2930 uint8_t hpd_status; 2931 /** 2932 * Alignment only 2933 */ 2934 uint8_t pad; 2935 }; 2936 2937 /** 2938 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2939 */ 2940 struct dmub_rb_cmd_dp_hpd_notify { 2941 /** 2942 * Command header. 2943 */ 2944 struct dmub_cmd_header header; 2945 /** 2946 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2947 */ 2948 struct dp_hpd_data hpd_data; 2949 }; 2950 2951 /** 2952 * Definition of a SET_CONFIG reply from DPOA. 2953 */ 2954 enum set_config_status { 2955 SET_CONFIG_PENDING = 0, 2956 SET_CONFIG_ACK_RECEIVED, 2957 SET_CONFIG_RX_TIMEOUT, 2958 SET_CONFIG_UNKNOWN_ERROR, 2959 }; 2960 2961 /** 2962 * Definition of a set_config reply 2963 */ 2964 struct set_config_reply_control_data { 2965 uint8_t instance; /* DPIA Instance */ 2966 uint8_t status; /* Set Config reply */ 2967 uint16_t pad; /* Alignment */ 2968 }; 2969 2970 /** 2971 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2972 */ 2973 struct dmub_rb_cmd_dp_set_config_reply { 2974 struct dmub_cmd_header header; 2975 struct set_config_reply_control_data set_config_reply_control; 2976 }; 2977 2978 /** 2979 * Definition of a DPIA notification header 2980 */ 2981 struct dpia_notification_header { 2982 uint8_t instance; /**< DPIA Instance */ 2983 uint8_t reserved[3]; 2984 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2985 }; 2986 2987 /** 2988 * Definition of the common data struct of DPIA notification 2989 */ 2990 struct dpia_notification_common { 2991 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2992 - sizeof(struct dpia_notification_header)]; 2993 }; 2994 2995 /** 2996 * Definition of a DPIA notification data 2997 */ 2998 struct dpia_bw_allocation_notify_data { 2999 union { 3000 struct { 3001 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3002 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3003 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3004 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3005 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3006 uint16_t reserved: 11; /**< Reserved */ 3007 } bits; 3008 3009 uint16_t flags; 3010 }; 3011 3012 uint8_t cm_id; /**< CM ID */ 3013 uint8_t group_id; /**< Group ID */ 3014 uint8_t granularity; /**< BW Allocation Granularity */ 3015 uint8_t estimated_bw; /**< Estimated_BW */ 3016 uint8_t allocated_bw; /**< Allocated_BW */ 3017 uint8_t reserved; 3018 }; 3019 3020 /** 3021 * union dpia_notify_data_type - DPIA Notification in Outbox command 3022 */ 3023 union dpia_notification_data { 3024 /** 3025 * DPIA Notification for common data struct 3026 */ 3027 struct dpia_notification_common common_data; 3028 3029 /** 3030 * DPIA Notification for DP BW Allocation support 3031 */ 3032 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3033 }; 3034 3035 /** 3036 * Definition of a DPIA notification payload 3037 */ 3038 struct dpia_notification_payload { 3039 struct dpia_notification_header header; 3040 union dpia_notification_data data; /**< DPIA notification payload data */ 3041 }; 3042 3043 /** 3044 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3045 */ 3046 struct dmub_rb_cmd_dpia_notification { 3047 struct dmub_cmd_header header; /**< DPIA notification header */ 3048 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3049 }; 3050 3051 /** 3052 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3053 */ 3054 struct dmub_cmd_hpd_state_query_data { 3055 uint8_t instance; /**< HPD instance or DPIA instance */ 3056 uint8_t result; /**< For returning HPD state */ 3057 uint16_t pad; /** < Alignment */ 3058 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3059 enum aux_return_code_type status; /**< for returning the status of command */ 3060 }; 3061 3062 /** 3063 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3064 */ 3065 struct dmub_rb_cmd_query_hpd_state { 3066 /** 3067 * Command header. 3068 */ 3069 struct dmub_cmd_header header; 3070 /** 3071 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3072 */ 3073 struct dmub_cmd_hpd_state_query_data data; 3074 }; 3075 3076 /** 3077 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3078 */ 3079 struct dmub_rb_cmd_hpd_sense_notify_data { 3080 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3081 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3082 }; 3083 3084 /** 3085 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3086 */ 3087 struct dmub_rb_cmd_hpd_sense_notify { 3088 struct dmub_cmd_header header; /**< header */ 3089 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3090 }; 3091 3092 /* 3093 * Command IDs should be treated as stable ABI. 3094 * Do not reuse or modify IDs. 3095 */ 3096 3097 /** 3098 * PSR command sub-types. 3099 */ 3100 enum dmub_cmd_psr_type { 3101 /** 3102 * Set PSR version support. 3103 */ 3104 DMUB_CMD__PSR_SET_VERSION = 0, 3105 /** 3106 * Copy driver-calculated parameters to PSR state. 3107 */ 3108 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3109 /** 3110 * Enable PSR. 3111 */ 3112 DMUB_CMD__PSR_ENABLE = 2, 3113 3114 /** 3115 * Disable PSR. 3116 */ 3117 DMUB_CMD__PSR_DISABLE = 3, 3118 3119 /** 3120 * Set PSR level. 3121 * PSR level is a 16-bit value dicated by driver that 3122 * will enable/disable different functionality. 3123 */ 3124 DMUB_CMD__PSR_SET_LEVEL = 4, 3125 3126 /** 3127 * Forces PSR enabled until an explicit PSR disable call. 3128 */ 3129 DMUB_CMD__PSR_FORCE_STATIC = 5, 3130 /** 3131 * Set vtotal in psr active for FreeSync PSR. 3132 */ 3133 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3134 /** 3135 * Set PSR power option 3136 */ 3137 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3138 }; 3139 3140 /** 3141 * Different PSR residency modes. 3142 * Different modes change the definition of PSR residency. 3143 */ 3144 enum psr_residency_mode { 3145 PSR_RESIDENCY_MODE_PHY = 0, 3146 PSR_RESIDENCY_MODE_ALPM, 3147 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3148 /* Do not add below. */ 3149 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3150 }; 3151 3152 enum dmub_cmd_fams_type { 3153 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3154 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3155 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3156 /** 3157 * For SubVP set manual trigger in FW because it 3158 * triggers DRR_UPDATE_PENDING which SubVP relies 3159 * on (for any SubVP cases that use a DRR display) 3160 */ 3161 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3162 DMUB_CMD__FAMS2_CONFIG = 4, 3163 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3164 DMUB_CMD__FAMS2_FLIP = 6, 3165 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3166 }; 3167 3168 /** 3169 * PSR versions. 3170 */ 3171 enum psr_version { 3172 /** 3173 * PSR version 1. 3174 */ 3175 PSR_VERSION_1 = 0, 3176 /** 3177 * Freesync PSR SU. 3178 */ 3179 PSR_VERSION_SU_1 = 1, 3180 /** 3181 * PSR not supported. 3182 */ 3183 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3184 }; 3185 3186 /** 3187 * PHY Link rate for DP. 3188 */ 3189 enum phy_link_rate { 3190 /** 3191 * not supported. 3192 */ 3193 PHY_RATE_UNKNOWN = 0, 3194 /** 3195 * Rate_1 (RBR) - 1.62 Gbps/Lane 3196 */ 3197 PHY_RATE_162 = 1, 3198 /** 3199 * Rate_2 - 2.16 Gbps/Lane 3200 */ 3201 PHY_RATE_216 = 2, 3202 /** 3203 * Rate_3 - 2.43 Gbps/Lane 3204 */ 3205 PHY_RATE_243 = 3, 3206 /** 3207 * Rate_4 (HBR) - 2.70 Gbps/Lane 3208 */ 3209 PHY_RATE_270 = 4, 3210 /** 3211 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3212 */ 3213 PHY_RATE_324 = 5, 3214 /** 3215 * Rate_6 - 4.32 Gbps/Lane 3216 */ 3217 PHY_RATE_432 = 6, 3218 /** 3219 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3220 */ 3221 PHY_RATE_540 = 7, 3222 /** 3223 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3224 */ 3225 PHY_RATE_810 = 8, 3226 /** 3227 * UHBR10 - 10.0 Gbps/Lane 3228 */ 3229 PHY_RATE_1000 = 9, 3230 /** 3231 * UHBR13.5 - 13.5 Gbps/Lane 3232 */ 3233 PHY_RATE_1350 = 10, 3234 /** 3235 * UHBR10 - 20.0 Gbps/Lane 3236 */ 3237 PHY_RATE_2000 = 11, 3238 3239 PHY_RATE_675 = 12, 3240 /** 3241 * Rate 12 - 6.75 Gbps/Lane 3242 */ 3243 }; 3244 3245 /** 3246 * enum dmub_phy_fsm_state - PHY FSM states. 3247 * PHY FSM state to transit to during PSR enable/disable. 3248 */ 3249 enum dmub_phy_fsm_state { 3250 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3251 DMUB_PHY_FSM_RESET, 3252 DMUB_PHY_FSM_RESET_RELEASED, 3253 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3254 DMUB_PHY_FSM_INITIALIZED, 3255 DMUB_PHY_FSM_CALIBRATED, 3256 DMUB_PHY_FSM_CALIBRATED_LP, 3257 DMUB_PHY_FSM_CALIBRATED_PG, 3258 DMUB_PHY_FSM_POWER_DOWN, 3259 DMUB_PHY_FSM_PLL_EN, 3260 DMUB_PHY_FSM_TX_EN, 3261 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3262 DMUB_PHY_FSM_FAST_LP, 3263 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3264 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3265 DMUB_PHY_FSM_P2_PLL_OFF, 3266 DMUB_PHY_FSM_P2_PLL_ON, 3267 }; 3268 3269 /** 3270 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3271 */ 3272 struct dmub_cmd_psr_copy_settings_data { 3273 /** 3274 * Flags that can be set by driver to change some PSR behaviour. 3275 */ 3276 union dmub_psr_debug_flags debug; 3277 /** 3278 * 16-bit value dicated by driver that will enable/disable different functionality. 3279 */ 3280 uint16_t psr_level; 3281 /** 3282 * DPP HW instance. 3283 */ 3284 uint8_t dpp_inst; 3285 /** 3286 * MPCC HW instance. 3287 * Not used in dmub fw, 3288 * dmub fw will get active opp by reading odm registers. 3289 */ 3290 uint8_t mpcc_inst; 3291 /** 3292 * OPP HW instance. 3293 * Not used in dmub fw, 3294 * dmub fw will get active opp by reading odm registers. 3295 */ 3296 uint8_t opp_inst; 3297 /** 3298 * OTG HW instance. 3299 */ 3300 uint8_t otg_inst; 3301 /** 3302 * DIG FE HW instance. 3303 */ 3304 uint8_t digfe_inst; 3305 /** 3306 * DIG BE HW instance. 3307 */ 3308 uint8_t digbe_inst; 3309 /** 3310 * DP PHY HW instance. 3311 */ 3312 uint8_t dpphy_inst; 3313 /** 3314 * AUX HW instance. 3315 */ 3316 uint8_t aux_inst; 3317 /** 3318 * Determines if SMU optimzations are enabled/disabled. 3319 */ 3320 uint8_t smu_optimizations_en; 3321 /** 3322 * Unused. 3323 * TODO: Remove. 3324 */ 3325 uint8_t frame_delay; 3326 /** 3327 * If RFB setup time is greater than the total VBLANK time, 3328 * it is not possible for the sink to capture the video frame 3329 * in the same frame the SDP is sent. In this case, 3330 * the frame capture indication bit should be set and an extra 3331 * static frame should be transmitted to the sink. 3332 */ 3333 uint8_t frame_cap_ind; 3334 /** 3335 * Granularity of Y offset supported by sink. 3336 */ 3337 uint8_t su_y_granularity; 3338 /** 3339 * Indicates whether sink should start capturing 3340 * immediately following active scan line, 3341 * or starting with the 2nd active scan line. 3342 */ 3343 uint8_t line_capture_indication; 3344 /** 3345 * Multi-display optimizations are implemented on certain ASICs. 3346 */ 3347 uint8_t multi_disp_optimizations_en; 3348 /** 3349 * The last possible line SDP may be transmitted without violating 3350 * the RFB setup time or entering the active video frame. 3351 */ 3352 uint16_t init_sdp_deadline; 3353 /** 3354 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3355 */ 3356 uint8_t rate_control_caps ; 3357 /* 3358 * Force PSRSU always doing full frame update 3359 */ 3360 uint8_t force_ffu_mode; 3361 /** 3362 * Length of each horizontal line in us. 3363 */ 3364 uint32_t line_time_in_us; 3365 /** 3366 * FEC enable status in driver 3367 */ 3368 uint8_t fec_enable_status; 3369 /** 3370 * FEC re-enable delay when PSR exit. 3371 * unit is 100us, range form 0~255(0xFF). 3372 */ 3373 uint8_t fec_enable_delay_in100us; 3374 /** 3375 * PSR control version. 3376 */ 3377 uint8_t cmd_version; 3378 /** 3379 * Panel Instance. 3380 * Panel instance to identify which psr_state to use 3381 * Currently the support is only for 0 or 1 3382 */ 3383 uint8_t panel_inst; 3384 /* 3385 * DSC enable status in driver 3386 */ 3387 uint8_t dsc_enable_status; 3388 /* 3389 * Use FSM state for PSR power up/down 3390 */ 3391 uint8_t use_phy_fsm; 3392 /** 3393 * frame delay for frame re-lock 3394 */ 3395 uint8_t relock_delay_frame_cnt; 3396 /** 3397 * esd recovery indicate. 3398 */ 3399 uint8_t esd_recovery; 3400 /** 3401 * DSC Slice height. 3402 */ 3403 uint16_t dsc_slice_height; 3404 /** 3405 * Some panels request main link off before xth vertical line 3406 */ 3407 uint16_t poweroff_before_vertical_line; 3408 /** 3409 * Some panels cannot handle idle pattern during PSR entry. 3410 * To power down phy before disable stream to avoid sending 3411 * idle pattern. 3412 */ 3413 uint8_t power_down_phy_before_disable_stream; 3414 }; 3415 3416 /** 3417 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3418 */ 3419 struct dmub_rb_cmd_psr_copy_settings { 3420 /** 3421 * Command header. 3422 */ 3423 struct dmub_cmd_header header; 3424 /** 3425 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3426 */ 3427 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3428 }; 3429 3430 /** 3431 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3432 */ 3433 struct dmub_cmd_psr_set_level_data { 3434 /** 3435 * 16-bit value dicated by driver that will enable/disable different functionality. 3436 */ 3437 uint16_t psr_level; 3438 /** 3439 * PSR control version. 3440 */ 3441 uint8_t cmd_version; 3442 /** 3443 * Panel Instance. 3444 * Panel instance to identify which psr_state to use 3445 * Currently the support is only for 0 or 1 3446 */ 3447 uint8_t panel_inst; 3448 }; 3449 3450 /** 3451 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3452 */ 3453 struct dmub_rb_cmd_psr_set_level { 3454 /** 3455 * Command header. 3456 */ 3457 struct dmub_cmd_header header; 3458 /** 3459 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3460 */ 3461 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3462 }; 3463 3464 struct dmub_rb_cmd_psr_enable_data { 3465 /** 3466 * PSR control version. 3467 */ 3468 uint8_t cmd_version; 3469 /** 3470 * Panel Instance. 3471 * Panel instance to identify which psr_state to use 3472 * Currently the support is only for 0 or 1 3473 */ 3474 uint8_t panel_inst; 3475 /** 3476 * Phy state to enter. 3477 * Values to use are defined in dmub_phy_fsm_state 3478 */ 3479 uint8_t phy_fsm_state; 3480 /** 3481 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3482 * Set this using enum phy_link_rate. 3483 * This does not support HDMI/DP2 for now. 3484 */ 3485 uint8_t phy_rate; 3486 }; 3487 3488 /** 3489 * Definition of a DMUB_CMD__PSR_ENABLE command. 3490 * PSR enable/disable is controlled using the sub_type. 3491 */ 3492 struct dmub_rb_cmd_psr_enable { 3493 /** 3494 * Command header. 3495 */ 3496 struct dmub_cmd_header header; 3497 3498 struct dmub_rb_cmd_psr_enable_data data; 3499 }; 3500 3501 /** 3502 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3503 */ 3504 struct dmub_cmd_psr_set_version_data { 3505 /** 3506 * PSR version that FW should implement. 3507 */ 3508 enum psr_version version; 3509 /** 3510 * PSR control version. 3511 */ 3512 uint8_t cmd_version; 3513 /** 3514 * Panel Instance. 3515 * Panel instance to identify which psr_state to use 3516 * Currently the support is only for 0 or 1 3517 */ 3518 uint8_t panel_inst; 3519 /** 3520 * Explicit padding to 4 byte boundary. 3521 */ 3522 uint8_t pad[2]; 3523 }; 3524 3525 /** 3526 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3527 */ 3528 struct dmub_rb_cmd_psr_set_version { 3529 /** 3530 * Command header. 3531 */ 3532 struct dmub_cmd_header header; 3533 /** 3534 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3535 */ 3536 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3537 }; 3538 3539 struct dmub_cmd_psr_force_static_data { 3540 /** 3541 * PSR control version. 3542 */ 3543 uint8_t cmd_version; 3544 /** 3545 * Panel Instance. 3546 * Panel instance to identify which psr_state to use 3547 * Currently the support is only for 0 or 1 3548 */ 3549 uint8_t panel_inst; 3550 /** 3551 * Explicit padding to 4 byte boundary. 3552 */ 3553 uint8_t pad[2]; 3554 }; 3555 3556 /** 3557 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3558 */ 3559 struct dmub_rb_cmd_psr_force_static { 3560 /** 3561 * Command header. 3562 */ 3563 struct dmub_cmd_header header; 3564 /** 3565 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3566 */ 3567 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3568 }; 3569 3570 /** 3571 * PSR SU debug flags. 3572 */ 3573 union dmub_psr_su_debug_flags { 3574 /** 3575 * PSR SU debug flags. 3576 */ 3577 struct { 3578 /** 3579 * Update dirty rect in SW only. 3580 */ 3581 uint8_t update_dirty_rect_only : 1; 3582 /** 3583 * Reset the cursor/plane state before processing the call. 3584 */ 3585 uint8_t reset_state : 1; 3586 } bitfields; 3587 3588 /** 3589 * Union for debug flags. 3590 */ 3591 uint32_t u32All; 3592 }; 3593 3594 /** 3595 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3596 * This triggers a selective update for PSR SU. 3597 */ 3598 struct dmub_cmd_update_dirty_rect_data { 3599 /** 3600 * Dirty rects from OS. 3601 */ 3602 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3603 /** 3604 * PSR SU debug flags. 3605 */ 3606 union dmub_psr_su_debug_flags debug_flags; 3607 /** 3608 * OTG HW instance. 3609 */ 3610 uint8_t pipe_idx; 3611 /** 3612 * Number of dirty rects. 3613 */ 3614 uint8_t dirty_rect_count; 3615 /** 3616 * PSR control version. 3617 */ 3618 uint8_t cmd_version; 3619 /** 3620 * Panel Instance. 3621 * Panel instance to identify which psr_state to use 3622 * Currently the support is only for 0 or 1 3623 */ 3624 uint8_t panel_inst; 3625 }; 3626 3627 /** 3628 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3629 */ 3630 struct dmub_rb_cmd_update_dirty_rect { 3631 /** 3632 * Command header. 3633 */ 3634 struct dmub_cmd_header header; 3635 /** 3636 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3637 */ 3638 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3639 }; 3640 3641 /** 3642 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3643 */ 3644 union dmub_reg_cursor_control_cfg { 3645 struct { 3646 uint32_t cur_enable: 1; 3647 uint32_t reser0: 3; 3648 uint32_t cur_2x_magnify: 1; 3649 uint32_t reser1: 3; 3650 uint32_t mode: 3; 3651 uint32_t reser2: 5; 3652 uint32_t pitch: 2; 3653 uint32_t reser3: 6; 3654 uint32_t line_per_chunk: 5; 3655 uint32_t reser4: 3; 3656 } bits; 3657 uint32_t raw; 3658 }; 3659 struct dmub_cursor_position_cache_hubp { 3660 union dmub_reg_cursor_control_cfg cur_ctl; 3661 union dmub_reg_position_cfg { 3662 struct { 3663 uint32_t cur_x_pos: 16; 3664 uint32_t cur_y_pos: 16; 3665 } bits; 3666 uint32_t raw; 3667 } position; 3668 union dmub_reg_hot_spot_cfg { 3669 struct { 3670 uint32_t hot_x: 16; 3671 uint32_t hot_y: 16; 3672 } bits; 3673 uint32_t raw; 3674 } hot_spot; 3675 union dmub_reg_dst_offset_cfg { 3676 struct { 3677 uint32_t dst_x_offset: 13; 3678 uint32_t reserved: 19; 3679 } bits; 3680 uint32_t raw; 3681 } dst_offset; 3682 }; 3683 3684 union dmub_reg_cur0_control_cfg { 3685 struct { 3686 uint32_t cur0_enable: 1; 3687 uint32_t expansion_mode: 1; 3688 uint32_t reser0: 1; 3689 uint32_t cur0_rom_en: 1; 3690 uint32_t mode: 3; 3691 uint32_t reserved: 25; 3692 } bits; 3693 uint32_t raw; 3694 }; 3695 struct dmub_cursor_position_cache_dpp { 3696 union dmub_reg_cur0_control_cfg cur0_ctl; 3697 }; 3698 struct dmub_cursor_position_cfg { 3699 struct dmub_cursor_position_cache_hubp pHubp; 3700 struct dmub_cursor_position_cache_dpp pDpp; 3701 uint8_t pipe_idx; 3702 /* 3703 * Padding is required. To be 4 Bytes Aligned. 3704 */ 3705 uint8_t padding[3]; 3706 }; 3707 3708 struct dmub_cursor_attribute_cache_hubp { 3709 uint32_t SURFACE_ADDR_HIGH; 3710 uint32_t SURFACE_ADDR; 3711 union dmub_reg_cursor_control_cfg cur_ctl; 3712 union dmub_reg_cursor_size_cfg { 3713 struct { 3714 uint32_t width: 16; 3715 uint32_t height: 16; 3716 } bits; 3717 uint32_t raw; 3718 } size; 3719 union dmub_reg_cursor_settings_cfg { 3720 struct { 3721 uint32_t dst_y_offset: 8; 3722 uint32_t chunk_hdl_adjust: 2; 3723 uint32_t reserved: 22; 3724 } bits; 3725 uint32_t raw; 3726 } settings; 3727 }; 3728 struct dmub_cursor_attribute_cache_dpp { 3729 union dmub_reg_cur0_control_cfg cur0_ctl; 3730 }; 3731 struct dmub_cursor_attributes_cfg { 3732 struct dmub_cursor_attribute_cache_hubp aHubp; 3733 struct dmub_cursor_attribute_cache_dpp aDpp; 3734 }; 3735 3736 struct dmub_cmd_update_cursor_payload0 { 3737 /** 3738 * Cursor dirty rects. 3739 */ 3740 struct dmub_rect cursor_rect; 3741 /** 3742 * PSR SU debug flags. 3743 */ 3744 union dmub_psr_su_debug_flags debug_flags; 3745 /** 3746 * Cursor enable/disable. 3747 */ 3748 uint8_t enable; 3749 /** 3750 * OTG HW instance. 3751 */ 3752 uint8_t pipe_idx; 3753 /** 3754 * PSR control version. 3755 */ 3756 uint8_t cmd_version; 3757 /** 3758 * Panel Instance. 3759 * Panel instance to identify which psr_state to use 3760 * Currently the support is only for 0 or 1 3761 */ 3762 uint8_t panel_inst; 3763 /** 3764 * Cursor Position Register. 3765 * Registers contains Hubp & Dpp modules 3766 */ 3767 struct dmub_cursor_position_cfg position_cfg; 3768 }; 3769 3770 struct dmub_cmd_update_cursor_payload1 { 3771 struct dmub_cursor_attributes_cfg attribute_cfg; 3772 }; 3773 3774 union dmub_cmd_update_cursor_info_data { 3775 struct dmub_cmd_update_cursor_payload0 payload0; 3776 struct dmub_cmd_update_cursor_payload1 payload1; 3777 }; 3778 /** 3779 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3780 */ 3781 struct dmub_rb_cmd_update_cursor_info { 3782 /** 3783 * Command header. 3784 */ 3785 struct dmub_cmd_header header; 3786 /** 3787 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3788 */ 3789 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3790 }; 3791 3792 /** 3793 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3794 */ 3795 struct dmub_cmd_psr_set_vtotal_data { 3796 /** 3797 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3798 */ 3799 uint16_t psr_vtotal_idle; 3800 /** 3801 * PSR control version. 3802 */ 3803 uint8_t cmd_version; 3804 /** 3805 * Panel Instance. 3806 * Panel instance to identify which psr_state to use 3807 * Currently the support is only for 0 or 1 3808 */ 3809 uint8_t panel_inst; 3810 /* 3811 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3812 */ 3813 uint16_t psr_vtotal_su; 3814 /** 3815 * Explicit padding to 4 byte boundary. 3816 */ 3817 uint8_t pad2[2]; 3818 }; 3819 3820 /** 3821 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3822 */ 3823 struct dmub_rb_cmd_psr_set_vtotal { 3824 /** 3825 * Command header. 3826 */ 3827 struct dmub_cmd_header header; 3828 /** 3829 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3830 */ 3831 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3832 }; 3833 3834 /** 3835 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3836 */ 3837 struct dmub_cmd_psr_set_power_opt_data { 3838 /** 3839 * PSR control version. 3840 */ 3841 uint8_t cmd_version; 3842 /** 3843 * Panel Instance. 3844 * Panel instance to identify which psr_state to use 3845 * Currently the support is only for 0 or 1 3846 */ 3847 uint8_t panel_inst; 3848 /** 3849 * Explicit padding to 4 byte boundary. 3850 */ 3851 uint8_t pad[2]; 3852 /** 3853 * PSR power option 3854 */ 3855 uint32_t power_opt; 3856 }; 3857 3858 /** 3859 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3860 */ 3861 struct dmub_rb_cmd_psr_set_power_opt { 3862 /** 3863 * Command header. 3864 */ 3865 struct dmub_cmd_header header; 3866 /** 3867 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3868 */ 3869 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3870 }; 3871 3872 enum dmub_alpm_mode { 3873 ALPM_AUXWAKE = 0, 3874 ALPM_AUXLESS = 1, 3875 ALPM_UNSUPPORTED = 2, 3876 }; 3877 3878 /** 3879 * Definition of Replay Residency GPINT command. 3880 * Bit[0] - Residency mode for Revision 0 3881 * Bit[1] - Enable/Disable state 3882 * Bit[2-3] - Revision number 3883 * Bit[4-7] - Residency mode for Revision 1 3884 * Bit[8] - Panel instance 3885 * Bit[9-15] - Reserved 3886 */ 3887 3888 enum pr_residency_mode { 3889 PR_RESIDENCY_MODE_PHY = 0x0, 3890 PR_RESIDENCY_MODE_ALPM, 3891 PR_RESIDENCY_MODE_IPS2, 3892 PR_RESIDENCY_MODE_FRAME_CNT, 3893 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3894 }; 3895 3896 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3897 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3898 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3899 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3900 3901 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3902 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3903 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3904 3905 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3906 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3907 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3908 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3909 3910 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3911 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3912 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3913 3914 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3915 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3916 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3917 3918 /** 3919 * Definition of a replay_state. 3920 */ 3921 enum replay_state { 3922 REPLAY_STATE_0 = 0x0, 3923 REPLAY_STATE_1 = 0x10, 3924 REPLAY_STATE_1A = 0x11, 3925 REPLAY_STATE_2 = 0x20, 3926 REPLAY_STATE_2A = 0x21, 3927 REPLAY_STATE_3 = 0x30, 3928 REPLAY_STATE_3INIT = 0x31, 3929 REPLAY_STATE_4 = 0x40, 3930 REPLAY_STATE_4A = 0x41, 3931 REPLAY_STATE_4B = 0x42, 3932 REPLAY_STATE_4C = 0x43, 3933 REPLAY_STATE_4D = 0x44, 3934 REPLAY_STATE_4E = 0x45, 3935 REPLAY_STATE_4B_LOCKED = 0x4A, 3936 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3937 REPLAY_STATE_5 = 0x50, 3938 REPLAY_STATE_5A = 0x51, 3939 REPLAY_STATE_5B = 0x52, 3940 REPLAY_STATE_5A_LOCKED = 0x5A, 3941 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3942 REPLAY_STATE_6 = 0x60, 3943 REPLAY_STATE_6A = 0x61, 3944 REPLAY_STATE_6B = 0x62, 3945 REPLAY_STATE_INVALID = 0xFF, 3946 }; 3947 3948 /** 3949 * Replay command sub-types. 3950 */ 3951 enum dmub_cmd_replay_type { 3952 /** 3953 * Copy driver-calculated parameters to REPLAY state. 3954 */ 3955 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3956 /** 3957 * Enable REPLAY. 3958 */ 3959 DMUB_CMD__REPLAY_ENABLE = 1, 3960 /** 3961 * Set Replay power option. 3962 */ 3963 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3964 /** 3965 * Set coasting vtotal. 3966 */ 3967 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3968 /** 3969 * Set power opt and coasting vtotal. 3970 */ 3971 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3972 /** 3973 * Set disabled iiming sync. 3974 */ 3975 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3976 /** 3977 * Set Residency Frameupdate Timer. 3978 */ 3979 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3980 /** 3981 * Set pseudo vtotal 3982 */ 3983 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3984 /** 3985 * Set adaptive sync sdp enabled 3986 */ 3987 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3988 /** 3989 * Set Replay General command. 3990 */ 3991 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3992 }; 3993 3994 /** 3995 * Replay general command sub-types. 3996 */ 3997 enum dmub_cmd_replay_general_subtype { 3998 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3999 /** 4000 * TODO: For backward compatible, allow new command only. 4001 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4002 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4003 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4004 */ 4005 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4006 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4007 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4008 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4009 }; 4010 4011 struct dmub_alpm_auxless_data { 4012 uint16_t lfps_setup_ns; 4013 uint16_t lfps_period_ns; 4014 uint16_t lfps_silence_ns; 4015 uint16_t lfps_t1_t2_override_us; 4016 short lfps_t1_t2_offset_us; 4017 uint8_t lttpr_count; 4018 }; 4019 4020 /** 4021 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4022 */ 4023 struct dmub_cmd_replay_copy_settings_data { 4024 /** 4025 * Flags that can be set by driver to change some replay behaviour. 4026 */ 4027 union replay_debug_flags debug; 4028 4029 /** 4030 * @flags: Flags used to determine feature functionality. 4031 */ 4032 union replay_hw_flags flags; 4033 4034 /** 4035 * DPP HW instance. 4036 */ 4037 uint8_t dpp_inst; 4038 /** 4039 * OTG HW instance. 4040 */ 4041 uint8_t otg_inst; 4042 /** 4043 * DIG FE HW instance. 4044 */ 4045 uint8_t digfe_inst; 4046 /** 4047 * DIG BE HW instance. 4048 */ 4049 uint8_t digbe_inst; 4050 /** 4051 * AUX HW instance. 4052 */ 4053 uint8_t aux_inst; 4054 /** 4055 * Panel Instance. 4056 * Panel isntance to identify which psr_state to use 4057 * Currently the support is only for 0 or 1 4058 */ 4059 uint8_t panel_inst; 4060 /** 4061 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4062 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4063 */ 4064 uint8_t pixel_deviation_per_line; 4065 /** 4066 * @max_deviation_line: The max number of deviation line that can keep the timing 4067 * synchronized between the Source and Sink during Replay normal sleep mode. 4068 */ 4069 uint8_t max_deviation_line; 4070 /** 4071 * Length of each horizontal line in ns. 4072 */ 4073 uint32_t line_time_in_ns; 4074 /** 4075 * PHY instance. 4076 */ 4077 uint8_t dpphy_inst; 4078 /** 4079 * Determines if SMU optimzations are enabled/disabled. 4080 */ 4081 uint8_t smu_optimizations_en; 4082 /** 4083 * Determines if timing sync are enabled/disabled. 4084 */ 4085 uint8_t replay_timing_sync_supported; 4086 /* 4087 * Use FSM state for Replay power up/down 4088 */ 4089 uint8_t use_phy_fsm; 4090 /** 4091 * Use for AUX-less ALPM LFPS wake operation 4092 */ 4093 struct dmub_alpm_auxless_data auxless_alpm_data; 4094 4095 /** 4096 * @pad: Align structure to 4 byte boundary. 4097 */ 4098 uint8_t pad[2]; 4099 }; 4100 4101 /** 4102 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4103 */ 4104 struct dmub_rb_cmd_replay_copy_settings { 4105 /** 4106 * Command header. 4107 */ 4108 struct dmub_cmd_header header; 4109 /** 4110 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4111 */ 4112 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4113 }; 4114 4115 /** 4116 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4117 */ 4118 enum replay_enable { 4119 /** 4120 * Disable REPLAY. 4121 */ 4122 REPLAY_DISABLE = 0, 4123 /** 4124 * Enable REPLAY. 4125 */ 4126 REPLAY_ENABLE = 1, 4127 }; 4128 4129 /** 4130 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4131 */ 4132 struct dmub_rb_cmd_replay_enable_data { 4133 /** 4134 * Replay enable or disable. 4135 */ 4136 uint8_t enable; 4137 /** 4138 * Panel Instance. 4139 * Panel isntance to identify which replay_state to use 4140 * Currently the support is only for 0 or 1 4141 */ 4142 uint8_t panel_inst; 4143 /** 4144 * Phy state to enter. 4145 * Values to use are defined in dmub_phy_fsm_state 4146 */ 4147 uint8_t phy_fsm_state; 4148 /** 4149 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4150 * Set this using enum phy_link_rate. 4151 * This does not support HDMI/DP2 for now. 4152 */ 4153 uint8_t phy_rate; 4154 }; 4155 4156 /** 4157 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4158 * Replay enable/disable is controlled using action in data. 4159 */ 4160 struct dmub_rb_cmd_replay_enable { 4161 /** 4162 * Command header. 4163 */ 4164 struct dmub_cmd_header header; 4165 4166 struct dmub_rb_cmd_replay_enable_data data; 4167 }; 4168 4169 /** 4170 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4171 */ 4172 struct dmub_cmd_replay_set_power_opt_data { 4173 /** 4174 * Panel Instance. 4175 * Panel isntance to identify which replay_state to use 4176 * Currently the support is only for 0 or 1 4177 */ 4178 uint8_t panel_inst; 4179 /** 4180 * Explicit padding to 4 byte boundary. 4181 */ 4182 uint8_t pad[3]; 4183 /** 4184 * REPLAY power option 4185 */ 4186 uint32_t power_opt; 4187 }; 4188 4189 /** 4190 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4191 */ 4192 struct dmub_cmd_replay_set_timing_sync_data { 4193 /** 4194 * Panel Instance. 4195 * Panel isntance to identify which replay_state to use 4196 * Currently the support is only for 0 or 1 4197 */ 4198 uint8_t panel_inst; 4199 /** 4200 * REPLAY set_timing_sync 4201 */ 4202 uint8_t timing_sync_supported; 4203 /** 4204 * Explicit padding to 4 byte boundary. 4205 */ 4206 uint8_t pad[2]; 4207 }; 4208 4209 /** 4210 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4211 */ 4212 struct dmub_cmd_replay_set_pseudo_vtotal { 4213 /** 4214 * Panel Instance. 4215 * Panel isntance to identify which replay_state to use 4216 * Currently the support is only for 0 or 1 4217 */ 4218 uint8_t panel_inst; 4219 /** 4220 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4221 */ 4222 uint16_t vtotal; 4223 /** 4224 * Explicit padding to 4 byte boundary. 4225 */ 4226 uint8_t pad; 4227 }; 4228 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4229 /** 4230 * Panel Instance. 4231 * Panel isntance to identify which replay_state to use 4232 * Currently the support is only for 0 or 1 4233 */ 4234 uint8_t panel_inst; 4235 /** 4236 * enabled: set adaptive sync sdp enabled 4237 */ 4238 uint8_t force_disabled; 4239 4240 uint8_t pad[2]; 4241 }; 4242 struct dmub_cmd_replay_set_general_cmd_data { 4243 /** 4244 * Panel Instance. 4245 * Panel isntance to identify which replay_state to use 4246 * Currently the support is only for 0 or 1 4247 */ 4248 uint8_t panel_inst; 4249 /** 4250 * subtype: replay general cmd sub type 4251 */ 4252 uint8_t subtype; 4253 4254 uint8_t pad[2]; 4255 /** 4256 * config data with param1 and param2 4257 */ 4258 uint32_t param1; 4259 4260 uint32_t param2; 4261 }; 4262 4263 /** 4264 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4265 */ 4266 struct dmub_rb_cmd_replay_set_power_opt { 4267 /** 4268 * Command header. 4269 */ 4270 struct dmub_cmd_header header; 4271 /** 4272 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4273 */ 4274 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4275 }; 4276 4277 /** 4278 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4279 */ 4280 struct dmub_cmd_replay_set_coasting_vtotal_data { 4281 /** 4282 * 16-bit value dicated by driver that indicates the coasting vtotal. 4283 */ 4284 uint16_t coasting_vtotal; 4285 /** 4286 * REPLAY control version. 4287 */ 4288 uint8_t cmd_version; 4289 /** 4290 * Panel Instance. 4291 * Panel isntance to identify which replay_state to use 4292 * Currently the support is only for 0 or 1 4293 */ 4294 uint8_t panel_inst; 4295 /** 4296 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4297 */ 4298 uint16_t coasting_vtotal_high; 4299 /** 4300 * Explicit padding to 4 byte boundary. 4301 */ 4302 uint8_t pad[2]; 4303 }; 4304 4305 /** 4306 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4307 */ 4308 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4309 /** 4310 * Command header. 4311 */ 4312 struct dmub_cmd_header header; 4313 /** 4314 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4315 */ 4316 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4317 }; 4318 4319 /** 4320 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4321 */ 4322 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4323 /** 4324 * Command header. 4325 */ 4326 struct dmub_cmd_header header; 4327 /** 4328 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4329 */ 4330 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4331 /** 4332 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4333 */ 4334 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4335 }; 4336 4337 /** 4338 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4339 */ 4340 struct dmub_rb_cmd_replay_set_timing_sync { 4341 /** 4342 * Command header. 4343 */ 4344 struct dmub_cmd_header header; 4345 /** 4346 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4347 */ 4348 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4349 }; 4350 4351 /** 4352 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4353 */ 4354 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4355 /** 4356 * Command header. 4357 */ 4358 struct dmub_cmd_header header; 4359 /** 4360 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4361 */ 4362 struct dmub_cmd_replay_set_pseudo_vtotal data; 4363 }; 4364 4365 /** 4366 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4367 */ 4368 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4369 /** 4370 * Command header. 4371 */ 4372 struct dmub_cmd_header header; 4373 /** 4374 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4375 */ 4376 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4377 }; 4378 4379 /** 4380 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4381 */ 4382 struct dmub_rb_cmd_replay_set_general_cmd { 4383 /** 4384 * Command header. 4385 */ 4386 struct dmub_cmd_header header; 4387 /** 4388 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4389 */ 4390 struct dmub_cmd_replay_set_general_cmd_data data; 4391 }; 4392 4393 /** 4394 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4395 */ 4396 struct dmub_cmd_replay_frameupdate_timer_data { 4397 /** 4398 * Panel Instance. 4399 * Panel isntance to identify which replay_state to use 4400 * Currently the support is only for 0 or 1 4401 */ 4402 uint8_t panel_inst; 4403 /** 4404 * Replay Frameupdate Timer Enable or not 4405 */ 4406 uint8_t enable; 4407 /** 4408 * REPLAY force reflash frame update number 4409 */ 4410 uint16_t frameupdate_count; 4411 }; 4412 /** 4413 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4414 */ 4415 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4416 /** 4417 * Command header. 4418 */ 4419 struct dmub_cmd_header header; 4420 /** 4421 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4422 */ 4423 struct dmub_cmd_replay_frameupdate_timer_data data; 4424 }; 4425 4426 /** 4427 * Definition union of replay command set 4428 */ 4429 union dmub_replay_cmd_set { 4430 /** 4431 * Panel Instance. 4432 * Panel isntance to identify which replay_state to use 4433 * Currently the support is only for 0 or 1 4434 */ 4435 uint8_t panel_inst; 4436 /** 4437 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4438 */ 4439 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4440 /** 4441 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4442 */ 4443 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4444 /** 4445 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4446 */ 4447 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4448 /** 4449 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4450 */ 4451 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4452 /** 4453 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4454 */ 4455 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4456 }; 4457 4458 /** 4459 * Set of HW components that can be locked. 4460 * 4461 * Note: If updating with more HW components, fields 4462 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4463 */ 4464 union dmub_hw_lock_flags { 4465 /** 4466 * Set of HW components that can be locked. 4467 */ 4468 struct { 4469 /** 4470 * Lock/unlock OTG master update lock. 4471 */ 4472 uint8_t lock_pipe : 1; 4473 /** 4474 * Lock/unlock cursor. 4475 */ 4476 uint8_t lock_cursor : 1; 4477 /** 4478 * Lock/unlock global update lock. 4479 */ 4480 uint8_t lock_dig : 1; 4481 /** 4482 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4483 */ 4484 uint8_t triple_buffer_lock : 1; 4485 } bits; 4486 4487 /** 4488 * Union for HW Lock flags. 4489 */ 4490 uint8_t u8All; 4491 }; 4492 4493 /** 4494 * Instances of HW to be locked. 4495 * 4496 * Note: If updating with more HW components, fields 4497 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4498 */ 4499 struct dmub_hw_lock_inst_flags { 4500 /** 4501 * OTG HW instance for OTG master update lock. 4502 */ 4503 uint8_t otg_inst; 4504 /** 4505 * OPP instance for cursor lock. 4506 */ 4507 uint8_t opp_inst; 4508 /** 4509 * OTG HW instance for global update lock. 4510 * TODO: Remove, and re-use otg_inst. 4511 */ 4512 uint8_t dig_inst; 4513 /** 4514 * Explicit pad to 4 byte boundary. 4515 */ 4516 uint8_t pad; 4517 }; 4518 4519 /** 4520 * Clients that can acquire the HW Lock Manager. 4521 * 4522 * Note: If updating with more clients, fields in 4523 * dmub_inbox0_cmd_lock_hw must be updated to match. 4524 */ 4525 enum hw_lock_client { 4526 /** 4527 * Driver is the client of HW Lock Manager. 4528 */ 4529 HW_LOCK_CLIENT_DRIVER = 0, 4530 /** 4531 * PSR SU is the client of HW Lock Manager. 4532 */ 4533 HW_LOCK_CLIENT_PSR_SU = 1, 4534 HW_LOCK_CLIENT_SUBVP = 3, 4535 /** 4536 * Replay is the client of HW Lock Manager. 4537 */ 4538 HW_LOCK_CLIENT_REPLAY = 4, 4539 HW_LOCK_CLIENT_FAMS2 = 5, 4540 /** 4541 * Invalid client. 4542 */ 4543 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4544 }; 4545 4546 /** 4547 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4548 */ 4549 struct dmub_cmd_lock_hw_data { 4550 /** 4551 * Specifies the client accessing HW Lock Manager. 4552 */ 4553 enum hw_lock_client client; 4554 /** 4555 * HW instances to be locked. 4556 */ 4557 struct dmub_hw_lock_inst_flags inst_flags; 4558 /** 4559 * Which components to be locked. 4560 */ 4561 union dmub_hw_lock_flags hw_locks; 4562 /** 4563 * Specifies lock/unlock. 4564 */ 4565 uint8_t lock; 4566 /** 4567 * HW can be unlocked separately from releasing the HW Lock Mgr. 4568 * This flag is set if the client wishes to release the object. 4569 */ 4570 uint8_t should_release; 4571 /** 4572 * Explicit padding to 4 byte boundary. 4573 */ 4574 uint8_t pad; 4575 }; 4576 4577 /** 4578 * Definition of a DMUB_CMD__HW_LOCK command. 4579 * Command is used by driver and FW. 4580 */ 4581 struct dmub_rb_cmd_lock_hw { 4582 /** 4583 * Command header. 4584 */ 4585 struct dmub_cmd_header header; 4586 /** 4587 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4588 */ 4589 struct dmub_cmd_lock_hw_data lock_hw_data; 4590 }; 4591 4592 /** 4593 * ABM command sub-types. 4594 */ 4595 enum dmub_cmd_abm_type { 4596 /** 4597 * Initialize parameters for ABM algorithm. 4598 * Data is passed through an indirect buffer. 4599 */ 4600 DMUB_CMD__ABM_INIT_CONFIG = 0, 4601 /** 4602 * Set OTG and panel HW instance. 4603 */ 4604 DMUB_CMD__ABM_SET_PIPE = 1, 4605 /** 4606 * Set user requested backklight level. 4607 */ 4608 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4609 /** 4610 * Set ABM operating/aggression level. 4611 */ 4612 DMUB_CMD__ABM_SET_LEVEL = 3, 4613 /** 4614 * Set ambient light level. 4615 */ 4616 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4617 /** 4618 * Enable/disable fractional duty cycle for backlight PWM. 4619 */ 4620 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4621 4622 /** 4623 * unregister vertical interrupt after steady state is reached 4624 */ 4625 DMUB_CMD__ABM_PAUSE = 6, 4626 4627 /** 4628 * Save and Restore ABM state. On save we save parameters, and 4629 * on restore we update state with passed in data. 4630 */ 4631 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4632 4633 /** 4634 * Query ABM caps. 4635 */ 4636 DMUB_CMD__ABM_QUERY_CAPS = 8, 4637 4638 /** 4639 * Set ABM Events 4640 */ 4641 DMUB_CMD__ABM_SET_EVENT = 9, 4642 4643 /** 4644 * Get the current ACE curve. 4645 */ 4646 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4647 4648 /** 4649 * Get current histogram data 4650 */ 4651 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4652 }; 4653 4654 /** 4655 * LSDMA command sub-types. 4656 */ 4657 enum dmub_cmd_lsdma_type { 4658 /** 4659 * Initialize parameters for LSDMA. 4660 * Ring buffer is mapped to the ring buffer 4661 */ 4662 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 4663 /** 4664 * LSDMA copies data from source to destination linearly 4665 */ 4666 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 4667 /** 4668 * Send the tiled-to-tiled copy command 4669 */ 4670 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 2, 4671 /** 4672 * Send the poll reg write command 4673 */ 4674 DMUB_CMD__LSDMA_POLL_REG_WRITE = 3, 4675 /** 4676 * Send the pio copy command 4677 */ 4678 DMUB_CMD__LSDMA_PIO_COPY = 4, 4679 /** 4680 * Send the pio constfill command 4681 */ 4682 DMUB_CMD__LSDMA_PIO_CONSTFILL = 5, 4683 }; 4684 4685 struct abm_ace_curve { 4686 /** 4687 * @offsets: ACE curve offsets. 4688 */ 4689 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4690 4691 /** 4692 * @thresholds: ACE curve thresholds. 4693 */ 4694 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4695 4696 /** 4697 * @slopes: ACE curve slopes. 4698 */ 4699 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4700 }; 4701 4702 struct fixed_pt_format { 4703 /** 4704 * @sign_bit: Indicates whether one bit is reserved for the sign. 4705 */ 4706 bool sign_bit; 4707 4708 /** 4709 * @num_int_bits: Number of bits used for integer part. 4710 */ 4711 uint8_t num_int_bits; 4712 4713 /** 4714 * @num_frac_bits: Number of bits used for fractional part. 4715 */ 4716 uint8_t num_frac_bits; 4717 4718 /** 4719 * @pad: Explicit padding to 4 byte boundary. 4720 */ 4721 uint8_t pad; 4722 }; 4723 4724 struct abm_caps { 4725 /** 4726 * @num_hg_bins: Number of histogram bins. 4727 */ 4728 uint8_t num_hg_bins; 4729 4730 /** 4731 * @num_ace_segments: Number of ACE curve segments. 4732 */ 4733 uint8_t num_ace_segments; 4734 4735 /** 4736 * @pad: Explicit padding to 4 byte boundary. 4737 */ 4738 uint8_t pad[2]; 4739 4740 /** 4741 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4742 */ 4743 struct fixed_pt_format ace_thresholds_format; 4744 4745 /** 4746 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4747 */ 4748 struct fixed_pt_format ace_offsets_format; 4749 4750 /** 4751 * @ace_slopes_format: Format of the ACE slopes. 4752 */ 4753 struct fixed_pt_format ace_slopes_format; 4754 }; 4755 4756 /** 4757 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4758 * Requirements: 4759 * - Padded explicitly to 32-bit boundary. 4760 * - Must ensure this structure matches the one on driver-side, 4761 * otherwise it won't be aligned. 4762 */ 4763 struct abm_config_table { 4764 /** 4765 * Gamma curve thresholds, used for crgb conversion. 4766 */ 4767 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4768 /** 4769 * Gamma curve offsets, used for crgb conversion. 4770 */ 4771 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4772 /** 4773 * Gamma curve slopes, used for crgb conversion. 4774 */ 4775 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4776 /** 4777 * Custom backlight curve thresholds. 4778 */ 4779 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4780 /** 4781 * Custom backlight curve offsets. 4782 */ 4783 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4784 /** 4785 * Ambient light thresholds. 4786 */ 4787 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4788 /** 4789 * Minimum programmable backlight. 4790 */ 4791 uint16_t min_abm_backlight; // 122B 4792 /** 4793 * Minimum reduction values. 4794 */ 4795 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4796 /** 4797 * Maximum reduction values. 4798 */ 4799 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4800 /** 4801 * Bright positive gain. 4802 */ 4803 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4804 /** 4805 * Dark negative gain. 4806 */ 4807 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4808 /** 4809 * Hybrid factor. 4810 */ 4811 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4812 /** 4813 * Contrast factor. 4814 */ 4815 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4816 /** 4817 * Deviation gain. 4818 */ 4819 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4820 /** 4821 * Minimum knee. 4822 */ 4823 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4824 /** 4825 * Maximum knee. 4826 */ 4827 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4828 /** 4829 * Unused. 4830 */ 4831 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4832 /** 4833 * Explicit padding to 4 byte boundary. 4834 */ 4835 uint8_t pad3[3]; // 229B 4836 /** 4837 * Backlight ramp reduction. 4838 */ 4839 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4840 /** 4841 * Backlight ramp start. 4842 */ 4843 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4844 }; 4845 4846 /** 4847 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4848 */ 4849 struct dmub_cmd_abm_set_pipe_data { 4850 /** 4851 * OTG HW instance. 4852 */ 4853 uint8_t otg_inst; 4854 4855 /** 4856 * Panel Control HW instance. 4857 */ 4858 uint8_t panel_inst; 4859 4860 /** 4861 * Controls how ABM will interpret a set pipe or set level command. 4862 */ 4863 uint8_t set_pipe_option; 4864 4865 /** 4866 * Unused. 4867 * TODO: Remove. 4868 */ 4869 uint8_t ramping_boundary; 4870 4871 /** 4872 * PwrSeq HW Instance. 4873 */ 4874 uint8_t pwrseq_inst; 4875 4876 /** 4877 * Explicit padding to 4 byte boundary. 4878 */ 4879 uint8_t pad[3]; 4880 }; 4881 4882 /** 4883 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4884 */ 4885 struct dmub_rb_cmd_abm_set_pipe { 4886 /** 4887 * Command header. 4888 */ 4889 struct dmub_cmd_header header; 4890 4891 /** 4892 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4893 */ 4894 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4895 }; 4896 4897 /** 4898 * Type of backlight control method to be used by ABM module 4899 */ 4900 enum dmub_backlight_control_type { 4901 /** 4902 * PWM Backlight control 4903 */ 4904 DMU_BACKLIGHT_CONTROL_PWM = 0, 4905 /** 4906 * VESA Aux-based backlight control 4907 */ 4908 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4909 /** 4910 * AMD DPCD Aux-based backlight control 4911 */ 4912 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4913 }; 4914 4915 /** 4916 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4917 */ 4918 struct dmub_cmd_abm_set_backlight_data { 4919 /** 4920 * Number of frames to ramp to backlight user level. 4921 */ 4922 uint32_t frame_ramp; 4923 4924 /** 4925 * Requested backlight level from user. 4926 */ 4927 uint32_t backlight_user_level; 4928 4929 /** 4930 * ABM control version. 4931 */ 4932 uint8_t version; 4933 4934 /** 4935 * Panel Control HW instance mask. 4936 * Bit 0 is Panel Control HW instance 0. 4937 * Bit 1 is Panel Control HW instance 1. 4938 */ 4939 uint8_t panel_mask; 4940 4941 /** 4942 * AUX HW Instance. 4943 */ 4944 uint8_t aux_inst; 4945 4946 /** 4947 * Explicit padding to 4 byte boundary. 4948 */ 4949 uint8_t pad[1]; 4950 4951 /** 4952 * Backlight control type. 4953 * Value 0 is PWM backlight control. 4954 * Value 1 is VAUX backlight control. 4955 * Value 2 is AMD DPCD AUX backlight control. 4956 */ 4957 enum dmub_backlight_control_type backlight_control_type; 4958 4959 /** 4960 * Minimum luminance in nits. 4961 */ 4962 uint32_t min_luminance; 4963 4964 /** 4965 * Maximum luminance in nits. 4966 */ 4967 uint32_t max_luminance; 4968 4969 /** 4970 * Minimum backlight in pwm. 4971 */ 4972 uint32_t min_backlight_pwm; 4973 4974 /** 4975 * Maximum backlight in pwm. 4976 */ 4977 uint32_t max_backlight_pwm; 4978 }; 4979 4980 /** 4981 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4982 */ 4983 struct dmub_rb_cmd_abm_set_backlight { 4984 /** 4985 * Command header. 4986 */ 4987 struct dmub_cmd_header header; 4988 4989 /** 4990 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4991 */ 4992 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4993 }; 4994 4995 /** 4996 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4997 */ 4998 struct dmub_cmd_abm_set_level_data { 4999 /** 5000 * Set current ABM operating/aggression level. 5001 */ 5002 uint32_t level; 5003 5004 /** 5005 * ABM control version. 5006 */ 5007 uint8_t version; 5008 5009 /** 5010 * Panel Control HW instance mask. 5011 * Bit 0 is Panel Control HW instance 0. 5012 * Bit 1 is Panel Control HW instance 1. 5013 */ 5014 uint8_t panel_mask; 5015 5016 /** 5017 * Explicit padding to 4 byte boundary. 5018 */ 5019 uint8_t pad[2]; 5020 }; 5021 5022 /** 5023 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5024 */ 5025 struct dmub_rb_cmd_abm_set_level { 5026 /** 5027 * Command header. 5028 */ 5029 struct dmub_cmd_header header; 5030 5031 /** 5032 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5033 */ 5034 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5035 }; 5036 5037 /** 5038 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5039 */ 5040 struct dmub_cmd_abm_set_ambient_level_data { 5041 /** 5042 * Ambient light sensor reading from OS. 5043 */ 5044 uint32_t ambient_lux; 5045 5046 /** 5047 * ABM control version. 5048 */ 5049 uint8_t version; 5050 5051 /** 5052 * Panel Control HW instance mask. 5053 * Bit 0 is Panel Control HW instance 0. 5054 * Bit 1 is Panel Control HW instance 1. 5055 */ 5056 uint8_t panel_mask; 5057 5058 /** 5059 * Explicit padding to 4 byte boundary. 5060 */ 5061 uint8_t pad[2]; 5062 }; 5063 5064 /** 5065 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5066 */ 5067 struct dmub_rb_cmd_abm_set_ambient_level { 5068 /** 5069 * Command header. 5070 */ 5071 struct dmub_cmd_header header; 5072 5073 /** 5074 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5075 */ 5076 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5077 }; 5078 5079 /** 5080 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5081 */ 5082 struct dmub_cmd_abm_set_pwm_frac_data { 5083 /** 5084 * Enable/disable fractional duty cycle for backlight PWM. 5085 * TODO: Convert to uint8_t. 5086 */ 5087 uint32_t fractional_pwm; 5088 5089 /** 5090 * ABM control version. 5091 */ 5092 uint8_t version; 5093 5094 /** 5095 * Panel Control HW instance mask. 5096 * Bit 0 is Panel Control HW instance 0. 5097 * Bit 1 is Panel Control HW instance 1. 5098 */ 5099 uint8_t panel_mask; 5100 5101 /** 5102 * Explicit padding to 4 byte boundary. 5103 */ 5104 uint8_t pad[2]; 5105 }; 5106 5107 /** 5108 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5109 */ 5110 struct dmub_rb_cmd_abm_set_pwm_frac { 5111 /** 5112 * Command header. 5113 */ 5114 struct dmub_cmd_header header; 5115 5116 /** 5117 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5118 */ 5119 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5120 }; 5121 5122 /** 5123 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5124 */ 5125 struct dmub_cmd_abm_init_config_data { 5126 /** 5127 * Location of indirect buffer used to pass init data to ABM. 5128 */ 5129 union dmub_addr src; 5130 5131 /** 5132 * Indirect buffer length. 5133 */ 5134 uint16_t bytes; 5135 5136 5137 /** 5138 * ABM control version. 5139 */ 5140 uint8_t version; 5141 5142 /** 5143 * Panel Control HW instance mask. 5144 * Bit 0 is Panel Control HW instance 0. 5145 * Bit 1 is Panel Control HW instance 1. 5146 */ 5147 uint8_t panel_mask; 5148 5149 /** 5150 * Explicit padding to 4 byte boundary. 5151 */ 5152 uint8_t pad[2]; 5153 }; 5154 5155 /** 5156 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5157 */ 5158 struct dmub_rb_cmd_abm_init_config { 5159 /** 5160 * Command header. 5161 */ 5162 struct dmub_cmd_header header; 5163 5164 /** 5165 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5166 */ 5167 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5168 }; 5169 5170 /** 5171 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5172 */ 5173 5174 struct dmub_cmd_abm_pause_data { 5175 5176 /** 5177 * Panel Control HW instance mask. 5178 * Bit 0 is Panel Control HW instance 0. 5179 * Bit 1 is Panel Control HW instance 1. 5180 */ 5181 uint8_t panel_mask; 5182 5183 /** 5184 * OTG hw instance 5185 */ 5186 uint8_t otg_inst; 5187 5188 /** 5189 * Enable or disable ABM pause 5190 */ 5191 uint8_t enable; 5192 5193 /** 5194 * Explicit padding to 4 byte boundary. 5195 */ 5196 uint8_t pad[1]; 5197 }; 5198 5199 /** 5200 * Definition of a DMUB_CMD__ABM_PAUSE command. 5201 */ 5202 struct dmub_rb_cmd_abm_pause { 5203 /** 5204 * Command header. 5205 */ 5206 struct dmub_cmd_header header; 5207 5208 /** 5209 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5210 */ 5211 struct dmub_cmd_abm_pause_data abm_pause_data; 5212 }; 5213 5214 /** 5215 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5216 */ 5217 struct dmub_cmd_abm_query_caps_in { 5218 /** 5219 * Panel instance. 5220 */ 5221 uint8_t panel_inst; 5222 5223 /** 5224 * Explicit padding to 4 byte boundary. 5225 */ 5226 uint8_t pad[3]; 5227 }; 5228 5229 /** 5230 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5231 */ 5232 struct dmub_cmd_abm_query_caps_out { 5233 /** 5234 * SW Algorithm caps. 5235 */ 5236 struct abm_caps sw_caps; 5237 5238 /** 5239 * ABM HW caps. 5240 */ 5241 struct abm_caps hw_caps; 5242 }; 5243 5244 /** 5245 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5246 */ 5247 struct dmub_rb_cmd_abm_query_caps { 5248 /** 5249 * Command header. 5250 */ 5251 struct dmub_cmd_header header; 5252 5253 /** 5254 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5255 */ 5256 union { 5257 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5258 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5259 } data; 5260 }; 5261 5262 /** 5263 * enum dmub_abm_ace_curve_type - ACE curve type. 5264 */ 5265 enum dmub_abm_ace_curve_type { 5266 /** 5267 * ACE curve as defined by the SW layer. 5268 */ 5269 ABM_ACE_CURVE_TYPE__SW = 0, 5270 /** 5271 * ACE curve as defined by the SW to HW translation interface layer. 5272 */ 5273 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5274 }; 5275 5276 /** 5277 * enum dmub_abm_histogram_type - Histogram type. 5278 */ 5279 enum dmub_abm_histogram_type { 5280 /** 5281 * ACE curve as defined by the SW layer. 5282 */ 5283 ABM_HISTOGRAM_TYPE__SW = 0, 5284 /** 5285 * ACE curve as defined by the SW to HW translation interface layer. 5286 */ 5287 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5288 }; 5289 5290 /** 5291 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5292 */ 5293 struct dmub_rb_cmd_abm_get_ace_curve { 5294 /** 5295 * Command header. 5296 */ 5297 struct dmub_cmd_header header; 5298 5299 /** 5300 * Address where ACE curve should be copied. 5301 */ 5302 union dmub_addr dest; 5303 5304 /** 5305 * Type of ACE curve being queried. 5306 */ 5307 enum dmub_abm_ace_curve_type ace_type; 5308 5309 /** 5310 * Indirect buffer length. 5311 */ 5312 uint16_t bytes; 5313 5314 /** 5315 * eDP panel instance. 5316 */ 5317 uint8_t panel_inst; 5318 5319 /** 5320 * Explicit padding to 4 byte boundary. 5321 */ 5322 uint8_t pad; 5323 }; 5324 5325 /** 5326 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5327 */ 5328 struct dmub_rb_cmd_abm_get_histogram { 5329 /** 5330 * Command header. 5331 */ 5332 struct dmub_cmd_header header; 5333 5334 /** 5335 * Address where Histogram should be copied. 5336 */ 5337 union dmub_addr dest; 5338 5339 /** 5340 * Type of Histogram being queried. 5341 */ 5342 enum dmub_abm_histogram_type histogram_type; 5343 5344 /** 5345 * Indirect buffer length. 5346 */ 5347 uint16_t bytes; 5348 5349 /** 5350 * eDP panel instance. 5351 */ 5352 uint8_t panel_inst; 5353 5354 /** 5355 * Explicit padding to 4 byte boundary. 5356 */ 5357 uint8_t pad; 5358 }; 5359 5360 /** 5361 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5362 */ 5363 struct dmub_rb_cmd_abm_save_restore { 5364 /** 5365 * Command header. 5366 */ 5367 struct dmub_cmd_header header; 5368 5369 /** 5370 * OTG hw instance 5371 */ 5372 uint8_t otg_inst; 5373 5374 /** 5375 * Enable or disable ABM pause 5376 */ 5377 uint8_t freeze; 5378 5379 /** 5380 * Explicit padding to 4 byte boundary. 5381 */ 5382 uint8_t debug; 5383 5384 /** 5385 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5386 */ 5387 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5388 }; 5389 5390 /** 5391 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5392 */ 5393 5394 struct dmub_cmd_abm_set_event_data { 5395 5396 /** 5397 * VB Scaling Init. Strength Mapping 5398 * Byte 0: 0~255 for VB level 0 5399 * Byte 1: 0~255 for VB level 1 5400 * Byte 2: 0~255 for VB level 2 5401 * Byte 3: 0~255 for VB level 3 5402 */ 5403 uint32_t vb_scaling_strength_mapping; 5404 /** 5405 * VariBright Scaling Enable 5406 */ 5407 uint8_t vb_scaling_enable; 5408 /** 5409 * Panel Control HW instance mask. 5410 * Bit 0 is Panel Control HW instance 0. 5411 * Bit 1 is Panel Control HW instance 1. 5412 */ 5413 uint8_t panel_mask; 5414 5415 /** 5416 * Explicit padding to 4 byte boundary. 5417 */ 5418 uint8_t pad[2]; 5419 }; 5420 5421 /** 5422 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5423 */ 5424 struct dmub_rb_cmd_abm_set_event { 5425 /** 5426 * Command header. 5427 */ 5428 struct dmub_cmd_header header; 5429 5430 /** 5431 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5432 */ 5433 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5434 }; 5435 5436 /** 5437 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5438 */ 5439 struct dmub_cmd_query_feature_caps_data { 5440 /** 5441 * DMUB feature capabilities. 5442 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5443 */ 5444 struct dmub_feature_caps feature_caps; 5445 }; 5446 5447 /** 5448 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5449 */ 5450 struct dmub_rb_cmd_query_feature_caps { 5451 /** 5452 * Command header. 5453 */ 5454 struct dmub_cmd_header header; 5455 /** 5456 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5457 */ 5458 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5459 }; 5460 5461 /** 5462 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5463 */ 5464 struct dmub_cmd_visual_confirm_color_data { 5465 /** 5466 * DMUB visual confirm color 5467 */ 5468 struct dmub_visual_confirm_color visual_confirm_color; 5469 }; 5470 5471 /** 5472 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5473 */ 5474 struct dmub_rb_cmd_get_visual_confirm_color { 5475 /** 5476 * Command header. 5477 */ 5478 struct dmub_cmd_header header; 5479 /** 5480 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5481 */ 5482 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5483 }; 5484 5485 /** 5486 * enum dmub_cmd_panel_cntl_type - Panel control command. 5487 */ 5488 enum dmub_cmd_panel_cntl_type { 5489 /** 5490 * Initializes embedded panel hardware blocks. 5491 */ 5492 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5493 /** 5494 * Queries backlight info for the embedded panel. 5495 */ 5496 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5497 /** 5498 * Sets the PWM Freq as per user's requirement. 5499 */ 5500 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5501 }; 5502 5503 /** 5504 * struct dmub_cmd_panel_cntl_data - Panel control data. 5505 */ 5506 struct dmub_cmd_panel_cntl_data { 5507 uint32_t pwrseq_inst; /**< pwrseq instance */ 5508 uint32_t current_backlight; /* in/out */ 5509 uint32_t bl_pwm_cntl; /* in/out */ 5510 uint32_t bl_pwm_period_cntl; /* in/out */ 5511 uint32_t bl_pwm_ref_div1; /* in/out */ 5512 uint8_t is_backlight_on : 1; /* in/out */ 5513 uint8_t is_powered_on : 1; /* in/out */ 5514 uint8_t padding[3]; 5515 uint32_t bl_pwm_ref_div2; /* in/out */ 5516 uint8_t reserved[4]; 5517 }; 5518 5519 /** 5520 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5521 */ 5522 struct dmub_rb_cmd_panel_cntl { 5523 struct dmub_cmd_header header; /**< header */ 5524 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5525 }; 5526 5527 struct dmub_optc_state { 5528 uint32_t v_total_max; 5529 uint32_t v_total_min; 5530 uint32_t tg_inst; 5531 }; 5532 5533 struct dmub_rb_cmd_drr_update { 5534 struct dmub_cmd_header header; 5535 struct dmub_optc_state dmub_optc_state_req; 5536 }; 5537 5538 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5539 uint32_t pix_clk_100hz; 5540 uint8_t max_ramp_step; 5541 uint8_t pipes; 5542 uint8_t min_refresh_in_hz; 5543 uint8_t pipe_count; 5544 uint8_t pipe_index[4]; 5545 }; 5546 5547 struct dmub_cmd_fw_assisted_mclk_switch_config { 5548 uint8_t fams_enabled; 5549 uint8_t visual_confirm_enabled; 5550 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5551 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5552 }; 5553 5554 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5555 struct dmub_cmd_header header; 5556 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5557 }; 5558 5559 /** 5560 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5561 */ 5562 struct dmub_cmd_lvtma_control_data { 5563 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5564 uint8_t bypass_panel_control_wait; 5565 uint8_t reserved_0[2]; /**< For future use */ 5566 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5567 uint8_t reserved_1[3]; /**< For future use */ 5568 }; 5569 5570 /** 5571 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5572 */ 5573 struct dmub_rb_cmd_lvtma_control { 5574 /** 5575 * Command header. 5576 */ 5577 struct dmub_cmd_header header; 5578 /** 5579 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5580 */ 5581 struct dmub_cmd_lvtma_control_data data; 5582 }; 5583 5584 /** 5585 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5586 */ 5587 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5588 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5589 uint8_t is_usb; /**< is phy is usb */ 5590 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5591 uint8_t is_dp4; /**< is dp in 4 lane */ 5592 }; 5593 5594 /** 5595 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5596 */ 5597 struct dmub_rb_cmd_transmitter_query_dp_alt { 5598 struct dmub_cmd_header header; /**< header */ 5599 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5600 }; 5601 5602 struct phy_test_mode { 5603 uint8_t mode; 5604 uint8_t pat0; 5605 uint8_t pad[2]; 5606 }; 5607 5608 /** 5609 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5610 */ 5611 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5612 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5613 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5614 uint8_t lane_num; /**< Number of lanes */ 5615 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5616 struct phy_test_mode test_mode; 5617 enum dmub_phy_fsm_state state; 5618 uint32_t status; 5619 uint8_t pad; 5620 }; 5621 5622 /** 5623 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5624 */ 5625 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5626 struct dmub_cmd_header header; /**< header */ 5627 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5628 }; 5629 5630 /** 5631 * Maximum number of bytes a chunk sent to DMUB for parsing 5632 */ 5633 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5634 5635 /** 5636 * Represent a chunk of CEA blocks sent to DMUB for parsing 5637 */ 5638 struct dmub_cmd_send_edid_cea { 5639 uint16_t offset; /**< offset into the CEA block */ 5640 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5641 uint16_t cea_total_length; /**< total length of the CEA block */ 5642 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5643 uint8_t pad[3]; /**< padding and for future expansion */ 5644 }; 5645 5646 /** 5647 * Result of VSDB parsing from CEA block 5648 */ 5649 struct dmub_cmd_edid_cea_amd_vsdb { 5650 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5651 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5652 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5653 uint16_t min_frame_rate; /**< Maximum frame rate */ 5654 uint16_t max_frame_rate; /**< Minimum frame rate */ 5655 }; 5656 5657 /** 5658 * Result of sending a CEA chunk 5659 */ 5660 struct dmub_cmd_edid_cea_ack { 5661 uint16_t offset; /**< offset of the chunk into the CEA block */ 5662 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5663 uint8_t pad; /**< padding and for future expansion */ 5664 }; 5665 5666 /** 5667 * Specify whether the result is an ACK/NACK or the parsing has finished 5668 */ 5669 enum dmub_cmd_edid_cea_reply_type { 5670 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5671 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5672 }; 5673 5674 /** 5675 * Definition of a DMUB_CMD__EDID_CEA command. 5676 */ 5677 struct dmub_rb_cmd_edid_cea { 5678 struct dmub_cmd_header header; /**< Command header */ 5679 union dmub_cmd_edid_cea_data { 5680 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5681 struct dmub_cmd_edid_cea_output { /**< output with results */ 5682 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5683 union { 5684 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5685 struct dmub_cmd_edid_cea_ack ack; 5686 }; 5687 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5688 } data; /**< Command data */ 5689 5690 }; 5691 5692 /** 5693 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5694 */ 5695 struct dmub_cmd_cable_id_input { 5696 uint8_t phy_inst; /**< phy inst for cable id data */ 5697 }; 5698 5699 /** 5700 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5701 */ 5702 struct dmub_cmd_cable_id_output { 5703 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5704 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5705 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5706 uint8_t RESERVED :2; /**< reserved means not defined */ 5707 }; 5708 5709 /** 5710 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5711 */ 5712 struct dmub_rb_cmd_get_usbc_cable_id { 5713 struct dmub_cmd_header header; /**< Command header */ 5714 /** 5715 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5716 */ 5717 union dmub_cmd_cable_id_data { 5718 struct dmub_cmd_cable_id_input input; /**< Input */ 5719 struct dmub_cmd_cable_id_output output; /**< Output */ 5720 uint8_t output_raw; /**< Raw data output */ 5721 } data; 5722 }; 5723 5724 enum dmub_cmd_fused_io_sub_type { 5725 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5726 DMUB_CMD__FUSED_IO_ABORT = 1, 5727 }; 5728 5729 enum dmub_cmd_fused_request_type { 5730 FUSED_REQUEST_READ, 5731 FUSED_REQUEST_WRITE, 5732 FUSED_REQUEST_POLL, 5733 }; 5734 5735 enum dmub_cmd_fused_request_status { 5736 FUSED_REQUEST_STATUS_SUCCESS, 5737 FUSED_REQUEST_STATUS_BEGIN, 5738 FUSED_REQUEST_STATUS_SUBMIT, 5739 FUSED_REQUEST_STATUS_REPLY, 5740 FUSED_REQUEST_STATUS_POLL, 5741 FUSED_REQUEST_STATUS_ABORTED, 5742 FUSED_REQUEST_STATUS_FAILED = 0x80, 5743 FUSED_REQUEST_STATUS_INVALID, 5744 FUSED_REQUEST_STATUS_BUSY, 5745 FUSED_REQUEST_STATUS_TIMEOUT, 5746 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5747 }; 5748 5749 struct dmub_cmd_fused_request { 5750 uint8_t status; 5751 uint8_t type : 2; 5752 uint8_t _reserved0 : 3; 5753 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5754 uint8_t identifier; 5755 uint8_t _reserved1; 5756 uint32_t timeout_us; 5757 union dmub_cmd_fused_request_location { 5758 struct dmub_cmd_fused_request_location_i2c { 5759 uint8_t is_aux : 1; // False 5760 uint8_t ddc_line : 3; 5761 uint8_t over_aux : 1; 5762 uint8_t _reserved0 : 3; 5763 uint8_t address; 5764 uint8_t offset; 5765 uint8_t length; 5766 } i2c; 5767 struct dmub_cmd_fused_request_location_aux { 5768 uint32_t is_aux : 1; // True 5769 uint32_t ddc_line : 3; 5770 uint32_t address : 20; 5771 uint32_t length : 8; // Automatically split into 16B transactions 5772 } aux; 5773 } u; 5774 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5775 }; 5776 5777 struct dmub_rb_cmd_fused_io { 5778 struct dmub_cmd_header header; 5779 struct dmub_cmd_fused_request request; 5780 }; 5781 5782 /** 5783 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5784 */ 5785 enum dmub_cmd_secure_display_type { 5786 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5787 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5788 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5789 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5790 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5791 }; 5792 5793 #define MAX_ROI_NUM 2 5794 5795 struct dmub_cmd_roi_info { 5796 uint16_t x_start; 5797 uint16_t x_end; 5798 uint16_t y_start; 5799 uint16_t y_end; 5800 uint8_t otg_id; 5801 uint8_t phy_id; 5802 }; 5803 5804 struct dmub_cmd_roi_window_ctl { 5805 uint16_t x_start; 5806 uint16_t x_end; 5807 uint16_t y_start; 5808 uint16_t y_end; 5809 bool enable; 5810 }; 5811 5812 struct dmub_cmd_roi_ctl_info { 5813 uint8_t otg_id; 5814 uint8_t phy_id; 5815 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5816 }; 5817 5818 /** 5819 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5820 */ 5821 struct dmub_rb_cmd_secure_display { 5822 struct dmub_cmd_header header; 5823 /** 5824 * Data passed from driver to dmub firmware. 5825 */ 5826 struct dmub_cmd_roi_info roi_info; 5827 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5828 }; 5829 5830 /** 5831 * Command type of a DMUB_CMD__PSP command 5832 */ 5833 enum dmub_cmd_psp_type { 5834 DMUB_CMD__PSP_ASSR_ENABLE = 0 5835 }; 5836 5837 /** 5838 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5839 */ 5840 struct dmub_cmd_assr_enable_data { 5841 /** 5842 * ASSR enable or disable. 5843 */ 5844 uint8_t enable; 5845 /** 5846 * PHY port type. 5847 * Indicates eDP / non-eDP port type 5848 */ 5849 uint8_t phy_port_type; 5850 /** 5851 * PHY port ID. 5852 */ 5853 uint8_t phy_port_id; 5854 /** 5855 * Link encoder index. 5856 */ 5857 uint8_t link_enc_index; 5858 /** 5859 * HPO mode. 5860 */ 5861 uint8_t hpo_mode; 5862 5863 /** 5864 * Reserved field. 5865 */ 5866 uint8_t reserved[7]; 5867 }; 5868 5869 /** 5870 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5871 */ 5872 struct dmub_rb_cmd_assr_enable { 5873 /** 5874 * Command header. 5875 */ 5876 struct dmub_cmd_header header; 5877 5878 /** 5879 * Assr data. 5880 */ 5881 struct dmub_cmd_assr_enable_data assr_data; 5882 5883 /** 5884 * Reserved field. 5885 */ 5886 uint32_t reserved[3]; 5887 }; 5888 5889 /** 5890 * Current definition of "ips_mode" from driver 5891 */ 5892 enum ips_residency_mode { 5893 IPS_RESIDENCY__IPS1_MAX, 5894 IPS_RESIDENCY__IPS2, 5895 IPS_RESIDENCY__IPS1_RCG, 5896 IPS_RESIDENCY__IPS1_ONO2_ON, 5897 }; 5898 5899 #define NUM_IPS_HISTOGRAM_BUCKETS 16 5900 5901 /** 5902 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 5903 */ 5904 struct dmub_ips_residency_info { 5905 uint32_t residency_millipercent; 5906 uint32_t entry_counter; 5907 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 5908 uint64_t total_time_us; 5909 uint64_t total_inactive_time_us; 5910 }; 5911 5912 /** 5913 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 5914 */ 5915 struct dmub_cmd_ips_residency_cntl_data { 5916 uint8_t panel_inst; 5917 uint8_t start_measurement; 5918 uint8_t padding[2]; // align to 4-byte boundary 5919 }; 5920 5921 struct dmub_rb_cmd_ips_residency_cntl { 5922 struct dmub_cmd_header header; 5923 struct dmub_cmd_ips_residency_cntl_data cntl_data; 5924 }; 5925 5926 /** 5927 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 5928 */ 5929 struct dmub_cmd_ips_query_residency_info_data { 5930 union dmub_addr dest; 5931 uint32_t size; 5932 uint32_t ips_mode; 5933 uint8_t panel_inst; 5934 uint8_t padding[3]; // align to 4-byte boundary 5935 }; 5936 5937 struct dmub_rb_cmd_ips_query_residency_info { 5938 struct dmub_cmd_header header; 5939 struct dmub_cmd_ips_query_residency_info_data info_data; 5940 }; 5941 5942 /** 5943 * union dmub_rb_cmd - DMUB inbox command. 5944 */ 5945 union dmub_rb_cmd { 5946 /** 5947 * Elements shared with all commands. 5948 */ 5949 struct dmub_rb_cmd_common cmd_common; 5950 /** 5951 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5952 */ 5953 struct dmub_rb_cmd_read_modify_write read_modify_write; 5954 /** 5955 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5956 */ 5957 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5958 /** 5959 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5960 */ 5961 struct dmub_rb_cmd_burst_write burst_write; 5962 /** 5963 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5964 */ 5965 struct dmub_rb_cmd_reg_wait reg_wait; 5966 /** 5967 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5968 */ 5969 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5970 /** 5971 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5972 */ 5973 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5974 /** 5975 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5976 */ 5977 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5978 /** 5979 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5980 */ 5981 struct dmub_rb_cmd_dpphy_init dpphy_init; 5982 /** 5983 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5984 */ 5985 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5986 /** 5987 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5988 */ 5989 struct dmub_rb_cmd_domain_control domain_control; 5990 /** 5991 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5992 */ 5993 struct dmub_rb_cmd_psr_set_version psr_set_version; 5994 /** 5995 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5996 */ 5997 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5998 /** 5999 * Definition of a DMUB_CMD__PSR_ENABLE command. 6000 */ 6001 struct dmub_rb_cmd_psr_enable psr_enable; 6002 /** 6003 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 6004 */ 6005 struct dmub_rb_cmd_psr_set_level psr_set_level; 6006 /** 6007 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 6008 */ 6009 struct dmub_rb_cmd_psr_force_static psr_force_static; 6010 /** 6011 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 6012 */ 6013 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6014 /** 6015 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6016 */ 6017 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6018 /** 6019 * Definition of a DMUB_CMD__HW_LOCK command. 6020 * Command is used by driver and FW. 6021 */ 6022 struct dmub_rb_cmd_lock_hw lock_hw; 6023 /** 6024 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6025 */ 6026 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6027 /** 6028 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6029 */ 6030 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6031 /** 6032 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6033 */ 6034 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6035 /** 6036 * Definition of a DMUB_CMD__MALL command. 6037 */ 6038 struct dmub_rb_cmd_mall mall; 6039 6040 /** 6041 * Definition of a DMUB_CMD__CAB command. 6042 */ 6043 struct dmub_rb_cmd_cab_for_ss cab; 6044 6045 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6046 6047 /** 6048 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6049 */ 6050 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6051 6052 /** 6053 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6054 */ 6055 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6056 6057 /** 6058 * Definition of DMUB_CMD__PANEL_CNTL commands. 6059 */ 6060 struct dmub_rb_cmd_panel_cntl panel_cntl; 6061 6062 /** 6063 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6064 */ 6065 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6066 6067 /** 6068 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6069 */ 6070 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6071 6072 /** 6073 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6074 */ 6075 struct dmub_rb_cmd_abm_set_level abm_set_level; 6076 6077 /** 6078 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6079 */ 6080 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6081 6082 /** 6083 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6084 */ 6085 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6086 6087 /** 6088 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6089 */ 6090 struct dmub_rb_cmd_abm_init_config abm_init_config; 6091 6092 /** 6093 * Definition of a DMUB_CMD__ABM_PAUSE command. 6094 */ 6095 struct dmub_rb_cmd_abm_pause abm_pause; 6096 6097 /** 6098 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6099 */ 6100 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6101 6102 /** 6103 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6104 */ 6105 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6106 6107 /** 6108 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6109 */ 6110 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6111 6112 /** 6113 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6114 */ 6115 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6116 6117 /** 6118 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6119 */ 6120 struct dmub_rb_cmd_abm_set_event abm_set_event; 6121 6122 /** 6123 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6124 */ 6125 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6126 6127 /** 6128 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6129 */ 6130 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6131 6132 /** 6133 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6134 */ 6135 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6136 6137 /** 6138 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6139 */ 6140 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6141 struct dmub_rb_cmd_drr_update drr_update; 6142 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6143 6144 /** 6145 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6146 */ 6147 struct dmub_rb_cmd_lvtma_control lvtma_control; 6148 /** 6149 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6150 */ 6151 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6152 /** 6153 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6154 */ 6155 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6156 /** 6157 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6158 */ 6159 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6160 /** 6161 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6162 */ 6163 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6164 /** 6165 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6166 */ 6167 struct dmub_rb_cmd_set_config_request set_config_request; 6168 /** 6169 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6170 */ 6171 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6172 /** 6173 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6174 */ 6175 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6176 /** 6177 * Definition of a DMUB_CMD__EDID_CEA command. 6178 */ 6179 struct dmub_rb_cmd_edid_cea edid_cea; 6180 /** 6181 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6182 */ 6183 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6184 6185 /** 6186 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6187 */ 6188 struct dmub_rb_cmd_query_hpd_state query_hpd; 6189 /** 6190 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6191 */ 6192 struct dmub_rb_cmd_secure_display secure_display; 6193 6194 /** 6195 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6196 */ 6197 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6198 /** 6199 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6200 */ 6201 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6202 /** 6203 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6204 */ 6205 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6206 /* 6207 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6208 */ 6209 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6210 /** 6211 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6212 */ 6213 struct dmub_rb_cmd_replay_enable replay_enable; 6214 /** 6215 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6216 */ 6217 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6218 /** 6219 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6220 */ 6221 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6222 /** 6223 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6224 */ 6225 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6226 6227 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6228 /** 6229 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6230 */ 6231 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6232 /** 6233 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6234 */ 6235 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6236 /** 6237 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6238 */ 6239 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6240 /** 6241 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6242 */ 6243 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6244 /** 6245 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6246 */ 6247 struct dmub_rb_cmd_assr_enable assr_enable; 6248 6249 struct dmub_rb_cmd_fams2 fams2_config; 6250 6251 struct dmub_rb_cmd_ib ib_fams2_config; 6252 6253 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6254 6255 struct dmub_rb_cmd_fams2_flip fams2_flip; 6256 6257 struct dmub_rb_cmd_fused_io fused_io; 6258 6259 /** 6260 * Definition of a DMUB_CMD__LSDMA command. 6261 */ 6262 struct dmub_rb_cmd_lsdma lsdma; 6263 6264 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 6265 6266 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 6267 }; 6268 6269 /** 6270 * union dmub_rb_out_cmd - Outbox command 6271 */ 6272 union dmub_rb_out_cmd { 6273 /** 6274 * Parameters common to every command. 6275 */ 6276 struct dmub_rb_cmd_common cmd_common; 6277 /** 6278 * AUX reply command. 6279 */ 6280 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6281 /** 6282 * HPD notify command. 6283 */ 6284 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6285 /** 6286 * SET_CONFIG reply command. 6287 */ 6288 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6289 /** 6290 * DPIA notification command. 6291 */ 6292 struct dmub_rb_cmd_dpia_notification dpia_notification; 6293 /** 6294 * HPD sense notification command. 6295 */ 6296 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6297 struct dmub_rb_cmd_fused_io fused_io; 6298 }; 6299 #pragma pack(pop) 6300 6301 6302 //============================================================================== 6303 //</DMUB_CMD>=================================================================== 6304 //============================================================================== 6305 //< DMUB_RB>==================================================================== 6306 //============================================================================== 6307 6308 /** 6309 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6310 */ 6311 struct dmub_rb_init_params { 6312 void *ctx; /**< Caller provided context pointer */ 6313 void *base_address; /**< CPU base address for ring's data */ 6314 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6315 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6316 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6317 }; 6318 6319 /** 6320 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6321 */ 6322 struct dmub_rb { 6323 void *base_address; /**< CPU address for the ring's data */ 6324 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6325 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6326 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6327 6328 void *ctx; /**< Caller provided context pointer */ 6329 void *dmub; /**< Pointer to the DMUB interface */ 6330 }; 6331 6332 /** 6333 * @brief Checks if the ringbuffer is empty. 6334 * 6335 * @param rb DMUB Ringbuffer 6336 * @return true if empty 6337 * @return false otherwise 6338 */ 6339 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6340 { 6341 return (rb->wrpt == rb->rptr); 6342 } 6343 6344 /** 6345 * @brief gets number of outstanding requests in the RB 6346 * 6347 * @param rb DMUB Ringbuffer 6348 * @return true if full 6349 */ 6350 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6351 { 6352 uint32_t data_count; 6353 6354 if (rb->wrpt >= rb->rptr) 6355 data_count = rb->wrpt - rb->rptr; 6356 else 6357 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6358 6359 return data_count / DMUB_RB_CMD_SIZE; 6360 } 6361 6362 /** 6363 * @brief gets number of free buffers in the RB 6364 * 6365 * @param rb DMUB Ringbuffer 6366 * @return true if full 6367 */ 6368 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6369 { 6370 uint32_t data_count; 6371 6372 if (rb->wrpt >= rb->rptr) 6373 data_count = rb->wrpt - rb->rptr; 6374 else 6375 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6376 6377 /* +1 because 1 entry is always unusable */ 6378 data_count += DMUB_RB_CMD_SIZE; 6379 6380 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6381 } 6382 6383 /** 6384 * @brief Checks if the ringbuffer is full 6385 * 6386 * @param rb DMUB Ringbuffer 6387 * @return true if full 6388 * @return false otherwise 6389 */ 6390 static inline bool dmub_rb_full(struct dmub_rb *rb) 6391 { 6392 uint32_t data_count; 6393 6394 if (rb->wrpt >= rb->rptr) 6395 data_count = rb->wrpt - rb->rptr; 6396 else 6397 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6398 6399 /* -1 because 1 entry is always unusable */ 6400 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6401 } 6402 6403 /** 6404 * @brief Pushes a command into the ringbuffer 6405 * 6406 * @param rb DMUB ringbuffer 6407 * @param cmd The command to push 6408 * @return true if the ringbuffer was not full 6409 * @return false otherwise 6410 */ 6411 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6412 const union dmub_rb_cmd *cmd) 6413 { 6414 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6415 const uint64_t *src = (const uint64_t *)cmd; 6416 uint8_t i; 6417 6418 if (dmub_rb_full(rb)) 6419 return false; 6420 6421 // copying data 6422 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6423 *dst++ = *src++; 6424 6425 rb->wrpt += DMUB_RB_CMD_SIZE; 6426 6427 if (rb->wrpt >= rb->capacity) 6428 rb->wrpt %= rb->capacity; 6429 6430 return true; 6431 } 6432 6433 /** 6434 * @brief Pushes a command into the DMUB outbox ringbuffer 6435 * 6436 * @param rb DMUB outbox ringbuffer 6437 * @param cmd Outbox command 6438 * @return true if not full 6439 * @return false otherwise 6440 */ 6441 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6442 const union dmub_rb_out_cmd *cmd) 6443 { 6444 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6445 const uint8_t *src = (const uint8_t *)cmd; 6446 6447 if (dmub_rb_full(rb)) 6448 return false; 6449 6450 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6451 6452 rb->wrpt += DMUB_RB_CMD_SIZE; 6453 6454 if (rb->wrpt >= rb->capacity) 6455 rb->wrpt %= rb->capacity; 6456 6457 return true; 6458 } 6459 6460 /** 6461 * @brief Returns the next unprocessed command in the ringbuffer. 6462 * 6463 * @param rb DMUB ringbuffer 6464 * @param cmd The command to return 6465 * @return true if not empty 6466 * @return false otherwise 6467 */ 6468 static inline bool dmub_rb_front(struct dmub_rb *rb, 6469 union dmub_rb_cmd **cmd) 6470 { 6471 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6472 6473 if (dmub_rb_empty(rb)) 6474 return false; 6475 6476 *cmd = (union dmub_rb_cmd *)rb_cmd; 6477 6478 return true; 6479 } 6480 6481 /** 6482 * @brief Determines the next ringbuffer offset. 6483 * 6484 * @param rb DMUB inbox ringbuffer 6485 * @param num_cmds Number of commands 6486 * @param next_rptr The next offset in the ringbuffer 6487 */ 6488 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6489 uint32_t num_cmds, 6490 uint32_t *next_rptr) 6491 { 6492 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6493 6494 if (*next_rptr >= rb->capacity) 6495 *next_rptr %= rb->capacity; 6496 } 6497 6498 /** 6499 * @brief Returns a pointer to a command in the inbox. 6500 * 6501 * @param rb DMUB inbox ringbuffer 6502 * @param cmd The inbox command to return 6503 * @param rptr The ringbuffer offset 6504 * @return true if not empty 6505 * @return false otherwise 6506 */ 6507 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6508 union dmub_rb_cmd **cmd, 6509 uint32_t rptr) 6510 { 6511 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6512 6513 if (dmub_rb_empty(rb)) 6514 return false; 6515 6516 *cmd = (union dmub_rb_cmd *)rb_cmd; 6517 6518 return true; 6519 } 6520 6521 /** 6522 * @brief Returns the next unprocessed command in the outbox. 6523 * 6524 * @param rb DMUB outbox ringbuffer 6525 * @param cmd The outbox command to return 6526 * @return true if not empty 6527 * @return false otherwise 6528 */ 6529 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6530 union dmub_rb_out_cmd *cmd) 6531 { 6532 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6533 uint64_t *dst = (uint64_t *)cmd; 6534 uint8_t i; 6535 6536 if (dmub_rb_empty(rb)) 6537 return false; 6538 6539 // copying data 6540 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6541 *dst++ = *src++; 6542 6543 return true; 6544 } 6545 6546 /** 6547 * @brief Removes the front entry in the ringbuffer. 6548 * 6549 * @param rb DMUB ringbuffer 6550 * @return true if the command was removed 6551 * @return false if there were no commands 6552 */ 6553 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6554 { 6555 if (dmub_rb_empty(rb)) 6556 return false; 6557 6558 rb->rptr += DMUB_RB_CMD_SIZE; 6559 6560 if (rb->rptr >= rb->capacity) 6561 rb->rptr %= rb->capacity; 6562 6563 return true; 6564 } 6565 6566 /** 6567 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6568 * 6569 * Avoids a race condition where DMCUB accesses memory while 6570 * there are still writes in flight to framebuffer. 6571 * 6572 * @param rb DMUB ringbuffer 6573 */ 6574 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6575 { 6576 uint32_t rptr = rb->rptr; 6577 uint32_t wptr = rb->wrpt; 6578 6579 while (rptr != wptr) { 6580 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6581 uint8_t i; 6582 6583 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6584 (void)READ_ONCE(*data++); 6585 6586 rptr += DMUB_RB_CMD_SIZE; 6587 if (rptr >= rb->capacity) 6588 rptr %= rb->capacity; 6589 } 6590 } 6591 6592 /** 6593 * @brief Initializes a DMCUB ringbuffer 6594 * 6595 * @param rb DMUB ringbuffer 6596 * @param init_params initial configuration for the ringbuffer 6597 */ 6598 static inline void dmub_rb_init(struct dmub_rb *rb, 6599 struct dmub_rb_init_params *init_params) 6600 { 6601 rb->base_address = init_params->base_address; 6602 rb->capacity = init_params->capacity; 6603 rb->rptr = init_params->read_ptr; 6604 rb->wrpt = init_params->write_ptr; 6605 } 6606 6607 /** 6608 * @brief Copies output data from in/out commands into the given command. 6609 * 6610 * @param rb DMUB ringbuffer 6611 * @param cmd Command to copy data into 6612 */ 6613 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6614 union dmub_rb_cmd *cmd) 6615 { 6616 // Copy rb entry back into command 6617 uint8_t *rd_ptr = (rb->rptr == 0) ? 6618 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6619 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6620 6621 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6622 } 6623 6624 //============================================================================== 6625 //</DMUB_RB>==================================================================== 6626 //============================================================================== 6627 #endif /* _DMUB_CMD_H_ */ 6628