1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic udelay 165 */ 166 #ifndef dmub_udelay 167 #define dmub_udelay(microseconds) udelay(microseconds) 168 #endif 169 170 #pragma pack(push, 1) 171 #define ABM_NUM_OF_ACE_SEGMENTS 5 172 173 union abm_flags { 174 struct { 175 /** 176 * @abm_enabled: Indicates if ABM is enabled. 177 */ 178 unsigned int abm_enabled : 1; 179 180 /** 181 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 182 */ 183 unsigned int disable_abm_requested : 1; 184 185 /** 186 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 187 */ 188 unsigned int disable_abm_immediately : 1; 189 190 /** 191 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 192 * to be disabled immediately and keep gain. 193 */ 194 unsigned int disable_abm_immediate_keep_gain : 1; 195 196 /** 197 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 198 */ 199 unsigned int fractional_pwm : 1; 200 201 /** 202 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 203 * of user backlight level. 204 */ 205 unsigned int abm_gradual_bl_change : 1; 206 207 /** 208 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 209 */ 210 unsigned int abm_new_frame : 1; 211 212 /** 213 * @vb_scaling_enabled: Indicates variBright Scaling Enable 214 */ 215 unsigned int vb_scaling_enabled : 1; 216 } bitfields; 217 218 unsigned int u32All; 219 }; 220 221 struct abm_save_restore { 222 /** 223 * @flags: Misc. ABM flags. 224 */ 225 union abm_flags flags; 226 227 /** 228 * @pause: true: pause ABM and get state 229 * false: unpause ABM after setting state 230 */ 231 uint32_t pause; 232 233 /** 234 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 235 */ 236 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 237 238 /** 239 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 240 */ 241 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 242 243 /** 244 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 245 */ 246 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 247 248 249 /** 250 * @knee_threshold: Current x-position of ACE knee (u0.16). 251 */ 252 uint32_t knee_threshold; 253 /** 254 * @current_gain: Current backlight reduction (u16.16). 255 */ 256 uint32_t current_gain; 257 /** 258 * @curr_bl_level: Current actual backlight level converging to target backlight level. 259 */ 260 uint16_t curr_bl_level; 261 262 /** 263 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 264 */ 265 uint16_t curr_user_bl_level; 266 267 }; 268 269 /** 270 * union dmub_addr - DMUB physical/virtual 64-bit address. 271 */ 272 union dmub_addr { 273 struct { 274 uint32_t low_part; /**< Lower 32 bits */ 275 uint32_t high_part; /**< Upper 32 bits */ 276 } u; /*<< Low/high bit access */ 277 uint64_t quad_part; /*<< 64 bit address */ 278 }; 279 #pragma pack(pop) 280 281 /** 282 * Dirty rect definition. 283 */ 284 struct dmub_rect { 285 /** 286 * Dirty rect x offset. 287 */ 288 uint32_t x; 289 290 /** 291 * Dirty rect y offset. 292 */ 293 uint32_t y; 294 295 /** 296 * Dirty rect width. 297 */ 298 uint32_t width; 299 300 /** 301 * Dirty rect height. 302 */ 303 uint32_t height; 304 }; 305 306 /** 307 * Flags that can be set by driver to change some PSR behaviour. 308 */ 309 union dmub_psr_debug_flags { 310 /** 311 * Debug flags. 312 */ 313 struct { 314 /** 315 * Enable visual confirm in FW. 316 */ 317 uint32_t visual_confirm : 1; 318 319 /** 320 * Force all selective updates to bw full frame updates. 321 */ 322 uint32_t force_full_frame_update : 1; 323 324 /** 325 * Use HW Lock Mgr object to do HW locking in FW. 326 */ 327 uint32_t use_hw_lock_mgr : 1; 328 329 /** 330 * Use TPS3 signal when restore main link. 331 */ 332 uint32_t force_wakeup_by_tps3 : 1; 333 334 /** 335 * Back to back flip, therefore cannot power down PHY 336 */ 337 uint32_t back_to_back_flip : 1; 338 339 } bitfields; 340 341 /** 342 * Union for debug flags. 343 */ 344 uint32_t u32All; 345 }; 346 347 /** 348 * Flags that can be set by driver to change some Replay behaviour. 349 */ 350 union replay_debug_flags { 351 struct { 352 /** 353 * 0x1 (bit 0) 354 * Enable visual confirm in FW. 355 */ 356 uint32_t visual_confirm : 1; 357 358 /** 359 * 0x2 (bit 1) 360 * @skip_crc: Set if need to skip CRC. 361 */ 362 uint32_t skip_crc : 1; 363 364 /** 365 * 0x4 (bit 2) 366 * @force_link_power_on: Force disable ALPM control 367 */ 368 uint32_t force_link_power_on : 1; 369 370 /** 371 * 0x8 (bit 3) 372 * @force_phy_power_on: Force phy power on 373 */ 374 uint32_t force_phy_power_on : 1; 375 376 /** 377 * 0x10 (bit 4) 378 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 379 */ 380 uint32_t timing_resync_disabled : 1; 381 382 /** 383 * 0x20 (bit 5) 384 * @skip_crtc_disabled: CRTC disable skipped 385 */ 386 uint32_t skip_crtc_disabled : 1; 387 388 /** 389 * 0x40 (bit 6) 390 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 391 */ 392 uint32_t force_defer_one_frame_update : 1; 393 394 /** 395 * 0x80 (bit 7) 396 * @disable_delay_alpm_on: Force disable delay alpm on 397 */ 398 uint32_t disable_delay_alpm_on : 1; 399 400 /** 401 * 0x100 (bit 8) 402 * @disable_desync_error_check: Force disable desync error check 403 */ 404 uint32_t disable_desync_error_check : 1; 405 406 /** 407 * 0x200 (bit 9) 408 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 409 */ 410 uint32_t force_self_update_when_abm_non_steady : 1; 411 412 /** 413 * 0x400 (bit 10) 414 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 415 * If we enter IPS2, the Visual confirm bar will change to yellow 416 */ 417 uint32_t enable_ips_visual_confirm : 1; 418 419 /** 420 * 0x800 (bit 11) 421 * @enable_ips_residency_profiling: Enable IPS residency profiling 422 */ 423 uint32_t enable_ips_residency_profiling : 1; 424 425 uint32_t reserved : 20; 426 } bitfields; 427 428 uint32_t u32All; 429 }; 430 431 union replay_hw_flags { 432 struct { 433 /** 434 * @allow_alpm_fw_standby_mode: To indicate whether the 435 * ALPM FW standby mode is allowed 436 */ 437 uint32_t allow_alpm_fw_standby_mode : 1; 438 439 /* 440 * @dsc_enable_status: DSC enable status in driver 441 */ 442 uint32_t dsc_enable_status : 1; 443 444 /** 445 * @fec_enable_status: receive fec enable/disable status from driver 446 */ 447 uint32_t fec_enable_status : 1; 448 449 /* 450 * @smu_optimizations_en: SMU power optimization. 451 * Only when active display is Replay capable and display enters Replay. 452 * Trigger interrupt to SMU to powerup/down. 453 */ 454 uint32_t smu_optimizations_en : 1; 455 456 /** 457 * @phy_power_state: Indicates current phy power state 458 */ 459 uint32_t phy_power_state : 1; 460 461 /** 462 * @link_power_state: Indicates current link power state 463 */ 464 uint32_t link_power_state : 1; 465 /** 466 * Use TPS3 signal when restore main link. 467 */ 468 uint32_t force_wakeup_by_tps3 : 1; 469 } bitfields; 470 471 uint32_t u32All; 472 }; 473 474 /** 475 * DMUB feature capabilities. 476 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 477 */ 478 struct dmub_feature_caps { 479 /** 480 * Max PSR version supported by FW. 481 */ 482 uint8_t psr; 483 uint8_t fw_assisted_mclk_switch_ver; 484 uint8_t reserved[4]; 485 uint8_t subvp_psr_support; 486 uint8_t gecc_enable; 487 uint8_t replay_supported; 488 uint8_t replay_reserved[3]; 489 }; 490 491 struct dmub_visual_confirm_color { 492 /** 493 * Maximum 10 bits color value 494 */ 495 uint16_t color_r_cr; 496 uint16_t color_g_y; 497 uint16_t color_b_cb; 498 uint16_t panel_inst; 499 }; 500 501 //============================================================================== 502 //</DMUB_TYPES>================================================================= 503 //============================================================================== 504 //< DMUB_META>================================================================== 505 //============================================================================== 506 #pragma pack(push, 1) 507 508 /* Magic value for identifying dmub_fw_meta_info */ 509 #define DMUB_FW_META_MAGIC 0x444D5542 510 511 /* Offset from the end of the file to the dmub_fw_meta_info */ 512 #define DMUB_FW_META_OFFSET 0x24 513 514 /** 515 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 516 */ 517 union dmub_fw_meta_feature_bits { 518 struct { 519 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 520 uint32_t reserved : 31; 521 } bits; /**< status bits */ 522 uint32_t all; /**< 32-bit access to status bits */ 523 }; 524 525 /** 526 * struct dmub_fw_meta_info - metadata associated with fw binary 527 * 528 * NOTE: This should be considered a stable API. Fields should 529 * not be repurposed or reordered. New fields should be 530 * added instead to extend the structure. 531 * 532 * @magic_value: magic value identifying DMUB firmware meta info 533 * @fw_region_size: size of the firmware state region 534 * @trace_buffer_size: size of the tracebuffer region 535 * @fw_version: the firmware version information 536 * @dal_fw: 1 if the firmware is DAL 537 * @shared_state_size: size of the shared state region in bytes 538 * @shared_state_features: number of shared state features 539 */ 540 struct dmub_fw_meta_info { 541 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 542 uint32_t fw_region_size; /**< size of the firmware state region */ 543 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 544 uint32_t fw_version; /**< the firmware version information */ 545 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 546 uint8_t reserved[3]; /**< padding bits */ 547 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 548 uint16_t shared_state_features; /**< number of shared state features */ 549 uint16_t reserved2; /**< padding bytes */ 550 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 551 }; 552 553 /** 554 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 555 */ 556 union dmub_fw_meta { 557 struct dmub_fw_meta_info info; /**< metadata info */ 558 uint8_t reserved[64]; /**< padding bits */ 559 }; 560 561 #pragma pack(pop) 562 563 //============================================================================== 564 //< DMUB Trace Buffer>================================================================ 565 //============================================================================== 566 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 567 /** 568 * dmub_trace_code_t - firmware trace code, 32-bits 569 */ 570 typedef uint32_t dmub_trace_code_t; 571 572 /** 573 * struct dmcub_trace_buf_entry - Firmware trace entry 574 */ 575 struct dmcub_trace_buf_entry { 576 dmub_trace_code_t trace_code; /**< trace code for the event */ 577 uint32_t tick_count; /**< the tick count at time of trace */ 578 uint32_t param0; /**< trace defined parameter 0 */ 579 uint32_t param1; /**< trace defined parameter 1 */ 580 }; 581 #endif 582 583 //============================================================================== 584 //< DMUB_STATUS>================================================================ 585 //============================================================================== 586 587 /** 588 * DMCUB scratch registers can be used to determine firmware status. 589 * Current scratch register usage is as follows: 590 * 591 * SCRATCH0: FW Boot Status register 592 * SCRATCH5: LVTMA Status Register 593 * SCRATCH15: FW Boot Options register 594 */ 595 596 /** 597 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 598 */ 599 union dmub_fw_boot_status { 600 struct { 601 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 602 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 603 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 604 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 605 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 606 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 607 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 608 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 609 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 610 } bits; /**< status bits */ 611 uint32_t all; /**< 32-bit access to status bits */ 612 }; 613 614 /** 615 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 616 */ 617 enum dmub_fw_boot_status_bit { 618 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 619 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 620 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 621 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 622 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 623 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 624 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 625 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 626 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 627 }; 628 629 /* Register bit definition for SCRATCH5 */ 630 union dmub_lvtma_status { 631 struct { 632 uint32_t psp_ok : 1; 633 uint32_t edp_on : 1; 634 uint32_t reserved : 30; 635 } bits; 636 uint32_t all; 637 }; 638 639 enum dmub_lvtma_status_bit { 640 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 641 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 642 }; 643 644 enum dmub_ips_disable_type { 645 DMUB_IPS_ENABLE = 0, 646 DMUB_IPS_DISABLE_ALL = 1, 647 DMUB_IPS_DISABLE_IPS1 = 2, 648 DMUB_IPS_DISABLE_IPS2 = 3, 649 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 650 DMUB_IPS_DISABLE_DYNAMIC = 5, 651 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 652 }; 653 654 #define DMUB_IPS1_ALLOW_MASK 0x00000001 655 #define DMUB_IPS2_ALLOW_MASK 0x00000002 656 #define DMUB_IPS1_COMMIT_MASK 0x00000004 657 #define DMUB_IPS2_COMMIT_MASK 0x00000008 658 659 /** 660 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 661 */ 662 union dmub_fw_boot_options { 663 struct { 664 uint32_t pemu_env : 1; /**< 1 if PEMU */ 665 uint32_t fpga_env : 1; /**< 1 if FPGA */ 666 uint32_t optimized_init : 1; /**< 1 if optimized init */ 667 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 668 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 669 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 670 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 671 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 672 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 673 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 674 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 675 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 676 uint32_t power_optimization: 1; 677 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 678 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 679 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 680 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 681 uint32_t reserved0: 1; 682 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 683 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 684 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 685 uint32_t ips_disable: 3; /* options to disable ips support*/ 686 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 687 uint32_t reserved : 8; /**< reserved */ 688 } bits; /**< boot bits */ 689 uint32_t all; /**< 32-bit access to bits */ 690 }; 691 692 enum dmub_fw_boot_options_bit { 693 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 694 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 695 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 696 }; 697 698 //============================================================================== 699 //< DMUB_SHARED_STATE>========================================================== 700 //============================================================================== 701 702 /** 703 * Shared firmware state between driver and firmware for lockless communication 704 * in situations where the inbox/outbox may be unavailable. 705 * 706 * Each structure *must* be at most 256-bytes in size. The layout allocation is 707 * described below: 708 * 709 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 710 */ 711 712 /** 713 * enum dmub_shared_state_feature_id - List of shared state features. 714 */ 715 enum dmub_shared_state_feature_id { 716 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 717 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 718 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 719 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 720 }; 721 722 /** 723 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 724 */ 725 union dmub_shared_state_ips_fw_signals { 726 struct { 727 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 728 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 729 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 730 uint32_t detection_required : 1; /**< 1 if detection is required */ 731 uint32_t reserved_bits : 28; /**< Reversed */ 732 } bits; 733 uint32_t all; 734 }; 735 736 /** 737 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 738 */ 739 union dmub_shared_state_ips_driver_signals { 740 struct { 741 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 742 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 743 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 744 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 745 uint32_t reserved_bits : 28; /**< Reversed bits */ 746 } bits; 747 uint32_t all; 748 }; 749 750 /** 751 * IPS FW Version 752 */ 753 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 754 755 /** 756 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 757 */ 758 struct dmub_shared_state_ips_fw { 759 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 760 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 761 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 762 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 763 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 764 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 765 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 766 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 767 }; /* 248-bytes, fixed */ 768 769 /** 770 * IPS Driver Version 771 */ 772 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 773 774 /** 775 * struct dmub_shared_state_ips_driver - Driver state for IPS. 776 */ 777 struct dmub_shared_state_ips_driver { 778 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 779 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 780 }; /* 248-bytes, fixed */ 781 782 /** 783 * enum dmub_shared_state_feature_common - Generic payload. 784 */ 785 struct dmub_shared_state_feature_common { 786 uint32_t padding[62]; 787 }; /* 248-bytes, fixed */ 788 789 /** 790 * enum dmub_shared_state_feature_header - Feature description. 791 */ 792 struct dmub_shared_state_feature_header { 793 uint16_t id; /**< Feature ID */ 794 uint16_t version; /**< Feature version */ 795 uint32_t reserved; /**< Reserved bytes. */ 796 }; /* 8 bytes, fixed */ 797 798 /** 799 * struct dmub_shared_state_feature_block - Feature block. 800 */ 801 struct dmub_shared_state_feature_block { 802 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 803 union dmub_shared_feature_state_union { 804 struct dmub_shared_state_feature_common common; /**< Generic data */ 805 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 806 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 807 } data; /**< Shared state data. */ 808 }; /* 256-bytes, fixed */ 809 810 /** 811 * Shared state size in bytes. 812 */ 813 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 814 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 815 816 //============================================================================== 817 //</DMUB_STATUS>================================================================ 818 //============================================================================== 819 //< DMUB_VBIOS>================================================================= 820 //============================================================================== 821 822 /* 823 * enum dmub_cmd_vbios_type - VBIOS commands. 824 * 825 * Command IDs should be treated as stable ABI. 826 * Do not reuse or modify IDs. 827 */ 828 enum dmub_cmd_vbios_type { 829 /** 830 * Configures the DIG encoder. 831 */ 832 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 833 /** 834 * Controls the PHY. 835 */ 836 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 837 /** 838 * Sets the pixel clock/symbol clock. 839 */ 840 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 841 /** 842 * Enables or disables power gating. 843 */ 844 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 845 /** 846 * Controls embedded panels. 847 */ 848 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 849 /** 850 * Query DP alt status on a transmitter. 851 */ 852 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 853 /** 854 * Control PHY FSM 855 */ 856 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 857 /** 858 * Controls domain power gating 859 */ 860 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 861 }; 862 863 //============================================================================== 864 //</DMUB_VBIOS>================================================================= 865 //============================================================================== 866 //< DMUB_GPINT>================================================================= 867 //============================================================================== 868 869 /** 870 * The shifts and masks below may alternatively be used to format and read 871 * the command register bits. 872 */ 873 874 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 875 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 876 877 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 878 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 879 880 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 881 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 882 883 /** 884 * Command responses. 885 */ 886 887 /** 888 * Return response for DMUB_GPINT__STOP_FW command. 889 */ 890 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 891 892 /** 893 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 894 */ 895 union dmub_gpint_data_register { 896 struct { 897 uint32_t param : 16; /**< 16-bit parameter */ 898 uint32_t command_code : 12; /**< GPINT command */ 899 uint32_t status : 4; /**< Command status bit */ 900 } bits; /**< GPINT bit access */ 901 uint32_t all; /**< GPINT 32-bit access */ 902 }; 903 904 /* 905 * enum dmub_gpint_command - GPINT command to DMCUB FW 906 * 907 * Command IDs should be treated as stable ABI. 908 * Do not reuse or modify IDs. 909 */ 910 enum dmub_gpint_command { 911 /** 912 * Invalid command, ignored. 913 */ 914 DMUB_GPINT__INVALID_COMMAND = 0, 915 /** 916 * DESC: Queries the firmware version. 917 * RETURN: Firmware version. 918 */ 919 DMUB_GPINT__GET_FW_VERSION = 1, 920 /** 921 * DESC: Halts the firmware. 922 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 923 */ 924 DMUB_GPINT__STOP_FW = 2, 925 /** 926 * DESC: Get PSR state from FW. 927 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 928 */ 929 DMUB_GPINT__GET_PSR_STATE = 7, 930 /** 931 * DESC: Notifies DMCUB of the currently active streams. 932 * ARGS: Stream mask, 1 bit per active stream index. 933 */ 934 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 935 /** 936 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 937 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 938 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 939 * RETURN: PSR residency in milli-percent. 940 */ 941 DMUB_GPINT__PSR_RESIDENCY = 9, 942 943 /** 944 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 945 */ 946 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 947 948 /** 949 * DESC: Get REPLAY state from FW. 950 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 951 */ 952 DMUB_GPINT__GET_REPLAY_STATE = 13, 953 954 /** 955 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 956 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 957 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 958 * RETURN: REPLAY residency in milli-percent. 959 */ 960 DMUB_GPINT__REPLAY_RESIDENCY = 14, 961 962 /** 963 * DESC: Copy bounding box to the host. 964 * ARGS: Version of bounding box to copy 965 * RETURN: Result of copying bounding box 966 */ 967 DMUB_GPINT__BB_COPY = 96, 968 969 /** 970 * DESC: Updates the host addresses bit48~bit63 for bounding box. 971 * ARGS: The word3 for the 64 bit address 972 */ 973 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 974 975 /** 976 * DESC: Updates the host addresses bit32~bit47 for bounding box. 977 * ARGS: The word2 for the 64 bit address 978 */ 979 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 980 981 /** 982 * DESC: Updates the host addresses bit16~bit31 for bounding box. 983 * ARGS: The word1 for the 64 bit address 984 */ 985 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 986 987 /** 988 * DESC: Updates the host addresses bit0~bit15 for bounding box. 989 * ARGS: The word0 for the 64 bit address 990 */ 991 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 992 993 /** 994 * DESC: Updates the trace buffer lower 32-bit mask. 995 * ARGS: The new mask 996 * RETURN: Lower 32-bit mask. 997 */ 998 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 999 1000 /** 1001 * DESC: Updates the trace buffer mask bit0~bit15. 1002 * ARGS: The new mask 1003 * RETURN: Lower 32-bit mask. 1004 */ 1005 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1006 1007 /** 1008 * DESC: Updates the trace buffer mask bit16~bit31. 1009 * ARGS: The new mask 1010 * RETURN: Lower 32-bit mask. 1011 */ 1012 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1013 1014 /** 1015 * DESC: Updates the trace buffer mask bit32~bit47. 1016 * ARGS: The new mask 1017 * RETURN: Lower 32-bit mask. 1018 */ 1019 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1020 1021 /** 1022 * DESC: Updates the trace buffer mask bit48~bit63. 1023 * ARGS: The new mask 1024 * RETURN: Lower 32-bit mask. 1025 */ 1026 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1027 1028 /** 1029 * DESC: Read the trace buffer mask bi0~bit15. 1030 */ 1031 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1032 1033 /** 1034 * DESC: Read the trace buffer mask bit16~bit31. 1035 */ 1036 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1037 1038 /** 1039 * DESC: Read the trace buffer mask bi32~bit47. 1040 */ 1041 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1042 1043 /** 1044 * DESC: Updates the trace buffer mask bit32~bit63. 1045 */ 1046 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1047 1048 /** 1049 * DESC: Enable measurements for various task duration 1050 * ARGS: 0 - Disable measurement 1051 * 1 - Enable measurement 1052 */ 1053 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1054 }; 1055 1056 /** 1057 * INBOX0 generic command definition 1058 */ 1059 union dmub_inbox0_cmd_common { 1060 struct { 1061 uint32_t command_code: 8; /**< INBOX0 command code */ 1062 uint32_t param: 24; /**< 24-bit parameter */ 1063 } bits; 1064 uint32_t all; 1065 }; 1066 1067 /** 1068 * INBOX0 hw_lock command definition 1069 */ 1070 union dmub_inbox0_cmd_lock_hw { 1071 struct { 1072 uint32_t command_code: 8; 1073 1074 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1075 uint32_t hw_lock_client: 2; 1076 1077 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1078 uint32_t otg_inst: 3; 1079 uint32_t opp_inst: 3; 1080 uint32_t dig_inst: 3; 1081 1082 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1083 uint32_t lock_pipe: 1; 1084 uint32_t lock_cursor: 1; 1085 uint32_t lock_dig: 1; 1086 uint32_t triple_buffer_lock: 1; 1087 1088 uint32_t lock: 1; /**< Lock */ 1089 uint32_t should_release: 1; /**< Release */ 1090 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1091 } bits; 1092 uint32_t all; 1093 }; 1094 1095 union dmub_inbox0_data_register { 1096 union dmub_inbox0_cmd_common inbox0_cmd_common; 1097 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1098 }; 1099 1100 enum dmub_inbox0_command { 1101 /** 1102 * DESC: Invalid command, ignored. 1103 */ 1104 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1105 /** 1106 * DESC: Notification to acquire/release HW lock 1107 * ARGS: 1108 */ 1109 DMUB_INBOX0_CMD__HW_LOCK = 1, 1110 }; 1111 //============================================================================== 1112 //</DMUB_GPINT>================================================================= 1113 //============================================================================== 1114 //< DMUB_CMD>=================================================================== 1115 //============================================================================== 1116 1117 /** 1118 * Size in bytes of each DMUB command. 1119 */ 1120 #define DMUB_RB_CMD_SIZE 64 1121 1122 /** 1123 * Maximum number of items in the DMUB ringbuffer. 1124 */ 1125 #define DMUB_RB_MAX_ENTRY 128 1126 1127 /** 1128 * Ringbuffer size in bytes. 1129 */ 1130 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1131 1132 /** 1133 * REG_SET mask for reg offload. 1134 */ 1135 #define REG_SET_MASK 0xFFFF 1136 1137 /* 1138 * enum dmub_cmd_type - DMUB inbox command. 1139 * 1140 * Command IDs should be treated as stable ABI. 1141 * Do not reuse or modify IDs. 1142 */ 1143 enum dmub_cmd_type { 1144 /** 1145 * Invalid command. 1146 */ 1147 DMUB_CMD__NULL = 0, 1148 /** 1149 * Read modify write register sequence offload. 1150 */ 1151 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1152 /** 1153 * Field update register sequence offload. 1154 */ 1155 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1156 /** 1157 * Burst write sequence offload. 1158 */ 1159 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1160 /** 1161 * Reg wait sequence offload. 1162 */ 1163 DMUB_CMD__REG_REG_WAIT = 4, 1164 /** 1165 * Workaround to avoid HUBP underflow during NV12 playback. 1166 */ 1167 DMUB_CMD__PLAT_54186_WA = 5, 1168 /** 1169 * Command type used to query FW feature caps. 1170 */ 1171 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1172 /** 1173 * Command type used to get visual confirm color. 1174 */ 1175 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1176 /** 1177 * Command type used for all PSR commands. 1178 */ 1179 DMUB_CMD__PSR = 64, 1180 /** 1181 * Command type used for all MALL commands. 1182 */ 1183 DMUB_CMD__MALL = 65, 1184 /** 1185 * Command type used for all ABM commands. 1186 */ 1187 DMUB_CMD__ABM = 66, 1188 /** 1189 * Command type used to update dirty rects in FW. 1190 */ 1191 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1192 /** 1193 * Command type used to update cursor info in FW. 1194 */ 1195 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1196 /** 1197 * Command type used for HW locking in FW. 1198 */ 1199 DMUB_CMD__HW_LOCK = 69, 1200 /** 1201 * Command type used to access DP AUX. 1202 */ 1203 DMUB_CMD__DP_AUX_ACCESS = 70, 1204 /** 1205 * Command type used for OUTBOX1 notification enable 1206 */ 1207 DMUB_CMD__OUTBOX1_ENABLE = 71, 1208 1209 /** 1210 * Command type used for all idle optimization commands. 1211 */ 1212 DMUB_CMD__IDLE_OPT = 72, 1213 /** 1214 * Command type used for all clock manager commands. 1215 */ 1216 DMUB_CMD__CLK_MGR = 73, 1217 /** 1218 * Command type used for all panel control commands. 1219 */ 1220 DMUB_CMD__PANEL_CNTL = 74, 1221 1222 /** 1223 * Command type used for all CAB commands. 1224 */ 1225 DMUB_CMD__CAB_FOR_SS = 75, 1226 1227 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1228 1229 /** 1230 * Command type used for interfacing with DPIA. 1231 */ 1232 DMUB_CMD__DPIA = 77, 1233 /** 1234 * Command type used for EDID CEA parsing 1235 */ 1236 DMUB_CMD__EDID_CEA = 79, 1237 /** 1238 * Command type used for getting usbc cable ID 1239 */ 1240 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1241 /** 1242 * Command type used to query HPD state. 1243 */ 1244 DMUB_CMD__QUERY_HPD_STATE = 82, 1245 /** 1246 * Command type used for all VBIOS interface commands. 1247 */ 1248 /** 1249 * Command type used for all REPLAY commands. 1250 */ 1251 DMUB_CMD__REPLAY = 83, 1252 1253 /** 1254 * Command type used for all SECURE_DISPLAY commands. 1255 */ 1256 DMUB_CMD__SECURE_DISPLAY = 85, 1257 1258 /** 1259 * Command type used to set DPIA HPD interrupt state 1260 */ 1261 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1262 1263 /** 1264 * Command type used for all PSP commands. 1265 */ 1266 DMUB_CMD__PSP = 88, 1267 1268 DMUB_CMD__VBIOS = 128, 1269 }; 1270 1271 /** 1272 * enum dmub_out_cmd_type - DMUB outbox commands. 1273 */ 1274 enum dmub_out_cmd_type { 1275 /** 1276 * Invalid outbox command, ignored. 1277 */ 1278 DMUB_OUT_CMD__NULL = 0, 1279 /** 1280 * Command type used for DP AUX Reply data notification 1281 */ 1282 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1283 /** 1284 * Command type used for DP HPD event notification 1285 */ 1286 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1287 /** 1288 * Command type used for SET_CONFIG Reply notification 1289 */ 1290 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1291 /** 1292 * Command type used for USB4 DPIA notification 1293 */ 1294 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1295 /** 1296 * Command type used for HPD redetect notification 1297 */ 1298 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1299 }; 1300 1301 /* DMUB_CMD__DPIA command sub-types. */ 1302 enum dmub_cmd_dpia_type { 1303 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1304 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1305 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1306 }; 1307 1308 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1309 enum dmub_cmd_dpia_notification_type { 1310 DPIA_NOTIFY__BW_ALLOCATION = 0, 1311 }; 1312 1313 #pragma pack(push, 1) 1314 1315 /** 1316 * struct dmub_cmd_header - Common command header fields. 1317 */ 1318 struct dmub_cmd_header { 1319 unsigned int type : 8; /**< command type */ 1320 unsigned int sub_type : 8; /**< command sub type */ 1321 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1322 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1323 unsigned int reserved0 : 6; /**< reserved bits */ 1324 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1325 unsigned int reserved1 : 2; /**< reserved bits */ 1326 }; 1327 1328 /* 1329 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1330 * 1331 * 60 payload bytes can hold up to 5 sets of read modify writes, 1332 * each take 3 dwords. 1333 * 1334 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1335 * 1336 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1337 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1338 */ 1339 struct dmub_cmd_read_modify_write_sequence { 1340 uint32_t addr; /**< register address */ 1341 uint32_t modify_mask; /**< modify mask */ 1342 uint32_t modify_value; /**< modify value */ 1343 }; 1344 1345 /** 1346 * Maximum number of ops in read modify write sequence. 1347 */ 1348 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1349 1350 /** 1351 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1352 */ 1353 struct dmub_rb_cmd_read_modify_write { 1354 struct dmub_cmd_header header; /**< command header */ 1355 /** 1356 * Read modify write sequence. 1357 */ 1358 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1359 }; 1360 1361 /* 1362 * Update a register with specified masks and values sequeunce 1363 * 1364 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1365 * 1366 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1367 * 1368 * 1369 * USE CASE: 1370 * 1. auto-increment register where additional read would update pointer and produce wrong result 1371 * 2. toggle a bit without read in the middle 1372 */ 1373 1374 struct dmub_cmd_reg_field_update_sequence { 1375 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1376 uint32_t modify_value; /**< value to update with */ 1377 }; 1378 1379 /** 1380 * Maximum number of ops in field update sequence. 1381 */ 1382 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1383 1384 /** 1385 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1386 */ 1387 struct dmub_rb_cmd_reg_field_update_sequence { 1388 struct dmub_cmd_header header; /**< command header */ 1389 uint32_t addr; /**< register address */ 1390 /** 1391 * Field update sequence. 1392 */ 1393 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1394 }; 1395 1396 1397 /** 1398 * Maximum number of burst write values. 1399 */ 1400 #define DMUB_BURST_WRITE_VALUES__MAX 14 1401 1402 /* 1403 * struct dmub_rb_cmd_burst_write - Burst write 1404 * 1405 * support use case such as writing out LUTs. 1406 * 1407 * 60 payload bytes can hold up to 14 values to write to given address 1408 * 1409 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1410 */ 1411 struct dmub_rb_cmd_burst_write { 1412 struct dmub_cmd_header header; /**< command header */ 1413 uint32_t addr; /**< register start address */ 1414 /** 1415 * Burst write register values. 1416 */ 1417 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1418 }; 1419 1420 /** 1421 * struct dmub_rb_cmd_common - Common command header 1422 */ 1423 struct dmub_rb_cmd_common { 1424 struct dmub_cmd_header header; /**< command header */ 1425 /** 1426 * Padding to RB_CMD_SIZE 1427 */ 1428 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1429 }; 1430 1431 /** 1432 * struct dmub_cmd_reg_wait_data - Register wait data 1433 */ 1434 struct dmub_cmd_reg_wait_data { 1435 uint32_t addr; /**< Register address */ 1436 uint32_t mask; /**< Mask for register bits */ 1437 uint32_t condition_field_value; /**< Value to wait for */ 1438 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1439 }; 1440 1441 /** 1442 * struct dmub_rb_cmd_reg_wait - Register wait command 1443 */ 1444 struct dmub_rb_cmd_reg_wait { 1445 struct dmub_cmd_header header; /**< Command header */ 1446 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1447 }; 1448 1449 /** 1450 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1451 * 1452 * Reprograms surface parameters to avoid underflow. 1453 */ 1454 struct dmub_cmd_PLAT_54186_wa { 1455 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1456 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1457 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1458 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1459 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1460 struct { 1461 uint32_t hubp_inst : 4; /**< HUBP instance */ 1462 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1463 uint32_t immediate :1; /**< Immediate flip */ 1464 uint32_t vmid : 4; /**< VMID */ 1465 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1466 uint32_t reserved : 21; /**< Reserved */ 1467 } flip_params; /**< Pageflip parameters */ 1468 uint32_t reserved[9]; /**< Reserved bits */ 1469 }; 1470 1471 /** 1472 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1473 */ 1474 struct dmub_rb_cmd_PLAT_54186_wa { 1475 struct dmub_cmd_header header; /**< Command header */ 1476 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1477 }; 1478 1479 /** 1480 * enum dmub_cmd_mall_type - MALL commands 1481 */ 1482 enum dmub_cmd_mall_type { 1483 /** 1484 * Allows display refresh from MALL. 1485 */ 1486 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1487 /** 1488 * Disallows display refresh from MALL. 1489 */ 1490 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1491 /** 1492 * Cursor copy for MALL. 1493 */ 1494 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1495 /** 1496 * Controls DF requests. 1497 */ 1498 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1499 }; 1500 1501 /** 1502 * struct dmub_rb_cmd_mall - MALL command data. 1503 */ 1504 struct dmub_rb_cmd_mall { 1505 struct dmub_cmd_header header; /**< Common command header */ 1506 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1507 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1508 uint32_t tmr_delay; /**< Timer delay */ 1509 uint32_t tmr_scale; /**< Timer scale */ 1510 uint16_t cursor_width; /**< Cursor width in pixels */ 1511 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1512 uint16_t cursor_height; /**< Cursor height in pixels */ 1513 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1514 uint8_t debug_bits; /**< Debug bits */ 1515 1516 uint8_t reserved1; /**< Reserved bits */ 1517 uint8_t reserved2; /**< Reserved bits */ 1518 }; 1519 1520 /** 1521 * enum dmub_cmd_cab_type - CAB command data. 1522 */ 1523 enum dmub_cmd_cab_type { 1524 /** 1525 * No idle optimizations (i.e. no CAB) 1526 */ 1527 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1528 /** 1529 * No DCN requests for memory 1530 */ 1531 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1532 /** 1533 * Fit surfaces in CAB (i.e. CAB enable) 1534 */ 1535 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1536 /** 1537 * Do not fit surfaces in CAB (i.e. no CAB) 1538 */ 1539 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1540 }; 1541 1542 /** 1543 * struct dmub_rb_cmd_cab - CAB command data. 1544 */ 1545 struct dmub_rb_cmd_cab_for_ss { 1546 struct dmub_cmd_header header; 1547 uint8_t cab_alloc_ways; /* total number of ways */ 1548 uint8_t debug_bits; /* debug bits */ 1549 }; 1550 1551 /** 1552 * Enum for indicating which MCLK switch mode per pipe 1553 */ 1554 enum mclk_switch_mode { 1555 NONE = 0, 1556 FPO = 1, 1557 SUBVP = 2, 1558 VBLANK = 3, 1559 }; 1560 1561 /* Per pipe struct which stores the MCLK switch mode 1562 * data to be sent to DMUB. 1563 * Named "v2" for now -- once FPO and SUBVP are fully merged 1564 * the type name can be updated 1565 */ 1566 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1567 union { 1568 struct { 1569 uint32_t pix_clk_100hz; 1570 uint16_t main_vblank_start; 1571 uint16_t main_vblank_end; 1572 uint16_t mall_region_lines; 1573 uint16_t prefetch_lines; 1574 uint16_t prefetch_to_mall_start_lines; 1575 uint16_t processing_delay_lines; 1576 uint16_t htotal; // required to calculate line time for multi-display cases 1577 uint16_t vtotal; 1578 uint8_t main_pipe_index; 1579 uint8_t phantom_pipe_index; 1580 /* Since the microschedule is calculated in terms of OTG lines, 1581 * include any scaling factors to make sure when we get accurate 1582 * conversion when programming MALL_START_LINE (which is in terms 1583 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1584 * is 1/2 (numerator = 1, denominator = 2). 1585 */ 1586 uint8_t scale_factor_numerator; 1587 uint8_t scale_factor_denominator; 1588 uint8_t is_drr; 1589 uint8_t main_split_pipe_index; 1590 uint8_t phantom_split_pipe_index; 1591 } subvp_data; 1592 1593 struct { 1594 uint32_t pix_clk_100hz; 1595 uint16_t vblank_start; 1596 uint16_t vblank_end; 1597 uint16_t vstartup_start; 1598 uint16_t vtotal; 1599 uint16_t htotal; 1600 uint8_t vblank_pipe_index; 1601 uint8_t padding[1]; 1602 struct { 1603 uint8_t drr_in_use; 1604 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1605 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1606 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1607 uint8_t use_ramping; // Use ramping or not 1608 uint8_t drr_vblank_start_margin; 1609 } drr_info; // DRR considered as part of SubVP + VBLANK case 1610 } vblank_data; 1611 } pipe_config; 1612 1613 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1614 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1615 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1616 */ 1617 uint8_t mode; // enum mclk_switch_mode 1618 }; 1619 1620 /** 1621 * Config data for Sub-VP and FPO 1622 * Named "v2" for now -- once FPO and SUBVP are fully merged 1623 * the type name can be updated 1624 */ 1625 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1626 uint16_t watermark_a_cache; 1627 uint8_t vertical_int_margin_us; 1628 uint8_t pstate_allow_width_us; 1629 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1630 }; 1631 1632 /** 1633 * DMUB rb command definition for Sub-VP and FPO 1634 * Named "v2" for now -- once FPO and SUBVP are fully merged 1635 * the type name can be updated 1636 */ 1637 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1638 struct dmub_cmd_header header; 1639 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1640 }; 1641 1642 struct dmub_flip_addr_info { 1643 uint32_t surf_addr_lo; 1644 uint32_t surf_addr_c_lo; 1645 uint32_t meta_addr_lo; 1646 uint32_t meta_addr_c_lo; 1647 uint16_t surf_addr_hi; 1648 uint16_t surf_addr_c_hi; 1649 uint16_t meta_addr_hi; 1650 uint16_t meta_addr_c_hi; 1651 }; 1652 1653 struct dmub_fams2_flip_info { 1654 union { 1655 struct { 1656 uint8_t is_immediate: 1; 1657 } bits; 1658 uint8_t all; 1659 } config; 1660 uint8_t otg_inst; 1661 uint8_t pipe_mask; 1662 uint8_t pad; 1663 struct dmub_flip_addr_info addr_info; 1664 }; 1665 1666 struct dmub_rb_cmd_fams2_flip { 1667 struct dmub_cmd_header header; 1668 struct dmub_fams2_flip_info flip_info; 1669 }; 1670 1671 struct dmub_optc_state_v2 { 1672 uint32_t v_total_min; 1673 uint32_t v_total_max; 1674 uint32_t v_total_mid; 1675 uint32_t v_total_mid_frame_num; 1676 uint8_t program_manual_trigger; 1677 uint8_t tg_inst; 1678 uint8_t pad[2]; 1679 }; 1680 1681 struct dmub_optc_position { 1682 uint32_t vpos; 1683 uint32_t hpos; 1684 uint32_t frame; 1685 }; 1686 1687 struct dmub_rb_cmd_fams2_drr_update { 1688 struct dmub_cmd_header header; 1689 struct dmub_optc_state_v2 dmub_optc_state_req; 1690 }; 1691 1692 /* HW and FW global configuration data for FAMS2 */ 1693 /* FAMS2 types and structs */ 1694 enum fams2_stream_type { 1695 FAMS2_STREAM_TYPE_NONE = 0, 1696 FAMS2_STREAM_TYPE_VBLANK = 1, 1697 FAMS2_STREAM_TYPE_VACTIVE = 2, 1698 FAMS2_STREAM_TYPE_DRR = 3, 1699 FAMS2_STREAM_TYPE_SUBVP = 4, 1700 }; 1701 1702 /* dynamic stream state */ 1703 struct dmub_fams2_legacy_stream_dynamic_state { 1704 uint8_t force_allow_at_vblank; 1705 uint8_t pad[3]; 1706 }; 1707 1708 struct dmub_fams2_subvp_stream_dynamic_state { 1709 uint16_t viewport_start_hubp_vline; 1710 uint16_t viewport_height_hubp_vlines; 1711 uint16_t viewport_start_c_hubp_vline; 1712 uint16_t viewport_height_c_hubp_vlines; 1713 uint16_t phantom_viewport_height_hubp_vlines; 1714 uint16_t phantom_viewport_height_c_hubp_vlines; 1715 uint16_t microschedule_start_otg_vline; 1716 uint16_t mall_start_otg_vline; 1717 uint16_t mall_start_hubp_vline; 1718 uint16_t mall_start_c_hubp_vline; 1719 uint8_t force_allow_at_vblank_only; 1720 uint8_t pad[3]; 1721 }; 1722 1723 struct dmub_fams2_drr_stream_dynamic_state { 1724 uint16_t stretched_vtotal; 1725 uint8_t use_cur_vtotal; 1726 uint8_t pad; 1727 }; 1728 1729 struct dmub_fams2_stream_dynamic_state { 1730 uint64_t ref_tick; 1731 uint32_t cur_vtotal; 1732 uint16_t adjusted_allow_end_otg_vline; 1733 uint8_t pad[2]; 1734 struct dmub_optc_position ref_otg_pos; 1735 struct dmub_optc_position target_otg_pos; 1736 union { 1737 struct dmub_fams2_legacy_stream_dynamic_state legacy; 1738 struct dmub_fams2_subvp_stream_dynamic_state subvp; 1739 struct dmub_fams2_drr_stream_dynamic_state drr; 1740 } sub_state; 1741 }; 1742 1743 /* static stream state */ 1744 struct dmub_fams2_legacy_stream_static_state { 1745 uint8_t vactive_det_fill_delay_otg_vlines; 1746 uint8_t programming_delay_otg_vlines; 1747 }; 1748 1749 struct dmub_fams2_subvp_stream_static_state { 1750 uint16_t vratio_numerator; 1751 uint16_t vratio_denominator; 1752 uint16_t phantom_vtotal; 1753 uint16_t phantom_vactive; 1754 union { 1755 struct { 1756 uint8_t is_multi_planar : 1; 1757 uint8_t is_yuv420 : 1; 1758 } bits; 1759 uint8_t all; 1760 } config; 1761 uint8_t programming_delay_otg_vlines; 1762 uint8_t prefetch_to_mall_otg_vlines; 1763 uint8_t phantom_otg_inst; 1764 uint8_t phantom_pipe_mask; 1765 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1766 }; 1767 1768 struct dmub_fams2_drr_stream_static_state { 1769 uint16_t nom_stretched_vtotal; 1770 uint8_t programming_delay_otg_vlines; 1771 uint8_t only_stretch_if_required; 1772 uint8_t pad[2]; 1773 }; 1774 1775 struct dmub_fams2_stream_static_state { 1776 enum fams2_stream_type type; 1777 uint32_t otg_vline_time_ns; 1778 uint32_t otg_vline_time_ticks; 1779 uint16_t htotal; 1780 uint16_t vtotal; // nominal vtotal 1781 uint16_t vblank_start; 1782 uint16_t vblank_end; 1783 uint16_t max_vtotal; 1784 uint16_t allow_start_otg_vline; 1785 uint16_t allow_end_otg_vline; 1786 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1787 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1788 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 1789 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1790 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1791 union { 1792 struct { 1793 uint8_t is_drr: 1; // stream is DRR enabled 1794 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 1795 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1796 } bits; 1797 uint8_t all; 1798 } config; 1799 uint8_t otg_inst; 1800 uint8_t pipe_mask; // pipe mask for the whole config 1801 uint8_t num_planes; 1802 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1803 uint8_t pad[DMUB_MAX_PLANES % 4]; 1804 union { 1805 struct dmub_fams2_legacy_stream_static_state legacy; 1806 struct dmub_fams2_subvp_stream_static_state subvp; 1807 struct dmub_fams2_drr_stream_static_state drr; 1808 } sub_state; 1809 }; 1810 1811 /** 1812 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 1813 * p-state request to allow latency 1814 */ 1815 enum dmub_fams2_allow_delay_check_mode { 1816 /* No check for request to allow delay */ 1817 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 1818 /* Check for request to allow delay */ 1819 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 1820 /* Check for prepare to allow delay */ 1821 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 1822 }; 1823 1824 union dmub_fams2_global_feature_config { 1825 struct { 1826 uint32_t enable: 1; 1827 uint32_t enable_ppt_check: 1; 1828 uint32_t enable_stall_recovery: 1; 1829 uint32_t enable_debug: 1; 1830 uint32_t enable_offload_flip: 1; 1831 uint32_t enable_visual_confirm: 1; 1832 uint32_t allow_delay_check_mode: 2; 1833 uint32_t reserved: 24; 1834 } bits; 1835 uint32_t all; 1836 }; 1837 1838 struct dmub_cmd_fams2_global_config { 1839 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 1840 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 1841 uint32_t num_streams; 1842 union dmub_fams2_global_feature_config features; 1843 uint32_t recovery_timeout_us; 1844 uint32_t hwfq_flip_programming_delay_us; 1845 }; 1846 1847 union dmub_cmd_fams2_config { 1848 struct dmub_cmd_fams2_global_config global; 1849 struct dmub_fams2_stream_static_state stream; 1850 }; 1851 1852 /** 1853 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 1854 */ 1855 struct dmub_rb_cmd_fams2 { 1856 struct dmub_cmd_header header; 1857 union dmub_cmd_fams2_config config; 1858 }; 1859 1860 /** 1861 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1862 */ 1863 enum dmub_cmd_idle_opt_type { 1864 /** 1865 * DCN hardware restore. 1866 */ 1867 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1868 1869 /** 1870 * DCN hardware save. 1871 */ 1872 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1873 1874 /** 1875 * DCN hardware notify idle. 1876 */ 1877 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1878 }; 1879 1880 /** 1881 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1882 */ 1883 struct dmub_rb_cmd_idle_opt_dcn_restore { 1884 struct dmub_cmd_header header; /**< header */ 1885 }; 1886 1887 /** 1888 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1889 */ 1890 struct dmub_dcn_notify_idle_cntl_data { 1891 uint8_t driver_idle; 1892 uint8_t skip_otg_disable; 1893 uint8_t reserved[58]; 1894 }; 1895 1896 /** 1897 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1898 */ 1899 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1900 struct dmub_cmd_header header; /**< header */ 1901 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1902 }; 1903 1904 /** 1905 * struct dmub_clocks - Clock update notification. 1906 */ 1907 struct dmub_clocks { 1908 uint32_t dispclk_khz; /**< dispclk kHz */ 1909 uint32_t dppclk_khz; /**< dppclk kHz */ 1910 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1911 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1912 }; 1913 1914 /** 1915 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1916 */ 1917 enum dmub_cmd_clk_mgr_type { 1918 /** 1919 * Notify DMCUB of clock update. 1920 */ 1921 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1922 }; 1923 1924 /** 1925 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1926 */ 1927 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1928 struct dmub_cmd_header header; /**< header */ 1929 struct dmub_clocks clocks; /**< clock data */ 1930 }; 1931 1932 /** 1933 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1934 */ 1935 struct dmub_cmd_digx_encoder_control_data { 1936 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1937 }; 1938 1939 /** 1940 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1941 */ 1942 struct dmub_rb_cmd_digx_encoder_control { 1943 struct dmub_cmd_header header; /**< header */ 1944 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1945 }; 1946 1947 /** 1948 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1949 */ 1950 struct dmub_cmd_set_pixel_clock_data { 1951 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1952 }; 1953 1954 /** 1955 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1956 */ 1957 struct dmub_rb_cmd_set_pixel_clock { 1958 struct dmub_cmd_header header; /**< header */ 1959 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1960 }; 1961 1962 /** 1963 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1964 */ 1965 struct dmub_cmd_enable_disp_power_gating_data { 1966 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1967 }; 1968 1969 /** 1970 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1971 */ 1972 struct dmub_rb_cmd_enable_disp_power_gating { 1973 struct dmub_cmd_header header; /**< header */ 1974 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1975 }; 1976 1977 /** 1978 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1979 */ 1980 struct dmub_dig_transmitter_control_data_v1_7 { 1981 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1982 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1983 union { 1984 uint8_t digmode; /**< enum atom_encode_mode_def */ 1985 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1986 } mode_laneset; 1987 uint8_t lanenum; /**< Number of lanes */ 1988 union { 1989 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1990 } symclk_units; 1991 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1992 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1993 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1994 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1995 uint8_t reserved1; /**< For future use */ 1996 uint8_t reserved2[3]; /**< For future use */ 1997 uint32_t reserved3[11]; /**< For future use */ 1998 }; 1999 2000 /** 2001 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2002 */ 2003 union dmub_cmd_dig1_transmitter_control_data { 2004 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2005 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2006 }; 2007 2008 /** 2009 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2010 */ 2011 struct dmub_rb_cmd_dig1_transmitter_control { 2012 struct dmub_cmd_header header; /**< header */ 2013 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2014 }; 2015 2016 /** 2017 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2018 */ 2019 struct dmub_rb_cmd_domain_control_data { 2020 uint8_t inst : 6; /**< DOMAIN instance to control */ 2021 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2022 uint8_t reserved[3]; /**< Reserved for future use */ 2023 }; 2024 2025 /** 2026 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2027 */ 2028 struct dmub_rb_cmd_domain_control { 2029 struct dmub_cmd_header header; /**< header */ 2030 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2031 }; 2032 2033 /** 2034 * DPIA tunnel command parameters. 2035 */ 2036 struct dmub_cmd_dig_dpia_control_data { 2037 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2038 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2039 union { 2040 uint8_t digmode; /** enum atom_encode_mode_def */ 2041 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2042 } mode_laneset; 2043 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2044 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2045 uint8_t hpdsel; /** =0: HPD is not assigned */ 2046 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2047 uint8_t dpia_id; /** Index of DPIA */ 2048 uint8_t fec_rdy : 1; 2049 uint8_t reserved : 7; 2050 uint32_t reserved1; 2051 }; 2052 2053 /** 2054 * DMUB command for DPIA tunnel control. 2055 */ 2056 struct dmub_rb_cmd_dig1_dpia_control { 2057 struct dmub_cmd_header header; 2058 struct dmub_cmd_dig_dpia_control_data dpia_control; 2059 }; 2060 2061 /** 2062 * SET_CONFIG Command Payload 2063 */ 2064 struct set_config_cmd_payload { 2065 uint8_t msg_type; /* set config message type */ 2066 uint8_t msg_data; /* set config message data */ 2067 }; 2068 2069 /** 2070 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2071 */ 2072 struct dmub_cmd_set_config_control_data { 2073 struct set_config_cmd_payload cmd_pkt; 2074 uint8_t instance; /* DPIA instance */ 2075 uint8_t immed_status; /* Immediate status returned in case of error */ 2076 }; 2077 2078 /** 2079 * DMUB command structure for SET_CONFIG command. 2080 */ 2081 struct dmub_rb_cmd_set_config_access { 2082 struct dmub_cmd_header header; /* header */ 2083 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2084 }; 2085 2086 /** 2087 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2088 */ 2089 struct dmub_cmd_mst_alloc_slots_control_data { 2090 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2091 uint8_t instance; /* DPIA instance */ 2092 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2093 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2094 }; 2095 2096 /** 2097 * DMUB command structure for SET_ command. 2098 */ 2099 struct dmub_rb_cmd_set_mst_alloc_slots { 2100 struct dmub_cmd_header header; /* header */ 2101 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2102 }; 2103 2104 /** 2105 * DMUB command structure for DPIA HPD int enable control. 2106 */ 2107 struct dmub_rb_cmd_dpia_hpd_int_enable { 2108 struct dmub_cmd_header header; /* header */ 2109 uint32_t enable; /* dpia hpd interrupt enable */ 2110 }; 2111 2112 /** 2113 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2114 */ 2115 struct dmub_rb_cmd_dpphy_init { 2116 struct dmub_cmd_header header; /**< header */ 2117 uint8_t reserved[60]; /**< reserved bits */ 2118 }; 2119 2120 /** 2121 * enum dp_aux_request_action - DP AUX request command listing. 2122 * 2123 * 4 AUX request command bits are shifted to high nibble. 2124 */ 2125 enum dp_aux_request_action { 2126 /** I2C-over-AUX write request */ 2127 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2128 /** I2C-over-AUX read request */ 2129 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2130 /** I2C-over-AUX write status request */ 2131 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2132 /** I2C-over-AUX write request with MOT=1 */ 2133 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2134 /** I2C-over-AUX read request with MOT=1 */ 2135 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2136 /** I2C-over-AUX write status request with MOT=1 */ 2137 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2138 /** Native AUX write request */ 2139 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2140 /** Native AUX read request */ 2141 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2142 }; 2143 2144 /** 2145 * enum aux_return_code_type - DP AUX process return code listing. 2146 */ 2147 enum aux_return_code_type { 2148 /** AUX process succeeded */ 2149 AUX_RET_SUCCESS = 0, 2150 /** AUX process failed with unknown reason */ 2151 AUX_RET_ERROR_UNKNOWN, 2152 /** AUX process completed with invalid reply */ 2153 AUX_RET_ERROR_INVALID_REPLY, 2154 /** AUX process timed out */ 2155 AUX_RET_ERROR_TIMEOUT, 2156 /** HPD was low during AUX process */ 2157 AUX_RET_ERROR_HPD_DISCON, 2158 /** Failed to acquire AUX engine */ 2159 AUX_RET_ERROR_ENGINE_ACQUIRE, 2160 /** AUX request not supported */ 2161 AUX_RET_ERROR_INVALID_OPERATION, 2162 /** AUX process not available */ 2163 AUX_RET_ERROR_PROTOCOL_ERROR, 2164 }; 2165 2166 /** 2167 * enum aux_channel_type - DP AUX channel type listing. 2168 */ 2169 enum aux_channel_type { 2170 /** AUX thru Legacy DP AUX */ 2171 AUX_CHANNEL_LEGACY_DDC, 2172 /** AUX thru DPIA DP tunneling */ 2173 AUX_CHANNEL_DPIA 2174 }; 2175 2176 /** 2177 * struct aux_transaction_parameters - DP AUX request transaction data 2178 */ 2179 struct aux_transaction_parameters { 2180 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2181 uint8_t action; /**< enum dp_aux_request_action */ 2182 uint8_t length; /**< DP AUX request data length */ 2183 uint8_t reserved; /**< For future use */ 2184 uint32_t address; /**< DP AUX address */ 2185 uint8_t data[16]; /**< DP AUX write data */ 2186 }; 2187 2188 /** 2189 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2190 */ 2191 struct dmub_cmd_dp_aux_control_data { 2192 uint8_t instance; /**< AUX instance or DPIA instance */ 2193 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2194 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2195 uint8_t reserved0; /**< For future use */ 2196 uint16_t timeout; /**< timeout time in us */ 2197 uint16_t reserved1; /**< For future use */ 2198 enum aux_channel_type type; /**< enum aux_channel_type */ 2199 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2200 }; 2201 2202 /** 2203 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2204 */ 2205 struct dmub_rb_cmd_dp_aux_access { 2206 /** 2207 * Command header. 2208 */ 2209 struct dmub_cmd_header header; 2210 /** 2211 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2212 */ 2213 struct dmub_cmd_dp_aux_control_data aux_control; 2214 }; 2215 2216 /** 2217 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2218 */ 2219 struct dmub_rb_cmd_outbox1_enable { 2220 /** 2221 * Command header. 2222 */ 2223 struct dmub_cmd_header header; 2224 /** 2225 * enable: 0x0 -> disable outbox1 notification (default value) 2226 * 0x1 -> enable outbox1 notification 2227 */ 2228 uint32_t enable; 2229 }; 2230 2231 /* DP AUX Reply command - OutBox Cmd */ 2232 /** 2233 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2234 */ 2235 struct aux_reply_data { 2236 /** 2237 * Aux cmd 2238 */ 2239 uint8_t command; 2240 /** 2241 * Aux reply data length (max: 16 bytes) 2242 */ 2243 uint8_t length; 2244 /** 2245 * Alignment only 2246 */ 2247 uint8_t pad[2]; 2248 /** 2249 * Aux reply data 2250 */ 2251 uint8_t data[16]; 2252 }; 2253 2254 /** 2255 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2256 */ 2257 struct aux_reply_control_data { 2258 /** 2259 * Reserved for future use 2260 */ 2261 uint32_t handle; 2262 /** 2263 * Aux Instance 2264 */ 2265 uint8_t instance; 2266 /** 2267 * Aux transaction result: definition in enum aux_return_code_type 2268 */ 2269 uint8_t result; 2270 /** 2271 * Alignment only 2272 */ 2273 uint16_t pad; 2274 }; 2275 2276 /** 2277 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2278 */ 2279 struct dmub_rb_cmd_dp_aux_reply { 2280 /** 2281 * Command header. 2282 */ 2283 struct dmub_cmd_header header; 2284 /** 2285 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2286 */ 2287 struct aux_reply_control_data control; 2288 /** 2289 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2290 */ 2291 struct aux_reply_data reply_data; 2292 }; 2293 2294 /* DP HPD Notify command - OutBox Cmd */ 2295 /** 2296 * DP HPD Type 2297 */ 2298 enum dp_hpd_type { 2299 /** 2300 * Normal DP HPD 2301 */ 2302 DP_HPD = 0, 2303 /** 2304 * DP HPD short pulse 2305 */ 2306 DP_IRQ 2307 }; 2308 2309 /** 2310 * DP HPD Status 2311 */ 2312 enum dp_hpd_status { 2313 /** 2314 * DP_HPD status low 2315 */ 2316 DP_HPD_UNPLUG = 0, 2317 /** 2318 * DP_HPD status high 2319 */ 2320 DP_HPD_PLUG 2321 }; 2322 2323 /** 2324 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2325 */ 2326 struct dp_hpd_data { 2327 /** 2328 * DP HPD instance 2329 */ 2330 uint8_t instance; 2331 /** 2332 * HPD type 2333 */ 2334 uint8_t hpd_type; 2335 /** 2336 * HPD status: only for type: DP_HPD to indicate status 2337 */ 2338 uint8_t hpd_status; 2339 /** 2340 * Alignment only 2341 */ 2342 uint8_t pad; 2343 }; 2344 2345 /** 2346 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2347 */ 2348 struct dmub_rb_cmd_dp_hpd_notify { 2349 /** 2350 * Command header. 2351 */ 2352 struct dmub_cmd_header header; 2353 /** 2354 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2355 */ 2356 struct dp_hpd_data hpd_data; 2357 }; 2358 2359 /** 2360 * Definition of a SET_CONFIG reply from DPOA. 2361 */ 2362 enum set_config_status { 2363 SET_CONFIG_PENDING = 0, 2364 SET_CONFIG_ACK_RECEIVED, 2365 SET_CONFIG_RX_TIMEOUT, 2366 SET_CONFIG_UNKNOWN_ERROR, 2367 }; 2368 2369 /** 2370 * Definition of a set_config reply 2371 */ 2372 struct set_config_reply_control_data { 2373 uint8_t instance; /* DPIA Instance */ 2374 uint8_t status; /* Set Config reply */ 2375 uint16_t pad; /* Alignment */ 2376 }; 2377 2378 /** 2379 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2380 */ 2381 struct dmub_rb_cmd_dp_set_config_reply { 2382 struct dmub_cmd_header header; 2383 struct set_config_reply_control_data set_config_reply_control; 2384 }; 2385 2386 /** 2387 * Definition of a DPIA notification header 2388 */ 2389 struct dpia_notification_header { 2390 uint8_t instance; /**< DPIA Instance */ 2391 uint8_t reserved[3]; 2392 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2393 }; 2394 2395 /** 2396 * Definition of the common data struct of DPIA notification 2397 */ 2398 struct dpia_notification_common { 2399 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2400 - sizeof(struct dpia_notification_header)]; 2401 }; 2402 2403 /** 2404 * Definition of a DPIA notification data 2405 */ 2406 struct dpia_bw_allocation_notify_data { 2407 union { 2408 struct { 2409 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2410 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2411 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2412 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2413 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2414 uint16_t reserved: 11; /**< Reserved */ 2415 } bits; 2416 2417 uint16_t flags; 2418 }; 2419 2420 uint8_t cm_id; /**< CM ID */ 2421 uint8_t group_id; /**< Group ID */ 2422 uint8_t granularity; /**< BW Allocation Granularity */ 2423 uint8_t estimated_bw; /**< Estimated_BW */ 2424 uint8_t allocated_bw; /**< Allocated_BW */ 2425 uint8_t reserved; 2426 }; 2427 2428 /** 2429 * union dpia_notify_data_type - DPIA Notification in Outbox command 2430 */ 2431 union dpia_notification_data { 2432 /** 2433 * DPIA Notification for common data struct 2434 */ 2435 struct dpia_notification_common common_data; 2436 2437 /** 2438 * DPIA Notification for DP BW Allocation support 2439 */ 2440 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2441 }; 2442 2443 /** 2444 * Definition of a DPIA notification payload 2445 */ 2446 struct dpia_notification_payload { 2447 struct dpia_notification_header header; 2448 union dpia_notification_data data; /**< DPIA notification payload data */ 2449 }; 2450 2451 /** 2452 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2453 */ 2454 struct dmub_rb_cmd_dpia_notification { 2455 struct dmub_cmd_header header; /**< DPIA notification header */ 2456 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2457 }; 2458 2459 /** 2460 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2461 */ 2462 struct dmub_cmd_hpd_state_query_data { 2463 uint8_t instance; /**< HPD instance or DPIA instance */ 2464 uint8_t result; /**< For returning HPD state */ 2465 uint16_t pad; /** < Alignment */ 2466 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2467 enum aux_return_code_type status; /**< for returning the status of command */ 2468 }; 2469 2470 /** 2471 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2472 */ 2473 struct dmub_rb_cmd_query_hpd_state { 2474 /** 2475 * Command header. 2476 */ 2477 struct dmub_cmd_header header; 2478 /** 2479 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2480 */ 2481 struct dmub_cmd_hpd_state_query_data data; 2482 }; 2483 2484 /** 2485 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2486 */ 2487 struct dmub_rb_cmd_hpd_sense_notify_data { 2488 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2489 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2490 }; 2491 2492 /** 2493 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2494 */ 2495 struct dmub_rb_cmd_hpd_sense_notify { 2496 struct dmub_cmd_header header; /**< header */ 2497 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2498 }; 2499 2500 /* 2501 * Command IDs should be treated as stable ABI. 2502 * Do not reuse or modify IDs. 2503 */ 2504 2505 /** 2506 * PSR command sub-types. 2507 */ 2508 enum dmub_cmd_psr_type { 2509 /** 2510 * Set PSR version support. 2511 */ 2512 DMUB_CMD__PSR_SET_VERSION = 0, 2513 /** 2514 * Copy driver-calculated parameters to PSR state. 2515 */ 2516 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2517 /** 2518 * Enable PSR. 2519 */ 2520 DMUB_CMD__PSR_ENABLE = 2, 2521 2522 /** 2523 * Disable PSR. 2524 */ 2525 DMUB_CMD__PSR_DISABLE = 3, 2526 2527 /** 2528 * Set PSR level. 2529 * PSR level is a 16-bit value dicated by driver that 2530 * will enable/disable different functionality. 2531 */ 2532 DMUB_CMD__PSR_SET_LEVEL = 4, 2533 2534 /** 2535 * Forces PSR enabled until an explicit PSR disable call. 2536 */ 2537 DMUB_CMD__PSR_FORCE_STATIC = 5, 2538 /** 2539 * Set vtotal in psr active for FreeSync PSR. 2540 */ 2541 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2542 /** 2543 * Set PSR power option 2544 */ 2545 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2546 }; 2547 2548 /** 2549 * Different PSR residency modes. 2550 * Different modes change the definition of PSR residency. 2551 */ 2552 enum psr_residency_mode { 2553 PSR_RESIDENCY_MODE_PHY = 0, 2554 PSR_RESIDENCY_MODE_ALPM, 2555 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2556 /* Do not add below. */ 2557 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2558 }; 2559 2560 enum dmub_cmd_fams_type { 2561 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2562 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2563 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2564 /** 2565 * For SubVP set manual trigger in FW because it 2566 * triggers DRR_UPDATE_PENDING which SubVP relies 2567 * on (for any SubVP cases that use a DRR display) 2568 */ 2569 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2570 DMUB_CMD__FAMS2_CONFIG = 4, 2571 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2572 DMUB_CMD__FAMS2_FLIP = 6, 2573 }; 2574 2575 /** 2576 * PSR versions. 2577 */ 2578 enum psr_version { 2579 /** 2580 * PSR version 1. 2581 */ 2582 PSR_VERSION_1 = 0, 2583 /** 2584 * Freesync PSR SU. 2585 */ 2586 PSR_VERSION_SU_1 = 1, 2587 /** 2588 * PSR not supported. 2589 */ 2590 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2591 }; 2592 2593 /** 2594 * PHY Link rate for DP. 2595 */ 2596 enum phy_link_rate { 2597 /** 2598 * not supported. 2599 */ 2600 PHY_RATE_UNKNOWN = 0, 2601 /** 2602 * Rate_1 (RBR) - 1.62 Gbps/Lane 2603 */ 2604 PHY_RATE_162 = 1, 2605 /** 2606 * Rate_2 - 2.16 Gbps/Lane 2607 */ 2608 PHY_RATE_216 = 2, 2609 /** 2610 * Rate_3 - 2.43 Gbps/Lane 2611 */ 2612 PHY_RATE_243 = 3, 2613 /** 2614 * Rate_4 (HBR) - 2.70 Gbps/Lane 2615 */ 2616 PHY_RATE_270 = 4, 2617 /** 2618 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2619 */ 2620 PHY_RATE_324 = 5, 2621 /** 2622 * Rate_6 - 4.32 Gbps/Lane 2623 */ 2624 PHY_RATE_432 = 6, 2625 /** 2626 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2627 */ 2628 PHY_RATE_540 = 7, 2629 /** 2630 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2631 */ 2632 PHY_RATE_810 = 8, 2633 /** 2634 * UHBR10 - 10.0 Gbps/Lane 2635 */ 2636 PHY_RATE_1000 = 9, 2637 /** 2638 * UHBR13.5 - 13.5 Gbps/Lane 2639 */ 2640 PHY_RATE_1350 = 10, 2641 /** 2642 * UHBR10 - 20.0 Gbps/Lane 2643 */ 2644 PHY_RATE_2000 = 11, 2645 2646 PHY_RATE_675 = 12, 2647 /** 2648 * Rate 12 - 6.75 Gbps/Lane 2649 */ 2650 }; 2651 2652 /** 2653 * enum dmub_phy_fsm_state - PHY FSM states. 2654 * PHY FSM state to transit to during PSR enable/disable. 2655 */ 2656 enum dmub_phy_fsm_state { 2657 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2658 DMUB_PHY_FSM_RESET, 2659 DMUB_PHY_FSM_RESET_RELEASED, 2660 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2661 DMUB_PHY_FSM_INITIALIZED, 2662 DMUB_PHY_FSM_CALIBRATED, 2663 DMUB_PHY_FSM_CALIBRATED_LP, 2664 DMUB_PHY_FSM_CALIBRATED_PG, 2665 DMUB_PHY_FSM_POWER_DOWN, 2666 DMUB_PHY_FSM_PLL_EN, 2667 DMUB_PHY_FSM_TX_EN, 2668 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2669 DMUB_PHY_FSM_FAST_LP, 2670 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2671 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2672 DMUB_PHY_FSM_P2_PLL_OFF, 2673 DMUB_PHY_FSM_P2_PLL_ON, 2674 }; 2675 2676 /** 2677 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2678 */ 2679 struct dmub_cmd_psr_copy_settings_data { 2680 /** 2681 * Flags that can be set by driver to change some PSR behaviour. 2682 */ 2683 union dmub_psr_debug_flags debug; 2684 /** 2685 * 16-bit value dicated by driver that will enable/disable different functionality. 2686 */ 2687 uint16_t psr_level; 2688 /** 2689 * DPP HW instance. 2690 */ 2691 uint8_t dpp_inst; 2692 /** 2693 * MPCC HW instance. 2694 * Not used in dmub fw, 2695 * dmub fw will get active opp by reading odm registers. 2696 */ 2697 uint8_t mpcc_inst; 2698 /** 2699 * OPP HW instance. 2700 * Not used in dmub fw, 2701 * dmub fw will get active opp by reading odm registers. 2702 */ 2703 uint8_t opp_inst; 2704 /** 2705 * OTG HW instance. 2706 */ 2707 uint8_t otg_inst; 2708 /** 2709 * DIG FE HW instance. 2710 */ 2711 uint8_t digfe_inst; 2712 /** 2713 * DIG BE HW instance. 2714 */ 2715 uint8_t digbe_inst; 2716 /** 2717 * DP PHY HW instance. 2718 */ 2719 uint8_t dpphy_inst; 2720 /** 2721 * AUX HW instance. 2722 */ 2723 uint8_t aux_inst; 2724 /** 2725 * Determines if SMU optimzations are enabled/disabled. 2726 */ 2727 uint8_t smu_optimizations_en; 2728 /** 2729 * Unused. 2730 * TODO: Remove. 2731 */ 2732 uint8_t frame_delay; 2733 /** 2734 * If RFB setup time is greater than the total VBLANK time, 2735 * it is not possible for the sink to capture the video frame 2736 * in the same frame the SDP is sent. In this case, 2737 * the frame capture indication bit should be set and an extra 2738 * static frame should be transmitted to the sink. 2739 */ 2740 uint8_t frame_cap_ind; 2741 /** 2742 * Granularity of Y offset supported by sink. 2743 */ 2744 uint8_t su_y_granularity; 2745 /** 2746 * Indicates whether sink should start capturing 2747 * immediately following active scan line, 2748 * or starting with the 2nd active scan line. 2749 */ 2750 uint8_t line_capture_indication; 2751 /** 2752 * Multi-display optimizations are implemented on certain ASICs. 2753 */ 2754 uint8_t multi_disp_optimizations_en; 2755 /** 2756 * The last possible line SDP may be transmitted without violating 2757 * the RFB setup time or entering the active video frame. 2758 */ 2759 uint16_t init_sdp_deadline; 2760 /** 2761 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2762 */ 2763 uint8_t rate_control_caps ; 2764 /* 2765 * Force PSRSU always doing full frame update 2766 */ 2767 uint8_t force_ffu_mode; 2768 /** 2769 * Length of each horizontal line in us. 2770 */ 2771 uint32_t line_time_in_us; 2772 /** 2773 * FEC enable status in driver 2774 */ 2775 uint8_t fec_enable_status; 2776 /** 2777 * FEC re-enable delay when PSR exit. 2778 * unit is 100us, range form 0~255(0xFF). 2779 */ 2780 uint8_t fec_enable_delay_in100us; 2781 /** 2782 * PSR control version. 2783 */ 2784 uint8_t cmd_version; 2785 /** 2786 * Panel Instance. 2787 * Panel instance to identify which psr_state to use 2788 * Currently the support is only for 0 or 1 2789 */ 2790 uint8_t panel_inst; 2791 /* 2792 * DSC enable status in driver 2793 */ 2794 uint8_t dsc_enable_status; 2795 /* 2796 * Use FSM state for PSR power up/down 2797 */ 2798 uint8_t use_phy_fsm; 2799 /** 2800 * frame delay for frame re-lock 2801 */ 2802 uint8_t relock_delay_frame_cnt; 2803 /** 2804 * esd recovery indicate. 2805 */ 2806 uint8_t esd_recovery; 2807 /** 2808 * DSC Slice height. 2809 */ 2810 uint16_t dsc_slice_height; 2811 /** 2812 * Some panels request main link off before xth vertical line 2813 */ 2814 uint16_t poweroff_before_vertical_line; 2815 }; 2816 2817 /** 2818 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2819 */ 2820 struct dmub_rb_cmd_psr_copy_settings { 2821 /** 2822 * Command header. 2823 */ 2824 struct dmub_cmd_header header; 2825 /** 2826 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2827 */ 2828 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2829 }; 2830 2831 /** 2832 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2833 */ 2834 struct dmub_cmd_psr_set_level_data { 2835 /** 2836 * 16-bit value dicated by driver that will enable/disable different functionality. 2837 */ 2838 uint16_t psr_level; 2839 /** 2840 * PSR control version. 2841 */ 2842 uint8_t cmd_version; 2843 /** 2844 * Panel Instance. 2845 * Panel instance to identify which psr_state to use 2846 * Currently the support is only for 0 or 1 2847 */ 2848 uint8_t panel_inst; 2849 }; 2850 2851 /** 2852 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2853 */ 2854 struct dmub_rb_cmd_psr_set_level { 2855 /** 2856 * Command header. 2857 */ 2858 struct dmub_cmd_header header; 2859 /** 2860 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2861 */ 2862 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2863 }; 2864 2865 struct dmub_rb_cmd_psr_enable_data { 2866 /** 2867 * PSR control version. 2868 */ 2869 uint8_t cmd_version; 2870 /** 2871 * Panel Instance. 2872 * Panel instance to identify which psr_state to use 2873 * Currently the support is only for 0 or 1 2874 */ 2875 uint8_t panel_inst; 2876 /** 2877 * Phy state to enter. 2878 * Values to use are defined in dmub_phy_fsm_state 2879 */ 2880 uint8_t phy_fsm_state; 2881 /** 2882 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2883 * Set this using enum phy_link_rate. 2884 * This does not support HDMI/DP2 for now. 2885 */ 2886 uint8_t phy_rate; 2887 }; 2888 2889 /** 2890 * Definition of a DMUB_CMD__PSR_ENABLE command. 2891 * PSR enable/disable is controlled using the sub_type. 2892 */ 2893 struct dmub_rb_cmd_psr_enable { 2894 /** 2895 * Command header. 2896 */ 2897 struct dmub_cmd_header header; 2898 2899 struct dmub_rb_cmd_psr_enable_data data; 2900 }; 2901 2902 /** 2903 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2904 */ 2905 struct dmub_cmd_psr_set_version_data { 2906 /** 2907 * PSR version that FW should implement. 2908 */ 2909 enum psr_version version; 2910 /** 2911 * PSR control version. 2912 */ 2913 uint8_t cmd_version; 2914 /** 2915 * Panel Instance. 2916 * Panel instance to identify which psr_state to use 2917 * Currently the support is only for 0 or 1 2918 */ 2919 uint8_t panel_inst; 2920 /** 2921 * Explicit padding to 4 byte boundary. 2922 */ 2923 uint8_t pad[2]; 2924 }; 2925 2926 /** 2927 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2928 */ 2929 struct dmub_rb_cmd_psr_set_version { 2930 /** 2931 * Command header. 2932 */ 2933 struct dmub_cmd_header header; 2934 /** 2935 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2936 */ 2937 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2938 }; 2939 2940 struct dmub_cmd_psr_force_static_data { 2941 /** 2942 * PSR control version. 2943 */ 2944 uint8_t cmd_version; 2945 /** 2946 * Panel Instance. 2947 * Panel instance to identify which psr_state to use 2948 * Currently the support is only for 0 or 1 2949 */ 2950 uint8_t panel_inst; 2951 /** 2952 * Explicit padding to 4 byte boundary. 2953 */ 2954 uint8_t pad[2]; 2955 }; 2956 2957 /** 2958 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2959 */ 2960 struct dmub_rb_cmd_psr_force_static { 2961 /** 2962 * Command header. 2963 */ 2964 struct dmub_cmd_header header; 2965 /** 2966 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2967 */ 2968 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2969 }; 2970 2971 /** 2972 * PSR SU debug flags. 2973 */ 2974 union dmub_psr_su_debug_flags { 2975 /** 2976 * PSR SU debug flags. 2977 */ 2978 struct { 2979 /** 2980 * Update dirty rect in SW only. 2981 */ 2982 uint8_t update_dirty_rect_only : 1; 2983 /** 2984 * Reset the cursor/plane state before processing the call. 2985 */ 2986 uint8_t reset_state : 1; 2987 } bitfields; 2988 2989 /** 2990 * Union for debug flags. 2991 */ 2992 uint32_t u32All; 2993 }; 2994 2995 /** 2996 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2997 * This triggers a selective update for PSR SU. 2998 */ 2999 struct dmub_cmd_update_dirty_rect_data { 3000 /** 3001 * Dirty rects from OS. 3002 */ 3003 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3004 /** 3005 * PSR SU debug flags. 3006 */ 3007 union dmub_psr_su_debug_flags debug_flags; 3008 /** 3009 * OTG HW instance. 3010 */ 3011 uint8_t pipe_idx; 3012 /** 3013 * Number of dirty rects. 3014 */ 3015 uint8_t dirty_rect_count; 3016 /** 3017 * PSR control version. 3018 */ 3019 uint8_t cmd_version; 3020 /** 3021 * Panel Instance. 3022 * Panel instance to identify which psr_state to use 3023 * Currently the support is only for 0 or 1 3024 */ 3025 uint8_t panel_inst; 3026 /** 3027 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3028 */ 3029 uint16_t coasting_vtotal_high; 3030 /** 3031 * Explicit padding to 4 byte boundary. 3032 */ 3033 uint8_t pad[2]; 3034 }; 3035 3036 /** 3037 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3038 */ 3039 struct dmub_rb_cmd_update_dirty_rect { 3040 /** 3041 * Command header. 3042 */ 3043 struct dmub_cmd_header header; 3044 /** 3045 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3046 */ 3047 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3048 }; 3049 3050 /** 3051 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3052 */ 3053 union dmub_reg_cursor_control_cfg { 3054 struct { 3055 uint32_t cur_enable: 1; 3056 uint32_t reser0: 3; 3057 uint32_t cur_2x_magnify: 1; 3058 uint32_t reser1: 3; 3059 uint32_t mode: 3; 3060 uint32_t reser2: 5; 3061 uint32_t pitch: 2; 3062 uint32_t reser3: 6; 3063 uint32_t line_per_chunk: 5; 3064 uint32_t reser4: 3; 3065 } bits; 3066 uint32_t raw; 3067 }; 3068 struct dmub_cursor_position_cache_hubp { 3069 union dmub_reg_cursor_control_cfg cur_ctl; 3070 union dmub_reg_position_cfg { 3071 struct { 3072 uint32_t cur_x_pos: 16; 3073 uint32_t cur_y_pos: 16; 3074 } bits; 3075 uint32_t raw; 3076 } position; 3077 union dmub_reg_hot_spot_cfg { 3078 struct { 3079 uint32_t hot_x: 16; 3080 uint32_t hot_y: 16; 3081 } bits; 3082 uint32_t raw; 3083 } hot_spot; 3084 union dmub_reg_dst_offset_cfg { 3085 struct { 3086 uint32_t dst_x_offset: 13; 3087 uint32_t reserved: 19; 3088 } bits; 3089 uint32_t raw; 3090 } dst_offset; 3091 }; 3092 3093 union dmub_reg_cur0_control_cfg { 3094 struct { 3095 uint32_t cur0_enable: 1; 3096 uint32_t expansion_mode: 1; 3097 uint32_t reser0: 1; 3098 uint32_t cur0_rom_en: 1; 3099 uint32_t mode: 3; 3100 uint32_t reserved: 25; 3101 } bits; 3102 uint32_t raw; 3103 }; 3104 struct dmub_cursor_position_cache_dpp { 3105 union dmub_reg_cur0_control_cfg cur0_ctl; 3106 }; 3107 struct dmub_cursor_position_cfg { 3108 struct dmub_cursor_position_cache_hubp pHubp; 3109 struct dmub_cursor_position_cache_dpp pDpp; 3110 uint8_t pipe_idx; 3111 /* 3112 * Padding is required. To be 4 Bytes Aligned. 3113 */ 3114 uint8_t padding[3]; 3115 }; 3116 3117 struct dmub_cursor_attribute_cache_hubp { 3118 uint32_t SURFACE_ADDR_HIGH; 3119 uint32_t SURFACE_ADDR; 3120 union dmub_reg_cursor_control_cfg cur_ctl; 3121 union dmub_reg_cursor_size_cfg { 3122 struct { 3123 uint32_t width: 16; 3124 uint32_t height: 16; 3125 } bits; 3126 uint32_t raw; 3127 } size; 3128 union dmub_reg_cursor_settings_cfg { 3129 struct { 3130 uint32_t dst_y_offset: 8; 3131 uint32_t chunk_hdl_adjust: 2; 3132 uint32_t reserved: 22; 3133 } bits; 3134 uint32_t raw; 3135 } settings; 3136 }; 3137 struct dmub_cursor_attribute_cache_dpp { 3138 union dmub_reg_cur0_control_cfg cur0_ctl; 3139 }; 3140 struct dmub_cursor_attributes_cfg { 3141 struct dmub_cursor_attribute_cache_hubp aHubp; 3142 struct dmub_cursor_attribute_cache_dpp aDpp; 3143 }; 3144 3145 struct dmub_cmd_update_cursor_payload0 { 3146 /** 3147 * Cursor dirty rects. 3148 */ 3149 struct dmub_rect cursor_rect; 3150 /** 3151 * PSR SU debug flags. 3152 */ 3153 union dmub_psr_su_debug_flags debug_flags; 3154 /** 3155 * Cursor enable/disable. 3156 */ 3157 uint8_t enable; 3158 /** 3159 * OTG HW instance. 3160 */ 3161 uint8_t pipe_idx; 3162 /** 3163 * PSR control version. 3164 */ 3165 uint8_t cmd_version; 3166 /** 3167 * Panel Instance. 3168 * Panel instance to identify which psr_state to use 3169 * Currently the support is only for 0 or 1 3170 */ 3171 uint8_t panel_inst; 3172 /** 3173 * Cursor Position Register. 3174 * Registers contains Hubp & Dpp modules 3175 */ 3176 struct dmub_cursor_position_cfg position_cfg; 3177 }; 3178 3179 struct dmub_cmd_update_cursor_payload1 { 3180 struct dmub_cursor_attributes_cfg attribute_cfg; 3181 }; 3182 3183 union dmub_cmd_update_cursor_info_data { 3184 struct dmub_cmd_update_cursor_payload0 payload0; 3185 struct dmub_cmd_update_cursor_payload1 payload1; 3186 }; 3187 /** 3188 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3189 */ 3190 struct dmub_rb_cmd_update_cursor_info { 3191 /** 3192 * Command header. 3193 */ 3194 struct dmub_cmd_header header; 3195 /** 3196 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3197 */ 3198 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3199 }; 3200 3201 /** 3202 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3203 */ 3204 struct dmub_cmd_psr_set_vtotal_data { 3205 /** 3206 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3207 */ 3208 uint16_t psr_vtotal_idle; 3209 /** 3210 * PSR control version. 3211 */ 3212 uint8_t cmd_version; 3213 /** 3214 * Panel Instance. 3215 * Panel instance to identify which psr_state to use 3216 * Currently the support is only for 0 or 1 3217 */ 3218 uint8_t panel_inst; 3219 /* 3220 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3221 */ 3222 uint16_t psr_vtotal_su; 3223 /** 3224 * Explicit padding to 4 byte boundary. 3225 */ 3226 uint8_t pad2[2]; 3227 }; 3228 3229 /** 3230 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3231 */ 3232 struct dmub_rb_cmd_psr_set_vtotal { 3233 /** 3234 * Command header. 3235 */ 3236 struct dmub_cmd_header header; 3237 /** 3238 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3239 */ 3240 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3241 }; 3242 3243 /** 3244 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3245 */ 3246 struct dmub_cmd_psr_set_power_opt_data { 3247 /** 3248 * PSR control version. 3249 */ 3250 uint8_t cmd_version; 3251 /** 3252 * Panel Instance. 3253 * Panel instance to identify which psr_state to use 3254 * Currently the support is only for 0 or 1 3255 */ 3256 uint8_t panel_inst; 3257 /** 3258 * Explicit padding to 4 byte boundary. 3259 */ 3260 uint8_t pad[2]; 3261 /** 3262 * PSR power option 3263 */ 3264 uint32_t power_opt; 3265 }; 3266 3267 /** 3268 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3269 */ 3270 struct dmub_rb_cmd_psr_set_power_opt { 3271 /** 3272 * Command header. 3273 */ 3274 struct dmub_cmd_header header; 3275 /** 3276 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3277 */ 3278 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3279 }; 3280 3281 /** 3282 * Definition of Replay Residency GPINT command. 3283 * Bit[0] - Residency mode for Revision 0 3284 * Bit[1] - Enable/Disable state 3285 * Bit[2-3] - Revision number 3286 * Bit[4-7] - Residency mode for Revision 1 3287 * Bit[8] - Panel instance 3288 * Bit[9-15] - Reserved 3289 */ 3290 3291 enum pr_residency_mode { 3292 PR_RESIDENCY_MODE_PHY = 0x0, 3293 PR_RESIDENCY_MODE_ALPM, 3294 PR_RESIDENCY_MODE_IPS2, 3295 PR_RESIDENCY_MODE_FRAME_CNT, 3296 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3297 }; 3298 3299 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3300 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3301 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3302 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3303 3304 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3305 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3306 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3307 3308 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3309 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3310 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3311 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3312 3313 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3314 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3315 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3316 3317 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3318 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3319 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3320 3321 /** 3322 * Definition of a replay_state. 3323 */ 3324 enum replay_state { 3325 REPLAY_STATE_0 = 0x0, 3326 REPLAY_STATE_1 = 0x10, 3327 REPLAY_STATE_1A = 0x11, 3328 REPLAY_STATE_2 = 0x20, 3329 REPLAY_STATE_3 = 0x30, 3330 REPLAY_STATE_3INIT = 0x31, 3331 REPLAY_STATE_4 = 0x40, 3332 REPLAY_STATE_4A = 0x41, 3333 REPLAY_STATE_4B = 0x42, 3334 REPLAY_STATE_4C = 0x43, 3335 REPLAY_STATE_4D = 0x44, 3336 REPLAY_STATE_4B_LOCKED = 0x4A, 3337 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3338 REPLAY_STATE_5 = 0x50, 3339 REPLAY_STATE_5A = 0x51, 3340 REPLAY_STATE_5B = 0x52, 3341 REPLAY_STATE_5A_LOCKED = 0x5A, 3342 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3343 REPLAY_STATE_6 = 0x60, 3344 REPLAY_STATE_6A = 0x61, 3345 REPLAY_STATE_6B = 0x62, 3346 REPLAY_STATE_INVALID = 0xFF, 3347 }; 3348 3349 /** 3350 * Replay command sub-types. 3351 */ 3352 enum dmub_cmd_replay_type { 3353 /** 3354 * Copy driver-calculated parameters to REPLAY state. 3355 */ 3356 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3357 /** 3358 * Enable REPLAY. 3359 */ 3360 DMUB_CMD__REPLAY_ENABLE = 1, 3361 /** 3362 * Set Replay power option. 3363 */ 3364 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3365 /** 3366 * Set coasting vtotal. 3367 */ 3368 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3369 /** 3370 * Set power opt and coasting vtotal. 3371 */ 3372 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3373 /** 3374 * Set disabled iiming sync. 3375 */ 3376 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3377 /** 3378 * Set Residency Frameupdate Timer. 3379 */ 3380 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3381 /** 3382 * Set pseudo vtotal 3383 */ 3384 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3385 /** 3386 * Set adaptive sync sdp enabled 3387 */ 3388 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3389 /** 3390 * Set Replay General command. 3391 */ 3392 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3393 }; 3394 3395 /** 3396 * Replay general command sub-types. 3397 */ 3398 enum dmub_cmd_replay_general_subtype { 3399 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3400 /** 3401 * TODO: For backward compatible, allow new command only. 3402 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3403 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3404 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3405 */ 3406 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3407 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3408 }; 3409 3410 /** 3411 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3412 */ 3413 struct dmub_cmd_replay_copy_settings_data { 3414 /** 3415 * Flags that can be set by driver to change some replay behaviour. 3416 */ 3417 union replay_debug_flags debug; 3418 3419 /** 3420 * @flags: Flags used to determine feature functionality. 3421 */ 3422 union replay_hw_flags flags; 3423 3424 /** 3425 * DPP HW instance. 3426 */ 3427 uint8_t dpp_inst; 3428 /** 3429 * OTG HW instance. 3430 */ 3431 uint8_t otg_inst; 3432 /** 3433 * DIG FE HW instance. 3434 */ 3435 uint8_t digfe_inst; 3436 /** 3437 * DIG BE HW instance. 3438 */ 3439 uint8_t digbe_inst; 3440 /** 3441 * AUX HW instance. 3442 */ 3443 uint8_t aux_inst; 3444 /** 3445 * Panel Instance. 3446 * Panel isntance to identify which psr_state to use 3447 * Currently the support is only for 0 or 1 3448 */ 3449 uint8_t panel_inst; 3450 /** 3451 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3452 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3453 */ 3454 uint8_t pixel_deviation_per_line; 3455 /** 3456 * @max_deviation_line: The max number of deviation line that can keep the timing 3457 * synchronized between the Source and Sink during Replay normal sleep mode. 3458 */ 3459 uint8_t max_deviation_line; 3460 /** 3461 * Length of each horizontal line in ns. 3462 */ 3463 uint32_t line_time_in_ns; 3464 /** 3465 * PHY instance. 3466 */ 3467 uint8_t dpphy_inst; 3468 /** 3469 * Determines if SMU optimzations are enabled/disabled. 3470 */ 3471 uint8_t smu_optimizations_en; 3472 /** 3473 * Determines if timing sync are enabled/disabled. 3474 */ 3475 uint8_t replay_timing_sync_supported; 3476 /* 3477 * Use FSM state for Replay power up/down 3478 */ 3479 uint8_t use_phy_fsm; 3480 }; 3481 3482 /** 3483 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3484 */ 3485 struct dmub_rb_cmd_replay_copy_settings { 3486 /** 3487 * Command header. 3488 */ 3489 struct dmub_cmd_header header; 3490 /** 3491 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3492 */ 3493 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3494 }; 3495 3496 /** 3497 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3498 */ 3499 enum replay_enable { 3500 /** 3501 * Disable REPLAY. 3502 */ 3503 REPLAY_DISABLE = 0, 3504 /** 3505 * Enable REPLAY. 3506 */ 3507 REPLAY_ENABLE = 1, 3508 }; 3509 3510 /** 3511 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3512 */ 3513 struct dmub_rb_cmd_replay_enable_data { 3514 /** 3515 * Replay enable or disable. 3516 */ 3517 uint8_t enable; 3518 /** 3519 * Panel Instance. 3520 * Panel isntance to identify which replay_state to use 3521 * Currently the support is only for 0 or 1 3522 */ 3523 uint8_t panel_inst; 3524 /** 3525 * Phy state to enter. 3526 * Values to use are defined in dmub_phy_fsm_state 3527 */ 3528 uint8_t phy_fsm_state; 3529 /** 3530 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3531 * Set this using enum phy_link_rate. 3532 * This does not support HDMI/DP2 for now. 3533 */ 3534 uint8_t phy_rate; 3535 }; 3536 3537 /** 3538 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3539 * Replay enable/disable is controlled using action in data. 3540 */ 3541 struct dmub_rb_cmd_replay_enable { 3542 /** 3543 * Command header. 3544 */ 3545 struct dmub_cmd_header header; 3546 3547 struct dmub_rb_cmd_replay_enable_data data; 3548 }; 3549 3550 /** 3551 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3552 */ 3553 struct dmub_cmd_replay_set_power_opt_data { 3554 /** 3555 * Panel Instance. 3556 * Panel isntance to identify which replay_state to use 3557 * Currently the support is only for 0 or 1 3558 */ 3559 uint8_t panel_inst; 3560 /** 3561 * Explicit padding to 4 byte boundary. 3562 */ 3563 uint8_t pad[3]; 3564 /** 3565 * REPLAY power option 3566 */ 3567 uint32_t power_opt; 3568 }; 3569 3570 /** 3571 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3572 */ 3573 struct dmub_cmd_replay_set_timing_sync_data { 3574 /** 3575 * Panel Instance. 3576 * Panel isntance to identify which replay_state to use 3577 * Currently the support is only for 0 or 1 3578 */ 3579 uint8_t panel_inst; 3580 /** 3581 * REPLAY set_timing_sync 3582 */ 3583 uint8_t timing_sync_supported; 3584 /** 3585 * Explicit padding to 4 byte boundary. 3586 */ 3587 uint8_t pad[2]; 3588 }; 3589 3590 /** 3591 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3592 */ 3593 struct dmub_cmd_replay_set_pseudo_vtotal { 3594 /** 3595 * Panel Instance. 3596 * Panel isntance to identify which replay_state to use 3597 * Currently the support is only for 0 or 1 3598 */ 3599 uint8_t panel_inst; 3600 /** 3601 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3602 */ 3603 uint16_t vtotal; 3604 /** 3605 * Explicit padding to 4 byte boundary. 3606 */ 3607 uint8_t pad; 3608 }; 3609 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3610 /** 3611 * Panel Instance. 3612 * Panel isntance to identify which replay_state to use 3613 * Currently the support is only for 0 or 1 3614 */ 3615 uint8_t panel_inst; 3616 /** 3617 * enabled: set adaptive sync sdp enabled 3618 */ 3619 uint8_t force_disabled; 3620 3621 uint8_t pad[2]; 3622 }; 3623 struct dmub_cmd_replay_set_general_cmd_data { 3624 /** 3625 * Panel Instance. 3626 * Panel isntance to identify which replay_state to use 3627 * Currently the support is only for 0 or 1 3628 */ 3629 uint8_t panel_inst; 3630 /** 3631 * subtype: replay general cmd sub type 3632 */ 3633 uint8_t subtype; 3634 3635 uint8_t pad[2]; 3636 /** 3637 * config data with param1 and param2 3638 */ 3639 uint32_t param1; 3640 3641 uint32_t param2; 3642 }; 3643 3644 /** 3645 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3646 */ 3647 struct dmub_rb_cmd_replay_set_power_opt { 3648 /** 3649 * Command header. 3650 */ 3651 struct dmub_cmd_header header; 3652 /** 3653 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3654 */ 3655 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3656 }; 3657 3658 /** 3659 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3660 */ 3661 struct dmub_cmd_replay_set_coasting_vtotal_data { 3662 /** 3663 * 16-bit value dicated by driver that indicates the coasting vtotal. 3664 */ 3665 uint16_t coasting_vtotal; 3666 /** 3667 * REPLAY control version. 3668 */ 3669 uint8_t cmd_version; 3670 /** 3671 * Panel Instance. 3672 * Panel isntance to identify which replay_state to use 3673 * Currently the support is only for 0 or 1 3674 */ 3675 uint8_t panel_inst; 3676 /** 3677 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3678 */ 3679 uint16_t coasting_vtotal_high; 3680 /** 3681 * Explicit padding to 4 byte boundary. 3682 */ 3683 uint8_t pad[2]; 3684 }; 3685 3686 /** 3687 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3688 */ 3689 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3690 /** 3691 * Command header. 3692 */ 3693 struct dmub_cmd_header header; 3694 /** 3695 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3696 */ 3697 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3698 }; 3699 3700 /** 3701 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3702 */ 3703 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3704 /** 3705 * Command header. 3706 */ 3707 struct dmub_cmd_header header; 3708 /** 3709 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3710 */ 3711 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3712 /** 3713 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3714 */ 3715 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3716 }; 3717 3718 /** 3719 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3720 */ 3721 struct dmub_rb_cmd_replay_set_timing_sync { 3722 /** 3723 * Command header. 3724 */ 3725 struct dmub_cmd_header header; 3726 /** 3727 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3728 */ 3729 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3730 }; 3731 3732 /** 3733 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3734 */ 3735 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3736 /** 3737 * Command header. 3738 */ 3739 struct dmub_cmd_header header; 3740 /** 3741 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3742 */ 3743 struct dmub_cmd_replay_set_pseudo_vtotal data; 3744 }; 3745 3746 /** 3747 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3748 */ 3749 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3750 /** 3751 * Command header. 3752 */ 3753 struct dmub_cmd_header header; 3754 /** 3755 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3756 */ 3757 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3758 }; 3759 3760 /** 3761 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3762 */ 3763 struct dmub_rb_cmd_replay_set_general_cmd { 3764 /** 3765 * Command header. 3766 */ 3767 struct dmub_cmd_header header; 3768 /** 3769 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3770 */ 3771 struct dmub_cmd_replay_set_general_cmd_data data; 3772 }; 3773 3774 /** 3775 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3776 */ 3777 struct dmub_cmd_replay_frameupdate_timer_data { 3778 /** 3779 * Panel Instance. 3780 * Panel isntance to identify which replay_state to use 3781 * Currently the support is only for 0 or 1 3782 */ 3783 uint8_t panel_inst; 3784 /** 3785 * Replay Frameupdate Timer Enable or not 3786 */ 3787 uint8_t enable; 3788 /** 3789 * REPLAY force reflash frame update number 3790 */ 3791 uint16_t frameupdate_count; 3792 }; 3793 /** 3794 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3795 */ 3796 struct dmub_rb_cmd_replay_set_frameupdate_timer { 3797 /** 3798 * Command header. 3799 */ 3800 struct dmub_cmd_header header; 3801 /** 3802 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3803 */ 3804 struct dmub_cmd_replay_frameupdate_timer_data data; 3805 }; 3806 3807 /** 3808 * Definition union of replay command set 3809 */ 3810 union dmub_replay_cmd_set { 3811 /** 3812 * Panel Instance. 3813 * Panel isntance to identify which replay_state to use 3814 * Currently the support is only for 0 or 1 3815 */ 3816 uint8_t panel_inst; 3817 /** 3818 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 3819 */ 3820 struct dmub_cmd_replay_set_timing_sync_data sync_data; 3821 /** 3822 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 3823 */ 3824 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 3825 /** 3826 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 3827 */ 3828 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 3829 /** 3830 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 3831 */ 3832 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 3833 /** 3834 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 3835 */ 3836 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 3837 }; 3838 3839 /** 3840 * Set of HW components that can be locked. 3841 * 3842 * Note: If updating with more HW components, fields 3843 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3844 */ 3845 union dmub_hw_lock_flags { 3846 /** 3847 * Set of HW components that can be locked. 3848 */ 3849 struct { 3850 /** 3851 * Lock/unlock OTG master update lock. 3852 */ 3853 uint8_t lock_pipe : 1; 3854 /** 3855 * Lock/unlock cursor. 3856 */ 3857 uint8_t lock_cursor : 1; 3858 /** 3859 * Lock/unlock global update lock. 3860 */ 3861 uint8_t lock_dig : 1; 3862 /** 3863 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3864 */ 3865 uint8_t triple_buffer_lock : 1; 3866 } bits; 3867 3868 /** 3869 * Union for HW Lock flags. 3870 */ 3871 uint8_t u8All; 3872 }; 3873 3874 /** 3875 * Instances of HW to be locked. 3876 * 3877 * Note: If updating with more HW components, fields 3878 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3879 */ 3880 struct dmub_hw_lock_inst_flags { 3881 /** 3882 * OTG HW instance for OTG master update lock. 3883 */ 3884 uint8_t otg_inst; 3885 /** 3886 * OPP instance for cursor lock. 3887 */ 3888 uint8_t opp_inst; 3889 /** 3890 * OTG HW instance for global update lock. 3891 * TODO: Remove, and re-use otg_inst. 3892 */ 3893 uint8_t dig_inst; 3894 /** 3895 * Explicit pad to 4 byte boundary. 3896 */ 3897 uint8_t pad; 3898 }; 3899 3900 /** 3901 * Clients that can acquire the HW Lock Manager. 3902 * 3903 * Note: If updating with more clients, fields in 3904 * dmub_inbox0_cmd_lock_hw must be updated to match. 3905 */ 3906 enum hw_lock_client { 3907 /** 3908 * Driver is the client of HW Lock Manager. 3909 */ 3910 HW_LOCK_CLIENT_DRIVER = 0, 3911 /** 3912 * PSR SU is the client of HW Lock Manager. 3913 */ 3914 HW_LOCK_CLIENT_PSR_SU = 1, 3915 HW_LOCK_CLIENT_SUBVP = 3, 3916 /** 3917 * Replay is the client of HW Lock Manager. 3918 */ 3919 HW_LOCK_CLIENT_REPLAY = 4, 3920 HW_LOCK_CLIENT_FAMS2 = 5, 3921 /** 3922 * Invalid client. 3923 */ 3924 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3925 }; 3926 3927 /** 3928 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3929 */ 3930 struct dmub_cmd_lock_hw_data { 3931 /** 3932 * Specifies the client accessing HW Lock Manager. 3933 */ 3934 enum hw_lock_client client; 3935 /** 3936 * HW instances to be locked. 3937 */ 3938 struct dmub_hw_lock_inst_flags inst_flags; 3939 /** 3940 * Which components to be locked. 3941 */ 3942 union dmub_hw_lock_flags hw_locks; 3943 /** 3944 * Specifies lock/unlock. 3945 */ 3946 uint8_t lock; 3947 /** 3948 * HW can be unlocked separately from releasing the HW Lock Mgr. 3949 * This flag is set if the client wishes to release the object. 3950 */ 3951 uint8_t should_release; 3952 /** 3953 * Explicit padding to 4 byte boundary. 3954 */ 3955 uint8_t pad; 3956 }; 3957 3958 /** 3959 * Definition of a DMUB_CMD__HW_LOCK command. 3960 * Command is used by driver and FW. 3961 */ 3962 struct dmub_rb_cmd_lock_hw { 3963 /** 3964 * Command header. 3965 */ 3966 struct dmub_cmd_header header; 3967 /** 3968 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3969 */ 3970 struct dmub_cmd_lock_hw_data lock_hw_data; 3971 }; 3972 3973 /** 3974 * ABM command sub-types. 3975 */ 3976 enum dmub_cmd_abm_type { 3977 /** 3978 * Initialize parameters for ABM algorithm. 3979 * Data is passed through an indirect buffer. 3980 */ 3981 DMUB_CMD__ABM_INIT_CONFIG = 0, 3982 /** 3983 * Set OTG and panel HW instance. 3984 */ 3985 DMUB_CMD__ABM_SET_PIPE = 1, 3986 /** 3987 * Set user requested backklight level. 3988 */ 3989 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3990 /** 3991 * Set ABM operating/aggression level. 3992 */ 3993 DMUB_CMD__ABM_SET_LEVEL = 3, 3994 /** 3995 * Set ambient light level. 3996 */ 3997 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 3998 /** 3999 * Enable/disable fractional duty cycle for backlight PWM. 4000 */ 4001 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4002 4003 /** 4004 * unregister vertical interrupt after steady state is reached 4005 */ 4006 DMUB_CMD__ABM_PAUSE = 6, 4007 4008 /** 4009 * Save and Restore ABM state. On save we save parameters, and 4010 * on restore we update state with passed in data. 4011 */ 4012 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4013 4014 /** 4015 * Query ABM caps. 4016 */ 4017 DMUB_CMD__ABM_QUERY_CAPS = 8, 4018 4019 /** 4020 * Set ABM Events 4021 */ 4022 DMUB_CMD__ABM_SET_EVENT = 9, 4023 4024 /** 4025 * Get the current ACE curve. 4026 */ 4027 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4028 }; 4029 4030 struct abm_ace_curve { 4031 /** 4032 * @offsets: ACE curve offsets. 4033 */ 4034 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4035 4036 /** 4037 * @thresholds: ACE curve thresholds. 4038 */ 4039 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4040 4041 /** 4042 * @slopes: ACE curve slopes. 4043 */ 4044 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4045 }; 4046 4047 struct fixed_pt_format { 4048 /** 4049 * @sign_bit: Indicates whether one bit is reserved for the sign. 4050 */ 4051 bool sign_bit; 4052 4053 /** 4054 * @num_int_bits: Number of bits used for integer part. 4055 */ 4056 uint8_t num_int_bits; 4057 4058 /** 4059 * @num_frac_bits: Number of bits used for fractional part. 4060 */ 4061 uint8_t num_frac_bits; 4062 4063 /** 4064 * @pad: Explicit padding to 4 byte boundary. 4065 */ 4066 uint8_t pad; 4067 }; 4068 4069 struct abm_caps { 4070 /** 4071 * @num_hg_bins: Number of histogram bins. 4072 */ 4073 uint8_t num_hg_bins; 4074 4075 /** 4076 * @num_ace_segments: Number of ACE curve segments. 4077 */ 4078 uint8_t num_ace_segments; 4079 4080 /** 4081 * @pad: Explicit padding to 4 byte boundary. 4082 */ 4083 uint8_t pad[2]; 4084 4085 /** 4086 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4087 */ 4088 struct fixed_pt_format ace_thresholds_format; 4089 4090 /** 4091 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4092 */ 4093 struct fixed_pt_format ace_offsets_format; 4094 4095 /** 4096 * @ace_slopes_format: Format of the ACE slopes. 4097 */ 4098 struct fixed_pt_format ace_slopes_format; 4099 }; 4100 4101 /** 4102 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4103 * Requirements: 4104 * - Padded explicitly to 32-bit boundary. 4105 * - Must ensure this structure matches the one on driver-side, 4106 * otherwise it won't be aligned. 4107 */ 4108 struct abm_config_table { 4109 /** 4110 * Gamma curve thresholds, used for crgb conversion. 4111 */ 4112 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4113 /** 4114 * Gamma curve offsets, used for crgb conversion. 4115 */ 4116 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4117 /** 4118 * Gamma curve slopes, used for crgb conversion. 4119 */ 4120 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4121 /** 4122 * Custom backlight curve thresholds. 4123 */ 4124 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4125 /** 4126 * Custom backlight curve offsets. 4127 */ 4128 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4129 /** 4130 * Ambient light thresholds. 4131 */ 4132 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4133 /** 4134 * Minimum programmable backlight. 4135 */ 4136 uint16_t min_abm_backlight; // 122B 4137 /** 4138 * Minimum reduction values. 4139 */ 4140 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4141 /** 4142 * Maximum reduction values. 4143 */ 4144 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4145 /** 4146 * Bright positive gain. 4147 */ 4148 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4149 /** 4150 * Dark negative gain. 4151 */ 4152 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4153 /** 4154 * Hybrid factor. 4155 */ 4156 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4157 /** 4158 * Contrast factor. 4159 */ 4160 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4161 /** 4162 * Deviation gain. 4163 */ 4164 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4165 /** 4166 * Minimum knee. 4167 */ 4168 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4169 /** 4170 * Maximum knee. 4171 */ 4172 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4173 /** 4174 * Unused. 4175 */ 4176 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4177 /** 4178 * Explicit padding to 4 byte boundary. 4179 */ 4180 uint8_t pad3[3]; // 229B 4181 /** 4182 * Backlight ramp reduction. 4183 */ 4184 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4185 /** 4186 * Backlight ramp start. 4187 */ 4188 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4189 }; 4190 4191 /** 4192 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4193 */ 4194 struct dmub_cmd_abm_set_pipe_data { 4195 /** 4196 * OTG HW instance. 4197 */ 4198 uint8_t otg_inst; 4199 4200 /** 4201 * Panel Control HW instance. 4202 */ 4203 uint8_t panel_inst; 4204 4205 /** 4206 * Controls how ABM will interpret a set pipe or set level command. 4207 */ 4208 uint8_t set_pipe_option; 4209 4210 /** 4211 * Unused. 4212 * TODO: Remove. 4213 */ 4214 uint8_t ramping_boundary; 4215 4216 /** 4217 * PwrSeq HW Instance. 4218 */ 4219 uint8_t pwrseq_inst; 4220 4221 /** 4222 * Explicit padding to 4 byte boundary. 4223 */ 4224 uint8_t pad[3]; 4225 }; 4226 4227 /** 4228 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4229 */ 4230 struct dmub_rb_cmd_abm_set_pipe { 4231 /** 4232 * Command header. 4233 */ 4234 struct dmub_cmd_header header; 4235 4236 /** 4237 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4238 */ 4239 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4240 }; 4241 4242 /** 4243 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4244 */ 4245 struct dmub_cmd_abm_set_backlight_data { 4246 /** 4247 * Number of frames to ramp to backlight user level. 4248 */ 4249 uint32_t frame_ramp; 4250 4251 /** 4252 * Requested backlight level from user. 4253 */ 4254 uint32_t backlight_user_level; 4255 4256 /** 4257 * ABM control version. 4258 */ 4259 uint8_t version; 4260 4261 /** 4262 * Panel Control HW instance mask. 4263 * Bit 0 is Panel Control HW instance 0. 4264 * Bit 1 is Panel Control HW instance 1. 4265 */ 4266 uint8_t panel_mask; 4267 4268 /** 4269 * Explicit padding to 4 byte boundary. 4270 */ 4271 uint8_t pad[2]; 4272 }; 4273 4274 /** 4275 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4276 */ 4277 struct dmub_rb_cmd_abm_set_backlight { 4278 /** 4279 * Command header. 4280 */ 4281 struct dmub_cmd_header header; 4282 4283 /** 4284 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4285 */ 4286 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4287 }; 4288 4289 /** 4290 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4291 */ 4292 struct dmub_cmd_abm_set_level_data { 4293 /** 4294 * Set current ABM operating/aggression level. 4295 */ 4296 uint32_t level; 4297 4298 /** 4299 * ABM control version. 4300 */ 4301 uint8_t version; 4302 4303 /** 4304 * Panel Control HW instance mask. 4305 * Bit 0 is Panel Control HW instance 0. 4306 * Bit 1 is Panel Control HW instance 1. 4307 */ 4308 uint8_t panel_mask; 4309 4310 /** 4311 * Explicit padding to 4 byte boundary. 4312 */ 4313 uint8_t pad[2]; 4314 }; 4315 4316 /** 4317 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4318 */ 4319 struct dmub_rb_cmd_abm_set_level { 4320 /** 4321 * Command header. 4322 */ 4323 struct dmub_cmd_header header; 4324 4325 /** 4326 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4327 */ 4328 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4329 }; 4330 4331 /** 4332 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4333 */ 4334 struct dmub_cmd_abm_set_ambient_level_data { 4335 /** 4336 * Ambient light sensor reading from OS. 4337 */ 4338 uint32_t ambient_lux; 4339 4340 /** 4341 * ABM control version. 4342 */ 4343 uint8_t version; 4344 4345 /** 4346 * Panel Control HW instance mask. 4347 * Bit 0 is Panel Control HW instance 0. 4348 * Bit 1 is Panel Control HW instance 1. 4349 */ 4350 uint8_t panel_mask; 4351 4352 /** 4353 * Explicit padding to 4 byte boundary. 4354 */ 4355 uint8_t pad[2]; 4356 }; 4357 4358 /** 4359 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4360 */ 4361 struct dmub_rb_cmd_abm_set_ambient_level { 4362 /** 4363 * Command header. 4364 */ 4365 struct dmub_cmd_header header; 4366 4367 /** 4368 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4369 */ 4370 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4371 }; 4372 4373 /** 4374 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4375 */ 4376 struct dmub_cmd_abm_set_pwm_frac_data { 4377 /** 4378 * Enable/disable fractional duty cycle for backlight PWM. 4379 * TODO: Convert to uint8_t. 4380 */ 4381 uint32_t fractional_pwm; 4382 4383 /** 4384 * ABM control version. 4385 */ 4386 uint8_t version; 4387 4388 /** 4389 * Panel Control HW instance mask. 4390 * Bit 0 is Panel Control HW instance 0. 4391 * Bit 1 is Panel Control HW instance 1. 4392 */ 4393 uint8_t panel_mask; 4394 4395 /** 4396 * Explicit padding to 4 byte boundary. 4397 */ 4398 uint8_t pad[2]; 4399 }; 4400 4401 /** 4402 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4403 */ 4404 struct dmub_rb_cmd_abm_set_pwm_frac { 4405 /** 4406 * Command header. 4407 */ 4408 struct dmub_cmd_header header; 4409 4410 /** 4411 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4412 */ 4413 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4414 }; 4415 4416 /** 4417 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4418 */ 4419 struct dmub_cmd_abm_init_config_data { 4420 /** 4421 * Location of indirect buffer used to pass init data to ABM. 4422 */ 4423 union dmub_addr src; 4424 4425 /** 4426 * Indirect buffer length. 4427 */ 4428 uint16_t bytes; 4429 4430 4431 /** 4432 * ABM control version. 4433 */ 4434 uint8_t version; 4435 4436 /** 4437 * Panel Control HW instance mask. 4438 * Bit 0 is Panel Control HW instance 0. 4439 * Bit 1 is Panel Control HW instance 1. 4440 */ 4441 uint8_t panel_mask; 4442 4443 /** 4444 * Explicit padding to 4 byte boundary. 4445 */ 4446 uint8_t pad[2]; 4447 }; 4448 4449 /** 4450 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4451 */ 4452 struct dmub_rb_cmd_abm_init_config { 4453 /** 4454 * Command header. 4455 */ 4456 struct dmub_cmd_header header; 4457 4458 /** 4459 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4460 */ 4461 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4462 }; 4463 4464 /** 4465 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4466 */ 4467 4468 struct dmub_cmd_abm_pause_data { 4469 4470 /** 4471 * Panel Control HW instance mask. 4472 * Bit 0 is Panel Control HW instance 0. 4473 * Bit 1 is Panel Control HW instance 1. 4474 */ 4475 uint8_t panel_mask; 4476 4477 /** 4478 * OTG hw instance 4479 */ 4480 uint8_t otg_inst; 4481 4482 /** 4483 * Enable or disable ABM pause 4484 */ 4485 uint8_t enable; 4486 4487 /** 4488 * Explicit padding to 4 byte boundary. 4489 */ 4490 uint8_t pad[1]; 4491 }; 4492 4493 /** 4494 * Definition of a DMUB_CMD__ABM_PAUSE command. 4495 */ 4496 struct dmub_rb_cmd_abm_pause { 4497 /** 4498 * Command header. 4499 */ 4500 struct dmub_cmd_header header; 4501 4502 /** 4503 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4504 */ 4505 struct dmub_cmd_abm_pause_data abm_pause_data; 4506 }; 4507 4508 /** 4509 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4510 */ 4511 struct dmub_cmd_abm_query_caps_in { 4512 /** 4513 * Panel instance. 4514 */ 4515 uint8_t panel_inst; 4516 4517 /** 4518 * Explicit padding to 4 byte boundary. 4519 */ 4520 uint8_t pad[3]; 4521 }; 4522 4523 /** 4524 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4525 */ 4526 struct dmub_cmd_abm_query_caps_out { 4527 /** 4528 * SW Algorithm caps. 4529 */ 4530 struct abm_caps sw_caps; 4531 4532 /** 4533 * ABM HW caps. 4534 */ 4535 struct abm_caps hw_caps; 4536 }; 4537 4538 /** 4539 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4540 */ 4541 struct dmub_rb_cmd_abm_query_caps { 4542 /** 4543 * Command header. 4544 */ 4545 struct dmub_cmd_header header; 4546 4547 /** 4548 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4549 */ 4550 union { 4551 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4552 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4553 } data; 4554 }; 4555 4556 /** 4557 * enum dmub_abm_ace_curve_type - ACE curve type. 4558 */ 4559 enum dmub_abm_ace_curve_type { 4560 /** 4561 * ACE curve as defined by the SW layer. 4562 */ 4563 ABM_ACE_CURVE_TYPE__SW = 0, 4564 /** 4565 * ACE curve as defined by the SW to HW translation interface layer. 4566 */ 4567 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4568 }; 4569 4570 /** 4571 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4572 */ 4573 struct dmub_rb_cmd_abm_get_ace_curve { 4574 /** 4575 * Command header. 4576 */ 4577 struct dmub_cmd_header header; 4578 4579 /** 4580 * Address where ACE curve should be copied. 4581 */ 4582 union dmub_addr dest; 4583 4584 /** 4585 * Type of ACE curve being queried. 4586 */ 4587 enum dmub_abm_ace_curve_type ace_type; 4588 4589 /** 4590 * Indirect buffer length. 4591 */ 4592 uint16_t bytes; 4593 4594 /** 4595 * eDP panel instance. 4596 */ 4597 uint8_t panel_inst; 4598 4599 /** 4600 * Explicit padding to 4 byte boundary. 4601 */ 4602 uint8_t pad; 4603 }; 4604 4605 /** 4606 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4607 */ 4608 struct dmub_rb_cmd_abm_save_restore { 4609 /** 4610 * Command header. 4611 */ 4612 struct dmub_cmd_header header; 4613 4614 /** 4615 * OTG hw instance 4616 */ 4617 uint8_t otg_inst; 4618 4619 /** 4620 * Enable or disable ABM pause 4621 */ 4622 uint8_t freeze; 4623 4624 /** 4625 * Explicit padding to 4 byte boundary. 4626 */ 4627 uint8_t debug; 4628 4629 /** 4630 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4631 */ 4632 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4633 }; 4634 4635 /** 4636 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4637 */ 4638 4639 struct dmub_cmd_abm_set_event_data { 4640 4641 /** 4642 * VB Scaling Init. Strength Mapping 4643 * Byte 0: 0~255 for VB level 0 4644 * Byte 1: 0~255 for VB level 1 4645 * Byte 2: 0~255 for VB level 2 4646 * Byte 3: 0~255 for VB level 3 4647 */ 4648 uint32_t vb_scaling_strength_mapping; 4649 /** 4650 * VariBright Scaling Enable 4651 */ 4652 uint8_t vb_scaling_enable; 4653 /** 4654 * Panel Control HW instance mask. 4655 * Bit 0 is Panel Control HW instance 0. 4656 * Bit 1 is Panel Control HW instance 1. 4657 */ 4658 uint8_t panel_mask; 4659 4660 /** 4661 * Explicit padding to 4 byte boundary. 4662 */ 4663 uint8_t pad[2]; 4664 }; 4665 4666 /** 4667 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 4668 */ 4669 struct dmub_rb_cmd_abm_set_event { 4670 /** 4671 * Command header. 4672 */ 4673 struct dmub_cmd_header header; 4674 4675 /** 4676 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4677 */ 4678 struct dmub_cmd_abm_set_event_data abm_set_event_data; 4679 }; 4680 4681 /** 4682 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4683 */ 4684 struct dmub_cmd_query_feature_caps_data { 4685 /** 4686 * DMUB feature capabilities. 4687 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4688 */ 4689 struct dmub_feature_caps feature_caps; 4690 }; 4691 4692 /** 4693 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4694 */ 4695 struct dmub_rb_cmd_query_feature_caps { 4696 /** 4697 * Command header. 4698 */ 4699 struct dmub_cmd_header header; 4700 /** 4701 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4702 */ 4703 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4704 }; 4705 4706 /** 4707 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4708 */ 4709 struct dmub_cmd_visual_confirm_color_data { 4710 /** 4711 * DMUB visual confirm color 4712 */ 4713 struct dmub_visual_confirm_color visual_confirm_color; 4714 }; 4715 4716 /** 4717 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4718 */ 4719 struct dmub_rb_cmd_get_visual_confirm_color { 4720 /** 4721 * Command header. 4722 */ 4723 struct dmub_cmd_header header; 4724 /** 4725 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4726 */ 4727 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4728 }; 4729 4730 /** 4731 * enum dmub_cmd_panel_cntl_type - Panel control command. 4732 */ 4733 enum dmub_cmd_panel_cntl_type { 4734 /** 4735 * Initializes embedded panel hardware blocks. 4736 */ 4737 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4738 /** 4739 * Queries backlight info for the embedded panel. 4740 */ 4741 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4742 /** 4743 * Sets the PWM Freq as per user's requirement. 4744 */ 4745 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 4746 }; 4747 4748 /** 4749 * struct dmub_cmd_panel_cntl_data - Panel control data. 4750 */ 4751 struct dmub_cmd_panel_cntl_data { 4752 uint32_t pwrseq_inst; /**< pwrseq instance */ 4753 uint32_t current_backlight; /* in/out */ 4754 uint32_t bl_pwm_cntl; /* in/out */ 4755 uint32_t bl_pwm_period_cntl; /* in/out */ 4756 uint32_t bl_pwm_ref_div1; /* in/out */ 4757 uint8_t is_backlight_on : 1; /* in/out */ 4758 uint8_t is_powered_on : 1; /* in/out */ 4759 uint8_t padding[3]; 4760 uint32_t bl_pwm_ref_div2; /* in/out */ 4761 uint8_t reserved[4]; 4762 }; 4763 4764 /** 4765 * struct dmub_rb_cmd_panel_cntl - Panel control command. 4766 */ 4767 struct dmub_rb_cmd_panel_cntl { 4768 struct dmub_cmd_header header; /**< header */ 4769 struct dmub_cmd_panel_cntl_data data; /**< payload */ 4770 }; 4771 4772 struct dmub_optc_state { 4773 uint32_t v_total_max; 4774 uint32_t v_total_min; 4775 uint32_t tg_inst; 4776 }; 4777 4778 struct dmub_rb_cmd_drr_update { 4779 struct dmub_cmd_header header; 4780 struct dmub_optc_state dmub_optc_state_req; 4781 }; 4782 4783 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 4784 uint32_t pix_clk_100hz; 4785 uint8_t max_ramp_step; 4786 uint8_t pipes; 4787 uint8_t min_refresh_in_hz; 4788 uint8_t pipe_count; 4789 uint8_t pipe_index[4]; 4790 }; 4791 4792 struct dmub_cmd_fw_assisted_mclk_switch_config { 4793 uint8_t fams_enabled; 4794 uint8_t visual_confirm_enabled; 4795 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 4796 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 4797 }; 4798 4799 struct dmub_rb_cmd_fw_assisted_mclk_switch { 4800 struct dmub_cmd_header header; 4801 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 4802 }; 4803 4804 /** 4805 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4806 */ 4807 struct dmub_cmd_lvtma_control_data { 4808 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 4809 uint8_t bypass_panel_control_wait; 4810 uint8_t reserved_0[2]; /**< For future use */ 4811 uint8_t pwrseq_inst; /**< LVTMA control instance */ 4812 uint8_t reserved_1[3]; /**< For future use */ 4813 }; 4814 4815 /** 4816 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4817 */ 4818 struct dmub_rb_cmd_lvtma_control { 4819 /** 4820 * Command header. 4821 */ 4822 struct dmub_cmd_header header; 4823 /** 4824 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4825 */ 4826 struct dmub_cmd_lvtma_control_data data; 4827 }; 4828 4829 /** 4830 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4831 */ 4832 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 4833 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4834 uint8_t is_usb; /**< is phy is usb */ 4835 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 4836 uint8_t is_dp4; /**< is dp in 4 lane */ 4837 }; 4838 4839 /** 4840 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4841 */ 4842 struct dmub_rb_cmd_transmitter_query_dp_alt { 4843 struct dmub_cmd_header header; /**< header */ 4844 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 4845 }; 4846 4847 struct phy_test_mode { 4848 uint8_t mode; 4849 uint8_t pat0; 4850 uint8_t pad[2]; 4851 }; 4852 4853 /** 4854 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4855 */ 4856 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 4857 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4858 uint8_t mode; /**< HDMI/DP/DP2 etc */ 4859 uint8_t lane_num; /**< Number of lanes */ 4860 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 4861 struct phy_test_mode test_mode; 4862 enum dmub_phy_fsm_state state; 4863 uint32_t status; 4864 uint8_t pad; 4865 }; 4866 4867 /** 4868 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4869 */ 4870 struct dmub_rb_cmd_transmitter_set_phy_fsm { 4871 struct dmub_cmd_header header; /**< header */ 4872 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 4873 }; 4874 4875 /** 4876 * Maximum number of bytes a chunk sent to DMUB for parsing 4877 */ 4878 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 4879 4880 /** 4881 * Represent a chunk of CEA blocks sent to DMUB for parsing 4882 */ 4883 struct dmub_cmd_send_edid_cea { 4884 uint16_t offset; /**< offset into the CEA block */ 4885 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 4886 uint16_t cea_total_length; /**< total length of the CEA block */ 4887 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 4888 uint8_t pad[3]; /**< padding and for future expansion */ 4889 }; 4890 4891 /** 4892 * Result of VSDB parsing from CEA block 4893 */ 4894 struct dmub_cmd_edid_cea_amd_vsdb { 4895 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 4896 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 4897 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 4898 uint16_t min_frame_rate; /**< Maximum frame rate */ 4899 uint16_t max_frame_rate; /**< Minimum frame rate */ 4900 }; 4901 4902 /** 4903 * Result of sending a CEA chunk 4904 */ 4905 struct dmub_cmd_edid_cea_ack { 4906 uint16_t offset; /**< offset of the chunk into the CEA block */ 4907 uint8_t success; /**< 1 if this sending of chunk succeeded */ 4908 uint8_t pad; /**< padding and for future expansion */ 4909 }; 4910 4911 /** 4912 * Specify whether the result is an ACK/NACK or the parsing has finished 4913 */ 4914 enum dmub_cmd_edid_cea_reply_type { 4915 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 4916 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 4917 }; 4918 4919 /** 4920 * Definition of a DMUB_CMD__EDID_CEA command. 4921 */ 4922 struct dmub_rb_cmd_edid_cea { 4923 struct dmub_cmd_header header; /**< Command header */ 4924 union dmub_cmd_edid_cea_data { 4925 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 4926 struct dmub_cmd_edid_cea_output { /**< output with results */ 4927 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 4928 union { 4929 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 4930 struct dmub_cmd_edid_cea_ack ack; 4931 }; 4932 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 4933 } data; /**< Command data */ 4934 4935 }; 4936 4937 /** 4938 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 4939 */ 4940 struct dmub_cmd_cable_id_input { 4941 uint8_t phy_inst; /**< phy inst for cable id data */ 4942 }; 4943 4944 /** 4945 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 4946 */ 4947 struct dmub_cmd_cable_id_output { 4948 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 4949 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 4950 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 4951 uint8_t RESERVED :2; /**< reserved means not defined */ 4952 }; 4953 4954 /** 4955 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 4956 */ 4957 struct dmub_rb_cmd_get_usbc_cable_id { 4958 struct dmub_cmd_header header; /**< Command header */ 4959 /** 4960 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 4961 */ 4962 union dmub_cmd_cable_id_data { 4963 struct dmub_cmd_cable_id_input input; /**< Input */ 4964 struct dmub_cmd_cable_id_output output; /**< Output */ 4965 uint8_t output_raw; /**< Raw data output */ 4966 } data; 4967 }; 4968 4969 /** 4970 * Command type of a DMUB_CMD__SECURE_DISPLAY command 4971 */ 4972 enum dmub_cmd_secure_display_type { 4973 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 4974 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 4975 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 4976 }; 4977 4978 /** 4979 * Definition of a DMUB_CMD__SECURE_DISPLAY command 4980 */ 4981 struct dmub_rb_cmd_secure_display { 4982 struct dmub_cmd_header header; 4983 /** 4984 * Data passed from driver to dmub firmware. 4985 */ 4986 struct dmub_cmd_roi_info { 4987 uint16_t x_start; 4988 uint16_t x_end; 4989 uint16_t y_start; 4990 uint16_t y_end; 4991 uint8_t otg_id; 4992 uint8_t phy_id; 4993 } roi_info; 4994 }; 4995 4996 /** 4997 * Command type of a DMUB_CMD__PSP command 4998 */ 4999 enum dmub_cmd_psp_type { 5000 DMUB_CMD__PSP_ASSR_ENABLE = 0 5001 }; 5002 5003 /** 5004 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5005 */ 5006 struct dmub_cmd_assr_enable_data { 5007 /** 5008 * ASSR enable or disable. 5009 */ 5010 uint8_t enable; 5011 /** 5012 * PHY port type. 5013 * Indicates eDP / non-eDP port type 5014 */ 5015 uint8_t phy_port_type; 5016 /** 5017 * PHY port ID. 5018 */ 5019 uint8_t phy_port_id; 5020 /** 5021 * Link encoder index. 5022 */ 5023 uint8_t link_enc_index; 5024 /** 5025 * HPO mode. 5026 */ 5027 uint8_t hpo_mode; 5028 5029 /** 5030 * Reserved field. 5031 */ 5032 uint8_t reserved[7]; 5033 }; 5034 5035 /** 5036 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5037 */ 5038 struct dmub_rb_cmd_assr_enable { 5039 /** 5040 * Command header. 5041 */ 5042 struct dmub_cmd_header header; 5043 5044 /** 5045 * Assr data. 5046 */ 5047 struct dmub_cmd_assr_enable_data assr_data; 5048 5049 /** 5050 * Reserved field. 5051 */ 5052 uint32_t reserved[3]; 5053 }; 5054 5055 /** 5056 * union dmub_rb_cmd - DMUB inbox command. 5057 */ 5058 union dmub_rb_cmd { 5059 /** 5060 * Elements shared with all commands. 5061 */ 5062 struct dmub_rb_cmd_common cmd_common; 5063 /** 5064 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5065 */ 5066 struct dmub_rb_cmd_read_modify_write read_modify_write; 5067 /** 5068 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5069 */ 5070 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5071 /** 5072 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5073 */ 5074 struct dmub_rb_cmd_burst_write burst_write; 5075 /** 5076 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5077 */ 5078 struct dmub_rb_cmd_reg_wait reg_wait; 5079 /** 5080 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5081 */ 5082 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5083 /** 5084 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5085 */ 5086 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5087 /** 5088 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5089 */ 5090 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5091 /** 5092 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5093 */ 5094 struct dmub_rb_cmd_dpphy_init dpphy_init; 5095 /** 5096 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5097 */ 5098 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5099 /** 5100 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5101 */ 5102 struct dmub_rb_cmd_domain_control domain_control; 5103 /** 5104 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5105 */ 5106 struct dmub_rb_cmd_psr_set_version psr_set_version; 5107 /** 5108 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5109 */ 5110 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5111 /** 5112 * Definition of a DMUB_CMD__PSR_ENABLE command. 5113 */ 5114 struct dmub_rb_cmd_psr_enable psr_enable; 5115 /** 5116 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5117 */ 5118 struct dmub_rb_cmd_psr_set_level psr_set_level; 5119 /** 5120 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5121 */ 5122 struct dmub_rb_cmd_psr_force_static psr_force_static; 5123 /** 5124 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5125 */ 5126 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5127 /** 5128 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5129 */ 5130 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5131 /** 5132 * Definition of a DMUB_CMD__HW_LOCK command. 5133 * Command is used by driver and FW. 5134 */ 5135 struct dmub_rb_cmd_lock_hw lock_hw; 5136 /** 5137 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5138 */ 5139 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5140 /** 5141 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5142 */ 5143 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5144 /** 5145 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5146 */ 5147 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5148 /** 5149 * Definition of a DMUB_CMD__MALL command. 5150 */ 5151 struct dmub_rb_cmd_mall mall; 5152 5153 /** 5154 * Definition of a DMUB_CMD__CAB command. 5155 */ 5156 struct dmub_rb_cmd_cab_for_ss cab; 5157 5158 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5159 5160 /** 5161 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5162 */ 5163 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5164 5165 /** 5166 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5167 */ 5168 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5169 5170 /** 5171 * Definition of DMUB_CMD__PANEL_CNTL commands. 5172 */ 5173 struct dmub_rb_cmd_panel_cntl panel_cntl; 5174 5175 /** 5176 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5177 */ 5178 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5179 5180 /** 5181 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5182 */ 5183 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5184 5185 /** 5186 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5187 */ 5188 struct dmub_rb_cmd_abm_set_level abm_set_level; 5189 5190 /** 5191 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5192 */ 5193 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5194 5195 /** 5196 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5197 */ 5198 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5199 5200 /** 5201 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5202 */ 5203 struct dmub_rb_cmd_abm_init_config abm_init_config; 5204 5205 /** 5206 * Definition of a DMUB_CMD__ABM_PAUSE command. 5207 */ 5208 struct dmub_rb_cmd_abm_pause abm_pause; 5209 5210 /** 5211 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5212 */ 5213 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5214 5215 /** 5216 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5217 */ 5218 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5219 5220 /** 5221 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5222 */ 5223 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5224 5225 /** 5226 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5227 */ 5228 struct dmub_rb_cmd_abm_set_event abm_set_event; 5229 5230 /** 5231 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5232 */ 5233 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5234 5235 /** 5236 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5237 */ 5238 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5239 5240 /** 5241 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5242 */ 5243 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5244 5245 /** 5246 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5247 */ 5248 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5249 struct dmub_rb_cmd_drr_update drr_update; 5250 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5251 5252 /** 5253 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5254 */ 5255 struct dmub_rb_cmd_lvtma_control lvtma_control; 5256 /** 5257 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5258 */ 5259 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5260 /** 5261 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5262 */ 5263 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5264 /** 5265 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5266 */ 5267 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5268 /** 5269 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5270 */ 5271 struct dmub_rb_cmd_set_config_access set_config_access; 5272 /** 5273 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5274 */ 5275 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5276 /** 5277 * Definition of a DMUB_CMD__EDID_CEA command. 5278 */ 5279 struct dmub_rb_cmd_edid_cea edid_cea; 5280 /** 5281 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5282 */ 5283 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5284 5285 /** 5286 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5287 */ 5288 struct dmub_rb_cmd_query_hpd_state query_hpd; 5289 /** 5290 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5291 */ 5292 struct dmub_rb_cmd_secure_display secure_display; 5293 5294 /** 5295 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5296 */ 5297 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5298 /** 5299 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5300 */ 5301 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5302 /* 5303 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5304 */ 5305 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5306 /** 5307 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5308 */ 5309 struct dmub_rb_cmd_replay_enable replay_enable; 5310 /** 5311 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5312 */ 5313 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5314 /** 5315 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5316 */ 5317 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5318 /** 5319 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5320 */ 5321 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5322 5323 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5324 /** 5325 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5326 */ 5327 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5328 /** 5329 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5330 */ 5331 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5332 /** 5333 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5334 */ 5335 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5336 /** 5337 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5338 */ 5339 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5340 /** 5341 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5342 */ 5343 struct dmub_rb_cmd_assr_enable assr_enable; 5344 struct dmub_rb_cmd_fams2 fams2_config; 5345 5346 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5347 5348 struct dmub_rb_cmd_fams2_flip fams2_flip; 5349 }; 5350 5351 /** 5352 * union dmub_rb_out_cmd - Outbox command 5353 */ 5354 union dmub_rb_out_cmd { 5355 /** 5356 * Parameters common to every command. 5357 */ 5358 struct dmub_rb_cmd_common cmd_common; 5359 /** 5360 * AUX reply command. 5361 */ 5362 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5363 /** 5364 * HPD notify command. 5365 */ 5366 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5367 /** 5368 * SET_CONFIG reply command. 5369 */ 5370 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5371 /** 5372 * DPIA notification command. 5373 */ 5374 struct dmub_rb_cmd_dpia_notification dpia_notification; 5375 /** 5376 * HPD sense notification command. 5377 */ 5378 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5379 }; 5380 #pragma pack(pop) 5381 5382 5383 //============================================================================== 5384 //</DMUB_CMD>=================================================================== 5385 //============================================================================== 5386 //< DMUB_RB>==================================================================== 5387 //============================================================================== 5388 5389 /** 5390 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5391 */ 5392 struct dmub_rb_init_params { 5393 void *ctx; /**< Caller provided context pointer */ 5394 void *base_address; /**< CPU base address for ring's data */ 5395 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5396 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5397 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5398 }; 5399 5400 /** 5401 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5402 */ 5403 struct dmub_rb { 5404 void *base_address; /**< CPU address for the ring's data */ 5405 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5406 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5407 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5408 5409 void *ctx; /**< Caller provided context pointer */ 5410 void *dmub; /**< Pointer to the DMUB interface */ 5411 }; 5412 5413 /** 5414 * @brief Checks if the ringbuffer is empty. 5415 * 5416 * @param rb DMUB Ringbuffer 5417 * @return true if empty 5418 * @return false otherwise 5419 */ 5420 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5421 { 5422 return (rb->wrpt == rb->rptr); 5423 } 5424 5425 /** 5426 * @brief Checks if the ringbuffer is full 5427 * 5428 * @param rb DMUB Ringbuffer 5429 * @return true if full 5430 * @return false otherwise 5431 */ 5432 static inline bool dmub_rb_full(struct dmub_rb *rb) 5433 { 5434 uint32_t data_count; 5435 5436 if (rb->wrpt >= rb->rptr) 5437 data_count = rb->wrpt - rb->rptr; 5438 else 5439 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5440 5441 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5442 } 5443 5444 /** 5445 * @brief Pushes a command into the ringbuffer 5446 * 5447 * @param rb DMUB ringbuffer 5448 * @param cmd The command to push 5449 * @return true if the ringbuffer was not full 5450 * @return false otherwise 5451 */ 5452 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5453 const union dmub_rb_cmd *cmd) 5454 { 5455 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5456 const uint64_t *src = (const uint64_t *)cmd; 5457 uint8_t i; 5458 5459 if (dmub_rb_full(rb)) 5460 return false; 5461 5462 // copying data 5463 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5464 *dst++ = *src++; 5465 5466 rb->wrpt += DMUB_RB_CMD_SIZE; 5467 5468 if (rb->wrpt >= rb->capacity) 5469 rb->wrpt %= rb->capacity; 5470 5471 return true; 5472 } 5473 5474 /** 5475 * @brief Pushes a command into the DMUB outbox ringbuffer 5476 * 5477 * @param rb DMUB outbox ringbuffer 5478 * @param cmd Outbox command 5479 * @return true if not full 5480 * @return false otherwise 5481 */ 5482 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5483 const union dmub_rb_out_cmd *cmd) 5484 { 5485 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 5486 const uint8_t *src = (const uint8_t *)cmd; 5487 5488 if (dmub_rb_full(rb)) 5489 return false; 5490 5491 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 5492 5493 rb->wrpt += DMUB_RB_CMD_SIZE; 5494 5495 if (rb->wrpt >= rb->capacity) 5496 rb->wrpt %= rb->capacity; 5497 5498 return true; 5499 } 5500 5501 /** 5502 * @brief Returns the next unprocessed command in the ringbuffer. 5503 * 5504 * @param rb DMUB ringbuffer 5505 * @param cmd The command to return 5506 * @return true if not empty 5507 * @return false otherwise 5508 */ 5509 static inline bool dmub_rb_front(struct dmub_rb *rb, 5510 union dmub_rb_cmd **cmd) 5511 { 5512 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 5513 5514 if (dmub_rb_empty(rb)) 5515 return false; 5516 5517 *cmd = (union dmub_rb_cmd *)rb_cmd; 5518 5519 return true; 5520 } 5521 5522 /** 5523 * @brief Determines the next ringbuffer offset. 5524 * 5525 * @param rb DMUB inbox ringbuffer 5526 * @param num_cmds Number of commands 5527 * @param next_rptr The next offset in the ringbuffer 5528 */ 5529 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 5530 uint32_t num_cmds, 5531 uint32_t *next_rptr) 5532 { 5533 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 5534 5535 if (*next_rptr >= rb->capacity) 5536 *next_rptr %= rb->capacity; 5537 } 5538 5539 /** 5540 * @brief Returns a pointer to a command in the inbox. 5541 * 5542 * @param rb DMUB inbox ringbuffer 5543 * @param cmd The inbox command to return 5544 * @param rptr The ringbuffer offset 5545 * @return true if not empty 5546 * @return false otherwise 5547 */ 5548 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 5549 union dmub_rb_cmd **cmd, 5550 uint32_t rptr) 5551 { 5552 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 5553 5554 if (dmub_rb_empty(rb)) 5555 return false; 5556 5557 *cmd = (union dmub_rb_cmd *)rb_cmd; 5558 5559 return true; 5560 } 5561 5562 /** 5563 * @brief Returns the next unprocessed command in the outbox. 5564 * 5565 * @param rb DMUB outbox ringbuffer 5566 * @param cmd The outbox command to return 5567 * @return true if not empty 5568 * @return false otherwise 5569 */ 5570 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 5571 union dmub_rb_out_cmd *cmd) 5572 { 5573 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 5574 uint64_t *dst = (uint64_t *)cmd; 5575 uint8_t i; 5576 5577 if (dmub_rb_empty(rb)) 5578 return false; 5579 5580 // copying data 5581 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5582 *dst++ = *src++; 5583 5584 return true; 5585 } 5586 5587 /** 5588 * @brief Removes the front entry in the ringbuffer. 5589 * 5590 * @param rb DMUB ringbuffer 5591 * @return true if the command was removed 5592 * @return false if there were no commands 5593 */ 5594 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 5595 { 5596 if (dmub_rb_empty(rb)) 5597 return false; 5598 5599 rb->rptr += DMUB_RB_CMD_SIZE; 5600 5601 if (rb->rptr >= rb->capacity) 5602 rb->rptr %= rb->capacity; 5603 5604 return true; 5605 } 5606 5607 /** 5608 * @brief Flushes commands in the ringbuffer to framebuffer memory. 5609 * 5610 * Avoids a race condition where DMCUB accesses memory while 5611 * there are still writes in flight to framebuffer. 5612 * 5613 * @param rb DMUB ringbuffer 5614 */ 5615 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 5616 { 5617 uint32_t rptr = rb->rptr; 5618 uint32_t wptr = rb->wrpt; 5619 5620 while (rptr != wptr) { 5621 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 5622 uint8_t i; 5623 5624 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5625 (void)READ_ONCE(*data++); 5626 5627 rptr += DMUB_RB_CMD_SIZE; 5628 if (rptr >= rb->capacity) 5629 rptr %= rb->capacity; 5630 } 5631 } 5632 5633 /** 5634 * @brief Initializes a DMCUB ringbuffer 5635 * 5636 * @param rb DMUB ringbuffer 5637 * @param init_params initial configuration for the ringbuffer 5638 */ 5639 static inline void dmub_rb_init(struct dmub_rb *rb, 5640 struct dmub_rb_init_params *init_params) 5641 { 5642 rb->base_address = init_params->base_address; 5643 rb->capacity = init_params->capacity; 5644 rb->rptr = init_params->read_ptr; 5645 rb->wrpt = init_params->write_ptr; 5646 } 5647 5648 /** 5649 * @brief Copies output data from in/out commands into the given command. 5650 * 5651 * @param rb DMUB ringbuffer 5652 * @param cmd Command to copy data into 5653 */ 5654 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5655 union dmub_rb_cmd *cmd) 5656 { 5657 // Copy rb entry back into command 5658 uint8_t *rd_ptr = (rb->rptr == 0) ? 5659 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5660 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5661 5662 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5663 } 5664 5665 //============================================================================== 5666 //</DMUB_RB>==================================================================== 5667 //============================================================================== 5668 #endif /* _DMUB_CMD_H_ */ 5669