1 /* 2 * Note: This header is the authoritative source for the DMUB firmware 3 * command interface. In the Linux kernel, it is maintained as an 4 * auto-generated copy from an AMD internal repository. 5 * 6 * This file follows Doxygen formatting for firmware standards and 7 * is NOT intended to be kernel-doc compliant. 8 */ 9 10 /* 11 * Copyright 2019 Advanced Micro Devices, Inc. 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 * 31 * Authors: AMD 32 * 33 */ 34 35 #ifndef DMUB_CMD_H 36 #define DMUB_CMD_H 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 //<DMUB_TYPES>================================================================== 46 /* Basic type definitions. */ 47 48 #ifdef __forceinline 49 #undef __forceinline 50 #endif 51 #define __forceinline inline 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled gradually 55 * by slowly reversing all backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 58 59 /** 60 * Flag from driver to indicate that ABM should be disabled immediately 61 * and undo all backlight programming and pixel compensation. 62 */ 63 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 64 65 /** 66 * Flag from driver to indicate that ABM should be disabled immediately 67 * and keep the current backlight programming and pixel compensation. 68 */ 69 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 70 71 /** 72 * Flag from driver to set the current ABM pipe index or ABM operating level. 73 */ 74 #define SET_ABM_PIPE_NORMAL 1 75 76 /** 77 * Number of ambient light levels in ABM algorithm. 78 */ 79 #define NUM_AMBI_LEVEL 5 80 81 /** 82 * Number of operating/aggression levels in ABM algorithm. 83 */ 84 #define NUM_AGGR_LEVEL 4 85 86 /** 87 * Number of segments in the gamma curve. 88 */ 89 #define NUM_POWER_FN_SEGS 8 90 91 /** 92 * Number of segments in the backlight curve. 93 */ 94 #define NUM_BL_CURVE_SEGS 16 95 96 /** 97 * Maximum number of segments in ABM ACE curve. 98 */ 99 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 100 101 /** 102 * Maximum number of bins in ABM histogram. 103 */ 104 #define ABM_MAX_NUM_OF_HG_BINS 64 105 106 /** 107 * Flag from driver to indicate that CACP should be disabled gradually 108 * by slowly reversing all programming and pixel compensation. 109 */ 110 #define SET_CACP_PIPE_GRADUALLY_DISABLE 0 111 112 /** 113 * Flag from driver to indicate that CACP should be disabled immediately 114 * and undo all programming and pixel compensation. 115 */ 116 #define SET_CACP_PIPE_IMMEDIATELY_DISABLE 255 117 118 /** 119 * Flag from driver to indicate that CACP should be disabled immediately 120 * and keep the current programming and pixel compensation. 121 */ 122 #define SET_CACP_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 123 124 /** 125 * Flag from driver to indicate that CACP should be disabled immediately 126 * on the next abm vertical interrupt 127 */ 128 #define SET_CACP_PIPE_IMMEDIATE_ON_NEXT_DISABLE 253 129 130 /** 131 * Flag from driver to set the current CACP pipe index or CACP operating level. 132 */ 133 #define SET_CACP_PIPE_NORMAL 1 134 135 /* Maximum number of SubVP streams */ 136 #define DMUB_MAX_SUBVP_STREAMS 2 137 138 /* Define max FPO streams as 4 for now. Current implementation today 139 * only supports 1, but could be more in the future. Reduce array 140 * size to ensure the command size remains less than 64 bytes if 141 * adding new fields. 142 */ 143 #define DMUB_MAX_FPO_STREAMS 4 144 145 /* Define to ensure that the "common" members always appear in the same 146 * order in different structs for back compat purposes 147 */ 148 #define COMMON_STREAM_STATIC_SUB_STATE \ 149 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 150 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 151 struct dmub_fams2_cmd_drr_stream_static_state drr; 152 153 /* Maximum number of streams on any ASIC. */ 154 #define DMUB_MAX_STREAMS 6 155 156 /* Maximum number of planes on any ASIC. */ 157 #define DMUB_MAX_PLANES 6 158 159 /* Maximum number of phantom planes on any ASIC */ 160 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 161 162 /* Trace buffer offset for entry */ 163 #define TRACE_BUFFER_ENTRY_OFFSET 16 164 165 /** 166 * Maximum number of dirty rects supported by FW. 167 */ 168 #define DMUB_MAX_DIRTY_RECTS 3 169 170 /** 171 * 172 * PSR control version legacy 173 */ 174 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 175 /** 176 * PSR control version with multi edp support 177 */ 178 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 179 180 /** 181 * 182 * dirty rect cmd version legacy 183 */ 184 #define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0 185 /** 186 * dirty rect cmd version with multi edp support 187 */ 188 #define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1 189 /** 190 * dirty rect cmd version with external monitor support 191 */ 192 #define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2 193 194 /** 195 * 196 * Cursor update cmd version legacy 197 */ 198 #define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0 199 /** 200 * Cursor update cmd version with multi edp support 201 */ 202 #define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1 203 /** 204 * Cursor update cmd version with external monitor support 205 */ 206 #define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2 207 208 /** 209 * ABM control version legacy 210 */ 211 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 212 213 /** 214 * ABM control version with multi edp support 215 */ 216 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 217 218 /** 219 * CACP control version legacy 220 */ 221 #define DMUB_CMD_CACP_CONTROL_VERSION_UNKNOWN 0x0 222 223 /** 224 * CACP control version with multi edp support 225 */ 226 #define DMUB_CMD_CACP_CONTROL_VERSION_1 0x1 227 228 /** 229 * CACP control mode with dynamic switch between v1 and v2 230 */ 231 #define DMUB_CMD_CACP_CONTROL_MODE_0 0x0 232 233 /** 234 * CACP control version with forced configure to v1 on new ABM HW 235 */ 236 #define DMUB_CMD_CACP_CONTROL_MODE_1 0x1 237 238 /** 239 * Physical framebuffer address location, 64-bit. 240 */ 241 #ifndef PHYSICAL_ADDRESS_LOC 242 #define PHYSICAL_ADDRESS_LOC union large_integer 243 #endif 244 245 /** 246 * OS/FW agnostic memcpy 247 */ 248 #ifndef dmub_memcpy 249 #define dmub_memcpy(dest, source, bytes) ((void)memcpy((dest), (source), (bytes))) 250 #endif 251 252 /** 253 * OS/FW agnostic memset 254 */ 255 #ifndef dmub_memset 256 #define dmub_memset(dest, val, bytes) ((void)memset((dest), (val), (bytes))) 257 #endif 258 259 /** 260 * OS/FW agnostic memcmp 261 */ 262 #ifndef dmub_memcmp 263 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 264 #endif 265 266 /** 267 * OS/FW agnostic udelay 268 */ 269 #ifndef dmub_udelay 270 #define dmub_udelay(microseconds) udelay(microseconds) 271 #endif 272 273 #pragma pack(push, 1) 274 #define ABM_NUM_OF_ACE_SEGMENTS 5 275 276 /** 277 * Debug FW state offset 278 */ 279 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 280 281 union abm_flags { 282 struct { 283 /** 284 * @abm_enabled: Indicates if ABM is enabled. 285 */ 286 unsigned int abm_enabled : 1; 287 288 /** 289 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 290 */ 291 unsigned int disable_abm_requested : 1; 292 293 /** 294 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 295 */ 296 unsigned int disable_abm_immediately : 1; 297 298 /** 299 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 300 * to be disabled immediately and keep gain. 301 */ 302 unsigned int disable_abm_immediate_keep_gain : 1; 303 304 /** 305 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 306 */ 307 unsigned int fractional_pwm : 1; 308 309 /** 310 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 311 * of user backlight level. 312 */ 313 unsigned int abm_gradual_bl_change : 1; 314 315 /** 316 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 317 */ 318 unsigned int abm_new_frame : 1; 319 320 /** 321 * @vb_scaling_enabled: Indicates variBright Scaling Enable 322 */ 323 unsigned int vb_scaling_enabled : 1; 324 } bitfields; 325 326 unsigned int u32All; 327 }; 328 329 struct abm_save_restore { 330 /** 331 * @flags: Misc. ABM flags. 332 */ 333 union abm_flags flags; 334 335 /** 336 * @pause: true: pause ABM and get state 337 * false: unpause ABM after setting state 338 */ 339 uint32_t pause; 340 341 /** 342 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 343 */ 344 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 345 346 /** 347 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 348 */ 349 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 350 351 /** 352 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 353 */ 354 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 355 356 357 /** 358 * @knee_threshold: Current x-position of ACE knee (u0.16). 359 */ 360 uint32_t knee_threshold; 361 /** 362 * @current_gain: Current backlight reduction (u16.16). 363 */ 364 uint32_t current_gain; 365 /** 366 * @curr_bl_level: Current actual backlight level converging to target backlight level. 367 */ 368 uint16_t curr_bl_level; 369 370 /** 371 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 372 */ 373 uint16_t curr_user_bl_level; 374 375 }; 376 377 /** 378 * union dmub_addr - DMUB physical/virtual 64-bit address. 379 */ 380 union dmub_addr { 381 struct { 382 uint32_t low_part; /**< Lower 32 bits */ 383 uint32_t high_part; /**< Upper 32 bits */ 384 } u; /*<< Low/high bit access */ 385 uint64_t quad_part; /*<< 64 bit address */ 386 }; 387 388 /* Flattened structure containing SOC BB parameters stored in the VBIOS 389 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 390 * This also prevents alighment issues when new parameters are added to the SoC BB. 391 * The following parameters should be added since these values can't be obtained elsewhere: 392 * -dml2_soc_power_management_parameters 393 * -dml2_soc_vmin_clock_limits 394 */ 395 struct dmub_soc_bb_params { 396 uint32_t dram_clk_change_blackout_ns; 397 uint32_t dram_clk_change_read_only_ns; 398 uint32_t dram_clk_change_write_only_ns; 399 uint32_t fclk_change_blackout_ns; 400 uint32_t g7_ppt_blackout_ns; 401 uint32_t stutter_enter_plus_exit_latency_ns; 402 uint32_t stutter_exit_latency_ns; 403 uint32_t z8_stutter_enter_plus_exit_latency_ns; 404 uint32_t z8_stutter_exit_latency_ns; 405 uint32_t z8_min_idle_time_ns; 406 uint32_t type_b_dram_clk_change_blackout_ns; 407 uint32_t type_b_ppt_blackout_ns; 408 uint32_t vmin_limit_dispclk_khz; 409 uint32_t vmin_limit_dcfclk_khz; 410 uint32_t g7_temperature_read_blackout_ns; 411 }; 412 #pragma pack(pop) 413 414 /** 415 * Dirty rect definition. 416 */ 417 struct dmub_rect { 418 /** 419 * Dirty rect x offset. 420 */ 421 uint32_t x; 422 423 /** 424 * Dirty rect y offset. 425 */ 426 uint32_t y; 427 428 /** 429 * Dirty rect width. 430 */ 431 uint32_t width; 432 433 /** 434 * Dirty rect height. 435 */ 436 uint32_t height; 437 }; 438 439 /** 440 * Flags that can be set by driver to change some PSR behaviour. 441 */ 442 union dmub_psr_debug_flags { 443 /** 444 * Debug flags. 445 */ 446 struct { 447 /** 448 * Enable visual confirm in FW. 449 */ 450 uint32_t visual_confirm : 1; 451 452 /** 453 * Force all selective updates to bw full frame updates. 454 */ 455 uint32_t force_full_frame_update : 1; 456 457 /** 458 * Use HW Lock Mgr object to do HW locking in FW. 459 */ 460 uint32_t use_hw_lock_mgr : 1; 461 462 /** 463 * Use TPS3 signal when restore main link. 464 */ 465 uint32_t force_wakeup_by_tps3 : 1; 466 467 /** 468 * Back to back flip, therefore cannot power down PHY 469 */ 470 uint32_t back_to_back_flip : 1; 471 472 /** 473 * Enable visual confirm for IPS 474 */ 475 uint32_t enable_ips_visual_confirm : 1; 476 } bitfields; 477 478 /** 479 * Union for debug flags. 480 */ 481 uint32_t u32All; 482 }; 483 484 /** 485 * Flags that can be set by driver to change some Replay behaviour. 486 */ 487 union replay_debug_flags { 488 struct { 489 /** 490 * 0x1 (bit 0) 491 * Enable visual confirm in FW. 492 */ 493 uint32_t visual_confirm : 1; 494 495 /** 496 * 0x2 (bit 1) 497 * @skip_crc: Set if need to skip CRC. 498 */ 499 uint32_t skip_crc : 1; 500 501 /** 502 * 0x4 (bit 2) 503 * @force_link_power_on: Force disable ALPM control 504 */ 505 uint32_t force_link_power_on : 1; 506 507 /** 508 * 0x8 (bit 3) 509 * @force_phy_power_on: Force phy power on 510 */ 511 uint32_t force_phy_power_on : 1; 512 513 /** 514 * 0x10 (bit 4) 515 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 516 */ 517 uint32_t timing_resync_disabled : 1; 518 519 /** 520 * 0x20 (bit 5) 521 * @skip_crtc_disabled: CRTC disable skipped 522 */ 523 uint32_t skip_crtc_disabled : 1; 524 525 /** 526 * 0x40 (bit 6) 527 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 528 */ 529 uint32_t force_defer_one_frame_update : 1; 530 531 /** 532 * 0x80 (bit 7) 533 * @disable_delay_alpm_on: Force disable delay alpm on 534 */ 535 uint32_t disable_delay_alpm_on : 1; 536 537 /** 538 * 0x100 (bit 8) 539 * @disable_desync_error_check: Force disable desync error check 540 */ 541 uint32_t disable_desync_error_check : 1; 542 543 /** 544 * 0x200 (bit 9) 545 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 546 */ 547 uint32_t force_self_update_when_abm_non_steady : 1; 548 549 /** 550 * 0x400 (bit 10) 551 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 552 * If we enter IPS2, the Visual confirm bar will change to yellow 553 */ 554 uint32_t enable_ips_visual_confirm : 1; 555 556 /** 557 * 0x800 (bit 11) 558 * @enable_ips_residency_profiling: Enable IPS residency profiling 559 */ 560 uint32_t enable_ips_residency_profiling : 1; 561 562 /** 563 * 0x1000 (bit 12) 564 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 565 */ 566 uint32_t enable_coasting_vtotal_check : 1; 567 /** 568 * 0x2000 (bit 13) 569 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 570 */ 571 uint32_t enable_visual_confirm_debug : 1; 572 573 /** 574 * 0x4000 (bit 14) 575 * @debug_log_enabled: Debug Log Enabled 576 */ 577 uint32_t debug_log_enabled : 1; 578 579 /** 580 * 0x8000 (bit 15) 581 * @enable_sub_feature_visual_confirm: Enable Sub Feature Visual Confirm 582 */ 583 uint32_t enable_sub_feature_visual_confirm : 1; 584 585 uint32_t reserved : 16; 586 } bitfields; 587 588 uint32_t u32All; 589 }; 590 591 /** 592 * Flags record error state. 593 */ 594 union replay_visual_confirm_error_state_flags { 595 struct { 596 /** 597 * 0x1 (bit 0) - Desync Error flag. 598 */ 599 uint32_t desync_error : 1; 600 601 /** 602 * 0x2 (bit 1) - State Transition Error flag. 603 */ 604 uint32_t state_transition_error : 1; 605 606 /** 607 * 0x4 (bit 2) - Crc Error flag 608 */ 609 uint32_t crc_error : 1; 610 611 /** 612 * 0x8 (bit 3) - Reserved 613 */ 614 uint32_t reserved_3 : 1; 615 616 /** 617 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 618 * Added new debug flag to control DPCD. 619 */ 620 uint32_t incorrect_vtotal_in_static_screen : 1; 621 622 /** 623 * 0x20 (bit 5) - No doubled Refresh Rate. 624 */ 625 uint32_t no_double_rr : 1; 626 627 /** 628 * Reserved bit 6-7 629 */ 630 uint32_t reserved_6_7 : 2; 631 632 /** 633 * Reserved bit 9-31 634 */ 635 uint32_t reserved_9_31 : 24; 636 } bitfields; 637 638 uint32_t u32All; 639 }; 640 641 union replay_hw_flags { 642 struct { 643 /** 644 * @allow_alpm_fw_standby_mode: To indicate whether the 645 * ALPM FW standby mode is allowed 646 */ 647 uint32_t allow_alpm_fw_standby_mode : 1; 648 649 /* 650 * @dsc_enable_status: DSC enable status in driver 651 */ 652 uint32_t dsc_enable_status : 1; 653 654 /** 655 * @fec_enable_status: receive fec enable/disable status from driver 656 */ 657 uint32_t fec_enable_status : 1; 658 659 /* 660 * @smu_optimizations_en: SMU power optimization. 661 * Only when active display is Replay capable and display enters Replay. 662 * Trigger interrupt to SMU to powerup/down. 663 */ 664 uint32_t smu_optimizations_en : 1; 665 666 /** 667 * @phy_power_state: Indicates current phy power state 668 */ 669 uint32_t phy_power_state : 1; 670 671 /** 672 * @link_power_state: Indicates current link power state 673 */ 674 uint32_t link_power_state : 1; 675 /** 676 * Use TPS3 signal when restore main link. 677 */ 678 uint32_t force_wakeup_by_tps3 : 1; 679 /** 680 * @is_alpm_initialized: Indicates whether ALPM is initialized 681 */ 682 uint32_t is_alpm_initialized : 1; 683 684 /** 685 * @alpm_mode: Indicates ALPM mode selected 686 */ 687 uint32_t alpm_mode : 2; 688 } bitfields; 689 690 uint32_t u32All; 691 }; 692 693 /** 694 * Flags that can be set by driver to change some Panel Replay behaviour. 695 */ 696 union pr_debug_flags { 697 struct { 698 /** 699 * 0x1 (bit 0) 700 * Enable visual confirm in FW. 701 */ 702 uint32_t visual_confirm : 1; 703 704 /** 705 * 0x2 (bit 1) 706 * @skip_crc: Set if need to skip CRC. 707 */ 708 uint32_t skip_crc : 1; 709 710 /** 711 * 0x4 (bit 2) 712 * @force_link_power_on: Force disable ALPM control 713 */ 714 uint32_t force_link_power_on : 1; 715 716 /** 717 * 0x8 (bit 3) 718 * @force_phy_power_on: Force phy power on 719 */ 720 uint32_t force_phy_power_on : 1; 721 722 /** 723 * 0x10 (bit 4) 724 * @visual_confirm_rate_control: Enable Visual Confirm rate control detection 725 */ 726 uint32_t visual_confirm_rate_control : 1; 727 728 /** 729 * 0x20 (bit 5) 730 * @force_full_frame_update: Force all selective updates to be full frame updates 731 */ 732 uint32_t force_full_frame_update : 1; 733 734 /** 735 * 0x40 (bit 6) 736 * @force_dpg_on: Force DPG on 737 */ 738 uint32_t force_dpg_on : 1; 739 740 /** 741 * 0x80 (bit 7) 742 * @force_hubp_on: Force Hubp on 743 */ 744 uint32_t force_hubp_on : 1; 745 746 uint32_t reserved : 24; 747 } bitfields; 748 749 uint32_t u32All; 750 }; 751 752 union pr_hw_flags { 753 struct { 754 /** 755 * @allow_alpm_fw_standby_mode: To indicate whether the 756 * ALPM FW standby mode is allowed 757 */ 758 uint32_t allow_alpm_fw_standby_mode : 1; 759 760 /* 761 * @dsc_enable_status: DSC enable status in driver 762 */ 763 uint32_t dsc_enable_status : 1; 764 765 /** 766 * @fec_enable_status: receive fec enable/disable status from driver 767 */ 768 uint32_t fec_enable_status : 1; 769 /* 770 * @smu_optimizations_en: SMU power optimization. 771 * Only when active display is Replay capable and display enters Replay. 772 * Trigger interrupt to SMU to powerup/down. 773 */ 774 uint32_t smu_optimizations_en : 1; 775 /** 776 * @link_power_state: Indicates current link power state 777 */ 778 uint32_t link_power_state : 1; 779 /** 780 * Use TPS3 signal when restore main link. 781 */ 782 uint32_t force_wakeup_by_tps3 : 1; 783 /** 784 * @is_alpm_initialized: Indicates whether ALPM is initialized 785 */ 786 uint32_t is_alpm_initialized : 1; 787 /** 788 * @alpm_mode: Indicates ALPM mode selected 789 */ 790 uint32_t alpm_mode : 2; 791 uint32_t reserved : 23; 792 } bitfields; 793 794 uint32_t u32All; 795 }; 796 797 /** 798 * Definition of Panel Replay ML Activity Options 799 */ 800 enum pr_ml_activity_option { 801 OPTION_DEFAULT = 0x00, // VESA Option Default (1C) 802 OPTION_1A = 0x01, // VESA Option 1A 803 OPTION_1B = 0x02, // VESA Option 1B 804 OPTION_1C = 0x03, // VESA Option 1C 805 }; 806 807 union fw_assisted_mclk_switch_version { 808 struct { 809 uint8_t minor : 5; 810 uint8_t major : 3; 811 }; 812 uint8_t ver; 813 }; 814 815 /** 816 * DMUB feature capabilities. 817 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 818 */ 819 struct dmub_feature_caps { 820 /** 821 * Max PSR version supported by FW. 822 */ 823 uint8_t psr; 824 uint8_t fw_assisted_mclk_switch_ver; 825 uint8_t reserved[4]; 826 uint8_t subvp_psr_support; 827 uint8_t gecc_enable; 828 uint8_t replay_supported; 829 uint8_t replay_reserved[3]; 830 uint8_t abm_aux_backlight_support; 831 uint8_t lsdma_support_in_dmu; 832 }; 833 834 struct dmub_visual_confirm_color { 835 /** 836 * Maximum 10 bits color value 837 */ 838 uint16_t color_r_cr; 839 uint16_t color_g_y; 840 uint16_t color_b_cb; 841 uint16_t panel_inst; 842 }; 843 844 /** 845 * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data. 846 */ 847 struct dmub_cursor_offload_pipe_data_dcn30_v1 { 848 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 849 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 850 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 851 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 852 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 853 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 854 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 855 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 856 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 857 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 858 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 859 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 860 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 861 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 862 uint32_t reserved0[4]; 863 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 864 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 865 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 866 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 867 uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 868 uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 869 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16; 870 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16; 871 uint32_t reserved1[5]; 872 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 873 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 874 uint32_t reserved2[3]; 875 }; 876 877 /** 878 * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data. 879 */ 880 struct dmub_cursor_offload_pipe_data_dcn401_v1 { 881 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 882 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 883 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 884 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 885 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 886 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 887 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 888 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 889 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 890 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 891 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 892 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 893 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 894 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 895 uint32_t reserved0[4]; 896 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 897 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 898 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 899 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 900 uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 901 uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 902 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16; 903 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16; 904 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16; 905 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16; 906 uint32_t reserved1[4]; 907 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 908 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 909 uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1; 910 uint32_t reserved2[3]; 911 }; 912 913 /** 914 * struct dmub_cursor_offload_pipe_data_dcn60_v1 - DCN60 per pipe data. 915 */ 916 struct dmub_cursor_offload_pipe_data_dcn60_v1 { 917 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 918 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 919 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 920 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 921 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 922 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 923 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 924 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 925 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 926 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 927 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 928 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 929 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 930 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 931 uint32_t reserved0[4]; 932 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 933 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 934 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 935 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 936 uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 937 uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 938 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16; 939 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16; 940 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16; 941 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16; 942 uint32_t reserved1[4]; 943 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 944 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 945 uint32_t HUBPREQ0_CURSOR_SETTINGS__FORCE_CURSOR_TO_DISP_PREF : 1; 946 uint32_t reserved2[3]; 947 }; 948 /** 949 * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload. 950 */ 951 struct dmub_cursor_offload_pipe_data_v1 { 952 union { 953 struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */ 954 struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */ 955 struct dmub_cursor_offload_pipe_data_dcn60_v1 dcn60; /**< DCN60 cursor data. */ 956 uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */ 957 }; 958 }; 959 960 /** 961 * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data. 962 */ 963 struct dmub_cursor_offload_payload_data_v1 { 964 uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */ 965 uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */ 966 uint32_t pipe_mask; /**< Mask of pipes to update. */ 967 uint32_t reserved; /**< Reserved for future use. */ 968 struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */ 969 }; 970 971 /** 972 * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload. 973 */ 974 struct dmub_cursor_offload_stream_v1 { 975 struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */ 976 uint32_t write_idx; /**< The index of the last written payload. */ 977 }; 978 979 /** 980 * struct dmub_cursor_offload_v1 - Cursor offload feature state. 981 */ 982 struct dmub_cursor_offload_v1 { 983 struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */ 984 }; 985 986 //============================================================================== 987 //</DMUB_TYPES>================================================================= 988 //============================================================================== 989 //< DMUB_META>================================================================== 990 //============================================================================== 991 #pragma pack(push, 1) 992 993 /* Magic value for identifying dmub_fw_meta_info */ 994 #define DMUB_FW_META_MAGIC 0x444D5542 995 996 /* Offset from the end of the file to the dmub_fw_meta_info */ 997 #define DMUB_FW_META_OFFSET 0x24 998 999 /** 1000 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 1001 */ 1002 union dmub_fw_meta_feature_bits { 1003 struct { 1004 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 1005 uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ 1006 uint32_t inbox0_lock_support: 1; /**< 1 supports inbox0 lock mechanism */ 1007 uint32_t reserved : 29; 1008 } bits; /**< status bits */ 1009 uint32_t all; /**< 32-bit access to status bits */ 1010 }; 1011 1012 /** 1013 * struct dmub_fw_meta_info - metadata associated with fw binary 1014 * 1015 * NOTE: This should be considered a stable API. Fields should 1016 * not be repurposed or reordered. New fields should be 1017 * added instead to extend the structure. 1018 * 1019 * @magic_value: magic value identifying DMUB firmware meta info 1020 * @fw_region_size: size of the firmware state region 1021 * @trace_buffer_size: size of the tracebuffer region 1022 * @fw_version: the firmware version information 1023 * @dal_fw: 1 if the firmware is DAL 1024 * @shared_state_size: size of the shared state region in bytes 1025 * @shared_state_features: number of shared state features 1026 */ 1027 struct dmub_fw_meta_info { 1028 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 1029 uint32_t fw_region_size; /**< size of the firmware state region */ 1030 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 1031 uint32_t fw_version; /**< the firmware version information */ 1032 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 1033 uint8_t reserved[3]; /**< padding bits */ 1034 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 1035 uint16_t shared_state_features; /**< number of shared state features */ 1036 uint16_t reserved2; /**< padding bytes */ 1037 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 1038 }; 1039 1040 /** 1041 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 1042 */ 1043 union dmub_fw_meta { 1044 struct dmub_fw_meta_info info; /**< metadata info */ 1045 uint8_t reserved[64]; /**< padding bits */ 1046 }; 1047 1048 #pragma pack(pop) 1049 1050 //============================================================================== 1051 //< DMUB Trace Buffer>================================================================ 1052 //============================================================================== 1053 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 1054 /** 1055 * dmub_trace_code_t - firmware trace code, 32-bits 1056 */ 1057 typedef uint32_t dmub_trace_code_t; 1058 1059 /** 1060 * struct dmcub_trace_buf_entry - Firmware trace entry 1061 */ 1062 struct dmcub_trace_buf_entry { 1063 dmub_trace_code_t trace_code; /**< trace code for the event */ 1064 uint32_t tick_count; /**< the tick count at time of trace */ 1065 uint32_t param0; /**< trace defined parameter 0 */ 1066 uint32_t param1; /**< trace defined parameter 1 */ 1067 }; 1068 #endif 1069 1070 //============================================================================== 1071 //< DMUB_STATUS>================================================================ 1072 //============================================================================== 1073 1074 /** 1075 * DMCUB scratch registers can be used to determine firmware status. 1076 * Current scratch register usage is as follows: 1077 * 1078 * SCRATCH0: FW Boot Status register 1079 * SCRATCH5: LVTMA Status Register 1080 * SCRATCH15: FW Boot Options register 1081 */ 1082 1083 /** 1084 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 1085 */ 1086 union dmub_fw_boot_status { 1087 struct { 1088 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 1089 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 1090 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 1091 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 1092 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 1093 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 1094 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 1095 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 1096 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 1097 } bits; /**< status bits */ 1098 uint32_t all; /**< 32-bit access to status bits */ 1099 }; 1100 1101 /** 1102 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 1103 */ 1104 enum dmub_fw_boot_status_bit { 1105 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 1106 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 1107 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 1108 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 1109 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 1110 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 1111 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 1112 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 1113 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 1114 }; 1115 1116 /* Register bit definition for SCRATCH5 */ 1117 union dmub_lvtma_status { 1118 struct { 1119 uint32_t psp_ok : 1; 1120 uint32_t edp_on : 1; 1121 uint32_t reserved : 30; 1122 } bits; 1123 uint32_t all; 1124 }; 1125 1126 enum dmub_lvtma_status_bit { 1127 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 1128 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 1129 }; 1130 1131 enum dmub_ips_disable_type { 1132 DMUB_IPS_ENABLE = 0, 1133 DMUB_IPS_DISABLE_ALL = 1, 1134 DMUB_IPS_DISABLE_IPS1 = 2, 1135 DMUB_IPS_DISABLE_IPS2 = 3, 1136 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 1137 DMUB_IPS_DISABLE_DYNAMIC = 5, 1138 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 1139 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 1140 }; 1141 1142 enum dmub_ips_rcg_disable_type { 1143 DMUB_IPS_RCG_ENABLE = 0, 1144 DMUB_IPS0_RCG_DISABLE = 1, 1145 DMUB_IPS1_RCG_DISABLE = 2, 1146 DMUB_IPS_RCG_DISABLE = 3 1147 }; 1148 1149 enum dmub_ips_in_vpb_disable_type { 1150 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 1151 DMUB_IPS_VPB_DISABLE_ALL = 1, 1152 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 1153 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 1154 }; 1155 1156 #define DMUB_IPS1_ALLOW_MASK 0x00000001 1157 #define DMUB_IPS2_ALLOW_MASK 0x00000002 1158 #define DMUB_IPS1_COMMIT_MASK 0x00000004 1159 #define DMUB_IPS2_COMMIT_MASK 0x00000008 1160 1161 enum dmub_ips_comand_type { 1162 /** 1163 * Start/stop IPS residency measurements for a given IPS mode 1164 */ 1165 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 1166 /** 1167 * Query IPS residency information for a given IPS mode 1168 */ 1169 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 1170 }; 1171 1172 /** 1173 * enum dmub_cursor_offload_comand_type - Cursor offload subcommands. 1174 */ 1175 enum dmub_cursor_offload_comand_type { 1176 /** 1177 * Initializes the cursor offload feature. 1178 */ 1179 DMUB_CMD__CURSOR_OFFLOAD_INIT = 0, 1180 /** 1181 * Enables cursor offloading for a stream and updates the timing parameters. 1182 */ 1183 DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1, 1184 /** 1185 * Disables cursor offloading for a given stream. 1186 */ 1187 DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2, 1188 /** 1189 * Programs the latest data for a given stream. 1190 */ 1191 DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3, 1192 }; 1193 1194 /** 1195 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 1196 */ 1197 union dmub_fw_boot_options { 1198 struct { 1199 uint32_t pemu_env : 1; /**< 1 if PEMU */ 1200 uint32_t fpga_env : 1; /**< 1 if FPGA */ 1201 uint32_t optimized_init : 1; /**< 1 if optimized init */ 1202 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 1203 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 1204 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 1205 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 1206 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 1207 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 1208 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 1209 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 1210 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 1211 uint32_t power_optimization: 1; 1212 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 1213 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 1214 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 1215 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 1216 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 1217 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 1218 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 1219 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 1220 uint32_t ips_disable: 3; /* options to disable ips support*/ 1221 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 1222 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 1223 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 1224 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 1225 uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */ 1226 uint32_t bootcrc_en_at_preos: 1; /**< 1 to run the boot time crc during warm/cold boot*/ 1227 uint32_t bootcrc_en_at_S0i3: 1; /**< 1 to run the boot time crc during S0i3 boot*/ 1228 uint32_t bootcrc_boot_mode: 1; /**< 1 for S0i3 resume and 0 for Warm/cold boot*/ 1229 uint32_t reserved : 1; /**< reserved */ 1230 } bits; /**< boot bits */ 1231 uint32_t all; /**< 32-bit access to bits */ 1232 }; 1233 1234 enum dmub_fw_boot_options_bit { 1235 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 1236 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 1237 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 1238 }; 1239 1240 //============================================================================== 1241 //< DMUB_SHARED_STATE>========================================================== 1242 //============================================================================== 1243 1244 /** 1245 * Shared firmware state between driver and firmware for lockless communication 1246 * in situations where the inbox/outbox may be unavailable. 1247 * 1248 * Each structure *must* be at most 256-bytes in size. The layout allocation is 1249 * described below: 1250 * 1251 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 1252 */ 1253 1254 /** 1255 * enum dmub_shared_state_feature_id - List of shared state features. 1256 */ 1257 enum dmub_shared_state_feature_id { 1258 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 1259 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 1260 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 1261 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 1262 DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4, 1263 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 1264 }; 1265 1266 /** 1267 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 1268 */ 1269 union dmub_shared_state_ips_fw_signals { 1270 struct { 1271 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 1272 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 1273 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 1274 uint32_t detection_required : 1; /**< 1 if detection is required */ 1275 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 1276 uint32_t reserved_bits : 27; /**< Reversed */ 1277 } bits; 1278 uint32_t all; 1279 }; 1280 1281 /** 1282 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 1283 */ 1284 union dmub_shared_state_ips_driver_signals { 1285 struct { 1286 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 1287 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 1288 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 1289 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 1290 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 1291 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 1292 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 1293 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 1294 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 1295 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 1296 uint32_t reserved_bits : 22; /**< Reversed bits */ 1297 } bits; 1298 uint32_t all; 1299 }; 1300 1301 /** 1302 * IPS FW Version 1303 */ 1304 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 1305 1306 struct dmub_shared_state_debug_setup { 1307 union { 1308 struct { 1309 uint32_t exclude_points[62]; 1310 } profile_mode; 1311 }; 1312 }; 1313 1314 /** 1315 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 1316 */ 1317 struct dmub_shared_state_ips_fw { 1318 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 1319 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 1320 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 1321 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 1322 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 1323 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 1324 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 1325 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 1326 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 1327 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 1328 }; /* 248-bytes, fixed */ 1329 1330 /** 1331 * IPS Driver Version 1332 */ 1333 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 1334 1335 /** 1336 * struct dmub_shared_state_ips_driver - Driver state for IPS. 1337 */ 1338 struct dmub_shared_state_ips_driver { 1339 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 1340 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 1341 }; /* 248-bytes, fixed */ 1342 1343 /** 1344 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1345 */ 1346 struct dmub_shared_state_cursor_offload_stream_v1 { 1347 uint32_t last_write_idx; /**< Last write index */ 1348 uint8_t reserved[28]; /**< Reserved bytes. */ 1349 }; /* 32-bytes, fixed */ 1350 1351 /** 1352 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1353 */ 1354 struct dmub_shared_state_cursor_offload_v1 { 1355 struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */ 1356 uint8_t reserved[56]; /**< reserved for future use */ 1357 }; /* 248-bytes, fixed */ 1358 1359 /** 1360 * enum dmub_shared_state_feature_common - Generic payload. 1361 */ 1362 struct dmub_shared_state_feature_common { 1363 uint32_t padding[62]; 1364 }; /* 248-bytes, fixed */ 1365 1366 /** 1367 * enum dmub_shared_state_feature_header - Feature description. 1368 */ 1369 struct dmub_shared_state_feature_header { 1370 uint16_t id; /**< Feature ID */ 1371 uint16_t version; /**< Feature version */ 1372 uint32_t reserved; /**< Reserved bytes. */ 1373 }; /* 8 bytes, fixed */ 1374 1375 /** 1376 * struct dmub_shared_state_feature_block - Feature block. 1377 */ 1378 struct dmub_shared_state_feature_block { 1379 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 1380 union dmub_shared_feature_state_union { 1381 struct dmub_shared_state_feature_common common; /**< Generic data */ 1382 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 1383 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 1384 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 1385 struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */ 1386 } data; /**< Shared state data. */ 1387 }; /* 256-bytes, fixed */ 1388 1389 /** 1390 * Shared state size in bytes. 1391 */ 1392 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 1393 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 1394 1395 //============================================================================== 1396 //</DMUB_STATUS>================================================================ 1397 //============================================================================== 1398 //< DMUB_VBIOS>================================================================= 1399 //============================================================================== 1400 1401 /* 1402 * enum dmub_cmd_vbios_type - VBIOS commands. 1403 * 1404 * Command IDs should be treated as stable ABI. 1405 * Do not reuse or modify IDs. 1406 */ 1407 enum dmub_cmd_vbios_type { 1408 /** 1409 * Configures the DIG encoder. 1410 */ 1411 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1412 /** 1413 * Controls the PHY. 1414 */ 1415 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1416 /** 1417 * Sets the pixel clock/symbol clock. 1418 */ 1419 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1420 /** 1421 * Enables or disables power gating. 1422 */ 1423 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1424 /** 1425 * Controls embedded panels. 1426 */ 1427 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1428 /** 1429 * Query DP alt status on a transmitter. 1430 */ 1431 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1432 /** 1433 * Control PHY FSM 1434 */ 1435 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1436 /** 1437 * Controls domain power gating 1438 */ 1439 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1440 }; 1441 1442 //============================================================================== 1443 //</DMUB_VBIOS>================================================================= 1444 //============================================================================== 1445 //< DMUB_GPINT>================================================================= 1446 //============================================================================== 1447 1448 /** 1449 * The shifts and masks below may alternatively be used to format and read 1450 * the command register bits. 1451 */ 1452 1453 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1454 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1455 1456 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1457 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1458 1459 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1460 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1461 1462 /** 1463 * Command responses. 1464 */ 1465 1466 /** 1467 * Return response for DMUB_GPINT__STOP_FW command. 1468 */ 1469 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1470 1471 /** 1472 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1473 */ 1474 union dmub_gpint_data_register { 1475 struct { 1476 uint32_t param : 16; /**< 16-bit parameter */ 1477 uint32_t command_code : 12; /**< GPINT command */ 1478 uint32_t status : 4; /**< Command status bit */ 1479 } bits; /**< GPINT bit access */ 1480 uint32_t all; /**< GPINT 32-bit access */ 1481 }; 1482 1483 /* 1484 * enum dmub_gpint_command - GPINT command to DMCUB FW 1485 * 1486 * Command IDs should be treated as stable ABI. 1487 * Do not reuse or modify IDs. 1488 */ 1489 enum dmub_gpint_command { 1490 /** 1491 * Invalid command, ignored. 1492 */ 1493 DMUB_GPINT__INVALID_COMMAND = 0, 1494 /** 1495 * DESC: Queries the firmware version. 1496 * RETURN: Firmware version. 1497 */ 1498 DMUB_GPINT__GET_FW_VERSION = 1, 1499 /** 1500 * DESC: Halts the firmware. 1501 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1502 */ 1503 DMUB_GPINT__STOP_FW = 2, 1504 /** 1505 * DESC: Get PSR state from FW. 1506 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1507 */ 1508 DMUB_GPINT__GET_PSR_STATE = 7, 1509 /** 1510 * DESC: Notifies DMCUB of the currently active streams. 1511 * ARGS: Stream mask, 1 bit per active stream index. 1512 */ 1513 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1514 /** 1515 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1516 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1517 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1518 * RETURN: PSR residency in milli-percent. 1519 */ 1520 DMUB_GPINT__PSR_RESIDENCY = 9, 1521 1522 /** 1523 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1524 */ 1525 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1526 1527 /** 1528 * DESC: Get REPLAY state from FW. 1529 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1530 */ 1531 DMUB_GPINT__GET_REPLAY_STATE = 13, 1532 1533 /** 1534 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1535 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1536 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1537 * RETURN: REPLAY residency in milli-percent. 1538 */ 1539 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1540 1541 /** 1542 * DESC: Set CACP internal core configuration 1543 */ 1544 DMUB_GPINT__TRIGGER_CACP = 18, 1545 1546 /** 1547 * DESC: Copy bounding box to the host. 1548 * ARGS: Version of bounding box to copy 1549 * RETURN: Result of copying bounding box 1550 */ 1551 DMUB_GPINT__BB_COPY = 96, 1552 1553 /** 1554 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1555 * ARGS: The word3 for the 64 bit address 1556 */ 1557 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1558 1559 /** 1560 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1561 * ARGS: The word2 for the 64 bit address 1562 */ 1563 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1564 1565 /** 1566 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1567 * ARGS: The word1 for the 64 bit address 1568 */ 1569 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1570 1571 /** 1572 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1573 * ARGS: The word0 for the 64 bit address 1574 */ 1575 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1576 1577 /** 1578 * DESC: Updates the trace buffer lower 32-bit mask. 1579 * ARGS: The new mask 1580 * RETURN: Lower 32-bit mask. 1581 */ 1582 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1583 1584 /** 1585 * DESC: Updates the trace buffer mask bit0~bit15. 1586 * ARGS: The new mask 1587 * RETURN: Lower 32-bit mask. 1588 */ 1589 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1590 1591 /** 1592 * DESC: Updates the trace buffer mask bit16~bit31. 1593 * ARGS: The new mask 1594 * RETURN: Lower 32-bit mask. 1595 */ 1596 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1597 1598 /** 1599 * DESC: Updates the trace buffer mask bit32~bit47. 1600 * ARGS: The new mask 1601 * RETURN: Lower 32-bit mask. 1602 */ 1603 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1604 1605 /** 1606 * DESC: Updates the trace buffer mask bit48~bit63. 1607 * ARGS: The new mask 1608 * RETURN: Lower 32-bit mask. 1609 */ 1610 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1611 1612 /** 1613 * DESC: Read the trace buffer mask bi0~bit15. 1614 */ 1615 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1616 1617 /** 1618 * DESC: Read the trace buffer mask bit16~bit31. 1619 */ 1620 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1621 1622 /** 1623 * DESC: Read the trace buffer mask bi32~bit47. 1624 */ 1625 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1626 1627 /** 1628 * DESC: Updates the trace buffer mask bit32~bit63. 1629 */ 1630 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1631 1632 /** 1633 * DESC: Set IPS residency measurement 1634 * ARGS: 0 - Disable ips measurement 1635 * 1 - Enable ips measurement 1636 */ 1637 DMUB_GPINT__IPS_RESIDENCY = 121, 1638 /** 1639 * DESC: Enable measurements for various task duration 1640 * ARGS: 0 - Disable measurement 1641 * 1 - Enable measurement 1642 */ 1643 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1644 /** 1645 * DESC: Gets IPS residency in microseconds 1646 * ARGS: 0 - Return IPS1 residency 1647 * 1 - Return IPS2 residency 1648 * 2 - Return IPS0_RCG residency 1649 * 3 - Return IPS1_ONO2_ON residency 1650 * 4 - Return IPS1_Z8_RETENTION residency 1651 * RETURN: Total residency in microseconds - lower 32 bits 1652 */ 1653 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1654 /** 1655 * DESC: Gets IPS1 histogram counts 1656 * ARGS: Bucket index 1657 * RETURN: Total count for the bucket 1658 */ 1659 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1660 /** 1661 * DESC: Gets IPS2 histogram counts 1662 * ARGS: Bucket index 1663 * RETURN: Total count for the bucket 1664 */ 1665 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1666 /** 1667 * DESC: Gets IPS residency 1668 * ARGS: 0 - Return IPS1 residency 1669 * 1 - Return IPS2 residency 1670 * 2 - Return IPS0_RCG residency 1671 * 3 - Return IPS1_ONO2_ON residency 1672 * 4 - Return IPS1_Z8_RETENTION residency 1673 * RETURN: Total residency in milli-percent. 1674 */ 1675 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1676 /** 1677 * DESC: Gets IPS0_RCG histogram counts 1678 * ARGS: Bucket index 1679 * RETURN: Total count for the bucket 1680 */ 1681 DMUB_GPINT__GET_IPS0_RCG_HISTOGRAM_COUNTER = 128, 1682 /** 1683 * DESC: Gets IPS1_ONO2_ON histogram counts 1684 * ARGS: Bucket index 1685 * RETURN: Total count for the bucket 1686 */ 1687 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1688 /** 1689 * DESC: Gets IPS entry counter during residency measurement 1690 * ARGS: 0 - Return IPS1 entry counts 1691 * 1 - Return IPS2 entry counts 1692 * 2 - Return IPS0_RCG entry counts 1693 * 3 - Return IPS1_ONO2_ON entry counts 1694 * 4 - Return IPS1_Z8_RETENTION entry counts 1695 * RETURN: Entry counter for selected IPS mode 1696 */ 1697 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1698 /** 1699 * DESC: Gets IPS inactive residency in microseconds 1700 * ARGS: 0 - Return IPS1_MAX residency 1701 * 1 - Return IPS2 residency 1702 * 2 - Return IPS0_RCG residency 1703 * 3 - Return IPS1_ONO2_ON residency 1704 * 4 - Return IPS1_Z8_RETENTION residency 1705 * RETURN: Total inactive residency in microseconds - lower 32 bits 1706 */ 1707 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1708 /** 1709 * DESC: Gets IPS inactive residency in microseconds 1710 * ARGS: 0 - Return IPS1_MAX residency 1711 * 1 - Return IPS2 residency 1712 * 2 - Return IPS0_RCG residency 1713 * 3 - Return IPS1_ONO2_ON residency 1714 * 4 - Return IPS1_Z8_RETENTION residency 1715 * RETURN: Total inactive residency in microseconds - upper 32 bits 1716 */ 1717 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1718 /** 1719 * DESC: Gets IPS residency in microseconds 1720 * ARGS: 0 - Return IPS1 residency 1721 * 1 - Return IPS2 residency 1722 * 2 - Return IPS0_RCG residency 1723 * 3 - Return IPS1_ONO2_ON residency 1724 * 4 - Return IPS1_Z8_RETENTION residency 1725 * RETURN: Total residency in microseconds - upper 32 bits 1726 */ 1727 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1728 /** 1729 * DESC: Setup debug configs. 1730 */ 1731 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1732 /** 1733 * DESC: Initiates IPS wake sequence. 1734 */ 1735 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1736 /** 1737 * DESC: Do panel power off sequence 1738 * ARGS: 1 - Power off 1739 */ 1740 DMUB_GPINT__PANEL_POWER_OFF_SEQ = 138, 1741 /** 1742 * DESC: Gets panel polarity bias. 1743 * ARGS: 0 - Get panel polarity bias 1744 */ 1745 DMUB_GPINT__PANEL_POLARITY_GET_BIAS = 139, 1746 /** 1747 * DESC: Enables panel polarity. 1748 * ARGS: 0 - Disable panel polarity 1749 * 1 - Enable panel polarity 1750 */ 1751 DMUB_GPINT__PANEL_POLARITY_DEBUG_ENABLE = 140, 1752 }; 1753 1754 /** 1755 * INBOX0 generic command definition 1756 */ 1757 union dmub_inbox0_cmd_common { 1758 struct { 1759 uint32_t command_code: 8; /**< INBOX0 command code */ 1760 uint32_t param: 24; /**< 24-bit parameter */ 1761 } bits; 1762 uint32_t all; 1763 }; 1764 1765 /** 1766 * INBOX0 hw_lock command definition 1767 */ 1768 union dmub_inbox0_cmd_lock_hw { 1769 struct { 1770 uint32_t command_code: 8; 1771 1772 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1773 uint32_t hw_lock_client: 2; 1774 1775 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1776 uint32_t otg_inst: 3; 1777 uint32_t opp_inst: 3; 1778 uint32_t dig_inst: 3; 1779 1780 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1781 uint32_t lock_pipe: 1; 1782 uint32_t lock_cursor: 1; 1783 uint32_t lock_dig: 1; 1784 uint32_t triple_buffer_lock: 1; 1785 1786 uint32_t lock: 1; /**< Lock */ 1787 uint32_t should_release: 1; /**< Release */ 1788 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1789 } bits; 1790 uint32_t all; 1791 }; 1792 1793 union dmub_inbox0_data_register { 1794 union dmub_inbox0_cmd_common inbox0_cmd_common; 1795 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1796 }; 1797 1798 enum dmub_inbox0_command { 1799 /** 1800 * DESC: Invalid command, ignored. 1801 */ 1802 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1803 /** 1804 * DESC: Notification to acquire/release HW lock 1805 * ARGS: 1806 */ 1807 DMUB_INBOX0_CMD__HW_LOCK = 1, 1808 }; 1809 //============================================================================== 1810 //</DMUB_GPINT>================================================================= 1811 //============================================================================== 1812 //< DMUB_CMD>=================================================================== 1813 //============================================================================== 1814 1815 /** 1816 * Size in bytes of each DMUB command. 1817 */ 1818 #define DMUB_RB_CMD_SIZE 64 1819 1820 /** 1821 * Maximum number of items in the DMUB ringbuffer. 1822 */ 1823 #define DMUB_RB_MAX_ENTRY 128 1824 1825 /** 1826 * Ringbuffer size in bytes. 1827 */ 1828 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1829 1830 /** 1831 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1832 */ 1833 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1834 1835 /** 1836 * Ringbuffer size in bytes. 1837 */ 1838 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1839 1840 /** 1841 * REG_SET mask for reg offload. 1842 */ 1843 #define REG_SET_MASK 0xFFFF 1844 1845 /* 1846 * enum dmub_cmd_type - DMUB inbox command. 1847 * 1848 * Command IDs should be treated as stable ABI. 1849 * Do not reuse or modify IDs. 1850 * Note that command IDs 1-4 have been deprecated. 1851 */ 1852 enum dmub_cmd_type { 1853 /** 1854 * Invalid command. 1855 */ 1856 DMUB_CMD__NULL = 0, 1857 /** 1858 * Workaround to avoid HUBP underflow during NV12 playback. 1859 */ 1860 DMUB_CMD__PLAT_54186_WA = 5, 1861 /** 1862 * Command type used to query FW feature caps. 1863 */ 1864 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1865 /** 1866 * Command type used to get visual confirm color. 1867 */ 1868 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1869 /** 1870 * Command type used for all PSR commands. 1871 */ 1872 DMUB_CMD__PSR = 64, 1873 /** 1874 * Command type used for all MALL commands. 1875 */ 1876 DMUB_CMD__MALL = 65, 1877 /** 1878 * Command type used for all ABM commands. 1879 */ 1880 DMUB_CMD__ABM = 66, 1881 /** 1882 * Command type used to update dirty rects in FW. 1883 */ 1884 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1885 /** 1886 * Command type used to update cursor info in FW. 1887 */ 1888 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1889 /** 1890 * Command type used for HW locking in FW. 1891 */ 1892 DMUB_CMD__HW_LOCK = 69, 1893 /** 1894 * Command type used to access DP AUX. 1895 */ 1896 DMUB_CMD__DP_AUX_ACCESS = 70, 1897 /** 1898 * Command type used for OUTBOX1 notification enable 1899 */ 1900 DMUB_CMD__OUTBOX1_ENABLE = 71, 1901 1902 /** 1903 * Command type used for all idle optimization commands. 1904 */ 1905 DMUB_CMD__IDLE_OPT = 72, 1906 /** 1907 * Command type used for all clock manager commands. 1908 */ 1909 DMUB_CMD__CLK_MGR = 73, 1910 /** 1911 * Command type used for all panel control commands. 1912 */ 1913 DMUB_CMD__PANEL_CNTL = 74, 1914 1915 /** 1916 * Command type used for all CAB commands. 1917 */ 1918 DMUB_CMD__CAB_FOR_SS = 75, 1919 1920 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1921 1922 /** 1923 * Command type used for interfacing with DPIA. 1924 */ 1925 DMUB_CMD__DPIA = 77, 1926 /** 1927 * Command type used for EDID CEA parsing 1928 */ 1929 DMUB_CMD__EDID_CEA = 79, 1930 /** 1931 * Command type used for getting usbc cable ID 1932 */ 1933 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1934 /** 1935 * Command type used to query HPD state. 1936 */ 1937 DMUB_CMD__QUERY_HPD_STATE = 82, 1938 /** 1939 * Command type used for all VBIOS interface commands. 1940 */ 1941 /** 1942 * Command type used for all REPLAY commands. 1943 */ 1944 DMUB_CMD__REPLAY = 83, 1945 1946 /** 1947 * Command type used for all SECURE_DISPLAY commands. 1948 */ 1949 DMUB_CMD__SECURE_DISPLAY = 85, 1950 1951 /** 1952 * Command type used to set DPIA HPD interrupt state 1953 */ 1954 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1955 1956 /** 1957 * Command type used for all CACP commands. 1958 */ 1959 DMUB_CMD__CACP = 87, 1960 1961 /** 1962 * Command type used for all PSP commands. 1963 */ 1964 DMUB_CMD__PSP = 88, 1965 1966 /** 1967 * Command type used for all Fused IO commands. 1968 */ 1969 DMUB_CMD__FUSED_IO = 89, 1970 1971 /** 1972 * Command type used for all LSDMA commands. 1973 */ 1974 DMUB_CMD__LSDMA = 90, 1975 1976 /** 1977 * Command type use for all IPS commands. 1978 */ 1979 DMUB_CMD__IPS = 91, 1980 1981 /** 1982 * Command type use for Cursor offload. 1983 */ 1984 DMUB_CMD__CURSOR_OFFLOAD = 92, 1985 1986 /** 1987 * Command type used for all SMART_POWER_OLED commands. 1988 */ 1989 DMUB_CMD__SMART_POWER_OLED = 93, 1990 1991 /** 1992 * Command type use for all Panel Replay commands. 1993 */ 1994 DMUB_CMD__PR = 94, 1995 1996 /** 1997 * Command type used for all IHC commands. 1998 */ 1999 DMUB_CMD__IHC = 95, 2000 2001 /** 2002 * Command type use for boot time crc commands. 2003 */ 2004 DMUB_CMD__BOOT_TIME_CRC = 96, 2005 2006 /** 2007 * Command type use for all Panel Polarity commands. 2008 */ 2009 DMUB_CMD__PANEL_POLARITY = 97, 2010 2011 /** 2012 * Command type use for VBIOS shared commands. 2013 */ 2014 DMUB_CMD__VBIOS = 128, 2015 }; 2016 2017 /** 2018 * enum dmub_out_cmd_type - DMUB outbox commands. 2019 */ 2020 enum dmub_out_cmd_type { 2021 /** 2022 * Invalid outbox command, ignored. 2023 */ 2024 DMUB_OUT_CMD__NULL = 0, 2025 /** 2026 * Command type used for DP AUX Reply data notification 2027 */ 2028 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 2029 /** 2030 * Command type used for DP HPD event notification 2031 */ 2032 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 2033 /** 2034 * Command type used for SET_CONFIG Reply notification 2035 */ 2036 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 2037 /** 2038 * Command type used for USB4 DPIA notification 2039 */ 2040 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 2041 /** 2042 * Command type used for HPD redetect notification 2043 */ 2044 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 2045 /** 2046 * Command type used for Fused IO notification 2047 */ 2048 DMUB_OUT_CMD__FUSED_IO = 7, 2049 }; 2050 2051 /* DMUB_CMD__DPIA command sub-types. */ 2052 enum dmub_cmd_dpia_type { 2053 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 2054 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 2055 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 2056 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 2057 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 2058 }; 2059 2060 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 2061 enum dmub_cmd_dpia_notification_type { 2062 DPIA_NOTIFY__BW_ALLOCATION = 0, 2063 }; 2064 2065 #pragma pack(push, 1) 2066 2067 /** 2068 * struct dmub_cmd_header - Common command header fields. 2069 */ 2070 struct dmub_cmd_header { 2071 unsigned int type : 8; /**< command type */ 2072 unsigned int sub_type : 8; /**< command sub type */ 2073 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 2074 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 2075 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 2076 unsigned int reserved0 : 5; /**< reserved bits */ 2077 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 2078 unsigned int reserved1 : 2; /**< reserved bits */ 2079 }; 2080 2081 /** 2082 * struct dmub_rb_cmd_common - Common command header 2083 */ 2084 struct dmub_rb_cmd_common { 2085 struct dmub_cmd_header header; /**< command header */ 2086 /** 2087 * Padding to RB_CMD_SIZE 2088 */ 2089 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 2090 }; 2091 2092 /** 2093 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 2094 * 2095 * Reprograms surface parameters to avoid underflow. 2096 */ 2097 struct dmub_cmd_PLAT_54186_wa { 2098 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 2099 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 2100 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 2101 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 2102 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 2103 struct { 2104 uint32_t hubp_inst : 4; /**< HUBP instance */ 2105 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 2106 uint32_t immediate :1; /**< Immediate flip */ 2107 uint32_t vmid : 4; /**< VMID */ 2108 uint32_t grph_stereo : 1; /**< 1 if stereo */ 2109 uint32_t reserved : 21; /**< Reserved */ 2110 } flip_params; /**< Pageflip parameters */ 2111 uint32_t reserved[9]; /**< Reserved bits */ 2112 }; 2113 2114 /** 2115 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 2116 */ 2117 struct dmub_rb_cmd_PLAT_54186_wa { 2118 struct dmub_cmd_header header; /**< Command header */ 2119 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 2120 }; 2121 2122 /** 2123 * enum dmub_cmd_mall_type - MALL commands 2124 */ 2125 enum dmub_cmd_mall_type { 2126 /** 2127 * Allows display refresh from MALL. 2128 */ 2129 DMUB_CMD__MALL_ACTION_ALLOW = 0, 2130 /** 2131 * Disallows display refresh from MALL. 2132 */ 2133 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 2134 /** 2135 * Cursor copy for MALL. 2136 */ 2137 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 2138 /** 2139 * Controls DF requests. 2140 */ 2141 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 2142 }; 2143 2144 /** 2145 * struct dmub_rb_cmd_mall - MALL command data. 2146 */ 2147 struct dmub_rb_cmd_mall { 2148 struct dmub_cmd_header header; /**< Common command header */ 2149 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 2150 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 2151 uint32_t tmr_delay; /**< Timer delay */ 2152 uint32_t tmr_scale; /**< Timer scale */ 2153 uint16_t cursor_width; /**< Cursor width in pixels */ 2154 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 2155 uint16_t cursor_height; /**< Cursor height in pixels */ 2156 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 2157 uint8_t debug_bits; /**< Debug bits */ 2158 2159 uint8_t reserved1; /**< Reserved bits */ 2160 uint8_t reserved2; /**< Reserved bits */ 2161 }; 2162 2163 /** 2164 * enum dmub_cmd_cab_type - CAB command data. 2165 */ 2166 enum dmub_cmd_cab_type { 2167 /** 2168 * No idle optimizations (i.e. no CAB) 2169 */ 2170 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 2171 /** 2172 * No DCN requests for memory 2173 */ 2174 DMUB_CMD__CAB_NO_DCN_REQ = 1, 2175 /** 2176 * Fit surfaces in CAB (i.e. CAB enable) 2177 */ 2178 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 2179 /** 2180 * Do not fit surfaces in CAB (i.e. no CAB) 2181 */ 2182 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 2183 }; 2184 2185 /** 2186 * struct dmub_rb_cmd_cab_for_ss - CAB command data. 2187 */ 2188 struct dmub_rb_cmd_cab_for_ss { 2189 struct dmub_cmd_header header; 2190 uint8_t cab_alloc_ways; /* total number of ways */ 2191 uint8_t debug_bits; /* debug bits */ 2192 }; 2193 2194 /** 2195 * Enum for indicating which MCLK switch mode per pipe 2196 */ 2197 enum mclk_switch_mode { 2198 NONE = 0, 2199 FPO = 1, 2200 SUBVP = 2, 2201 VBLANK = 3, 2202 }; 2203 2204 /* Per pipe struct which stores the MCLK switch mode 2205 * data to be sent to DMUB. 2206 * Named "v2" for now -- once FPO and SUBVP are fully merged 2207 * the type name can be updated 2208 */ 2209 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 2210 union { 2211 struct { 2212 uint32_t pix_clk_100hz; 2213 uint16_t main_vblank_start; 2214 uint16_t main_vblank_end; 2215 uint16_t mall_region_lines; 2216 uint16_t prefetch_lines; 2217 uint16_t prefetch_to_mall_start_lines; 2218 uint16_t processing_delay_lines; 2219 uint16_t htotal; // required to calculate line time for multi-display cases 2220 uint16_t vtotal; 2221 uint8_t main_pipe_index; 2222 uint8_t phantom_pipe_index; 2223 /* Since the microschedule is calculated in terms of OTG lines, 2224 * include any scaling factors to make sure when we get accurate 2225 * conversion when programming MALL_START_LINE (which is in terms 2226 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 2227 * is 1/2 (numerator = 1, denominator = 2). 2228 */ 2229 uint8_t scale_factor_numerator; 2230 uint8_t scale_factor_denominator; 2231 uint8_t is_drr; 2232 uint8_t main_split_pipe_index; 2233 uint8_t phantom_split_pipe_index; 2234 } subvp_data; 2235 2236 struct { 2237 uint32_t pix_clk_100hz; 2238 uint16_t vblank_start; 2239 uint16_t vblank_end; 2240 uint16_t vstartup_start; 2241 uint16_t vtotal; 2242 uint16_t htotal; 2243 uint8_t vblank_pipe_index; 2244 uint8_t padding[1]; 2245 struct { 2246 uint8_t drr_in_use; 2247 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 2248 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 2249 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 2250 uint8_t use_ramping; // Use ramping or not 2251 uint8_t drr_vblank_start_margin; 2252 } drr_info; // DRR considered as part of SubVP + VBLANK case 2253 } vblank_data; 2254 } pipe_config; 2255 2256 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 2257 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 2258 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 2259 */ 2260 uint8_t mode; // enum mclk_switch_mode 2261 }; 2262 2263 /** 2264 * Config data for Sub-VP and FPO 2265 * Named "v2" for now -- once FPO and SUBVP are fully merged 2266 * the type name can be updated 2267 */ 2268 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 2269 uint16_t watermark_a_cache; 2270 uint8_t vertical_int_margin_us; 2271 uint8_t pstate_allow_width_us; 2272 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 2273 }; 2274 2275 /** 2276 * DMUB rb command definition for Sub-VP and FPO 2277 * Named "v2" for now -- once FPO and SUBVP are fully merged 2278 * the type name can be updated 2279 */ 2280 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 2281 struct dmub_cmd_header header; 2282 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 2283 }; 2284 2285 struct dmub_flip_addr_info { 2286 uint32_t surf_addr_lo; 2287 uint32_t surf_addr_c_lo; 2288 uint32_t meta_addr_lo; 2289 uint32_t meta_addr_c_lo; 2290 uint16_t surf_addr_hi; 2291 uint16_t surf_addr_c_hi; 2292 uint16_t meta_addr_hi; 2293 uint16_t meta_addr_c_hi; 2294 }; 2295 2296 struct dmub_fams2_flip_info { 2297 union { 2298 struct { 2299 uint8_t is_immediate: 1; 2300 } bits; 2301 uint8_t all; 2302 } config; 2303 uint8_t otg_inst; 2304 uint8_t pipe_mask; 2305 uint8_t pad; 2306 struct dmub_flip_addr_info addr_info; 2307 }; 2308 2309 struct dmub_rb_cmd_fams2_flip { 2310 struct dmub_cmd_header header; 2311 struct dmub_fams2_flip_info flip_info; 2312 }; 2313 2314 struct dmub_cmd_lsdma_data { 2315 union { 2316 struct lsdma_init_data { 2317 union dmub_addr gpu_addr_base; 2318 uint32_t ring_size; 2319 } init_data; 2320 struct lsdma_tiled_copy_data { 2321 uint32_t src_addr_lo; 2322 uint32_t src_addr_hi; 2323 2324 uint32_t dst_addr_lo; 2325 uint32_t dst_addr_hi; 2326 2327 uint32_t src_x : 16; 2328 uint32_t src_y : 16; 2329 2330 uint32_t dst_x : 16; 2331 uint32_t dst_y : 16; 2332 2333 uint32_t src_width : 16; 2334 uint32_t src_height : 16; 2335 2336 uint32_t dst_width : 16; 2337 uint32_t dst_height : 16; 2338 2339 uint32_t rect_x : 16; 2340 uint32_t rect_y : 16; 2341 2342 uint32_t src_swizzle_mode : 5; 2343 uint32_t src_mip_max : 5; 2344 uint32_t src_mip_id : 5; 2345 uint32_t dst_mip_max : 5; 2346 uint32_t dst_swizzle_mode : 5; 2347 uint32_t dst_mip_id : 5; 2348 uint32_t dcc : 1; 2349 uint32_t padding1 : 1; 2350 2351 uint32_t data_format : 6; 2352 uint32_t tmz : 4; 2353 uint32_t dst_element_size : 3; 2354 uint32_t num_type : 3; 2355 uint32_t src_element_size : 3; 2356 uint32_t write_compress : 2; 2357 uint32_t cache_policy_dst : 3; 2358 uint32_t cache_policy_src : 3; 2359 uint32_t read_compress : 2; 2360 uint32_t max_com : 2; 2361 uint32_t max_uncom : 1; 2362 2363 uint32_t dst_dim : 2; 2364 uint32_t src_dim : 2; 2365 uint32_t padding : 28; 2366 } tiled_copy_data; 2367 struct lsdma_linear_copy_data { 2368 uint32_t src_lo; 2369 uint32_t src_hi; 2370 2371 uint32_t dst_lo; 2372 uint32_t dst_hi; 2373 2374 uint32_t count : 30; 2375 uint32_t pad0 : 2; 2376 2377 uint32_t tmz : 4; 2378 uint32_t cache_policy_src : 3; 2379 uint32_t cache_policy_dst : 3; 2380 uint32_t data_format : 6; 2381 uint32_t num_type : 3; 2382 uint32_t read_compress : 2; 2383 uint32_t write_compress : 2; 2384 uint32_t max_com : 2; 2385 uint32_t max_uncom : 1; 2386 uint32_t pad1 : 6; 2387 } linear_copy_data; 2388 struct lsdma_linear_sub_window_copy_data { 2389 uint32_t src_lo; 2390 uint32_t src_hi; 2391 2392 uint32_t dst_lo; 2393 uint32_t dst_hi; 2394 2395 uint32_t src_x : 16; 2396 uint32_t src_y : 16; 2397 2398 uint32_t dst_x : 16; 2399 uint32_t dst_y : 16; 2400 2401 uint32_t rect_x : 16; 2402 uint32_t rect_y : 16; 2403 2404 uint32_t src_pitch : 16; 2405 uint32_t dst_pitch : 16; 2406 2407 uint32_t src_slice_pitch; 2408 uint32_t dst_slice_pitch; 2409 2410 uint32_t tmz : 4; 2411 uint32_t element_size : 3; 2412 uint32_t src_cache_policy : 3; 2413 uint32_t dst_cache_policy : 3; 2414 uint32_t data_format : 6; 2415 uint32_t num_type : 3; 2416 uint32_t read_compress : 2; 2417 uint32_t write_compress : 2; 2418 uint32_t max_com : 2; 2419 uint32_t max_uncom : 1; 2420 uint32_t reserved0 : 3; 2421 } linear_sub_window_copy_data; 2422 struct lsdma_reg_write_data { 2423 uint32_t reg_addr; 2424 uint32_t reg_data; 2425 } reg_write_data; 2426 struct lsdma_pio_copy_data { 2427 uint32_t src_lo; 2428 uint32_t src_hi; 2429 2430 uint32_t dst_lo; 2431 uint32_t dst_hi; 2432 2433 union { 2434 struct { 2435 uint32_t byte_count : 26; 2436 uint32_t src_loc : 1; 2437 uint32_t dst_loc : 1; 2438 uint32_t src_addr_inc : 1; 2439 uint32_t dst_addr_inc : 1; 2440 uint32_t overlap_disable : 1; 2441 uint32_t constant_fill : 1; 2442 } fields; 2443 uint32_t raw; 2444 } packet; 2445 } pio_copy_data; 2446 struct lsdma_pio_constfill_data { 2447 uint32_t dst_lo; 2448 uint32_t dst_hi; 2449 2450 union { 2451 struct { 2452 uint32_t byte_count : 26; 2453 uint32_t src_loc : 1; 2454 uint32_t dst_loc : 1; 2455 uint32_t src_addr_inc : 1; 2456 uint32_t dst_addr_inc : 1; 2457 uint32_t overlap_disable : 1; 2458 uint32_t constant_fill : 1; 2459 } fields; 2460 uint32_t raw; 2461 } packet; 2462 2463 uint32_t data; 2464 } pio_constfill_data; 2465 2466 uint32_t all[14]; 2467 } u; 2468 }; 2469 2470 struct dmub_rb_cmd_lsdma { 2471 struct dmub_cmd_header header; 2472 struct dmub_cmd_lsdma_data lsdma_data; 2473 }; 2474 2475 struct dmub_optc_state_v2 { 2476 uint32_t v_total_min; 2477 uint32_t v_total_max; 2478 uint32_t v_total_mid; 2479 uint32_t v_total_mid_frame_num; 2480 uint8_t program_manual_trigger; 2481 uint8_t tg_inst; 2482 uint8_t pad[2]; 2483 }; 2484 2485 struct dmub_optc_position { 2486 uint32_t vpos; 2487 uint32_t hpos; 2488 uint32_t frame; 2489 }; 2490 2491 struct dmub_rb_cmd_fams2_drr_update { 2492 struct dmub_cmd_header header; 2493 struct dmub_optc_state_v2 dmub_optc_state_req; 2494 }; 2495 2496 /* HW and FW global configuration data for FAMS2 */ 2497 /* FAMS2 types and structs */ 2498 enum fams2_stream_type { 2499 FAMS2_STREAM_TYPE_NONE = 0, 2500 FAMS2_STREAM_TYPE_VBLANK = 1, 2501 FAMS2_STREAM_TYPE_VACTIVE = 2, 2502 FAMS2_STREAM_TYPE_DRR = 3, 2503 FAMS2_STREAM_TYPE_SUBVP = 4, 2504 FAMS2_STREAM_TYPE_ALTERNATE = 5, 2505 }; 2506 2507 struct dmub_rect16 { 2508 /** 2509 * Dirty rect x offset. 2510 */ 2511 uint16_t x; 2512 2513 /** 2514 * Dirty rect y offset. 2515 */ 2516 uint16_t y; 2517 2518 /** 2519 * Dirty rect width. 2520 */ 2521 uint16_t width; 2522 2523 /** 2524 * Dirty rect height. 2525 */ 2526 uint16_t height; 2527 }; 2528 2529 struct plane_pipe_rect { 2530 struct dmub_rect16 luma; 2531 struct dmub_rect16 chroma; 2532 }; 2533 2534 /** 2535 * Structure to hold the LSDMA source / dest copy parameters. 2536 * Each field is an array of [2][4]: 2537 * [2] - Instance 0 is the copy for current frame, instance 1 is the copy for next frame (instance 1 potentially unused if no next) 2538 * [4] - One instance per pipe 2539 */ 2540 2541 struct lsdma_outputs { 2542 uint16_t src_x[2][4]; // src x position for the copy. Array of [2][4] for curr vs. next and each pipe 2543 uint16_t src_y[2][4]; // src y position for the copy 2544 uint16_t dst_x[2][4]; // dst x position for the copy (can change for curr vs. next) 2545 uint16_t dst_y[2][4]; // dst y position for the copy (can change for curr vs. next) 2546 uint16_t width[2][4]; // src and dst width for the copy (src and dst must match) 2547 uint16_t height[2][4]; // src and dst height for the copy (src and dst must match) 2548 uint16_t dst_pitch[4]; // dst pitch for the copy (same for curr and next) 2549 }; 2550 2551 struct dmub_fams2_alternate_stream_dynamic_state { 2552 uint64_t earliest_init_tick; // track earliest possible init tick for calculating is_tick_in_allow 2553 uint32_t otg_frame_pending_clear[3]; // In this context pending means prefetch has never been completed for this frame yet 2554 uint8_t flip_pending_clear_order[3]; 2555 uint8_t num_pending_flips; 2556 uint32_t prefetch_start_line_x1000[3]; // can compute from existing params, but store because we use this multiple times 2557 uint16_t prefetch_end_line[3]; // can compute from existing params, but store because we use this multiple times 2558 uint16_t recout_y[3]; 2559 uint8_t flip_pending[3]; 2560 uint8_t copy_from_earliest[3]; 2561 uint16_t lsdma_bandwidth_mbps; 2562 uint16_t vstartup_line; 2563 uint16_t vready_line; 2564 uint8_t cursor_size[3]; // Cursor array per plane for now - if we assume a single cursor, then we don't need an array 2565 uint8_t pad; // to maintain alignment for below fields - re-arrange structure once all fields are finalized 2566 /* outputs: */ 2567 uint16_t subvp_start_line_a[3]; 2568 uint16_t subvp_height_a[3]; 2569 uint16_t subvp_next_start_line_a[3]; 2570 uint16_t subvp_next_height_a[3]; 2571 uint16_t subvp_start_line_b[3]; 2572 uint16_t subvp_height_b[3]; 2573 uint16_t subvp_next_start_line_b[3]; 2574 uint16_t subvp_next_height_b[3]; 2575 uint16_t subvp_c_start_line_a[3]; 2576 uint16_t subvp_c_height_a[3]; 2577 uint16_t subvp_c_next_start_line_a[3]; 2578 uint16_t subvp_c_next_height_a[3]; 2579 uint16_t subvp_c_start_line_b[3]; 2580 uint16_t subvp_c_height_b[3]; 2581 uint16_t subvp_c_next_start_line_b[3]; 2582 uint16_t subvp_c_next_height_b[3]; 2583 uint8_t subvp_position[3]; 2584 uint8_t pad1[1]; // to maintain alignment for below fields - re-arrange structure once all fields are finalized 2585 uint32_t program_go_line; 2586 uint32_t program_go_frame_count; 2587 uint16_t svp0_start_dst_line; 2588 uint16_t svp0_end_dst_line; 2589 uint16_t svp1_start_dst_line; 2590 uint16_t svp1_end_dst_line; 2591 struct lsdma_outputs lsdma[2]; // [2] - instance per SVP0 and SVP1 2592 struct lsdma_outputs lsdma_c[2]; // [2] - instance per SVP0 and SVP1 2593 }; 2594 struct dmub_fams2_cmd_alternate_stream_static_state { 2595 uint32_t total_bytes_to_copy; 2596 uint16_t svp0_dst_lines; // per stream 2597 uint16_t svp1_dst_lines; // per stream 2598 uint16_t min_lead_dst_lines; // per stream, should be max(nominal_req_limit, vstartup_to_vactive). Does not have to be maxed over all planes 2599 uint16_t svp_req_limit; // per stream, should be the same value in time between all streams max(2 swaths, dst_y_pre) over all planes 2600 uint16_t fw_delays; 2601 uint16_t vstartup_start; 2602 uint16_t rec_height[3]; 2603 uint16_t viewport_start[3]; 2604 uint16_t viewport_size[3]; // for now size will be the number of lines perpendicular to scan direction (height for 0 / 180, width for 90 and 270) 2605 uint16_t viewport_start_c[3]; 2606 uint16_t viewport_size_c[3]; 2607 uint16_t surface_pitch[3]; 2608 uint16_t surface_pitch_c[3]; 2609 uint16_t surface_height[3]; 2610 uint16_t surface_height_c[3]; 2611 uint8_t element_size[3]; 2612 uint8_t element_size_c[3]; 2613 uint8_t swizzle_mode[3]; // TODO: Add mapping, should be value used in LSDMA command 2614 uint8_t vready_offset_lines; // vready offset from vstartup in lines (rounded up, as the actual offset may be a fraction of a line) 2615 uint16_t dst_y_prefetch_x1000[3]; 2616 uint16_t total_swaths[3]; 2617 uint16_t total_swaths_c[3]; 2618 uint8_t prefetch_swaths[3]; 2619 uint8_t prefetch_swaths_c[3]; 2620 uint8_t swath_height[3]; 2621 uint8_t swath_height_c[3]; 2622 uint16_t block_256b_width[3]; 2623 uint16_t block_256b_height[3]; 2624 uint16_t block_256b_width_c[3]; 2625 uint16_t block_256b_height_c[3]; 2626 uint16_t macro_tile_width[3]; 2627 uint16_t macro_tile_width_c[3]; 2628 union { 2629 struct { 2630 uint8_t is_multi_planar : 1; 2631 uint8_t is_yuv420 : 1; 2632 uint8_t prefetch_relative_vblank : 1; 2633 uint8_t vertical_access : 1; // vertical_access = 1 means 90 or 270 rotation 2634 uint8_t access_direction : 1; // access_direction = 1 means bigger to smaller coordinations (e.g., scan from 2160 to 0 as opposed to regular 0 to 2160) 2635 uint8_t dcc : 1; 2636 uint8_t tmz : 1; // TODO: Need to assign outside of DML (DML not aware of TMZ) 2637 } bits; 2638 uint8_t all; 2639 } config[3]; 2640 uint8_t max_cursor_size; 2641 uint16_t pre_hdl_delta_x1000[3]; 2642 uint16_t pre_hdl_delta_c_x1000[3]; 2643 uint16_t rec_hdl_delta_x1000[3]; 2644 uint16_t rec_hdl_delta_c_x1000[3]; 2645 uint16_t dst_y_per_vm_vblank_x1000[3]; 2646 uint16_t dst_y_per_row_vblank_x1000[3]; 2647 uint16_t dst_y_after_scaler[3]; 2648 uint16_t vinit_prefill[3]; 2649 uint16_t vinit_prefill_c[3]; 2650 uint16_t vratio_x1000[3]; 2651 uint16_t vratio_c_x1000[3]; 2652 struct plane_pipe_rect pipe_viewports[4]; 2653 /* TODO - remove these deprecated vars */ 2654 uint32_t pipe_copy_offset[2][4]; // [2] - SVP0/1, [4] - 4 pipes 2655 uint32_t pipe_copy_offset_c[2][4]; 2656 /* bits 47:16 of the surface address */ 2657 uint32_t pipe_copy_addr_47_16[2][4]; // [2] - SVP0/1, [4] - 4 pipes 2658 uint32_t pipe_copy_addr_47_16_c[2][4]; 2659 uint32_t pipe_copy_max_size[2][4]; 2660 uint32_t pipe_copy_max_size_c[2][4]; 2661 }; 2662 2663 /* static stream state */ 2664 struct dmub_fams2_legacy_stream_static_state { 2665 uint8_t vactive_det_fill_delay_otg_vlines; 2666 uint8_t programming_delay_otg_vlines; 2667 }; //v0 2668 2669 struct dmub_fams2_subvp_stream_static_state { 2670 uint16_t vratio_numerator; 2671 uint16_t vratio_denominator; 2672 uint16_t phantom_vtotal; 2673 uint16_t phantom_vactive; 2674 union { 2675 struct { 2676 uint8_t is_multi_planar : 1; 2677 uint8_t is_yuv420 : 1; 2678 } bits; 2679 uint8_t all; 2680 } config; 2681 uint8_t programming_delay_otg_vlines; 2682 uint8_t prefetch_to_mall_otg_vlines; 2683 uint8_t phantom_otg_inst; 2684 uint8_t phantom_pipe_mask; 2685 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2686 }; //v0 2687 2688 struct dmub_fams2_drr_stream_static_state { 2689 uint16_t nom_stretched_vtotal; 2690 uint8_t programming_delay_otg_vlines; 2691 uint8_t only_stretch_if_required; 2692 uint8_t pad[2]; 2693 }; //v0 2694 2695 struct dmub_fams2_cmd_legacy_stream_static_state { 2696 uint16_t vactive_det_fill_delay_otg_vlines; 2697 uint16_t programming_delay_otg_vlines; 2698 uint32_t disallow_time_us; 2699 }; //v1 2700 2701 struct dmub_fams2_cmd_subvp_stream_static_state { 2702 uint16_t vratio_numerator; 2703 uint16_t vratio_denominator; 2704 uint16_t phantom_vtotal; 2705 uint16_t phantom_vactive; 2706 uint16_t programming_delay_otg_vlines; 2707 uint16_t prefetch_to_mall_otg_vlines; 2708 union { 2709 struct { 2710 uint8_t is_multi_planar : 1; 2711 uint8_t is_yuv420 : 1; 2712 } bits; 2713 uint8_t all; 2714 } config; 2715 uint8_t phantom_otg_inst; 2716 uint8_t phantom_pipe_mask; 2717 uint8_t pad0; 2718 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2719 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2720 }; //v1 2721 2722 struct dmub_fams2_cmd_drr_stream_static_state { 2723 uint16_t nom_stretched_vtotal; 2724 uint16_t programming_delay_otg_vlines; 2725 uint8_t only_stretch_if_required; 2726 uint8_t pad[3]; 2727 }; //v1 2728 2729 union dmub_fams2_stream_static_sub_state { 2730 struct dmub_fams2_legacy_stream_static_state legacy; 2731 struct dmub_fams2_subvp_stream_static_state subvp; 2732 struct dmub_fams2_drr_stream_static_state drr; 2733 }; //v0 2734 2735 union dmub_fams2_cmd_stream_static_sub_state { 2736 COMMON_STREAM_STATIC_SUB_STATE 2737 }; //v1 2738 2739 union dmub_fams2_stream_static_sub_state_v2 { 2740 COMMON_STREAM_STATIC_SUB_STATE 2741 struct dmub_fams2_cmd_alternate_stream_static_state alternate; 2742 }; //v2 2743 2744 struct dmub_fams2_stream_static_state { 2745 enum fams2_stream_type type; 2746 uint32_t otg_vline_time_ns; 2747 uint32_t otg_vline_time_ticks; 2748 uint16_t htotal; 2749 uint16_t vtotal; // nominal vtotal 2750 uint16_t vblank_start; 2751 uint16_t vblank_end; 2752 uint16_t max_vtotal; 2753 uint16_t allow_start_otg_vline; 2754 uint16_t allow_end_otg_vline; 2755 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2756 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2757 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2758 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2759 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2760 union { 2761 struct { 2762 uint8_t is_drr : 1; // stream is DRR enabled 2763 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2764 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2765 } bits; 2766 uint8_t all; 2767 } config; 2768 uint8_t otg_inst; 2769 uint8_t pipe_mask; // pipe mask for the whole config 2770 uint8_t num_planes; 2771 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2772 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2773 union dmub_fams2_stream_static_sub_state sub_state; 2774 }; //v0 2775 2776 struct dmub_fams2_cmd_stream_static_base_state { 2777 enum fams2_stream_type type; 2778 uint32_t otg_vline_time_ns; 2779 uint32_t otg_vline_time_ticks; 2780 uint16_t htotal; 2781 uint16_t vtotal; // nominal vtotal 2782 uint16_t vblank_start; 2783 uint16_t vblank_end; 2784 uint16_t max_vtotal; 2785 uint16_t allow_start_otg_vline; 2786 uint16_t allow_end_otg_vline; 2787 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2788 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2789 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2790 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2791 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2792 union { 2793 struct { 2794 uint8_t is_drr : 1; // stream is DRR enabled 2795 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2796 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2797 } bits; 2798 uint8_t all; 2799 } config; 2800 uint8_t otg_inst; 2801 uint8_t pipe_mask; // pipe mask for the whole config 2802 uint8_t num_planes; 2803 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2804 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2805 }; //v1 2806 2807 struct dmub_fams2_stream_static_state_v1 { 2808 struct dmub_fams2_cmd_stream_static_base_state base; 2809 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2810 }; //v1 2811 2812 /** 2813 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2814 * p-state request to allow latency 2815 */ 2816 enum dmub_fams2_allow_delay_check_mode { 2817 /* No check for request to allow delay */ 2818 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2819 /* Check for request to allow delay */ 2820 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2821 /* Check for prepare to allow delay */ 2822 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2823 }; 2824 2825 union dmub_fams2_global_feature_config { 2826 struct { 2827 uint32_t enable: 1; 2828 uint32_t enable_ppt_check: 1; 2829 uint32_t enable_stall_recovery: 1; 2830 uint32_t enable_debug: 1; 2831 uint32_t enable_offload_flip: 1; 2832 uint32_t enable_visual_confirm: 1; 2833 uint32_t allow_delay_check_mode: 2; 2834 uint32_t legacy_method_no_fams2 : 1; 2835 uint32_t alternate_channel_workaround : 1; 2836 uint32_t reserved: 22; 2837 } bits; 2838 uint32_t all; 2839 }; 2840 2841 struct dmub_cmd_fams2_global_config { 2842 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2843 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2844 uint32_t num_streams; 2845 union dmub_fams2_global_feature_config features; 2846 uint32_t recovery_timeout_us; 2847 uint32_t hwfq_flip_programming_delay_us; 2848 uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target 2849 }; 2850 2851 union dmub_cmd_fams2_config { 2852 struct dmub_cmd_fams2_global_config global; 2853 struct dmub_fams2_stream_static_state stream; //v0 2854 union { 2855 struct dmub_fams2_cmd_stream_static_base_state base; 2856 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2857 } stream_v1; //v1 2858 }; 2859 2860 struct dmub_fams2_config_v2 { 2861 struct dmub_cmd_fams2_global_config global; 2862 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2863 }; 2864 2865 /** 2866 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2867 */ 2868 struct dmub_rb_cmd_fams2 { 2869 struct dmub_cmd_header header; 2870 union dmub_cmd_fams2_config config; 2871 }; 2872 2873 /** 2874 * Indirect buffer descriptor 2875 */ 2876 struct dmub_ib_data { 2877 union dmub_addr src; // location of indirect buffer in memory 2878 uint16_t size; // indirect buffer size in bytes 2879 }; 2880 2881 /** 2882 * DMUB rb command definition for commands passed over indirect buffer 2883 */ 2884 struct dmub_rb_cmd_ib { 2885 struct dmub_cmd_header header; 2886 struct dmub_ib_data ib_data; 2887 }; 2888 2889 /** 2890 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2891 */ 2892 enum dmub_cmd_idle_opt_type { 2893 /** 2894 * DCN hardware restore. 2895 */ 2896 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2897 2898 /** 2899 * DCN hardware save. 2900 */ 2901 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2902 2903 /** 2904 * DCN hardware notify idle. 2905 */ 2906 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2907 2908 /** 2909 * DCN hardware notify power state. 2910 */ 2911 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2912 2913 /** 2914 * DCN notify to release HW. 2915 */ 2916 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2917 }; 2918 2919 /** 2920 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2921 */ 2922 struct dmub_rb_cmd_idle_opt_dcn_restore { 2923 struct dmub_cmd_header header; /**< header */ 2924 }; 2925 2926 /** 2927 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2928 */ 2929 struct dmub_dcn_notify_idle_cntl_data { 2930 uint8_t driver_idle; 2931 uint8_t skip_otg_disable; 2932 uint8_t reserved[58]; 2933 }; 2934 2935 /** 2936 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2937 */ 2938 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2939 struct dmub_cmd_header header; /**< header */ 2940 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2941 }; 2942 2943 /** 2944 * enum dmub_idle_opt_dc_power_state - DC power states. 2945 */ 2946 enum dmub_idle_opt_dc_power_state { 2947 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2948 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2949 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2950 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2951 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2952 }; 2953 2954 /** 2955 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2956 */ 2957 struct dmub_idle_opt_set_dc_power_state_data { 2958 uint8_t power_state; /**< power state */ 2959 uint8_t pad[3]; /**< padding */ 2960 }; 2961 2962 /** 2963 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2964 */ 2965 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2966 struct dmub_cmd_header header; /**< header */ 2967 struct dmub_idle_opt_set_dc_power_state_data data; 2968 }; 2969 2970 /** 2971 * struct dmub_clocks - Clock update notification. 2972 */ 2973 struct dmub_clocks { 2974 uint32_t dispclk_khz; /**< dispclk kHz */ 2975 uint32_t dppclk_khz; /**< dppclk kHz */ 2976 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2977 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2978 }; 2979 2980 /** 2981 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2982 */ 2983 enum dmub_cmd_clk_mgr_type { 2984 /** 2985 * Notify DMCUB of clock update. 2986 */ 2987 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2988 }; 2989 2990 /** 2991 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2992 */ 2993 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2994 struct dmub_cmd_header header; /**< header */ 2995 struct dmub_clocks clocks; /**< clock data */ 2996 }; 2997 2998 /** 2999 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 3000 */ 3001 struct dmub_cmd_digx_encoder_control_data { 3002 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 3003 }; 3004 3005 /** 3006 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 3007 */ 3008 struct dmub_rb_cmd_digx_encoder_control { 3009 struct dmub_cmd_header header; /**< header */ 3010 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 3011 }; 3012 3013 /** 3014 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 3015 */ 3016 struct dmub_cmd_set_pixel_clock_data { 3017 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 3018 }; 3019 3020 /** 3021 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 3022 */ 3023 struct dmub_rb_cmd_set_pixel_clock { 3024 struct dmub_cmd_header header; /**< header */ 3025 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 3026 }; 3027 3028 /** 3029 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 3030 */ 3031 struct dmub_cmd_enable_disp_power_gating_data { 3032 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 3033 }; 3034 3035 /** 3036 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 3037 */ 3038 struct dmub_rb_cmd_enable_disp_power_gating { 3039 struct dmub_cmd_header header; /**< header */ 3040 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 3041 }; 3042 3043 /** 3044 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 3045 */ 3046 struct dmub_dig_transmitter_control_data_v1_7 { 3047 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3048 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 3049 union { 3050 uint8_t digmode; /**< enum atom_encode_mode_def */ 3051 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 3052 uint8_t txffe; /**< TxFFE settings for HDMI 2.1 */ 3053 } mode_laneset; 3054 uint8_t lanenum; /**< Number of lanes */ 3055 union { 3056 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 3057 uint32_t symclk_Hz; /**< Symbol clock in Hz for FRL */ 3058 } symclk_units; 3059 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 3060 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 3061 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 3062 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 3063 uint8_t TxFFELaneSel; /**< TxFFE lane select [3:0] 3064 (bit0: lane0, bit1: lane1, bit2: lane3, bit3: lane3) */ 3065 uint8_t skip_phy_ssc_reduction; 3066 uint8_t reserved2[2]; /**< For future use */ 3067 uint32_t reserved3[11]; /**< For future use */ 3068 }; 3069 3070 /** 3071 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 3072 */ 3073 union dmub_cmd_dig1_transmitter_control_data { 3074 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 3075 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 3076 }; 3077 3078 /** 3079 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 3080 */ 3081 struct dmub_rb_cmd_dig1_transmitter_control { 3082 struct dmub_cmd_header header; /**< header */ 3083 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 3084 }; 3085 3086 /** 3087 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 3088 */ 3089 struct dmub_rb_cmd_domain_control_data { 3090 uint8_t inst : 6; /**< DOMAIN instance to control */ 3091 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 3092 uint8_t reserved[3]; /**< Reserved for future use */ 3093 }; 3094 3095 /** 3096 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 3097 */ 3098 struct dmub_rb_cmd_domain_control { 3099 struct dmub_cmd_header header; /**< header */ 3100 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 3101 }; 3102 3103 /** 3104 * DPIA tunnel command parameters. 3105 */ 3106 struct dmub_cmd_dig_dpia_control_data { 3107 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 3108 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 3109 union { 3110 uint8_t digmode; /** enum atom_encode_mode_def */ 3111 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 3112 } mode_laneset; 3113 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 3114 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 3115 uint8_t hpdsel; /** =0: HPD is not assigned */ 3116 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 3117 uint8_t dpia_id; /** Index of DPIA */ 3118 uint8_t fec_rdy : 1; 3119 uint8_t reserved : 7; 3120 uint32_t reserved1; 3121 }; 3122 3123 /** 3124 * DMUB command for DPIA tunnel control. 3125 */ 3126 struct dmub_rb_cmd_dig1_dpia_control { 3127 struct dmub_cmd_header header; 3128 struct dmub_cmd_dig_dpia_control_data dpia_control; 3129 }; 3130 3131 /** 3132 * SET_CONFIG Command Payload (deprecated) 3133 */ 3134 struct set_config_cmd_payload { 3135 uint8_t msg_type; /* set config message type */ 3136 uint8_t msg_data; /* set config message data */ 3137 }; 3138 3139 /** 3140 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 3141 */ 3142 struct dmub_cmd_set_config_control_data { 3143 struct set_config_cmd_payload cmd_pkt; 3144 uint8_t instance; /* DPIA instance */ 3145 uint8_t immed_status; /* Immediate status returned in case of error */ 3146 }; 3147 3148 /** 3149 * SET_CONFIG Request Command Payload 3150 */ 3151 struct set_config_request_cmd_payload { 3152 uint8_t instance; /* DPIA instance */ 3153 uint8_t immed_status; /* Immediate status returned in case of error */ 3154 uint8_t msg_type; /* set config message type */ 3155 uint8_t reserved; 3156 uint32_t msg_data; /* set config message data */ 3157 }; 3158 3159 /** 3160 * DMUB command structure for SET_CONFIG command. 3161 */ 3162 struct dmub_rb_cmd_set_config_access { 3163 struct dmub_cmd_header header; /* header */ 3164 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 3165 }; 3166 3167 /** 3168 * DMUB command structure for SET_CONFIG request command. 3169 */ 3170 struct dmub_rb_cmd_set_config_request { 3171 struct dmub_cmd_header header; /* header */ 3172 struct set_config_request_cmd_payload payload; /* set config request payload */ 3173 }; 3174 3175 /** 3176 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3177 */ 3178 struct dmub_cmd_mst_alloc_slots_control_data { 3179 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 3180 uint8_t instance; /* DPIA instance */ 3181 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 3182 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 3183 }; 3184 3185 /** 3186 * DMUB command structure for SET_ command. 3187 */ 3188 struct dmub_rb_cmd_set_mst_alloc_slots { 3189 struct dmub_cmd_header header; /* header */ 3190 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 3191 }; 3192 3193 /** 3194 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 3195 */ 3196 struct dmub_cmd_tps_notification_data { 3197 uint8_t instance; /* DPIA instance */ 3198 uint8_t tps; /* requested training pattern */ 3199 uint8_t reserved1; 3200 uint8_t reserved2; 3201 }; 3202 3203 /** 3204 * DMUB command structure for SET_TPS_NOTIFICATION command. 3205 */ 3206 struct dmub_rb_cmd_set_tps_notification { 3207 struct dmub_cmd_header header; /* header */ 3208 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 3209 }; 3210 3211 /** 3212 * DMUB command structure for DPIA HPD int enable control. 3213 */ 3214 struct dmub_rb_cmd_dpia_hpd_int_enable { 3215 struct dmub_cmd_header header; /* header */ 3216 uint32_t enable; /* dpia hpd interrupt enable */ 3217 }; 3218 3219 /** 3220 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 3221 */ 3222 struct dmub_rb_cmd_dpphy_init { 3223 struct dmub_cmd_header header; /**< header */ 3224 uint8_t reserved[60]; /**< reserved bits */ 3225 }; 3226 3227 /** 3228 * enum dp_aux_request_action - DP AUX request command listing. 3229 * 3230 * 4 AUX request command bits are shifted to high nibble. 3231 */ 3232 enum dp_aux_request_action { 3233 /** I2C-over-AUX write request */ 3234 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 3235 /** I2C-over-AUX read request */ 3236 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 3237 /** I2C-over-AUX write status request */ 3238 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 3239 /** I2C-over-AUX write request with MOT=1 */ 3240 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 3241 /** I2C-over-AUX read request with MOT=1 */ 3242 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 3243 /** I2C-over-AUX write status request with MOT=1 */ 3244 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 3245 /** Native AUX write request */ 3246 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 3247 /** Native AUX read request */ 3248 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 3249 }; 3250 3251 /** 3252 * enum aux_return_code_type - DP AUX process return code listing. 3253 */ 3254 enum aux_return_code_type { 3255 /** AUX process succeeded */ 3256 AUX_RET_SUCCESS = 0, 3257 /** AUX process failed with unknown reason */ 3258 AUX_RET_ERROR_UNKNOWN, 3259 /** AUX process completed with invalid reply */ 3260 AUX_RET_ERROR_INVALID_REPLY, 3261 /** AUX process timed out */ 3262 AUX_RET_ERROR_TIMEOUT, 3263 /** HPD was low during AUX process */ 3264 AUX_RET_ERROR_HPD_DISCON, 3265 /** Failed to acquire AUX engine */ 3266 AUX_RET_ERROR_ENGINE_ACQUIRE, 3267 /** AUX request not supported */ 3268 AUX_RET_ERROR_INVALID_OPERATION, 3269 /** AUX process not available */ 3270 AUX_RET_ERROR_PROTOCOL_ERROR, 3271 }; 3272 3273 /** 3274 * enum aux_channel_type - DP AUX channel type listing. 3275 */ 3276 enum aux_channel_type { 3277 /** AUX thru Legacy DP AUX */ 3278 AUX_CHANNEL_LEGACY_DDC, 3279 /** AUX thru DPIA DP tunneling */ 3280 AUX_CHANNEL_DPIA 3281 }; 3282 3283 /** 3284 * struct aux_transaction_parameters - DP AUX request transaction data 3285 */ 3286 struct aux_transaction_parameters { 3287 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 3288 uint8_t action; /**< enum dp_aux_request_action */ 3289 uint8_t length; /**< DP AUX request data length */ 3290 uint8_t reserved; /**< For future use */ 3291 uint32_t address; /**< DP AUX address */ 3292 uint8_t data[16]; /**< DP AUX write data */ 3293 }; 3294 3295 /** 3296 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3297 */ 3298 struct dmub_cmd_dp_aux_control_data { 3299 uint8_t instance; /**< AUX instance or DPIA instance */ 3300 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 3301 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 3302 uint8_t reserved0; /**< For future use */ 3303 uint16_t timeout; /**< timeout time in us */ 3304 uint16_t reserved1; /**< For future use */ 3305 enum aux_channel_type type; /**< enum aux_channel_type */ 3306 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 3307 }; 3308 3309 /** 3310 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3311 */ 3312 struct dmub_rb_cmd_dp_aux_access { 3313 /** 3314 * Command header. 3315 */ 3316 struct dmub_cmd_header header; 3317 /** 3318 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3319 */ 3320 struct dmub_cmd_dp_aux_control_data aux_control; 3321 }; 3322 3323 /** 3324 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3325 */ 3326 struct dmub_rb_cmd_outbox1_enable { 3327 /** 3328 * Command header. 3329 */ 3330 struct dmub_cmd_header header; 3331 /** 3332 * enable: 0x0 -> disable outbox1 notification (default value) 3333 * 0x1 -> enable outbox1 notification 3334 */ 3335 uint32_t enable; 3336 }; 3337 3338 /* DP AUX Reply command - OutBox Cmd */ 3339 /** 3340 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3341 */ 3342 struct aux_reply_data { 3343 /** 3344 * Aux cmd 3345 */ 3346 uint8_t command; 3347 /** 3348 * Aux reply data length (max: 16 bytes) 3349 */ 3350 uint8_t length; 3351 /** 3352 * Alignment only 3353 */ 3354 uint8_t pad[2]; 3355 /** 3356 * Aux reply data 3357 */ 3358 uint8_t data[16]; 3359 }; 3360 3361 /** 3362 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3363 */ 3364 struct aux_reply_control_data { 3365 /** 3366 * Reserved for future use 3367 */ 3368 uint32_t handle; 3369 /** 3370 * Aux Instance 3371 */ 3372 uint8_t instance; 3373 /** 3374 * Aux transaction result: definition in enum aux_return_code_type 3375 */ 3376 uint8_t result; 3377 /** 3378 * Alignment only 3379 */ 3380 uint16_t pad; 3381 }; 3382 3383 /** 3384 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 3385 */ 3386 struct dmub_rb_cmd_dp_aux_reply { 3387 /** 3388 * Command header. 3389 */ 3390 struct dmub_cmd_header header; 3391 /** 3392 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3393 */ 3394 struct aux_reply_control_data control; 3395 /** 3396 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3397 */ 3398 struct aux_reply_data reply_data; 3399 }; 3400 3401 /* DP HPD Notify command - OutBox Cmd */ 3402 /** 3403 * DP HPD Type 3404 */ 3405 enum dp_hpd_type { 3406 /** 3407 * Normal DP HPD 3408 */ 3409 DP_HPD = 0, 3410 /** 3411 * DP HPD short pulse 3412 */ 3413 DP_IRQ = 1, 3414 /** 3415 * Failure to acquire DP HPD state 3416 */ 3417 DP_NONE_HPD = 2 3418 }; 3419 3420 /** 3421 * DP HPD Status 3422 */ 3423 enum dp_hpd_status { 3424 /** 3425 * DP_HPD status low 3426 */ 3427 DP_HPD_UNPLUG = 0, 3428 /** 3429 * DP_HPD status high 3430 */ 3431 DP_HPD_PLUG 3432 }; 3433 3434 /** 3435 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3436 */ 3437 struct dp_hpd_data { 3438 /** 3439 * DP HPD instance 3440 */ 3441 uint8_t instance; 3442 /** 3443 * HPD type 3444 */ 3445 uint8_t hpd_type; 3446 /** 3447 * HPD status: only for type: DP_HPD to indicate status 3448 */ 3449 uint8_t hpd_status; 3450 /** 3451 * Alignment only 3452 */ 3453 uint8_t pad; 3454 }; 3455 3456 /** 3457 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3458 */ 3459 struct dmub_rb_cmd_dp_hpd_notify { 3460 /** 3461 * Command header. 3462 */ 3463 struct dmub_cmd_header header; 3464 /** 3465 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3466 */ 3467 struct dp_hpd_data hpd_data; 3468 }; 3469 3470 /** 3471 * Definition of a SET_CONFIG reply from DPOA. 3472 */ 3473 enum set_config_status { 3474 SET_CONFIG_PENDING = 0, 3475 SET_CONFIG_ACK_RECEIVED, 3476 SET_CONFIG_RX_TIMEOUT, 3477 SET_CONFIG_UNKNOWN_ERROR, 3478 }; 3479 3480 /** 3481 * Definition of a set_config reply 3482 */ 3483 struct set_config_reply_control_data { 3484 uint8_t instance; /* DPIA Instance */ 3485 uint8_t status; /* Set Config reply */ 3486 uint16_t pad; /* Alignment */ 3487 }; 3488 3489 /** 3490 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 3491 */ 3492 struct dmub_rb_cmd_dp_set_config_reply { 3493 struct dmub_cmd_header header; 3494 struct set_config_reply_control_data set_config_reply_control; 3495 }; 3496 3497 /** 3498 * Definition of a DPIA notification header 3499 */ 3500 struct dpia_notification_header { 3501 uint8_t instance; /**< DPIA Instance */ 3502 uint8_t reserved[3]; 3503 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 3504 }; 3505 3506 /** 3507 * Definition of the common data struct of DPIA notification 3508 */ 3509 struct dpia_notification_common { 3510 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 3511 - sizeof(struct dpia_notification_header)]; 3512 }; 3513 3514 /** 3515 * Definition of a DPIA notification data 3516 */ 3517 struct dpia_bw_allocation_notify_data { 3518 union { 3519 struct { 3520 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3521 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3522 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3523 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3524 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3525 uint16_t reserved: 11; /**< Reserved */ 3526 } bits; 3527 3528 uint16_t flags; 3529 }; 3530 3531 uint8_t cm_id; /**< CM ID */ 3532 uint8_t group_id; /**< Group ID */ 3533 uint8_t granularity; /**< BW Allocation Granularity */ 3534 uint8_t estimated_bw; /**< Estimated_BW */ 3535 uint8_t allocated_bw; /**< Allocated_BW */ 3536 uint8_t reserved; 3537 }; 3538 3539 /** 3540 * union dpia_notify_data_type - DPIA Notification in Outbox command 3541 */ 3542 union dpia_notification_data { 3543 /** 3544 * DPIA Notification for common data struct 3545 */ 3546 struct dpia_notification_common common_data; 3547 3548 /** 3549 * DPIA Notification for DP BW Allocation support 3550 */ 3551 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3552 }; 3553 3554 /** 3555 * Definition of a DPIA notification payload 3556 */ 3557 struct dpia_notification_payload { 3558 struct dpia_notification_header header; 3559 union dpia_notification_data data; /**< DPIA notification payload data */ 3560 }; 3561 3562 /** 3563 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3564 */ 3565 struct dmub_rb_cmd_dpia_notification { 3566 struct dmub_cmd_header header; /**< DPIA notification header */ 3567 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3568 }; 3569 3570 /** 3571 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3572 */ 3573 struct dmub_cmd_hpd_state_query_data { 3574 uint8_t instance; /**< HPD instance or DPIA instance */ 3575 uint8_t result; /**< For returning HPD state */ 3576 uint16_t pad; /** < Alignment */ 3577 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3578 enum aux_return_code_type status; /**< for returning the status of command */ 3579 }; 3580 3581 /** 3582 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3583 */ 3584 struct dmub_rb_cmd_query_hpd_state { 3585 /** 3586 * Command header. 3587 */ 3588 struct dmub_cmd_header header; 3589 /** 3590 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3591 */ 3592 struct dmub_cmd_hpd_state_query_data data; 3593 }; 3594 3595 /** 3596 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3597 */ 3598 struct dmub_rb_cmd_hpd_sense_notify_data { 3599 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3600 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3601 }; 3602 3603 /** 3604 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3605 */ 3606 struct dmub_rb_cmd_hpd_sense_notify { 3607 struct dmub_cmd_header header; /**< header */ 3608 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3609 }; 3610 3611 /* 3612 * Command IDs should be treated as stable ABI. 3613 * Do not reuse or modify IDs. 3614 */ 3615 3616 /** 3617 * PSR command sub-types. 3618 */ 3619 enum dmub_cmd_psr_type { 3620 /** 3621 * Set PSR version support. 3622 */ 3623 DMUB_CMD__PSR_SET_VERSION = 0, 3624 /** 3625 * Copy driver-calculated parameters to PSR state. 3626 */ 3627 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3628 /** 3629 * Enable PSR. 3630 */ 3631 DMUB_CMD__PSR_ENABLE = 2, 3632 3633 /** 3634 * Disable PSR. 3635 */ 3636 DMUB_CMD__PSR_DISABLE = 3, 3637 3638 /** 3639 * Set PSR level. 3640 * PSR level is a 16-bit value dicated by driver that 3641 * will enable/disable different functionality. 3642 */ 3643 DMUB_CMD__PSR_SET_LEVEL = 4, 3644 3645 /** 3646 * Forces PSR enabled until an explicit PSR disable call. 3647 */ 3648 DMUB_CMD__PSR_FORCE_STATIC = 5, 3649 /** 3650 * Set vtotal in psr active for FreeSync PSR. 3651 */ 3652 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3653 /** 3654 * Set PSR power option 3655 */ 3656 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3657 }; 3658 3659 /** 3660 * Different PSR residency modes. 3661 * Different modes change the definition of PSR residency. 3662 */ 3663 enum psr_residency_mode { 3664 PSR_RESIDENCY_MODE_PHY = 0, 3665 PSR_RESIDENCY_MODE_ALPM, 3666 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3667 /* Do not add below. */ 3668 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3669 }; 3670 3671 enum dmub_cmd_fams_type { 3672 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3673 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3674 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3675 /** 3676 * For SubVP set manual trigger in FW because it 3677 * triggers DRR_UPDATE_PENDING which SubVP relies 3678 * on (for any SubVP cases that use a DRR display) 3679 */ 3680 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3681 DMUB_CMD__FAMS2_CONFIG = 4, 3682 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3683 DMUB_CMD__FAMS2_FLIP = 6, 3684 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3685 DMUB_CMD__FAMS2_IB_DEBUG_META = 8, 3686 }; 3687 3688 /** 3689 * PSR versions. 3690 */ 3691 enum psr_version { 3692 /** 3693 * PSR version 1. 3694 */ 3695 PSR_VERSION_1 = 0, 3696 /** 3697 * Freesync PSR SU. 3698 */ 3699 PSR_VERSION_SU_1 = 1, 3700 /** 3701 * PSR not supported. 3702 */ 3703 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3704 }; 3705 3706 /** 3707 * PHY Link rate for DP. 3708 */ 3709 enum phy_link_rate { 3710 /** 3711 * not supported. 3712 */ 3713 PHY_RATE_UNKNOWN = 0, 3714 /** 3715 * Rate_1 (RBR) - 1.62 Gbps/Lane 3716 */ 3717 PHY_RATE_162 = 1, 3718 /** 3719 * Rate_2 - 2.16 Gbps/Lane 3720 */ 3721 PHY_RATE_216 = 2, 3722 /** 3723 * Rate_3 - 2.43 Gbps/Lane 3724 */ 3725 PHY_RATE_243 = 3, 3726 /** 3727 * Rate_4 (HBR) - 2.70 Gbps/Lane 3728 */ 3729 PHY_RATE_270 = 4, 3730 /** 3731 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3732 */ 3733 PHY_RATE_324 = 5, 3734 /** 3735 * Rate_6 - 4.32 Gbps/Lane 3736 */ 3737 PHY_RATE_432 = 6, 3738 /** 3739 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3740 */ 3741 PHY_RATE_540 = 7, 3742 /** 3743 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3744 */ 3745 PHY_RATE_810 = 8, 3746 /** 3747 * UHBR10 - 10.0 Gbps/Lane 3748 */ 3749 PHY_RATE_1000 = 9, 3750 /** 3751 * UHBR13.5 - 13.5 Gbps/Lane 3752 */ 3753 PHY_RATE_1350 = 10, 3754 /** 3755 * UHBR10 - 20.0 Gbps/Lane 3756 */ 3757 PHY_RATE_2000 = 11, 3758 3759 PHY_RATE_675 = 12, 3760 /** 3761 * Rate 12 - 6.75 Gbps/Lane 3762 */ 3763 }; 3764 3765 /** 3766 * enum dmub_phy_fsm_state - PHY FSM states. 3767 * PHY FSM state to transit to during PSR enable/disable. 3768 */ 3769 enum dmub_phy_fsm_state { 3770 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3771 DMUB_PHY_FSM_RESET, 3772 DMUB_PHY_FSM_RESET_RELEASED, 3773 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3774 DMUB_PHY_FSM_INITIALIZED, 3775 DMUB_PHY_FSM_CALIBRATED, 3776 DMUB_PHY_FSM_CALIBRATED_LP, 3777 DMUB_PHY_FSM_CALIBRATED_PG, 3778 DMUB_PHY_FSM_POWER_DOWN, 3779 DMUB_PHY_FSM_PLL_EN, 3780 DMUB_PHY_FSM_TX_EN, 3781 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3782 DMUB_PHY_FSM_FAST_LP, 3783 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3784 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3785 DMUB_PHY_FSM_P2_PLL_OFF, 3786 DMUB_PHY_FSM_P2_PLL_ON, 3787 }; 3788 3789 /** 3790 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3791 */ 3792 struct dmub_cmd_psr_copy_settings_data { 3793 /** 3794 * Flags that can be set by driver to change some PSR behaviour. 3795 */ 3796 union dmub_psr_debug_flags debug; 3797 /** 3798 * 16-bit value dicated by driver that will enable/disable different functionality. 3799 */ 3800 uint16_t psr_level; 3801 /** 3802 * DPP HW instance. 3803 */ 3804 uint8_t dpp_inst; 3805 /** 3806 * MPCC HW instance. 3807 * Not used in dmub fw, 3808 * dmub fw will get active opp by reading odm registers. 3809 */ 3810 uint8_t mpcc_inst; 3811 /** 3812 * OPP HW instance. 3813 * Not used in dmub fw, 3814 * dmub fw will get active opp by reading odm registers. 3815 */ 3816 uint8_t opp_inst; 3817 /** 3818 * OTG HW instance. 3819 */ 3820 uint8_t otg_inst; 3821 /** 3822 * DIG FE HW instance. 3823 */ 3824 uint8_t digfe_inst; 3825 /** 3826 * DIG BE HW instance. 3827 */ 3828 uint8_t digbe_inst; 3829 /** 3830 * DP PHY HW instance. 3831 */ 3832 uint8_t dpphy_inst; 3833 /** 3834 * AUX HW instance. 3835 */ 3836 uint8_t aux_inst; 3837 /** 3838 * Determines if SMU optimzations are enabled/disabled. 3839 */ 3840 uint8_t smu_optimizations_en; 3841 /** 3842 * Unused. 3843 * TODO: Remove. 3844 */ 3845 uint8_t frame_delay; 3846 /** 3847 * If RFB setup time is greater than the total VBLANK time, 3848 * it is not possible for the sink to capture the video frame 3849 * in the same frame the SDP is sent. In this case, 3850 * the frame capture indication bit should be set and an extra 3851 * static frame should be transmitted to the sink. 3852 */ 3853 uint8_t frame_cap_ind; 3854 /** 3855 * Granularity of Y offset supported by sink. 3856 */ 3857 uint8_t su_y_granularity; 3858 /** 3859 * Indicates whether sink should start capturing 3860 * immediately following active scan line, 3861 * or starting with the 2nd active scan line. 3862 */ 3863 uint8_t line_capture_indication; 3864 /** 3865 * Multi-display optimizations are implemented on certain ASICs. 3866 */ 3867 uint8_t multi_disp_optimizations_en; 3868 /** 3869 * The last possible line SDP may be transmitted without violating 3870 * the RFB setup time or entering the active video frame. 3871 */ 3872 uint16_t init_sdp_deadline; 3873 /** 3874 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3875 */ 3876 uint8_t rate_control_caps; 3877 /* 3878 * Force PSRSU always doing full frame update 3879 */ 3880 uint8_t force_ffu_mode; 3881 /** 3882 * Length of each horizontal line in us. 3883 */ 3884 uint32_t line_time_in_us; 3885 /** 3886 * FEC enable status in driver 3887 */ 3888 uint8_t fec_enable_status; 3889 /** 3890 * FEC re-enable delay when PSR exit. 3891 * unit is 100us, range form 0~255(0xFF). 3892 */ 3893 uint8_t fec_enable_delay_in100us; 3894 /** 3895 * PSR control version. 3896 */ 3897 uint8_t cmd_version; 3898 /** 3899 * Panel Instance. 3900 * Panel instance to identify which psr_state to use 3901 * Currently the support is only for 0 or 1 3902 */ 3903 uint8_t panel_inst; 3904 /* 3905 * DSC enable status in driver 3906 */ 3907 uint8_t dsc_enable_status; 3908 /* 3909 * Use FSM state for PSR power up/down 3910 */ 3911 uint8_t use_phy_fsm; 3912 /** 3913 * frame delay for frame re-lock 3914 */ 3915 uint8_t relock_delay_frame_cnt; 3916 /** 3917 * esd recovery indicate. 3918 */ 3919 uint8_t esd_recovery; 3920 /** 3921 * DSC Slice height. 3922 */ 3923 uint16_t dsc_slice_height; 3924 /** 3925 * Some panels request main link off before xth vertical line 3926 */ 3927 uint16_t poweroff_before_vertical_line; 3928 /** 3929 * Some panels cannot handle idle pattern during PSR entry. 3930 * To power down phy before disable stream to avoid sending 3931 * idle pattern. 3932 */ 3933 uint8_t power_down_phy_before_disable_stream; 3934 }; 3935 3936 /** 3937 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3938 */ 3939 struct dmub_rb_cmd_psr_copy_settings { 3940 /** 3941 * Command header. 3942 */ 3943 struct dmub_cmd_header header; 3944 /** 3945 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3946 */ 3947 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3948 }; 3949 3950 /** 3951 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3952 */ 3953 struct dmub_cmd_psr_set_level_data { 3954 /** 3955 * 16-bit value dicated by driver that will enable/disable different functionality. 3956 */ 3957 uint16_t psr_level; 3958 /** 3959 * PSR control version. 3960 */ 3961 uint8_t cmd_version; 3962 /** 3963 * Panel Instance. 3964 * Panel instance to identify which psr_state to use 3965 * Currently the support is only for 0 or 1 3966 */ 3967 uint8_t panel_inst; 3968 }; 3969 3970 /** 3971 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3972 */ 3973 struct dmub_rb_cmd_psr_set_level { 3974 /** 3975 * Command header. 3976 */ 3977 struct dmub_cmd_header header; 3978 /** 3979 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3980 */ 3981 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3982 }; 3983 3984 struct dmub_rb_cmd_psr_enable_data { 3985 /** 3986 * PSR control version. 3987 */ 3988 uint8_t cmd_version; 3989 /** 3990 * Panel Instance. 3991 * Panel instance to identify which psr_state to use 3992 * Currently the support is only for 0 or 1 3993 */ 3994 uint8_t panel_inst; 3995 /** 3996 * Phy state to enter. 3997 * Values to use are defined in dmub_phy_fsm_state 3998 */ 3999 uint8_t phy_fsm_state; 4000 /** 4001 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4002 * Set this using enum phy_link_rate. 4003 * This does not support HDMI/DP2 for now. 4004 */ 4005 uint8_t phy_rate; 4006 }; 4007 4008 /** 4009 * Definition of a DMUB_CMD__PSR_ENABLE command. 4010 * PSR enable/disable is controlled using the sub_type. 4011 */ 4012 struct dmub_rb_cmd_psr_enable { 4013 /** 4014 * Command header. 4015 */ 4016 struct dmub_cmd_header header; 4017 4018 struct dmub_rb_cmd_psr_enable_data data; 4019 }; 4020 4021 /** 4022 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 4023 */ 4024 struct dmub_cmd_psr_set_version_data { 4025 /** 4026 * PSR version that FW should implement. 4027 */ 4028 enum psr_version version; 4029 /** 4030 * PSR control version. 4031 */ 4032 uint8_t cmd_version; 4033 /** 4034 * Panel Instance. 4035 * Panel instance to identify which psr_state to use 4036 * Currently the support is only for 0 or 1 4037 */ 4038 uint8_t panel_inst; 4039 /** 4040 * Explicit padding to 4 byte boundary. 4041 */ 4042 uint8_t pad[2]; 4043 }; 4044 4045 /** 4046 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 4047 */ 4048 struct dmub_rb_cmd_psr_set_version { 4049 /** 4050 * Command header. 4051 */ 4052 struct dmub_cmd_header header; 4053 /** 4054 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 4055 */ 4056 struct dmub_cmd_psr_set_version_data psr_set_version_data; 4057 }; 4058 4059 struct dmub_cmd_psr_force_static_data { 4060 /** 4061 * PSR control version. 4062 */ 4063 uint8_t cmd_version; 4064 /** 4065 * Panel Instance. 4066 * Panel instance to identify which psr_state to use 4067 * Currently the support is only for 0 or 1 4068 */ 4069 uint8_t panel_inst; 4070 /** 4071 * Explicit padding to 4 byte boundary. 4072 */ 4073 uint8_t pad[2]; 4074 }; 4075 4076 /** 4077 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 4078 */ 4079 struct dmub_rb_cmd_psr_force_static { 4080 /** 4081 * Command header. 4082 */ 4083 struct dmub_cmd_header header; 4084 /** 4085 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 4086 */ 4087 struct dmub_cmd_psr_force_static_data psr_force_static_data; 4088 }; 4089 4090 /** 4091 * PSR SU debug flags. 4092 */ 4093 union dmub_psr_su_debug_flags { 4094 /** 4095 * PSR SU debug flags. 4096 */ 4097 struct { 4098 /** 4099 * Update dirty rect in SW only. 4100 */ 4101 uint8_t update_dirty_rect_only : 1; 4102 /** 4103 * Reset the cursor/plane state before processing the call. 4104 */ 4105 uint8_t reset_state : 1; 4106 } bitfields; 4107 4108 /** 4109 * Union for debug flags. 4110 */ 4111 uint32_t u32All; 4112 }; 4113 4114 /** 4115 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 4116 * This triggers a selective update for PSR SU. 4117 */ 4118 struct dmub_cmd_update_dirty_rect_data { 4119 /** 4120 * Dirty rects from OS. 4121 */ 4122 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 4123 /** 4124 * PSR SU debug flags. 4125 */ 4126 union dmub_psr_su_debug_flags debug_flags; 4127 /** 4128 * Pipe index. 4129 */ 4130 uint8_t pipe_idx; 4131 /** 4132 * Number of dirty rects. 4133 */ 4134 uint8_t dirty_rect_count; 4135 /** 4136 * dirty rects cmd version. 4137 */ 4138 uint8_t cmd_version; 4139 /** 4140 * Panel Instance. 4141 * Panel instance to identify which psr_state to use 4142 * Currently the support is only for 0 or 1 4143 */ 4144 uint8_t panel_inst; 4145 /** 4146 * OTG HW instance 4147 */ 4148 uint8_t otg_inst; 4149 /** 4150 * Padding for 4 byte alignment 4151 */ 4152 uint8_t padding[3]; 4153 }; 4154 4155 /** 4156 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 4157 */ 4158 struct dmub_rb_cmd_update_dirty_rect { 4159 /** 4160 * Command header. 4161 */ 4162 struct dmub_cmd_header header; 4163 /** 4164 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 4165 */ 4166 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 4167 }; 4168 4169 /** 4170 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 4171 */ 4172 union dmub_reg_cursor_control_cfg { 4173 struct { 4174 uint32_t cur_enable: 1; 4175 uint32_t reser0: 3; 4176 uint32_t cur_2x_magnify: 1; 4177 uint32_t reser1: 3; 4178 uint32_t mode: 3; 4179 uint32_t reser2: 5; 4180 uint32_t pitch: 2; 4181 uint32_t reser3: 6; 4182 uint32_t line_per_chunk: 5; 4183 uint32_t reser4: 3; 4184 } bits; 4185 uint32_t raw; 4186 }; 4187 struct dmub_cursor_position_cache_hubp { 4188 union dmub_reg_cursor_control_cfg cur_ctl; 4189 union dmub_reg_position_cfg { 4190 struct { 4191 uint32_t cur_x_pos: 16; 4192 uint32_t cur_y_pos: 16; 4193 } bits; 4194 uint32_t raw; 4195 } position; 4196 union dmub_reg_hot_spot_cfg { 4197 struct { 4198 uint32_t hot_x: 16; 4199 uint32_t hot_y: 16; 4200 } bits; 4201 uint32_t raw; 4202 } hot_spot; 4203 union dmub_reg_dst_offset_cfg { 4204 struct { 4205 uint32_t dst_x_offset: 13; 4206 uint32_t reserved: 19; 4207 } bits; 4208 uint32_t raw; 4209 } dst_offset; 4210 }; 4211 4212 union dmub_reg_cur0_control_cfg { 4213 struct { 4214 uint32_t cur0_enable: 1; 4215 uint32_t expansion_mode: 1; 4216 uint32_t reser0: 1; 4217 uint32_t cur0_rom_en: 1; 4218 uint32_t mode: 3; 4219 uint32_t reserved: 25; 4220 } bits; 4221 uint32_t raw; 4222 }; 4223 struct dmub_cursor_position_cache_dpp { 4224 union dmub_reg_cur0_control_cfg cur0_ctl; 4225 }; 4226 struct dmub_cursor_position_cfg { 4227 struct dmub_cursor_position_cache_hubp pHubp; 4228 struct dmub_cursor_position_cache_dpp pDpp; 4229 uint8_t pipe_idx; 4230 /* 4231 * Padding is required. To be 4 Bytes Aligned. 4232 */ 4233 uint8_t padding[3]; 4234 }; 4235 4236 struct dmub_cursor_attribute_cache_hubp { 4237 uint32_t SURFACE_ADDR_HIGH; 4238 uint32_t SURFACE_ADDR; 4239 union dmub_reg_cursor_control_cfg cur_ctl; 4240 union dmub_reg_cursor_size_cfg { 4241 struct { 4242 uint32_t width: 16; 4243 uint32_t height: 16; 4244 } bits; 4245 uint32_t raw; 4246 } size; 4247 union dmub_reg_cursor_settings_cfg { 4248 struct { 4249 uint32_t dst_y_offset: 8; 4250 uint32_t chunk_hdl_adjust: 2; 4251 uint32_t reserved: 22; 4252 } bits; 4253 uint32_t raw; 4254 } settings; 4255 }; 4256 struct dmub_cursor_attribute_cache_dpp { 4257 union dmub_reg_cur0_control_cfg cur0_ctl; 4258 }; 4259 struct dmub_cursor_attributes_cfg { 4260 struct dmub_cursor_attribute_cache_hubp aHubp; 4261 struct dmub_cursor_attribute_cache_dpp aDpp; 4262 }; 4263 4264 struct dmub_cmd_update_cursor_payload0 { 4265 /** 4266 * Cursor dirty rects. 4267 */ 4268 struct dmub_rect cursor_rect; 4269 /** 4270 * PSR SU debug flags. 4271 */ 4272 union dmub_psr_su_debug_flags debug_flags; 4273 /** 4274 * Cursor enable/disable. 4275 */ 4276 uint8_t enable; 4277 /** 4278 * Pipe index. 4279 */ 4280 uint8_t pipe_idx; 4281 /** 4282 * Cursor update cmd version. 4283 */ 4284 uint8_t cmd_version; 4285 /** 4286 * Panel Instance. 4287 * Panel instance to identify which psr_state to use 4288 * Currently the support is only for 0 or 1 4289 */ 4290 uint8_t panel_inst; 4291 /** 4292 * Cursor Position Register. 4293 * Registers contains Hubp & Dpp modules 4294 */ 4295 struct dmub_cursor_position_cfg position_cfg; 4296 /** 4297 * OTG HW instance 4298 */ 4299 uint8_t otg_inst; 4300 /** 4301 * Padding for 4 byte alignment 4302 */ 4303 uint8_t padding[3]; 4304 }; 4305 4306 struct dmub_cmd_update_cursor_payload1 { 4307 struct dmub_cursor_attributes_cfg attribute_cfg; 4308 }; 4309 4310 union dmub_cmd_update_cursor_info_data { 4311 struct dmub_cmd_update_cursor_payload0 payload0; 4312 struct dmub_cmd_update_cursor_payload1 payload1; 4313 }; 4314 /** 4315 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4316 */ 4317 struct dmub_rb_cmd_update_cursor_info { 4318 /** 4319 * Command header. 4320 */ 4321 struct dmub_cmd_header header; 4322 /** 4323 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 4324 */ 4325 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 4326 }; 4327 4328 /** 4329 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4330 */ 4331 struct dmub_cmd_psr_set_vtotal_data { 4332 /** 4333 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 4334 */ 4335 uint16_t psr_vtotal_idle; 4336 /** 4337 * PSR control version. 4338 */ 4339 uint8_t cmd_version; 4340 /** 4341 * Panel Instance. 4342 * Panel instance to identify which psr_state to use 4343 * Currently the support is only for 0 or 1 4344 */ 4345 uint8_t panel_inst; 4346 /* 4347 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 4348 */ 4349 uint16_t psr_vtotal_su; 4350 /** 4351 * Explicit padding to 4 byte boundary. 4352 */ 4353 uint8_t pad2[2]; 4354 }; 4355 4356 /** 4357 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4358 */ 4359 struct dmub_rb_cmd_psr_set_vtotal { 4360 /** 4361 * Command header. 4362 */ 4363 struct dmub_cmd_header header; 4364 /** 4365 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4366 */ 4367 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 4368 }; 4369 4370 /** 4371 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 4372 */ 4373 struct dmub_cmd_psr_set_power_opt_data { 4374 /** 4375 * PSR control version. 4376 */ 4377 uint8_t cmd_version; 4378 /** 4379 * Panel Instance. 4380 * Panel instance to identify which psr_state to use 4381 * Currently the support is only for 0 or 1 4382 */ 4383 uint8_t panel_inst; 4384 /** 4385 * Explicit padding to 4 byte boundary. 4386 */ 4387 uint8_t pad[2]; 4388 /** 4389 * PSR power option 4390 */ 4391 uint32_t power_opt; 4392 }; 4393 4394 /** 4395 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4396 */ 4397 struct dmub_rb_cmd_psr_set_power_opt { 4398 /** 4399 * Command header. 4400 */ 4401 struct dmub_cmd_header header; 4402 /** 4403 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4404 */ 4405 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 4406 }; 4407 4408 enum dmub_alpm_mode { 4409 ALPM_AUXWAKE = 0, 4410 ALPM_AUXLESS = 1, 4411 ALPM_UNSUPPORTED = 2, 4412 }; 4413 4414 /** 4415 * Definition of Replay Residency GPINT command. 4416 * Bit[0] - Residency mode for Revision 0 4417 * Bit[1] - Enable/Disable state 4418 * Bit[2-3] - Revision number 4419 * Bit[4-7] - Residency mode for Revision 1 4420 * Bit[8] - Panel instance 4421 * Bit[9-15] - Reserved 4422 */ 4423 4424 enum pr_residency_mode { 4425 PR_RESIDENCY_MODE_PHY = 0x0, 4426 PR_RESIDENCY_MODE_ALPM, 4427 PR_RESIDENCY_MODE_IPS2, 4428 PR_RESIDENCY_MODE_FRAME_CNT, 4429 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 4430 }; 4431 4432 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 4433 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 4434 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 4435 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 4436 4437 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4438 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 4439 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4440 4441 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 4442 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 4443 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 4444 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 4445 4446 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4447 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4448 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4449 4450 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 4451 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 4452 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 4453 4454 /** 4455 * Definition of a replay_state. 4456 */ 4457 enum replay_state { 4458 REPLAY_STATE_0 = 0x0, 4459 REPLAY_STATE_1 = 0x10, 4460 REPLAY_STATE_1A = 0x11, 4461 REPLAY_STATE_2 = 0x20, 4462 REPLAY_STATE_2A = 0x21, 4463 REPLAY_STATE_3 = 0x30, 4464 REPLAY_STATE_3INIT = 0x31, 4465 REPLAY_STATE_4 = 0x40, 4466 REPLAY_STATE_4A = 0x41, 4467 REPLAY_STATE_4B = 0x42, 4468 REPLAY_STATE_4C = 0x43, 4469 REPLAY_STATE_4D = 0x44, 4470 REPLAY_STATE_4E = 0x45, 4471 REPLAY_STATE_4B_LOCKED = 0x4A, 4472 REPLAY_STATE_4C_UNLOCKED = 0x4B, 4473 REPLAY_STATE_5 = 0x50, 4474 REPLAY_STATE_5A = 0x51, 4475 REPLAY_STATE_5B = 0x52, 4476 REPLAY_STATE_5A_LOCKED = 0x5A, 4477 REPLAY_STATE_5B_UNLOCKED = 0x5B, 4478 REPLAY_STATE_6 = 0x60, 4479 REPLAY_STATE_6A = 0x61, 4480 REPLAY_STATE_6B = 0x62, 4481 REPLAY_STATE_INVALID = 0xFF, 4482 }; 4483 4484 /** 4485 * Definition of a panel replay state 4486 */ 4487 enum pr_state { 4488 PR_STATE_0 = 0x00, // State 0 steady state 4489 // Pending SDP and Unlock before back to State 0 4490 PR_STATE_0_PENDING_SDP_AND_UNLOCK = 0x01, 4491 PR_STATE_1 = 0x10, // State 1 4492 PR_STATE_2 = 0x20, // State 2 steady state 4493 // Pending frame transmission before transition to State 2 4494 PR_STATE_2_PENDING_FRAME_TRANSMISSION = 0x30, 4495 // Active and Powered Up 4496 PR_STATE_2_POWERED = 0x31, 4497 // Active and Powered Down, but need to blank HUBP after DPG_EN latch 4498 PR_STATE_2_PENDING_HUBP_BLANK = 0x32, 4499 // Active and Pending Power Up 4500 PR_STATE_2_PENDING_POWER_UP = 0x33, 4501 // Active and Powered Up, Pending DPG latch 4502 PR_STATE_2_PENDING_LOCK = 0x34, 4503 // Active and Powered Up, Pending SDP and Unlock 4504 PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35, 4505 // Pending transmission of AS SDP for timing sync, but no rfb update 4506 PR_STATE_2_PENDING_AS_SDP = 0x36, 4507 // Invalid 4508 PR_STATE_INVALID = 0xFF, 4509 }; 4510 4511 /** 4512 * Replay command sub-types. 4513 */ 4514 enum dmub_cmd_replay_type { 4515 /** 4516 * Copy driver-calculated parameters to REPLAY state. 4517 */ 4518 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 4519 /** 4520 * Enable REPLAY. 4521 */ 4522 DMUB_CMD__REPLAY_ENABLE = 1, 4523 /** 4524 * Set Replay power option. 4525 */ 4526 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 4527 /** 4528 * Set coasting vtotal. 4529 */ 4530 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 4531 /** 4532 * Set power opt and coasting vtotal. 4533 */ 4534 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 4535 /** 4536 * Set disabled iiming sync. 4537 */ 4538 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 4539 /** 4540 * Set Residency Frameupdate Timer. 4541 */ 4542 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 4543 /** 4544 * Set pseudo vtotal 4545 */ 4546 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 4547 /** 4548 * Set adaptive sync sdp enabled 4549 */ 4550 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4551 /** 4552 * Set Replay General command. 4553 */ 4554 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4555 }; 4556 4557 /* 4558 * Panel Polarity sub-types 4559 */ 4560 enum dmub_cmd_panel_polarity_type { 4561 DMUB_CMD__PANEL_POLARITY_ENABLE = 0, 4562 DMUB_CMD__PANEL_POLARITY_GET_BIAS = 1, 4563 DMUB_CMD__PANEL_POLARITY_RESET = 2, 4564 }; 4565 4566 /* 4567 * Panel Replay sub-types 4568 */ 4569 enum dmub_cmd_panel_replay_type { 4570 DMUB_CMD__PR_ENABLE = 0, 4571 DMUB_CMD__PR_COPY_SETTINGS = 1, 4572 DMUB_CMD__PR_UPDATE_STATE = 2, 4573 DMUB_CMD__PR_GENERAL_CMD = 3, 4574 }; 4575 4576 enum dmub_cmd_panel_replay_state_update_subtype { 4577 PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, 4578 PR_STATE_UPDATE_SYNC_MODE = 0x2, 4579 PR_STATE_UPDATE_RUNTIME_FLAGS = 0x3, 4580 PR_STATE_UPDATE_PSEUDO_VTOTAL = 0x4, 4581 }; 4582 4583 enum dmub_cmd_panel_replay_general_subtype { 4584 PR_GENERAL_CMD_DEBUG_OPTION = 0x1, 4585 }; 4586 4587 /** 4588 * Replay general command sub-types. 4589 */ 4590 enum dmub_cmd_replay_general_subtype { 4591 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 4592 /** 4593 * TODO: For backward compatible, allow new command only. 4594 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4595 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4596 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4597 */ 4598 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4599 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4600 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4601 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4602 REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, 4603 REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, 4604 REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE, 4605 REPLAY_GENERAL_CMD_LIVE_CAPTURE_WITH_CVT, 4606 }; 4607 4608 struct dmub_alpm_auxless_data { 4609 uint16_t lfps_setup_ns; 4610 uint16_t lfps_period_ns; 4611 uint16_t lfps_silence_ns; 4612 uint16_t lfps_t1_t2_override_us; 4613 short lfps_t1_t2_offset_us; 4614 uint8_t lttpr_count; 4615 /* 4616 * Padding to align structure to 4 byte boundary. 4617 */ 4618 uint8_t pad[1]; 4619 }; 4620 4621 /** 4622 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4623 */ 4624 struct dmub_cmd_replay_copy_settings_data { 4625 /** 4626 * Flags that can be set by driver to change some replay behaviour. 4627 */ 4628 union replay_debug_flags debug; 4629 4630 /** 4631 * @flags: Flags used to determine feature functionality. 4632 */ 4633 union replay_hw_flags flags; 4634 4635 /** 4636 * DPP HW instance. 4637 */ 4638 uint8_t dpp_inst; 4639 /** 4640 * OTG HW instance. 4641 */ 4642 uint8_t otg_inst; 4643 /** 4644 * DIG FE HW instance. 4645 */ 4646 uint8_t digfe_inst; 4647 /** 4648 * DIG BE HW instance. 4649 */ 4650 uint8_t digbe_inst; 4651 /** 4652 * AUX HW instance. 4653 */ 4654 uint8_t aux_inst; 4655 /** 4656 * Panel Instance. 4657 * Panel isntance to identify which psr_state to use 4658 * Currently the support is only for 0 or 1 4659 */ 4660 uint8_t panel_inst; 4661 /** 4662 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4663 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4664 */ 4665 uint8_t pixel_deviation_per_line; 4666 /** 4667 * @max_deviation_line: The max number of deviation line that can keep the timing 4668 * synchronized between the Source and Sink during Replay normal sleep mode. 4669 */ 4670 uint8_t max_deviation_line; 4671 /** 4672 * Length of each horizontal line in ns. 4673 */ 4674 uint32_t line_time_in_ns; 4675 /** 4676 * PHY instance. 4677 */ 4678 uint8_t dpphy_inst; 4679 /** 4680 * Determines if SMU optimzations are enabled/disabled. 4681 */ 4682 uint8_t smu_optimizations_en; 4683 /** 4684 * Determines if timing sync are enabled/disabled. 4685 */ 4686 uint8_t replay_timing_sync_supported; 4687 /* 4688 * Use FSM state for Replay power up/down 4689 */ 4690 uint8_t use_phy_fsm; 4691 /** 4692 * Use for AUX-less ALPM LFPS wake operation 4693 */ 4694 struct dmub_alpm_auxless_data auxless_alpm_data; 4695 /** 4696 * @hpo_stream_enc_inst: HPO stream encoder instance 4697 */ 4698 uint8_t hpo_stream_enc_inst; 4699 /** 4700 * @hpo_link_enc_inst: HPO link encoder instance 4701 */ 4702 uint8_t hpo_link_enc_inst; 4703 /** 4704 * Determines if fast resync in ultra sleep mode is enabled/disabled. 4705 */ 4706 uint8_t replay_support_fast_resync_in_ultra_sleep_mode; 4707 /** 4708 * @pad: Align structure to 4 byte boundary. 4709 */ 4710 uint8_t pad[1]; 4711 }; 4712 4713 4714 /** 4715 * Replay versions. 4716 */ 4717 enum replay_version { 4718 /** 4719 * FreeSync Replay 4720 */ 4721 REPLAY_VERSION_FREESYNC_REPLAY = 0, 4722 /** 4723 * Panel Replay 4724 */ 4725 REPLAY_VERSION_PANEL_REPLAY = 1, 4726 /** 4727 * Replay not supported. 4728 */ 4729 REPLAY_VERSION_UNSUPPORTED = 0xFF, 4730 }; 4731 4732 /** 4733 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4734 */ 4735 struct dmub_rb_cmd_replay_copy_settings { 4736 /** 4737 * Command header. 4738 */ 4739 struct dmub_cmd_header header; 4740 /** 4741 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4742 */ 4743 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4744 }; 4745 4746 /** 4747 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4748 */ 4749 enum replay_enable { 4750 /** 4751 * Disable REPLAY. 4752 */ 4753 REPLAY_DISABLE = 0, 4754 /** 4755 * Enable REPLAY. 4756 */ 4757 REPLAY_ENABLE = 1, 4758 }; 4759 4760 /** 4761 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 4762 */ 4763 struct dmub_rb_cmd_smart_power_oled_enable_data { 4764 /** 4765 * SMART_POWER_OLED enable or disable. 4766 */ 4767 uint8_t enable; 4768 /** 4769 * Panel Instance. 4770 * Panel isntance to identify which replay_state to use 4771 * Currently the support is only for 0 or 1 4772 */ 4773 uint8_t panel_inst; 4774 4775 uint16_t peak_nits; 4776 /** 4777 * OTG HW instance. 4778 */ 4779 uint8_t otg_inst; 4780 /** 4781 * DIG FE HW instance. 4782 */ 4783 uint8_t digfe_inst; 4784 /** 4785 * DIG BE HW instance. 4786 */ 4787 uint8_t digbe_inst; 4788 uint8_t debugcontrol; 4789 /* 4790 * vertical interrupt trigger line 4791 */ 4792 uint32_t triggerline; 4793 4794 uint16_t fixed_max_cll; 4795 4796 uint8_t pad[2]; 4797 }; 4798 4799 /** 4800 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4801 */ 4802 struct dmub_rb_cmd_replay_enable_data { 4803 /** 4804 * Replay enable or disable. 4805 */ 4806 uint8_t enable; 4807 /** 4808 * Panel Instance. 4809 * Panel isntance to identify which replay_state to use 4810 * Currently the support is only for 0 or 1 4811 */ 4812 uint8_t panel_inst; 4813 /** 4814 * Phy state to enter. 4815 * Values to use are defined in dmub_phy_fsm_state 4816 */ 4817 uint8_t phy_fsm_state; 4818 /** 4819 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4820 * Set this using enum phy_link_rate. 4821 * This does not support HDMI/DP2 for now. 4822 */ 4823 uint8_t phy_rate; 4824 /** 4825 * @hpo_stream_enc_inst: HPO stream encoder instance 4826 */ 4827 uint8_t hpo_stream_enc_inst; 4828 /** 4829 * @hpo_link_enc_inst: HPO link encoder instance 4830 */ 4831 uint8_t hpo_link_enc_inst; 4832 /** 4833 * @pad: Align structure to 4 byte boundary. 4834 */ 4835 uint8_t pad[2]; 4836 }; 4837 4838 /** 4839 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4840 * Replay enable/disable is controlled using action in data. 4841 */ 4842 struct dmub_rb_cmd_replay_enable { 4843 /** 4844 * Command header. 4845 */ 4846 struct dmub_cmd_header header; 4847 4848 struct dmub_rb_cmd_replay_enable_data data; 4849 }; 4850 4851 /** 4852 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4853 */ 4854 struct dmub_cmd_replay_set_power_opt_data { 4855 /** 4856 * Panel Instance. 4857 * Panel isntance to identify which replay_state to use 4858 * Currently the support is only for 0 or 1 4859 */ 4860 uint8_t panel_inst; 4861 /** 4862 * Explicit padding to 4 byte boundary. 4863 */ 4864 uint8_t pad[3]; 4865 /** 4866 * REPLAY power option 4867 */ 4868 uint32_t power_opt; 4869 }; 4870 4871 /** 4872 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4873 */ 4874 struct dmub_cmd_replay_set_timing_sync_data { 4875 /** 4876 * Panel Instance. 4877 * Panel isntance to identify which replay_state to use 4878 * Currently the support is only for 0 or 1 4879 */ 4880 uint8_t panel_inst; 4881 /** 4882 * REPLAY set_timing_sync 4883 */ 4884 uint8_t timing_sync_supported; 4885 /** 4886 * Explicit padding to 4 byte boundary. 4887 */ 4888 uint8_t pad[2]; 4889 }; 4890 4891 /** 4892 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4893 */ 4894 struct dmub_cmd_replay_set_pseudo_vtotal { 4895 /** 4896 * Panel Instance. 4897 * Panel isntance to identify which replay_state to use 4898 * Currently the support is only for 0 or 1 4899 */ 4900 uint8_t panel_inst; 4901 /** 4902 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4903 */ 4904 uint16_t vtotal; 4905 /** 4906 * Explicit padding to 4 byte boundary. 4907 */ 4908 uint8_t pad; 4909 }; 4910 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4911 /** 4912 * Panel Instance. 4913 * Panel isntance to identify which replay_state to use 4914 * Currently the support is only for 0 or 1 4915 */ 4916 uint8_t panel_inst; 4917 /** 4918 * enabled: set adaptive sync sdp enabled 4919 */ 4920 uint8_t force_disabled; 4921 4922 uint8_t pad[2]; 4923 }; 4924 struct dmub_cmd_replay_set_general_cmd_data { 4925 /** 4926 * Panel Instance. 4927 * Panel isntance to identify which replay_state to use 4928 * Currently the support is only for 0 or 1 4929 */ 4930 uint8_t panel_inst; 4931 /** 4932 * subtype: replay general cmd sub type 4933 */ 4934 uint8_t subtype; 4935 4936 uint8_t pad[2]; 4937 /** 4938 * config data with param1 and param2 4939 */ 4940 uint32_t param1; 4941 4942 uint32_t param2; 4943 }; 4944 4945 /** 4946 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4947 */ 4948 struct dmub_rb_cmd_replay_set_power_opt { 4949 /** 4950 * Command header. 4951 */ 4952 struct dmub_cmd_header header; 4953 /** 4954 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4955 */ 4956 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4957 }; 4958 4959 /** 4960 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4961 */ 4962 struct dmub_cmd_replay_set_coasting_vtotal_data { 4963 /** 4964 * 16-bit value dicated by driver that indicates the coasting vtotal. 4965 */ 4966 uint16_t coasting_vtotal; 4967 /** 4968 * REPLAY control version. 4969 */ 4970 uint8_t cmd_version; 4971 /** 4972 * Panel Instance. 4973 * Panel isntance to identify which replay_state to use 4974 * Currently the support is only for 0 or 1 4975 */ 4976 uint8_t panel_inst; 4977 /** 4978 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4979 */ 4980 uint16_t coasting_vtotal_high; 4981 /** 4982 * frame skip number. 4983 */ 4984 uint16_t frame_skip_number; 4985 }; 4986 4987 /** 4988 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4989 */ 4990 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4991 /** 4992 * Command header. 4993 */ 4994 struct dmub_cmd_header header; 4995 /** 4996 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4997 */ 4998 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4999 }; 5000 5001 /** 5002 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5003 */ 5004 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 5005 /** 5006 * Command header. 5007 */ 5008 struct dmub_cmd_header header; 5009 /** 5010 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5011 */ 5012 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 5013 /** 5014 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5015 */ 5016 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 5017 }; 5018 5019 /** 5020 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 5021 */ 5022 struct dmub_rb_cmd_replay_set_timing_sync { 5023 /** 5024 * Command header. 5025 */ 5026 struct dmub_cmd_header header; 5027 /** 5028 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 5029 */ 5030 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 5031 }; 5032 5033 /** 5034 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5035 */ 5036 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 5037 /** 5038 * Command header. 5039 */ 5040 struct dmub_cmd_header header; 5041 /** 5042 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5043 */ 5044 struct dmub_cmd_replay_set_pseudo_vtotal data; 5045 }; 5046 5047 /** 5048 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5049 */ 5050 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 5051 /** 5052 * Command header. 5053 */ 5054 struct dmub_cmd_header header; 5055 /** 5056 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5057 */ 5058 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 5059 }; 5060 5061 /** 5062 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5063 */ 5064 struct dmub_rb_cmd_replay_set_general_cmd { 5065 /** 5066 * Command header. 5067 */ 5068 struct dmub_cmd_header header; 5069 /** 5070 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5071 */ 5072 struct dmub_cmd_replay_set_general_cmd_data data; 5073 }; 5074 5075 /** 5076 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5077 */ 5078 struct dmub_cmd_replay_frameupdate_timer_data { 5079 /** 5080 * Panel Instance. 5081 * Panel isntance to identify which replay_state to use 5082 * Currently the support is only for 0 or 1 5083 */ 5084 uint8_t panel_inst; 5085 /** 5086 * Replay Frameupdate Timer Enable or not 5087 */ 5088 uint8_t enable; 5089 /** 5090 * REPLAY force reflash frame update number 5091 */ 5092 uint16_t frameupdate_count; 5093 }; 5094 /** 5095 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 5096 */ 5097 struct dmub_rb_cmd_replay_set_frameupdate_timer { 5098 /** 5099 * Command header. 5100 */ 5101 struct dmub_cmd_header header; 5102 /** 5103 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5104 */ 5105 struct dmub_cmd_replay_frameupdate_timer_data data; 5106 }; 5107 5108 /** 5109 * Definition union of replay command set 5110 */ 5111 union dmub_replay_cmd_set { 5112 /** 5113 * Panel Instance. 5114 * Panel isntance to identify which replay_state to use 5115 * Currently the support is only for 0 or 1 5116 */ 5117 uint8_t panel_inst; 5118 /** 5119 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 5120 */ 5121 struct dmub_cmd_replay_set_timing_sync_data sync_data; 5122 /** 5123 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 5124 */ 5125 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 5126 /** 5127 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 5128 */ 5129 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 5130 /** 5131 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 5132 */ 5133 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 5134 /** 5135 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 5136 */ 5137 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 5138 }; 5139 5140 /** 5141 * IHC command sub-types. 5142 */ 5143 enum dmub_cmd_ihc_type { 5144 /** 5145 * Set DIG HDCP interrupt destination. 5146 */ 5147 DMUB_CMD__IHC_SET_DIG_HDCP_INTERRUPT_DEST = 0, 5148 }; 5149 5150 /** 5151 * Data passed from driver to FW in a DMUB_CMD__IHC command. 5152 */ 5153 struct dmub_cmd_ihc_data { 5154 /** 5155 * DIG engine ID (0-3). 5156 */ 5157 uint8_t dig_id; 5158 /** 5159 * 1 = route to DMU, 0 = route to CPU. 5160 */ 5161 uint8_t to_dmu : 1; 5162 /** 5163 * Reserved bits. 5164 */ 5165 uint8_t reserved : 7; 5166 /** 5167 * Padding. 5168 */ 5169 uint8_t pad[2]; 5170 }; 5171 5172 /** 5173 * Definition of a DMUB_CMD__IHC command. 5174 */ 5175 struct dmub_rb_cmd_ihc { 5176 /** 5177 * Command header. 5178 */ 5179 struct dmub_cmd_header header; 5180 /** 5181 * IHC command data. 5182 */ 5183 struct dmub_cmd_ihc_data data; 5184 }; 5185 5186 /** 5187 * SMART POWER OLED command sub-types. 5188 */ 5189 enum dmub_cmd_smart_power_oled_type { 5190 5191 /** 5192 * Enable/Disable SMART_POWER_OLED. 5193 */ 5194 DMUB_CMD__SMART_POWER_OLED_ENABLE = 1, 5195 /** 5196 * Get current MaxCLL value if SMART POWER OLED is enabled. 5197 */ 5198 DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2, 5199 }; 5200 5201 /** 5202 * Definition of a DMUB_CMD__SMART_POWER_OLED command. 5203 */ 5204 struct dmub_rb_cmd_smart_power_oled_enable { 5205 /** 5206 * Command header. 5207 */ 5208 struct dmub_cmd_header header; 5209 5210 struct dmub_rb_cmd_smart_power_oled_enable_data data; 5211 }; 5212 5213 struct dmub_cmd_smart_power_oled_getmaxcll_input { 5214 uint8_t panel_inst; 5215 uint8_t pad[3]; 5216 }; 5217 5218 struct dmub_cmd_smart_power_oled_getmaxcll_output { 5219 uint16_t current_max_cll; 5220 uint8_t pad[2]; 5221 }; 5222 5223 /** 5224 * Definition of a DMUB_CMD__SMART_POWER_OLED command. 5225 */ 5226 struct dmub_rb_cmd_smart_power_oled_getmaxcll { 5227 struct dmub_cmd_header header; /**< Command header */ 5228 /** 5229 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 5230 */ 5231 union dmub_cmd_smart_power_oled_getmaxcll_data { 5232 struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */ 5233 struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */ 5234 uint32_t output_raw; /**< Raw data output */ 5235 } data; 5236 }; 5237 5238 /** 5239 * Set of HW components that can be locked. 5240 * 5241 * Note: If updating with more HW components, fields 5242 * in dmub_inbox0_cmd_lock_hw must be updated to match. 5243 */ 5244 union dmub_hw_lock_flags { 5245 /** 5246 * Set of HW components that can be locked. 5247 */ 5248 struct { 5249 /** 5250 * Lock/unlock OTG master update lock. 5251 */ 5252 uint8_t lock_pipe : 1; 5253 /** 5254 * Lock/unlock cursor. 5255 */ 5256 uint8_t lock_cursor : 1; 5257 /** 5258 * Lock/unlock global update lock. 5259 */ 5260 uint8_t lock_dig : 1; 5261 /** 5262 * Triple buffer lock requires additional hw programming to usual OTG master lock. 5263 */ 5264 uint8_t triple_buffer_lock : 1; 5265 } bits; 5266 5267 /** 5268 * Union for HW Lock flags. 5269 */ 5270 uint8_t u8All; 5271 }; 5272 5273 /** 5274 * Instances of HW to be locked. 5275 * 5276 * Note: If updating with more HW components, fields 5277 * in dmub_inbox0_cmd_lock_hw must be updated to match. 5278 */ 5279 struct dmub_hw_lock_inst_flags { 5280 /** 5281 * OTG HW instance for OTG master update lock. 5282 */ 5283 uint8_t otg_inst; 5284 /** 5285 * OPP instance for cursor lock. 5286 */ 5287 uint8_t opp_inst; 5288 /** 5289 * OTG HW instance for global update lock. 5290 * TODO: Remove, and re-use otg_inst. 5291 */ 5292 uint8_t dig_inst; 5293 /** 5294 * Explicit pad to 4 byte boundary. 5295 */ 5296 uint8_t pad; 5297 }; 5298 5299 /** 5300 * Clients that can acquire the HW Lock Manager. 5301 * 5302 * Note: If updating with more clients, fields in 5303 * dmub_inbox0_cmd_lock_hw must be updated to match. 5304 */ 5305 enum hw_lock_client { 5306 /** 5307 * Driver is the client of HW Lock Manager. 5308 */ 5309 HW_LOCK_CLIENT_DRIVER = 0, 5310 /** 5311 * PSR SU is the client of HW Lock Manager. 5312 */ 5313 HW_LOCK_CLIENT_PSR_SU = 1, 5314 HW_LOCK_CLIENT_SUBVP = 3, 5315 /** 5316 * Replay is the client of HW Lock Manager. 5317 */ 5318 HW_LOCK_CLIENT_REPLAY = 4, 5319 HW_LOCK_CLIENT_FAMS2 = 5, 5320 HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6, 5321 /** 5322 * Invalid client. 5323 */ 5324 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 5325 }; 5326 5327 /** 5328 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 5329 */ 5330 struct dmub_cmd_lock_hw_data { 5331 /** 5332 * Specifies the client accessing HW Lock Manager. 5333 */ 5334 enum hw_lock_client client; 5335 /** 5336 * HW instances to be locked. 5337 */ 5338 struct dmub_hw_lock_inst_flags inst_flags; 5339 /** 5340 * Which components to be locked. 5341 */ 5342 union dmub_hw_lock_flags hw_locks; 5343 /** 5344 * Specifies lock/unlock. 5345 */ 5346 uint8_t lock; 5347 /** 5348 * HW can be unlocked separately from releasing the HW Lock Mgr. 5349 * This flag is set if the client wishes to release the object. 5350 */ 5351 uint8_t should_release; 5352 /** 5353 * Explicit padding to 4 byte boundary. 5354 */ 5355 uint8_t pad; 5356 }; 5357 5358 /** 5359 * Definition of a DMUB_CMD__HW_LOCK command. 5360 * Command is used by driver and FW. 5361 */ 5362 struct dmub_rb_cmd_lock_hw { 5363 /** 5364 * Command header. 5365 */ 5366 struct dmub_cmd_header header; 5367 /** 5368 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 5369 */ 5370 struct dmub_cmd_lock_hw_data lock_hw_data; 5371 }; 5372 5373 /** 5374 * ABM command sub-types. 5375 */ 5376 enum dmub_cmd_abm_type { 5377 /** 5378 * Initialize parameters for ABM algorithm. 5379 * Data is passed through an indirect buffer. 5380 */ 5381 DMUB_CMD__ABM_INIT_CONFIG = 0, 5382 /** 5383 * Set OTG and panel HW instance. 5384 */ 5385 DMUB_CMD__ABM_SET_PIPE = 1, 5386 /** 5387 * Set user requested backklight level. 5388 */ 5389 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 5390 /** 5391 * Set ABM operating/aggression level. 5392 */ 5393 DMUB_CMD__ABM_SET_LEVEL = 3, 5394 /** 5395 * Set ambient light level. 5396 */ 5397 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 5398 /** 5399 * Enable/disable fractional duty cycle for backlight PWM. 5400 */ 5401 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 5402 5403 /** 5404 * unregister vertical interrupt after steady state is reached 5405 */ 5406 DMUB_CMD__ABM_PAUSE = 6, 5407 5408 /** 5409 * Save and Restore ABM state. On save we save parameters, and 5410 * on restore we update state with passed in data. 5411 */ 5412 DMUB_CMD__ABM_SAVE_RESTORE = 7, 5413 5414 /** 5415 * Query ABM caps. 5416 */ 5417 DMUB_CMD__ABM_QUERY_CAPS = 8, 5418 5419 /** 5420 * Set ABM Events 5421 */ 5422 DMUB_CMD__ABM_SET_EVENT = 9, 5423 5424 /** 5425 * Get the current ACE curve. 5426 */ 5427 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 5428 5429 /** 5430 * Get current histogram data 5431 */ 5432 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 5433 }; 5434 5435 /** 5436 * LSDMA command sub-types. 5437 */ 5438 enum dmub_cmd_lsdma_type { 5439 /** 5440 * Initialize parameters for LSDMA. 5441 * Ring buffer is mapped to the ring buffer 5442 */ 5443 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 5444 /** 5445 * LSDMA copies data from source to destination linearly 5446 */ 5447 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 5448 /** 5449 * LSDMA copies data from source to destination linearly in sub window 5450 */ 5451 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, 5452 /** 5453 * Send the tiled-to-tiled copy command 5454 */ 5455 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, 5456 /** 5457 * Send the poll reg write command 5458 */ 5459 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, 5460 /** 5461 * Send the pio copy command 5462 */ 5463 DMUB_CMD__LSDMA_PIO_COPY = 5, 5464 /** 5465 * Send the pio constfill command 5466 */ 5467 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, 5468 }; 5469 5470 struct abm_ace_curve { 5471 /** 5472 * @offsets: ACE curve offsets. 5473 */ 5474 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5475 5476 /** 5477 * @thresholds: ACE curve thresholds. 5478 */ 5479 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5480 5481 /** 5482 * @slopes: ACE curve slopes. 5483 */ 5484 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5485 }; 5486 5487 struct fixed_pt_format { 5488 /** 5489 * @sign_bit: Indicates whether one bit is reserved for the sign. 5490 */ 5491 bool sign_bit; 5492 5493 /** 5494 * @num_int_bits: Number of bits used for integer part. 5495 */ 5496 uint8_t num_int_bits; 5497 5498 /** 5499 * @num_frac_bits: Number of bits used for fractional part. 5500 */ 5501 uint8_t num_frac_bits; 5502 5503 /** 5504 * @pad: Explicit padding to 4 byte boundary. 5505 */ 5506 uint8_t pad; 5507 }; 5508 5509 struct abm_caps { 5510 /** 5511 * @num_hg_bins: Number of histogram bins. 5512 */ 5513 uint8_t num_hg_bins; 5514 5515 /** 5516 * @num_ace_segments: Number of ACE curve segments. 5517 */ 5518 uint8_t num_ace_segments; 5519 5520 /** 5521 * @pad: Explicit padding to 4 byte boundary. 5522 */ 5523 uint8_t pad[2]; 5524 5525 /** 5526 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 5527 */ 5528 struct fixed_pt_format ace_thresholds_format; 5529 5530 /** 5531 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 5532 */ 5533 struct fixed_pt_format ace_offsets_format; 5534 5535 /** 5536 * @ace_slopes_format: Format of the ACE slopes. 5537 */ 5538 struct fixed_pt_format ace_slopes_format; 5539 }; 5540 5541 /** 5542 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 5543 * Requirements: 5544 * - Padded explicitly to 32-bit boundary. 5545 * - Must ensure this structure matches the one on driver-side, 5546 * otherwise it won't be aligned. 5547 */ 5548 struct abm_config_table { 5549 /** 5550 * Gamma curve thresholds, used for crgb conversion. 5551 */ 5552 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 5553 /** 5554 * Gamma curve offsets, used for crgb conversion. 5555 */ 5556 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 5557 /** 5558 * Gamma curve slopes, used for crgb conversion. 5559 */ 5560 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 5561 /** 5562 * Custom backlight curve thresholds. 5563 */ 5564 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 5565 /** 5566 * Custom backlight curve offsets. 5567 */ 5568 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 5569 /** 5570 * Ambient light thresholds. 5571 */ 5572 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 5573 /** 5574 * Minimum programmable backlight. 5575 */ 5576 uint16_t min_abm_backlight; // 122B 5577 /** 5578 * Minimum reduction values. 5579 */ 5580 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 5581 /** 5582 * Maximum reduction values. 5583 */ 5584 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 5585 /** 5586 * Bright positive gain. 5587 */ 5588 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 5589 /** 5590 * Dark negative gain. 5591 */ 5592 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 5593 /** 5594 * Hybrid factor. 5595 */ 5596 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 5597 /** 5598 * Contrast factor. 5599 */ 5600 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 5601 /** 5602 * Deviation gain. 5603 */ 5604 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 5605 /** 5606 * Minimum knee. 5607 */ 5608 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 5609 /** 5610 * Maximum knee. 5611 */ 5612 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 5613 /** 5614 * Unused. 5615 */ 5616 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 5617 /** 5618 * Explicit padding to 4 byte boundary. 5619 */ 5620 uint8_t pad3[3]; // 229B 5621 /** 5622 * Backlight ramp reduction. 5623 */ 5624 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 5625 /** 5626 * Backlight ramp start. 5627 */ 5628 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 5629 }; 5630 5631 /** 5632 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5633 */ 5634 struct dmub_cmd_abm_set_pipe_data { 5635 /** 5636 * OTG HW instance. 5637 */ 5638 uint8_t otg_inst; 5639 5640 /** 5641 * Panel Control HW instance. 5642 */ 5643 uint8_t panel_inst; 5644 5645 /** 5646 * Controls how ABM will interpret a set pipe or set level command. 5647 */ 5648 uint8_t set_pipe_option; 5649 5650 /** 5651 * Unused. 5652 * TODO: Remove. 5653 */ 5654 uint8_t ramping_boundary; 5655 5656 /** 5657 * PwrSeq HW Instance. 5658 */ 5659 uint8_t pwrseq_inst; 5660 5661 /** 5662 * Explicit padding to 4 byte boundary. 5663 */ 5664 uint8_t pad[3]; 5665 }; 5666 5667 /** 5668 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5669 */ 5670 struct dmub_rb_cmd_abm_set_pipe { 5671 /** 5672 * Command header. 5673 */ 5674 struct dmub_cmd_header header; 5675 5676 /** 5677 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5678 */ 5679 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 5680 }; 5681 5682 /** 5683 * Type of backlight control method to be used by ABM module 5684 */ 5685 enum dmub_backlight_control_type { 5686 /** 5687 * PWM Backlight control 5688 */ 5689 DMU_BACKLIGHT_CONTROL_PWM = 0, 5690 /** 5691 * VESA Aux-based backlight control 5692 */ 5693 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 5694 /** 5695 * AMD DPCD Aux-based backlight control 5696 */ 5697 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 5698 }; 5699 5700 /** 5701 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5702 */ 5703 struct dmub_cmd_abm_set_backlight_data { 5704 /** 5705 * Number of frames to ramp to backlight user level. 5706 */ 5707 uint32_t frame_ramp; 5708 5709 /** 5710 * Requested backlight level from user. 5711 */ 5712 uint32_t backlight_user_level; 5713 5714 /** 5715 * ABM control version. 5716 */ 5717 uint8_t version; 5718 5719 /** 5720 * Panel Control HW instance mask. 5721 * Bit 0 is Panel Control HW instance 0. 5722 * Bit 1 is Panel Control HW instance 1. 5723 */ 5724 uint8_t panel_mask; 5725 5726 /** 5727 * AUX HW Instance. 5728 */ 5729 uint8_t aux_inst; 5730 5731 /** 5732 * Explicit padding to 4 byte boundary. 5733 */ 5734 uint8_t pad[1]; 5735 5736 /** 5737 * Backlight control type. 5738 * Value 0 is PWM backlight control. 5739 * Value 1 is VAUX backlight control. 5740 * Value 2 is AMD DPCD AUX backlight control. 5741 */ 5742 enum dmub_backlight_control_type backlight_control_type; 5743 5744 /** 5745 * Minimum luminance in nits. 5746 */ 5747 uint32_t min_luminance; 5748 5749 /** 5750 * Maximum luminance in nits. 5751 */ 5752 uint32_t max_luminance; 5753 5754 /** 5755 * Minimum backlight in pwm. 5756 */ 5757 uint32_t min_backlight_pwm; 5758 5759 /** 5760 * Maximum backlight in pwm. 5761 */ 5762 uint32_t max_backlight_pwm; 5763 }; 5764 5765 /** 5766 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5767 */ 5768 struct dmub_rb_cmd_abm_set_backlight { 5769 /** 5770 * Command header. 5771 */ 5772 struct dmub_cmd_header header; 5773 5774 /** 5775 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5776 */ 5777 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 5778 }; 5779 5780 /** 5781 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5782 */ 5783 struct dmub_cmd_abm_set_level_data { 5784 /** 5785 * Set current ABM operating/aggression level. 5786 */ 5787 uint32_t level; 5788 5789 /** 5790 * ABM control version. 5791 */ 5792 uint8_t version; 5793 5794 /** 5795 * Panel Control HW instance mask. 5796 * Bit 0 is Panel Control HW instance 0. 5797 * Bit 1 is Panel Control HW instance 1. 5798 */ 5799 uint8_t panel_mask; 5800 5801 /** 5802 * Explicit padding to 4 byte boundary. 5803 */ 5804 uint8_t pad[2]; 5805 }; 5806 5807 /** 5808 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5809 */ 5810 struct dmub_rb_cmd_abm_set_level { 5811 /** 5812 * Command header. 5813 */ 5814 struct dmub_cmd_header header; 5815 5816 /** 5817 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5818 */ 5819 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5820 }; 5821 5822 /** 5823 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5824 */ 5825 struct dmub_cmd_abm_set_ambient_level_data { 5826 /** 5827 * Ambient light sensor reading from OS. 5828 */ 5829 uint32_t ambient_lux; 5830 5831 /** 5832 * ABM control version. 5833 */ 5834 uint8_t version; 5835 5836 /** 5837 * Panel Control HW instance mask. 5838 * Bit 0 is Panel Control HW instance 0. 5839 * Bit 1 is Panel Control HW instance 1. 5840 */ 5841 uint8_t panel_mask; 5842 5843 /** 5844 * Explicit padding to 4 byte boundary. 5845 */ 5846 uint8_t pad[2]; 5847 }; 5848 5849 /** 5850 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5851 */ 5852 struct dmub_rb_cmd_abm_set_ambient_level { 5853 /** 5854 * Command header. 5855 */ 5856 struct dmub_cmd_header header; 5857 5858 /** 5859 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5860 */ 5861 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5862 }; 5863 5864 /** 5865 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5866 */ 5867 struct dmub_cmd_abm_set_pwm_frac_data { 5868 /** 5869 * Enable/disable fractional duty cycle for backlight PWM. 5870 * TODO: Convert to uint8_t. 5871 */ 5872 uint32_t fractional_pwm; 5873 5874 /** 5875 * ABM control version. 5876 */ 5877 uint8_t version; 5878 5879 /** 5880 * Panel Control HW instance mask. 5881 * Bit 0 is Panel Control HW instance 0. 5882 * Bit 1 is Panel Control HW instance 1. 5883 */ 5884 uint8_t panel_mask; 5885 5886 /** 5887 * Explicit padding to 4 byte boundary. 5888 */ 5889 uint8_t pad[2]; 5890 }; 5891 5892 /** 5893 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5894 */ 5895 struct dmub_rb_cmd_abm_set_pwm_frac { 5896 /** 5897 * Command header. 5898 */ 5899 struct dmub_cmd_header header; 5900 5901 /** 5902 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5903 */ 5904 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5905 }; 5906 5907 /** 5908 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5909 */ 5910 struct dmub_cmd_abm_init_config_data { 5911 /** 5912 * Location of indirect buffer used to pass init data to ABM. 5913 */ 5914 union dmub_addr src; 5915 5916 /** 5917 * Indirect buffer length. 5918 */ 5919 uint16_t bytes; 5920 5921 5922 /** 5923 * ABM control version. 5924 */ 5925 uint8_t version; 5926 5927 /** 5928 * Panel Control HW instance mask. 5929 * Bit 0 is Panel Control HW instance 0. 5930 * Bit 1 is Panel Control HW instance 1. 5931 */ 5932 uint8_t panel_mask; 5933 5934 /** 5935 * Explicit padding to 4 byte boundary. 5936 */ 5937 uint8_t pad[2]; 5938 }; 5939 5940 /** 5941 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5942 */ 5943 struct dmub_rb_cmd_abm_init_config { 5944 /** 5945 * Command header. 5946 */ 5947 struct dmub_cmd_header header; 5948 5949 /** 5950 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5951 */ 5952 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5953 }; 5954 5955 /** 5956 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5957 */ 5958 5959 struct dmub_cmd_abm_pause_data { 5960 5961 /** 5962 * Panel Control HW instance mask. 5963 * Bit 0 is Panel Control HW instance 0. 5964 * Bit 1 is Panel Control HW instance 1. 5965 */ 5966 uint8_t panel_mask; 5967 5968 /** 5969 * OTG hw instance 5970 */ 5971 uint8_t otg_inst; 5972 5973 /** 5974 * Enable or disable ABM pause 5975 */ 5976 uint8_t enable; 5977 5978 /** 5979 * Explicit padding to 4 byte boundary. 5980 */ 5981 uint8_t pad[1]; 5982 }; 5983 5984 /** 5985 * Definition of a DMUB_CMD__ABM_PAUSE command. 5986 */ 5987 struct dmub_rb_cmd_abm_pause { 5988 /** 5989 * Command header. 5990 */ 5991 struct dmub_cmd_header header; 5992 5993 /** 5994 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5995 */ 5996 struct dmub_cmd_abm_pause_data abm_pause_data; 5997 }; 5998 5999 /** 6000 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 6001 */ 6002 struct dmub_cmd_abm_query_caps_in { 6003 /** 6004 * Panel instance. 6005 */ 6006 uint8_t panel_inst; 6007 6008 /** 6009 * Explicit padding to 4 byte boundary. 6010 */ 6011 uint8_t pad[3]; 6012 }; 6013 6014 /** 6015 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 6016 */ 6017 struct dmub_cmd_abm_query_caps_out { 6018 /** 6019 * SW Algorithm caps. 6020 */ 6021 struct abm_caps sw_caps; 6022 6023 /** 6024 * ABM HW caps. 6025 */ 6026 struct abm_caps hw_caps; 6027 }; 6028 6029 /** 6030 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6031 */ 6032 struct dmub_rb_cmd_abm_query_caps { 6033 /** 6034 * Command header. 6035 */ 6036 struct dmub_cmd_header header; 6037 6038 /** 6039 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 6040 */ 6041 union { 6042 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 6043 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 6044 } data; 6045 }; 6046 6047 /** 6048 * enum dmub_abm_ace_curve_type - ACE curve type. 6049 */ 6050 enum dmub_abm_ace_curve_type { 6051 /** 6052 * ACE curve as defined by the SW layer. 6053 */ 6054 ABM_ACE_CURVE_TYPE__SW = 0, 6055 /** 6056 * ACE curve as defined by the SW to HW translation interface layer. 6057 */ 6058 ABM_ACE_CURVE_TYPE__SW_IF = 1, 6059 }; 6060 6061 /** 6062 * enum dmub_abm_histogram_type - Histogram type. 6063 */ 6064 enum dmub_abm_histogram_type { 6065 /** 6066 * ACE curve as defined by the SW layer. 6067 */ 6068 ABM_HISTOGRAM_TYPE__SW = 0, 6069 /** 6070 * ACE curve as defined by the SW to HW translation interface layer. 6071 */ 6072 ABM_HISTOGRAM_TYPE__SW_IF = 1, 6073 }; 6074 6075 /** 6076 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6077 */ 6078 struct dmub_rb_cmd_abm_get_ace_curve { 6079 /** 6080 * Command header. 6081 */ 6082 struct dmub_cmd_header header; 6083 6084 /** 6085 * Address where ACE curve should be copied. 6086 */ 6087 union dmub_addr dest; 6088 6089 /** 6090 * Type of ACE curve being queried. 6091 */ 6092 enum dmub_abm_ace_curve_type ace_type; 6093 6094 /** 6095 * Indirect buffer length. 6096 */ 6097 uint16_t bytes; 6098 6099 /** 6100 * eDP panel instance. 6101 */ 6102 uint8_t panel_inst; 6103 6104 /** 6105 * Explicit padding to 4 byte boundary. 6106 */ 6107 uint8_t pad; 6108 }; 6109 6110 /** 6111 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6112 */ 6113 struct dmub_rb_cmd_abm_get_histogram { 6114 /** 6115 * Command header. 6116 */ 6117 struct dmub_cmd_header header; 6118 6119 /** 6120 * Address where Histogram should be copied. 6121 */ 6122 union dmub_addr dest; 6123 6124 /** 6125 * Type of Histogram being queried. 6126 */ 6127 enum dmub_abm_histogram_type histogram_type; 6128 6129 /** 6130 * Indirect buffer length. 6131 */ 6132 uint16_t bytes; 6133 6134 /** 6135 * eDP panel instance. 6136 */ 6137 uint8_t panel_inst; 6138 6139 /** 6140 * Explicit padding to 4 byte boundary. 6141 */ 6142 uint8_t pad; 6143 }; 6144 6145 /** 6146 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6147 */ 6148 struct dmub_rb_cmd_abm_save_restore { 6149 /** 6150 * Command header. 6151 */ 6152 struct dmub_cmd_header header; 6153 6154 /** 6155 * OTG hw instance 6156 */ 6157 uint8_t otg_inst; 6158 6159 /** 6160 * Enable or disable ABM pause 6161 */ 6162 uint8_t freeze; 6163 6164 /** 6165 * Explicit padding to 4 byte boundary. 6166 */ 6167 uint8_t debug; 6168 6169 /** 6170 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 6171 */ 6172 struct dmub_cmd_abm_init_config_data abm_init_config_data; 6173 }; 6174 6175 /** 6176 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 6177 */ 6178 6179 struct dmub_cmd_abm_set_event_data { 6180 6181 /** 6182 * VB Scaling Init. Strength Mapping 6183 * Byte 0: 0~255 for VB level 0 6184 * Byte 1: 0~255 for VB level 1 6185 * Byte 2: 0~255 for VB level 2 6186 * Byte 3: 0~255 for VB level 3 6187 */ 6188 uint32_t vb_scaling_strength_mapping; 6189 /** 6190 * VariBright Scaling Enable 6191 */ 6192 uint8_t vb_scaling_enable; 6193 /** 6194 * Panel Control HW instance mask. 6195 * Bit 0 is Panel Control HW instance 0. 6196 * Bit 1 is Panel Control HW instance 1. 6197 */ 6198 uint8_t panel_mask; 6199 6200 /** 6201 * Explicit padding to 4 byte boundary. 6202 */ 6203 uint8_t pad[2]; 6204 }; 6205 6206 /** 6207 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6208 */ 6209 struct dmub_rb_cmd_abm_set_event { 6210 /** 6211 * Command header. 6212 */ 6213 struct dmub_cmd_header header; 6214 6215 /** 6216 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 6217 */ 6218 struct dmub_cmd_abm_set_event_data abm_set_event_data; 6219 }; 6220 6221 /** 6222 * CACP command sub-types. 6223 */ 6224 enum dmub_cmd_cacp_type { 6225 /** 6226 * Initialize parameters for CACP algorithm. 6227 * Data is passed through an indirect buffer. 6228 */ 6229 DMUB_CMD__CACP_INIT_CONFIG = 0, 6230 /** 6231 * Set OTG and panel HW instance. 6232 */ 6233 DMUB_CMD__CACP_SET_PIPE = 1, 6234 /** 6235 * Set CACP operating/aggression level. 6236 */ 6237 DMUB_CMD__CACP_SET_LEVEL = 2, 6238 /** 6239 * Set event: full-screen/video mode/Hdr mode 6240 */ 6241 DMUB_CMD__CACP_SET_EVENT = 3, 6242 6243 /** 6244 * unregister vertical interrupt after steady state is reached 6245 */ 6246 DMUB_CMD__CACP_PAUSE = 4, 6247 /** 6248 * Set backlight: only for miniLED 6249 */ 6250 DMUB_CMD__CACP_SET_BACKLIGHT = 5, 6251 /** 6252 * Enable/disable fractional duty cycle for backlight PWM. 6253 */ 6254 DMUB_CMD__CACP_SET_PWM_FRAC = 6, 6255 /** 6256 * Get CACP Histogram 6257 */ 6258 DMUB_CMD__CACP_GET_HISTOGRAM = 7, 6259 /** 6260 * Get ACE curve area for IGT test validation. 6261 */ 6262 DMUB_CMD__CACP_GET_ACE_CURVE_AREA = 8, 6263 }; 6264 6265 /** 6266 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PIPE command. 6267 */ 6268 struct dmub_cmd_cacp_set_pipe_data { 6269 /** 6270 * OTG HW instance. 6271 */ 6272 uint8_t otg_inst; 6273 6274 /** 6275 * Panel Control HW instance. 6276 */ 6277 uint8_t panel_inst; 6278 6279 /** 6280 * Controls how CACP will interpret a set pipe or set level command. 6281 */ 6282 uint8_t set_pipe_option; 6283 6284 /** 6285 * PwrSeq HW Instance. 6286 */ 6287 uint8_t pwrseq_inst; 6288 }; 6289 6290 /** 6291 * Definition of a DMUB_CMD__CACP_SET_PIPE command. 6292 */ 6293 struct dmub_rb_cmd_cacp_set_pipe { 6294 /** 6295 * Command header. 6296 */ 6297 struct dmub_cmd_header header; 6298 6299 /** 6300 * Data passed from driver to FW in a DMUB_CMD__CACP_PIPE command. 6301 */ 6302 struct dmub_cmd_cacp_set_pipe_data cacp_set_pipe_data; 6303 }; 6304 6305 /** 6306 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_LEVEL command. 6307 */ 6308 struct dmub_cmd_cacp_set_level_data { 6309 /** 6310 * Set current cacp operating/aggression level. 6311 */ 6312 uint32_t level; 6313 6314 /** 6315 * CACP control version. 6316 */ 6317 uint8_t version; 6318 6319 /** 6320 * Panel Control HW instance mask. 6321 * Bit 0 is Panel Control HW instance 0. 6322 * Bit 1 is Panel Control HW instance 1. 6323 */ 6324 uint8_t panel_mask; 6325 6326 /** 6327 * Explicit padding to 4 byte boundary. 6328 */ 6329 uint8_t pad[2]; 6330 }; 6331 6332 /** 6333 * Definition of a DMUB_CMD__CACP_SET_LEVEL command. 6334 */ 6335 struct dmub_rb_cmd_cacp_set_level { 6336 /** 6337 * Command header. 6338 */ 6339 struct dmub_cmd_header header; 6340 6341 /** 6342 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_LEVEL command. 6343 */ 6344 struct dmub_cmd_cacp_set_level_data cacp_set_level_data; 6345 }; 6346 6347 /** 6348 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_EVENT command. 6349 */ 6350 struct dmub_cmd_cacp_set_event_data { 6351 /** 6352 * Full screen mode 6353 */ 6354 uint8_t full_screen_mode; 6355 6356 /** 6357 * VariBright Scaling Enable 6358 */ 6359 uint8_t vb_scaling_enable; 6360 6361 /** 6362 * HDR mode 6363 */ 6364 uint8_t hdr_mode; 6365 6366 /** 6367 * Panel Control HW instance mask. 6368 * Bit 0 is Panel Control HW instance 0. 6369 * Bit 1 is Panel Control HW instance 1. 6370 */ 6371 uint8_t panel_mask; 6372 6373 /** 6374 * Transition time info 6375 */ 6376 uint32_t trans_info; 6377 }; 6378 6379 /** 6380 * Definition of a DMUB_CMD__CACP_SET_EVENT command. 6381 */ 6382 struct dmub_rb_cmd_cacp_set_event { 6383 /** 6384 * Command header. 6385 */ 6386 struct dmub_cmd_header header; 6387 6388 /** 6389 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_EVENT command. 6390 */ 6391 struct dmub_cmd_cacp_set_event_data cacp_set_event_data; 6392 }; 6393 6394 /** 6395 * Data passed from driver to FW in a DMUB_CMD__CACP_INIT_CONFIG command. 6396 */ 6397 struct dmub_cmd_cacp_init_config_data { 6398 /** 6399 * Location of indirect buffer used to pass init data to CACP. 6400 */ 6401 union dmub_addr src; 6402 6403 /** 6404 * Indirect buffer length. 6405 */ 6406 uint16_t bytes; 6407 6408 /** 6409 * CACP control version. 6410 */ 6411 uint8_t mode; 6412 6413 /** 6414 * Panel Control HW instance mask. 6415 * Bit 0 is Panel Control HW instance 0. 6416 * Bit 1 is Panel Control HW instance 1. 6417 */ 6418 uint8_t panel_mask; 6419 6420 /** 6421 * CACP visual_confirm debug 6422 */ 6423 uint32_t visual_confirm; 6424 6425 /** 6426 * CACP customized str_scl params 6427 */ 6428 uint8_t strscl_valid; 6429 uint8_t pad[3]; 6430 uint8_t strscl_sdr[4]; 6431 uint8_t strscl_hdr[4]; 6432 }; 6433 6434 /** 6435 * Definition of a DMUB_CMD__CACP_INIT_CONFIG command. 6436 */ 6437 struct dmub_rb_cmd_cacp_init_config { 6438 /** 6439 * Command header. 6440 */ 6441 struct dmub_cmd_header header; 6442 6443 /** 6444 * Data passed from driver to FW in a DMUB_CMD__CACP_INIT_CONFIG command. 6445 */ 6446 struct dmub_cmd_cacp_init_config_data cacp_init_config_data; 6447 }; 6448 6449 /** 6450 * Data passed from driver to FW in a DMUB_CMD__CACP_PAUSE command. 6451 */ 6452 6453 struct dmub_cmd_cacp_pause_data { 6454 6455 /** 6456 * Panel Control HW instance mask. 6457 * Bit 0 is Panel Control HW instance 0. 6458 * Bit 1 is Panel Control HW instance 1. 6459 */ 6460 uint8_t panel_mask; 6461 6462 /** 6463 * OTG hw instance 6464 */ 6465 uint8_t otg_inst; 6466 6467 /** 6468 * Enable or disable CACP pause 6469 */ 6470 uint8_t enable; 6471 6472 /** 6473 * Explicit padding to 4 byte boundary. 6474 */ 6475 uint8_t pad; 6476 }; 6477 6478 /** 6479 * Definition of a DMUB_CMD__CACP_PAUSE command. 6480 */ 6481 struct dmub_rb_cmd_cacp_pause { 6482 /** 6483 * Command header. 6484 */ 6485 struct dmub_cmd_header header; 6486 6487 /** 6488 * Data passed from driver to FW in a DMUB_CMD__CACP_PAUSE command. 6489 */ 6490 struct dmub_cmd_cacp_pause_data cacp_pause_data; 6491 }; 6492 6493 /** 6494 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_BACKLIGHT command. 6495 */ 6496 struct dmub_cmd_cacp_set_backlight_data { 6497 /** 6498 * Number of frames to ramp to backlight user level. 6499 */ 6500 uint32_t frame_ramp; 6501 6502 /** 6503 * Requested backlight level from user. 6504 */ 6505 uint32_t backlight_user_level; 6506 6507 /** 6508 * ABM control version. 6509 */ 6510 uint8_t version; 6511 6512 /** 6513 * Panel Control HW instance mask. 6514 * Bit 0 is Panel Control HW instance 0. 6515 * Bit 1 is Panel Control HW instance 1. 6516 */ 6517 uint8_t panel_mask; 6518 6519 /** 6520 * AUX HW Instance. 6521 */ 6522 uint8_t aux_inst; 6523 6524 /** 6525 * Explicit padding to 4 byte boundary. 6526 */ 6527 uint8_t pad[1]; 6528 6529 /** 6530 * Backlight control type. 6531 * Value 0 is PWM backlight control. 6532 * Value 1 is VAUX backlight control. 6533 * Value 2 is AMD DPCD AUX backlight control. 6534 */ 6535 enum dmub_backlight_control_type backlight_control_type; 6536 6537 /** 6538 * Minimum luminance in nits. 6539 */ 6540 uint32_t min_luminance; 6541 6542 /** 6543 * Maximum luminance in nits. 6544 */ 6545 uint32_t max_luminance; 6546 6547 /** 6548 * Minimum backlight in pwm. 6549 */ 6550 uint32_t min_backlight_pwm; 6551 6552 /** 6553 * Maximum backlight in pwm. 6554 */ 6555 uint32_t max_backlight_pwm; 6556 }; 6557 6558 /** 6559 * Definition of a DMUB_CMD__CACP_SET_BACKLIGHT command. 6560 */ 6561 struct dmub_rb_cmd_cacp_set_backlight { 6562 /** 6563 * Command header. 6564 */ 6565 struct dmub_cmd_header header; 6566 6567 /** 6568 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_BACKLIGHT command. 6569 */ 6570 struct dmub_cmd_cacp_set_backlight_data cacp_set_backlight_data; 6571 }; 6572 6573 /** 6574 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PWM_FRAC command. 6575 */ 6576 struct dmub_cmd_cacp_set_pwm_frac_data { 6577 /** 6578 * Enable/disable fractional duty cycle for backlight PWM. 6579 * TODO: Convert to uint8_t. 6580 */ 6581 uint32_t fractional_pwm; 6582 6583 /** 6584 * CACP control version. 6585 */ 6586 uint8_t version; 6587 6588 /** 6589 * Panel Control HW instance mask. 6590 * Bit 0 is Panel Control HW instance 0. 6591 * Bit 1 is Panel Control HW instance 1. 6592 */ 6593 uint8_t panel_mask; 6594 6595 /** 6596 * Explicit padding to 4 byte boundary. 6597 */ 6598 uint8_t pad[2]; 6599 }; 6600 6601 /** 6602 * Definition of a DMUB_CMD__CACP_SET_PWM_FRAC command. 6603 */ 6604 struct dmub_rb_cmd_cacp_set_pwm_frac { 6605 /** 6606 * Command header. 6607 */ 6608 struct dmub_cmd_header header; 6609 6610 /** 6611 * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PWM_FRAC command. 6612 */ 6613 struct dmub_cmd_cacp_set_pwm_frac_data cacp_set_pwm_frac_data; 6614 }; 6615 6616 /** 6617 * Definition of a DMUB_CMD__CACP_GET_HISTOGRAM command. 6618 */ 6619 struct dmub_rb_cmd_cacp_get_histogram { 6620 /** 6621 * Command header. 6622 */ 6623 struct dmub_cmd_header header; 6624 6625 /** 6626 * Address where Histogram should be copied. 6627 */ 6628 union dmub_addr dest; 6629 6630 /** 6631 * Type of Histogram being queried. 6632 */ 6633 enum dmub_abm_histogram_type histogram_type; 6634 6635 /** 6636 * Indirect buffer length. 6637 */ 6638 uint16_t bytes; 6639 6640 /** 6641 * eDP panel instance. 6642 */ 6643 uint8_t panel_inst; 6644 6645 /** 6646 * Explicit padding to 4 byte boundary. 6647 */ 6648 uint8_t pad; 6649 }; 6650 6651 /** 6652 * Data passed from driver to FW in a DMUB_CMD__CACP_GET_ACE_CURVE_AREA command. 6653 */ 6654 struct dmub_cmd_cacp_get_ace_curve_area_in { 6655 /** 6656 * eDP panel instance (0-based). 6657 */ 6658 uint8_t panel_inst; 6659 /** 6660 * Explicit padding to 4 byte boundary. 6661 */ 6662 uint8_t pad[3]; 6663 }; 6664 6665 /** 6666 * Data returned from FW in a DMUB_CMD__CACP_GET_ACE_CURVE_AREA command. 6667 */ 6668 struct dmub_cmd_cacp_get_ace_curve_area_out { 6669 /** 6670 * Computed area under the ACE PWL curve (trapezoidal integration). 6671 * Lower value = stronger dimming (higher CACP level). 6672 * Directly comparable across levels. 6673 */ 6674 uint32_t area; 6675 }; 6676 6677 /** 6678 * Definition of a DMUB_CMD__CACP_GET_ACE_CURVE_AREA command. 6679 * Uses inline response pattern: input and output share the data union. 6680 */ 6681 struct dmub_rb_cmd_cacp_get_ace_curve_area { 6682 /** 6683 * Command header. 6684 */ 6685 struct dmub_cmd_header header; 6686 /** 6687 * Data union for input/output. 6688 */ 6689 union { 6690 struct dmub_cmd_cacp_get_ace_curve_area_in in; 6691 struct dmub_cmd_cacp_get_ace_curve_area_out out; 6692 } data; 6693 }; 6694 6695 /** 6696 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 6697 */ 6698 struct dmub_cmd_query_feature_caps_data { 6699 /** 6700 * DMUB feature capabilities. 6701 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 6702 */ 6703 struct dmub_feature_caps feature_caps; 6704 }; 6705 6706 /** 6707 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6708 */ 6709 struct dmub_rb_cmd_query_feature_caps { 6710 /** 6711 * Command header. 6712 */ 6713 struct dmub_cmd_header header; 6714 /** 6715 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 6716 */ 6717 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 6718 }; 6719 6720 /** 6721 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6722 */ 6723 struct dmub_cmd_visual_confirm_color_data { 6724 /** 6725 * DMUB visual confirm color 6726 */ 6727 struct dmub_visual_confirm_color visual_confirm_color; 6728 }; 6729 6730 /** 6731 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6732 */ 6733 struct dmub_rb_cmd_get_visual_confirm_color { 6734 /** 6735 * Command header. 6736 */ 6737 struct dmub_cmd_header header; 6738 /** 6739 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6740 */ 6741 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 6742 }; 6743 6744 /** 6745 * enum dmub_cmd_panel_cntl_type - Panel control command. 6746 */ 6747 enum dmub_cmd_panel_cntl_type { 6748 /** 6749 * Initializes embedded panel hardware blocks. 6750 */ 6751 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 6752 /** 6753 * Queries backlight info for the embedded panel. 6754 */ 6755 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 6756 /** 6757 * Sets the PWM Freq as per user's requirement. 6758 */ 6759 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 6760 }; 6761 6762 /** 6763 * struct dmub_cmd_panel_cntl_data - Panel control data. 6764 */ 6765 struct dmub_cmd_panel_cntl_data { 6766 uint32_t pwrseq_inst; /**< pwrseq instance */ 6767 uint32_t current_backlight; /* in/out */ 6768 uint32_t bl_pwm_cntl; /* in/out */ 6769 uint32_t bl_pwm_period_cntl; /* in/out */ 6770 uint32_t bl_pwm_ref_div1; /* in/out */ 6771 uint8_t is_backlight_on : 1; /* in/out */ 6772 uint8_t is_powered_on : 1; /* in/out */ 6773 uint8_t padding[3]; 6774 uint32_t bl_pwm_ref_div2; /* in/out */ 6775 uint8_t reserved[4]; 6776 }; 6777 6778 /** 6779 * struct dmub_rb_cmd_panel_cntl - Panel control command. 6780 */ 6781 struct dmub_rb_cmd_panel_cntl { 6782 struct dmub_cmd_header header; /**< header */ 6783 struct dmub_cmd_panel_cntl_data data; /**< payload */ 6784 }; 6785 6786 struct dmub_optc_state { 6787 uint32_t v_total_max; 6788 uint32_t v_total_min; 6789 uint32_t tg_inst; 6790 }; 6791 6792 struct dmub_rb_cmd_drr_update { 6793 struct dmub_cmd_header header; 6794 struct dmub_optc_state dmub_optc_state_req; 6795 }; 6796 6797 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 6798 uint32_t pix_clk_100hz; 6799 uint8_t max_ramp_step; 6800 uint8_t pipes; 6801 uint8_t min_refresh_in_hz; 6802 uint8_t pipe_count; 6803 uint8_t pipe_index[4]; 6804 }; 6805 6806 struct dmub_cmd_fw_assisted_mclk_switch_config { 6807 uint8_t fams_enabled; 6808 uint8_t visual_confirm_enabled; 6809 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 6810 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 6811 }; 6812 6813 struct dmub_rb_cmd_fw_assisted_mclk_switch { 6814 struct dmub_cmd_header header; 6815 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 6816 }; 6817 6818 /** 6819 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6820 */ 6821 struct dmub_cmd_lvtma_control_data { 6822 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 6823 uint8_t bypass_panel_control_wait; 6824 uint8_t reserved_0[2]; /**< For future use */ 6825 uint8_t pwrseq_inst; /**< LVTMA control instance */ 6826 uint8_t reserved_1[3]; /**< For future use */ 6827 }; 6828 6829 /** 6830 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6831 */ 6832 struct dmub_rb_cmd_lvtma_control { 6833 /** 6834 * Command header. 6835 */ 6836 struct dmub_cmd_header header; 6837 /** 6838 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6839 */ 6840 struct dmub_cmd_lvtma_control_data data; 6841 }; 6842 6843 /** 6844 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6845 */ 6846 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 6847 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 6848 uint8_t is_usb; /**< is phy is usb */ 6849 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 6850 uint8_t is_dp4; /**< is dp in 4 lane */ 6851 }; 6852 6853 /** 6854 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6855 */ 6856 struct dmub_rb_cmd_transmitter_query_dp_alt { 6857 struct dmub_cmd_header header; /**< header */ 6858 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 6859 }; 6860 6861 struct phy_test_mode { 6862 uint8_t mode; 6863 uint8_t pat0; 6864 uint8_t pad[2]; 6865 }; 6866 6867 /** 6868 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6869 */ 6870 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 6871 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 6872 uint8_t mode; /**< HDMI/DP/DP2 etc */ 6873 uint8_t lane_num; /**< Number of lanes */ 6874 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 6875 struct phy_test_mode test_mode; 6876 enum dmub_phy_fsm_state state; 6877 uint32_t status; 6878 uint8_t pad; 6879 }; 6880 6881 /** 6882 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6883 */ 6884 struct dmub_rb_cmd_transmitter_set_phy_fsm { 6885 struct dmub_cmd_header header; /**< header */ 6886 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 6887 }; 6888 6889 /** 6890 * Maximum number of bytes a chunk sent to DMUB for parsing 6891 */ 6892 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 6893 6894 /** 6895 * Represent a chunk of CEA blocks sent to DMUB for parsing 6896 */ 6897 struct dmub_cmd_send_edid_cea { 6898 uint16_t offset; /**< offset into the CEA block */ 6899 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 6900 uint16_t cea_total_length; /**< total length of the CEA block */ 6901 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 6902 uint8_t pad[3]; /**< padding and for future expansion */ 6903 }; 6904 6905 /** 6906 * Result of VSDB parsing from CEA block 6907 */ 6908 struct dmub_cmd_edid_cea_amd_vsdb { 6909 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 6910 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 6911 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 6912 uint16_t min_frame_rate; /**< Maximum frame rate */ 6913 uint16_t max_frame_rate; /**< Minimum frame rate */ 6914 uint8_t freesync_mccs_vcp_code; /**< Freesync MCCS VCP code */ 6915 }; 6916 6917 /** 6918 * Result of sending a CEA chunk 6919 */ 6920 struct dmub_cmd_edid_cea_ack { 6921 uint16_t offset; /**< offset of the chunk into the CEA block */ 6922 uint8_t success; /**< 1 if this sending of chunk succeeded */ 6923 uint8_t pad; /**< padding and for future expansion */ 6924 }; 6925 6926 /** 6927 * Specify whether the result is an ACK/NACK or the parsing has finished 6928 */ 6929 enum dmub_cmd_edid_cea_reply_type { 6930 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 6931 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 6932 }; 6933 6934 /** 6935 * Definition of a DMUB_CMD__EDID_CEA command. 6936 */ 6937 struct dmub_rb_cmd_edid_cea { 6938 struct dmub_cmd_header header; /**< Command header */ 6939 union dmub_cmd_edid_cea_data { 6940 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 6941 struct dmub_cmd_edid_cea_output { /**< output with results */ 6942 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 6943 union { 6944 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 6945 struct dmub_cmd_edid_cea_ack ack; 6946 }; 6947 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 6948 } data; /**< Command data */ 6949 6950 }; 6951 6952 /** 6953 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 6954 */ 6955 struct dmub_cmd_cable_id_input { 6956 uint8_t phy_inst; /**< phy inst for cable id data */ 6957 }; 6958 6959 /** 6960 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 6961 */ 6962 struct dmub_cmd_cable_id_output { 6963 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 6964 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 6965 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 6966 uint8_t RESERVED :2; /**< reserved means not defined */ 6967 }; 6968 6969 /** 6970 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 6971 */ 6972 struct dmub_rb_cmd_get_usbc_cable_id { 6973 struct dmub_cmd_header header; /**< Command header */ 6974 /** 6975 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 6976 */ 6977 union dmub_cmd_cable_id_data { 6978 struct dmub_cmd_cable_id_input input; /**< Input */ 6979 struct dmub_cmd_cable_id_output output; /**< Output */ 6980 uint8_t output_raw; /**< Raw data output */ 6981 } data; 6982 }; 6983 6984 enum dmub_cmd_fused_io_sub_type { 6985 DMUB_CMD__FUSED_IO_EXECUTE = 0, 6986 DMUB_CMD__FUSED_IO_ABORT = 1, 6987 }; 6988 6989 enum dmub_cmd_fused_request_type { 6990 FUSED_REQUEST_READ, 6991 FUSED_REQUEST_WRITE, 6992 FUSED_REQUEST_POLL, 6993 }; 6994 6995 enum dmub_cmd_fused_request_status { 6996 FUSED_REQUEST_STATUS_SUCCESS, 6997 FUSED_REQUEST_STATUS_BEGIN, 6998 FUSED_REQUEST_STATUS_SUBMIT, 6999 FUSED_REQUEST_STATUS_REPLY, 7000 FUSED_REQUEST_STATUS_POLL, 7001 FUSED_REQUEST_STATUS_ABORTED, 7002 FUSED_REQUEST_STATUS_FAILED = 0x80, 7003 FUSED_REQUEST_STATUS_INVALID, 7004 FUSED_REQUEST_STATUS_BUSY, 7005 FUSED_REQUEST_STATUS_TIMEOUT, 7006 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 7007 }; 7008 7009 struct dmub_cmd_fused_request { 7010 uint8_t status; 7011 uint8_t type : 2; 7012 uint8_t _reserved0 : 3; 7013 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 7014 uint8_t identifier; 7015 uint8_t _reserved1; 7016 uint32_t timeout_us; 7017 union dmub_cmd_fused_request_location { 7018 struct dmub_cmd_fused_request_location_i2c { 7019 uint8_t is_aux : 1; // False 7020 uint8_t ddc_line : 3; 7021 uint8_t over_aux : 1; 7022 uint8_t _reserved0 : 3; 7023 uint8_t address; 7024 uint8_t offset; 7025 uint8_t length; 7026 } i2c; 7027 struct dmub_cmd_fused_request_location_aux { 7028 uint32_t is_aux : 1; // True 7029 uint32_t ddc_line : 3; 7030 uint32_t address : 20; 7031 uint32_t length : 8; // Automatically split into 16B transactions 7032 } aux; 7033 } u; 7034 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 7035 }; 7036 7037 struct dmub_rb_cmd_fused_io { 7038 struct dmub_cmd_header header; 7039 struct dmub_cmd_fused_request request; 7040 }; 7041 7042 /** 7043 * Command type of a DMUB_CMD__SECURE_DISPLAY command 7044 */ 7045 enum dmub_cmd_secure_display_type { 7046 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 7047 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 7048 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 7049 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 7050 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 7051 }; 7052 7053 #define MAX_ROI_NUM 2 7054 7055 struct dmub_cmd_roi_info { 7056 uint16_t x_start; 7057 uint16_t x_end; 7058 uint16_t y_start; 7059 uint16_t y_end; 7060 uint8_t otg_id; 7061 uint8_t phy_id; 7062 }; 7063 7064 struct dmub_cmd_roi_window_ctl { 7065 uint16_t x_start; 7066 uint16_t x_end; 7067 uint16_t y_start; 7068 uint16_t y_end; 7069 bool enable; 7070 }; 7071 7072 struct dmub_cmd_roi_ctl_info { 7073 uint8_t otg_id; 7074 uint8_t phy_id; 7075 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 7076 }; 7077 7078 /** 7079 * Definition of a DMUB_CMD__SECURE_DISPLAY command 7080 */ 7081 struct dmub_rb_cmd_secure_display { 7082 struct dmub_cmd_header header; 7083 /** 7084 * Data passed from driver to dmub firmware. 7085 */ 7086 struct dmub_cmd_roi_info roi_info; 7087 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 7088 }; 7089 7090 /** 7091 * Command type of a DMUB_CMD__PSP command 7092 */ 7093 enum dmub_cmd_psp_type { 7094 DMUB_CMD__PSP_ASSR_ENABLE = 0 7095 }; 7096 7097 /** 7098 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 7099 */ 7100 struct dmub_cmd_assr_enable_data { 7101 /** 7102 * ASSR enable or disable. 7103 */ 7104 uint8_t enable; 7105 /** 7106 * PHY port type. 7107 * Indicates eDP / non-eDP port type 7108 */ 7109 uint8_t phy_port_type; 7110 /** 7111 * PHY port ID. 7112 */ 7113 uint8_t phy_port_id; 7114 /** 7115 * Link encoder index. 7116 */ 7117 uint8_t link_enc_index; 7118 /** 7119 * HPO mode. 7120 */ 7121 uint8_t hpo_mode; 7122 7123 /** 7124 * Reserved field. 7125 */ 7126 uint8_t reserved[7]; 7127 }; 7128 7129 /** 7130 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 7131 */ 7132 struct dmub_rb_cmd_assr_enable { 7133 /** 7134 * Command header. 7135 */ 7136 struct dmub_cmd_header header; 7137 7138 /** 7139 * Assr data. 7140 */ 7141 struct dmub_cmd_assr_enable_data assr_data; 7142 7143 /** 7144 * Reserved field. 7145 */ 7146 uint32_t reserved[3]; 7147 }; 7148 7149 /** 7150 * Current definition of "ips_mode" from driver 7151 */ 7152 enum ips_residency_mode { 7153 IPS_RESIDENCY__IPS1_MAX, 7154 IPS_RESIDENCY__IPS2, 7155 IPS_RESIDENCY__IPS1_RCG, // refers to IPS0 + RCG 7156 IPS_RESIDENCY__IPS1_ONO2_ON, 7157 IPS_RESIDENCY__IPS1_Z8_RETENTION, 7158 IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, 7159 IPS_RESIDENCY__PG_ONO_CURRENT_STATE 7160 }; 7161 7162 #define NUM_IPS_HISTOGRAM_BUCKETS 16 7163 7164 /** 7165 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 7166 */ 7167 struct dmub_ips_residency_info { 7168 uint32_t residency_millipercent; 7169 uint32_t entry_counter; 7170 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 7171 uint64_t total_time_us; 7172 uint64_t total_inactive_time_us; 7173 uint32_t ono_pg_state_at_collection; 7174 uint32_t ono_pg_state_last_seen_in_ips; 7175 }; 7176 7177 /** 7178 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 7179 */ 7180 struct dmub_cmd_ips_residency_cntl_data { 7181 uint8_t panel_inst; 7182 uint8_t start_measurement; 7183 uint8_t padding[2]; // align to 4-byte boundary 7184 }; 7185 7186 struct dmub_rb_cmd_ips_residency_cntl { 7187 struct dmub_cmd_header header; 7188 struct dmub_cmd_ips_residency_cntl_data cntl_data; 7189 }; 7190 7191 /** 7192 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 7193 */ 7194 struct dmub_cmd_ips_query_residency_info_data { 7195 union dmub_addr dest; 7196 uint32_t size; 7197 uint32_t ips_mode; 7198 uint8_t panel_inst; 7199 uint8_t padding[3]; // align to 4-byte boundary 7200 }; 7201 7202 struct dmub_rb_cmd_ips_query_residency_info { 7203 struct dmub_cmd_header header; 7204 struct dmub_cmd_ips_query_residency_info_data info_data; 7205 }; 7206 7207 /** 7208 * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command. 7209 */ 7210 struct dmub_cmd_cursor_offload_init_data { 7211 union dmub_addr state_addr; /**< State address for dmub_cursor_offload */ 7212 uint32_t state_size; /**< State size for dmub_cursor_offload */ 7213 }; 7214 7215 /** 7216 * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload. 7217 */ 7218 struct dmub_rb_cmd_cursor_offload_init { 7219 struct dmub_cmd_header header; 7220 struct dmub_cmd_cursor_offload_init_data init_data; 7221 }; 7222 7223 /** 7224 * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command. 7225 */ 7226 struct dmub_cmd_cursor_offload_stream_data { 7227 uint32_t otg_inst: 4; /**< OTG instance to control */ 7228 uint32_t reserved: 28; /**< Reserved for future use */ 7229 uint32_t line_time_in_ns; /**< Line time in ns for the OTG */ 7230 uint32_t v_total_max; /**< OTG v_total_max */ 7231 }; 7232 7233 /** 7234 * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload. 7235 */ 7236 struct dmub_rb_cmd_cursor_offload_stream_cntl { 7237 struct dmub_cmd_header header; 7238 struct dmub_cmd_cursor_offload_stream_data data; 7239 }; 7240 7241 /** 7242 * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command. 7243 */ 7244 struct dmub_cmd_pr_enable_data { 7245 /** 7246 * Panel Replay enable or disable. 7247 */ 7248 uint8_t enable; 7249 /** 7250 * Panel Instance. 7251 * Panel isntance to identify which replay_state to use 7252 * Currently the support is only for 0 or 1 7253 */ 7254 uint8_t panel_inst; 7255 /** 7256 * Phy state to enter. 7257 * Values to use are defined in dmub_phy_fsm_state 7258 */ 7259 uint8_t phy_fsm_state; 7260 /** 7261 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 7262 * Set this using enum phy_link_rate. 7263 * This does not support HDMI/DP2 for now. 7264 */ 7265 uint8_t phy_rate; 7266 /** 7267 * @hpo_stream_enc_inst: HPO stream encoder instance 7268 */ 7269 uint8_t hpo_stream_enc_inst; 7270 /** 7271 * @hpo_link_enc_inst: HPO link encoder instance 7272 */ 7273 uint8_t hpo_link_enc_inst; 7274 /** 7275 * @pad: Align structure to 4 byte boundary. 7276 */ 7277 uint8_t pad[2]; 7278 }; 7279 7280 struct dmub_cmd_panel_polarity_enable_data { 7281 /** 7282 * Panel Polarity enable or disable. 7283 */ 7284 uint8_t enable; 7285 /** 7286 * OTG instance 7287 */ 7288 uint8_t otg_inst; 7289 /** 7290 * @pad: Align structure to 4 byte boundary. 7291 */ 7292 uint8_t pad[2]; 7293 }; 7294 7295 struct dmub_cmd_panel_polarity_reset_data { 7296 /** 7297 * OTG instance 7298 */ 7299 uint8_t otg_inst; 7300 /** 7301 * @pad: Align structure to 4 byte boundary. 7302 */ 7303 uint8_t pad[3]; 7304 }; 7305 7306 struct dmub_cmd_panel_polarity_get_bias_input { 7307 /** 7308 * OTG instance 7309 */ 7310 uint8_t otg_inst; 7311 uint8_t pad[3]; 7312 }; 7313 7314 struct dmub_cmd_panel_polarity_get_bias_output { 7315 /** 7316 * Accumulated Polarity Bias 7317 */ 7318 int32_t accumulated_bias; 7319 }; 7320 7321 struct dmub_rb_cmd_panel_polarity_enable { 7322 /** 7323 * Command header. 7324 */ 7325 struct dmub_cmd_header header; 7326 7327 struct dmub_cmd_panel_polarity_enable_data data; 7328 }; 7329 7330 7331 struct dmub_rb_cmd_panel_polarity_get_bias { 7332 /** 7333 * Command header. 7334 */ 7335 struct dmub_cmd_header header; 7336 7337 union dmub_cmd_panel_polarity_get_bias_data { 7338 struct dmub_cmd_panel_polarity_get_bias_input input; /**< Input */ 7339 struct dmub_cmd_panel_polarity_get_bias_output output; /**< Output */ 7340 uint32_t output_raw; /**< Raw data output */ 7341 } data; 7342 }; 7343 7344 struct dmub_rb_cmd_panel_polarity_reset { 7345 /** 7346 * Command header. 7347 */ 7348 struct dmub_cmd_header header; 7349 7350 struct dmub_cmd_panel_polarity_reset_data data; 7351 }; 7352 7353 7354 /** 7355 * Definition of a DMUB_CMD__PR_ENABLE command. 7356 * Panel Replay enable/disable is controlled using action in data. 7357 */ 7358 struct dmub_rb_cmd_pr_enable { 7359 /** 7360 * Command header. 7361 */ 7362 struct dmub_cmd_header header; 7363 7364 struct dmub_cmd_pr_enable_data data; 7365 }; 7366 7367 /** 7368 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 7369 */ 7370 struct dmub_cmd_pr_copy_settings_data { 7371 /** 7372 * Flags that can be set by driver to change some replay behaviour. 7373 */ 7374 union pr_debug_flags debug; 7375 7376 /** 7377 * @flags: Flags used to determine feature functionality. 7378 */ 7379 union pr_hw_flags flags; 7380 7381 /** 7382 * DPP HW instance. 7383 */ 7384 uint8_t dpp_inst; 7385 /** 7386 * OTG HW instance. 7387 */ 7388 uint8_t otg_inst; 7389 /** 7390 * DIG FE HW instance. 7391 */ 7392 uint8_t digfe_inst; 7393 /** 7394 * DIG BE HW instance. 7395 */ 7396 uint8_t digbe_inst; 7397 /** 7398 * AUX HW instance. 7399 */ 7400 uint8_t aux_inst; 7401 /** 7402 * Panel Instance. 7403 * Panel isntance to identify which psr_state to use 7404 * Currently the support is only for 0 or 1 7405 */ 7406 uint8_t panel_inst; 7407 /** 7408 * PHY instance. 7409 */ 7410 uint8_t dpphy_inst; 7411 /** 7412 * Determines if SMU optimzations are enabled/disabled. 7413 */ 7414 uint8_t smu_optimizations_en; 7415 /** 7416 * Length of each horizontal line in ns. 7417 */ 7418 uint32_t line_time_in_ns; 7419 /* 7420 * Use FSFT afftet pixel clk 7421 */ 7422 uint32_t pix_clk_100hz; 7423 /* 7424 * Use Original pixel clock 7425 */ 7426 uint32_t sink_pix_clk_100hz; 7427 /** 7428 * Use for AUX-less ALPM LFPS wake operation 7429 */ 7430 struct dmub_alpm_auxless_data auxless_alpm_data; 7431 /** 7432 * DSC Slice height. 7433 */ 7434 uint16_t dsc_slice_height; 7435 /* 7436 * Use FSM state for Replay power up/down 7437 */ 7438 uint8_t use_phy_fsm; 7439 /** 7440 * @hpo_stream_enc_inst: HPO stream encoder instance 7441 */ 7442 uint8_t hpo_stream_enc_inst; 7443 /** 7444 * @hpo_link_enc_inst: HPO link encoder instance 7445 */ 7446 uint8_t hpo_link_enc_inst; 7447 /* 7448 * Selective Update granularity needed. 7449 */ 7450 uint8_t su_granularity_needed; 7451 /* 7452 * Horizontal granularity for Selective Update. 7453 */ 7454 uint16_t su_x_granularity; 7455 /* 7456 * Extended caps of vertical granularity for Selective Update. 7457 */ 7458 uint16_t su_y_granularity_extended_caps; 7459 /* 7460 * Vertical granularity for Selective Update. 7461 */ 7462 uint8_t su_y_granularity; 7463 /** 7464 * @main_link_activity_option: Indicates main link activity option selected 7465 */ 7466 uint8_t main_link_activity_option; 7467 }; 7468 7469 /** 7470 * Definition of a DMUB_CMD__PR_COPY_SETTINGS command. 7471 */ 7472 struct dmub_rb_cmd_pr_copy_settings { 7473 /** 7474 * Command header. 7475 */ 7476 struct dmub_cmd_header header; 7477 /** 7478 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 7479 */ 7480 struct dmub_cmd_pr_copy_settings_data data; 7481 }; 7482 7483 union dmub_pr_runtime_flags { 7484 struct { 7485 uint32_t disable_abm_optimization : 1; // Disable ABM optimization for PR 7486 uint32_t abm_periodic_ffu_allowed : 1; // DAL: scenario wants periodic ABM keep-alive FFU 7487 } bitfields; 7488 uint32_t u32All; 7489 }; 7490 7491 struct dmub_cmd_pr_update_state_data { 7492 /** 7493 * Panel Instance. 7494 * Panel isntance to identify which psr_state to use 7495 * Currently the support is only for 0 or 1 7496 */ 7497 uint8_t panel_inst; 7498 7499 uint8_t pad[3]; // align to 4-byte boundary 7500 /* 7501 * Update flags to control the update behavior. 7502 */ 7503 uint32_t update_flag; 7504 /** 7505 * state/data to set. 7506 */ 7507 uint32_t coasting_vtotal; 7508 uint32_t sync_mode; 7509 uint32_t pseudo_vtotal; 7510 7511 union dmub_pr_runtime_flags pr_runtime_flags; 7512 }; 7513 7514 struct dmub_cmd_pr_general_cmd_data { 7515 /** 7516 * Panel Instance. 7517 * Panel isntance to identify which psr_state to use 7518 * Currently the support is only for 0 or 1 7519 */ 7520 uint8_t panel_inst; 7521 /** 7522 * subtype: PR general cmd sub type 7523 */ 7524 uint8_t subtype; 7525 7526 uint8_t pad[2]; 7527 /** 7528 * config data by different subtypes 7529 */ 7530 union { 7531 uint32_t u32All; 7532 } data; 7533 }; 7534 7535 /** 7536 * Definition of a DMUB_CMD__PR_UPDATE_STATE command. 7537 */ 7538 struct dmub_rb_cmd_pr_update_state { 7539 /** 7540 * Command header. 7541 */ 7542 struct dmub_cmd_header header; 7543 /** 7544 * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command. 7545 */ 7546 struct dmub_cmd_pr_update_state_data data; 7547 }; 7548 7549 /** 7550 * Definition of a DMUB_CMD__PR_GENERAL_CMD command. 7551 */ 7552 struct dmub_rb_cmd_pr_general_cmd { 7553 /** 7554 * Command header. 7555 */ 7556 struct dmub_cmd_header header; 7557 /** 7558 * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command. 7559 */ 7560 struct dmub_cmd_pr_general_cmd_data data; 7561 }; 7562 7563 /** 7564 * Command type of a DMUB_CMD__BOOT_TIME_CRC command 7565 */ 7566 enum dmub_cmd_boot_time_crc_type { 7567 DMUB_CMD__BOOT_TIME_CRC_INIT_MEM = 0 7568 }; 7569 7570 /** 7571 * Data passed from driver to FW in a DMUB_CMD__BOOT_TIME_CRC_INIT command. 7572 */ 7573 struct dmub_cmd_boot_time_crc_init_data { 7574 union dmub_addr buffer_addr; 7575 uint32_t buffer_size; 7576 }; 7577 7578 /** 7579 * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command. 7580 */ 7581 struct dmub_rb_cmd_boot_time_crc_init { 7582 struct dmub_cmd_header header; 7583 struct dmub_cmd_boot_time_crc_init_data data; 7584 }; 7585 7586 /** 7587 * union dmub_rb_cmd - DMUB inbox command. 7588 */ 7589 union dmub_rb_cmd { 7590 /** 7591 * Elements shared with all commands. 7592 */ 7593 struct dmub_rb_cmd_common cmd_common; 7594 /** 7595 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 7596 */ 7597 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 7598 /** 7599 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 7600 */ 7601 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 7602 /** 7603 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 7604 */ 7605 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 7606 /** 7607 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 7608 */ 7609 struct dmub_rb_cmd_dpphy_init dpphy_init; 7610 /** 7611 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 7612 */ 7613 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 7614 /** 7615 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 7616 */ 7617 struct dmub_rb_cmd_domain_control domain_control; 7618 /** 7619 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 7620 */ 7621 struct dmub_rb_cmd_psr_set_version psr_set_version; 7622 /** 7623 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 7624 */ 7625 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 7626 /** 7627 * Definition of a DMUB_CMD__PSR_ENABLE command. 7628 */ 7629 struct dmub_rb_cmd_psr_enable psr_enable; 7630 /** 7631 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 7632 */ 7633 struct dmub_rb_cmd_psr_set_level psr_set_level; 7634 /** 7635 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 7636 */ 7637 struct dmub_rb_cmd_psr_force_static psr_force_static; 7638 /** 7639 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 7640 */ 7641 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 7642 /** 7643 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 7644 */ 7645 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 7646 /** 7647 * Definition of a DMUB_CMD__HW_LOCK command. 7648 * Command is used by driver and FW. 7649 */ 7650 struct dmub_rb_cmd_lock_hw lock_hw; 7651 /** 7652 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 7653 */ 7654 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 7655 /** 7656 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 7657 */ 7658 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 7659 /** 7660 * Definition of a DMUB_CMD__PLAT_54186_WA command. 7661 */ 7662 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 7663 /** 7664 * Definition of a DMUB_CMD__MALL command. 7665 */ 7666 struct dmub_rb_cmd_mall mall; 7667 7668 /** 7669 * Definition of a DMUB_CMD__CAB command. 7670 */ 7671 struct dmub_rb_cmd_cab_for_ss cab; 7672 7673 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 7674 7675 /** 7676 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 7677 */ 7678 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 7679 7680 /** 7681 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 7682 */ 7683 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 7684 7685 /** 7686 * Definition of DMUB_CMD__PANEL_CNTL commands. 7687 */ 7688 struct dmub_rb_cmd_panel_cntl panel_cntl; 7689 7690 /** 7691 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 7692 */ 7693 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 7694 7695 /** 7696 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 7697 */ 7698 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 7699 7700 /** 7701 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 7702 */ 7703 struct dmub_rb_cmd_abm_set_level abm_set_level; 7704 7705 /** 7706 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 7707 */ 7708 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 7709 7710 /** 7711 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 7712 */ 7713 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 7714 7715 /** 7716 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 7717 */ 7718 struct dmub_rb_cmd_abm_init_config abm_init_config; 7719 7720 /** 7721 * Definition of a DMUB_CMD__ABM_PAUSE command. 7722 */ 7723 struct dmub_rb_cmd_abm_pause abm_pause; 7724 7725 /** 7726 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 7727 */ 7728 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 7729 7730 /** 7731 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 7732 */ 7733 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 7734 7735 /** 7736 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 7737 */ 7738 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 7739 7740 /** 7741 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 7742 */ 7743 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 7744 7745 /** 7746 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 7747 */ 7748 struct dmub_rb_cmd_abm_set_event abm_set_event; 7749 7750 /** 7751 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 7752 */ 7753 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 7754 7755 /** 7756 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 7757 */ 7758 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 7759 7760 /** 7761 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 7762 */ 7763 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 7764 7765 /** 7766 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 7767 */ 7768 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 7769 struct dmub_rb_cmd_drr_update drr_update; 7770 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 7771 7772 /** 7773 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 7774 */ 7775 struct dmub_rb_cmd_lvtma_control lvtma_control; 7776 /** 7777 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 7778 */ 7779 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 7780 /** 7781 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 7782 */ 7783 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 7784 /** 7785 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 7786 */ 7787 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 7788 /** 7789 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 7790 */ 7791 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 7792 /** 7793 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 7794 */ 7795 struct dmub_rb_cmd_set_config_request set_config_request; 7796 /** 7797 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 7798 */ 7799 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 7800 /** 7801 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 7802 */ 7803 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 7804 /** 7805 * Definition of a DMUB_CMD__EDID_CEA command. 7806 */ 7807 struct dmub_rb_cmd_edid_cea edid_cea; 7808 /** 7809 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 7810 */ 7811 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 7812 7813 /** 7814 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 7815 */ 7816 struct dmub_rb_cmd_query_hpd_state query_hpd; 7817 /** 7818 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 7819 */ 7820 struct dmub_rb_cmd_secure_display secure_display; 7821 7822 /** 7823 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 7824 */ 7825 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 7826 7827 /** 7828 * Definition of a DMUB_CMD__CACP_SET_PIPE command. 7829 */ 7830 struct dmub_rb_cmd_cacp_set_pipe cacp_set_pipe; 7831 7832 /** 7833 * Definition of a DMUB_CMD__CACP_SET_LEVEL command. 7834 */ 7835 struct dmub_rb_cmd_cacp_set_level cacp_set_level; 7836 7837 /** 7838 * Definition of a DMUB_CMD__CACP_SET_EVENT command. 7839 */ 7840 struct dmub_rb_cmd_cacp_set_event cacp_set_event; 7841 7842 /** 7843 * Definition of a DMUB_CMD__CACP_INIT_CONFIG command. 7844 */ 7845 struct dmub_rb_cmd_cacp_init_config cacp_init_config; 7846 7847 /** 7848 * Definition of a DMUB_CMD__CACP_PAUSE command. 7849 */ 7850 struct dmub_rb_cmd_cacp_pause cacp_pause; 7851 7852 /** 7853 * Definition of a DMUB_CMD__CACP_SET_BACKLIGHT command. 7854 */ 7855 struct dmub_rb_cmd_cacp_set_backlight cacp_set_backlight; 7856 7857 /** 7858 * Definition of a DMUB_CMD__CACP_SET_PWM_FRAC command. 7859 */ 7860 struct dmub_rb_cmd_cacp_set_pwm_frac cacp_set_pwm_frac; 7861 7862 /** 7863 * Definition of a DMUB_CMD__CACP_GET_HISTOGRAM command. 7864 */ 7865 struct dmub_rb_cmd_cacp_get_histogram cacp_get_histogram; 7866 7867 /** 7868 * Definition of a DMUB_CMD__CACP_GET_ACE_CURVE_AREA command. 7869 */ 7870 struct dmub_rb_cmd_cacp_get_ace_curve_area cacp_get_ace_curve_area; 7871 7872 /** 7873 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 7874 */ 7875 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 7876 /** 7877 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 7878 */ 7879 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 7880 /* 7881 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 7882 */ 7883 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 7884 /** 7885 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 7886 */ 7887 struct dmub_rb_cmd_replay_enable replay_enable; 7888 /** 7889 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 7890 */ 7891 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 7892 /** 7893 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 7894 */ 7895 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 7896 /** 7897 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 7898 */ 7899 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 7900 7901 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 7902 /** 7903 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 7904 */ 7905 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 7906 /** 7907 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 7908 */ 7909 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 7910 /** 7911 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 7912 */ 7913 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 7914 /** 7915 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 7916 */ 7917 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 7918 /** 7919 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 7920 */ 7921 struct dmub_rb_cmd_assr_enable assr_enable; 7922 7923 struct dmub_rb_cmd_fams2 fams2_config; 7924 7925 struct dmub_rb_cmd_ib ib_fams2_config; 7926 7927 struct dmub_rb_cmd_ib ib_fams2_debug_meta; 7928 7929 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 7930 7931 struct dmub_rb_cmd_fams2_flip fams2_flip; 7932 7933 struct dmub_rb_cmd_fused_io fused_io; 7934 7935 /** 7936 * Definition of a DMUB_CMD__LSDMA command. 7937 */ 7938 struct dmub_rb_cmd_lsdma lsdma; 7939 7940 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 7941 7942 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 7943 /** 7944 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command. 7945 */ 7946 struct dmub_rb_cmd_cursor_offload_init cursor_offload_init; 7947 /** 7948 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands. 7949 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE 7950 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE 7951 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM 7952 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR 7953 */ 7954 struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; 7955 /** 7956 * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 7957 */ 7958 struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable; 7959 /** 7960 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 7961 */ 7962 struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll; 7963 /* 7964 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 7965 */ 7966 struct dmub_rb_cmd_pr_copy_settings pr_copy_settings; 7967 /** 7968 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 7969 */ 7970 struct dmub_rb_cmd_pr_enable pr_enable; 7971 7972 struct dmub_rb_cmd_pr_update_state pr_update_state; 7973 7974 struct dmub_rb_cmd_pr_general_cmd pr_general_cmd; 7975 7976 /** 7977 * Definition of a DMUB_CMD__IHC command. 7978 */ 7979 struct dmub_rb_cmd_ihc ihc; 7980 /** 7981 * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command. 7982 */ 7983 struct dmub_rb_cmd_boot_time_crc_init boot_time_crc_init; 7984 7985 /** 7986 * Definition of a DMUB_CMD__PANEL_POLARITY_ENABLE command. 7987 */ 7988 struct dmub_rb_cmd_panel_polarity_enable panel_polarity_enable; 7989 struct dmub_rb_cmd_panel_polarity_get_bias panel_polarity_get_bias; 7990 struct dmub_rb_cmd_panel_polarity_reset panel_polarity_reset; 7991 }; 7992 7993 /** 7994 * union dmub_rb_out_cmd - Outbox command 7995 */ 7996 union dmub_rb_out_cmd { 7997 /** 7998 * Parameters common to every command. 7999 */ 8000 struct dmub_rb_cmd_common cmd_common; 8001 /** 8002 * AUX reply command. 8003 */ 8004 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 8005 /** 8006 * HPD notify command. 8007 */ 8008 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 8009 /** 8010 * SET_CONFIG reply command. 8011 */ 8012 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 8013 /** 8014 * DPIA notification command. 8015 */ 8016 struct dmub_rb_cmd_dpia_notification dpia_notification; 8017 /** 8018 * HPD sense notification command. 8019 */ 8020 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 8021 struct dmub_rb_cmd_fused_io fused_io; 8022 }; 8023 #pragma pack(pop) 8024 8025 8026 //============================================================================== 8027 //</DMUB_CMD>=================================================================== 8028 //============================================================================== 8029 //< DMUB_RB>==================================================================== 8030 //============================================================================== 8031 8032 /** 8033 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 8034 */ 8035 struct dmub_rb_init_params { 8036 void *ctx; /**< Caller provided context pointer */ 8037 void *base_address; /**< CPU base address for ring's data */ 8038 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 8039 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 8040 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 8041 }; 8042 8043 /** 8044 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 8045 */ 8046 struct dmub_rb { 8047 void *base_address; /**< CPU address for the ring's data */ 8048 uint32_t rptr; /**< Read pointer for consumer in bytes */ 8049 uint32_t wrpt; /**< Write pointer for producer in bytes */ 8050 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 8051 8052 void *ctx; /**< Caller provided context pointer */ 8053 void *dmub; /**< Pointer to the DMUB interface */ 8054 }; 8055 8056 /** 8057 * @brief Checks if the ringbuffer is empty. 8058 * 8059 * @param rb DMUB Ringbuffer 8060 * @return true if empty 8061 * @return false otherwise 8062 */ 8063 static inline bool dmub_rb_empty(struct dmub_rb *rb) 8064 { 8065 return (rb->wrpt == rb->rptr); 8066 } 8067 8068 /** 8069 * @brief gets number of outstanding requests in the RB 8070 * 8071 * @param rb DMUB Ringbuffer 8072 * @return true if full 8073 */ 8074 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 8075 { 8076 uint32_t data_count; 8077 8078 if (rb->wrpt >= rb->rptr) 8079 data_count = rb->wrpt - rb->rptr; 8080 else 8081 data_count = rb->capacity - (rb->rptr - rb->wrpt); 8082 8083 return data_count / DMUB_RB_CMD_SIZE; 8084 } 8085 8086 /** 8087 * @brief gets number of free buffers in the RB 8088 * 8089 * @param rb DMUB Ringbuffer 8090 * @return true if full 8091 */ 8092 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 8093 { 8094 uint32_t data_count; 8095 8096 if (rb->wrpt >= rb->rptr) 8097 data_count = rb->wrpt - rb->rptr; 8098 else 8099 data_count = rb->capacity - (rb->rptr - rb->wrpt); 8100 8101 /* +1 because 1 entry is always unusable */ 8102 data_count += DMUB_RB_CMD_SIZE; 8103 8104 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 8105 } 8106 8107 /** 8108 * @brief Checks if the ringbuffer is full 8109 * 8110 * @param rb DMUB Ringbuffer 8111 * @return true if full 8112 * @return false otherwise 8113 */ 8114 static inline bool dmub_rb_full(struct dmub_rb *rb) 8115 { 8116 uint32_t data_count; 8117 8118 if (rb->wrpt >= rb->rptr) 8119 data_count = rb->wrpt - rb->rptr; 8120 else 8121 data_count = rb->capacity - (rb->rptr - rb->wrpt); 8122 8123 /* -1 because 1 entry is always unusable */ 8124 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 8125 } 8126 8127 /** 8128 * @brief Pushes a command into the ringbuffer 8129 * 8130 * @param rb DMUB ringbuffer 8131 * @param cmd The command to push 8132 * @return true if the ringbuffer was not full 8133 * @return false otherwise 8134 */ 8135 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 8136 const union dmub_rb_cmd *cmd) 8137 { 8138 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 8139 const uint8_t *src = (const uint8_t *)cmd; 8140 uint8_t i; 8141 8142 if (rb->capacity == 0) 8143 return false; 8144 8145 if (dmub_rb_full(rb)) 8146 return false; 8147 8148 // copying data 8149 for (i = 0; i < DMUB_RB_CMD_SIZE; i++) 8150 *dst++ = *src++; 8151 8152 rb->wrpt += DMUB_RB_CMD_SIZE; 8153 8154 if (rb->wrpt >= rb->capacity) 8155 rb->wrpt %= rb->capacity; 8156 8157 return true; 8158 } 8159 8160 /** 8161 * @brief Pushes a command into the DMUB outbox ringbuffer 8162 * 8163 * @param rb DMUB outbox ringbuffer 8164 * @param cmd Outbox command 8165 * @return true if not full 8166 * @return false otherwise 8167 */ 8168 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 8169 const union dmub_rb_out_cmd *cmd) 8170 { 8171 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 8172 const uint8_t *src = (const uint8_t *)cmd; 8173 8174 if (rb->capacity == 0) 8175 return false; 8176 8177 if (dmub_rb_full(rb)) 8178 return false; 8179 8180 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 8181 8182 rb->wrpt += DMUB_RB_CMD_SIZE; 8183 8184 if (rb->wrpt >= rb->capacity) 8185 rb->wrpt %= rb->capacity; 8186 8187 return true; 8188 } 8189 8190 /** 8191 * @brief Returns the next unprocessed command in the ringbuffer. 8192 * 8193 * @param rb DMUB ringbuffer 8194 * @param cmd The command to return 8195 * @return true if not empty 8196 * @return false otherwise 8197 */ 8198 static inline bool dmub_rb_front(struct dmub_rb *rb, 8199 union dmub_rb_cmd **cmd) 8200 { 8201 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 8202 8203 if (dmub_rb_empty(rb)) 8204 return false; 8205 8206 *cmd = (union dmub_rb_cmd *)rb_cmd; 8207 8208 return true; 8209 } 8210 8211 /** 8212 * @brief Determines the next ringbuffer offset. 8213 * 8214 * @param rb DMUB inbox ringbuffer 8215 * @param num_cmds Number of commands 8216 * @param next_rptr The next offset in the ringbuffer 8217 */ 8218 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 8219 uint32_t num_cmds, 8220 uint32_t *next_rptr) 8221 { 8222 if (rb->capacity == 0) 8223 return; 8224 8225 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 8226 8227 if (*next_rptr >= rb->capacity) 8228 *next_rptr %= rb->capacity; 8229 } 8230 8231 /** 8232 * @brief Returns a pointer to a command in the inbox. 8233 * 8234 * @param rb DMUB inbox ringbuffer 8235 * @param cmd The inbox command to return 8236 * @param rptr The ringbuffer offset 8237 * @return true if not empty 8238 * @return false otherwise 8239 */ 8240 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 8241 union dmub_rb_cmd **cmd, 8242 uint32_t rptr) 8243 { 8244 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 8245 8246 if (dmub_rb_empty(rb)) 8247 return false; 8248 8249 *cmd = (union dmub_rb_cmd *)rb_cmd; 8250 8251 return true; 8252 } 8253 8254 /** 8255 * @brief Returns the next unprocessed command in the outbox. 8256 * 8257 * @param rb DMUB outbox ringbuffer 8258 * @param cmd The outbox command to return 8259 * @return true if not empty 8260 * @return false otherwise 8261 */ 8262 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 8263 union dmub_rb_out_cmd *cmd) 8264 { 8265 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 8266 uint64_t *dst = (uint64_t *)cmd; 8267 uint8_t i; 8268 8269 if (dmub_rb_empty(rb)) 8270 return false; 8271 8272 // copying data 8273 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 8274 *dst++ = *src++; 8275 8276 return true; 8277 } 8278 8279 /** 8280 * @brief Removes the front entry in the ringbuffer. 8281 * 8282 * @param rb DMUB ringbuffer 8283 * @return true if the command was removed 8284 * @return false if there were no commands 8285 */ 8286 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 8287 { 8288 if (rb->capacity == 0) 8289 return false; 8290 8291 if (dmub_rb_empty(rb)) 8292 return false; 8293 8294 rb->rptr += DMUB_RB_CMD_SIZE; 8295 8296 if (rb->rptr >= rb->capacity) 8297 rb->rptr %= rb->capacity; 8298 8299 return true; 8300 } 8301 8302 /** 8303 * @brief Flushes commands in the ringbuffer to framebuffer memory. 8304 * 8305 * Avoids a race condition where DMCUB accesses memory while 8306 * there are still writes in flight to framebuffer. 8307 * 8308 * @param rb DMUB ringbuffer 8309 */ 8310 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 8311 { 8312 uint32_t rptr = rb->rptr; 8313 uint32_t wptr = rb->wrpt; 8314 8315 if (rb->capacity == 0) 8316 return; 8317 8318 while (rptr != wptr) { 8319 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 8320 uint8_t i; 8321 8322 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 8323 (void)READ_ONCE(*data++); 8324 8325 rptr += DMUB_RB_CMD_SIZE; 8326 if (rptr >= rb->capacity) 8327 rptr %= rb->capacity; 8328 } 8329 } 8330 8331 /** 8332 * @brief Initializes a DMCUB ringbuffer 8333 * 8334 * @param rb DMUB ringbuffer 8335 * @param init_params initial configuration for the ringbuffer 8336 */ 8337 static inline void dmub_rb_init(struct dmub_rb *rb, 8338 struct dmub_rb_init_params *init_params) 8339 { 8340 rb->base_address = init_params->base_address; 8341 rb->capacity = init_params->capacity; 8342 rb->rptr = init_params->read_ptr; 8343 rb->wrpt = init_params->write_ptr; 8344 } 8345 8346 /** 8347 * @brief Copies output data from in/out commands into the given command. 8348 * 8349 * @param rb DMUB ringbuffer 8350 * @param cmd Command to copy data into 8351 */ 8352 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 8353 union dmub_rb_cmd *cmd) 8354 { 8355 // Copy rb entry back into command 8356 uint8_t *rd_ptr = (rb->rptr == 0) ? 8357 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 8358 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 8359 8360 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 8361 } 8362 8363 //============================================================================== 8364 //</DMUB_RB>==================================================================== 8365 //============================================================================== 8366 #endif /* _DMUB_CMD_H_ */ 8367