1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic udelay 165 */ 166 #ifndef dmub_udelay 167 #define dmub_udelay(microseconds) udelay(microseconds) 168 #endif 169 170 #pragma pack(push, 1) 171 #define ABM_NUM_OF_ACE_SEGMENTS 5 172 173 union abm_flags { 174 struct { 175 /** 176 * @abm_enabled: Indicates if ABM is enabled. 177 */ 178 unsigned int abm_enabled : 1; 179 180 /** 181 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 182 */ 183 unsigned int disable_abm_requested : 1; 184 185 /** 186 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 187 */ 188 unsigned int disable_abm_immediately : 1; 189 190 /** 191 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 192 * to be disabled immediately and keep gain. 193 */ 194 unsigned int disable_abm_immediate_keep_gain : 1; 195 196 /** 197 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 198 */ 199 unsigned int fractional_pwm : 1; 200 201 /** 202 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 203 * of user backlight level. 204 */ 205 unsigned int abm_gradual_bl_change : 1; 206 207 /** 208 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 209 */ 210 unsigned int abm_new_frame : 1; 211 212 /** 213 * @vb_scaling_enabled: Indicates variBright Scaling Enable 214 */ 215 unsigned int vb_scaling_enabled : 1; 216 } bitfields; 217 218 unsigned int u32All; 219 }; 220 221 struct abm_save_restore { 222 /** 223 * @flags: Misc. ABM flags. 224 */ 225 union abm_flags flags; 226 227 /** 228 * @pause: true: pause ABM and get state 229 * false: unpause ABM after setting state 230 */ 231 uint32_t pause; 232 233 /** 234 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 235 */ 236 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 237 238 /** 239 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 240 */ 241 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 242 243 /** 244 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 245 */ 246 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 247 248 249 /** 250 * @knee_threshold: Current x-position of ACE knee (u0.16). 251 */ 252 uint32_t knee_threshold; 253 /** 254 * @current_gain: Current backlight reduction (u16.16). 255 */ 256 uint32_t current_gain; 257 /** 258 * @curr_bl_level: Current actual backlight level converging to target backlight level. 259 */ 260 uint16_t curr_bl_level; 261 262 /** 263 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 264 */ 265 uint16_t curr_user_bl_level; 266 267 }; 268 269 /** 270 * union dmub_addr - DMUB physical/virtual 64-bit address. 271 */ 272 union dmub_addr { 273 struct { 274 uint32_t low_part; /**< Lower 32 bits */ 275 uint32_t high_part; /**< Upper 32 bits */ 276 } u; /*<< Low/high bit access */ 277 uint64_t quad_part; /*<< 64 bit address */ 278 }; 279 #pragma pack(pop) 280 281 /** 282 * Dirty rect definition. 283 */ 284 struct dmub_rect { 285 /** 286 * Dirty rect x offset. 287 */ 288 uint32_t x; 289 290 /** 291 * Dirty rect y offset. 292 */ 293 uint32_t y; 294 295 /** 296 * Dirty rect width. 297 */ 298 uint32_t width; 299 300 /** 301 * Dirty rect height. 302 */ 303 uint32_t height; 304 }; 305 306 /** 307 * Flags that can be set by driver to change some PSR behaviour. 308 */ 309 union dmub_psr_debug_flags { 310 /** 311 * Debug flags. 312 */ 313 struct { 314 /** 315 * Enable visual confirm in FW. 316 */ 317 uint32_t visual_confirm : 1; 318 319 /** 320 * Force all selective updates to bw full frame updates. 321 */ 322 uint32_t force_full_frame_update : 1; 323 324 /** 325 * Use HW Lock Mgr object to do HW locking in FW. 326 */ 327 uint32_t use_hw_lock_mgr : 1; 328 329 /** 330 * Use TPS3 signal when restore main link. 331 */ 332 uint32_t force_wakeup_by_tps3 : 1; 333 334 /** 335 * Back to back flip, therefore cannot power down PHY 336 */ 337 uint32_t back_to_back_flip : 1; 338 339 /** 340 * Enable visual confirm for IPS 341 */ 342 uint32_t enable_ips_visual_confirm : 1; 343 } bitfields; 344 345 /** 346 * Union for debug flags. 347 */ 348 uint32_t u32All; 349 }; 350 351 /** 352 * Flags that can be set by driver to change some Replay behaviour. 353 */ 354 union replay_debug_flags { 355 struct { 356 /** 357 * 0x1 (bit 0) 358 * Enable visual confirm in FW. 359 */ 360 uint32_t visual_confirm : 1; 361 362 /** 363 * 0x2 (bit 1) 364 * @skip_crc: Set if need to skip CRC. 365 */ 366 uint32_t skip_crc : 1; 367 368 /** 369 * 0x4 (bit 2) 370 * @force_link_power_on: Force disable ALPM control 371 */ 372 uint32_t force_link_power_on : 1; 373 374 /** 375 * 0x8 (bit 3) 376 * @force_phy_power_on: Force phy power on 377 */ 378 uint32_t force_phy_power_on : 1; 379 380 /** 381 * 0x10 (bit 4) 382 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 383 */ 384 uint32_t timing_resync_disabled : 1; 385 386 /** 387 * 0x20 (bit 5) 388 * @skip_crtc_disabled: CRTC disable skipped 389 */ 390 uint32_t skip_crtc_disabled : 1; 391 392 /** 393 * 0x40 (bit 6) 394 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 395 */ 396 uint32_t force_defer_one_frame_update : 1; 397 398 /** 399 * 0x80 (bit 7) 400 * @disable_delay_alpm_on: Force disable delay alpm on 401 */ 402 uint32_t disable_delay_alpm_on : 1; 403 404 /** 405 * 0x100 (bit 8) 406 * @disable_desync_error_check: Force disable desync error check 407 */ 408 uint32_t disable_desync_error_check : 1; 409 410 /** 411 * 0x200 (bit 9) 412 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 413 */ 414 uint32_t force_self_update_when_abm_non_steady : 1; 415 416 /** 417 * 0x400 (bit 10) 418 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 419 * If we enter IPS2, the Visual confirm bar will change to yellow 420 */ 421 uint32_t enable_ips_visual_confirm : 1; 422 423 /** 424 * 0x800 (bit 11) 425 * @enable_ips_residency_profiling: Enable IPS residency profiling 426 */ 427 uint32_t enable_ips_residency_profiling : 1; 428 429 uint32_t reserved : 20; 430 } bitfields; 431 432 uint32_t u32All; 433 }; 434 435 union replay_hw_flags { 436 struct { 437 /** 438 * @allow_alpm_fw_standby_mode: To indicate whether the 439 * ALPM FW standby mode is allowed 440 */ 441 uint32_t allow_alpm_fw_standby_mode : 1; 442 443 /* 444 * @dsc_enable_status: DSC enable status in driver 445 */ 446 uint32_t dsc_enable_status : 1; 447 448 /** 449 * @fec_enable_status: receive fec enable/disable status from driver 450 */ 451 uint32_t fec_enable_status : 1; 452 453 /* 454 * @smu_optimizations_en: SMU power optimization. 455 * Only when active display is Replay capable and display enters Replay. 456 * Trigger interrupt to SMU to powerup/down. 457 */ 458 uint32_t smu_optimizations_en : 1; 459 460 /** 461 * @phy_power_state: Indicates current phy power state 462 */ 463 uint32_t phy_power_state : 1; 464 465 /** 466 * @link_power_state: Indicates current link power state 467 */ 468 uint32_t link_power_state : 1; 469 /** 470 * Use TPS3 signal when restore main link. 471 */ 472 uint32_t force_wakeup_by_tps3 : 1; 473 } bitfields; 474 475 uint32_t u32All; 476 }; 477 478 /** 479 * DMUB feature capabilities. 480 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 481 */ 482 struct dmub_feature_caps { 483 /** 484 * Max PSR version supported by FW. 485 */ 486 uint8_t psr; 487 uint8_t fw_assisted_mclk_switch_ver; 488 uint8_t reserved[4]; 489 uint8_t subvp_psr_support; 490 uint8_t gecc_enable; 491 uint8_t replay_supported; 492 uint8_t replay_reserved[3]; 493 }; 494 495 struct dmub_visual_confirm_color { 496 /** 497 * Maximum 10 bits color value 498 */ 499 uint16_t color_r_cr; 500 uint16_t color_g_y; 501 uint16_t color_b_cb; 502 uint16_t panel_inst; 503 }; 504 505 //============================================================================== 506 //</DMUB_TYPES>================================================================= 507 //============================================================================== 508 //< DMUB_META>================================================================== 509 //============================================================================== 510 #pragma pack(push, 1) 511 512 /* Magic value for identifying dmub_fw_meta_info */ 513 #define DMUB_FW_META_MAGIC 0x444D5542 514 515 /* Offset from the end of the file to the dmub_fw_meta_info */ 516 #define DMUB_FW_META_OFFSET 0x24 517 518 /** 519 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 520 */ 521 union dmub_fw_meta_feature_bits { 522 struct { 523 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 524 uint32_t reserved : 31; 525 } bits; /**< status bits */ 526 uint32_t all; /**< 32-bit access to status bits */ 527 }; 528 529 /** 530 * struct dmub_fw_meta_info - metadata associated with fw binary 531 * 532 * NOTE: This should be considered a stable API. Fields should 533 * not be repurposed or reordered. New fields should be 534 * added instead to extend the structure. 535 * 536 * @magic_value: magic value identifying DMUB firmware meta info 537 * @fw_region_size: size of the firmware state region 538 * @trace_buffer_size: size of the tracebuffer region 539 * @fw_version: the firmware version information 540 * @dal_fw: 1 if the firmware is DAL 541 * @shared_state_size: size of the shared state region in bytes 542 * @shared_state_features: number of shared state features 543 */ 544 struct dmub_fw_meta_info { 545 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 546 uint32_t fw_region_size; /**< size of the firmware state region */ 547 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 548 uint32_t fw_version; /**< the firmware version information */ 549 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 550 uint8_t reserved[3]; /**< padding bits */ 551 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 552 uint16_t shared_state_features; /**< number of shared state features */ 553 uint16_t reserved2; /**< padding bytes */ 554 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 555 }; 556 557 /** 558 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 559 */ 560 union dmub_fw_meta { 561 struct dmub_fw_meta_info info; /**< metadata info */ 562 uint8_t reserved[64]; /**< padding bits */ 563 }; 564 565 #pragma pack(pop) 566 567 //============================================================================== 568 //< DMUB Trace Buffer>================================================================ 569 //============================================================================== 570 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 571 /** 572 * dmub_trace_code_t - firmware trace code, 32-bits 573 */ 574 typedef uint32_t dmub_trace_code_t; 575 576 /** 577 * struct dmcub_trace_buf_entry - Firmware trace entry 578 */ 579 struct dmcub_trace_buf_entry { 580 dmub_trace_code_t trace_code; /**< trace code for the event */ 581 uint32_t tick_count; /**< the tick count at time of trace */ 582 uint32_t param0; /**< trace defined parameter 0 */ 583 uint32_t param1; /**< trace defined parameter 1 */ 584 }; 585 #endif 586 587 //============================================================================== 588 //< DMUB_STATUS>================================================================ 589 //============================================================================== 590 591 /** 592 * DMCUB scratch registers can be used to determine firmware status. 593 * Current scratch register usage is as follows: 594 * 595 * SCRATCH0: FW Boot Status register 596 * SCRATCH5: LVTMA Status Register 597 * SCRATCH15: FW Boot Options register 598 */ 599 600 /** 601 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 602 */ 603 union dmub_fw_boot_status { 604 struct { 605 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 606 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 607 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 608 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 609 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 610 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 611 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 612 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 613 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 614 } bits; /**< status bits */ 615 uint32_t all; /**< 32-bit access to status bits */ 616 }; 617 618 /** 619 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 620 */ 621 enum dmub_fw_boot_status_bit { 622 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 623 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 624 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 625 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 626 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 627 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 628 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 629 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 630 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 631 }; 632 633 /* Register bit definition for SCRATCH5 */ 634 union dmub_lvtma_status { 635 struct { 636 uint32_t psp_ok : 1; 637 uint32_t edp_on : 1; 638 uint32_t reserved : 30; 639 } bits; 640 uint32_t all; 641 }; 642 643 enum dmub_lvtma_status_bit { 644 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 645 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 646 }; 647 648 enum dmub_ips_disable_type { 649 DMUB_IPS_ENABLE = 0, 650 DMUB_IPS_DISABLE_ALL = 1, 651 DMUB_IPS_DISABLE_IPS1 = 2, 652 DMUB_IPS_DISABLE_IPS2 = 3, 653 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 654 DMUB_IPS_DISABLE_DYNAMIC = 5, 655 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 656 }; 657 658 #define DMUB_IPS1_ALLOW_MASK 0x00000001 659 #define DMUB_IPS2_ALLOW_MASK 0x00000002 660 #define DMUB_IPS1_COMMIT_MASK 0x00000004 661 #define DMUB_IPS2_COMMIT_MASK 0x00000008 662 663 /** 664 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 665 */ 666 union dmub_fw_boot_options { 667 struct { 668 uint32_t pemu_env : 1; /**< 1 if PEMU */ 669 uint32_t fpga_env : 1; /**< 1 if FPGA */ 670 uint32_t optimized_init : 1; /**< 1 if optimized init */ 671 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 672 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 673 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 674 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 675 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 676 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 677 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 678 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 679 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 680 uint32_t power_optimization: 1; 681 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 682 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 683 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 684 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 685 uint32_t reserved0: 1; 686 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 687 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 688 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 689 uint32_t ips_disable: 3; /* options to disable ips support*/ 690 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 691 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 692 uint32_t reserved : 7; /**< reserved */ 693 } bits; /**< boot bits */ 694 uint32_t all; /**< 32-bit access to bits */ 695 }; 696 697 enum dmub_fw_boot_options_bit { 698 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 699 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 700 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 701 }; 702 703 //============================================================================== 704 //< DMUB_SHARED_STATE>========================================================== 705 //============================================================================== 706 707 /** 708 * Shared firmware state between driver and firmware for lockless communication 709 * in situations where the inbox/outbox may be unavailable. 710 * 711 * Each structure *must* be at most 256-bytes in size. The layout allocation is 712 * described below: 713 * 714 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 715 */ 716 717 /** 718 * enum dmub_shared_state_feature_id - List of shared state features. 719 */ 720 enum dmub_shared_state_feature_id { 721 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 722 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 723 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 724 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 725 }; 726 727 /** 728 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 729 */ 730 union dmub_shared_state_ips_fw_signals { 731 struct { 732 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 733 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 734 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 735 uint32_t detection_required : 1; /**< 1 if detection is required */ 736 uint32_t reserved_bits : 28; /**< Reversed */ 737 } bits; 738 uint32_t all; 739 }; 740 741 /** 742 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 743 */ 744 union dmub_shared_state_ips_driver_signals { 745 struct { 746 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 747 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 748 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 749 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 750 uint32_t reserved_bits : 28; /**< Reversed bits */ 751 } bits; 752 uint32_t all; 753 }; 754 755 /** 756 * IPS FW Version 757 */ 758 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 759 760 /** 761 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 762 */ 763 struct dmub_shared_state_ips_fw { 764 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 765 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 766 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 767 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 768 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 769 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 770 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 771 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 772 }; /* 248-bytes, fixed */ 773 774 /** 775 * IPS Driver Version 776 */ 777 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 778 779 /** 780 * struct dmub_shared_state_ips_driver - Driver state for IPS. 781 */ 782 struct dmub_shared_state_ips_driver { 783 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 784 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 785 }; /* 248-bytes, fixed */ 786 787 /** 788 * enum dmub_shared_state_feature_common - Generic payload. 789 */ 790 struct dmub_shared_state_feature_common { 791 uint32_t padding[62]; 792 }; /* 248-bytes, fixed */ 793 794 /** 795 * enum dmub_shared_state_feature_header - Feature description. 796 */ 797 struct dmub_shared_state_feature_header { 798 uint16_t id; /**< Feature ID */ 799 uint16_t version; /**< Feature version */ 800 uint32_t reserved; /**< Reserved bytes. */ 801 }; /* 8 bytes, fixed */ 802 803 /** 804 * struct dmub_shared_state_feature_block - Feature block. 805 */ 806 struct dmub_shared_state_feature_block { 807 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 808 union dmub_shared_feature_state_union { 809 struct dmub_shared_state_feature_common common; /**< Generic data */ 810 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 811 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 812 } data; /**< Shared state data. */ 813 }; /* 256-bytes, fixed */ 814 815 /** 816 * Shared state size in bytes. 817 */ 818 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 819 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 820 821 //============================================================================== 822 //</DMUB_STATUS>================================================================ 823 //============================================================================== 824 //< DMUB_VBIOS>================================================================= 825 //============================================================================== 826 827 /* 828 * enum dmub_cmd_vbios_type - VBIOS commands. 829 * 830 * Command IDs should be treated as stable ABI. 831 * Do not reuse or modify IDs. 832 */ 833 enum dmub_cmd_vbios_type { 834 /** 835 * Configures the DIG encoder. 836 */ 837 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 838 /** 839 * Controls the PHY. 840 */ 841 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 842 /** 843 * Sets the pixel clock/symbol clock. 844 */ 845 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 846 /** 847 * Enables or disables power gating. 848 */ 849 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 850 /** 851 * Controls embedded panels. 852 */ 853 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 854 /** 855 * Query DP alt status on a transmitter. 856 */ 857 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 858 /** 859 * Control PHY FSM 860 */ 861 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 862 /** 863 * Controls domain power gating 864 */ 865 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 866 }; 867 868 //============================================================================== 869 //</DMUB_VBIOS>================================================================= 870 //============================================================================== 871 //< DMUB_GPINT>================================================================= 872 //============================================================================== 873 874 /** 875 * The shifts and masks below may alternatively be used to format and read 876 * the command register bits. 877 */ 878 879 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 880 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 881 882 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 883 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 884 885 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 886 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 887 888 /** 889 * Command responses. 890 */ 891 892 /** 893 * Return response for DMUB_GPINT__STOP_FW command. 894 */ 895 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 896 897 /** 898 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 899 */ 900 union dmub_gpint_data_register { 901 struct { 902 uint32_t param : 16; /**< 16-bit parameter */ 903 uint32_t command_code : 12; /**< GPINT command */ 904 uint32_t status : 4; /**< Command status bit */ 905 } bits; /**< GPINT bit access */ 906 uint32_t all; /**< GPINT 32-bit access */ 907 }; 908 909 /* 910 * enum dmub_gpint_command - GPINT command to DMCUB FW 911 * 912 * Command IDs should be treated as stable ABI. 913 * Do not reuse or modify IDs. 914 */ 915 enum dmub_gpint_command { 916 /** 917 * Invalid command, ignored. 918 */ 919 DMUB_GPINT__INVALID_COMMAND = 0, 920 /** 921 * DESC: Queries the firmware version. 922 * RETURN: Firmware version. 923 */ 924 DMUB_GPINT__GET_FW_VERSION = 1, 925 /** 926 * DESC: Halts the firmware. 927 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 928 */ 929 DMUB_GPINT__STOP_FW = 2, 930 /** 931 * DESC: Get PSR state from FW. 932 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 933 */ 934 DMUB_GPINT__GET_PSR_STATE = 7, 935 /** 936 * DESC: Notifies DMCUB of the currently active streams. 937 * ARGS: Stream mask, 1 bit per active stream index. 938 */ 939 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 940 /** 941 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 942 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 943 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 944 * RETURN: PSR residency in milli-percent. 945 */ 946 DMUB_GPINT__PSR_RESIDENCY = 9, 947 948 /** 949 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 950 */ 951 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 952 953 /** 954 * DESC: Get REPLAY state from FW. 955 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 956 */ 957 DMUB_GPINT__GET_REPLAY_STATE = 13, 958 959 /** 960 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 961 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 962 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 963 * RETURN: REPLAY residency in milli-percent. 964 */ 965 DMUB_GPINT__REPLAY_RESIDENCY = 14, 966 967 /** 968 * DESC: Copy bounding box to the host. 969 * ARGS: Version of bounding box to copy 970 * RETURN: Result of copying bounding box 971 */ 972 DMUB_GPINT__BB_COPY = 96, 973 974 /** 975 * DESC: Updates the host addresses bit48~bit63 for bounding box. 976 * ARGS: The word3 for the 64 bit address 977 */ 978 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 979 980 /** 981 * DESC: Updates the host addresses bit32~bit47 for bounding box. 982 * ARGS: The word2 for the 64 bit address 983 */ 984 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 985 986 /** 987 * DESC: Updates the host addresses bit16~bit31 for bounding box. 988 * ARGS: The word1 for the 64 bit address 989 */ 990 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 991 992 /** 993 * DESC: Updates the host addresses bit0~bit15 for bounding box. 994 * ARGS: The word0 for the 64 bit address 995 */ 996 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 997 998 /** 999 * DESC: Updates the trace buffer lower 32-bit mask. 1000 * ARGS: The new mask 1001 * RETURN: Lower 32-bit mask. 1002 */ 1003 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1004 1005 /** 1006 * DESC: Updates the trace buffer mask bit0~bit15. 1007 * ARGS: The new mask 1008 * RETURN: Lower 32-bit mask. 1009 */ 1010 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1011 1012 /** 1013 * DESC: Updates the trace buffer mask bit16~bit31. 1014 * ARGS: The new mask 1015 * RETURN: Lower 32-bit mask. 1016 */ 1017 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1018 1019 /** 1020 * DESC: Updates the trace buffer mask bit32~bit47. 1021 * ARGS: The new mask 1022 * RETURN: Lower 32-bit mask. 1023 */ 1024 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1025 1026 /** 1027 * DESC: Updates the trace buffer mask bit48~bit63. 1028 * ARGS: The new mask 1029 * RETURN: Lower 32-bit mask. 1030 */ 1031 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1032 1033 /** 1034 * DESC: Read the trace buffer mask bi0~bit15. 1035 */ 1036 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1037 1038 /** 1039 * DESC: Read the trace buffer mask bit16~bit31. 1040 */ 1041 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1042 1043 /** 1044 * DESC: Read the trace buffer mask bi32~bit47. 1045 */ 1046 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1047 1048 /** 1049 * DESC: Updates the trace buffer mask bit32~bit63. 1050 */ 1051 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1052 1053 /** 1054 * DESC: Enable measurements for various task duration 1055 * ARGS: 0 - Disable measurement 1056 * 1 - Enable measurement 1057 */ 1058 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1059 }; 1060 1061 /** 1062 * INBOX0 generic command definition 1063 */ 1064 union dmub_inbox0_cmd_common { 1065 struct { 1066 uint32_t command_code: 8; /**< INBOX0 command code */ 1067 uint32_t param: 24; /**< 24-bit parameter */ 1068 } bits; 1069 uint32_t all; 1070 }; 1071 1072 /** 1073 * INBOX0 hw_lock command definition 1074 */ 1075 union dmub_inbox0_cmd_lock_hw { 1076 struct { 1077 uint32_t command_code: 8; 1078 1079 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1080 uint32_t hw_lock_client: 2; 1081 1082 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1083 uint32_t otg_inst: 3; 1084 uint32_t opp_inst: 3; 1085 uint32_t dig_inst: 3; 1086 1087 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1088 uint32_t lock_pipe: 1; 1089 uint32_t lock_cursor: 1; 1090 uint32_t lock_dig: 1; 1091 uint32_t triple_buffer_lock: 1; 1092 1093 uint32_t lock: 1; /**< Lock */ 1094 uint32_t should_release: 1; /**< Release */ 1095 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1096 } bits; 1097 uint32_t all; 1098 }; 1099 1100 union dmub_inbox0_data_register { 1101 union dmub_inbox0_cmd_common inbox0_cmd_common; 1102 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1103 }; 1104 1105 enum dmub_inbox0_command { 1106 /** 1107 * DESC: Invalid command, ignored. 1108 */ 1109 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1110 /** 1111 * DESC: Notification to acquire/release HW lock 1112 * ARGS: 1113 */ 1114 DMUB_INBOX0_CMD__HW_LOCK = 1, 1115 }; 1116 //============================================================================== 1117 //</DMUB_GPINT>================================================================= 1118 //============================================================================== 1119 //< DMUB_CMD>=================================================================== 1120 //============================================================================== 1121 1122 /** 1123 * Size in bytes of each DMUB command. 1124 */ 1125 #define DMUB_RB_CMD_SIZE 64 1126 1127 /** 1128 * Maximum number of items in the DMUB ringbuffer. 1129 */ 1130 #define DMUB_RB_MAX_ENTRY 128 1131 1132 /** 1133 * Ringbuffer size in bytes. 1134 */ 1135 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1136 1137 /** 1138 * REG_SET mask for reg offload. 1139 */ 1140 #define REG_SET_MASK 0xFFFF 1141 1142 /* 1143 * enum dmub_cmd_type - DMUB inbox command. 1144 * 1145 * Command IDs should be treated as stable ABI. 1146 * Do not reuse or modify IDs. 1147 */ 1148 enum dmub_cmd_type { 1149 /** 1150 * Invalid command. 1151 */ 1152 DMUB_CMD__NULL = 0, 1153 /** 1154 * Read modify write register sequence offload. 1155 */ 1156 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1157 /** 1158 * Field update register sequence offload. 1159 */ 1160 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1161 /** 1162 * Burst write sequence offload. 1163 */ 1164 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1165 /** 1166 * Reg wait sequence offload. 1167 */ 1168 DMUB_CMD__REG_REG_WAIT = 4, 1169 /** 1170 * Workaround to avoid HUBP underflow during NV12 playback. 1171 */ 1172 DMUB_CMD__PLAT_54186_WA = 5, 1173 /** 1174 * Command type used to query FW feature caps. 1175 */ 1176 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1177 /** 1178 * Command type used to get visual confirm color. 1179 */ 1180 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1181 /** 1182 * Command type used for all PSR commands. 1183 */ 1184 DMUB_CMD__PSR = 64, 1185 /** 1186 * Command type used for all MALL commands. 1187 */ 1188 DMUB_CMD__MALL = 65, 1189 /** 1190 * Command type used for all ABM commands. 1191 */ 1192 DMUB_CMD__ABM = 66, 1193 /** 1194 * Command type used to update dirty rects in FW. 1195 */ 1196 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1197 /** 1198 * Command type used to update cursor info in FW. 1199 */ 1200 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1201 /** 1202 * Command type used for HW locking in FW. 1203 */ 1204 DMUB_CMD__HW_LOCK = 69, 1205 /** 1206 * Command type used to access DP AUX. 1207 */ 1208 DMUB_CMD__DP_AUX_ACCESS = 70, 1209 /** 1210 * Command type used for OUTBOX1 notification enable 1211 */ 1212 DMUB_CMD__OUTBOX1_ENABLE = 71, 1213 1214 /** 1215 * Command type used for all idle optimization commands. 1216 */ 1217 DMUB_CMD__IDLE_OPT = 72, 1218 /** 1219 * Command type used for all clock manager commands. 1220 */ 1221 DMUB_CMD__CLK_MGR = 73, 1222 /** 1223 * Command type used for all panel control commands. 1224 */ 1225 DMUB_CMD__PANEL_CNTL = 74, 1226 1227 /** 1228 * Command type used for all CAB commands. 1229 */ 1230 DMUB_CMD__CAB_FOR_SS = 75, 1231 1232 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1233 1234 /** 1235 * Command type used for interfacing with DPIA. 1236 */ 1237 DMUB_CMD__DPIA = 77, 1238 /** 1239 * Command type used for EDID CEA parsing 1240 */ 1241 DMUB_CMD__EDID_CEA = 79, 1242 /** 1243 * Command type used for getting usbc cable ID 1244 */ 1245 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1246 /** 1247 * Command type used to query HPD state. 1248 */ 1249 DMUB_CMD__QUERY_HPD_STATE = 82, 1250 /** 1251 * Command type used for all VBIOS interface commands. 1252 */ 1253 /** 1254 * Command type used for all REPLAY commands. 1255 */ 1256 DMUB_CMD__REPLAY = 83, 1257 1258 /** 1259 * Command type used for all SECURE_DISPLAY commands. 1260 */ 1261 DMUB_CMD__SECURE_DISPLAY = 85, 1262 1263 /** 1264 * Command type used to set DPIA HPD interrupt state 1265 */ 1266 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1267 1268 /** 1269 * Command type used for all PSP commands. 1270 */ 1271 DMUB_CMD__PSP = 88, 1272 1273 DMUB_CMD__VBIOS = 128, 1274 }; 1275 1276 /** 1277 * enum dmub_out_cmd_type - DMUB outbox commands. 1278 */ 1279 enum dmub_out_cmd_type { 1280 /** 1281 * Invalid outbox command, ignored. 1282 */ 1283 DMUB_OUT_CMD__NULL = 0, 1284 /** 1285 * Command type used for DP AUX Reply data notification 1286 */ 1287 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1288 /** 1289 * Command type used for DP HPD event notification 1290 */ 1291 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1292 /** 1293 * Command type used for SET_CONFIG Reply notification 1294 */ 1295 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1296 /** 1297 * Command type used for USB4 DPIA notification 1298 */ 1299 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1300 /** 1301 * Command type used for HPD redetect notification 1302 */ 1303 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1304 }; 1305 1306 /* DMUB_CMD__DPIA command sub-types. */ 1307 enum dmub_cmd_dpia_type { 1308 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1309 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1310 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1311 }; 1312 1313 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1314 enum dmub_cmd_dpia_notification_type { 1315 DPIA_NOTIFY__BW_ALLOCATION = 0, 1316 }; 1317 1318 #pragma pack(push, 1) 1319 1320 /** 1321 * struct dmub_cmd_header - Common command header fields. 1322 */ 1323 struct dmub_cmd_header { 1324 unsigned int type : 8; /**< command type */ 1325 unsigned int sub_type : 8; /**< command sub type */ 1326 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1327 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1328 unsigned int reserved0 : 6; /**< reserved bits */ 1329 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1330 unsigned int reserved1 : 2; /**< reserved bits */ 1331 }; 1332 1333 /* 1334 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1335 * 1336 * 60 payload bytes can hold up to 5 sets of read modify writes, 1337 * each take 3 dwords. 1338 * 1339 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1340 * 1341 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1342 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1343 */ 1344 struct dmub_cmd_read_modify_write_sequence { 1345 uint32_t addr; /**< register address */ 1346 uint32_t modify_mask; /**< modify mask */ 1347 uint32_t modify_value; /**< modify value */ 1348 }; 1349 1350 /** 1351 * Maximum number of ops in read modify write sequence. 1352 */ 1353 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1354 1355 /** 1356 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1357 */ 1358 struct dmub_rb_cmd_read_modify_write { 1359 struct dmub_cmd_header header; /**< command header */ 1360 /** 1361 * Read modify write sequence. 1362 */ 1363 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1364 }; 1365 1366 /* 1367 * Update a register with specified masks and values sequeunce 1368 * 1369 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1370 * 1371 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1372 * 1373 * 1374 * USE CASE: 1375 * 1. auto-increment register where additional read would update pointer and produce wrong result 1376 * 2. toggle a bit without read in the middle 1377 */ 1378 1379 struct dmub_cmd_reg_field_update_sequence { 1380 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1381 uint32_t modify_value; /**< value to update with */ 1382 }; 1383 1384 /** 1385 * Maximum number of ops in field update sequence. 1386 */ 1387 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1388 1389 /** 1390 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1391 */ 1392 struct dmub_rb_cmd_reg_field_update_sequence { 1393 struct dmub_cmd_header header; /**< command header */ 1394 uint32_t addr; /**< register address */ 1395 /** 1396 * Field update sequence. 1397 */ 1398 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1399 }; 1400 1401 1402 /** 1403 * Maximum number of burst write values. 1404 */ 1405 #define DMUB_BURST_WRITE_VALUES__MAX 14 1406 1407 /* 1408 * struct dmub_rb_cmd_burst_write - Burst write 1409 * 1410 * support use case such as writing out LUTs. 1411 * 1412 * 60 payload bytes can hold up to 14 values to write to given address 1413 * 1414 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1415 */ 1416 struct dmub_rb_cmd_burst_write { 1417 struct dmub_cmd_header header; /**< command header */ 1418 uint32_t addr; /**< register start address */ 1419 /** 1420 * Burst write register values. 1421 */ 1422 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1423 }; 1424 1425 /** 1426 * struct dmub_rb_cmd_common - Common command header 1427 */ 1428 struct dmub_rb_cmd_common { 1429 struct dmub_cmd_header header; /**< command header */ 1430 /** 1431 * Padding to RB_CMD_SIZE 1432 */ 1433 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1434 }; 1435 1436 /** 1437 * struct dmub_cmd_reg_wait_data - Register wait data 1438 */ 1439 struct dmub_cmd_reg_wait_data { 1440 uint32_t addr; /**< Register address */ 1441 uint32_t mask; /**< Mask for register bits */ 1442 uint32_t condition_field_value; /**< Value to wait for */ 1443 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1444 }; 1445 1446 /** 1447 * struct dmub_rb_cmd_reg_wait - Register wait command 1448 */ 1449 struct dmub_rb_cmd_reg_wait { 1450 struct dmub_cmd_header header; /**< Command header */ 1451 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1452 }; 1453 1454 /** 1455 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1456 * 1457 * Reprograms surface parameters to avoid underflow. 1458 */ 1459 struct dmub_cmd_PLAT_54186_wa { 1460 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1461 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1462 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1463 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1464 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1465 struct { 1466 uint32_t hubp_inst : 4; /**< HUBP instance */ 1467 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1468 uint32_t immediate :1; /**< Immediate flip */ 1469 uint32_t vmid : 4; /**< VMID */ 1470 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1471 uint32_t reserved : 21; /**< Reserved */ 1472 } flip_params; /**< Pageflip parameters */ 1473 uint32_t reserved[9]; /**< Reserved bits */ 1474 }; 1475 1476 /** 1477 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1478 */ 1479 struct dmub_rb_cmd_PLAT_54186_wa { 1480 struct dmub_cmd_header header; /**< Command header */ 1481 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1482 }; 1483 1484 /** 1485 * enum dmub_cmd_mall_type - MALL commands 1486 */ 1487 enum dmub_cmd_mall_type { 1488 /** 1489 * Allows display refresh from MALL. 1490 */ 1491 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1492 /** 1493 * Disallows display refresh from MALL. 1494 */ 1495 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1496 /** 1497 * Cursor copy for MALL. 1498 */ 1499 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1500 /** 1501 * Controls DF requests. 1502 */ 1503 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1504 }; 1505 1506 /** 1507 * struct dmub_rb_cmd_mall - MALL command data. 1508 */ 1509 struct dmub_rb_cmd_mall { 1510 struct dmub_cmd_header header; /**< Common command header */ 1511 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1512 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1513 uint32_t tmr_delay; /**< Timer delay */ 1514 uint32_t tmr_scale; /**< Timer scale */ 1515 uint16_t cursor_width; /**< Cursor width in pixels */ 1516 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1517 uint16_t cursor_height; /**< Cursor height in pixels */ 1518 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1519 uint8_t debug_bits; /**< Debug bits */ 1520 1521 uint8_t reserved1; /**< Reserved bits */ 1522 uint8_t reserved2; /**< Reserved bits */ 1523 }; 1524 1525 /** 1526 * enum dmub_cmd_cab_type - CAB command data. 1527 */ 1528 enum dmub_cmd_cab_type { 1529 /** 1530 * No idle optimizations (i.e. no CAB) 1531 */ 1532 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1533 /** 1534 * No DCN requests for memory 1535 */ 1536 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1537 /** 1538 * Fit surfaces in CAB (i.e. CAB enable) 1539 */ 1540 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1541 /** 1542 * Do not fit surfaces in CAB (i.e. no CAB) 1543 */ 1544 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1545 }; 1546 1547 /** 1548 * struct dmub_rb_cmd_cab - CAB command data. 1549 */ 1550 struct dmub_rb_cmd_cab_for_ss { 1551 struct dmub_cmd_header header; 1552 uint8_t cab_alloc_ways; /* total number of ways */ 1553 uint8_t debug_bits; /* debug bits */ 1554 }; 1555 1556 /** 1557 * Enum for indicating which MCLK switch mode per pipe 1558 */ 1559 enum mclk_switch_mode { 1560 NONE = 0, 1561 FPO = 1, 1562 SUBVP = 2, 1563 VBLANK = 3, 1564 }; 1565 1566 /* Per pipe struct which stores the MCLK switch mode 1567 * data to be sent to DMUB. 1568 * Named "v2" for now -- once FPO and SUBVP are fully merged 1569 * the type name can be updated 1570 */ 1571 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1572 union { 1573 struct { 1574 uint32_t pix_clk_100hz; 1575 uint16_t main_vblank_start; 1576 uint16_t main_vblank_end; 1577 uint16_t mall_region_lines; 1578 uint16_t prefetch_lines; 1579 uint16_t prefetch_to_mall_start_lines; 1580 uint16_t processing_delay_lines; 1581 uint16_t htotal; // required to calculate line time for multi-display cases 1582 uint16_t vtotal; 1583 uint8_t main_pipe_index; 1584 uint8_t phantom_pipe_index; 1585 /* Since the microschedule is calculated in terms of OTG lines, 1586 * include any scaling factors to make sure when we get accurate 1587 * conversion when programming MALL_START_LINE (which is in terms 1588 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1589 * is 1/2 (numerator = 1, denominator = 2). 1590 */ 1591 uint8_t scale_factor_numerator; 1592 uint8_t scale_factor_denominator; 1593 uint8_t is_drr; 1594 uint8_t main_split_pipe_index; 1595 uint8_t phantom_split_pipe_index; 1596 } subvp_data; 1597 1598 struct { 1599 uint32_t pix_clk_100hz; 1600 uint16_t vblank_start; 1601 uint16_t vblank_end; 1602 uint16_t vstartup_start; 1603 uint16_t vtotal; 1604 uint16_t htotal; 1605 uint8_t vblank_pipe_index; 1606 uint8_t padding[1]; 1607 struct { 1608 uint8_t drr_in_use; 1609 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1610 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1611 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1612 uint8_t use_ramping; // Use ramping or not 1613 uint8_t drr_vblank_start_margin; 1614 } drr_info; // DRR considered as part of SubVP + VBLANK case 1615 } vblank_data; 1616 } pipe_config; 1617 1618 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1619 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1620 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1621 */ 1622 uint8_t mode; // enum mclk_switch_mode 1623 }; 1624 1625 /** 1626 * Config data for Sub-VP and FPO 1627 * Named "v2" for now -- once FPO and SUBVP are fully merged 1628 * the type name can be updated 1629 */ 1630 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1631 uint16_t watermark_a_cache; 1632 uint8_t vertical_int_margin_us; 1633 uint8_t pstate_allow_width_us; 1634 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1635 }; 1636 1637 /** 1638 * DMUB rb command definition for Sub-VP and FPO 1639 * Named "v2" for now -- once FPO and SUBVP are fully merged 1640 * the type name can be updated 1641 */ 1642 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1643 struct dmub_cmd_header header; 1644 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1645 }; 1646 1647 struct dmub_flip_addr_info { 1648 uint32_t surf_addr_lo; 1649 uint32_t surf_addr_c_lo; 1650 uint32_t meta_addr_lo; 1651 uint32_t meta_addr_c_lo; 1652 uint16_t surf_addr_hi; 1653 uint16_t surf_addr_c_hi; 1654 uint16_t meta_addr_hi; 1655 uint16_t meta_addr_c_hi; 1656 }; 1657 1658 struct dmub_fams2_flip_info { 1659 union { 1660 struct { 1661 uint8_t is_immediate: 1; 1662 } bits; 1663 uint8_t all; 1664 } config; 1665 uint8_t otg_inst; 1666 uint8_t pipe_mask; 1667 uint8_t pad; 1668 struct dmub_flip_addr_info addr_info; 1669 }; 1670 1671 struct dmub_rb_cmd_fams2_flip { 1672 struct dmub_cmd_header header; 1673 struct dmub_fams2_flip_info flip_info; 1674 }; 1675 1676 struct dmub_optc_state_v2 { 1677 uint32_t v_total_min; 1678 uint32_t v_total_max; 1679 uint32_t v_total_mid; 1680 uint32_t v_total_mid_frame_num; 1681 uint8_t program_manual_trigger; 1682 uint8_t tg_inst; 1683 uint8_t pad[2]; 1684 }; 1685 1686 struct dmub_optc_position { 1687 uint32_t vpos; 1688 uint32_t hpos; 1689 uint32_t frame; 1690 }; 1691 1692 struct dmub_rb_cmd_fams2_drr_update { 1693 struct dmub_cmd_header header; 1694 struct dmub_optc_state_v2 dmub_optc_state_req; 1695 }; 1696 1697 /* HW and FW global configuration data for FAMS2 */ 1698 /* FAMS2 types and structs */ 1699 enum fams2_stream_type { 1700 FAMS2_STREAM_TYPE_NONE = 0, 1701 FAMS2_STREAM_TYPE_VBLANK = 1, 1702 FAMS2_STREAM_TYPE_VACTIVE = 2, 1703 FAMS2_STREAM_TYPE_DRR = 3, 1704 FAMS2_STREAM_TYPE_SUBVP = 4, 1705 }; 1706 1707 /* dynamic stream state */ 1708 struct dmub_fams2_legacy_stream_dynamic_state { 1709 uint8_t force_allow_at_vblank; 1710 uint8_t pad[3]; 1711 }; 1712 1713 struct dmub_fams2_subvp_stream_dynamic_state { 1714 uint16_t viewport_start_hubp_vline; 1715 uint16_t viewport_height_hubp_vlines; 1716 uint16_t viewport_start_c_hubp_vline; 1717 uint16_t viewport_height_c_hubp_vlines; 1718 uint16_t phantom_viewport_height_hubp_vlines; 1719 uint16_t phantom_viewport_height_c_hubp_vlines; 1720 uint16_t microschedule_start_otg_vline; 1721 uint16_t mall_start_otg_vline; 1722 uint16_t mall_start_hubp_vline; 1723 uint16_t mall_start_c_hubp_vline; 1724 uint8_t force_allow_at_vblank_only; 1725 uint8_t pad[3]; 1726 }; 1727 1728 struct dmub_fams2_drr_stream_dynamic_state { 1729 uint16_t stretched_vtotal; 1730 uint8_t use_cur_vtotal; 1731 uint8_t pad; 1732 }; 1733 1734 struct dmub_fams2_stream_dynamic_state { 1735 uint64_t ref_tick; 1736 uint32_t cur_vtotal; 1737 uint16_t adjusted_allow_end_otg_vline; 1738 uint8_t pad[2]; 1739 struct dmub_optc_position ref_otg_pos; 1740 struct dmub_optc_position target_otg_pos; 1741 union { 1742 struct dmub_fams2_legacy_stream_dynamic_state legacy; 1743 struct dmub_fams2_subvp_stream_dynamic_state subvp; 1744 struct dmub_fams2_drr_stream_dynamic_state drr; 1745 } sub_state; 1746 }; 1747 1748 /* static stream state */ 1749 struct dmub_fams2_legacy_stream_static_state { 1750 uint8_t vactive_det_fill_delay_otg_vlines; 1751 uint8_t programming_delay_otg_vlines; 1752 }; 1753 1754 struct dmub_fams2_subvp_stream_static_state { 1755 uint16_t vratio_numerator; 1756 uint16_t vratio_denominator; 1757 uint16_t phantom_vtotal; 1758 uint16_t phantom_vactive; 1759 union { 1760 struct { 1761 uint8_t is_multi_planar : 1; 1762 uint8_t is_yuv420 : 1; 1763 } bits; 1764 uint8_t all; 1765 } config; 1766 uint8_t programming_delay_otg_vlines; 1767 uint8_t prefetch_to_mall_otg_vlines; 1768 uint8_t phantom_otg_inst; 1769 uint8_t phantom_pipe_mask; 1770 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1771 }; 1772 1773 struct dmub_fams2_drr_stream_static_state { 1774 uint16_t nom_stretched_vtotal; 1775 uint8_t programming_delay_otg_vlines; 1776 uint8_t only_stretch_if_required; 1777 uint8_t pad[2]; 1778 }; 1779 1780 struct dmub_fams2_stream_static_state { 1781 enum fams2_stream_type type; 1782 uint32_t otg_vline_time_ns; 1783 uint32_t otg_vline_time_ticks; 1784 uint16_t htotal; 1785 uint16_t vtotal; // nominal vtotal 1786 uint16_t vblank_start; 1787 uint16_t vblank_end; 1788 uint16_t max_vtotal; 1789 uint16_t allow_start_otg_vline; 1790 uint16_t allow_end_otg_vline; 1791 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 1792 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 1793 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 1794 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 1795 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 1796 union { 1797 struct { 1798 uint8_t is_drr: 1; // stream is DRR enabled 1799 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 1800 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 1801 } bits; 1802 uint8_t all; 1803 } config; 1804 uint8_t otg_inst; 1805 uint8_t pipe_mask; // pipe mask for the whole config 1806 uint8_t num_planes; 1807 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 1808 uint8_t pad[DMUB_MAX_PLANES % 4]; 1809 union { 1810 struct dmub_fams2_legacy_stream_static_state legacy; 1811 struct dmub_fams2_subvp_stream_static_state subvp; 1812 struct dmub_fams2_drr_stream_static_state drr; 1813 } sub_state; 1814 }; 1815 1816 /** 1817 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 1818 * p-state request to allow latency 1819 */ 1820 enum dmub_fams2_allow_delay_check_mode { 1821 /* No check for request to allow delay */ 1822 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 1823 /* Check for request to allow delay */ 1824 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 1825 /* Check for prepare to allow delay */ 1826 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 1827 }; 1828 1829 union dmub_fams2_global_feature_config { 1830 struct { 1831 uint32_t enable: 1; 1832 uint32_t enable_ppt_check: 1; 1833 uint32_t enable_stall_recovery: 1; 1834 uint32_t enable_debug: 1; 1835 uint32_t enable_offload_flip: 1; 1836 uint32_t enable_visual_confirm: 1; 1837 uint32_t allow_delay_check_mode: 2; 1838 uint32_t reserved: 24; 1839 } bits; 1840 uint32_t all; 1841 }; 1842 1843 struct dmub_cmd_fams2_global_config { 1844 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 1845 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 1846 uint32_t num_streams; 1847 union dmub_fams2_global_feature_config features; 1848 uint32_t recovery_timeout_us; 1849 uint32_t hwfq_flip_programming_delay_us; 1850 }; 1851 1852 union dmub_cmd_fams2_config { 1853 struct dmub_cmd_fams2_global_config global; 1854 struct dmub_fams2_stream_static_state stream; 1855 }; 1856 1857 /** 1858 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 1859 */ 1860 struct dmub_rb_cmd_fams2 { 1861 struct dmub_cmd_header header; 1862 union dmub_cmd_fams2_config config; 1863 }; 1864 1865 /** 1866 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1867 */ 1868 enum dmub_cmd_idle_opt_type { 1869 /** 1870 * DCN hardware restore. 1871 */ 1872 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1873 1874 /** 1875 * DCN hardware save. 1876 */ 1877 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1878 1879 /** 1880 * DCN hardware notify idle. 1881 */ 1882 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1883 }; 1884 1885 /** 1886 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1887 */ 1888 struct dmub_rb_cmd_idle_opt_dcn_restore { 1889 struct dmub_cmd_header header; /**< header */ 1890 }; 1891 1892 /** 1893 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1894 */ 1895 struct dmub_dcn_notify_idle_cntl_data { 1896 uint8_t driver_idle; 1897 uint8_t skip_otg_disable; 1898 uint8_t reserved[58]; 1899 }; 1900 1901 /** 1902 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1903 */ 1904 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1905 struct dmub_cmd_header header; /**< header */ 1906 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1907 }; 1908 1909 /** 1910 * struct dmub_clocks - Clock update notification. 1911 */ 1912 struct dmub_clocks { 1913 uint32_t dispclk_khz; /**< dispclk kHz */ 1914 uint32_t dppclk_khz; /**< dppclk kHz */ 1915 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1916 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1917 }; 1918 1919 /** 1920 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1921 */ 1922 enum dmub_cmd_clk_mgr_type { 1923 /** 1924 * Notify DMCUB of clock update. 1925 */ 1926 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1927 }; 1928 1929 /** 1930 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1931 */ 1932 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1933 struct dmub_cmd_header header; /**< header */ 1934 struct dmub_clocks clocks; /**< clock data */ 1935 }; 1936 1937 /** 1938 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1939 */ 1940 struct dmub_cmd_digx_encoder_control_data { 1941 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1942 }; 1943 1944 /** 1945 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1946 */ 1947 struct dmub_rb_cmd_digx_encoder_control { 1948 struct dmub_cmd_header header; /**< header */ 1949 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1950 }; 1951 1952 /** 1953 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1954 */ 1955 struct dmub_cmd_set_pixel_clock_data { 1956 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1957 }; 1958 1959 /** 1960 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1961 */ 1962 struct dmub_rb_cmd_set_pixel_clock { 1963 struct dmub_cmd_header header; /**< header */ 1964 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1965 }; 1966 1967 /** 1968 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1969 */ 1970 struct dmub_cmd_enable_disp_power_gating_data { 1971 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1972 }; 1973 1974 /** 1975 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1976 */ 1977 struct dmub_rb_cmd_enable_disp_power_gating { 1978 struct dmub_cmd_header header; /**< header */ 1979 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1980 }; 1981 1982 /** 1983 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1984 */ 1985 struct dmub_dig_transmitter_control_data_v1_7 { 1986 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1987 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1988 union { 1989 uint8_t digmode; /**< enum atom_encode_mode_def */ 1990 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1991 } mode_laneset; 1992 uint8_t lanenum; /**< Number of lanes */ 1993 union { 1994 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1995 } symclk_units; 1996 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1997 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1998 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1999 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2000 uint8_t reserved1; /**< For future use */ 2001 uint8_t reserved2[3]; /**< For future use */ 2002 uint32_t reserved3[11]; /**< For future use */ 2003 }; 2004 2005 /** 2006 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2007 */ 2008 union dmub_cmd_dig1_transmitter_control_data { 2009 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2010 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2011 }; 2012 2013 /** 2014 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2015 */ 2016 struct dmub_rb_cmd_dig1_transmitter_control { 2017 struct dmub_cmd_header header; /**< header */ 2018 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2019 }; 2020 2021 /** 2022 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2023 */ 2024 struct dmub_rb_cmd_domain_control_data { 2025 uint8_t inst : 6; /**< DOMAIN instance to control */ 2026 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2027 uint8_t reserved[3]; /**< Reserved for future use */ 2028 }; 2029 2030 /** 2031 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2032 */ 2033 struct dmub_rb_cmd_domain_control { 2034 struct dmub_cmd_header header; /**< header */ 2035 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2036 }; 2037 2038 /** 2039 * DPIA tunnel command parameters. 2040 */ 2041 struct dmub_cmd_dig_dpia_control_data { 2042 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2043 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2044 union { 2045 uint8_t digmode; /** enum atom_encode_mode_def */ 2046 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2047 } mode_laneset; 2048 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2049 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2050 uint8_t hpdsel; /** =0: HPD is not assigned */ 2051 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2052 uint8_t dpia_id; /** Index of DPIA */ 2053 uint8_t fec_rdy : 1; 2054 uint8_t reserved : 7; 2055 uint32_t reserved1; 2056 }; 2057 2058 /** 2059 * DMUB command for DPIA tunnel control. 2060 */ 2061 struct dmub_rb_cmd_dig1_dpia_control { 2062 struct dmub_cmd_header header; 2063 struct dmub_cmd_dig_dpia_control_data dpia_control; 2064 }; 2065 2066 /** 2067 * SET_CONFIG Command Payload 2068 */ 2069 struct set_config_cmd_payload { 2070 uint8_t msg_type; /* set config message type */ 2071 uint8_t msg_data; /* set config message data */ 2072 }; 2073 2074 /** 2075 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2076 */ 2077 struct dmub_cmd_set_config_control_data { 2078 struct set_config_cmd_payload cmd_pkt; 2079 uint8_t instance; /* DPIA instance */ 2080 uint8_t immed_status; /* Immediate status returned in case of error */ 2081 }; 2082 2083 /** 2084 * DMUB command structure for SET_CONFIG command. 2085 */ 2086 struct dmub_rb_cmd_set_config_access { 2087 struct dmub_cmd_header header; /* header */ 2088 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2089 }; 2090 2091 /** 2092 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2093 */ 2094 struct dmub_cmd_mst_alloc_slots_control_data { 2095 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2096 uint8_t instance; /* DPIA instance */ 2097 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2098 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2099 }; 2100 2101 /** 2102 * DMUB command structure for SET_ command. 2103 */ 2104 struct dmub_rb_cmd_set_mst_alloc_slots { 2105 struct dmub_cmd_header header; /* header */ 2106 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2107 }; 2108 2109 /** 2110 * DMUB command structure for DPIA HPD int enable control. 2111 */ 2112 struct dmub_rb_cmd_dpia_hpd_int_enable { 2113 struct dmub_cmd_header header; /* header */ 2114 uint32_t enable; /* dpia hpd interrupt enable */ 2115 }; 2116 2117 /** 2118 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2119 */ 2120 struct dmub_rb_cmd_dpphy_init { 2121 struct dmub_cmd_header header; /**< header */ 2122 uint8_t reserved[60]; /**< reserved bits */ 2123 }; 2124 2125 /** 2126 * enum dp_aux_request_action - DP AUX request command listing. 2127 * 2128 * 4 AUX request command bits are shifted to high nibble. 2129 */ 2130 enum dp_aux_request_action { 2131 /** I2C-over-AUX write request */ 2132 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2133 /** I2C-over-AUX read request */ 2134 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2135 /** I2C-over-AUX write status request */ 2136 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2137 /** I2C-over-AUX write request with MOT=1 */ 2138 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2139 /** I2C-over-AUX read request with MOT=1 */ 2140 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2141 /** I2C-over-AUX write status request with MOT=1 */ 2142 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2143 /** Native AUX write request */ 2144 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2145 /** Native AUX read request */ 2146 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2147 }; 2148 2149 /** 2150 * enum aux_return_code_type - DP AUX process return code listing. 2151 */ 2152 enum aux_return_code_type { 2153 /** AUX process succeeded */ 2154 AUX_RET_SUCCESS = 0, 2155 /** AUX process failed with unknown reason */ 2156 AUX_RET_ERROR_UNKNOWN, 2157 /** AUX process completed with invalid reply */ 2158 AUX_RET_ERROR_INVALID_REPLY, 2159 /** AUX process timed out */ 2160 AUX_RET_ERROR_TIMEOUT, 2161 /** HPD was low during AUX process */ 2162 AUX_RET_ERROR_HPD_DISCON, 2163 /** Failed to acquire AUX engine */ 2164 AUX_RET_ERROR_ENGINE_ACQUIRE, 2165 /** AUX request not supported */ 2166 AUX_RET_ERROR_INVALID_OPERATION, 2167 /** AUX process not available */ 2168 AUX_RET_ERROR_PROTOCOL_ERROR, 2169 }; 2170 2171 /** 2172 * enum aux_channel_type - DP AUX channel type listing. 2173 */ 2174 enum aux_channel_type { 2175 /** AUX thru Legacy DP AUX */ 2176 AUX_CHANNEL_LEGACY_DDC, 2177 /** AUX thru DPIA DP tunneling */ 2178 AUX_CHANNEL_DPIA 2179 }; 2180 2181 /** 2182 * struct aux_transaction_parameters - DP AUX request transaction data 2183 */ 2184 struct aux_transaction_parameters { 2185 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2186 uint8_t action; /**< enum dp_aux_request_action */ 2187 uint8_t length; /**< DP AUX request data length */ 2188 uint8_t reserved; /**< For future use */ 2189 uint32_t address; /**< DP AUX address */ 2190 uint8_t data[16]; /**< DP AUX write data */ 2191 }; 2192 2193 /** 2194 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2195 */ 2196 struct dmub_cmd_dp_aux_control_data { 2197 uint8_t instance; /**< AUX instance or DPIA instance */ 2198 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2199 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2200 uint8_t reserved0; /**< For future use */ 2201 uint16_t timeout; /**< timeout time in us */ 2202 uint16_t reserved1; /**< For future use */ 2203 enum aux_channel_type type; /**< enum aux_channel_type */ 2204 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2205 }; 2206 2207 /** 2208 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2209 */ 2210 struct dmub_rb_cmd_dp_aux_access { 2211 /** 2212 * Command header. 2213 */ 2214 struct dmub_cmd_header header; 2215 /** 2216 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2217 */ 2218 struct dmub_cmd_dp_aux_control_data aux_control; 2219 }; 2220 2221 /** 2222 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2223 */ 2224 struct dmub_rb_cmd_outbox1_enable { 2225 /** 2226 * Command header. 2227 */ 2228 struct dmub_cmd_header header; 2229 /** 2230 * enable: 0x0 -> disable outbox1 notification (default value) 2231 * 0x1 -> enable outbox1 notification 2232 */ 2233 uint32_t enable; 2234 }; 2235 2236 /* DP AUX Reply command - OutBox Cmd */ 2237 /** 2238 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2239 */ 2240 struct aux_reply_data { 2241 /** 2242 * Aux cmd 2243 */ 2244 uint8_t command; 2245 /** 2246 * Aux reply data length (max: 16 bytes) 2247 */ 2248 uint8_t length; 2249 /** 2250 * Alignment only 2251 */ 2252 uint8_t pad[2]; 2253 /** 2254 * Aux reply data 2255 */ 2256 uint8_t data[16]; 2257 }; 2258 2259 /** 2260 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2261 */ 2262 struct aux_reply_control_data { 2263 /** 2264 * Reserved for future use 2265 */ 2266 uint32_t handle; 2267 /** 2268 * Aux Instance 2269 */ 2270 uint8_t instance; 2271 /** 2272 * Aux transaction result: definition in enum aux_return_code_type 2273 */ 2274 uint8_t result; 2275 /** 2276 * Alignment only 2277 */ 2278 uint16_t pad; 2279 }; 2280 2281 /** 2282 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2283 */ 2284 struct dmub_rb_cmd_dp_aux_reply { 2285 /** 2286 * Command header. 2287 */ 2288 struct dmub_cmd_header header; 2289 /** 2290 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2291 */ 2292 struct aux_reply_control_data control; 2293 /** 2294 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2295 */ 2296 struct aux_reply_data reply_data; 2297 }; 2298 2299 /* DP HPD Notify command - OutBox Cmd */ 2300 /** 2301 * DP HPD Type 2302 */ 2303 enum dp_hpd_type { 2304 /** 2305 * Normal DP HPD 2306 */ 2307 DP_HPD = 0, 2308 /** 2309 * DP HPD short pulse 2310 */ 2311 DP_IRQ 2312 }; 2313 2314 /** 2315 * DP HPD Status 2316 */ 2317 enum dp_hpd_status { 2318 /** 2319 * DP_HPD status low 2320 */ 2321 DP_HPD_UNPLUG = 0, 2322 /** 2323 * DP_HPD status high 2324 */ 2325 DP_HPD_PLUG 2326 }; 2327 2328 /** 2329 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2330 */ 2331 struct dp_hpd_data { 2332 /** 2333 * DP HPD instance 2334 */ 2335 uint8_t instance; 2336 /** 2337 * HPD type 2338 */ 2339 uint8_t hpd_type; 2340 /** 2341 * HPD status: only for type: DP_HPD to indicate status 2342 */ 2343 uint8_t hpd_status; 2344 /** 2345 * Alignment only 2346 */ 2347 uint8_t pad; 2348 }; 2349 2350 /** 2351 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2352 */ 2353 struct dmub_rb_cmd_dp_hpd_notify { 2354 /** 2355 * Command header. 2356 */ 2357 struct dmub_cmd_header header; 2358 /** 2359 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2360 */ 2361 struct dp_hpd_data hpd_data; 2362 }; 2363 2364 /** 2365 * Definition of a SET_CONFIG reply from DPOA. 2366 */ 2367 enum set_config_status { 2368 SET_CONFIG_PENDING = 0, 2369 SET_CONFIG_ACK_RECEIVED, 2370 SET_CONFIG_RX_TIMEOUT, 2371 SET_CONFIG_UNKNOWN_ERROR, 2372 }; 2373 2374 /** 2375 * Definition of a set_config reply 2376 */ 2377 struct set_config_reply_control_data { 2378 uint8_t instance; /* DPIA Instance */ 2379 uint8_t status; /* Set Config reply */ 2380 uint16_t pad; /* Alignment */ 2381 }; 2382 2383 /** 2384 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2385 */ 2386 struct dmub_rb_cmd_dp_set_config_reply { 2387 struct dmub_cmd_header header; 2388 struct set_config_reply_control_data set_config_reply_control; 2389 }; 2390 2391 /** 2392 * Definition of a DPIA notification header 2393 */ 2394 struct dpia_notification_header { 2395 uint8_t instance; /**< DPIA Instance */ 2396 uint8_t reserved[3]; 2397 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2398 }; 2399 2400 /** 2401 * Definition of the common data struct of DPIA notification 2402 */ 2403 struct dpia_notification_common { 2404 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2405 - sizeof(struct dpia_notification_header)]; 2406 }; 2407 2408 /** 2409 * Definition of a DPIA notification data 2410 */ 2411 struct dpia_bw_allocation_notify_data { 2412 union { 2413 struct { 2414 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2415 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2416 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2417 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2418 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2419 uint16_t reserved: 11; /**< Reserved */ 2420 } bits; 2421 2422 uint16_t flags; 2423 }; 2424 2425 uint8_t cm_id; /**< CM ID */ 2426 uint8_t group_id; /**< Group ID */ 2427 uint8_t granularity; /**< BW Allocation Granularity */ 2428 uint8_t estimated_bw; /**< Estimated_BW */ 2429 uint8_t allocated_bw; /**< Allocated_BW */ 2430 uint8_t reserved; 2431 }; 2432 2433 /** 2434 * union dpia_notify_data_type - DPIA Notification in Outbox command 2435 */ 2436 union dpia_notification_data { 2437 /** 2438 * DPIA Notification for common data struct 2439 */ 2440 struct dpia_notification_common common_data; 2441 2442 /** 2443 * DPIA Notification for DP BW Allocation support 2444 */ 2445 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2446 }; 2447 2448 /** 2449 * Definition of a DPIA notification payload 2450 */ 2451 struct dpia_notification_payload { 2452 struct dpia_notification_header header; 2453 union dpia_notification_data data; /**< DPIA notification payload data */ 2454 }; 2455 2456 /** 2457 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2458 */ 2459 struct dmub_rb_cmd_dpia_notification { 2460 struct dmub_cmd_header header; /**< DPIA notification header */ 2461 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2462 }; 2463 2464 /** 2465 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2466 */ 2467 struct dmub_cmd_hpd_state_query_data { 2468 uint8_t instance; /**< HPD instance or DPIA instance */ 2469 uint8_t result; /**< For returning HPD state */ 2470 uint16_t pad; /** < Alignment */ 2471 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2472 enum aux_return_code_type status; /**< for returning the status of command */ 2473 }; 2474 2475 /** 2476 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2477 */ 2478 struct dmub_rb_cmd_query_hpd_state { 2479 /** 2480 * Command header. 2481 */ 2482 struct dmub_cmd_header header; 2483 /** 2484 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2485 */ 2486 struct dmub_cmd_hpd_state_query_data data; 2487 }; 2488 2489 /** 2490 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2491 */ 2492 struct dmub_rb_cmd_hpd_sense_notify_data { 2493 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2494 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2495 }; 2496 2497 /** 2498 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2499 */ 2500 struct dmub_rb_cmd_hpd_sense_notify { 2501 struct dmub_cmd_header header; /**< header */ 2502 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2503 }; 2504 2505 /* 2506 * Command IDs should be treated as stable ABI. 2507 * Do not reuse or modify IDs. 2508 */ 2509 2510 /** 2511 * PSR command sub-types. 2512 */ 2513 enum dmub_cmd_psr_type { 2514 /** 2515 * Set PSR version support. 2516 */ 2517 DMUB_CMD__PSR_SET_VERSION = 0, 2518 /** 2519 * Copy driver-calculated parameters to PSR state. 2520 */ 2521 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2522 /** 2523 * Enable PSR. 2524 */ 2525 DMUB_CMD__PSR_ENABLE = 2, 2526 2527 /** 2528 * Disable PSR. 2529 */ 2530 DMUB_CMD__PSR_DISABLE = 3, 2531 2532 /** 2533 * Set PSR level. 2534 * PSR level is a 16-bit value dicated by driver that 2535 * will enable/disable different functionality. 2536 */ 2537 DMUB_CMD__PSR_SET_LEVEL = 4, 2538 2539 /** 2540 * Forces PSR enabled until an explicit PSR disable call. 2541 */ 2542 DMUB_CMD__PSR_FORCE_STATIC = 5, 2543 /** 2544 * Set vtotal in psr active for FreeSync PSR. 2545 */ 2546 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2547 /** 2548 * Set PSR power option 2549 */ 2550 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2551 }; 2552 2553 /** 2554 * Different PSR residency modes. 2555 * Different modes change the definition of PSR residency. 2556 */ 2557 enum psr_residency_mode { 2558 PSR_RESIDENCY_MODE_PHY = 0, 2559 PSR_RESIDENCY_MODE_ALPM, 2560 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2561 /* Do not add below. */ 2562 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2563 }; 2564 2565 enum dmub_cmd_fams_type { 2566 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2567 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2568 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2569 /** 2570 * For SubVP set manual trigger in FW because it 2571 * triggers DRR_UPDATE_PENDING which SubVP relies 2572 * on (for any SubVP cases that use a DRR display) 2573 */ 2574 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2575 DMUB_CMD__FAMS2_CONFIG = 4, 2576 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2577 DMUB_CMD__FAMS2_FLIP = 6, 2578 }; 2579 2580 /** 2581 * PSR versions. 2582 */ 2583 enum psr_version { 2584 /** 2585 * PSR version 1. 2586 */ 2587 PSR_VERSION_1 = 0, 2588 /** 2589 * Freesync PSR SU. 2590 */ 2591 PSR_VERSION_SU_1 = 1, 2592 /** 2593 * PSR not supported. 2594 */ 2595 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2596 }; 2597 2598 /** 2599 * PHY Link rate for DP. 2600 */ 2601 enum phy_link_rate { 2602 /** 2603 * not supported. 2604 */ 2605 PHY_RATE_UNKNOWN = 0, 2606 /** 2607 * Rate_1 (RBR) - 1.62 Gbps/Lane 2608 */ 2609 PHY_RATE_162 = 1, 2610 /** 2611 * Rate_2 - 2.16 Gbps/Lane 2612 */ 2613 PHY_RATE_216 = 2, 2614 /** 2615 * Rate_3 - 2.43 Gbps/Lane 2616 */ 2617 PHY_RATE_243 = 3, 2618 /** 2619 * Rate_4 (HBR) - 2.70 Gbps/Lane 2620 */ 2621 PHY_RATE_270 = 4, 2622 /** 2623 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2624 */ 2625 PHY_RATE_324 = 5, 2626 /** 2627 * Rate_6 - 4.32 Gbps/Lane 2628 */ 2629 PHY_RATE_432 = 6, 2630 /** 2631 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2632 */ 2633 PHY_RATE_540 = 7, 2634 /** 2635 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2636 */ 2637 PHY_RATE_810 = 8, 2638 /** 2639 * UHBR10 - 10.0 Gbps/Lane 2640 */ 2641 PHY_RATE_1000 = 9, 2642 /** 2643 * UHBR13.5 - 13.5 Gbps/Lane 2644 */ 2645 PHY_RATE_1350 = 10, 2646 /** 2647 * UHBR10 - 20.0 Gbps/Lane 2648 */ 2649 PHY_RATE_2000 = 11, 2650 2651 PHY_RATE_675 = 12, 2652 /** 2653 * Rate 12 - 6.75 Gbps/Lane 2654 */ 2655 }; 2656 2657 /** 2658 * enum dmub_phy_fsm_state - PHY FSM states. 2659 * PHY FSM state to transit to during PSR enable/disable. 2660 */ 2661 enum dmub_phy_fsm_state { 2662 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2663 DMUB_PHY_FSM_RESET, 2664 DMUB_PHY_FSM_RESET_RELEASED, 2665 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2666 DMUB_PHY_FSM_INITIALIZED, 2667 DMUB_PHY_FSM_CALIBRATED, 2668 DMUB_PHY_FSM_CALIBRATED_LP, 2669 DMUB_PHY_FSM_CALIBRATED_PG, 2670 DMUB_PHY_FSM_POWER_DOWN, 2671 DMUB_PHY_FSM_PLL_EN, 2672 DMUB_PHY_FSM_TX_EN, 2673 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2674 DMUB_PHY_FSM_FAST_LP, 2675 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2676 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2677 DMUB_PHY_FSM_P2_PLL_OFF, 2678 DMUB_PHY_FSM_P2_PLL_ON, 2679 }; 2680 2681 /** 2682 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2683 */ 2684 struct dmub_cmd_psr_copy_settings_data { 2685 /** 2686 * Flags that can be set by driver to change some PSR behaviour. 2687 */ 2688 union dmub_psr_debug_flags debug; 2689 /** 2690 * 16-bit value dicated by driver that will enable/disable different functionality. 2691 */ 2692 uint16_t psr_level; 2693 /** 2694 * DPP HW instance. 2695 */ 2696 uint8_t dpp_inst; 2697 /** 2698 * MPCC HW instance. 2699 * Not used in dmub fw, 2700 * dmub fw will get active opp by reading odm registers. 2701 */ 2702 uint8_t mpcc_inst; 2703 /** 2704 * OPP HW instance. 2705 * Not used in dmub fw, 2706 * dmub fw will get active opp by reading odm registers. 2707 */ 2708 uint8_t opp_inst; 2709 /** 2710 * OTG HW instance. 2711 */ 2712 uint8_t otg_inst; 2713 /** 2714 * DIG FE HW instance. 2715 */ 2716 uint8_t digfe_inst; 2717 /** 2718 * DIG BE HW instance. 2719 */ 2720 uint8_t digbe_inst; 2721 /** 2722 * DP PHY HW instance. 2723 */ 2724 uint8_t dpphy_inst; 2725 /** 2726 * AUX HW instance. 2727 */ 2728 uint8_t aux_inst; 2729 /** 2730 * Determines if SMU optimzations are enabled/disabled. 2731 */ 2732 uint8_t smu_optimizations_en; 2733 /** 2734 * Unused. 2735 * TODO: Remove. 2736 */ 2737 uint8_t frame_delay; 2738 /** 2739 * If RFB setup time is greater than the total VBLANK time, 2740 * it is not possible for the sink to capture the video frame 2741 * in the same frame the SDP is sent. In this case, 2742 * the frame capture indication bit should be set and an extra 2743 * static frame should be transmitted to the sink. 2744 */ 2745 uint8_t frame_cap_ind; 2746 /** 2747 * Granularity of Y offset supported by sink. 2748 */ 2749 uint8_t su_y_granularity; 2750 /** 2751 * Indicates whether sink should start capturing 2752 * immediately following active scan line, 2753 * or starting with the 2nd active scan line. 2754 */ 2755 uint8_t line_capture_indication; 2756 /** 2757 * Multi-display optimizations are implemented on certain ASICs. 2758 */ 2759 uint8_t multi_disp_optimizations_en; 2760 /** 2761 * The last possible line SDP may be transmitted without violating 2762 * the RFB setup time or entering the active video frame. 2763 */ 2764 uint16_t init_sdp_deadline; 2765 /** 2766 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2767 */ 2768 uint8_t rate_control_caps ; 2769 /* 2770 * Force PSRSU always doing full frame update 2771 */ 2772 uint8_t force_ffu_mode; 2773 /** 2774 * Length of each horizontal line in us. 2775 */ 2776 uint32_t line_time_in_us; 2777 /** 2778 * FEC enable status in driver 2779 */ 2780 uint8_t fec_enable_status; 2781 /** 2782 * FEC re-enable delay when PSR exit. 2783 * unit is 100us, range form 0~255(0xFF). 2784 */ 2785 uint8_t fec_enable_delay_in100us; 2786 /** 2787 * PSR control version. 2788 */ 2789 uint8_t cmd_version; 2790 /** 2791 * Panel Instance. 2792 * Panel instance to identify which psr_state to use 2793 * Currently the support is only for 0 or 1 2794 */ 2795 uint8_t panel_inst; 2796 /* 2797 * DSC enable status in driver 2798 */ 2799 uint8_t dsc_enable_status; 2800 /* 2801 * Use FSM state for PSR power up/down 2802 */ 2803 uint8_t use_phy_fsm; 2804 /** 2805 * frame delay for frame re-lock 2806 */ 2807 uint8_t relock_delay_frame_cnt; 2808 /** 2809 * esd recovery indicate. 2810 */ 2811 uint8_t esd_recovery; 2812 /** 2813 * DSC Slice height. 2814 */ 2815 uint16_t dsc_slice_height; 2816 /** 2817 * Some panels request main link off before xth vertical line 2818 */ 2819 uint16_t poweroff_before_vertical_line; 2820 }; 2821 2822 /** 2823 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2824 */ 2825 struct dmub_rb_cmd_psr_copy_settings { 2826 /** 2827 * Command header. 2828 */ 2829 struct dmub_cmd_header header; 2830 /** 2831 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2832 */ 2833 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2834 }; 2835 2836 /** 2837 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2838 */ 2839 struct dmub_cmd_psr_set_level_data { 2840 /** 2841 * 16-bit value dicated by driver that will enable/disable different functionality. 2842 */ 2843 uint16_t psr_level; 2844 /** 2845 * PSR control version. 2846 */ 2847 uint8_t cmd_version; 2848 /** 2849 * Panel Instance. 2850 * Panel instance to identify which psr_state to use 2851 * Currently the support is only for 0 or 1 2852 */ 2853 uint8_t panel_inst; 2854 }; 2855 2856 /** 2857 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2858 */ 2859 struct dmub_rb_cmd_psr_set_level { 2860 /** 2861 * Command header. 2862 */ 2863 struct dmub_cmd_header header; 2864 /** 2865 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2866 */ 2867 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2868 }; 2869 2870 struct dmub_rb_cmd_psr_enable_data { 2871 /** 2872 * PSR control version. 2873 */ 2874 uint8_t cmd_version; 2875 /** 2876 * Panel Instance. 2877 * Panel instance to identify which psr_state to use 2878 * Currently the support is only for 0 or 1 2879 */ 2880 uint8_t panel_inst; 2881 /** 2882 * Phy state to enter. 2883 * Values to use are defined in dmub_phy_fsm_state 2884 */ 2885 uint8_t phy_fsm_state; 2886 /** 2887 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2888 * Set this using enum phy_link_rate. 2889 * This does not support HDMI/DP2 for now. 2890 */ 2891 uint8_t phy_rate; 2892 }; 2893 2894 /** 2895 * Definition of a DMUB_CMD__PSR_ENABLE command. 2896 * PSR enable/disable is controlled using the sub_type. 2897 */ 2898 struct dmub_rb_cmd_psr_enable { 2899 /** 2900 * Command header. 2901 */ 2902 struct dmub_cmd_header header; 2903 2904 struct dmub_rb_cmd_psr_enable_data data; 2905 }; 2906 2907 /** 2908 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2909 */ 2910 struct dmub_cmd_psr_set_version_data { 2911 /** 2912 * PSR version that FW should implement. 2913 */ 2914 enum psr_version version; 2915 /** 2916 * PSR control version. 2917 */ 2918 uint8_t cmd_version; 2919 /** 2920 * Panel Instance. 2921 * Panel instance to identify which psr_state to use 2922 * Currently the support is only for 0 or 1 2923 */ 2924 uint8_t panel_inst; 2925 /** 2926 * Explicit padding to 4 byte boundary. 2927 */ 2928 uint8_t pad[2]; 2929 }; 2930 2931 /** 2932 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2933 */ 2934 struct dmub_rb_cmd_psr_set_version { 2935 /** 2936 * Command header. 2937 */ 2938 struct dmub_cmd_header header; 2939 /** 2940 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2941 */ 2942 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2943 }; 2944 2945 struct dmub_cmd_psr_force_static_data { 2946 /** 2947 * PSR control version. 2948 */ 2949 uint8_t cmd_version; 2950 /** 2951 * Panel Instance. 2952 * Panel instance to identify which psr_state to use 2953 * Currently the support is only for 0 or 1 2954 */ 2955 uint8_t panel_inst; 2956 /** 2957 * Explicit padding to 4 byte boundary. 2958 */ 2959 uint8_t pad[2]; 2960 }; 2961 2962 /** 2963 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2964 */ 2965 struct dmub_rb_cmd_psr_force_static { 2966 /** 2967 * Command header. 2968 */ 2969 struct dmub_cmd_header header; 2970 /** 2971 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2972 */ 2973 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2974 }; 2975 2976 /** 2977 * PSR SU debug flags. 2978 */ 2979 union dmub_psr_su_debug_flags { 2980 /** 2981 * PSR SU debug flags. 2982 */ 2983 struct { 2984 /** 2985 * Update dirty rect in SW only. 2986 */ 2987 uint8_t update_dirty_rect_only : 1; 2988 /** 2989 * Reset the cursor/plane state before processing the call. 2990 */ 2991 uint8_t reset_state : 1; 2992 } bitfields; 2993 2994 /** 2995 * Union for debug flags. 2996 */ 2997 uint32_t u32All; 2998 }; 2999 3000 /** 3001 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3002 * This triggers a selective update for PSR SU. 3003 */ 3004 struct dmub_cmd_update_dirty_rect_data { 3005 /** 3006 * Dirty rects from OS. 3007 */ 3008 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3009 /** 3010 * PSR SU debug flags. 3011 */ 3012 union dmub_psr_su_debug_flags debug_flags; 3013 /** 3014 * OTG HW instance. 3015 */ 3016 uint8_t pipe_idx; 3017 /** 3018 * Number of dirty rects. 3019 */ 3020 uint8_t dirty_rect_count; 3021 /** 3022 * PSR control version. 3023 */ 3024 uint8_t cmd_version; 3025 /** 3026 * Panel Instance. 3027 * Panel instance to identify which psr_state to use 3028 * Currently the support is only for 0 or 1 3029 */ 3030 uint8_t panel_inst; 3031 }; 3032 3033 /** 3034 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3035 */ 3036 struct dmub_rb_cmd_update_dirty_rect { 3037 /** 3038 * Command header. 3039 */ 3040 struct dmub_cmd_header header; 3041 /** 3042 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3043 */ 3044 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3045 }; 3046 3047 /** 3048 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3049 */ 3050 union dmub_reg_cursor_control_cfg { 3051 struct { 3052 uint32_t cur_enable: 1; 3053 uint32_t reser0: 3; 3054 uint32_t cur_2x_magnify: 1; 3055 uint32_t reser1: 3; 3056 uint32_t mode: 3; 3057 uint32_t reser2: 5; 3058 uint32_t pitch: 2; 3059 uint32_t reser3: 6; 3060 uint32_t line_per_chunk: 5; 3061 uint32_t reser4: 3; 3062 } bits; 3063 uint32_t raw; 3064 }; 3065 struct dmub_cursor_position_cache_hubp { 3066 union dmub_reg_cursor_control_cfg cur_ctl; 3067 union dmub_reg_position_cfg { 3068 struct { 3069 uint32_t cur_x_pos: 16; 3070 uint32_t cur_y_pos: 16; 3071 } bits; 3072 uint32_t raw; 3073 } position; 3074 union dmub_reg_hot_spot_cfg { 3075 struct { 3076 uint32_t hot_x: 16; 3077 uint32_t hot_y: 16; 3078 } bits; 3079 uint32_t raw; 3080 } hot_spot; 3081 union dmub_reg_dst_offset_cfg { 3082 struct { 3083 uint32_t dst_x_offset: 13; 3084 uint32_t reserved: 19; 3085 } bits; 3086 uint32_t raw; 3087 } dst_offset; 3088 }; 3089 3090 union dmub_reg_cur0_control_cfg { 3091 struct { 3092 uint32_t cur0_enable: 1; 3093 uint32_t expansion_mode: 1; 3094 uint32_t reser0: 1; 3095 uint32_t cur0_rom_en: 1; 3096 uint32_t mode: 3; 3097 uint32_t reserved: 25; 3098 } bits; 3099 uint32_t raw; 3100 }; 3101 struct dmub_cursor_position_cache_dpp { 3102 union dmub_reg_cur0_control_cfg cur0_ctl; 3103 }; 3104 struct dmub_cursor_position_cfg { 3105 struct dmub_cursor_position_cache_hubp pHubp; 3106 struct dmub_cursor_position_cache_dpp pDpp; 3107 uint8_t pipe_idx; 3108 /* 3109 * Padding is required. To be 4 Bytes Aligned. 3110 */ 3111 uint8_t padding[3]; 3112 }; 3113 3114 struct dmub_cursor_attribute_cache_hubp { 3115 uint32_t SURFACE_ADDR_HIGH; 3116 uint32_t SURFACE_ADDR; 3117 union dmub_reg_cursor_control_cfg cur_ctl; 3118 union dmub_reg_cursor_size_cfg { 3119 struct { 3120 uint32_t width: 16; 3121 uint32_t height: 16; 3122 } bits; 3123 uint32_t raw; 3124 } size; 3125 union dmub_reg_cursor_settings_cfg { 3126 struct { 3127 uint32_t dst_y_offset: 8; 3128 uint32_t chunk_hdl_adjust: 2; 3129 uint32_t reserved: 22; 3130 } bits; 3131 uint32_t raw; 3132 } settings; 3133 }; 3134 struct dmub_cursor_attribute_cache_dpp { 3135 union dmub_reg_cur0_control_cfg cur0_ctl; 3136 }; 3137 struct dmub_cursor_attributes_cfg { 3138 struct dmub_cursor_attribute_cache_hubp aHubp; 3139 struct dmub_cursor_attribute_cache_dpp aDpp; 3140 }; 3141 3142 struct dmub_cmd_update_cursor_payload0 { 3143 /** 3144 * Cursor dirty rects. 3145 */ 3146 struct dmub_rect cursor_rect; 3147 /** 3148 * PSR SU debug flags. 3149 */ 3150 union dmub_psr_su_debug_flags debug_flags; 3151 /** 3152 * Cursor enable/disable. 3153 */ 3154 uint8_t enable; 3155 /** 3156 * OTG HW instance. 3157 */ 3158 uint8_t pipe_idx; 3159 /** 3160 * PSR control version. 3161 */ 3162 uint8_t cmd_version; 3163 /** 3164 * Panel Instance. 3165 * Panel instance to identify which psr_state to use 3166 * Currently the support is only for 0 or 1 3167 */ 3168 uint8_t panel_inst; 3169 /** 3170 * Cursor Position Register. 3171 * Registers contains Hubp & Dpp modules 3172 */ 3173 struct dmub_cursor_position_cfg position_cfg; 3174 }; 3175 3176 struct dmub_cmd_update_cursor_payload1 { 3177 struct dmub_cursor_attributes_cfg attribute_cfg; 3178 }; 3179 3180 union dmub_cmd_update_cursor_info_data { 3181 struct dmub_cmd_update_cursor_payload0 payload0; 3182 struct dmub_cmd_update_cursor_payload1 payload1; 3183 }; 3184 /** 3185 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3186 */ 3187 struct dmub_rb_cmd_update_cursor_info { 3188 /** 3189 * Command header. 3190 */ 3191 struct dmub_cmd_header header; 3192 /** 3193 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3194 */ 3195 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3196 }; 3197 3198 /** 3199 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3200 */ 3201 struct dmub_cmd_psr_set_vtotal_data { 3202 /** 3203 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3204 */ 3205 uint16_t psr_vtotal_idle; 3206 /** 3207 * PSR control version. 3208 */ 3209 uint8_t cmd_version; 3210 /** 3211 * Panel Instance. 3212 * Panel instance to identify which psr_state to use 3213 * Currently the support is only for 0 or 1 3214 */ 3215 uint8_t panel_inst; 3216 /* 3217 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3218 */ 3219 uint16_t psr_vtotal_su; 3220 /** 3221 * Explicit padding to 4 byte boundary. 3222 */ 3223 uint8_t pad2[2]; 3224 }; 3225 3226 /** 3227 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3228 */ 3229 struct dmub_rb_cmd_psr_set_vtotal { 3230 /** 3231 * Command header. 3232 */ 3233 struct dmub_cmd_header header; 3234 /** 3235 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3236 */ 3237 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3238 }; 3239 3240 /** 3241 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3242 */ 3243 struct dmub_cmd_psr_set_power_opt_data { 3244 /** 3245 * PSR control version. 3246 */ 3247 uint8_t cmd_version; 3248 /** 3249 * Panel Instance. 3250 * Panel instance to identify which psr_state to use 3251 * Currently the support is only for 0 or 1 3252 */ 3253 uint8_t panel_inst; 3254 /** 3255 * Explicit padding to 4 byte boundary. 3256 */ 3257 uint8_t pad[2]; 3258 /** 3259 * PSR power option 3260 */ 3261 uint32_t power_opt; 3262 }; 3263 3264 /** 3265 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3266 */ 3267 struct dmub_rb_cmd_psr_set_power_opt { 3268 /** 3269 * Command header. 3270 */ 3271 struct dmub_cmd_header header; 3272 /** 3273 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3274 */ 3275 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3276 }; 3277 3278 /** 3279 * Definition of Replay Residency GPINT command. 3280 * Bit[0] - Residency mode for Revision 0 3281 * Bit[1] - Enable/Disable state 3282 * Bit[2-3] - Revision number 3283 * Bit[4-7] - Residency mode for Revision 1 3284 * Bit[8] - Panel instance 3285 * Bit[9-15] - Reserved 3286 */ 3287 3288 enum pr_residency_mode { 3289 PR_RESIDENCY_MODE_PHY = 0x0, 3290 PR_RESIDENCY_MODE_ALPM, 3291 PR_RESIDENCY_MODE_IPS2, 3292 PR_RESIDENCY_MODE_FRAME_CNT, 3293 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3294 }; 3295 3296 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3297 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3298 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3299 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3300 3301 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3302 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3303 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3304 3305 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3306 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3307 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3308 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3309 3310 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3311 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3312 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3313 3314 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3315 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3316 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3317 3318 /** 3319 * Definition of a replay_state. 3320 */ 3321 enum replay_state { 3322 REPLAY_STATE_0 = 0x0, 3323 REPLAY_STATE_1 = 0x10, 3324 REPLAY_STATE_1A = 0x11, 3325 REPLAY_STATE_2 = 0x20, 3326 REPLAY_STATE_2A = 0x21, 3327 REPLAY_STATE_3 = 0x30, 3328 REPLAY_STATE_3INIT = 0x31, 3329 REPLAY_STATE_4 = 0x40, 3330 REPLAY_STATE_4A = 0x41, 3331 REPLAY_STATE_4B = 0x42, 3332 REPLAY_STATE_4C = 0x43, 3333 REPLAY_STATE_4D = 0x44, 3334 REPLAY_STATE_4E = 0x45, 3335 REPLAY_STATE_4B_LOCKED = 0x4A, 3336 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3337 REPLAY_STATE_5 = 0x50, 3338 REPLAY_STATE_5A = 0x51, 3339 REPLAY_STATE_5B = 0x52, 3340 REPLAY_STATE_5A_LOCKED = 0x5A, 3341 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3342 REPLAY_STATE_6 = 0x60, 3343 REPLAY_STATE_6A = 0x61, 3344 REPLAY_STATE_6B = 0x62, 3345 REPLAY_STATE_INVALID = 0xFF, 3346 }; 3347 3348 /** 3349 * Replay command sub-types. 3350 */ 3351 enum dmub_cmd_replay_type { 3352 /** 3353 * Copy driver-calculated parameters to REPLAY state. 3354 */ 3355 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3356 /** 3357 * Enable REPLAY. 3358 */ 3359 DMUB_CMD__REPLAY_ENABLE = 1, 3360 /** 3361 * Set Replay power option. 3362 */ 3363 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3364 /** 3365 * Set coasting vtotal. 3366 */ 3367 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3368 /** 3369 * Set power opt and coasting vtotal. 3370 */ 3371 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3372 /** 3373 * Set disabled iiming sync. 3374 */ 3375 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3376 /** 3377 * Set Residency Frameupdate Timer. 3378 */ 3379 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3380 /** 3381 * Set pseudo vtotal 3382 */ 3383 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3384 /** 3385 * Set adaptive sync sdp enabled 3386 */ 3387 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3388 /** 3389 * Set Replay General command. 3390 */ 3391 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3392 }; 3393 3394 /** 3395 * Replay general command sub-types. 3396 */ 3397 enum dmub_cmd_replay_general_subtype { 3398 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3399 /** 3400 * TODO: For backward compatible, allow new command only. 3401 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3402 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3403 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3404 */ 3405 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3406 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3407 }; 3408 3409 /** 3410 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3411 */ 3412 struct dmub_cmd_replay_copy_settings_data { 3413 /** 3414 * Flags that can be set by driver to change some replay behaviour. 3415 */ 3416 union replay_debug_flags debug; 3417 3418 /** 3419 * @flags: Flags used to determine feature functionality. 3420 */ 3421 union replay_hw_flags flags; 3422 3423 /** 3424 * DPP HW instance. 3425 */ 3426 uint8_t dpp_inst; 3427 /** 3428 * OTG HW instance. 3429 */ 3430 uint8_t otg_inst; 3431 /** 3432 * DIG FE HW instance. 3433 */ 3434 uint8_t digfe_inst; 3435 /** 3436 * DIG BE HW instance. 3437 */ 3438 uint8_t digbe_inst; 3439 /** 3440 * AUX HW instance. 3441 */ 3442 uint8_t aux_inst; 3443 /** 3444 * Panel Instance. 3445 * Panel isntance to identify which psr_state to use 3446 * Currently the support is only for 0 or 1 3447 */ 3448 uint8_t panel_inst; 3449 /** 3450 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3451 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3452 */ 3453 uint8_t pixel_deviation_per_line; 3454 /** 3455 * @max_deviation_line: The max number of deviation line that can keep the timing 3456 * synchronized between the Source and Sink during Replay normal sleep mode. 3457 */ 3458 uint8_t max_deviation_line; 3459 /** 3460 * Length of each horizontal line in ns. 3461 */ 3462 uint32_t line_time_in_ns; 3463 /** 3464 * PHY instance. 3465 */ 3466 uint8_t dpphy_inst; 3467 /** 3468 * Determines if SMU optimzations are enabled/disabled. 3469 */ 3470 uint8_t smu_optimizations_en; 3471 /** 3472 * Determines if timing sync are enabled/disabled. 3473 */ 3474 uint8_t replay_timing_sync_supported; 3475 /* 3476 * Use FSM state for Replay power up/down 3477 */ 3478 uint8_t use_phy_fsm; 3479 }; 3480 3481 /** 3482 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3483 */ 3484 struct dmub_rb_cmd_replay_copy_settings { 3485 /** 3486 * Command header. 3487 */ 3488 struct dmub_cmd_header header; 3489 /** 3490 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3491 */ 3492 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3493 }; 3494 3495 /** 3496 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3497 */ 3498 enum replay_enable { 3499 /** 3500 * Disable REPLAY. 3501 */ 3502 REPLAY_DISABLE = 0, 3503 /** 3504 * Enable REPLAY. 3505 */ 3506 REPLAY_ENABLE = 1, 3507 }; 3508 3509 /** 3510 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3511 */ 3512 struct dmub_rb_cmd_replay_enable_data { 3513 /** 3514 * Replay enable or disable. 3515 */ 3516 uint8_t enable; 3517 /** 3518 * Panel Instance. 3519 * Panel isntance to identify which replay_state to use 3520 * Currently the support is only for 0 or 1 3521 */ 3522 uint8_t panel_inst; 3523 /** 3524 * Phy state to enter. 3525 * Values to use are defined in dmub_phy_fsm_state 3526 */ 3527 uint8_t phy_fsm_state; 3528 /** 3529 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3530 * Set this using enum phy_link_rate. 3531 * This does not support HDMI/DP2 for now. 3532 */ 3533 uint8_t phy_rate; 3534 }; 3535 3536 /** 3537 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3538 * Replay enable/disable is controlled using action in data. 3539 */ 3540 struct dmub_rb_cmd_replay_enable { 3541 /** 3542 * Command header. 3543 */ 3544 struct dmub_cmd_header header; 3545 3546 struct dmub_rb_cmd_replay_enable_data data; 3547 }; 3548 3549 /** 3550 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3551 */ 3552 struct dmub_cmd_replay_set_power_opt_data { 3553 /** 3554 * Panel Instance. 3555 * Panel isntance to identify which replay_state to use 3556 * Currently the support is only for 0 or 1 3557 */ 3558 uint8_t panel_inst; 3559 /** 3560 * Explicit padding to 4 byte boundary. 3561 */ 3562 uint8_t pad[3]; 3563 /** 3564 * REPLAY power option 3565 */ 3566 uint32_t power_opt; 3567 }; 3568 3569 /** 3570 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3571 */ 3572 struct dmub_cmd_replay_set_timing_sync_data { 3573 /** 3574 * Panel Instance. 3575 * Panel isntance to identify which replay_state to use 3576 * Currently the support is only for 0 or 1 3577 */ 3578 uint8_t panel_inst; 3579 /** 3580 * REPLAY set_timing_sync 3581 */ 3582 uint8_t timing_sync_supported; 3583 /** 3584 * Explicit padding to 4 byte boundary. 3585 */ 3586 uint8_t pad[2]; 3587 }; 3588 3589 /** 3590 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3591 */ 3592 struct dmub_cmd_replay_set_pseudo_vtotal { 3593 /** 3594 * Panel Instance. 3595 * Panel isntance to identify which replay_state to use 3596 * Currently the support is only for 0 or 1 3597 */ 3598 uint8_t panel_inst; 3599 /** 3600 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3601 */ 3602 uint16_t vtotal; 3603 /** 3604 * Explicit padding to 4 byte boundary. 3605 */ 3606 uint8_t pad; 3607 }; 3608 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3609 /** 3610 * Panel Instance. 3611 * Panel isntance to identify which replay_state to use 3612 * Currently the support is only for 0 or 1 3613 */ 3614 uint8_t panel_inst; 3615 /** 3616 * enabled: set adaptive sync sdp enabled 3617 */ 3618 uint8_t force_disabled; 3619 3620 uint8_t pad[2]; 3621 }; 3622 struct dmub_cmd_replay_set_general_cmd_data { 3623 /** 3624 * Panel Instance. 3625 * Panel isntance to identify which replay_state to use 3626 * Currently the support is only for 0 or 1 3627 */ 3628 uint8_t panel_inst; 3629 /** 3630 * subtype: replay general cmd sub type 3631 */ 3632 uint8_t subtype; 3633 3634 uint8_t pad[2]; 3635 /** 3636 * config data with param1 and param2 3637 */ 3638 uint32_t param1; 3639 3640 uint32_t param2; 3641 }; 3642 3643 /** 3644 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3645 */ 3646 struct dmub_rb_cmd_replay_set_power_opt { 3647 /** 3648 * Command header. 3649 */ 3650 struct dmub_cmd_header header; 3651 /** 3652 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3653 */ 3654 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3655 }; 3656 3657 /** 3658 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3659 */ 3660 struct dmub_cmd_replay_set_coasting_vtotal_data { 3661 /** 3662 * 16-bit value dicated by driver that indicates the coasting vtotal. 3663 */ 3664 uint16_t coasting_vtotal; 3665 /** 3666 * REPLAY control version. 3667 */ 3668 uint8_t cmd_version; 3669 /** 3670 * Panel Instance. 3671 * Panel isntance to identify which replay_state to use 3672 * Currently the support is only for 0 or 1 3673 */ 3674 uint8_t panel_inst; 3675 /** 3676 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3677 */ 3678 uint16_t coasting_vtotal_high; 3679 /** 3680 * Explicit padding to 4 byte boundary. 3681 */ 3682 uint8_t pad[2]; 3683 }; 3684 3685 /** 3686 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3687 */ 3688 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3689 /** 3690 * Command header. 3691 */ 3692 struct dmub_cmd_header header; 3693 /** 3694 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3695 */ 3696 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3697 }; 3698 3699 /** 3700 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3701 */ 3702 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3703 /** 3704 * Command header. 3705 */ 3706 struct dmub_cmd_header header; 3707 /** 3708 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3709 */ 3710 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3711 /** 3712 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3713 */ 3714 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3715 }; 3716 3717 /** 3718 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3719 */ 3720 struct dmub_rb_cmd_replay_set_timing_sync { 3721 /** 3722 * Command header. 3723 */ 3724 struct dmub_cmd_header header; 3725 /** 3726 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3727 */ 3728 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3729 }; 3730 3731 /** 3732 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3733 */ 3734 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3735 /** 3736 * Command header. 3737 */ 3738 struct dmub_cmd_header header; 3739 /** 3740 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3741 */ 3742 struct dmub_cmd_replay_set_pseudo_vtotal data; 3743 }; 3744 3745 /** 3746 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3747 */ 3748 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3749 /** 3750 * Command header. 3751 */ 3752 struct dmub_cmd_header header; 3753 /** 3754 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3755 */ 3756 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3757 }; 3758 3759 /** 3760 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3761 */ 3762 struct dmub_rb_cmd_replay_set_general_cmd { 3763 /** 3764 * Command header. 3765 */ 3766 struct dmub_cmd_header header; 3767 /** 3768 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 3769 */ 3770 struct dmub_cmd_replay_set_general_cmd_data data; 3771 }; 3772 3773 /** 3774 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3775 */ 3776 struct dmub_cmd_replay_frameupdate_timer_data { 3777 /** 3778 * Panel Instance. 3779 * Panel isntance to identify which replay_state to use 3780 * Currently the support is only for 0 or 1 3781 */ 3782 uint8_t panel_inst; 3783 /** 3784 * Replay Frameupdate Timer Enable or not 3785 */ 3786 uint8_t enable; 3787 /** 3788 * REPLAY force reflash frame update number 3789 */ 3790 uint16_t frameupdate_count; 3791 }; 3792 /** 3793 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3794 */ 3795 struct dmub_rb_cmd_replay_set_frameupdate_timer { 3796 /** 3797 * Command header. 3798 */ 3799 struct dmub_cmd_header header; 3800 /** 3801 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3802 */ 3803 struct dmub_cmd_replay_frameupdate_timer_data data; 3804 }; 3805 3806 /** 3807 * Definition union of replay command set 3808 */ 3809 union dmub_replay_cmd_set { 3810 /** 3811 * Panel Instance. 3812 * Panel isntance to identify which replay_state to use 3813 * Currently the support is only for 0 or 1 3814 */ 3815 uint8_t panel_inst; 3816 /** 3817 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 3818 */ 3819 struct dmub_cmd_replay_set_timing_sync_data sync_data; 3820 /** 3821 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 3822 */ 3823 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 3824 /** 3825 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 3826 */ 3827 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 3828 /** 3829 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 3830 */ 3831 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 3832 /** 3833 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 3834 */ 3835 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 3836 }; 3837 3838 /** 3839 * Set of HW components that can be locked. 3840 * 3841 * Note: If updating with more HW components, fields 3842 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3843 */ 3844 union dmub_hw_lock_flags { 3845 /** 3846 * Set of HW components that can be locked. 3847 */ 3848 struct { 3849 /** 3850 * Lock/unlock OTG master update lock. 3851 */ 3852 uint8_t lock_pipe : 1; 3853 /** 3854 * Lock/unlock cursor. 3855 */ 3856 uint8_t lock_cursor : 1; 3857 /** 3858 * Lock/unlock global update lock. 3859 */ 3860 uint8_t lock_dig : 1; 3861 /** 3862 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3863 */ 3864 uint8_t triple_buffer_lock : 1; 3865 } bits; 3866 3867 /** 3868 * Union for HW Lock flags. 3869 */ 3870 uint8_t u8All; 3871 }; 3872 3873 /** 3874 * Instances of HW to be locked. 3875 * 3876 * Note: If updating with more HW components, fields 3877 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3878 */ 3879 struct dmub_hw_lock_inst_flags { 3880 /** 3881 * OTG HW instance for OTG master update lock. 3882 */ 3883 uint8_t otg_inst; 3884 /** 3885 * OPP instance for cursor lock. 3886 */ 3887 uint8_t opp_inst; 3888 /** 3889 * OTG HW instance for global update lock. 3890 * TODO: Remove, and re-use otg_inst. 3891 */ 3892 uint8_t dig_inst; 3893 /** 3894 * Explicit pad to 4 byte boundary. 3895 */ 3896 uint8_t pad; 3897 }; 3898 3899 /** 3900 * Clients that can acquire the HW Lock Manager. 3901 * 3902 * Note: If updating with more clients, fields in 3903 * dmub_inbox0_cmd_lock_hw must be updated to match. 3904 */ 3905 enum hw_lock_client { 3906 /** 3907 * Driver is the client of HW Lock Manager. 3908 */ 3909 HW_LOCK_CLIENT_DRIVER = 0, 3910 /** 3911 * PSR SU is the client of HW Lock Manager. 3912 */ 3913 HW_LOCK_CLIENT_PSR_SU = 1, 3914 HW_LOCK_CLIENT_SUBVP = 3, 3915 /** 3916 * Replay is the client of HW Lock Manager. 3917 */ 3918 HW_LOCK_CLIENT_REPLAY = 4, 3919 HW_LOCK_CLIENT_FAMS2 = 5, 3920 /** 3921 * Invalid client. 3922 */ 3923 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3924 }; 3925 3926 /** 3927 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3928 */ 3929 struct dmub_cmd_lock_hw_data { 3930 /** 3931 * Specifies the client accessing HW Lock Manager. 3932 */ 3933 enum hw_lock_client client; 3934 /** 3935 * HW instances to be locked. 3936 */ 3937 struct dmub_hw_lock_inst_flags inst_flags; 3938 /** 3939 * Which components to be locked. 3940 */ 3941 union dmub_hw_lock_flags hw_locks; 3942 /** 3943 * Specifies lock/unlock. 3944 */ 3945 uint8_t lock; 3946 /** 3947 * HW can be unlocked separately from releasing the HW Lock Mgr. 3948 * This flag is set if the client wishes to release the object. 3949 */ 3950 uint8_t should_release; 3951 /** 3952 * Explicit padding to 4 byte boundary. 3953 */ 3954 uint8_t pad; 3955 }; 3956 3957 /** 3958 * Definition of a DMUB_CMD__HW_LOCK command. 3959 * Command is used by driver and FW. 3960 */ 3961 struct dmub_rb_cmd_lock_hw { 3962 /** 3963 * Command header. 3964 */ 3965 struct dmub_cmd_header header; 3966 /** 3967 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3968 */ 3969 struct dmub_cmd_lock_hw_data lock_hw_data; 3970 }; 3971 3972 /** 3973 * ABM command sub-types. 3974 */ 3975 enum dmub_cmd_abm_type { 3976 /** 3977 * Initialize parameters for ABM algorithm. 3978 * Data is passed through an indirect buffer. 3979 */ 3980 DMUB_CMD__ABM_INIT_CONFIG = 0, 3981 /** 3982 * Set OTG and panel HW instance. 3983 */ 3984 DMUB_CMD__ABM_SET_PIPE = 1, 3985 /** 3986 * Set user requested backklight level. 3987 */ 3988 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3989 /** 3990 * Set ABM operating/aggression level. 3991 */ 3992 DMUB_CMD__ABM_SET_LEVEL = 3, 3993 /** 3994 * Set ambient light level. 3995 */ 3996 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 3997 /** 3998 * Enable/disable fractional duty cycle for backlight PWM. 3999 */ 4000 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4001 4002 /** 4003 * unregister vertical interrupt after steady state is reached 4004 */ 4005 DMUB_CMD__ABM_PAUSE = 6, 4006 4007 /** 4008 * Save and Restore ABM state. On save we save parameters, and 4009 * on restore we update state with passed in data. 4010 */ 4011 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4012 4013 /** 4014 * Query ABM caps. 4015 */ 4016 DMUB_CMD__ABM_QUERY_CAPS = 8, 4017 4018 /** 4019 * Set ABM Events 4020 */ 4021 DMUB_CMD__ABM_SET_EVENT = 9, 4022 4023 /** 4024 * Get the current ACE curve. 4025 */ 4026 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4027 }; 4028 4029 struct abm_ace_curve { 4030 /** 4031 * @offsets: ACE curve offsets. 4032 */ 4033 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4034 4035 /** 4036 * @thresholds: ACE curve thresholds. 4037 */ 4038 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4039 4040 /** 4041 * @slopes: ACE curve slopes. 4042 */ 4043 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4044 }; 4045 4046 struct fixed_pt_format { 4047 /** 4048 * @sign_bit: Indicates whether one bit is reserved for the sign. 4049 */ 4050 bool sign_bit; 4051 4052 /** 4053 * @num_int_bits: Number of bits used for integer part. 4054 */ 4055 uint8_t num_int_bits; 4056 4057 /** 4058 * @num_frac_bits: Number of bits used for fractional part. 4059 */ 4060 uint8_t num_frac_bits; 4061 4062 /** 4063 * @pad: Explicit padding to 4 byte boundary. 4064 */ 4065 uint8_t pad; 4066 }; 4067 4068 struct abm_caps { 4069 /** 4070 * @num_hg_bins: Number of histogram bins. 4071 */ 4072 uint8_t num_hg_bins; 4073 4074 /** 4075 * @num_ace_segments: Number of ACE curve segments. 4076 */ 4077 uint8_t num_ace_segments; 4078 4079 /** 4080 * @pad: Explicit padding to 4 byte boundary. 4081 */ 4082 uint8_t pad[2]; 4083 4084 /** 4085 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4086 */ 4087 struct fixed_pt_format ace_thresholds_format; 4088 4089 /** 4090 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4091 */ 4092 struct fixed_pt_format ace_offsets_format; 4093 4094 /** 4095 * @ace_slopes_format: Format of the ACE slopes. 4096 */ 4097 struct fixed_pt_format ace_slopes_format; 4098 }; 4099 4100 /** 4101 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4102 * Requirements: 4103 * - Padded explicitly to 32-bit boundary. 4104 * - Must ensure this structure matches the one on driver-side, 4105 * otherwise it won't be aligned. 4106 */ 4107 struct abm_config_table { 4108 /** 4109 * Gamma curve thresholds, used for crgb conversion. 4110 */ 4111 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4112 /** 4113 * Gamma curve offsets, used for crgb conversion. 4114 */ 4115 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4116 /** 4117 * Gamma curve slopes, used for crgb conversion. 4118 */ 4119 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4120 /** 4121 * Custom backlight curve thresholds. 4122 */ 4123 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4124 /** 4125 * Custom backlight curve offsets. 4126 */ 4127 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4128 /** 4129 * Ambient light thresholds. 4130 */ 4131 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4132 /** 4133 * Minimum programmable backlight. 4134 */ 4135 uint16_t min_abm_backlight; // 122B 4136 /** 4137 * Minimum reduction values. 4138 */ 4139 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4140 /** 4141 * Maximum reduction values. 4142 */ 4143 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4144 /** 4145 * Bright positive gain. 4146 */ 4147 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4148 /** 4149 * Dark negative gain. 4150 */ 4151 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4152 /** 4153 * Hybrid factor. 4154 */ 4155 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4156 /** 4157 * Contrast factor. 4158 */ 4159 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4160 /** 4161 * Deviation gain. 4162 */ 4163 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4164 /** 4165 * Minimum knee. 4166 */ 4167 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4168 /** 4169 * Maximum knee. 4170 */ 4171 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4172 /** 4173 * Unused. 4174 */ 4175 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4176 /** 4177 * Explicit padding to 4 byte boundary. 4178 */ 4179 uint8_t pad3[3]; // 229B 4180 /** 4181 * Backlight ramp reduction. 4182 */ 4183 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4184 /** 4185 * Backlight ramp start. 4186 */ 4187 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4188 }; 4189 4190 /** 4191 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4192 */ 4193 struct dmub_cmd_abm_set_pipe_data { 4194 /** 4195 * OTG HW instance. 4196 */ 4197 uint8_t otg_inst; 4198 4199 /** 4200 * Panel Control HW instance. 4201 */ 4202 uint8_t panel_inst; 4203 4204 /** 4205 * Controls how ABM will interpret a set pipe or set level command. 4206 */ 4207 uint8_t set_pipe_option; 4208 4209 /** 4210 * Unused. 4211 * TODO: Remove. 4212 */ 4213 uint8_t ramping_boundary; 4214 4215 /** 4216 * PwrSeq HW Instance. 4217 */ 4218 uint8_t pwrseq_inst; 4219 4220 /** 4221 * Explicit padding to 4 byte boundary. 4222 */ 4223 uint8_t pad[3]; 4224 }; 4225 4226 /** 4227 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4228 */ 4229 struct dmub_rb_cmd_abm_set_pipe { 4230 /** 4231 * Command header. 4232 */ 4233 struct dmub_cmd_header header; 4234 4235 /** 4236 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4237 */ 4238 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4239 }; 4240 4241 /** 4242 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4243 */ 4244 struct dmub_cmd_abm_set_backlight_data { 4245 /** 4246 * Number of frames to ramp to backlight user level. 4247 */ 4248 uint32_t frame_ramp; 4249 4250 /** 4251 * Requested backlight level from user. 4252 */ 4253 uint32_t backlight_user_level; 4254 4255 /** 4256 * ABM control version. 4257 */ 4258 uint8_t version; 4259 4260 /** 4261 * Panel Control HW instance mask. 4262 * Bit 0 is Panel Control HW instance 0. 4263 * Bit 1 is Panel Control HW instance 1. 4264 */ 4265 uint8_t panel_mask; 4266 4267 /** 4268 * Explicit padding to 4 byte boundary. 4269 */ 4270 uint8_t pad[2]; 4271 }; 4272 4273 /** 4274 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4275 */ 4276 struct dmub_rb_cmd_abm_set_backlight { 4277 /** 4278 * Command header. 4279 */ 4280 struct dmub_cmd_header header; 4281 4282 /** 4283 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4284 */ 4285 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4286 }; 4287 4288 /** 4289 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4290 */ 4291 struct dmub_cmd_abm_set_level_data { 4292 /** 4293 * Set current ABM operating/aggression level. 4294 */ 4295 uint32_t level; 4296 4297 /** 4298 * ABM control version. 4299 */ 4300 uint8_t version; 4301 4302 /** 4303 * Panel Control HW instance mask. 4304 * Bit 0 is Panel Control HW instance 0. 4305 * Bit 1 is Panel Control HW instance 1. 4306 */ 4307 uint8_t panel_mask; 4308 4309 /** 4310 * Explicit padding to 4 byte boundary. 4311 */ 4312 uint8_t pad[2]; 4313 }; 4314 4315 /** 4316 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4317 */ 4318 struct dmub_rb_cmd_abm_set_level { 4319 /** 4320 * Command header. 4321 */ 4322 struct dmub_cmd_header header; 4323 4324 /** 4325 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4326 */ 4327 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4328 }; 4329 4330 /** 4331 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4332 */ 4333 struct dmub_cmd_abm_set_ambient_level_data { 4334 /** 4335 * Ambient light sensor reading from OS. 4336 */ 4337 uint32_t ambient_lux; 4338 4339 /** 4340 * ABM control version. 4341 */ 4342 uint8_t version; 4343 4344 /** 4345 * Panel Control HW instance mask. 4346 * Bit 0 is Panel Control HW instance 0. 4347 * Bit 1 is Panel Control HW instance 1. 4348 */ 4349 uint8_t panel_mask; 4350 4351 /** 4352 * Explicit padding to 4 byte boundary. 4353 */ 4354 uint8_t pad[2]; 4355 }; 4356 4357 /** 4358 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4359 */ 4360 struct dmub_rb_cmd_abm_set_ambient_level { 4361 /** 4362 * Command header. 4363 */ 4364 struct dmub_cmd_header header; 4365 4366 /** 4367 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4368 */ 4369 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4370 }; 4371 4372 /** 4373 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4374 */ 4375 struct dmub_cmd_abm_set_pwm_frac_data { 4376 /** 4377 * Enable/disable fractional duty cycle for backlight PWM. 4378 * TODO: Convert to uint8_t. 4379 */ 4380 uint32_t fractional_pwm; 4381 4382 /** 4383 * ABM control version. 4384 */ 4385 uint8_t version; 4386 4387 /** 4388 * Panel Control HW instance mask. 4389 * Bit 0 is Panel Control HW instance 0. 4390 * Bit 1 is Panel Control HW instance 1. 4391 */ 4392 uint8_t panel_mask; 4393 4394 /** 4395 * Explicit padding to 4 byte boundary. 4396 */ 4397 uint8_t pad[2]; 4398 }; 4399 4400 /** 4401 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4402 */ 4403 struct dmub_rb_cmd_abm_set_pwm_frac { 4404 /** 4405 * Command header. 4406 */ 4407 struct dmub_cmd_header header; 4408 4409 /** 4410 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4411 */ 4412 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4413 }; 4414 4415 /** 4416 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4417 */ 4418 struct dmub_cmd_abm_init_config_data { 4419 /** 4420 * Location of indirect buffer used to pass init data to ABM. 4421 */ 4422 union dmub_addr src; 4423 4424 /** 4425 * Indirect buffer length. 4426 */ 4427 uint16_t bytes; 4428 4429 4430 /** 4431 * ABM control version. 4432 */ 4433 uint8_t version; 4434 4435 /** 4436 * Panel Control HW instance mask. 4437 * Bit 0 is Panel Control HW instance 0. 4438 * Bit 1 is Panel Control HW instance 1. 4439 */ 4440 uint8_t panel_mask; 4441 4442 /** 4443 * Explicit padding to 4 byte boundary. 4444 */ 4445 uint8_t pad[2]; 4446 }; 4447 4448 /** 4449 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4450 */ 4451 struct dmub_rb_cmd_abm_init_config { 4452 /** 4453 * Command header. 4454 */ 4455 struct dmub_cmd_header header; 4456 4457 /** 4458 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4459 */ 4460 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4461 }; 4462 4463 /** 4464 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4465 */ 4466 4467 struct dmub_cmd_abm_pause_data { 4468 4469 /** 4470 * Panel Control HW instance mask. 4471 * Bit 0 is Panel Control HW instance 0. 4472 * Bit 1 is Panel Control HW instance 1. 4473 */ 4474 uint8_t panel_mask; 4475 4476 /** 4477 * OTG hw instance 4478 */ 4479 uint8_t otg_inst; 4480 4481 /** 4482 * Enable or disable ABM pause 4483 */ 4484 uint8_t enable; 4485 4486 /** 4487 * Explicit padding to 4 byte boundary. 4488 */ 4489 uint8_t pad[1]; 4490 }; 4491 4492 /** 4493 * Definition of a DMUB_CMD__ABM_PAUSE command. 4494 */ 4495 struct dmub_rb_cmd_abm_pause { 4496 /** 4497 * Command header. 4498 */ 4499 struct dmub_cmd_header header; 4500 4501 /** 4502 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4503 */ 4504 struct dmub_cmd_abm_pause_data abm_pause_data; 4505 }; 4506 4507 /** 4508 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4509 */ 4510 struct dmub_cmd_abm_query_caps_in { 4511 /** 4512 * Panel instance. 4513 */ 4514 uint8_t panel_inst; 4515 4516 /** 4517 * Explicit padding to 4 byte boundary. 4518 */ 4519 uint8_t pad[3]; 4520 }; 4521 4522 /** 4523 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4524 */ 4525 struct dmub_cmd_abm_query_caps_out { 4526 /** 4527 * SW Algorithm caps. 4528 */ 4529 struct abm_caps sw_caps; 4530 4531 /** 4532 * ABM HW caps. 4533 */ 4534 struct abm_caps hw_caps; 4535 }; 4536 4537 /** 4538 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4539 */ 4540 struct dmub_rb_cmd_abm_query_caps { 4541 /** 4542 * Command header. 4543 */ 4544 struct dmub_cmd_header header; 4545 4546 /** 4547 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4548 */ 4549 union { 4550 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4551 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4552 } data; 4553 }; 4554 4555 /** 4556 * enum dmub_abm_ace_curve_type - ACE curve type. 4557 */ 4558 enum dmub_abm_ace_curve_type { 4559 /** 4560 * ACE curve as defined by the SW layer. 4561 */ 4562 ABM_ACE_CURVE_TYPE__SW = 0, 4563 /** 4564 * ACE curve as defined by the SW to HW translation interface layer. 4565 */ 4566 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4567 }; 4568 4569 /** 4570 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4571 */ 4572 struct dmub_rb_cmd_abm_get_ace_curve { 4573 /** 4574 * Command header. 4575 */ 4576 struct dmub_cmd_header header; 4577 4578 /** 4579 * Address where ACE curve should be copied. 4580 */ 4581 union dmub_addr dest; 4582 4583 /** 4584 * Type of ACE curve being queried. 4585 */ 4586 enum dmub_abm_ace_curve_type ace_type; 4587 4588 /** 4589 * Indirect buffer length. 4590 */ 4591 uint16_t bytes; 4592 4593 /** 4594 * eDP panel instance. 4595 */ 4596 uint8_t panel_inst; 4597 4598 /** 4599 * Explicit padding to 4 byte boundary. 4600 */ 4601 uint8_t pad; 4602 }; 4603 4604 /** 4605 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4606 */ 4607 struct dmub_rb_cmd_abm_save_restore { 4608 /** 4609 * Command header. 4610 */ 4611 struct dmub_cmd_header header; 4612 4613 /** 4614 * OTG hw instance 4615 */ 4616 uint8_t otg_inst; 4617 4618 /** 4619 * Enable or disable ABM pause 4620 */ 4621 uint8_t freeze; 4622 4623 /** 4624 * Explicit padding to 4 byte boundary. 4625 */ 4626 uint8_t debug; 4627 4628 /** 4629 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4630 */ 4631 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4632 }; 4633 4634 /** 4635 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4636 */ 4637 4638 struct dmub_cmd_abm_set_event_data { 4639 4640 /** 4641 * VB Scaling Init. Strength Mapping 4642 * Byte 0: 0~255 for VB level 0 4643 * Byte 1: 0~255 for VB level 1 4644 * Byte 2: 0~255 for VB level 2 4645 * Byte 3: 0~255 for VB level 3 4646 */ 4647 uint32_t vb_scaling_strength_mapping; 4648 /** 4649 * VariBright Scaling Enable 4650 */ 4651 uint8_t vb_scaling_enable; 4652 /** 4653 * Panel Control HW instance mask. 4654 * Bit 0 is Panel Control HW instance 0. 4655 * Bit 1 is Panel Control HW instance 1. 4656 */ 4657 uint8_t panel_mask; 4658 4659 /** 4660 * Explicit padding to 4 byte boundary. 4661 */ 4662 uint8_t pad[2]; 4663 }; 4664 4665 /** 4666 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 4667 */ 4668 struct dmub_rb_cmd_abm_set_event { 4669 /** 4670 * Command header. 4671 */ 4672 struct dmub_cmd_header header; 4673 4674 /** 4675 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 4676 */ 4677 struct dmub_cmd_abm_set_event_data abm_set_event_data; 4678 }; 4679 4680 /** 4681 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4682 */ 4683 struct dmub_cmd_query_feature_caps_data { 4684 /** 4685 * DMUB feature capabilities. 4686 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4687 */ 4688 struct dmub_feature_caps feature_caps; 4689 }; 4690 4691 /** 4692 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4693 */ 4694 struct dmub_rb_cmd_query_feature_caps { 4695 /** 4696 * Command header. 4697 */ 4698 struct dmub_cmd_header header; 4699 /** 4700 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4701 */ 4702 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4703 }; 4704 4705 /** 4706 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4707 */ 4708 struct dmub_cmd_visual_confirm_color_data { 4709 /** 4710 * DMUB visual confirm color 4711 */ 4712 struct dmub_visual_confirm_color visual_confirm_color; 4713 }; 4714 4715 /** 4716 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4717 */ 4718 struct dmub_rb_cmd_get_visual_confirm_color { 4719 /** 4720 * Command header. 4721 */ 4722 struct dmub_cmd_header header; 4723 /** 4724 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4725 */ 4726 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4727 }; 4728 4729 /** 4730 * enum dmub_cmd_panel_cntl_type - Panel control command. 4731 */ 4732 enum dmub_cmd_panel_cntl_type { 4733 /** 4734 * Initializes embedded panel hardware blocks. 4735 */ 4736 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4737 /** 4738 * Queries backlight info for the embedded panel. 4739 */ 4740 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4741 /** 4742 * Sets the PWM Freq as per user's requirement. 4743 */ 4744 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 4745 }; 4746 4747 /** 4748 * struct dmub_cmd_panel_cntl_data - Panel control data. 4749 */ 4750 struct dmub_cmd_panel_cntl_data { 4751 uint32_t pwrseq_inst; /**< pwrseq instance */ 4752 uint32_t current_backlight; /* in/out */ 4753 uint32_t bl_pwm_cntl; /* in/out */ 4754 uint32_t bl_pwm_period_cntl; /* in/out */ 4755 uint32_t bl_pwm_ref_div1; /* in/out */ 4756 uint8_t is_backlight_on : 1; /* in/out */ 4757 uint8_t is_powered_on : 1; /* in/out */ 4758 uint8_t padding[3]; 4759 uint32_t bl_pwm_ref_div2; /* in/out */ 4760 uint8_t reserved[4]; 4761 }; 4762 4763 /** 4764 * struct dmub_rb_cmd_panel_cntl - Panel control command. 4765 */ 4766 struct dmub_rb_cmd_panel_cntl { 4767 struct dmub_cmd_header header; /**< header */ 4768 struct dmub_cmd_panel_cntl_data data; /**< payload */ 4769 }; 4770 4771 struct dmub_optc_state { 4772 uint32_t v_total_max; 4773 uint32_t v_total_min; 4774 uint32_t tg_inst; 4775 }; 4776 4777 struct dmub_rb_cmd_drr_update { 4778 struct dmub_cmd_header header; 4779 struct dmub_optc_state dmub_optc_state_req; 4780 }; 4781 4782 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 4783 uint32_t pix_clk_100hz; 4784 uint8_t max_ramp_step; 4785 uint8_t pipes; 4786 uint8_t min_refresh_in_hz; 4787 uint8_t pipe_count; 4788 uint8_t pipe_index[4]; 4789 }; 4790 4791 struct dmub_cmd_fw_assisted_mclk_switch_config { 4792 uint8_t fams_enabled; 4793 uint8_t visual_confirm_enabled; 4794 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 4795 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 4796 }; 4797 4798 struct dmub_rb_cmd_fw_assisted_mclk_switch { 4799 struct dmub_cmd_header header; 4800 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 4801 }; 4802 4803 /** 4804 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4805 */ 4806 struct dmub_cmd_lvtma_control_data { 4807 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 4808 uint8_t bypass_panel_control_wait; 4809 uint8_t reserved_0[2]; /**< For future use */ 4810 uint8_t pwrseq_inst; /**< LVTMA control instance */ 4811 uint8_t reserved_1[3]; /**< For future use */ 4812 }; 4813 4814 /** 4815 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4816 */ 4817 struct dmub_rb_cmd_lvtma_control { 4818 /** 4819 * Command header. 4820 */ 4821 struct dmub_cmd_header header; 4822 /** 4823 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4824 */ 4825 struct dmub_cmd_lvtma_control_data data; 4826 }; 4827 4828 /** 4829 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4830 */ 4831 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 4832 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4833 uint8_t is_usb; /**< is phy is usb */ 4834 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 4835 uint8_t is_dp4; /**< is dp in 4 lane */ 4836 }; 4837 4838 /** 4839 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4840 */ 4841 struct dmub_rb_cmd_transmitter_query_dp_alt { 4842 struct dmub_cmd_header header; /**< header */ 4843 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 4844 }; 4845 4846 struct phy_test_mode { 4847 uint8_t mode; 4848 uint8_t pat0; 4849 uint8_t pad[2]; 4850 }; 4851 4852 /** 4853 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4854 */ 4855 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 4856 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4857 uint8_t mode; /**< HDMI/DP/DP2 etc */ 4858 uint8_t lane_num; /**< Number of lanes */ 4859 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 4860 struct phy_test_mode test_mode; 4861 enum dmub_phy_fsm_state state; 4862 uint32_t status; 4863 uint8_t pad; 4864 }; 4865 4866 /** 4867 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4868 */ 4869 struct dmub_rb_cmd_transmitter_set_phy_fsm { 4870 struct dmub_cmd_header header; /**< header */ 4871 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 4872 }; 4873 4874 /** 4875 * Maximum number of bytes a chunk sent to DMUB for parsing 4876 */ 4877 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 4878 4879 /** 4880 * Represent a chunk of CEA blocks sent to DMUB for parsing 4881 */ 4882 struct dmub_cmd_send_edid_cea { 4883 uint16_t offset; /**< offset into the CEA block */ 4884 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 4885 uint16_t cea_total_length; /**< total length of the CEA block */ 4886 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 4887 uint8_t pad[3]; /**< padding and for future expansion */ 4888 }; 4889 4890 /** 4891 * Result of VSDB parsing from CEA block 4892 */ 4893 struct dmub_cmd_edid_cea_amd_vsdb { 4894 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 4895 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 4896 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 4897 uint16_t min_frame_rate; /**< Maximum frame rate */ 4898 uint16_t max_frame_rate; /**< Minimum frame rate */ 4899 }; 4900 4901 /** 4902 * Result of sending a CEA chunk 4903 */ 4904 struct dmub_cmd_edid_cea_ack { 4905 uint16_t offset; /**< offset of the chunk into the CEA block */ 4906 uint8_t success; /**< 1 if this sending of chunk succeeded */ 4907 uint8_t pad; /**< padding and for future expansion */ 4908 }; 4909 4910 /** 4911 * Specify whether the result is an ACK/NACK or the parsing has finished 4912 */ 4913 enum dmub_cmd_edid_cea_reply_type { 4914 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 4915 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 4916 }; 4917 4918 /** 4919 * Definition of a DMUB_CMD__EDID_CEA command. 4920 */ 4921 struct dmub_rb_cmd_edid_cea { 4922 struct dmub_cmd_header header; /**< Command header */ 4923 union dmub_cmd_edid_cea_data { 4924 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 4925 struct dmub_cmd_edid_cea_output { /**< output with results */ 4926 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 4927 union { 4928 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 4929 struct dmub_cmd_edid_cea_ack ack; 4930 }; 4931 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 4932 } data; /**< Command data */ 4933 4934 }; 4935 4936 /** 4937 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 4938 */ 4939 struct dmub_cmd_cable_id_input { 4940 uint8_t phy_inst; /**< phy inst for cable id data */ 4941 }; 4942 4943 /** 4944 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 4945 */ 4946 struct dmub_cmd_cable_id_output { 4947 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 4948 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 4949 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 4950 uint8_t RESERVED :2; /**< reserved means not defined */ 4951 }; 4952 4953 /** 4954 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 4955 */ 4956 struct dmub_rb_cmd_get_usbc_cable_id { 4957 struct dmub_cmd_header header; /**< Command header */ 4958 /** 4959 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 4960 */ 4961 union dmub_cmd_cable_id_data { 4962 struct dmub_cmd_cable_id_input input; /**< Input */ 4963 struct dmub_cmd_cable_id_output output; /**< Output */ 4964 uint8_t output_raw; /**< Raw data output */ 4965 } data; 4966 }; 4967 4968 /** 4969 * Command type of a DMUB_CMD__SECURE_DISPLAY command 4970 */ 4971 enum dmub_cmd_secure_display_type { 4972 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 4973 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 4974 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 4975 }; 4976 4977 /** 4978 * Definition of a DMUB_CMD__SECURE_DISPLAY command 4979 */ 4980 struct dmub_rb_cmd_secure_display { 4981 struct dmub_cmd_header header; 4982 /** 4983 * Data passed from driver to dmub firmware. 4984 */ 4985 struct dmub_cmd_roi_info { 4986 uint16_t x_start; 4987 uint16_t x_end; 4988 uint16_t y_start; 4989 uint16_t y_end; 4990 uint8_t otg_id; 4991 uint8_t phy_id; 4992 } roi_info; 4993 }; 4994 4995 /** 4996 * Command type of a DMUB_CMD__PSP command 4997 */ 4998 enum dmub_cmd_psp_type { 4999 DMUB_CMD__PSP_ASSR_ENABLE = 0 5000 }; 5001 5002 /** 5003 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5004 */ 5005 struct dmub_cmd_assr_enable_data { 5006 /** 5007 * ASSR enable or disable. 5008 */ 5009 uint8_t enable; 5010 /** 5011 * PHY port type. 5012 * Indicates eDP / non-eDP port type 5013 */ 5014 uint8_t phy_port_type; 5015 /** 5016 * PHY port ID. 5017 */ 5018 uint8_t phy_port_id; 5019 /** 5020 * Link encoder index. 5021 */ 5022 uint8_t link_enc_index; 5023 /** 5024 * HPO mode. 5025 */ 5026 uint8_t hpo_mode; 5027 5028 /** 5029 * Reserved field. 5030 */ 5031 uint8_t reserved[7]; 5032 }; 5033 5034 /** 5035 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5036 */ 5037 struct dmub_rb_cmd_assr_enable { 5038 /** 5039 * Command header. 5040 */ 5041 struct dmub_cmd_header header; 5042 5043 /** 5044 * Assr data. 5045 */ 5046 struct dmub_cmd_assr_enable_data assr_data; 5047 5048 /** 5049 * Reserved field. 5050 */ 5051 uint32_t reserved[3]; 5052 }; 5053 5054 /** 5055 * union dmub_rb_cmd - DMUB inbox command. 5056 */ 5057 union dmub_rb_cmd { 5058 /** 5059 * Elements shared with all commands. 5060 */ 5061 struct dmub_rb_cmd_common cmd_common; 5062 /** 5063 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5064 */ 5065 struct dmub_rb_cmd_read_modify_write read_modify_write; 5066 /** 5067 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5068 */ 5069 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5070 /** 5071 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5072 */ 5073 struct dmub_rb_cmd_burst_write burst_write; 5074 /** 5075 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5076 */ 5077 struct dmub_rb_cmd_reg_wait reg_wait; 5078 /** 5079 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5080 */ 5081 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5082 /** 5083 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5084 */ 5085 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5086 /** 5087 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5088 */ 5089 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5090 /** 5091 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5092 */ 5093 struct dmub_rb_cmd_dpphy_init dpphy_init; 5094 /** 5095 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5096 */ 5097 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5098 /** 5099 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5100 */ 5101 struct dmub_rb_cmd_domain_control domain_control; 5102 /** 5103 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5104 */ 5105 struct dmub_rb_cmd_psr_set_version psr_set_version; 5106 /** 5107 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5108 */ 5109 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5110 /** 5111 * Definition of a DMUB_CMD__PSR_ENABLE command. 5112 */ 5113 struct dmub_rb_cmd_psr_enable psr_enable; 5114 /** 5115 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5116 */ 5117 struct dmub_rb_cmd_psr_set_level psr_set_level; 5118 /** 5119 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5120 */ 5121 struct dmub_rb_cmd_psr_force_static psr_force_static; 5122 /** 5123 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5124 */ 5125 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5126 /** 5127 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5128 */ 5129 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5130 /** 5131 * Definition of a DMUB_CMD__HW_LOCK command. 5132 * Command is used by driver and FW. 5133 */ 5134 struct dmub_rb_cmd_lock_hw lock_hw; 5135 /** 5136 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5137 */ 5138 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5139 /** 5140 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5141 */ 5142 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5143 /** 5144 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5145 */ 5146 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5147 /** 5148 * Definition of a DMUB_CMD__MALL command. 5149 */ 5150 struct dmub_rb_cmd_mall mall; 5151 5152 /** 5153 * Definition of a DMUB_CMD__CAB command. 5154 */ 5155 struct dmub_rb_cmd_cab_for_ss cab; 5156 5157 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5158 5159 /** 5160 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5161 */ 5162 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5163 5164 /** 5165 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5166 */ 5167 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5168 5169 /** 5170 * Definition of DMUB_CMD__PANEL_CNTL commands. 5171 */ 5172 struct dmub_rb_cmd_panel_cntl panel_cntl; 5173 5174 /** 5175 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5176 */ 5177 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5178 5179 /** 5180 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5181 */ 5182 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5183 5184 /** 5185 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5186 */ 5187 struct dmub_rb_cmd_abm_set_level abm_set_level; 5188 5189 /** 5190 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5191 */ 5192 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5193 5194 /** 5195 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5196 */ 5197 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5198 5199 /** 5200 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5201 */ 5202 struct dmub_rb_cmd_abm_init_config abm_init_config; 5203 5204 /** 5205 * Definition of a DMUB_CMD__ABM_PAUSE command. 5206 */ 5207 struct dmub_rb_cmd_abm_pause abm_pause; 5208 5209 /** 5210 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5211 */ 5212 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5213 5214 /** 5215 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5216 */ 5217 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5218 5219 /** 5220 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5221 */ 5222 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5223 5224 /** 5225 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5226 */ 5227 struct dmub_rb_cmd_abm_set_event abm_set_event; 5228 5229 /** 5230 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5231 */ 5232 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5233 5234 /** 5235 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5236 */ 5237 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5238 5239 /** 5240 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5241 */ 5242 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5243 5244 /** 5245 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5246 */ 5247 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5248 struct dmub_rb_cmd_drr_update drr_update; 5249 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5250 5251 /** 5252 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5253 */ 5254 struct dmub_rb_cmd_lvtma_control lvtma_control; 5255 /** 5256 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5257 */ 5258 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5259 /** 5260 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5261 */ 5262 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5263 /** 5264 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5265 */ 5266 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5267 /** 5268 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5269 */ 5270 struct dmub_rb_cmd_set_config_access set_config_access; 5271 /** 5272 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5273 */ 5274 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5275 /** 5276 * Definition of a DMUB_CMD__EDID_CEA command. 5277 */ 5278 struct dmub_rb_cmd_edid_cea edid_cea; 5279 /** 5280 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5281 */ 5282 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5283 5284 /** 5285 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5286 */ 5287 struct dmub_rb_cmd_query_hpd_state query_hpd; 5288 /** 5289 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5290 */ 5291 struct dmub_rb_cmd_secure_display secure_display; 5292 5293 /** 5294 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5295 */ 5296 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5297 /** 5298 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5299 */ 5300 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5301 /* 5302 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5303 */ 5304 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5305 /** 5306 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5307 */ 5308 struct dmub_rb_cmd_replay_enable replay_enable; 5309 /** 5310 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5311 */ 5312 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5313 /** 5314 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5315 */ 5316 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5317 /** 5318 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5319 */ 5320 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5321 5322 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5323 /** 5324 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5325 */ 5326 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5327 /** 5328 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5329 */ 5330 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5331 /** 5332 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5333 */ 5334 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5335 /** 5336 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5337 */ 5338 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5339 /** 5340 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5341 */ 5342 struct dmub_rb_cmd_assr_enable assr_enable; 5343 struct dmub_rb_cmd_fams2 fams2_config; 5344 5345 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5346 5347 struct dmub_rb_cmd_fams2_flip fams2_flip; 5348 }; 5349 5350 /** 5351 * union dmub_rb_out_cmd - Outbox command 5352 */ 5353 union dmub_rb_out_cmd { 5354 /** 5355 * Parameters common to every command. 5356 */ 5357 struct dmub_rb_cmd_common cmd_common; 5358 /** 5359 * AUX reply command. 5360 */ 5361 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5362 /** 5363 * HPD notify command. 5364 */ 5365 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5366 /** 5367 * SET_CONFIG reply command. 5368 */ 5369 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5370 /** 5371 * DPIA notification command. 5372 */ 5373 struct dmub_rb_cmd_dpia_notification dpia_notification; 5374 /** 5375 * HPD sense notification command. 5376 */ 5377 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5378 }; 5379 #pragma pack(pop) 5380 5381 5382 //============================================================================== 5383 //</DMUB_CMD>=================================================================== 5384 //============================================================================== 5385 //< DMUB_RB>==================================================================== 5386 //============================================================================== 5387 5388 /** 5389 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5390 */ 5391 struct dmub_rb_init_params { 5392 void *ctx; /**< Caller provided context pointer */ 5393 void *base_address; /**< CPU base address for ring's data */ 5394 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5395 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5396 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5397 }; 5398 5399 /** 5400 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5401 */ 5402 struct dmub_rb { 5403 void *base_address; /**< CPU address for the ring's data */ 5404 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5405 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5406 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5407 5408 void *ctx; /**< Caller provided context pointer */ 5409 void *dmub; /**< Pointer to the DMUB interface */ 5410 }; 5411 5412 /** 5413 * @brief Checks if the ringbuffer is empty. 5414 * 5415 * @param rb DMUB Ringbuffer 5416 * @return true if empty 5417 * @return false otherwise 5418 */ 5419 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5420 { 5421 return (rb->wrpt == rb->rptr); 5422 } 5423 5424 /** 5425 * @brief Checks if the ringbuffer is full 5426 * 5427 * @param rb DMUB Ringbuffer 5428 * @return true if full 5429 * @return false otherwise 5430 */ 5431 static inline bool dmub_rb_full(struct dmub_rb *rb) 5432 { 5433 uint32_t data_count; 5434 5435 if (rb->wrpt >= rb->rptr) 5436 data_count = rb->wrpt - rb->rptr; 5437 else 5438 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5439 5440 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5441 } 5442 5443 /** 5444 * @brief Pushes a command into the ringbuffer 5445 * 5446 * @param rb DMUB ringbuffer 5447 * @param cmd The command to push 5448 * @return true if the ringbuffer was not full 5449 * @return false otherwise 5450 */ 5451 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5452 const union dmub_rb_cmd *cmd) 5453 { 5454 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5455 const uint64_t *src = (const uint64_t *)cmd; 5456 uint8_t i; 5457 5458 if (dmub_rb_full(rb)) 5459 return false; 5460 5461 // copying data 5462 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5463 *dst++ = *src++; 5464 5465 rb->wrpt += DMUB_RB_CMD_SIZE; 5466 5467 if (rb->wrpt >= rb->capacity) 5468 rb->wrpt %= rb->capacity; 5469 5470 return true; 5471 } 5472 5473 /** 5474 * @brief Pushes a command into the DMUB outbox ringbuffer 5475 * 5476 * @param rb DMUB outbox ringbuffer 5477 * @param cmd Outbox command 5478 * @return true if not full 5479 * @return false otherwise 5480 */ 5481 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5482 const union dmub_rb_out_cmd *cmd) 5483 { 5484 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 5485 const uint8_t *src = (const uint8_t *)cmd; 5486 5487 if (dmub_rb_full(rb)) 5488 return false; 5489 5490 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 5491 5492 rb->wrpt += DMUB_RB_CMD_SIZE; 5493 5494 if (rb->wrpt >= rb->capacity) 5495 rb->wrpt %= rb->capacity; 5496 5497 return true; 5498 } 5499 5500 /** 5501 * @brief Returns the next unprocessed command in the ringbuffer. 5502 * 5503 * @param rb DMUB ringbuffer 5504 * @param cmd The command to return 5505 * @return true if not empty 5506 * @return false otherwise 5507 */ 5508 static inline bool dmub_rb_front(struct dmub_rb *rb, 5509 union dmub_rb_cmd **cmd) 5510 { 5511 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 5512 5513 if (dmub_rb_empty(rb)) 5514 return false; 5515 5516 *cmd = (union dmub_rb_cmd *)rb_cmd; 5517 5518 return true; 5519 } 5520 5521 /** 5522 * @brief Determines the next ringbuffer offset. 5523 * 5524 * @param rb DMUB inbox ringbuffer 5525 * @param num_cmds Number of commands 5526 * @param next_rptr The next offset in the ringbuffer 5527 */ 5528 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 5529 uint32_t num_cmds, 5530 uint32_t *next_rptr) 5531 { 5532 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 5533 5534 if (*next_rptr >= rb->capacity) 5535 *next_rptr %= rb->capacity; 5536 } 5537 5538 /** 5539 * @brief Returns a pointer to a command in the inbox. 5540 * 5541 * @param rb DMUB inbox ringbuffer 5542 * @param cmd The inbox command to return 5543 * @param rptr The ringbuffer offset 5544 * @return true if not empty 5545 * @return false otherwise 5546 */ 5547 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 5548 union dmub_rb_cmd **cmd, 5549 uint32_t rptr) 5550 { 5551 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 5552 5553 if (dmub_rb_empty(rb)) 5554 return false; 5555 5556 *cmd = (union dmub_rb_cmd *)rb_cmd; 5557 5558 return true; 5559 } 5560 5561 /** 5562 * @brief Returns the next unprocessed command in the outbox. 5563 * 5564 * @param rb DMUB outbox ringbuffer 5565 * @param cmd The outbox command to return 5566 * @return true if not empty 5567 * @return false otherwise 5568 */ 5569 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 5570 union dmub_rb_out_cmd *cmd) 5571 { 5572 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 5573 uint64_t *dst = (uint64_t *)cmd; 5574 uint8_t i; 5575 5576 if (dmub_rb_empty(rb)) 5577 return false; 5578 5579 // copying data 5580 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5581 *dst++ = *src++; 5582 5583 return true; 5584 } 5585 5586 /** 5587 * @brief Removes the front entry in the ringbuffer. 5588 * 5589 * @param rb DMUB ringbuffer 5590 * @return true if the command was removed 5591 * @return false if there were no commands 5592 */ 5593 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 5594 { 5595 if (dmub_rb_empty(rb)) 5596 return false; 5597 5598 rb->rptr += DMUB_RB_CMD_SIZE; 5599 5600 if (rb->rptr >= rb->capacity) 5601 rb->rptr %= rb->capacity; 5602 5603 return true; 5604 } 5605 5606 /** 5607 * @brief Flushes commands in the ringbuffer to framebuffer memory. 5608 * 5609 * Avoids a race condition where DMCUB accesses memory while 5610 * there are still writes in flight to framebuffer. 5611 * 5612 * @param rb DMUB ringbuffer 5613 */ 5614 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 5615 { 5616 uint32_t rptr = rb->rptr; 5617 uint32_t wptr = rb->wrpt; 5618 5619 while (rptr != wptr) { 5620 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 5621 uint8_t i; 5622 5623 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5624 (void)READ_ONCE(*data++); 5625 5626 rptr += DMUB_RB_CMD_SIZE; 5627 if (rptr >= rb->capacity) 5628 rptr %= rb->capacity; 5629 } 5630 } 5631 5632 /** 5633 * @brief Initializes a DMCUB ringbuffer 5634 * 5635 * @param rb DMUB ringbuffer 5636 * @param init_params initial configuration for the ringbuffer 5637 */ 5638 static inline void dmub_rb_init(struct dmub_rb *rb, 5639 struct dmub_rb_init_params *init_params) 5640 { 5641 rb->base_address = init_params->base_address; 5642 rb->capacity = init_params->capacity; 5643 rb->rptr = init_params->read_ptr; 5644 rb->wrpt = init_params->write_ptr; 5645 } 5646 5647 /** 5648 * @brief Copies output data from in/out commands into the given command. 5649 * 5650 * @param rb DMUB ringbuffer 5651 * @param cmd Command to copy data into 5652 */ 5653 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5654 union dmub_rb_cmd *cmd) 5655 { 5656 // Copy rb entry back into command 5657 uint8_t *rd_ptr = (rb->rptr == 0) ? 5658 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5659 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5660 5661 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5662 } 5663 5664 //============================================================================== 5665 //</DMUB_RB>==================================================================== 5666 //============================================================================== 5667 #endif /* _DMUB_CMD_H_ */ 5668