1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Maximum number of streams on any ASIC. */ 108 #define DMUB_MAX_STREAMS 6 109 110 /* Maximum number of planes on any ASIC. */ 111 #define DMUB_MAX_PLANES 6 112 113 /* Maximum number of phantom planes on any ASIC */ 114 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 115 116 /* Trace buffer offset for entry */ 117 #define TRACE_BUFFER_ENTRY_OFFSET 16 118 119 /** 120 * Maximum number of dirty rects supported by FW. 121 */ 122 #define DMUB_MAX_DIRTY_RECTS 3 123 124 /** 125 * 126 * PSR control version legacy 127 */ 128 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 129 /** 130 * PSR control version with multi edp support 131 */ 132 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 133 134 135 /** 136 * ABM control version legacy 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 139 140 /** 141 * ABM control version with multi edp support 142 */ 143 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 144 145 /** 146 * Physical framebuffer address location, 64-bit. 147 */ 148 #ifndef PHYSICAL_ADDRESS_LOC 149 #define PHYSICAL_ADDRESS_LOC union large_integer 150 #endif 151 152 /** 153 * OS/FW agnostic memcpy 154 */ 155 #ifndef dmub_memcpy 156 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 157 #endif 158 159 /** 160 * OS/FW agnostic memset 161 */ 162 #ifndef dmub_memset 163 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 164 #endif 165 166 /** 167 * OS/FW agnostic memcmp 168 */ 169 #ifndef dmub_memcmp 170 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 171 #endif 172 173 /** 174 * OS/FW agnostic udelay 175 */ 176 #ifndef dmub_udelay 177 #define dmub_udelay(microseconds) udelay(microseconds) 178 #endif 179 180 #pragma pack(push, 1) 181 #define ABM_NUM_OF_ACE_SEGMENTS 5 182 183 /** 184 * Debug FW state offset 185 */ 186 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 187 188 union abm_flags { 189 struct { 190 /** 191 * @abm_enabled: Indicates if ABM is enabled. 192 */ 193 unsigned int abm_enabled : 1; 194 195 /** 196 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 197 */ 198 unsigned int disable_abm_requested : 1; 199 200 /** 201 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 202 */ 203 unsigned int disable_abm_immediately : 1; 204 205 /** 206 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 207 * to be disabled immediately and keep gain. 208 */ 209 unsigned int disable_abm_immediate_keep_gain : 1; 210 211 /** 212 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 213 */ 214 unsigned int fractional_pwm : 1; 215 216 /** 217 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 218 * of user backlight level. 219 */ 220 unsigned int abm_gradual_bl_change : 1; 221 222 /** 223 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 224 */ 225 unsigned int abm_new_frame : 1; 226 227 /** 228 * @vb_scaling_enabled: Indicates variBright Scaling Enable 229 */ 230 unsigned int vb_scaling_enabled : 1; 231 } bitfields; 232 233 unsigned int u32All; 234 }; 235 236 struct abm_save_restore { 237 /** 238 * @flags: Misc. ABM flags. 239 */ 240 union abm_flags flags; 241 242 /** 243 * @pause: true: pause ABM and get state 244 * false: unpause ABM after setting state 245 */ 246 uint32_t pause; 247 248 /** 249 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 250 */ 251 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 252 253 /** 254 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 255 */ 256 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 257 258 /** 259 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 260 */ 261 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 262 263 264 /** 265 * @knee_threshold: Current x-position of ACE knee (u0.16). 266 */ 267 uint32_t knee_threshold; 268 /** 269 * @current_gain: Current backlight reduction (u16.16). 270 */ 271 uint32_t current_gain; 272 /** 273 * @curr_bl_level: Current actual backlight level converging to target backlight level. 274 */ 275 uint16_t curr_bl_level; 276 277 /** 278 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 279 */ 280 uint16_t curr_user_bl_level; 281 282 }; 283 284 /** 285 * union dmub_addr - DMUB physical/virtual 64-bit address. 286 */ 287 union dmub_addr { 288 struct { 289 uint32_t low_part; /**< Lower 32 bits */ 290 uint32_t high_part; /**< Upper 32 bits */ 291 } u; /*<< Low/high bit access */ 292 uint64_t quad_part; /*<< 64 bit address */ 293 }; 294 #pragma pack(pop) 295 296 /** 297 * Dirty rect definition. 298 */ 299 struct dmub_rect { 300 /** 301 * Dirty rect x offset. 302 */ 303 uint32_t x; 304 305 /** 306 * Dirty rect y offset. 307 */ 308 uint32_t y; 309 310 /** 311 * Dirty rect width. 312 */ 313 uint32_t width; 314 315 /** 316 * Dirty rect height. 317 */ 318 uint32_t height; 319 }; 320 321 /** 322 * Flags that can be set by driver to change some PSR behaviour. 323 */ 324 union dmub_psr_debug_flags { 325 /** 326 * Debug flags. 327 */ 328 struct { 329 /** 330 * Enable visual confirm in FW. 331 */ 332 uint32_t visual_confirm : 1; 333 334 /** 335 * Force all selective updates to bw full frame updates. 336 */ 337 uint32_t force_full_frame_update : 1; 338 339 /** 340 * Use HW Lock Mgr object to do HW locking in FW. 341 */ 342 uint32_t use_hw_lock_mgr : 1; 343 344 /** 345 * Use TPS3 signal when restore main link. 346 */ 347 uint32_t force_wakeup_by_tps3 : 1; 348 349 /** 350 * Back to back flip, therefore cannot power down PHY 351 */ 352 uint32_t back_to_back_flip : 1; 353 354 /** 355 * Enable visual confirm for IPS 356 */ 357 uint32_t enable_ips_visual_confirm : 1; 358 } bitfields; 359 360 /** 361 * Union for debug flags. 362 */ 363 uint32_t u32All; 364 }; 365 366 /** 367 * Flags that can be set by driver to change some Replay behaviour. 368 */ 369 union replay_debug_flags { 370 struct { 371 /** 372 * 0x1 (bit 0) 373 * Enable visual confirm in FW. 374 */ 375 uint32_t visual_confirm : 1; 376 377 /** 378 * 0x2 (bit 1) 379 * @skip_crc: Set if need to skip CRC. 380 */ 381 uint32_t skip_crc : 1; 382 383 /** 384 * 0x4 (bit 2) 385 * @force_link_power_on: Force disable ALPM control 386 */ 387 uint32_t force_link_power_on : 1; 388 389 /** 390 * 0x8 (bit 3) 391 * @force_phy_power_on: Force phy power on 392 */ 393 uint32_t force_phy_power_on : 1; 394 395 /** 396 * 0x10 (bit 4) 397 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 398 */ 399 uint32_t timing_resync_disabled : 1; 400 401 /** 402 * 0x20 (bit 5) 403 * @skip_crtc_disabled: CRTC disable skipped 404 */ 405 uint32_t skip_crtc_disabled : 1; 406 407 /** 408 * 0x40 (bit 6) 409 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 410 */ 411 uint32_t force_defer_one_frame_update : 1; 412 413 /** 414 * 0x80 (bit 7) 415 * @disable_delay_alpm_on: Force disable delay alpm on 416 */ 417 uint32_t disable_delay_alpm_on : 1; 418 419 /** 420 * 0x100 (bit 8) 421 * @disable_desync_error_check: Force disable desync error check 422 */ 423 uint32_t disable_desync_error_check : 1; 424 425 /** 426 * 0x200 (bit 9) 427 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 428 */ 429 uint32_t force_self_update_when_abm_non_steady : 1; 430 431 /** 432 * 0x400 (bit 10) 433 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 434 * If we enter IPS2, the Visual confirm bar will change to yellow 435 */ 436 uint32_t enable_ips_visual_confirm : 1; 437 438 /** 439 * 0x800 (bit 11) 440 * @enable_ips_residency_profiling: Enable IPS residency profiling 441 */ 442 uint32_t enable_ips_residency_profiling : 1; 443 444 /** 445 * 0x1000 (bit 12) 446 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 447 */ 448 uint32_t enable_coasting_vtotal_check : 1; 449 /** 450 * 0x2000 (bit 13) 451 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 452 */ 453 uint32_t enable_visual_confirm_debug : 1; 454 455 uint32_t reserved : 18; 456 } bitfields; 457 458 uint32_t u32All; 459 }; 460 461 /** 462 * Flags record error state. 463 */ 464 union replay_visual_confirm_error_state_flags { 465 struct { 466 /** 467 * 0x1 (bit 0) - Desync Error flag. 468 */ 469 uint32_t desync_error : 1; 470 471 /** 472 * 0x2 (bit 1) - State Transition Error flag. 473 */ 474 uint32_t state_transition_error : 1; 475 476 /** 477 * 0x4 (bit 2) - Crc Error flag 478 */ 479 uint32_t crc_error : 1; 480 481 /** 482 * 0x8 (bit 3) - Reserved 483 */ 484 uint32_t reserved_3 : 1; 485 486 /** 487 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 488 * Added new debug flag to control DPCD. 489 */ 490 uint32_t incorrect_vtotal_in_static_screen : 1; 491 492 /** 493 * 0x20 (bit 5) - No doubled Refresh Rate. 494 */ 495 uint32_t no_double_rr : 1; 496 497 /** 498 * Reserved bit 6-7 499 */ 500 uint32_t reserved_6_7 : 2; 501 502 /** 503 * Reserved bit 9-31 504 */ 505 uint32_t reserved_9_31 : 24; 506 } bitfields; 507 508 uint32_t u32All; 509 }; 510 511 union replay_hw_flags { 512 struct { 513 /** 514 * @allow_alpm_fw_standby_mode: To indicate whether the 515 * ALPM FW standby mode is allowed 516 */ 517 uint32_t allow_alpm_fw_standby_mode : 1; 518 519 /* 520 * @dsc_enable_status: DSC enable status in driver 521 */ 522 uint32_t dsc_enable_status : 1; 523 524 /** 525 * @fec_enable_status: receive fec enable/disable status from driver 526 */ 527 uint32_t fec_enable_status : 1; 528 529 /* 530 * @smu_optimizations_en: SMU power optimization. 531 * Only when active display is Replay capable and display enters Replay. 532 * Trigger interrupt to SMU to powerup/down. 533 */ 534 uint32_t smu_optimizations_en : 1; 535 536 /** 537 * @phy_power_state: Indicates current phy power state 538 */ 539 uint32_t phy_power_state : 1; 540 541 /** 542 * @link_power_state: Indicates current link power state 543 */ 544 uint32_t link_power_state : 1; 545 /** 546 * Use TPS3 signal when restore main link. 547 */ 548 uint32_t force_wakeup_by_tps3 : 1; 549 /** 550 * @is_alpm_initialized: Indicates whether ALPM is initialized 551 */ 552 uint32_t is_alpm_initialized : 1; 553 554 /** 555 * @alpm_mode: Indicates ALPM mode selected 556 */ 557 uint32_t alpm_mode : 2; 558 } bitfields; 559 560 uint32_t u32All; 561 }; 562 563 union fw_assisted_mclk_switch_version { 564 struct { 565 uint8_t minor : 5; 566 uint8_t major : 3; 567 }; 568 uint8_t ver; 569 }; 570 571 /** 572 * DMUB feature capabilities. 573 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 574 */ 575 struct dmub_feature_caps { 576 /** 577 * Max PSR version supported by FW. 578 */ 579 uint8_t psr; 580 uint8_t fw_assisted_mclk_switch_ver; 581 uint8_t reserved[4]; 582 uint8_t subvp_psr_support; 583 uint8_t gecc_enable; 584 uint8_t replay_supported; 585 uint8_t replay_reserved[3]; 586 uint8_t abm_aux_backlight_support; 587 }; 588 589 struct dmub_visual_confirm_color { 590 /** 591 * Maximum 10 bits color value 592 */ 593 uint16_t color_r_cr; 594 uint16_t color_g_y; 595 uint16_t color_b_cb; 596 uint16_t panel_inst; 597 }; 598 599 //============================================================================== 600 //</DMUB_TYPES>================================================================= 601 //============================================================================== 602 //< DMUB_META>================================================================== 603 //============================================================================== 604 #pragma pack(push, 1) 605 606 /* Magic value for identifying dmub_fw_meta_info */ 607 #define DMUB_FW_META_MAGIC 0x444D5542 608 609 /* Offset from the end of the file to the dmub_fw_meta_info */ 610 #define DMUB_FW_META_OFFSET 0x24 611 612 /** 613 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 614 */ 615 union dmub_fw_meta_feature_bits { 616 struct { 617 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 618 uint32_t reserved : 31; 619 } bits; /**< status bits */ 620 uint32_t all; /**< 32-bit access to status bits */ 621 }; 622 623 /** 624 * struct dmub_fw_meta_info - metadata associated with fw binary 625 * 626 * NOTE: This should be considered a stable API. Fields should 627 * not be repurposed or reordered. New fields should be 628 * added instead to extend the structure. 629 * 630 * @magic_value: magic value identifying DMUB firmware meta info 631 * @fw_region_size: size of the firmware state region 632 * @trace_buffer_size: size of the tracebuffer region 633 * @fw_version: the firmware version information 634 * @dal_fw: 1 if the firmware is DAL 635 * @shared_state_size: size of the shared state region in bytes 636 * @shared_state_features: number of shared state features 637 */ 638 struct dmub_fw_meta_info { 639 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 640 uint32_t fw_region_size; /**< size of the firmware state region */ 641 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 642 uint32_t fw_version; /**< the firmware version information */ 643 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 644 uint8_t reserved[3]; /**< padding bits */ 645 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 646 uint16_t shared_state_features; /**< number of shared state features */ 647 uint16_t reserved2; /**< padding bytes */ 648 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 649 }; 650 651 /** 652 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 653 */ 654 union dmub_fw_meta { 655 struct dmub_fw_meta_info info; /**< metadata info */ 656 uint8_t reserved[64]; /**< padding bits */ 657 }; 658 659 #pragma pack(pop) 660 661 //============================================================================== 662 //< DMUB Trace Buffer>================================================================ 663 //============================================================================== 664 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 665 /** 666 * dmub_trace_code_t - firmware trace code, 32-bits 667 */ 668 typedef uint32_t dmub_trace_code_t; 669 670 /** 671 * struct dmcub_trace_buf_entry - Firmware trace entry 672 */ 673 struct dmcub_trace_buf_entry { 674 dmub_trace_code_t trace_code; /**< trace code for the event */ 675 uint32_t tick_count; /**< the tick count at time of trace */ 676 uint32_t param0; /**< trace defined parameter 0 */ 677 uint32_t param1; /**< trace defined parameter 1 */ 678 }; 679 #endif 680 681 //============================================================================== 682 //< DMUB_STATUS>================================================================ 683 //============================================================================== 684 685 /** 686 * DMCUB scratch registers can be used to determine firmware status. 687 * Current scratch register usage is as follows: 688 * 689 * SCRATCH0: FW Boot Status register 690 * SCRATCH5: LVTMA Status Register 691 * SCRATCH15: FW Boot Options register 692 */ 693 694 /** 695 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 696 */ 697 union dmub_fw_boot_status { 698 struct { 699 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 700 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 701 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 702 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 703 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 704 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 705 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 706 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 707 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 708 } bits; /**< status bits */ 709 uint32_t all; /**< 32-bit access to status bits */ 710 }; 711 712 /** 713 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 714 */ 715 enum dmub_fw_boot_status_bit { 716 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 717 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 718 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 719 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 720 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 721 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 722 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 723 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 724 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 725 }; 726 727 /* Register bit definition for SCRATCH5 */ 728 union dmub_lvtma_status { 729 struct { 730 uint32_t psp_ok : 1; 731 uint32_t edp_on : 1; 732 uint32_t reserved : 30; 733 } bits; 734 uint32_t all; 735 }; 736 737 enum dmub_lvtma_status_bit { 738 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 739 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 740 }; 741 742 enum dmub_ips_disable_type { 743 DMUB_IPS_ENABLE = 0, 744 DMUB_IPS_DISABLE_ALL = 1, 745 DMUB_IPS_DISABLE_IPS1 = 2, 746 DMUB_IPS_DISABLE_IPS2 = 3, 747 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 748 DMUB_IPS_DISABLE_DYNAMIC = 5, 749 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 750 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 751 }; 752 753 enum dmub_ips_rcg_disable_type { 754 DMUB_IPS_RCG_ENABLE = 0, 755 DMUB_IPS0_RCG_DISABLE = 1, 756 DMUB_IPS1_RCG_DISABLE = 2, 757 DMUB_IPS_RCG_DISABLE = 3 758 }; 759 760 #define DMUB_IPS1_ALLOW_MASK 0x00000001 761 #define DMUB_IPS2_ALLOW_MASK 0x00000002 762 #define DMUB_IPS1_COMMIT_MASK 0x00000004 763 #define DMUB_IPS2_COMMIT_MASK 0x00000008 764 765 /** 766 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 767 */ 768 union dmub_fw_boot_options { 769 struct { 770 uint32_t pemu_env : 1; /**< 1 if PEMU */ 771 uint32_t fpga_env : 1; /**< 1 if FPGA */ 772 uint32_t optimized_init : 1; /**< 1 if optimized init */ 773 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 774 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 775 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 776 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 777 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 778 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 779 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 780 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 781 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 782 uint32_t power_optimization: 1; 783 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 784 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 785 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 786 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 787 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 788 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 789 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 790 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 791 uint32_t ips_disable: 3; /* options to disable ips support*/ 792 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 793 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 794 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 795 uint32_t reserved : 6; /**< reserved */ 796 } bits; /**< boot bits */ 797 uint32_t all; /**< 32-bit access to bits */ 798 }; 799 800 enum dmub_fw_boot_options_bit { 801 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 802 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 803 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 804 }; 805 806 //============================================================================== 807 //< DMUB_SHARED_STATE>========================================================== 808 //============================================================================== 809 810 /** 811 * Shared firmware state between driver and firmware for lockless communication 812 * in situations where the inbox/outbox may be unavailable. 813 * 814 * Each structure *must* be at most 256-bytes in size. The layout allocation is 815 * described below: 816 * 817 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 818 */ 819 820 /** 821 * enum dmub_shared_state_feature_id - List of shared state features. 822 */ 823 enum dmub_shared_state_feature_id { 824 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 825 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 826 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 827 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 828 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 829 }; 830 831 /** 832 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 833 */ 834 union dmub_shared_state_ips_fw_signals { 835 struct { 836 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 837 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 838 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 839 uint32_t detection_required : 1; /**< 1 if detection is required */ 840 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 841 uint32_t reserved_bits : 27; /**< Reversed */ 842 } bits; 843 uint32_t all; 844 }; 845 846 /** 847 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 848 */ 849 union dmub_shared_state_ips_driver_signals { 850 struct { 851 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 852 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 853 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 854 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 855 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 856 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 857 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 858 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 859 uint32_t reserved_bits : 24; /**< Reversed bits */ 860 } bits; 861 uint32_t all; 862 }; 863 864 /** 865 * IPS FW Version 866 */ 867 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 868 869 struct dmub_shared_state_debug_setup { 870 union { 871 struct { 872 uint32_t exclude_points[62]; 873 } profile_mode; 874 }; 875 }; 876 877 /** 878 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 879 */ 880 struct dmub_shared_state_ips_fw { 881 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 882 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 883 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 884 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 885 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 886 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 887 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 888 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 889 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 890 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 891 }; /* 248-bytes, fixed */ 892 893 /** 894 * IPS Driver Version 895 */ 896 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 897 898 /** 899 * struct dmub_shared_state_ips_driver - Driver state for IPS. 900 */ 901 struct dmub_shared_state_ips_driver { 902 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 903 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 904 }; /* 248-bytes, fixed */ 905 906 /** 907 * enum dmub_shared_state_feature_common - Generic payload. 908 */ 909 struct dmub_shared_state_feature_common { 910 uint32_t padding[62]; 911 }; /* 248-bytes, fixed */ 912 913 /** 914 * enum dmub_shared_state_feature_header - Feature description. 915 */ 916 struct dmub_shared_state_feature_header { 917 uint16_t id; /**< Feature ID */ 918 uint16_t version; /**< Feature version */ 919 uint32_t reserved; /**< Reserved bytes. */ 920 }; /* 8 bytes, fixed */ 921 922 /** 923 * struct dmub_shared_state_feature_block - Feature block. 924 */ 925 struct dmub_shared_state_feature_block { 926 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 927 union dmub_shared_feature_state_union { 928 struct dmub_shared_state_feature_common common; /**< Generic data */ 929 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 930 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 931 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 932 } data; /**< Shared state data. */ 933 }; /* 256-bytes, fixed */ 934 935 /** 936 * Shared state size in bytes. 937 */ 938 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 939 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 940 941 //============================================================================== 942 //</DMUB_STATUS>================================================================ 943 //============================================================================== 944 //< DMUB_VBIOS>================================================================= 945 //============================================================================== 946 947 /* 948 * enum dmub_cmd_vbios_type - VBIOS commands. 949 * 950 * Command IDs should be treated as stable ABI. 951 * Do not reuse or modify IDs. 952 */ 953 enum dmub_cmd_vbios_type { 954 /** 955 * Configures the DIG encoder. 956 */ 957 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 958 /** 959 * Controls the PHY. 960 */ 961 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 962 /** 963 * Sets the pixel clock/symbol clock. 964 */ 965 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 966 /** 967 * Enables or disables power gating. 968 */ 969 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 970 /** 971 * Controls embedded panels. 972 */ 973 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 974 /** 975 * Query DP alt status on a transmitter. 976 */ 977 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 978 /** 979 * Control PHY FSM 980 */ 981 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 982 /** 983 * Controls domain power gating 984 */ 985 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 986 }; 987 988 //============================================================================== 989 //</DMUB_VBIOS>================================================================= 990 //============================================================================== 991 //< DMUB_GPINT>================================================================= 992 //============================================================================== 993 994 /** 995 * The shifts and masks below may alternatively be used to format and read 996 * the command register bits. 997 */ 998 999 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1000 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1001 1002 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1003 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1004 1005 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1006 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1007 1008 /** 1009 * Command responses. 1010 */ 1011 1012 /** 1013 * Return response for DMUB_GPINT__STOP_FW command. 1014 */ 1015 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1016 1017 /** 1018 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1019 */ 1020 union dmub_gpint_data_register { 1021 struct { 1022 uint32_t param : 16; /**< 16-bit parameter */ 1023 uint32_t command_code : 12; /**< GPINT command */ 1024 uint32_t status : 4; /**< Command status bit */ 1025 } bits; /**< GPINT bit access */ 1026 uint32_t all; /**< GPINT 32-bit access */ 1027 }; 1028 1029 /* 1030 * enum dmub_gpint_command - GPINT command to DMCUB FW 1031 * 1032 * Command IDs should be treated as stable ABI. 1033 * Do not reuse or modify IDs. 1034 */ 1035 enum dmub_gpint_command { 1036 /** 1037 * Invalid command, ignored. 1038 */ 1039 DMUB_GPINT__INVALID_COMMAND = 0, 1040 /** 1041 * DESC: Queries the firmware version. 1042 * RETURN: Firmware version. 1043 */ 1044 DMUB_GPINT__GET_FW_VERSION = 1, 1045 /** 1046 * DESC: Halts the firmware. 1047 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1048 */ 1049 DMUB_GPINT__STOP_FW = 2, 1050 /** 1051 * DESC: Get PSR state from FW. 1052 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1053 */ 1054 DMUB_GPINT__GET_PSR_STATE = 7, 1055 /** 1056 * DESC: Notifies DMCUB of the currently active streams. 1057 * ARGS: Stream mask, 1 bit per active stream index. 1058 */ 1059 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1060 /** 1061 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1062 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1063 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1064 * RETURN: PSR residency in milli-percent. 1065 */ 1066 DMUB_GPINT__PSR_RESIDENCY = 9, 1067 1068 /** 1069 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1070 */ 1071 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1072 1073 /** 1074 * DESC: Get REPLAY state from FW. 1075 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1076 */ 1077 DMUB_GPINT__GET_REPLAY_STATE = 13, 1078 1079 /** 1080 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1081 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1082 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1083 * RETURN: REPLAY residency in milli-percent. 1084 */ 1085 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1086 1087 /** 1088 * DESC: Copy bounding box to the host. 1089 * ARGS: Version of bounding box to copy 1090 * RETURN: Result of copying bounding box 1091 */ 1092 DMUB_GPINT__BB_COPY = 96, 1093 1094 /** 1095 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1096 * ARGS: The word3 for the 64 bit address 1097 */ 1098 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1099 1100 /** 1101 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1102 * ARGS: The word2 for the 64 bit address 1103 */ 1104 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1105 1106 /** 1107 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1108 * ARGS: The word1 for the 64 bit address 1109 */ 1110 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1111 1112 /** 1113 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1114 * ARGS: The word0 for the 64 bit address 1115 */ 1116 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1117 1118 /** 1119 * DESC: Updates the trace buffer lower 32-bit mask. 1120 * ARGS: The new mask 1121 * RETURN: Lower 32-bit mask. 1122 */ 1123 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1124 1125 /** 1126 * DESC: Updates the trace buffer mask bit0~bit15. 1127 * ARGS: The new mask 1128 * RETURN: Lower 32-bit mask. 1129 */ 1130 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1131 1132 /** 1133 * DESC: Updates the trace buffer mask bit16~bit31. 1134 * ARGS: The new mask 1135 * RETURN: Lower 32-bit mask. 1136 */ 1137 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1138 1139 /** 1140 * DESC: Updates the trace buffer mask bit32~bit47. 1141 * ARGS: The new mask 1142 * RETURN: Lower 32-bit mask. 1143 */ 1144 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1145 1146 /** 1147 * DESC: Updates the trace buffer mask bit48~bit63. 1148 * ARGS: The new mask 1149 * RETURN: Lower 32-bit mask. 1150 */ 1151 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1152 1153 /** 1154 * DESC: Read the trace buffer mask bi0~bit15. 1155 */ 1156 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1157 1158 /** 1159 * DESC: Read the trace buffer mask bit16~bit31. 1160 */ 1161 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1162 1163 /** 1164 * DESC: Read the trace buffer mask bi32~bit47. 1165 */ 1166 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1167 1168 /** 1169 * DESC: Updates the trace buffer mask bit32~bit63. 1170 */ 1171 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1172 1173 /** 1174 * DESC: Set IPS residency measurement 1175 * ARGS: 0 - Disable ips measurement 1176 * 1 - Enable ips measurement 1177 */ 1178 DMUB_GPINT__IPS_RESIDENCY = 121, 1179 1180 /** 1181 * DESC: Enable measurements for various task duration 1182 * ARGS: 0 - Disable measurement 1183 * 1 - Enable measurement 1184 */ 1185 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1186 1187 /** 1188 * DESC: Gets IPS residency in microseconds 1189 * ARGS: 0 - Return IPS1 residency 1190 * 1 - Return IPS2 residency 1191 * 2 - Return IPS1_RCG residency 1192 * 3 - Return IPS1_ONO2_ON residency 1193 * RETURN: Total residency in microseconds - lower 32 bits 1194 */ 1195 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1196 1197 /** 1198 * DESC: Gets IPS1 histogram counts 1199 * ARGS: Bucket index 1200 * RETURN: Total count for the bucket 1201 */ 1202 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1203 1204 /** 1205 * DESC: Gets IPS2 histogram counts 1206 * ARGS: Bucket index 1207 * RETURN: Total count for the bucket 1208 */ 1209 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1210 1211 /** 1212 * DESC: Gets IPS residency 1213 * ARGS: 0 - Return IPS1 residency 1214 * 1 - Return IPS2 residency 1215 * 2 - Return IPS1_RCG residency 1216 * 3 - Return IPS1_ONO2_ON residency 1217 * RETURN: Total residency in milli-percent. 1218 */ 1219 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1220 1221 /** 1222 * DESC: Gets IPS1_RCG histogram counts 1223 * ARGS: Bucket index 1224 * RETURN: Total count for the bucket 1225 */ 1226 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1227 1228 /** 1229 * DESC: Gets IPS1_ONO2_ON histogram counts 1230 * ARGS: Bucket index 1231 * RETURN: Total count for the bucket 1232 */ 1233 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1234 1235 /** 1236 * DESC: Gets IPS entry counter during residency measurement 1237 * ARGS: 0 - Return IPS1 entry counts 1238 * 1 - Return IPS2 entry counts 1239 * 2 - Return IPS1_RCG entry counts 1240 * 3 - Return IPS2_ONO2_ON entry counts 1241 * RETURN: Entry counter for selected IPS mode 1242 */ 1243 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1244 1245 /** 1246 * DESC: Gets IPS inactive residency in microseconds 1247 * ARGS: 0 - Return IPS1_MAX residency 1248 * 1 - Return IPS2 residency 1249 * 2 - Return IPS1_RCG residency 1250 * 3 - Return IPS1_ONO2_ON residency 1251 * RETURN: Total inactive residency in microseconds - lower 32 bits 1252 */ 1253 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1254 1255 /** 1256 * DESC: Gets IPS inactive residency in microseconds 1257 * ARGS: 0 - Return IPS1_MAX residency 1258 * 1 - Return IPS2 residency 1259 * 2 - Return IPS1_RCG residency 1260 * 3 - Return IPS1_ONO2_ON residency 1261 * RETURN: Total inactive residency in microseconds - upper 32 bits 1262 */ 1263 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1264 1265 /** 1266 * DESC: Gets IPS residency in microseconds 1267 * ARGS: 0 - Return IPS1 residency 1268 * 1 - Return IPS2 residency 1269 * 2 - Return IPS1_RCG residency 1270 * 3 - Return IPS1_ONO2_ON residency 1271 * RETURN: Total residency in microseconds - upper 32 bits 1272 */ 1273 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1274 /** 1275 * DESC: Setup debug configs. 1276 */ 1277 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1278 /** 1279 * DESC: Initiates IPS wake sequence. 1280 */ 1281 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1282 }; 1283 1284 /** 1285 * INBOX0 generic command definition 1286 */ 1287 union dmub_inbox0_cmd_common { 1288 struct { 1289 uint32_t command_code: 8; /**< INBOX0 command code */ 1290 uint32_t param: 24; /**< 24-bit parameter */ 1291 } bits; 1292 uint32_t all; 1293 }; 1294 1295 /** 1296 * INBOX0 hw_lock command definition 1297 */ 1298 union dmub_inbox0_cmd_lock_hw { 1299 struct { 1300 uint32_t command_code: 8; 1301 1302 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1303 uint32_t hw_lock_client: 2; 1304 1305 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1306 uint32_t otg_inst: 3; 1307 uint32_t opp_inst: 3; 1308 uint32_t dig_inst: 3; 1309 1310 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1311 uint32_t lock_pipe: 1; 1312 uint32_t lock_cursor: 1; 1313 uint32_t lock_dig: 1; 1314 uint32_t triple_buffer_lock: 1; 1315 1316 uint32_t lock: 1; /**< Lock */ 1317 uint32_t should_release: 1; /**< Release */ 1318 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1319 } bits; 1320 uint32_t all; 1321 }; 1322 1323 union dmub_inbox0_data_register { 1324 union dmub_inbox0_cmd_common inbox0_cmd_common; 1325 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1326 }; 1327 1328 enum dmub_inbox0_command { 1329 /** 1330 * DESC: Invalid command, ignored. 1331 */ 1332 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1333 /** 1334 * DESC: Notification to acquire/release HW lock 1335 * ARGS: 1336 */ 1337 DMUB_INBOX0_CMD__HW_LOCK = 1, 1338 }; 1339 //============================================================================== 1340 //</DMUB_GPINT>================================================================= 1341 //============================================================================== 1342 //< DMUB_CMD>=================================================================== 1343 //============================================================================== 1344 1345 /** 1346 * Size in bytes of each DMUB command. 1347 */ 1348 #define DMUB_RB_CMD_SIZE 64 1349 1350 /** 1351 * Maximum number of items in the DMUB ringbuffer. 1352 */ 1353 #define DMUB_RB_MAX_ENTRY 128 1354 1355 /** 1356 * Ringbuffer size in bytes. 1357 */ 1358 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1359 1360 /** 1361 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1362 */ 1363 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1364 1365 /** 1366 * Ringbuffer size in bytes. 1367 */ 1368 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1369 1370 /** 1371 * REG_SET mask for reg offload. 1372 */ 1373 #define REG_SET_MASK 0xFFFF 1374 1375 /* 1376 * enum dmub_cmd_type - DMUB inbox command. 1377 * 1378 * Command IDs should be treated as stable ABI. 1379 * Do not reuse or modify IDs. 1380 */ 1381 enum dmub_cmd_type { 1382 /** 1383 * Invalid command. 1384 */ 1385 DMUB_CMD__NULL = 0, 1386 /** 1387 * Read modify write register sequence offload. 1388 */ 1389 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1390 /** 1391 * Field update register sequence offload. 1392 */ 1393 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1394 /** 1395 * Burst write sequence offload. 1396 */ 1397 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1398 /** 1399 * Reg wait sequence offload. 1400 */ 1401 DMUB_CMD__REG_REG_WAIT = 4, 1402 /** 1403 * Workaround to avoid HUBP underflow during NV12 playback. 1404 */ 1405 DMUB_CMD__PLAT_54186_WA = 5, 1406 /** 1407 * Command type used to query FW feature caps. 1408 */ 1409 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1410 /** 1411 * Command type used to get visual confirm color. 1412 */ 1413 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1414 /** 1415 * Command type used for all PSR commands. 1416 */ 1417 DMUB_CMD__PSR = 64, 1418 /** 1419 * Command type used for all MALL commands. 1420 */ 1421 DMUB_CMD__MALL = 65, 1422 /** 1423 * Command type used for all ABM commands. 1424 */ 1425 DMUB_CMD__ABM = 66, 1426 /** 1427 * Command type used to update dirty rects in FW. 1428 */ 1429 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1430 /** 1431 * Command type used to update cursor info in FW. 1432 */ 1433 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1434 /** 1435 * Command type used for HW locking in FW. 1436 */ 1437 DMUB_CMD__HW_LOCK = 69, 1438 /** 1439 * Command type used to access DP AUX. 1440 */ 1441 DMUB_CMD__DP_AUX_ACCESS = 70, 1442 /** 1443 * Command type used for OUTBOX1 notification enable 1444 */ 1445 DMUB_CMD__OUTBOX1_ENABLE = 71, 1446 1447 /** 1448 * Command type used for all idle optimization commands. 1449 */ 1450 DMUB_CMD__IDLE_OPT = 72, 1451 /** 1452 * Command type used for all clock manager commands. 1453 */ 1454 DMUB_CMD__CLK_MGR = 73, 1455 /** 1456 * Command type used for all panel control commands. 1457 */ 1458 DMUB_CMD__PANEL_CNTL = 74, 1459 1460 /** 1461 * Command type used for all CAB commands. 1462 */ 1463 DMUB_CMD__CAB_FOR_SS = 75, 1464 1465 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1466 1467 /** 1468 * Command type used for interfacing with DPIA. 1469 */ 1470 DMUB_CMD__DPIA = 77, 1471 /** 1472 * Command type used for EDID CEA parsing 1473 */ 1474 DMUB_CMD__EDID_CEA = 79, 1475 /** 1476 * Command type used for getting usbc cable ID 1477 */ 1478 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1479 /** 1480 * Command type used to query HPD state. 1481 */ 1482 DMUB_CMD__QUERY_HPD_STATE = 82, 1483 /** 1484 * Command type used for all VBIOS interface commands. 1485 */ 1486 /** 1487 * Command type used for all REPLAY commands. 1488 */ 1489 DMUB_CMD__REPLAY = 83, 1490 1491 /** 1492 * Command type used for all SECURE_DISPLAY commands. 1493 */ 1494 DMUB_CMD__SECURE_DISPLAY = 85, 1495 1496 /** 1497 * Command type used to set DPIA HPD interrupt state 1498 */ 1499 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1500 1501 /** 1502 * Command type used for all PSP commands. 1503 */ 1504 DMUB_CMD__PSP = 88, 1505 1506 /** 1507 * Command type used for all Fused IO commands. 1508 */ 1509 DMUB_CMD__FUSED_IO = 89, 1510 1511 DMUB_CMD__VBIOS = 128, 1512 }; 1513 1514 /** 1515 * enum dmub_out_cmd_type - DMUB outbox commands. 1516 */ 1517 enum dmub_out_cmd_type { 1518 /** 1519 * Invalid outbox command, ignored. 1520 */ 1521 DMUB_OUT_CMD__NULL = 0, 1522 /** 1523 * Command type used for DP AUX Reply data notification 1524 */ 1525 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1526 /** 1527 * Command type used for DP HPD event notification 1528 */ 1529 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1530 /** 1531 * Command type used for SET_CONFIG Reply notification 1532 */ 1533 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1534 /** 1535 * Command type used for USB4 DPIA notification 1536 */ 1537 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1538 /** 1539 * Command type used for HPD redetect notification 1540 */ 1541 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1542 /** 1543 * Command type used for Fused IO notification 1544 */ 1545 DMUB_OUT_CMD__FUSED_IO = 7, 1546 }; 1547 1548 /* DMUB_CMD__DPIA command sub-types. */ 1549 enum dmub_cmd_dpia_type { 1550 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1551 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1552 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1553 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1554 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1555 }; 1556 1557 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1558 enum dmub_cmd_dpia_notification_type { 1559 DPIA_NOTIFY__BW_ALLOCATION = 0, 1560 }; 1561 1562 #pragma pack(push, 1) 1563 1564 /** 1565 * struct dmub_cmd_header - Common command header fields. 1566 */ 1567 struct dmub_cmd_header { 1568 unsigned int type : 8; /**< command type */ 1569 unsigned int sub_type : 8; /**< command sub type */ 1570 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1571 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1572 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1573 unsigned int reserved0 : 5; /**< reserved bits */ 1574 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1575 unsigned int reserved1 : 2; /**< reserved bits */ 1576 }; 1577 1578 /* 1579 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1580 * 1581 * 60 payload bytes can hold up to 5 sets of read modify writes, 1582 * each take 3 dwords. 1583 * 1584 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1585 * 1586 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1587 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1588 */ 1589 struct dmub_cmd_read_modify_write_sequence { 1590 uint32_t addr; /**< register address */ 1591 uint32_t modify_mask; /**< modify mask */ 1592 uint32_t modify_value; /**< modify value */ 1593 }; 1594 1595 /** 1596 * Maximum number of ops in read modify write sequence. 1597 */ 1598 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1599 1600 /** 1601 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1602 */ 1603 struct dmub_rb_cmd_read_modify_write { 1604 struct dmub_cmd_header header; /**< command header */ 1605 /** 1606 * Read modify write sequence. 1607 */ 1608 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1609 }; 1610 1611 /* 1612 * Update a register with specified masks and values sequeunce 1613 * 1614 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1615 * 1616 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1617 * 1618 * 1619 * USE CASE: 1620 * 1. auto-increment register where additional read would update pointer and produce wrong result 1621 * 2. toggle a bit without read in the middle 1622 */ 1623 1624 struct dmub_cmd_reg_field_update_sequence { 1625 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1626 uint32_t modify_value; /**< value to update with */ 1627 }; 1628 1629 /** 1630 * Maximum number of ops in field update sequence. 1631 */ 1632 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1633 1634 /** 1635 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1636 */ 1637 struct dmub_rb_cmd_reg_field_update_sequence { 1638 struct dmub_cmd_header header; /**< command header */ 1639 uint32_t addr; /**< register address */ 1640 /** 1641 * Field update sequence. 1642 */ 1643 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1644 }; 1645 1646 1647 /** 1648 * Maximum number of burst write values. 1649 */ 1650 #define DMUB_BURST_WRITE_VALUES__MAX 14 1651 1652 /* 1653 * struct dmub_rb_cmd_burst_write - Burst write 1654 * 1655 * support use case such as writing out LUTs. 1656 * 1657 * 60 payload bytes can hold up to 14 values to write to given address 1658 * 1659 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1660 */ 1661 struct dmub_rb_cmd_burst_write { 1662 struct dmub_cmd_header header; /**< command header */ 1663 uint32_t addr; /**< register start address */ 1664 /** 1665 * Burst write register values. 1666 */ 1667 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1668 }; 1669 1670 /** 1671 * struct dmub_rb_cmd_common - Common command header 1672 */ 1673 struct dmub_rb_cmd_common { 1674 struct dmub_cmd_header header; /**< command header */ 1675 /** 1676 * Padding to RB_CMD_SIZE 1677 */ 1678 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1679 }; 1680 1681 /** 1682 * struct dmub_cmd_reg_wait_data - Register wait data 1683 */ 1684 struct dmub_cmd_reg_wait_data { 1685 uint32_t addr; /**< Register address */ 1686 uint32_t mask; /**< Mask for register bits */ 1687 uint32_t condition_field_value; /**< Value to wait for */ 1688 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1689 }; 1690 1691 /** 1692 * struct dmub_rb_cmd_reg_wait - Register wait command 1693 */ 1694 struct dmub_rb_cmd_reg_wait { 1695 struct dmub_cmd_header header; /**< Command header */ 1696 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1697 }; 1698 1699 /** 1700 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1701 * 1702 * Reprograms surface parameters to avoid underflow. 1703 */ 1704 struct dmub_cmd_PLAT_54186_wa { 1705 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1706 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1707 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1708 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1709 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1710 struct { 1711 uint32_t hubp_inst : 4; /**< HUBP instance */ 1712 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1713 uint32_t immediate :1; /**< Immediate flip */ 1714 uint32_t vmid : 4; /**< VMID */ 1715 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1716 uint32_t reserved : 21; /**< Reserved */ 1717 } flip_params; /**< Pageflip parameters */ 1718 uint32_t reserved[9]; /**< Reserved bits */ 1719 }; 1720 1721 /** 1722 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1723 */ 1724 struct dmub_rb_cmd_PLAT_54186_wa { 1725 struct dmub_cmd_header header; /**< Command header */ 1726 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1727 }; 1728 1729 /** 1730 * enum dmub_cmd_mall_type - MALL commands 1731 */ 1732 enum dmub_cmd_mall_type { 1733 /** 1734 * Allows display refresh from MALL. 1735 */ 1736 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1737 /** 1738 * Disallows display refresh from MALL. 1739 */ 1740 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1741 /** 1742 * Cursor copy for MALL. 1743 */ 1744 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1745 /** 1746 * Controls DF requests. 1747 */ 1748 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1749 }; 1750 1751 /** 1752 * struct dmub_rb_cmd_mall - MALL command data. 1753 */ 1754 struct dmub_rb_cmd_mall { 1755 struct dmub_cmd_header header; /**< Common command header */ 1756 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1757 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1758 uint32_t tmr_delay; /**< Timer delay */ 1759 uint32_t tmr_scale; /**< Timer scale */ 1760 uint16_t cursor_width; /**< Cursor width in pixels */ 1761 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1762 uint16_t cursor_height; /**< Cursor height in pixels */ 1763 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1764 uint8_t debug_bits; /**< Debug bits */ 1765 1766 uint8_t reserved1; /**< Reserved bits */ 1767 uint8_t reserved2; /**< Reserved bits */ 1768 }; 1769 1770 /** 1771 * enum dmub_cmd_cab_type - CAB command data. 1772 */ 1773 enum dmub_cmd_cab_type { 1774 /** 1775 * No idle optimizations (i.e. no CAB) 1776 */ 1777 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1778 /** 1779 * No DCN requests for memory 1780 */ 1781 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1782 /** 1783 * Fit surfaces in CAB (i.e. CAB enable) 1784 */ 1785 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1786 /** 1787 * Do not fit surfaces in CAB (i.e. no CAB) 1788 */ 1789 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1790 }; 1791 1792 /** 1793 * struct dmub_rb_cmd_cab - CAB command data. 1794 */ 1795 struct dmub_rb_cmd_cab_for_ss { 1796 struct dmub_cmd_header header; 1797 uint8_t cab_alloc_ways; /* total number of ways */ 1798 uint8_t debug_bits; /* debug bits */ 1799 }; 1800 1801 /** 1802 * Enum for indicating which MCLK switch mode per pipe 1803 */ 1804 enum mclk_switch_mode { 1805 NONE = 0, 1806 FPO = 1, 1807 SUBVP = 2, 1808 VBLANK = 3, 1809 }; 1810 1811 /* Per pipe struct which stores the MCLK switch mode 1812 * data to be sent to DMUB. 1813 * Named "v2" for now -- once FPO and SUBVP are fully merged 1814 * the type name can be updated 1815 */ 1816 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1817 union { 1818 struct { 1819 uint32_t pix_clk_100hz; 1820 uint16_t main_vblank_start; 1821 uint16_t main_vblank_end; 1822 uint16_t mall_region_lines; 1823 uint16_t prefetch_lines; 1824 uint16_t prefetch_to_mall_start_lines; 1825 uint16_t processing_delay_lines; 1826 uint16_t htotal; // required to calculate line time for multi-display cases 1827 uint16_t vtotal; 1828 uint8_t main_pipe_index; 1829 uint8_t phantom_pipe_index; 1830 /* Since the microschedule is calculated in terms of OTG lines, 1831 * include any scaling factors to make sure when we get accurate 1832 * conversion when programming MALL_START_LINE (which is in terms 1833 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1834 * is 1/2 (numerator = 1, denominator = 2). 1835 */ 1836 uint8_t scale_factor_numerator; 1837 uint8_t scale_factor_denominator; 1838 uint8_t is_drr; 1839 uint8_t main_split_pipe_index; 1840 uint8_t phantom_split_pipe_index; 1841 } subvp_data; 1842 1843 struct { 1844 uint32_t pix_clk_100hz; 1845 uint16_t vblank_start; 1846 uint16_t vblank_end; 1847 uint16_t vstartup_start; 1848 uint16_t vtotal; 1849 uint16_t htotal; 1850 uint8_t vblank_pipe_index; 1851 uint8_t padding[1]; 1852 struct { 1853 uint8_t drr_in_use; 1854 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1855 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1856 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1857 uint8_t use_ramping; // Use ramping or not 1858 uint8_t drr_vblank_start_margin; 1859 } drr_info; // DRR considered as part of SubVP + VBLANK case 1860 } vblank_data; 1861 } pipe_config; 1862 1863 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1864 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1865 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1866 */ 1867 uint8_t mode; // enum mclk_switch_mode 1868 }; 1869 1870 /** 1871 * Config data for Sub-VP and FPO 1872 * Named "v2" for now -- once FPO and SUBVP are fully merged 1873 * the type name can be updated 1874 */ 1875 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1876 uint16_t watermark_a_cache; 1877 uint8_t vertical_int_margin_us; 1878 uint8_t pstate_allow_width_us; 1879 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1880 }; 1881 1882 /** 1883 * DMUB rb command definition for Sub-VP and FPO 1884 * Named "v2" for now -- once FPO and SUBVP are fully merged 1885 * the type name can be updated 1886 */ 1887 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1888 struct dmub_cmd_header header; 1889 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1890 }; 1891 1892 struct dmub_flip_addr_info { 1893 uint32_t surf_addr_lo; 1894 uint32_t surf_addr_c_lo; 1895 uint32_t meta_addr_lo; 1896 uint32_t meta_addr_c_lo; 1897 uint16_t surf_addr_hi; 1898 uint16_t surf_addr_c_hi; 1899 uint16_t meta_addr_hi; 1900 uint16_t meta_addr_c_hi; 1901 }; 1902 1903 struct dmub_fams2_flip_info { 1904 union { 1905 struct { 1906 uint8_t is_immediate: 1; 1907 } bits; 1908 uint8_t all; 1909 } config; 1910 uint8_t otg_inst; 1911 uint8_t pipe_mask; 1912 uint8_t pad; 1913 struct dmub_flip_addr_info addr_info; 1914 }; 1915 1916 struct dmub_rb_cmd_fams2_flip { 1917 struct dmub_cmd_header header; 1918 struct dmub_fams2_flip_info flip_info; 1919 }; 1920 1921 struct dmub_optc_state_v2 { 1922 uint32_t v_total_min; 1923 uint32_t v_total_max; 1924 uint32_t v_total_mid; 1925 uint32_t v_total_mid_frame_num; 1926 uint8_t program_manual_trigger; 1927 uint8_t tg_inst; 1928 uint8_t pad[2]; 1929 }; 1930 1931 struct dmub_optc_position { 1932 uint32_t vpos; 1933 uint32_t hpos; 1934 uint32_t frame; 1935 }; 1936 1937 struct dmub_rb_cmd_fams2_drr_update { 1938 struct dmub_cmd_header header; 1939 struct dmub_optc_state_v2 dmub_optc_state_req; 1940 }; 1941 1942 /* HW and FW global configuration data for FAMS2 */ 1943 /* FAMS2 types and structs */ 1944 enum fams2_stream_type { 1945 FAMS2_STREAM_TYPE_NONE = 0, 1946 FAMS2_STREAM_TYPE_VBLANK = 1, 1947 FAMS2_STREAM_TYPE_VACTIVE = 2, 1948 FAMS2_STREAM_TYPE_DRR = 3, 1949 FAMS2_STREAM_TYPE_SUBVP = 4, 1950 }; 1951 1952 /* static stream state */ 1953 struct dmub_fams2_legacy_stream_static_state { 1954 uint8_t vactive_det_fill_delay_otg_vlines; 1955 uint8_t programming_delay_otg_vlines; 1956 }; //v0 1957 1958 struct dmub_fams2_subvp_stream_static_state { 1959 uint16_t vratio_numerator; 1960 uint16_t vratio_denominator; 1961 uint16_t phantom_vtotal; 1962 uint16_t phantom_vactive; 1963 union { 1964 struct { 1965 uint8_t is_multi_planar : 1; 1966 uint8_t is_yuv420 : 1; 1967 } bits; 1968 uint8_t all; 1969 } config; 1970 uint8_t programming_delay_otg_vlines; 1971 uint8_t prefetch_to_mall_otg_vlines; 1972 uint8_t phantom_otg_inst; 1973 uint8_t phantom_pipe_mask; 1974 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1975 }; //v0 1976 1977 struct dmub_fams2_drr_stream_static_state { 1978 uint16_t nom_stretched_vtotal; 1979 uint8_t programming_delay_otg_vlines; 1980 uint8_t only_stretch_if_required; 1981 uint8_t pad[2]; 1982 }; //v0 1983 1984 struct dmub_fams2_cmd_legacy_stream_static_state { 1985 uint16_t vactive_det_fill_delay_otg_vlines; 1986 uint16_t programming_delay_otg_vlines; 1987 }; //v1 1988 1989 struct dmub_fams2_cmd_subvp_stream_static_state { 1990 uint16_t vratio_numerator; 1991 uint16_t vratio_denominator; 1992 uint16_t phantom_vtotal; 1993 uint16_t phantom_vactive; 1994 uint16_t programming_delay_otg_vlines; 1995 uint16_t prefetch_to_mall_otg_vlines; 1996 union { 1997 struct { 1998 uint8_t is_multi_planar : 1; 1999 uint8_t is_yuv420 : 1; 2000 } bits; 2001 uint8_t all; 2002 } config; 2003 uint8_t phantom_otg_inst; 2004 uint8_t phantom_pipe_mask; 2005 uint8_t pad0; 2006 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2007 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2008 }; //v1 2009 2010 struct dmub_fams2_cmd_drr_stream_static_state { 2011 uint16_t nom_stretched_vtotal; 2012 uint16_t programming_delay_otg_vlines; 2013 uint8_t only_stretch_if_required; 2014 uint8_t pad[3]; 2015 }; //v1 2016 2017 union dmub_fams2_stream_static_sub_state { 2018 struct dmub_fams2_legacy_stream_static_state legacy; 2019 struct dmub_fams2_subvp_stream_static_state subvp; 2020 struct dmub_fams2_drr_stream_static_state drr; 2021 }; //v0 2022 2023 union dmub_fams2_cmd_stream_static_sub_state { 2024 struct dmub_fams2_cmd_legacy_stream_static_state legacy; 2025 struct dmub_fams2_cmd_subvp_stream_static_state subvp; 2026 struct dmub_fams2_cmd_drr_stream_static_state drr; 2027 }; //v1 2028 2029 struct dmub_fams2_stream_static_state { 2030 enum fams2_stream_type type; 2031 uint32_t otg_vline_time_ns; 2032 uint32_t otg_vline_time_ticks; 2033 uint16_t htotal; 2034 uint16_t vtotal; // nominal vtotal 2035 uint16_t vblank_start; 2036 uint16_t vblank_end; 2037 uint16_t max_vtotal; 2038 uint16_t allow_start_otg_vline; 2039 uint16_t allow_end_otg_vline; 2040 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2041 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2042 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2043 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2044 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2045 union { 2046 struct { 2047 uint8_t is_drr: 1; // stream is DRR enabled 2048 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2049 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2050 } bits; 2051 uint8_t all; 2052 } config; 2053 uint8_t otg_inst; 2054 uint8_t pipe_mask; // pipe mask for the whole config 2055 uint8_t num_planes; 2056 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2057 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2058 union dmub_fams2_stream_static_sub_state sub_state; 2059 }; //v0 2060 2061 struct dmub_fams2_cmd_stream_static_base_state { 2062 enum fams2_stream_type type; 2063 uint32_t otg_vline_time_ns; 2064 uint32_t otg_vline_time_ticks; 2065 uint16_t htotal; 2066 uint16_t vtotal; // nominal vtotal 2067 uint16_t vblank_start; 2068 uint16_t vblank_end; 2069 uint16_t max_vtotal; 2070 uint16_t allow_start_otg_vline; 2071 uint16_t allow_end_otg_vline; 2072 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2073 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2074 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2075 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2076 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2077 union { 2078 struct { 2079 uint8_t is_drr : 1; // stream is DRR enabled 2080 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2081 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2082 } bits; 2083 uint8_t all; 2084 } config; 2085 uint8_t otg_inst; 2086 uint8_t pipe_mask; // pipe mask for the whole config 2087 uint8_t num_planes; 2088 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2089 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2090 }; //v1 2091 2092 struct dmub_fams2_stream_static_state_v1 { 2093 struct dmub_fams2_cmd_stream_static_base_state base; 2094 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2095 }; //v1 2096 2097 /** 2098 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2099 * p-state request to allow latency 2100 */ 2101 enum dmub_fams2_allow_delay_check_mode { 2102 /* No check for request to allow delay */ 2103 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2104 /* Check for request to allow delay */ 2105 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2106 /* Check for prepare to allow delay */ 2107 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2108 }; 2109 2110 union dmub_fams2_global_feature_config { 2111 struct { 2112 uint32_t enable: 1; 2113 uint32_t enable_ppt_check: 1; 2114 uint32_t enable_stall_recovery: 1; 2115 uint32_t enable_debug: 1; 2116 uint32_t enable_offload_flip: 1; 2117 uint32_t enable_visual_confirm: 1; 2118 uint32_t allow_delay_check_mode: 2; 2119 uint32_t reserved: 24; 2120 } bits; 2121 uint32_t all; 2122 }; 2123 2124 struct dmub_cmd_fams2_global_config { 2125 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2126 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2127 uint32_t num_streams; 2128 union dmub_fams2_global_feature_config features; 2129 uint32_t recovery_timeout_us; 2130 uint32_t hwfq_flip_programming_delay_us; 2131 }; 2132 2133 union dmub_cmd_fams2_config { 2134 struct dmub_cmd_fams2_global_config global; 2135 struct dmub_fams2_stream_static_state stream; //v0 2136 union { 2137 struct dmub_fams2_cmd_stream_static_base_state base; 2138 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2139 } stream_v1; //v1 2140 }; 2141 2142 /** 2143 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2144 */ 2145 struct dmub_rb_cmd_fams2 { 2146 struct dmub_cmd_header header; 2147 union dmub_cmd_fams2_config config; 2148 }; 2149 2150 /** 2151 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2152 */ 2153 enum dmub_cmd_idle_opt_type { 2154 /** 2155 * DCN hardware restore. 2156 */ 2157 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2158 2159 /** 2160 * DCN hardware save. 2161 */ 2162 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2163 2164 /** 2165 * DCN hardware notify idle. 2166 */ 2167 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2168 2169 /** 2170 * DCN hardware notify power state. 2171 */ 2172 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2173 }; 2174 2175 /** 2176 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2177 */ 2178 struct dmub_rb_cmd_idle_opt_dcn_restore { 2179 struct dmub_cmd_header header; /**< header */ 2180 }; 2181 2182 /** 2183 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2184 */ 2185 struct dmub_dcn_notify_idle_cntl_data { 2186 uint8_t driver_idle; 2187 uint8_t skip_otg_disable; 2188 uint8_t reserved[58]; 2189 }; 2190 2191 /** 2192 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2193 */ 2194 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2195 struct dmub_cmd_header header; /**< header */ 2196 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2197 }; 2198 2199 /** 2200 * enum dmub_idle_opt_dc_power_state - DC power states. 2201 */ 2202 enum dmub_idle_opt_dc_power_state { 2203 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2204 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2205 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2206 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2207 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2208 }; 2209 2210 /** 2211 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2212 */ 2213 struct dmub_idle_opt_set_dc_power_state_data { 2214 uint8_t power_state; /**< power state */ 2215 uint8_t pad[3]; /**< padding */ 2216 }; 2217 2218 /** 2219 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2220 */ 2221 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2222 struct dmub_cmd_header header; /**< header */ 2223 struct dmub_idle_opt_set_dc_power_state_data data; 2224 }; 2225 2226 /** 2227 * struct dmub_clocks - Clock update notification. 2228 */ 2229 struct dmub_clocks { 2230 uint32_t dispclk_khz; /**< dispclk kHz */ 2231 uint32_t dppclk_khz; /**< dppclk kHz */ 2232 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2233 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2234 }; 2235 2236 /** 2237 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2238 */ 2239 enum dmub_cmd_clk_mgr_type { 2240 /** 2241 * Notify DMCUB of clock update. 2242 */ 2243 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2244 }; 2245 2246 /** 2247 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2248 */ 2249 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2250 struct dmub_cmd_header header; /**< header */ 2251 struct dmub_clocks clocks; /**< clock data */ 2252 }; 2253 2254 /** 2255 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2256 */ 2257 struct dmub_cmd_digx_encoder_control_data { 2258 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2259 }; 2260 2261 /** 2262 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2263 */ 2264 struct dmub_rb_cmd_digx_encoder_control { 2265 struct dmub_cmd_header header; /**< header */ 2266 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2267 }; 2268 2269 /** 2270 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2271 */ 2272 struct dmub_cmd_set_pixel_clock_data { 2273 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2274 }; 2275 2276 /** 2277 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2278 */ 2279 struct dmub_rb_cmd_set_pixel_clock { 2280 struct dmub_cmd_header header; /**< header */ 2281 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2282 }; 2283 2284 /** 2285 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2286 */ 2287 struct dmub_cmd_enable_disp_power_gating_data { 2288 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2289 }; 2290 2291 /** 2292 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2293 */ 2294 struct dmub_rb_cmd_enable_disp_power_gating { 2295 struct dmub_cmd_header header; /**< header */ 2296 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2297 }; 2298 2299 /** 2300 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2301 */ 2302 struct dmub_dig_transmitter_control_data_v1_7 { 2303 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2304 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2305 union { 2306 uint8_t digmode; /**< enum atom_encode_mode_def */ 2307 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2308 } mode_laneset; 2309 uint8_t lanenum; /**< Number of lanes */ 2310 union { 2311 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2312 } symclk_units; 2313 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2314 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2315 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2316 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2317 uint8_t reserved1; /**< For future use */ 2318 uint8_t reserved2[3]; /**< For future use */ 2319 uint32_t reserved3[11]; /**< For future use */ 2320 }; 2321 2322 /** 2323 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2324 */ 2325 union dmub_cmd_dig1_transmitter_control_data { 2326 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2327 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2328 }; 2329 2330 /** 2331 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2332 */ 2333 struct dmub_rb_cmd_dig1_transmitter_control { 2334 struct dmub_cmd_header header; /**< header */ 2335 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2336 }; 2337 2338 /** 2339 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2340 */ 2341 struct dmub_rb_cmd_domain_control_data { 2342 uint8_t inst : 6; /**< DOMAIN instance to control */ 2343 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2344 uint8_t reserved[3]; /**< Reserved for future use */ 2345 }; 2346 2347 /** 2348 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2349 */ 2350 struct dmub_rb_cmd_domain_control { 2351 struct dmub_cmd_header header; /**< header */ 2352 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2353 }; 2354 2355 /** 2356 * DPIA tunnel command parameters. 2357 */ 2358 struct dmub_cmd_dig_dpia_control_data { 2359 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2360 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2361 union { 2362 uint8_t digmode; /** enum atom_encode_mode_def */ 2363 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2364 } mode_laneset; 2365 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2366 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2367 uint8_t hpdsel; /** =0: HPD is not assigned */ 2368 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2369 uint8_t dpia_id; /** Index of DPIA */ 2370 uint8_t fec_rdy : 1; 2371 uint8_t reserved : 7; 2372 uint32_t reserved1; 2373 }; 2374 2375 /** 2376 * DMUB command for DPIA tunnel control. 2377 */ 2378 struct dmub_rb_cmd_dig1_dpia_control { 2379 struct dmub_cmd_header header; 2380 struct dmub_cmd_dig_dpia_control_data dpia_control; 2381 }; 2382 2383 /** 2384 * SET_CONFIG Command Payload (deprecated) 2385 */ 2386 struct set_config_cmd_payload { 2387 uint8_t msg_type; /* set config message type */ 2388 uint8_t msg_data; /* set config message data */ 2389 }; 2390 2391 /** 2392 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2393 */ 2394 struct dmub_cmd_set_config_control_data { 2395 struct set_config_cmd_payload cmd_pkt; 2396 uint8_t instance; /* DPIA instance */ 2397 uint8_t immed_status; /* Immediate status returned in case of error */ 2398 }; 2399 2400 /** 2401 * SET_CONFIG Request Command Payload 2402 */ 2403 struct set_config_request_cmd_payload { 2404 uint8_t instance; /* DPIA instance */ 2405 uint8_t immed_status; /* Immediate status returned in case of error */ 2406 uint8_t msg_type; /* set config message type */ 2407 uint8_t reserved; 2408 uint32_t msg_data; /* set config message data */ 2409 }; 2410 2411 /** 2412 * DMUB command structure for SET_CONFIG command. 2413 */ 2414 struct dmub_rb_cmd_set_config_access { 2415 struct dmub_cmd_header header; /* header */ 2416 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2417 }; 2418 2419 /** 2420 * DMUB command structure for SET_CONFIG request command. 2421 */ 2422 struct dmub_rb_cmd_set_config_request { 2423 struct dmub_cmd_header header; /* header */ 2424 struct set_config_request_cmd_payload payload; /* set config request payload */ 2425 }; 2426 2427 /** 2428 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2429 */ 2430 struct dmub_cmd_mst_alloc_slots_control_data { 2431 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2432 uint8_t instance; /* DPIA instance */ 2433 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2434 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2435 }; 2436 2437 /** 2438 * DMUB command structure for SET_ command. 2439 */ 2440 struct dmub_rb_cmd_set_mst_alloc_slots { 2441 struct dmub_cmd_header header; /* header */ 2442 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2443 }; 2444 2445 /** 2446 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2447 */ 2448 struct dmub_cmd_tps_notification_data { 2449 uint8_t instance; /* DPIA instance */ 2450 uint8_t tps; /* requested training pattern */ 2451 uint8_t reserved1; 2452 uint8_t reserved2; 2453 }; 2454 2455 /** 2456 * DMUB command structure for SET_TPS_NOTIFICATION command. 2457 */ 2458 struct dmub_rb_cmd_set_tps_notification { 2459 struct dmub_cmd_header header; /* header */ 2460 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2461 }; 2462 2463 /** 2464 * DMUB command structure for DPIA HPD int enable control. 2465 */ 2466 struct dmub_rb_cmd_dpia_hpd_int_enable { 2467 struct dmub_cmd_header header; /* header */ 2468 uint32_t enable; /* dpia hpd interrupt enable */ 2469 }; 2470 2471 /** 2472 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2473 */ 2474 struct dmub_rb_cmd_dpphy_init { 2475 struct dmub_cmd_header header; /**< header */ 2476 uint8_t reserved[60]; /**< reserved bits */ 2477 }; 2478 2479 /** 2480 * enum dp_aux_request_action - DP AUX request command listing. 2481 * 2482 * 4 AUX request command bits are shifted to high nibble. 2483 */ 2484 enum dp_aux_request_action { 2485 /** I2C-over-AUX write request */ 2486 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2487 /** I2C-over-AUX read request */ 2488 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2489 /** I2C-over-AUX write status request */ 2490 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2491 /** I2C-over-AUX write request with MOT=1 */ 2492 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2493 /** I2C-over-AUX read request with MOT=1 */ 2494 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2495 /** I2C-over-AUX write status request with MOT=1 */ 2496 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2497 /** Native AUX write request */ 2498 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2499 /** Native AUX read request */ 2500 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2501 }; 2502 2503 /** 2504 * enum aux_return_code_type - DP AUX process return code listing. 2505 */ 2506 enum aux_return_code_type { 2507 /** AUX process succeeded */ 2508 AUX_RET_SUCCESS = 0, 2509 /** AUX process failed with unknown reason */ 2510 AUX_RET_ERROR_UNKNOWN, 2511 /** AUX process completed with invalid reply */ 2512 AUX_RET_ERROR_INVALID_REPLY, 2513 /** AUX process timed out */ 2514 AUX_RET_ERROR_TIMEOUT, 2515 /** HPD was low during AUX process */ 2516 AUX_RET_ERROR_HPD_DISCON, 2517 /** Failed to acquire AUX engine */ 2518 AUX_RET_ERROR_ENGINE_ACQUIRE, 2519 /** AUX request not supported */ 2520 AUX_RET_ERROR_INVALID_OPERATION, 2521 /** AUX process not available */ 2522 AUX_RET_ERROR_PROTOCOL_ERROR, 2523 }; 2524 2525 /** 2526 * enum aux_channel_type - DP AUX channel type listing. 2527 */ 2528 enum aux_channel_type { 2529 /** AUX thru Legacy DP AUX */ 2530 AUX_CHANNEL_LEGACY_DDC, 2531 /** AUX thru DPIA DP tunneling */ 2532 AUX_CHANNEL_DPIA 2533 }; 2534 2535 /** 2536 * struct aux_transaction_parameters - DP AUX request transaction data 2537 */ 2538 struct aux_transaction_parameters { 2539 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2540 uint8_t action; /**< enum dp_aux_request_action */ 2541 uint8_t length; /**< DP AUX request data length */ 2542 uint8_t reserved; /**< For future use */ 2543 uint32_t address; /**< DP AUX address */ 2544 uint8_t data[16]; /**< DP AUX write data */ 2545 }; 2546 2547 /** 2548 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2549 */ 2550 struct dmub_cmd_dp_aux_control_data { 2551 uint8_t instance; /**< AUX instance or DPIA instance */ 2552 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2553 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2554 uint8_t reserved0; /**< For future use */ 2555 uint16_t timeout; /**< timeout time in us */ 2556 uint16_t reserved1; /**< For future use */ 2557 enum aux_channel_type type; /**< enum aux_channel_type */ 2558 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2559 }; 2560 2561 /** 2562 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2563 */ 2564 struct dmub_rb_cmd_dp_aux_access { 2565 /** 2566 * Command header. 2567 */ 2568 struct dmub_cmd_header header; 2569 /** 2570 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2571 */ 2572 struct dmub_cmd_dp_aux_control_data aux_control; 2573 }; 2574 2575 /** 2576 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2577 */ 2578 struct dmub_rb_cmd_outbox1_enable { 2579 /** 2580 * Command header. 2581 */ 2582 struct dmub_cmd_header header; 2583 /** 2584 * enable: 0x0 -> disable outbox1 notification (default value) 2585 * 0x1 -> enable outbox1 notification 2586 */ 2587 uint32_t enable; 2588 }; 2589 2590 /* DP AUX Reply command - OutBox Cmd */ 2591 /** 2592 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2593 */ 2594 struct aux_reply_data { 2595 /** 2596 * Aux cmd 2597 */ 2598 uint8_t command; 2599 /** 2600 * Aux reply data length (max: 16 bytes) 2601 */ 2602 uint8_t length; 2603 /** 2604 * Alignment only 2605 */ 2606 uint8_t pad[2]; 2607 /** 2608 * Aux reply data 2609 */ 2610 uint8_t data[16]; 2611 }; 2612 2613 /** 2614 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2615 */ 2616 struct aux_reply_control_data { 2617 /** 2618 * Reserved for future use 2619 */ 2620 uint32_t handle; 2621 /** 2622 * Aux Instance 2623 */ 2624 uint8_t instance; 2625 /** 2626 * Aux transaction result: definition in enum aux_return_code_type 2627 */ 2628 uint8_t result; 2629 /** 2630 * Alignment only 2631 */ 2632 uint16_t pad; 2633 }; 2634 2635 /** 2636 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2637 */ 2638 struct dmub_rb_cmd_dp_aux_reply { 2639 /** 2640 * Command header. 2641 */ 2642 struct dmub_cmd_header header; 2643 /** 2644 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2645 */ 2646 struct aux_reply_control_data control; 2647 /** 2648 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2649 */ 2650 struct aux_reply_data reply_data; 2651 }; 2652 2653 /* DP HPD Notify command - OutBox Cmd */ 2654 /** 2655 * DP HPD Type 2656 */ 2657 enum dp_hpd_type { 2658 /** 2659 * Normal DP HPD 2660 */ 2661 DP_HPD = 0, 2662 /** 2663 * DP HPD short pulse 2664 */ 2665 DP_IRQ = 1, 2666 /** 2667 * Failure to acquire DP HPD state 2668 */ 2669 DP_NONE_HPD = 2 2670 }; 2671 2672 /** 2673 * DP HPD Status 2674 */ 2675 enum dp_hpd_status { 2676 /** 2677 * DP_HPD status low 2678 */ 2679 DP_HPD_UNPLUG = 0, 2680 /** 2681 * DP_HPD status high 2682 */ 2683 DP_HPD_PLUG 2684 }; 2685 2686 /** 2687 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2688 */ 2689 struct dp_hpd_data { 2690 /** 2691 * DP HPD instance 2692 */ 2693 uint8_t instance; 2694 /** 2695 * HPD type 2696 */ 2697 uint8_t hpd_type; 2698 /** 2699 * HPD status: only for type: DP_HPD to indicate status 2700 */ 2701 uint8_t hpd_status; 2702 /** 2703 * Alignment only 2704 */ 2705 uint8_t pad; 2706 }; 2707 2708 /** 2709 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2710 */ 2711 struct dmub_rb_cmd_dp_hpd_notify { 2712 /** 2713 * Command header. 2714 */ 2715 struct dmub_cmd_header header; 2716 /** 2717 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2718 */ 2719 struct dp_hpd_data hpd_data; 2720 }; 2721 2722 /** 2723 * Definition of a SET_CONFIG reply from DPOA. 2724 */ 2725 enum set_config_status { 2726 SET_CONFIG_PENDING = 0, 2727 SET_CONFIG_ACK_RECEIVED, 2728 SET_CONFIG_RX_TIMEOUT, 2729 SET_CONFIG_UNKNOWN_ERROR, 2730 }; 2731 2732 /** 2733 * Definition of a set_config reply 2734 */ 2735 struct set_config_reply_control_data { 2736 uint8_t instance; /* DPIA Instance */ 2737 uint8_t status; /* Set Config reply */ 2738 uint16_t pad; /* Alignment */ 2739 }; 2740 2741 /** 2742 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2743 */ 2744 struct dmub_rb_cmd_dp_set_config_reply { 2745 struct dmub_cmd_header header; 2746 struct set_config_reply_control_data set_config_reply_control; 2747 }; 2748 2749 /** 2750 * Definition of a DPIA notification header 2751 */ 2752 struct dpia_notification_header { 2753 uint8_t instance; /**< DPIA Instance */ 2754 uint8_t reserved[3]; 2755 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2756 }; 2757 2758 /** 2759 * Definition of the common data struct of DPIA notification 2760 */ 2761 struct dpia_notification_common { 2762 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2763 - sizeof(struct dpia_notification_header)]; 2764 }; 2765 2766 /** 2767 * Definition of a DPIA notification data 2768 */ 2769 struct dpia_bw_allocation_notify_data { 2770 union { 2771 struct { 2772 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2773 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2774 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2775 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2776 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2777 uint16_t reserved: 11; /**< Reserved */ 2778 } bits; 2779 2780 uint16_t flags; 2781 }; 2782 2783 uint8_t cm_id; /**< CM ID */ 2784 uint8_t group_id; /**< Group ID */ 2785 uint8_t granularity; /**< BW Allocation Granularity */ 2786 uint8_t estimated_bw; /**< Estimated_BW */ 2787 uint8_t allocated_bw; /**< Allocated_BW */ 2788 uint8_t reserved; 2789 }; 2790 2791 /** 2792 * union dpia_notify_data_type - DPIA Notification in Outbox command 2793 */ 2794 union dpia_notification_data { 2795 /** 2796 * DPIA Notification for common data struct 2797 */ 2798 struct dpia_notification_common common_data; 2799 2800 /** 2801 * DPIA Notification for DP BW Allocation support 2802 */ 2803 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2804 }; 2805 2806 /** 2807 * Definition of a DPIA notification payload 2808 */ 2809 struct dpia_notification_payload { 2810 struct dpia_notification_header header; 2811 union dpia_notification_data data; /**< DPIA notification payload data */ 2812 }; 2813 2814 /** 2815 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2816 */ 2817 struct dmub_rb_cmd_dpia_notification { 2818 struct dmub_cmd_header header; /**< DPIA notification header */ 2819 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2820 }; 2821 2822 /** 2823 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2824 */ 2825 struct dmub_cmd_hpd_state_query_data { 2826 uint8_t instance; /**< HPD instance or DPIA instance */ 2827 uint8_t result; /**< For returning HPD state */ 2828 uint16_t pad; /** < Alignment */ 2829 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2830 enum aux_return_code_type status; /**< for returning the status of command */ 2831 }; 2832 2833 /** 2834 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2835 */ 2836 struct dmub_rb_cmd_query_hpd_state { 2837 /** 2838 * Command header. 2839 */ 2840 struct dmub_cmd_header header; 2841 /** 2842 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2843 */ 2844 struct dmub_cmd_hpd_state_query_data data; 2845 }; 2846 2847 /** 2848 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2849 */ 2850 struct dmub_rb_cmd_hpd_sense_notify_data { 2851 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2852 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2853 }; 2854 2855 /** 2856 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2857 */ 2858 struct dmub_rb_cmd_hpd_sense_notify { 2859 struct dmub_cmd_header header; /**< header */ 2860 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2861 }; 2862 2863 /* 2864 * Command IDs should be treated as stable ABI. 2865 * Do not reuse or modify IDs. 2866 */ 2867 2868 /** 2869 * PSR command sub-types. 2870 */ 2871 enum dmub_cmd_psr_type { 2872 /** 2873 * Set PSR version support. 2874 */ 2875 DMUB_CMD__PSR_SET_VERSION = 0, 2876 /** 2877 * Copy driver-calculated parameters to PSR state. 2878 */ 2879 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2880 /** 2881 * Enable PSR. 2882 */ 2883 DMUB_CMD__PSR_ENABLE = 2, 2884 2885 /** 2886 * Disable PSR. 2887 */ 2888 DMUB_CMD__PSR_DISABLE = 3, 2889 2890 /** 2891 * Set PSR level. 2892 * PSR level is a 16-bit value dicated by driver that 2893 * will enable/disable different functionality. 2894 */ 2895 DMUB_CMD__PSR_SET_LEVEL = 4, 2896 2897 /** 2898 * Forces PSR enabled until an explicit PSR disable call. 2899 */ 2900 DMUB_CMD__PSR_FORCE_STATIC = 5, 2901 /** 2902 * Set vtotal in psr active for FreeSync PSR. 2903 */ 2904 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2905 /** 2906 * Set PSR power option 2907 */ 2908 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2909 }; 2910 2911 /** 2912 * Different PSR residency modes. 2913 * Different modes change the definition of PSR residency. 2914 */ 2915 enum psr_residency_mode { 2916 PSR_RESIDENCY_MODE_PHY = 0, 2917 PSR_RESIDENCY_MODE_ALPM, 2918 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2919 /* Do not add below. */ 2920 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2921 }; 2922 2923 enum dmub_cmd_fams_type { 2924 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2925 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2926 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2927 /** 2928 * For SubVP set manual trigger in FW because it 2929 * triggers DRR_UPDATE_PENDING which SubVP relies 2930 * on (for any SubVP cases that use a DRR display) 2931 */ 2932 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2933 DMUB_CMD__FAMS2_CONFIG = 4, 2934 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2935 DMUB_CMD__FAMS2_FLIP = 6, 2936 }; 2937 2938 /** 2939 * PSR versions. 2940 */ 2941 enum psr_version { 2942 /** 2943 * PSR version 1. 2944 */ 2945 PSR_VERSION_1 = 0, 2946 /** 2947 * Freesync PSR SU. 2948 */ 2949 PSR_VERSION_SU_1 = 1, 2950 /** 2951 * PSR not supported. 2952 */ 2953 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2954 }; 2955 2956 /** 2957 * PHY Link rate for DP. 2958 */ 2959 enum phy_link_rate { 2960 /** 2961 * not supported. 2962 */ 2963 PHY_RATE_UNKNOWN = 0, 2964 /** 2965 * Rate_1 (RBR) - 1.62 Gbps/Lane 2966 */ 2967 PHY_RATE_162 = 1, 2968 /** 2969 * Rate_2 - 2.16 Gbps/Lane 2970 */ 2971 PHY_RATE_216 = 2, 2972 /** 2973 * Rate_3 - 2.43 Gbps/Lane 2974 */ 2975 PHY_RATE_243 = 3, 2976 /** 2977 * Rate_4 (HBR) - 2.70 Gbps/Lane 2978 */ 2979 PHY_RATE_270 = 4, 2980 /** 2981 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2982 */ 2983 PHY_RATE_324 = 5, 2984 /** 2985 * Rate_6 - 4.32 Gbps/Lane 2986 */ 2987 PHY_RATE_432 = 6, 2988 /** 2989 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2990 */ 2991 PHY_RATE_540 = 7, 2992 /** 2993 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2994 */ 2995 PHY_RATE_810 = 8, 2996 /** 2997 * UHBR10 - 10.0 Gbps/Lane 2998 */ 2999 PHY_RATE_1000 = 9, 3000 /** 3001 * UHBR13.5 - 13.5 Gbps/Lane 3002 */ 3003 PHY_RATE_1350 = 10, 3004 /** 3005 * UHBR10 - 20.0 Gbps/Lane 3006 */ 3007 PHY_RATE_2000 = 11, 3008 3009 PHY_RATE_675 = 12, 3010 /** 3011 * Rate 12 - 6.75 Gbps/Lane 3012 */ 3013 }; 3014 3015 /** 3016 * enum dmub_phy_fsm_state - PHY FSM states. 3017 * PHY FSM state to transit to during PSR enable/disable. 3018 */ 3019 enum dmub_phy_fsm_state { 3020 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3021 DMUB_PHY_FSM_RESET, 3022 DMUB_PHY_FSM_RESET_RELEASED, 3023 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3024 DMUB_PHY_FSM_INITIALIZED, 3025 DMUB_PHY_FSM_CALIBRATED, 3026 DMUB_PHY_FSM_CALIBRATED_LP, 3027 DMUB_PHY_FSM_CALIBRATED_PG, 3028 DMUB_PHY_FSM_POWER_DOWN, 3029 DMUB_PHY_FSM_PLL_EN, 3030 DMUB_PHY_FSM_TX_EN, 3031 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3032 DMUB_PHY_FSM_FAST_LP, 3033 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3034 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3035 DMUB_PHY_FSM_P2_PLL_OFF, 3036 DMUB_PHY_FSM_P2_PLL_ON, 3037 }; 3038 3039 /** 3040 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3041 */ 3042 struct dmub_cmd_psr_copy_settings_data { 3043 /** 3044 * Flags that can be set by driver to change some PSR behaviour. 3045 */ 3046 union dmub_psr_debug_flags debug; 3047 /** 3048 * 16-bit value dicated by driver that will enable/disable different functionality. 3049 */ 3050 uint16_t psr_level; 3051 /** 3052 * DPP HW instance. 3053 */ 3054 uint8_t dpp_inst; 3055 /** 3056 * MPCC HW instance. 3057 * Not used in dmub fw, 3058 * dmub fw will get active opp by reading odm registers. 3059 */ 3060 uint8_t mpcc_inst; 3061 /** 3062 * OPP HW instance. 3063 * Not used in dmub fw, 3064 * dmub fw will get active opp by reading odm registers. 3065 */ 3066 uint8_t opp_inst; 3067 /** 3068 * OTG HW instance. 3069 */ 3070 uint8_t otg_inst; 3071 /** 3072 * DIG FE HW instance. 3073 */ 3074 uint8_t digfe_inst; 3075 /** 3076 * DIG BE HW instance. 3077 */ 3078 uint8_t digbe_inst; 3079 /** 3080 * DP PHY HW instance. 3081 */ 3082 uint8_t dpphy_inst; 3083 /** 3084 * AUX HW instance. 3085 */ 3086 uint8_t aux_inst; 3087 /** 3088 * Determines if SMU optimzations are enabled/disabled. 3089 */ 3090 uint8_t smu_optimizations_en; 3091 /** 3092 * Unused. 3093 * TODO: Remove. 3094 */ 3095 uint8_t frame_delay; 3096 /** 3097 * If RFB setup time is greater than the total VBLANK time, 3098 * it is not possible for the sink to capture the video frame 3099 * in the same frame the SDP is sent. In this case, 3100 * the frame capture indication bit should be set and an extra 3101 * static frame should be transmitted to the sink. 3102 */ 3103 uint8_t frame_cap_ind; 3104 /** 3105 * Granularity of Y offset supported by sink. 3106 */ 3107 uint8_t su_y_granularity; 3108 /** 3109 * Indicates whether sink should start capturing 3110 * immediately following active scan line, 3111 * or starting with the 2nd active scan line. 3112 */ 3113 uint8_t line_capture_indication; 3114 /** 3115 * Multi-display optimizations are implemented on certain ASICs. 3116 */ 3117 uint8_t multi_disp_optimizations_en; 3118 /** 3119 * The last possible line SDP may be transmitted without violating 3120 * the RFB setup time or entering the active video frame. 3121 */ 3122 uint16_t init_sdp_deadline; 3123 /** 3124 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3125 */ 3126 uint8_t rate_control_caps ; 3127 /* 3128 * Force PSRSU always doing full frame update 3129 */ 3130 uint8_t force_ffu_mode; 3131 /** 3132 * Length of each horizontal line in us. 3133 */ 3134 uint32_t line_time_in_us; 3135 /** 3136 * FEC enable status in driver 3137 */ 3138 uint8_t fec_enable_status; 3139 /** 3140 * FEC re-enable delay when PSR exit. 3141 * unit is 100us, range form 0~255(0xFF). 3142 */ 3143 uint8_t fec_enable_delay_in100us; 3144 /** 3145 * PSR control version. 3146 */ 3147 uint8_t cmd_version; 3148 /** 3149 * Panel Instance. 3150 * Panel instance to identify which psr_state to use 3151 * Currently the support is only for 0 or 1 3152 */ 3153 uint8_t panel_inst; 3154 /* 3155 * DSC enable status in driver 3156 */ 3157 uint8_t dsc_enable_status; 3158 /* 3159 * Use FSM state for PSR power up/down 3160 */ 3161 uint8_t use_phy_fsm; 3162 /** 3163 * frame delay for frame re-lock 3164 */ 3165 uint8_t relock_delay_frame_cnt; 3166 /** 3167 * esd recovery indicate. 3168 */ 3169 uint8_t esd_recovery; 3170 /** 3171 * DSC Slice height. 3172 */ 3173 uint16_t dsc_slice_height; 3174 /** 3175 * Some panels request main link off before xth vertical line 3176 */ 3177 uint16_t poweroff_before_vertical_line; 3178 /** 3179 * Some panels cannot handle idle pattern during PSR entry. 3180 * To power down phy before disable stream to avoid sending 3181 * idle pattern. 3182 */ 3183 uint8_t power_down_phy_before_disable_stream; 3184 }; 3185 3186 /** 3187 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3188 */ 3189 struct dmub_rb_cmd_psr_copy_settings { 3190 /** 3191 * Command header. 3192 */ 3193 struct dmub_cmd_header header; 3194 /** 3195 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3196 */ 3197 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3198 }; 3199 3200 /** 3201 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3202 */ 3203 struct dmub_cmd_psr_set_level_data { 3204 /** 3205 * 16-bit value dicated by driver that will enable/disable different functionality. 3206 */ 3207 uint16_t psr_level; 3208 /** 3209 * PSR control version. 3210 */ 3211 uint8_t cmd_version; 3212 /** 3213 * Panel Instance. 3214 * Panel instance to identify which psr_state to use 3215 * Currently the support is only for 0 or 1 3216 */ 3217 uint8_t panel_inst; 3218 }; 3219 3220 /** 3221 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3222 */ 3223 struct dmub_rb_cmd_psr_set_level { 3224 /** 3225 * Command header. 3226 */ 3227 struct dmub_cmd_header header; 3228 /** 3229 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3230 */ 3231 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3232 }; 3233 3234 struct dmub_rb_cmd_psr_enable_data { 3235 /** 3236 * PSR control version. 3237 */ 3238 uint8_t cmd_version; 3239 /** 3240 * Panel Instance. 3241 * Panel instance to identify which psr_state to use 3242 * Currently the support is only for 0 or 1 3243 */ 3244 uint8_t panel_inst; 3245 /** 3246 * Phy state to enter. 3247 * Values to use are defined in dmub_phy_fsm_state 3248 */ 3249 uint8_t phy_fsm_state; 3250 /** 3251 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3252 * Set this using enum phy_link_rate. 3253 * This does not support HDMI/DP2 for now. 3254 */ 3255 uint8_t phy_rate; 3256 }; 3257 3258 /** 3259 * Definition of a DMUB_CMD__PSR_ENABLE command. 3260 * PSR enable/disable is controlled using the sub_type. 3261 */ 3262 struct dmub_rb_cmd_psr_enable { 3263 /** 3264 * Command header. 3265 */ 3266 struct dmub_cmd_header header; 3267 3268 struct dmub_rb_cmd_psr_enable_data data; 3269 }; 3270 3271 /** 3272 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3273 */ 3274 struct dmub_cmd_psr_set_version_data { 3275 /** 3276 * PSR version that FW should implement. 3277 */ 3278 enum psr_version version; 3279 /** 3280 * PSR control version. 3281 */ 3282 uint8_t cmd_version; 3283 /** 3284 * Panel Instance. 3285 * Panel instance to identify which psr_state to use 3286 * Currently the support is only for 0 or 1 3287 */ 3288 uint8_t panel_inst; 3289 /** 3290 * Explicit padding to 4 byte boundary. 3291 */ 3292 uint8_t pad[2]; 3293 }; 3294 3295 /** 3296 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3297 */ 3298 struct dmub_rb_cmd_psr_set_version { 3299 /** 3300 * Command header. 3301 */ 3302 struct dmub_cmd_header header; 3303 /** 3304 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3305 */ 3306 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3307 }; 3308 3309 struct dmub_cmd_psr_force_static_data { 3310 /** 3311 * PSR control version. 3312 */ 3313 uint8_t cmd_version; 3314 /** 3315 * Panel Instance. 3316 * Panel instance to identify which psr_state to use 3317 * Currently the support is only for 0 or 1 3318 */ 3319 uint8_t panel_inst; 3320 /** 3321 * Explicit padding to 4 byte boundary. 3322 */ 3323 uint8_t pad[2]; 3324 }; 3325 3326 /** 3327 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3328 */ 3329 struct dmub_rb_cmd_psr_force_static { 3330 /** 3331 * Command header. 3332 */ 3333 struct dmub_cmd_header header; 3334 /** 3335 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3336 */ 3337 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3338 }; 3339 3340 /** 3341 * PSR SU debug flags. 3342 */ 3343 union dmub_psr_su_debug_flags { 3344 /** 3345 * PSR SU debug flags. 3346 */ 3347 struct { 3348 /** 3349 * Update dirty rect in SW only. 3350 */ 3351 uint8_t update_dirty_rect_only : 1; 3352 /** 3353 * Reset the cursor/plane state before processing the call. 3354 */ 3355 uint8_t reset_state : 1; 3356 } bitfields; 3357 3358 /** 3359 * Union for debug flags. 3360 */ 3361 uint32_t u32All; 3362 }; 3363 3364 /** 3365 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3366 * This triggers a selective update for PSR SU. 3367 */ 3368 struct dmub_cmd_update_dirty_rect_data { 3369 /** 3370 * Dirty rects from OS. 3371 */ 3372 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3373 /** 3374 * PSR SU debug flags. 3375 */ 3376 union dmub_psr_su_debug_flags debug_flags; 3377 /** 3378 * OTG HW instance. 3379 */ 3380 uint8_t pipe_idx; 3381 /** 3382 * Number of dirty rects. 3383 */ 3384 uint8_t dirty_rect_count; 3385 /** 3386 * PSR control version. 3387 */ 3388 uint8_t cmd_version; 3389 /** 3390 * Panel Instance. 3391 * Panel instance to identify which psr_state to use 3392 * Currently the support is only for 0 or 1 3393 */ 3394 uint8_t panel_inst; 3395 }; 3396 3397 /** 3398 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3399 */ 3400 struct dmub_rb_cmd_update_dirty_rect { 3401 /** 3402 * Command header. 3403 */ 3404 struct dmub_cmd_header header; 3405 /** 3406 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3407 */ 3408 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3409 }; 3410 3411 /** 3412 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3413 */ 3414 union dmub_reg_cursor_control_cfg { 3415 struct { 3416 uint32_t cur_enable: 1; 3417 uint32_t reser0: 3; 3418 uint32_t cur_2x_magnify: 1; 3419 uint32_t reser1: 3; 3420 uint32_t mode: 3; 3421 uint32_t reser2: 5; 3422 uint32_t pitch: 2; 3423 uint32_t reser3: 6; 3424 uint32_t line_per_chunk: 5; 3425 uint32_t reser4: 3; 3426 } bits; 3427 uint32_t raw; 3428 }; 3429 struct dmub_cursor_position_cache_hubp { 3430 union dmub_reg_cursor_control_cfg cur_ctl; 3431 union dmub_reg_position_cfg { 3432 struct { 3433 uint32_t cur_x_pos: 16; 3434 uint32_t cur_y_pos: 16; 3435 } bits; 3436 uint32_t raw; 3437 } position; 3438 union dmub_reg_hot_spot_cfg { 3439 struct { 3440 uint32_t hot_x: 16; 3441 uint32_t hot_y: 16; 3442 } bits; 3443 uint32_t raw; 3444 } hot_spot; 3445 union dmub_reg_dst_offset_cfg { 3446 struct { 3447 uint32_t dst_x_offset: 13; 3448 uint32_t reserved: 19; 3449 } bits; 3450 uint32_t raw; 3451 } dst_offset; 3452 }; 3453 3454 union dmub_reg_cur0_control_cfg { 3455 struct { 3456 uint32_t cur0_enable: 1; 3457 uint32_t expansion_mode: 1; 3458 uint32_t reser0: 1; 3459 uint32_t cur0_rom_en: 1; 3460 uint32_t mode: 3; 3461 uint32_t reserved: 25; 3462 } bits; 3463 uint32_t raw; 3464 }; 3465 struct dmub_cursor_position_cache_dpp { 3466 union dmub_reg_cur0_control_cfg cur0_ctl; 3467 }; 3468 struct dmub_cursor_position_cfg { 3469 struct dmub_cursor_position_cache_hubp pHubp; 3470 struct dmub_cursor_position_cache_dpp pDpp; 3471 uint8_t pipe_idx; 3472 /* 3473 * Padding is required. To be 4 Bytes Aligned. 3474 */ 3475 uint8_t padding[3]; 3476 }; 3477 3478 struct dmub_cursor_attribute_cache_hubp { 3479 uint32_t SURFACE_ADDR_HIGH; 3480 uint32_t SURFACE_ADDR; 3481 union dmub_reg_cursor_control_cfg cur_ctl; 3482 union dmub_reg_cursor_size_cfg { 3483 struct { 3484 uint32_t width: 16; 3485 uint32_t height: 16; 3486 } bits; 3487 uint32_t raw; 3488 } size; 3489 union dmub_reg_cursor_settings_cfg { 3490 struct { 3491 uint32_t dst_y_offset: 8; 3492 uint32_t chunk_hdl_adjust: 2; 3493 uint32_t reserved: 22; 3494 } bits; 3495 uint32_t raw; 3496 } settings; 3497 }; 3498 struct dmub_cursor_attribute_cache_dpp { 3499 union dmub_reg_cur0_control_cfg cur0_ctl; 3500 }; 3501 struct dmub_cursor_attributes_cfg { 3502 struct dmub_cursor_attribute_cache_hubp aHubp; 3503 struct dmub_cursor_attribute_cache_dpp aDpp; 3504 }; 3505 3506 struct dmub_cmd_update_cursor_payload0 { 3507 /** 3508 * Cursor dirty rects. 3509 */ 3510 struct dmub_rect cursor_rect; 3511 /** 3512 * PSR SU debug flags. 3513 */ 3514 union dmub_psr_su_debug_flags debug_flags; 3515 /** 3516 * Cursor enable/disable. 3517 */ 3518 uint8_t enable; 3519 /** 3520 * OTG HW instance. 3521 */ 3522 uint8_t pipe_idx; 3523 /** 3524 * PSR control version. 3525 */ 3526 uint8_t cmd_version; 3527 /** 3528 * Panel Instance. 3529 * Panel instance to identify which psr_state to use 3530 * Currently the support is only for 0 or 1 3531 */ 3532 uint8_t panel_inst; 3533 /** 3534 * Cursor Position Register. 3535 * Registers contains Hubp & Dpp modules 3536 */ 3537 struct dmub_cursor_position_cfg position_cfg; 3538 }; 3539 3540 struct dmub_cmd_update_cursor_payload1 { 3541 struct dmub_cursor_attributes_cfg attribute_cfg; 3542 }; 3543 3544 union dmub_cmd_update_cursor_info_data { 3545 struct dmub_cmd_update_cursor_payload0 payload0; 3546 struct dmub_cmd_update_cursor_payload1 payload1; 3547 }; 3548 /** 3549 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3550 */ 3551 struct dmub_rb_cmd_update_cursor_info { 3552 /** 3553 * Command header. 3554 */ 3555 struct dmub_cmd_header header; 3556 /** 3557 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3558 */ 3559 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3560 }; 3561 3562 /** 3563 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3564 */ 3565 struct dmub_cmd_psr_set_vtotal_data { 3566 /** 3567 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3568 */ 3569 uint16_t psr_vtotal_idle; 3570 /** 3571 * PSR control version. 3572 */ 3573 uint8_t cmd_version; 3574 /** 3575 * Panel Instance. 3576 * Panel instance to identify which psr_state to use 3577 * Currently the support is only for 0 or 1 3578 */ 3579 uint8_t panel_inst; 3580 /* 3581 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3582 */ 3583 uint16_t psr_vtotal_su; 3584 /** 3585 * Explicit padding to 4 byte boundary. 3586 */ 3587 uint8_t pad2[2]; 3588 }; 3589 3590 /** 3591 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3592 */ 3593 struct dmub_rb_cmd_psr_set_vtotal { 3594 /** 3595 * Command header. 3596 */ 3597 struct dmub_cmd_header header; 3598 /** 3599 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3600 */ 3601 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3602 }; 3603 3604 /** 3605 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3606 */ 3607 struct dmub_cmd_psr_set_power_opt_data { 3608 /** 3609 * PSR control version. 3610 */ 3611 uint8_t cmd_version; 3612 /** 3613 * Panel Instance. 3614 * Panel instance to identify which psr_state to use 3615 * Currently the support is only for 0 or 1 3616 */ 3617 uint8_t panel_inst; 3618 /** 3619 * Explicit padding to 4 byte boundary. 3620 */ 3621 uint8_t pad[2]; 3622 /** 3623 * PSR power option 3624 */ 3625 uint32_t power_opt; 3626 }; 3627 3628 /** 3629 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3630 */ 3631 struct dmub_rb_cmd_psr_set_power_opt { 3632 /** 3633 * Command header. 3634 */ 3635 struct dmub_cmd_header header; 3636 /** 3637 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3638 */ 3639 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3640 }; 3641 3642 enum dmub_alpm_mode { 3643 ALPM_AUXWAKE = 0, 3644 ALPM_AUXLESS = 1, 3645 ALPM_UNSUPPORTED = 2, 3646 }; 3647 3648 /** 3649 * Definition of Replay Residency GPINT command. 3650 * Bit[0] - Residency mode for Revision 0 3651 * Bit[1] - Enable/Disable state 3652 * Bit[2-3] - Revision number 3653 * Bit[4-7] - Residency mode for Revision 1 3654 * Bit[8] - Panel instance 3655 * Bit[9-15] - Reserved 3656 */ 3657 3658 enum pr_residency_mode { 3659 PR_RESIDENCY_MODE_PHY = 0x0, 3660 PR_RESIDENCY_MODE_ALPM, 3661 PR_RESIDENCY_MODE_IPS2, 3662 PR_RESIDENCY_MODE_FRAME_CNT, 3663 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3664 }; 3665 3666 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3667 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3668 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3669 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3670 3671 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3672 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3673 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3674 3675 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3676 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3677 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3678 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3679 3680 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3681 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3682 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3683 3684 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3685 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3686 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3687 3688 /** 3689 * Definition of a replay_state. 3690 */ 3691 enum replay_state { 3692 REPLAY_STATE_0 = 0x0, 3693 REPLAY_STATE_1 = 0x10, 3694 REPLAY_STATE_1A = 0x11, 3695 REPLAY_STATE_2 = 0x20, 3696 REPLAY_STATE_2A = 0x21, 3697 REPLAY_STATE_3 = 0x30, 3698 REPLAY_STATE_3INIT = 0x31, 3699 REPLAY_STATE_4 = 0x40, 3700 REPLAY_STATE_4A = 0x41, 3701 REPLAY_STATE_4B = 0x42, 3702 REPLAY_STATE_4C = 0x43, 3703 REPLAY_STATE_4D = 0x44, 3704 REPLAY_STATE_4E = 0x45, 3705 REPLAY_STATE_4B_LOCKED = 0x4A, 3706 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3707 REPLAY_STATE_5 = 0x50, 3708 REPLAY_STATE_5A = 0x51, 3709 REPLAY_STATE_5B = 0x52, 3710 REPLAY_STATE_5A_LOCKED = 0x5A, 3711 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3712 REPLAY_STATE_6 = 0x60, 3713 REPLAY_STATE_6A = 0x61, 3714 REPLAY_STATE_6B = 0x62, 3715 REPLAY_STATE_INVALID = 0xFF, 3716 }; 3717 3718 /** 3719 * Replay command sub-types. 3720 */ 3721 enum dmub_cmd_replay_type { 3722 /** 3723 * Copy driver-calculated parameters to REPLAY state. 3724 */ 3725 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3726 /** 3727 * Enable REPLAY. 3728 */ 3729 DMUB_CMD__REPLAY_ENABLE = 1, 3730 /** 3731 * Set Replay power option. 3732 */ 3733 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3734 /** 3735 * Set coasting vtotal. 3736 */ 3737 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3738 /** 3739 * Set power opt and coasting vtotal. 3740 */ 3741 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3742 /** 3743 * Set disabled iiming sync. 3744 */ 3745 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3746 /** 3747 * Set Residency Frameupdate Timer. 3748 */ 3749 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3750 /** 3751 * Set pseudo vtotal 3752 */ 3753 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3754 /** 3755 * Set adaptive sync sdp enabled 3756 */ 3757 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3758 /** 3759 * Set Replay General command. 3760 */ 3761 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3762 }; 3763 3764 /** 3765 * Replay general command sub-types. 3766 */ 3767 enum dmub_cmd_replay_general_subtype { 3768 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3769 /** 3770 * TODO: For backward compatible, allow new command only. 3771 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3772 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3773 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3774 */ 3775 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3776 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3777 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 3778 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 3779 }; 3780 3781 struct dmub_alpm_auxless_data { 3782 uint16_t lfps_setup_ns; 3783 uint16_t lfps_period_ns; 3784 uint16_t lfps_silence_ns; 3785 uint16_t lfps_t1_t2_override_us; 3786 short lfps_t1_t2_offset_us; 3787 uint8_t lttpr_count; 3788 }; 3789 3790 /** 3791 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3792 */ 3793 struct dmub_cmd_replay_copy_settings_data { 3794 /** 3795 * Flags that can be set by driver to change some replay behaviour. 3796 */ 3797 union replay_debug_flags debug; 3798 3799 /** 3800 * @flags: Flags used to determine feature functionality. 3801 */ 3802 union replay_hw_flags flags; 3803 3804 /** 3805 * DPP HW instance. 3806 */ 3807 uint8_t dpp_inst; 3808 /** 3809 * OTG HW instance. 3810 */ 3811 uint8_t otg_inst; 3812 /** 3813 * DIG FE HW instance. 3814 */ 3815 uint8_t digfe_inst; 3816 /** 3817 * DIG BE HW instance. 3818 */ 3819 uint8_t digbe_inst; 3820 /** 3821 * AUX HW instance. 3822 */ 3823 uint8_t aux_inst; 3824 /** 3825 * Panel Instance. 3826 * Panel isntance to identify which psr_state to use 3827 * Currently the support is only for 0 or 1 3828 */ 3829 uint8_t panel_inst; 3830 /** 3831 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3832 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3833 */ 3834 uint8_t pixel_deviation_per_line; 3835 /** 3836 * @max_deviation_line: The max number of deviation line that can keep the timing 3837 * synchronized between the Source and Sink during Replay normal sleep mode. 3838 */ 3839 uint8_t max_deviation_line; 3840 /** 3841 * Length of each horizontal line in ns. 3842 */ 3843 uint32_t line_time_in_ns; 3844 /** 3845 * PHY instance. 3846 */ 3847 uint8_t dpphy_inst; 3848 /** 3849 * Determines if SMU optimzations are enabled/disabled. 3850 */ 3851 uint8_t smu_optimizations_en; 3852 /** 3853 * Determines if timing sync are enabled/disabled. 3854 */ 3855 uint8_t replay_timing_sync_supported; 3856 /* 3857 * Use FSM state for Replay power up/down 3858 */ 3859 uint8_t use_phy_fsm; 3860 /** 3861 * Use for AUX-less ALPM LFPS wake operation 3862 */ 3863 struct dmub_alpm_auxless_data auxless_alpm_data; 3864 }; 3865 3866 /** 3867 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3868 */ 3869 struct dmub_rb_cmd_replay_copy_settings { 3870 /** 3871 * Command header. 3872 */ 3873 struct dmub_cmd_header header; 3874 /** 3875 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3876 */ 3877 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3878 }; 3879 3880 /** 3881 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3882 */ 3883 enum replay_enable { 3884 /** 3885 * Disable REPLAY. 3886 */ 3887 REPLAY_DISABLE = 0, 3888 /** 3889 * Enable REPLAY. 3890 */ 3891 REPLAY_ENABLE = 1, 3892 }; 3893 3894 /** 3895 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3896 */ 3897 struct dmub_rb_cmd_replay_enable_data { 3898 /** 3899 * Replay enable or disable. 3900 */ 3901 uint8_t enable; 3902 /** 3903 * Panel Instance. 3904 * Panel isntance to identify which replay_state to use 3905 * Currently the support is only for 0 or 1 3906 */ 3907 uint8_t panel_inst; 3908 /** 3909 * Phy state to enter. 3910 * Values to use are defined in dmub_phy_fsm_state 3911 */ 3912 uint8_t phy_fsm_state; 3913 /** 3914 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3915 * Set this using enum phy_link_rate. 3916 * This does not support HDMI/DP2 for now. 3917 */ 3918 uint8_t phy_rate; 3919 }; 3920 3921 /** 3922 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3923 * Replay enable/disable is controlled using action in data. 3924 */ 3925 struct dmub_rb_cmd_replay_enable { 3926 /** 3927 * Command header. 3928 */ 3929 struct dmub_cmd_header header; 3930 3931 struct dmub_rb_cmd_replay_enable_data data; 3932 }; 3933 3934 /** 3935 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3936 */ 3937 struct dmub_cmd_replay_set_power_opt_data { 3938 /** 3939 * Panel Instance. 3940 * Panel isntance to identify which replay_state to use 3941 * Currently the support is only for 0 or 1 3942 */ 3943 uint8_t panel_inst; 3944 /** 3945 * Explicit padding to 4 byte boundary. 3946 */ 3947 uint8_t pad[3]; 3948 /** 3949 * REPLAY power option 3950 */ 3951 uint32_t power_opt; 3952 }; 3953 3954 /** 3955 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3956 */ 3957 struct dmub_cmd_replay_set_timing_sync_data { 3958 /** 3959 * Panel Instance. 3960 * Panel isntance to identify which replay_state to use 3961 * Currently the support is only for 0 or 1 3962 */ 3963 uint8_t panel_inst; 3964 /** 3965 * REPLAY set_timing_sync 3966 */ 3967 uint8_t timing_sync_supported; 3968 /** 3969 * Explicit padding to 4 byte boundary. 3970 */ 3971 uint8_t pad[2]; 3972 }; 3973 3974 /** 3975 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3976 */ 3977 struct dmub_cmd_replay_set_pseudo_vtotal { 3978 /** 3979 * Panel Instance. 3980 * Panel isntance to identify which replay_state to use 3981 * Currently the support is only for 0 or 1 3982 */ 3983 uint8_t panel_inst; 3984 /** 3985 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3986 */ 3987 uint16_t vtotal; 3988 /** 3989 * Explicit padding to 4 byte boundary. 3990 */ 3991 uint8_t pad; 3992 }; 3993 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3994 /** 3995 * Panel Instance. 3996 * Panel isntance to identify which replay_state to use 3997 * Currently the support is only for 0 or 1 3998 */ 3999 uint8_t panel_inst; 4000 /** 4001 * enabled: set adaptive sync sdp enabled 4002 */ 4003 uint8_t force_disabled; 4004 4005 uint8_t pad[2]; 4006 }; 4007 struct dmub_cmd_replay_set_general_cmd_data { 4008 /** 4009 * Panel Instance. 4010 * Panel isntance to identify which replay_state to use 4011 * Currently the support is only for 0 or 1 4012 */ 4013 uint8_t panel_inst; 4014 /** 4015 * subtype: replay general cmd sub type 4016 */ 4017 uint8_t subtype; 4018 4019 uint8_t pad[2]; 4020 /** 4021 * config data with param1 and param2 4022 */ 4023 uint32_t param1; 4024 4025 uint32_t param2; 4026 }; 4027 4028 /** 4029 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4030 */ 4031 struct dmub_rb_cmd_replay_set_power_opt { 4032 /** 4033 * Command header. 4034 */ 4035 struct dmub_cmd_header header; 4036 /** 4037 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4038 */ 4039 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4040 }; 4041 4042 /** 4043 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4044 */ 4045 struct dmub_cmd_replay_set_coasting_vtotal_data { 4046 /** 4047 * 16-bit value dicated by driver that indicates the coasting vtotal. 4048 */ 4049 uint16_t coasting_vtotal; 4050 /** 4051 * REPLAY control version. 4052 */ 4053 uint8_t cmd_version; 4054 /** 4055 * Panel Instance. 4056 * Panel isntance to identify which replay_state to use 4057 * Currently the support is only for 0 or 1 4058 */ 4059 uint8_t panel_inst; 4060 /** 4061 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4062 */ 4063 uint16_t coasting_vtotal_high; 4064 /** 4065 * Explicit padding to 4 byte boundary. 4066 */ 4067 uint8_t pad[2]; 4068 }; 4069 4070 /** 4071 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4072 */ 4073 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4074 /** 4075 * Command header. 4076 */ 4077 struct dmub_cmd_header header; 4078 /** 4079 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4080 */ 4081 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4082 }; 4083 4084 /** 4085 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4086 */ 4087 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4088 /** 4089 * Command header. 4090 */ 4091 struct dmub_cmd_header header; 4092 /** 4093 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4094 */ 4095 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4096 /** 4097 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4098 */ 4099 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4100 }; 4101 4102 /** 4103 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4104 */ 4105 struct dmub_rb_cmd_replay_set_timing_sync { 4106 /** 4107 * Command header. 4108 */ 4109 struct dmub_cmd_header header; 4110 /** 4111 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4112 */ 4113 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4114 }; 4115 4116 /** 4117 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4118 */ 4119 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4120 /** 4121 * Command header. 4122 */ 4123 struct dmub_cmd_header header; 4124 /** 4125 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4126 */ 4127 struct dmub_cmd_replay_set_pseudo_vtotal data; 4128 }; 4129 4130 /** 4131 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4132 */ 4133 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4134 /** 4135 * Command header. 4136 */ 4137 struct dmub_cmd_header header; 4138 /** 4139 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4140 */ 4141 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4142 }; 4143 4144 /** 4145 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4146 */ 4147 struct dmub_rb_cmd_replay_set_general_cmd { 4148 /** 4149 * Command header. 4150 */ 4151 struct dmub_cmd_header header; 4152 /** 4153 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4154 */ 4155 struct dmub_cmd_replay_set_general_cmd_data data; 4156 }; 4157 4158 /** 4159 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4160 */ 4161 struct dmub_cmd_replay_frameupdate_timer_data { 4162 /** 4163 * Panel Instance. 4164 * Panel isntance to identify which replay_state to use 4165 * Currently the support is only for 0 or 1 4166 */ 4167 uint8_t panel_inst; 4168 /** 4169 * Replay Frameupdate Timer Enable or not 4170 */ 4171 uint8_t enable; 4172 /** 4173 * REPLAY force reflash frame update number 4174 */ 4175 uint16_t frameupdate_count; 4176 }; 4177 /** 4178 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4179 */ 4180 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4181 /** 4182 * Command header. 4183 */ 4184 struct dmub_cmd_header header; 4185 /** 4186 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4187 */ 4188 struct dmub_cmd_replay_frameupdate_timer_data data; 4189 }; 4190 4191 /** 4192 * Definition union of replay command set 4193 */ 4194 union dmub_replay_cmd_set { 4195 /** 4196 * Panel Instance. 4197 * Panel isntance to identify which replay_state to use 4198 * Currently the support is only for 0 or 1 4199 */ 4200 uint8_t panel_inst; 4201 /** 4202 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4203 */ 4204 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4205 /** 4206 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4207 */ 4208 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4209 /** 4210 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4211 */ 4212 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4213 /** 4214 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4215 */ 4216 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4217 /** 4218 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4219 */ 4220 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4221 }; 4222 4223 /** 4224 * Set of HW components that can be locked. 4225 * 4226 * Note: If updating with more HW components, fields 4227 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4228 */ 4229 union dmub_hw_lock_flags { 4230 /** 4231 * Set of HW components that can be locked. 4232 */ 4233 struct { 4234 /** 4235 * Lock/unlock OTG master update lock. 4236 */ 4237 uint8_t lock_pipe : 1; 4238 /** 4239 * Lock/unlock cursor. 4240 */ 4241 uint8_t lock_cursor : 1; 4242 /** 4243 * Lock/unlock global update lock. 4244 */ 4245 uint8_t lock_dig : 1; 4246 /** 4247 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4248 */ 4249 uint8_t triple_buffer_lock : 1; 4250 } bits; 4251 4252 /** 4253 * Union for HW Lock flags. 4254 */ 4255 uint8_t u8All; 4256 }; 4257 4258 /** 4259 * Instances of HW to be locked. 4260 * 4261 * Note: If updating with more HW components, fields 4262 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4263 */ 4264 struct dmub_hw_lock_inst_flags { 4265 /** 4266 * OTG HW instance for OTG master update lock. 4267 */ 4268 uint8_t otg_inst; 4269 /** 4270 * OPP instance for cursor lock. 4271 */ 4272 uint8_t opp_inst; 4273 /** 4274 * OTG HW instance for global update lock. 4275 * TODO: Remove, and re-use otg_inst. 4276 */ 4277 uint8_t dig_inst; 4278 /** 4279 * Explicit pad to 4 byte boundary. 4280 */ 4281 uint8_t pad; 4282 }; 4283 4284 /** 4285 * Clients that can acquire the HW Lock Manager. 4286 * 4287 * Note: If updating with more clients, fields in 4288 * dmub_inbox0_cmd_lock_hw must be updated to match. 4289 */ 4290 enum hw_lock_client { 4291 /** 4292 * Driver is the client of HW Lock Manager. 4293 */ 4294 HW_LOCK_CLIENT_DRIVER = 0, 4295 /** 4296 * PSR SU is the client of HW Lock Manager. 4297 */ 4298 HW_LOCK_CLIENT_PSR_SU = 1, 4299 HW_LOCK_CLIENT_SUBVP = 3, 4300 /** 4301 * Replay is the client of HW Lock Manager. 4302 */ 4303 HW_LOCK_CLIENT_REPLAY = 4, 4304 HW_LOCK_CLIENT_FAMS2 = 5, 4305 /** 4306 * Invalid client. 4307 */ 4308 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4309 }; 4310 4311 /** 4312 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4313 */ 4314 struct dmub_cmd_lock_hw_data { 4315 /** 4316 * Specifies the client accessing HW Lock Manager. 4317 */ 4318 enum hw_lock_client client; 4319 /** 4320 * HW instances to be locked. 4321 */ 4322 struct dmub_hw_lock_inst_flags inst_flags; 4323 /** 4324 * Which components to be locked. 4325 */ 4326 union dmub_hw_lock_flags hw_locks; 4327 /** 4328 * Specifies lock/unlock. 4329 */ 4330 uint8_t lock; 4331 /** 4332 * HW can be unlocked separately from releasing the HW Lock Mgr. 4333 * This flag is set if the client wishes to release the object. 4334 */ 4335 uint8_t should_release; 4336 /** 4337 * Explicit padding to 4 byte boundary. 4338 */ 4339 uint8_t pad; 4340 }; 4341 4342 /** 4343 * Definition of a DMUB_CMD__HW_LOCK command. 4344 * Command is used by driver and FW. 4345 */ 4346 struct dmub_rb_cmd_lock_hw { 4347 /** 4348 * Command header. 4349 */ 4350 struct dmub_cmd_header header; 4351 /** 4352 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4353 */ 4354 struct dmub_cmd_lock_hw_data lock_hw_data; 4355 }; 4356 4357 /** 4358 * ABM command sub-types. 4359 */ 4360 enum dmub_cmd_abm_type { 4361 /** 4362 * Initialize parameters for ABM algorithm. 4363 * Data is passed through an indirect buffer. 4364 */ 4365 DMUB_CMD__ABM_INIT_CONFIG = 0, 4366 /** 4367 * Set OTG and panel HW instance. 4368 */ 4369 DMUB_CMD__ABM_SET_PIPE = 1, 4370 /** 4371 * Set user requested backklight level. 4372 */ 4373 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4374 /** 4375 * Set ABM operating/aggression level. 4376 */ 4377 DMUB_CMD__ABM_SET_LEVEL = 3, 4378 /** 4379 * Set ambient light level. 4380 */ 4381 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4382 /** 4383 * Enable/disable fractional duty cycle for backlight PWM. 4384 */ 4385 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4386 4387 /** 4388 * unregister vertical interrupt after steady state is reached 4389 */ 4390 DMUB_CMD__ABM_PAUSE = 6, 4391 4392 /** 4393 * Save and Restore ABM state. On save we save parameters, and 4394 * on restore we update state with passed in data. 4395 */ 4396 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4397 4398 /** 4399 * Query ABM caps. 4400 */ 4401 DMUB_CMD__ABM_QUERY_CAPS = 8, 4402 4403 /** 4404 * Set ABM Events 4405 */ 4406 DMUB_CMD__ABM_SET_EVENT = 9, 4407 4408 /** 4409 * Get the current ACE curve. 4410 */ 4411 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4412 4413 /** 4414 * Get current histogram data 4415 */ 4416 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4417 }; 4418 4419 struct abm_ace_curve { 4420 /** 4421 * @offsets: ACE curve offsets. 4422 */ 4423 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4424 4425 /** 4426 * @thresholds: ACE curve thresholds. 4427 */ 4428 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4429 4430 /** 4431 * @slopes: ACE curve slopes. 4432 */ 4433 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4434 }; 4435 4436 struct fixed_pt_format { 4437 /** 4438 * @sign_bit: Indicates whether one bit is reserved for the sign. 4439 */ 4440 bool sign_bit; 4441 4442 /** 4443 * @num_int_bits: Number of bits used for integer part. 4444 */ 4445 uint8_t num_int_bits; 4446 4447 /** 4448 * @num_frac_bits: Number of bits used for fractional part. 4449 */ 4450 uint8_t num_frac_bits; 4451 4452 /** 4453 * @pad: Explicit padding to 4 byte boundary. 4454 */ 4455 uint8_t pad; 4456 }; 4457 4458 struct abm_caps { 4459 /** 4460 * @num_hg_bins: Number of histogram bins. 4461 */ 4462 uint8_t num_hg_bins; 4463 4464 /** 4465 * @num_ace_segments: Number of ACE curve segments. 4466 */ 4467 uint8_t num_ace_segments; 4468 4469 /** 4470 * @pad: Explicit padding to 4 byte boundary. 4471 */ 4472 uint8_t pad[2]; 4473 4474 /** 4475 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4476 */ 4477 struct fixed_pt_format ace_thresholds_format; 4478 4479 /** 4480 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4481 */ 4482 struct fixed_pt_format ace_offsets_format; 4483 4484 /** 4485 * @ace_slopes_format: Format of the ACE slopes. 4486 */ 4487 struct fixed_pt_format ace_slopes_format; 4488 }; 4489 4490 /** 4491 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4492 * Requirements: 4493 * - Padded explicitly to 32-bit boundary. 4494 * - Must ensure this structure matches the one on driver-side, 4495 * otherwise it won't be aligned. 4496 */ 4497 struct abm_config_table { 4498 /** 4499 * Gamma curve thresholds, used for crgb conversion. 4500 */ 4501 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4502 /** 4503 * Gamma curve offsets, used for crgb conversion. 4504 */ 4505 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4506 /** 4507 * Gamma curve slopes, used for crgb conversion. 4508 */ 4509 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4510 /** 4511 * Custom backlight curve thresholds. 4512 */ 4513 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4514 /** 4515 * Custom backlight curve offsets. 4516 */ 4517 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4518 /** 4519 * Ambient light thresholds. 4520 */ 4521 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4522 /** 4523 * Minimum programmable backlight. 4524 */ 4525 uint16_t min_abm_backlight; // 122B 4526 /** 4527 * Minimum reduction values. 4528 */ 4529 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4530 /** 4531 * Maximum reduction values. 4532 */ 4533 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4534 /** 4535 * Bright positive gain. 4536 */ 4537 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4538 /** 4539 * Dark negative gain. 4540 */ 4541 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4542 /** 4543 * Hybrid factor. 4544 */ 4545 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4546 /** 4547 * Contrast factor. 4548 */ 4549 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4550 /** 4551 * Deviation gain. 4552 */ 4553 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4554 /** 4555 * Minimum knee. 4556 */ 4557 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4558 /** 4559 * Maximum knee. 4560 */ 4561 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4562 /** 4563 * Unused. 4564 */ 4565 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4566 /** 4567 * Explicit padding to 4 byte boundary. 4568 */ 4569 uint8_t pad3[3]; // 229B 4570 /** 4571 * Backlight ramp reduction. 4572 */ 4573 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4574 /** 4575 * Backlight ramp start. 4576 */ 4577 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4578 }; 4579 4580 /** 4581 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4582 */ 4583 struct dmub_cmd_abm_set_pipe_data { 4584 /** 4585 * OTG HW instance. 4586 */ 4587 uint8_t otg_inst; 4588 4589 /** 4590 * Panel Control HW instance. 4591 */ 4592 uint8_t panel_inst; 4593 4594 /** 4595 * Controls how ABM will interpret a set pipe or set level command. 4596 */ 4597 uint8_t set_pipe_option; 4598 4599 /** 4600 * Unused. 4601 * TODO: Remove. 4602 */ 4603 uint8_t ramping_boundary; 4604 4605 /** 4606 * PwrSeq HW Instance. 4607 */ 4608 uint8_t pwrseq_inst; 4609 4610 /** 4611 * Explicit padding to 4 byte boundary. 4612 */ 4613 uint8_t pad[3]; 4614 }; 4615 4616 /** 4617 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4618 */ 4619 struct dmub_rb_cmd_abm_set_pipe { 4620 /** 4621 * Command header. 4622 */ 4623 struct dmub_cmd_header header; 4624 4625 /** 4626 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4627 */ 4628 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4629 }; 4630 4631 /** 4632 * Type of backlight control method to be used by ABM module 4633 */ 4634 enum dmub_backlight_control_type { 4635 /** 4636 * PWM Backlight control 4637 */ 4638 DMU_BACKLIGHT_CONTROL_PWM = 0, 4639 /** 4640 * VESA Aux-based backlight control 4641 */ 4642 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4643 /** 4644 * AMD DPCD Aux-based backlight control 4645 */ 4646 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4647 }; 4648 4649 /** 4650 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4651 */ 4652 struct dmub_cmd_abm_set_backlight_data { 4653 /** 4654 * Number of frames to ramp to backlight user level. 4655 */ 4656 uint32_t frame_ramp; 4657 4658 /** 4659 * Requested backlight level from user. 4660 */ 4661 uint32_t backlight_user_level; 4662 4663 /** 4664 * ABM control version. 4665 */ 4666 uint8_t version; 4667 4668 /** 4669 * Panel Control HW instance mask. 4670 * Bit 0 is Panel Control HW instance 0. 4671 * Bit 1 is Panel Control HW instance 1. 4672 */ 4673 uint8_t panel_mask; 4674 4675 /** 4676 * AUX HW Instance. 4677 */ 4678 uint8_t aux_inst; 4679 4680 /** 4681 * Explicit padding to 4 byte boundary. 4682 */ 4683 uint8_t pad[1]; 4684 4685 /** 4686 * Backlight control type. 4687 * Value 0 is PWM backlight control. 4688 * Value 1 is VAUX backlight control. 4689 * Value 2 is AMD DPCD AUX backlight control. 4690 */ 4691 enum dmub_backlight_control_type backlight_control_type; 4692 4693 /** 4694 * Minimum luminance in nits. 4695 */ 4696 uint32_t min_luminance; 4697 4698 /** 4699 * Maximum luminance in nits. 4700 */ 4701 uint32_t max_luminance; 4702 4703 /** 4704 * Minimum backlight in pwm. 4705 */ 4706 uint32_t min_backlight_pwm; 4707 4708 /** 4709 * Maximum backlight in pwm. 4710 */ 4711 uint32_t max_backlight_pwm; 4712 }; 4713 4714 /** 4715 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4716 */ 4717 struct dmub_rb_cmd_abm_set_backlight { 4718 /** 4719 * Command header. 4720 */ 4721 struct dmub_cmd_header header; 4722 4723 /** 4724 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4725 */ 4726 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4727 }; 4728 4729 /** 4730 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4731 */ 4732 struct dmub_cmd_abm_set_level_data { 4733 /** 4734 * Set current ABM operating/aggression level. 4735 */ 4736 uint32_t level; 4737 4738 /** 4739 * ABM control version. 4740 */ 4741 uint8_t version; 4742 4743 /** 4744 * Panel Control HW instance mask. 4745 * Bit 0 is Panel Control HW instance 0. 4746 * Bit 1 is Panel Control HW instance 1. 4747 */ 4748 uint8_t panel_mask; 4749 4750 /** 4751 * Explicit padding to 4 byte boundary. 4752 */ 4753 uint8_t pad[2]; 4754 }; 4755 4756 /** 4757 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4758 */ 4759 struct dmub_rb_cmd_abm_set_level { 4760 /** 4761 * Command header. 4762 */ 4763 struct dmub_cmd_header header; 4764 4765 /** 4766 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4767 */ 4768 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4769 }; 4770 4771 /** 4772 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4773 */ 4774 struct dmub_cmd_abm_set_ambient_level_data { 4775 /** 4776 * Ambient light sensor reading from OS. 4777 */ 4778 uint32_t ambient_lux; 4779 4780 /** 4781 * ABM control version. 4782 */ 4783 uint8_t version; 4784 4785 /** 4786 * Panel Control HW instance mask. 4787 * Bit 0 is Panel Control HW instance 0. 4788 * Bit 1 is Panel Control HW instance 1. 4789 */ 4790 uint8_t panel_mask; 4791 4792 /** 4793 * Explicit padding to 4 byte boundary. 4794 */ 4795 uint8_t pad[2]; 4796 }; 4797 4798 /** 4799 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4800 */ 4801 struct dmub_rb_cmd_abm_set_ambient_level { 4802 /** 4803 * Command header. 4804 */ 4805 struct dmub_cmd_header header; 4806 4807 /** 4808 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4809 */ 4810 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4811 }; 4812 4813 /** 4814 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4815 */ 4816 struct dmub_cmd_abm_set_pwm_frac_data { 4817 /** 4818 * Enable/disable fractional duty cycle for backlight PWM. 4819 * TODO: Convert to uint8_t. 4820 */ 4821 uint32_t fractional_pwm; 4822 4823 /** 4824 * ABM control version. 4825 */ 4826 uint8_t version; 4827 4828 /** 4829 * Panel Control HW instance mask. 4830 * Bit 0 is Panel Control HW instance 0. 4831 * Bit 1 is Panel Control HW instance 1. 4832 */ 4833 uint8_t panel_mask; 4834 4835 /** 4836 * Explicit padding to 4 byte boundary. 4837 */ 4838 uint8_t pad[2]; 4839 }; 4840 4841 /** 4842 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4843 */ 4844 struct dmub_rb_cmd_abm_set_pwm_frac { 4845 /** 4846 * Command header. 4847 */ 4848 struct dmub_cmd_header header; 4849 4850 /** 4851 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4852 */ 4853 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4854 }; 4855 4856 /** 4857 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4858 */ 4859 struct dmub_cmd_abm_init_config_data { 4860 /** 4861 * Location of indirect buffer used to pass init data to ABM. 4862 */ 4863 union dmub_addr src; 4864 4865 /** 4866 * Indirect buffer length. 4867 */ 4868 uint16_t bytes; 4869 4870 4871 /** 4872 * ABM control version. 4873 */ 4874 uint8_t version; 4875 4876 /** 4877 * Panel Control HW instance mask. 4878 * Bit 0 is Panel Control HW instance 0. 4879 * Bit 1 is Panel Control HW instance 1. 4880 */ 4881 uint8_t panel_mask; 4882 4883 /** 4884 * Explicit padding to 4 byte boundary. 4885 */ 4886 uint8_t pad[2]; 4887 }; 4888 4889 /** 4890 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4891 */ 4892 struct dmub_rb_cmd_abm_init_config { 4893 /** 4894 * Command header. 4895 */ 4896 struct dmub_cmd_header header; 4897 4898 /** 4899 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4900 */ 4901 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4902 }; 4903 4904 /** 4905 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4906 */ 4907 4908 struct dmub_cmd_abm_pause_data { 4909 4910 /** 4911 * Panel Control HW instance mask. 4912 * Bit 0 is Panel Control HW instance 0. 4913 * Bit 1 is Panel Control HW instance 1. 4914 */ 4915 uint8_t panel_mask; 4916 4917 /** 4918 * OTG hw instance 4919 */ 4920 uint8_t otg_inst; 4921 4922 /** 4923 * Enable or disable ABM pause 4924 */ 4925 uint8_t enable; 4926 4927 /** 4928 * Explicit padding to 4 byte boundary. 4929 */ 4930 uint8_t pad[1]; 4931 }; 4932 4933 /** 4934 * Definition of a DMUB_CMD__ABM_PAUSE command. 4935 */ 4936 struct dmub_rb_cmd_abm_pause { 4937 /** 4938 * Command header. 4939 */ 4940 struct dmub_cmd_header header; 4941 4942 /** 4943 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4944 */ 4945 struct dmub_cmd_abm_pause_data abm_pause_data; 4946 }; 4947 4948 /** 4949 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4950 */ 4951 struct dmub_cmd_abm_query_caps_in { 4952 /** 4953 * Panel instance. 4954 */ 4955 uint8_t panel_inst; 4956 4957 /** 4958 * Explicit padding to 4 byte boundary. 4959 */ 4960 uint8_t pad[3]; 4961 }; 4962 4963 /** 4964 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4965 */ 4966 struct dmub_cmd_abm_query_caps_out { 4967 /** 4968 * SW Algorithm caps. 4969 */ 4970 struct abm_caps sw_caps; 4971 4972 /** 4973 * ABM HW caps. 4974 */ 4975 struct abm_caps hw_caps; 4976 }; 4977 4978 /** 4979 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4980 */ 4981 struct dmub_rb_cmd_abm_query_caps { 4982 /** 4983 * Command header. 4984 */ 4985 struct dmub_cmd_header header; 4986 4987 /** 4988 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4989 */ 4990 union { 4991 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4992 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4993 } data; 4994 }; 4995 4996 /** 4997 * enum dmub_abm_ace_curve_type - ACE curve type. 4998 */ 4999 enum dmub_abm_ace_curve_type { 5000 /** 5001 * ACE curve as defined by the SW layer. 5002 */ 5003 ABM_ACE_CURVE_TYPE__SW = 0, 5004 /** 5005 * ACE curve as defined by the SW to HW translation interface layer. 5006 */ 5007 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5008 }; 5009 5010 /** 5011 * enum dmub_abm_histogram_type - Histogram type. 5012 */ 5013 enum dmub_abm_histogram_type { 5014 /** 5015 * ACE curve as defined by the SW layer. 5016 */ 5017 ABM_HISTOGRAM_TYPE__SW = 0, 5018 /** 5019 * ACE curve as defined by the SW to HW translation interface layer. 5020 */ 5021 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5022 }; 5023 5024 /** 5025 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5026 */ 5027 struct dmub_rb_cmd_abm_get_ace_curve { 5028 /** 5029 * Command header. 5030 */ 5031 struct dmub_cmd_header header; 5032 5033 /** 5034 * Address where ACE curve should be copied. 5035 */ 5036 union dmub_addr dest; 5037 5038 /** 5039 * Type of ACE curve being queried. 5040 */ 5041 enum dmub_abm_ace_curve_type ace_type; 5042 5043 /** 5044 * Indirect buffer length. 5045 */ 5046 uint16_t bytes; 5047 5048 /** 5049 * eDP panel instance. 5050 */ 5051 uint8_t panel_inst; 5052 5053 /** 5054 * Explicit padding to 4 byte boundary. 5055 */ 5056 uint8_t pad; 5057 }; 5058 5059 /** 5060 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5061 */ 5062 struct dmub_rb_cmd_abm_get_histogram { 5063 /** 5064 * Command header. 5065 */ 5066 struct dmub_cmd_header header; 5067 5068 /** 5069 * Address where Histogram should be copied. 5070 */ 5071 union dmub_addr dest; 5072 5073 /** 5074 * Type of Histogram being queried. 5075 */ 5076 enum dmub_abm_histogram_type histogram_type; 5077 5078 /** 5079 * Indirect buffer length. 5080 */ 5081 uint16_t bytes; 5082 5083 /** 5084 * eDP panel instance. 5085 */ 5086 uint8_t panel_inst; 5087 5088 /** 5089 * Explicit padding to 4 byte boundary. 5090 */ 5091 uint8_t pad; 5092 }; 5093 5094 /** 5095 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5096 */ 5097 struct dmub_rb_cmd_abm_save_restore { 5098 /** 5099 * Command header. 5100 */ 5101 struct dmub_cmd_header header; 5102 5103 /** 5104 * OTG hw instance 5105 */ 5106 uint8_t otg_inst; 5107 5108 /** 5109 * Enable or disable ABM pause 5110 */ 5111 uint8_t freeze; 5112 5113 /** 5114 * Explicit padding to 4 byte boundary. 5115 */ 5116 uint8_t debug; 5117 5118 /** 5119 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5120 */ 5121 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5122 }; 5123 5124 /** 5125 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5126 */ 5127 5128 struct dmub_cmd_abm_set_event_data { 5129 5130 /** 5131 * VB Scaling Init. Strength Mapping 5132 * Byte 0: 0~255 for VB level 0 5133 * Byte 1: 0~255 for VB level 1 5134 * Byte 2: 0~255 for VB level 2 5135 * Byte 3: 0~255 for VB level 3 5136 */ 5137 uint32_t vb_scaling_strength_mapping; 5138 /** 5139 * VariBright Scaling Enable 5140 */ 5141 uint8_t vb_scaling_enable; 5142 /** 5143 * Panel Control HW instance mask. 5144 * Bit 0 is Panel Control HW instance 0. 5145 * Bit 1 is Panel Control HW instance 1. 5146 */ 5147 uint8_t panel_mask; 5148 5149 /** 5150 * Explicit padding to 4 byte boundary. 5151 */ 5152 uint8_t pad[2]; 5153 }; 5154 5155 /** 5156 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5157 */ 5158 struct dmub_rb_cmd_abm_set_event { 5159 /** 5160 * Command header. 5161 */ 5162 struct dmub_cmd_header header; 5163 5164 /** 5165 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5166 */ 5167 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5168 }; 5169 5170 /** 5171 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5172 */ 5173 struct dmub_cmd_query_feature_caps_data { 5174 /** 5175 * DMUB feature capabilities. 5176 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5177 */ 5178 struct dmub_feature_caps feature_caps; 5179 }; 5180 5181 /** 5182 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5183 */ 5184 struct dmub_rb_cmd_query_feature_caps { 5185 /** 5186 * Command header. 5187 */ 5188 struct dmub_cmd_header header; 5189 /** 5190 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5191 */ 5192 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5193 }; 5194 5195 /** 5196 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5197 */ 5198 struct dmub_cmd_visual_confirm_color_data { 5199 /** 5200 * DMUB visual confirm color 5201 */ 5202 struct dmub_visual_confirm_color visual_confirm_color; 5203 }; 5204 5205 /** 5206 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5207 */ 5208 struct dmub_rb_cmd_get_visual_confirm_color { 5209 /** 5210 * Command header. 5211 */ 5212 struct dmub_cmd_header header; 5213 /** 5214 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5215 */ 5216 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5217 }; 5218 5219 /** 5220 * enum dmub_cmd_panel_cntl_type - Panel control command. 5221 */ 5222 enum dmub_cmd_panel_cntl_type { 5223 /** 5224 * Initializes embedded panel hardware blocks. 5225 */ 5226 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5227 /** 5228 * Queries backlight info for the embedded panel. 5229 */ 5230 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5231 /** 5232 * Sets the PWM Freq as per user's requirement. 5233 */ 5234 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5235 }; 5236 5237 /** 5238 * struct dmub_cmd_panel_cntl_data - Panel control data. 5239 */ 5240 struct dmub_cmd_panel_cntl_data { 5241 uint32_t pwrseq_inst; /**< pwrseq instance */ 5242 uint32_t current_backlight; /* in/out */ 5243 uint32_t bl_pwm_cntl; /* in/out */ 5244 uint32_t bl_pwm_period_cntl; /* in/out */ 5245 uint32_t bl_pwm_ref_div1; /* in/out */ 5246 uint8_t is_backlight_on : 1; /* in/out */ 5247 uint8_t is_powered_on : 1; /* in/out */ 5248 uint8_t padding[3]; 5249 uint32_t bl_pwm_ref_div2; /* in/out */ 5250 uint8_t reserved[4]; 5251 }; 5252 5253 /** 5254 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5255 */ 5256 struct dmub_rb_cmd_panel_cntl { 5257 struct dmub_cmd_header header; /**< header */ 5258 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5259 }; 5260 5261 struct dmub_optc_state { 5262 uint32_t v_total_max; 5263 uint32_t v_total_min; 5264 uint32_t tg_inst; 5265 }; 5266 5267 struct dmub_rb_cmd_drr_update { 5268 struct dmub_cmd_header header; 5269 struct dmub_optc_state dmub_optc_state_req; 5270 }; 5271 5272 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5273 uint32_t pix_clk_100hz; 5274 uint8_t max_ramp_step; 5275 uint8_t pipes; 5276 uint8_t min_refresh_in_hz; 5277 uint8_t pipe_count; 5278 uint8_t pipe_index[4]; 5279 }; 5280 5281 struct dmub_cmd_fw_assisted_mclk_switch_config { 5282 uint8_t fams_enabled; 5283 uint8_t visual_confirm_enabled; 5284 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5285 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5286 }; 5287 5288 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5289 struct dmub_cmd_header header; 5290 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5291 }; 5292 5293 /** 5294 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5295 */ 5296 struct dmub_cmd_lvtma_control_data { 5297 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5298 uint8_t bypass_panel_control_wait; 5299 uint8_t reserved_0[2]; /**< For future use */ 5300 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5301 uint8_t reserved_1[3]; /**< For future use */ 5302 }; 5303 5304 /** 5305 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5306 */ 5307 struct dmub_rb_cmd_lvtma_control { 5308 /** 5309 * Command header. 5310 */ 5311 struct dmub_cmd_header header; 5312 /** 5313 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5314 */ 5315 struct dmub_cmd_lvtma_control_data data; 5316 }; 5317 5318 /** 5319 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5320 */ 5321 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5322 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5323 uint8_t is_usb; /**< is phy is usb */ 5324 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5325 uint8_t is_dp4; /**< is dp in 4 lane */ 5326 }; 5327 5328 /** 5329 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5330 */ 5331 struct dmub_rb_cmd_transmitter_query_dp_alt { 5332 struct dmub_cmd_header header; /**< header */ 5333 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5334 }; 5335 5336 struct phy_test_mode { 5337 uint8_t mode; 5338 uint8_t pat0; 5339 uint8_t pad[2]; 5340 }; 5341 5342 /** 5343 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5344 */ 5345 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5346 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5347 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5348 uint8_t lane_num; /**< Number of lanes */ 5349 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5350 struct phy_test_mode test_mode; 5351 enum dmub_phy_fsm_state state; 5352 uint32_t status; 5353 uint8_t pad; 5354 }; 5355 5356 /** 5357 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5358 */ 5359 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5360 struct dmub_cmd_header header; /**< header */ 5361 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5362 }; 5363 5364 /** 5365 * Maximum number of bytes a chunk sent to DMUB for parsing 5366 */ 5367 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5368 5369 /** 5370 * Represent a chunk of CEA blocks sent to DMUB for parsing 5371 */ 5372 struct dmub_cmd_send_edid_cea { 5373 uint16_t offset; /**< offset into the CEA block */ 5374 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5375 uint16_t cea_total_length; /**< total length of the CEA block */ 5376 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5377 uint8_t pad[3]; /**< padding and for future expansion */ 5378 }; 5379 5380 /** 5381 * Result of VSDB parsing from CEA block 5382 */ 5383 struct dmub_cmd_edid_cea_amd_vsdb { 5384 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5385 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5386 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5387 uint16_t min_frame_rate; /**< Maximum frame rate */ 5388 uint16_t max_frame_rate; /**< Minimum frame rate */ 5389 }; 5390 5391 /** 5392 * Result of sending a CEA chunk 5393 */ 5394 struct dmub_cmd_edid_cea_ack { 5395 uint16_t offset; /**< offset of the chunk into the CEA block */ 5396 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5397 uint8_t pad; /**< padding and for future expansion */ 5398 }; 5399 5400 /** 5401 * Specify whether the result is an ACK/NACK or the parsing has finished 5402 */ 5403 enum dmub_cmd_edid_cea_reply_type { 5404 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5405 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5406 }; 5407 5408 /** 5409 * Definition of a DMUB_CMD__EDID_CEA command. 5410 */ 5411 struct dmub_rb_cmd_edid_cea { 5412 struct dmub_cmd_header header; /**< Command header */ 5413 union dmub_cmd_edid_cea_data { 5414 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5415 struct dmub_cmd_edid_cea_output { /**< output with results */ 5416 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5417 union { 5418 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5419 struct dmub_cmd_edid_cea_ack ack; 5420 }; 5421 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5422 } data; /**< Command data */ 5423 5424 }; 5425 5426 /** 5427 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5428 */ 5429 struct dmub_cmd_cable_id_input { 5430 uint8_t phy_inst; /**< phy inst for cable id data */ 5431 }; 5432 5433 /** 5434 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5435 */ 5436 struct dmub_cmd_cable_id_output { 5437 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5438 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5439 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5440 uint8_t RESERVED :2; /**< reserved means not defined */ 5441 }; 5442 5443 /** 5444 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5445 */ 5446 struct dmub_rb_cmd_get_usbc_cable_id { 5447 struct dmub_cmd_header header; /**< Command header */ 5448 /** 5449 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5450 */ 5451 union dmub_cmd_cable_id_data { 5452 struct dmub_cmd_cable_id_input input; /**< Input */ 5453 struct dmub_cmd_cable_id_output output; /**< Output */ 5454 uint8_t output_raw; /**< Raw data output */ 5455 } data; 5456 }; 5457 5458 enum dmub_cmd_fused_io_sub_type { 5459 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5460 DMUB_CMD__FUSED_IO_ABORT = 1, 5461 }; 5462 5463 enum dmub_cmd_fused_request_type { 5464 FUSED_REQUEST_READ, 5465 FUSED_REQUEST_WRITE, 5466 FUSED_REQUEST_POLL, 5467 }; 5468 5469 enum dmub_cmd_fused_request_status { 5470 FUSED_REQUEST_STATUS_SUCCESS, 5471 FUSED_REQUEST_STATUS_BEGIN, 5472 FUSED_REQUEST_STATUS_SUBMIT, 5473 FUSED_REQUEST_STATUS_REPLY, 5474 FUSED_REQUEST_STATUS_POLL, 5475 FUSED_REQUEST_STATUS_ABORTED, 5476 FUSED_REQUEST_STATUS_FAILED = 0x80, 5477 FUSED_REQUEST_STATUS_INVALID, 5478 FUSED_REQUEST_STATUS_BUSY, 5479 FUSED_REQUEST_STATUS_TIMEOUT, 5480 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5481 }; 5482 5483 struct dmub_cmd_fused_request { 5484 uint8_t status; 5485 uint8_t type : 2; 5486 uint8_t _reserved0 : 3; 5487 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5488 uint8_t identifier; 5489 uint8_t _reserved1; 5490 uint32_t timeout_us; 5491 union dmub_cmd_fused_request_location { 5492 struct dmub_cmd_fused_request_location_i2c { 5493 uint8_t is_aux : 1; // False 5494 uint8_t ddc_line : 3; 5495 uint8_t over_aux : 1; 5496 uint8_t _reserved0 : 3; 5497 uint8_t address; 5498 uint8_t offset; 5499 uint8_t length; 5500 } i2c; 5501 struct dmub_cmd_fused_request_location_aux { 5502 uint32_t is_aux : 1; // True 5503 uint32_t ddc_line : 3; 5504 uint32_t address : 20; 5505 uint32_t length : 8; // Automatically split into 16B transactions 5506 } aux; 5507 } u; 5508 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5509 }; 5510 5511 struct dmub_rb_cmd_fused_io { 5512 struct dmub_cmd_header header; 5513 struct dmub_cmd_fused_request request; 5514 }; 5515 5516 /** 5517 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5518 */ 5519 enum dmub_cmd_secure_display_type { 5520 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5521 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5522 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5523 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5524 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5525 }; 5526 5527 #define MAX_ROI_NUM 2 5528 5529 struct dmub_cmd_roi_info { 5530 uint16_t x_start; 5531 uint16_t x_end; 5532 uint16_t y_start; 5533 uint16_t y_end; 5534 uint8_t otg_id; 5535 uint8_t phy_id; 5536 }; 5537 5538 struct dmub_cmd_roi_window_ctl { 5539 uint16_t x_start; 5540 uint16_t x_end; 5541 uint16_t y_start; 5542 uint16_t y_end; 5543 bool enable; 5544 }; 5545 5546 struct dmub_cmd_roi_ctl_info { 5547 uint8_t otg_id; 5548 uint8_t phy_id; 5549 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5550 }; 5551 5552 /** 5553 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5554 */ 5555 struct dmub_rb_cmd_secure_display { 5556 struct dmub_cmd_header header; 5557 /** 5558 * Data passed from driver to dmub firmware. 5559 */ 5560 struct dmub_cmd_roi_info roi_info; 5561 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5562 }; 5563 5564 /** 5565 * Command type of a DMUB_CMD__PSP command 5566 */ 5567 enum dmub_cmd_psp_type { 5568 DMUB_CMD__PSP_ASSR_ENABLE = 0 5569 }; 5570 5571 /** 5572 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5573 */ 5574 struct dmub_cmd_assr_enable_data { 5575 /** 5576 * ASSR enable or disable. 5577 */ 5578 uint8_t enable; 5579 /** 5580 * PHY port type. 5581 * Indicates eDP / non-eDP port type 5582 */ 5583 uint8_t phy_port_type; 5584 /** 5585 * PHY port ID. 5586 */ 5587 uint8_t phy_port_id; 5588 /** 5589 * Link encoder index. 5590 */ 5591 uint8_t link_enc_index; 5592 /** 5593 * HPO mode. 5594 */ 5595 uint8_t hpo_mode; 5596 5597 /** 5598 * Reserved field. 5599 */ 5600 uint8_t reserved[7]; 5601 }; 5602 5603 /** 5604 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5605 */ 5606 struct dmub_rb_cmd_assr_enable { 5607 /** 5608 * Command header. 5609 */ 5610 struct dmub_cmd_header header; 5611 5612 /** 5613 * Assr data. 5614 */ 5615 struct dmub_cmd_assr_enable_data assr_data; 5616 5617 /** 5618 * Reserved field. 5619 */ 5620 uint32_t reserved[3]; 5621 }; 5622 5623 /** 5624 * union dmub_rb_cmd - DMUB inbox command. 5625 */ 5626 union dmub_rb_cmd { 5627 /** 5628 * Elements shared with all commands. 5629 */ 5630 struct dmub_rb_cmd_common cmd_common; 5631 /** 5632 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5633 */ 5634 struct dmub_rb_cmd_read_modify_write read_modify_write; 5635 /** 5636 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5637 */ 5638 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5639 /** 5640 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5641 */ 5642 struct dmub_rb_cmd_burst_write burst_write; 5643 /** 5644 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5645 */ 5646 struct dmub_rb_cmd_reg_wait reg_wait; 5647 /** 5648 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5649 */ 5650 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5651 /** 5652 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5653 */ 5654 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5655 /** 5656 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5657 */ 5658 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5659 /** 5660 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5661 */ 5662 struct dmub_rb_cmd_dpphy_init dpphy_init; 5663 /** 5664 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5665 */ 5666 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5667 /** 5668 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5669 */ 5670 struct dmub_rb_cmd_domain_control domain_control; 5671 /** 5672 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5673 */ 5674 struct dmub_rb_cmd_psr_set_version psr_set_version; 5675 /** 5676 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5677 */ 5678 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5679 /** 5680 * Definition of a DMUB_CMD__PSR_ENABLE command. 5681 */ 5682 struct dmub_rb_cmd_psr_enable psr_enable; 5683 /** 5684 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5685 */ 5686 struct dmub_rb_cmd_psr_set_level psr_set_level; 5687 /** 5688 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5689 */ 5690 struct dmub_rb_cmd_psr_force_static psr_force_static; 5691 /** 5692 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5693 */ 5694 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5695 /** 5696 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5697 */ 5698 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5699 /** 5700 * Definition of a DMUB_CMD__HW_LOCK command. 5701 * Command is used by driver and FW. 5702 */ 5703 struct dmub_rb_cmd_lock_hw lock_hw; 5704 /** 5705 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5706 */ 5707 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5708 /** 5709 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5710 */ 5711 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5712 /** 5713 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5714 */ 5715 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5716 /** 5717 * Definition of a DMUB_CMD__MALL command. 5718 */ 5719 struct dmub_rb_cmd_mall mall; 5720 5721 /** 5722 * Definition of a DMUB_CMD__CAB command. 5723 */ 5724 struct dmub_rb_cmd_cab_for_ss cab; 5725 5726 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5727 5728 /** 5729 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5730 */ 5731 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5732 5733 /** 5734 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5735 */ 5736 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5737 5738 /** 5739 * Definition of DMUB_CMD__PANEL_CNTL commands. 5740 */ 5741 struct dmub_rb_cmd_panel_cntl panel_cntl; 5742 5743 /** 5744 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5745 */ 5746 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5747 5748 /** 5749 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5750 */ 5751 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5752 5753 /** 5754 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5755 */ 5756 struct dmub_rb_cmd_abm_set_level abm_set_level; 5757 5758 /** 5759 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5760 */ 5761 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5762 5763 /** 5764 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5765 */ 5766 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5767 5768 /** 5769 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5770 */ 5771 struct dmub_rb_cmd_abm_init_config abm_init_config; 5772 5773 /** 5774 * Definition of a DMUB_CMD__ABM_PAUSE command. 5775 */ 5776 struct dmub_rb_cmd_abm_pause abm_pause; 5777 5778 /** 5779 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5780 */ 5781 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5782 5783 /** 5784 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5785 */ 5786 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5787 5788 /** 5789 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5790 */ 5791 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5792 5793 /** 5794 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5795 */ 5796 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 5797 5798 /** 5799 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5800 */ 5801 struct dmub_rb_cmd_abm_set_event abm_set_event; 5802 5803 /** 5804 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5805 */ 5806 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5807 5808 /** 5809 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5810 */ 5811 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5812 5813 /** 5814 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5815 */ 5816 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5817 5818 /** 5819 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5820 */ 5821 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5822 struct dmub_rb_cmd_drr_update drr_update; 5823 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5824 5825 /** 5826 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5827 */ 5828 struct dmub_rb_cmd_lvtma_control lvtma_control; 5829 /** 5830 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5831 */ 5832 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5833 /** 5834 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5835 */ 5836 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5837 /** 5838 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5839 */ 5840 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5841 /** 5842 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5843 */ 5844 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 5845 /** 5846 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5847 */ 5848 struct dmub_rb_cmd_set_config_request set_config_request; 5849 /** 5850 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5851 */ 5852 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5853 /** 5854 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 5855 */ 5856 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 5857 /** 5858 * Definition of a DMUB_CMD__EDID_CEA command. 5859 */ 5860 struct dmub_rb_cmd_edid_cea edid_cea; 5861 /** 5862 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5863 */ 5864 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5865 5866 /** 5867 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5868 */ 5869 struct dmub_rb_cmd_query_hpd_state query_hpd; 5870 /** 5871 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5872 */ 5873 struct dmub_rb_cmd_secure_display secure_display; 5874 5875 /** 5876 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5877 */ 5878 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5879 /** 5880 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5881 */ 5882 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5883 /** 5884 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 5885 */ 5886 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 5887 /* 5888 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5889 */ 5890 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5891 /** 5892 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5893 */ 5894 struct dmub_rb_cmd_replay_enable replay_enable; 5895 /** 5896 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5897 */ 5898 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5899 /** 5900 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5901 */ 5902 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5903 /** 5904 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5905 */ 5906 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5907 5908 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5909 /** 5910 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5911 */ 5912 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5913 /** 5914 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5915 */ 5916 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5917 /** 5918 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5919 */ 5920 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5921 /** 5922 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5923 */ 5924 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5925 /** 5926 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5927 */ 5928 struct dmub_rb_cmd_assr_enable assr_enable; 5929 struct dmub_rb_cmd_fams2 fams2_config; 5930 5931 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5932 5933 struct dmub_rb_cmd_fams2_flip fams2_flip; 5934 5935 struct dmub_rb_cmd_fused_io fused_io; 5936 }; 5937 5938 /** 5939 * union dmub_rb_out_cmd - Outbox command 5940 */ 5941 union dmub_rb_out_cmd { 5942 /** 5943 * Parameters common to every command. 5944 */ 5945 struct dmub_rb_cmd_common cmd_common; 5946 /** 5947 * AUX reply command. 5948 */ 5949 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5950 /** 5951 * HPD notify command. 5952 */ 5953 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5954 /** 5955 * SET_CONFIG reply command. 5956 */ 5957 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5958 /** 5959 * DPIA notification command. 5960 */ 5961 struct dmub_rb_cmd_dpia_notification dpia_notification; 5962 /** 5963 * HPD sense notification command. 5964 */ 5965 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5966 struct dmub_rb_cmd_fused_io fused_io; 5967 }; 5968 #pragma pack(pop) 5969 5970 5971 //============================================================================== 5972 //</DMUB_CMD>=================================================================== 5973 //============================================================================== 5974 //< DMUB_RB>==================================================================== 5975 //============================================================================== 5976 5977 /** 5978 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5979 */ 5980 struct dmub_rb_init_params { 5981 void *ctx; /**< Caller provided context pointer */ 5982 void *base_address; /**< CPU base address for ring's data */ 5983 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5984 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5985 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5986 }; 5987 5988 /** 5989 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5990 */ 5991 struct dmub_rb { 5992 void *base_address; /**< CPU address for the ring's data */ 5993 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5994 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5995 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5996 5997 void *ctx; /**< Caller provided context pointer */ 5998 void *dmub; /**< Pointer to the DMUB interface */ 5999 }; 6000 6001 /** 6002 * @brief Checks if the ringbuffer is empty. 6003 * 6004 * @param rb DMUB Ringbuffer 6005 * @return true if empty 6006 * @return false otherwise 6007 */ 6008 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6009 { 6010 return (rb->wrpt == rb->rptr); 6011 } 6012 6013 /** 6014 * @brief gets number of outstanding requests in the RB 6015 * 6016 * @param rb DMUB Ringbuffer 6017 * @return true if full 6018 */ 6019 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6020 { 6021 uint32_t data_count; 6022 6023 if (rb->wrpt >= rb->rptr) 6024 data_count = rb->wrpt - rb->rptr; 6025 else 6026 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6027 6028 return data_count / DMUB_RB_CMD_SIZE; 6029 } 6030 6031 /** 6032 * @brief gets number of free buffers in the RB 6033 * 6034 * @param rb DMUB Ringbuffer 6035 * @return true if full 6036 */ 6037 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6038 { 6039 uint32_t data_count; 6040 6041 if (rb->wrpt >= rb->rptr) 6042 data_count = rb->wrpt - rb->rptr; 6043 else 6044 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6045 6046 /* +1 because 1 entry is always unusable */ 6047 data_count += DMUB_RB_CMD_SIZE; 6048 6049 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6050 } 6051 6052 /** 6053 * @brief Checks if the ringbuffer is full 6054 * 6055 * @param rb DMUB Ringbuffer 6056 * @return true if full 6057 * @return false otherwise 6058 */ 6059 static inline bool dmub_rb_full(struct dmub_rb *rb) 6060 { 6061 uint32_t data_count; 6062 6063 if (rb->wrpt >= rb->rptr) 6064 data_count = rb->wrpt - rb->rptr; 6065 else 6066 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6067 6068 /* -1 because 1 entry is always unusable */ 6069 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6070 } 6071 6072 /** 6073 * @brief Pushes a command into the ringbuffer 6074 * 6075 * @param rb DMUB ringbuffer 6076 * @param cmd The command to push 6077 * @return true if the ringbuffer was not full 6078 * @return false otherwise 6079 */ 6080 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6081 const union dmub_rb_cmd *cmd) 6082 { 6083 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6084 const uint64_t *src = (const uint64_t *)cmd; 6085 uint8_t i; 6086 6087 if (dmub_rb_full(rb)) 6088 return false; 6089 6090 // copying data 6091 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6092 *dst++ = *src++; 6093 6094 rb->wrpt += DMUB_RB_CMD_SIZE; 6095 6096 if (rb->wrpt >= rb->capacity) 6097 rb->wrpt %= rb->capacity; 6098 6099 return true; 6100 } 6101 6102 /** 6103 * @brief Pushes a command into the DMUB outbox ringbuffer 6104 * 6105 * @param rb DMUB outbox ringbuffer 6106 * @param cmd Outbox command 6107 * @return true if not full 6108 * @return false otherwise 6109 */ 6110 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6111 const union dmub_rb_out_cmd *cmd) 6112 { 6113 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6114 const uint8_t *src = (const uint8_t *)cmd; 6115 6116 if (dmub_rb_full(rb)) 6117 return false; 6118 6119 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6120 6121 rb->wrpt += DMUB_RB_CMD_SIZE; 6122 6123 if (rb->wrpt >= rb->capacity) 6124 rb->wrpt %= rb->capacity; 6125 6126 return true; 6127 } 6128 6129 /** 6130 * @brief Returns the next unprocessed command in the ringbuffer. 6131 * 6132 * @param rb DMUB ringbuffer 6133 * @param cmd The command to return 6134 * @return true if not empty 6135 * @return false otherwise 6136 */ 6137 static inline bool dmub_rb_front(struct dmub_rb *rb, 6138 union dmub_rb_cmd **cmd) 6139 { 6140 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6141 6142 if (dmub_rb_empty(rb)) 6143 return false; 6144 6145 *cmd = (union dmub_rb_cmd *)rb_cmd; 6146 6147 return true; 6148 } 6149 6150 /** 6151 * @brief Determines the next ringbuffer offset. 6152 * 6153 * @param rb DMUB inbox ringbuffer 6154 * @param num_cmds Number of commands 6155 * @param next_rptr The next offset in the ringbuffer 6156 */ 6157 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6158 uint32_t num_cmds, 6159 uint32_t *next_rptr) 6160 { 6161 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6162 6163 if (*next_rptr >= rb->capacity) 6164 *next_rptr %= rb->capacity; 6165 } 6166 6167 /** 6168 * @brief Returns a pointer to a command in the inbox. 6169 * 6170 * @param rb DMUB inbox ringbuffer 6171 * @param cmd The inbox command to return 6172 * @param rptr The ringbuffer offset 6173 * @return true if not empty 6174 * @return false otherwise 6175 */ 6176 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6177 union dmub_rb_cmd **cmd, 6178 uint32_t rptr) 6179 { 6180 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6181 6182 if (dmub_rb_empty(rb)) 6183 return false; 6184 6185 *cmd = (union dmub_rb_cmd *)rb_cmd; 6186 6187 return true; 6188 } 6189 6190 /** 6191 * @brief Returns the next unprocessed command in the outbox. 6192 * 6193 * @param rb DMUB outbox ringbuffer 6194 * @param cmd The outbox command to return 6195 * @return true if not empty 6196 * @return false otherwise 6197 */ 6198 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6199 union dmub_rb_out_cmd *cmd) 6200 { 6201 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6202 uint64_t *dst = (uint64_t *)cmd; 6203 uint8_t i; 6204 6205 if (dmub_rb_empty(rb)) 6206 return false; 6207 6208 // copying data 6209 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6210 *dst++ = *src++; 6211 6212 return true; 6213 } 6214 6215 /** 6216 * @brief Removes the front entry in the ringbuffer. 6217 * 6218 * @param rb DMUB ringbuffer 6219 * @return true if the command was removed 6220 * @return false if there were no commands 6221 */ 6222 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6223 { 6224 if (dmub_rb_empty(rb)) 6225 return false; 6226 6227 rb->rptr += DMUB_RB_CMD_SIZE; 6228 6229 if (rb->rptr >= rb->capacity) 6230 rb->rptr %= rb->capacity; 6231 6232 return true; 6233 } 6234 6235 /** 6236 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6237 * 6238 * Avoids a race condition where DMCUB accesses memory while 6239 * there are still writes in flight to framebuffer. 6240 * 6241 * @param rb DMUB ringbuffer 6242 */ 6243 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6244 { 6245 uint32_t rptr = rb->rptr; 6246 uint32_t wptr = rb->wrpt; 6247 6248 while (rptr != wptr) { 6249 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6250 uint8_t i; 6251 6252 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6253 (void)READ_ONCE(*data++); 6254 6255 rptr += DMUB_RB_CMD_SIZE; 6256 if (rptr >= rb->capacity) 6257 rptr %= rb->capacity; 6258 } 6259 } 6260 6261 /** 6262 * @brief Initializes a DMCUB ringbuffer 6263 * 6264 * @param rb DMUB ringbuffer 6265 * @param init_params initial configuration for the ringbuffer 6266 */ 6267 static inline void dmub_rb_init(struct dmub_rb *rb, 6268 struct dmub_rb_init_params *init_params) 6269 { 6270 rb->base_address = init_params->base_address; 6271 rb->capacity = init_params->capacity; 6272 rb->rptr = init_params->read_ptr; 6273 rb->wrpt = init_params->write_ptr; 6274 } 6275 6276 /** 6277 * @brief Copies output data from in/out commands into the given command. 6278 * 6279 * @param rb DMUB ringbuffer 6280 * @param cmd Command to copy data into 6281 */ 6282 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6283 union dmub_rb_cmd *cmd) 6284 { 6285 // Copy rb entry back into command 6286 uint8_t *rd_ptr = (rb->rptr == 0) ? 6287 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6288 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6289 6290 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6291 } 6292 6293 //============================================================================== 6294 //</DMUB_RB>==================================================================== 6295 //============================================================================== 6296 #endif /* _DMUB_CMD_H_ */ 6297