1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 /** 148 * OS/FW agnostic memcpy 149 */ 150 #ifndef dmub_memcpy 151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 152 #endif 153 154 /** 155 * OS/FW agnostic memset 156 */ 157 #ifndef dmub_memset 158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 159 #endif 160 161 #if defined(__cplusplus) 162 extern "C" { 163 #endif 164 165 /** 166 * OS/FW agnostic udelay 167 */ 168 #ifndef dmub_udelay 169 #define dmub_udelay(microseconds) udelay(microseconds) 170 #endif 171 172 #pragma pack(push, 1) 173 #define ABM_NUM_OF_ACE_SEGMENTS 5 174 175 union abm_flags { 176 struct { 177 /** 178 * @abm_enabled: Indicates if ABM is enabled. 179 */ 180 unsigned int abm_enabled : 1; 181 182 /** 183 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 184 */ 185 unsigned int disable_abm_requested : 1; 186 187 /** 188 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled 189 * immediately. 190 */ 191 unsigned int disable_abm_immediately : 1; 192 193 /** 194 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 195 * to be disabled immediately and keep gain. 196 */ 197 unsigned int disable_abm_immediate_keep_gain : 1; 198 199 /** 200 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 201 */ 202 unsigned int fractional_pwm : 1; 203 204 /** 205 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 206 * of user backlight level. 207 */ 208 unsigned int abm_gradual_bl_change : 1; 209 } bitfields; 210 211 unsigned int u32All; 212 }; 213 214 struct abm_save_restore { 215 /** 216 * @flags: Misc. ABM flags. 217 */ 218 union abm_flags flags; 219 220 /** 221 * @pause: true: pause ABM and get state 222 * false: unpause ABM after setting state 223 */ 224 uint32_t pause; 225 226 /** 227 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 228 */ 229 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 230 231 /** 232 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 233 */ 234 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 235 236 /** 237 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 238 */ 239 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 240 241 242 /** 243 * @knee_threshold: Current x-position of ACE knee (u0.16). 244 */ 245 uint32_t knee_threshold; 246 /** 247 * @current_gain: Current backlight reduction (u16.16). 248 */ 249 uint32_t current_gain; 250 /** 251 * @curr_bl_level: Current actual backlight level converging to target backlight level. 252 */ 253 uint16_t curr_bl_level; 254 255 /** 256 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 257 */ 258 uint16_t curr_user_bl_level; 259 260 }; 261 262 /** 263 * union dmub_addr - DMUB physical/virtual 64-bit address. 264 */ 265 union dmub_addr { 266 struct { 267 uint32_t low_part; /**< Lower 32 bits */ 268 uint32_t high_part; /**< Upper 32 bits */ 269 } u; /*<< Low/high bit access */ 270 uint64_t quad_part; /*<< 64 bit address */ 271 }; 272 #pragma pack(pop) 273 274 /** 275 * Dirty rect definition. 276 */ 277 struct dmub_rect { 278 /** 279 * Dirty rect x offset. 280 */ 281 uint32_t x; 282 283 /** 284 * Dirty rect y offset. 285 */ 286 uint32_t y; 287 288 /** 289 * Dirty rect width. 290 */ 291 uint32_t width; 292 293 /** 294 * Dirty rect height. 295 */ 296 uint32_t height; 297 }; 298 299 /** 300 * Flags that can be set by driver to change some PSR behaviour. 301 */ 302 union dmub_psr_debug_flags { 303 /** 304 * Debug flags. 305 */ 306 struct { 307 /** 308 * Enable visual confirm in FW. 309 */ 310 uint32_t visual_confirm : 1; 311 312 /** 313 * Force all selective updates to bw full frame updates. 314 */ 315 uint32_t force_full_frame_update : 1; 316 317 /** 318 * Use HW Lock Mgr object to do HW locking in FW. 319 */ 320 uint32_t use_hw_lock_mgr : 1; 321 322 /** 323 * Use TPS3 signal when restore main link. 324 */ 325 uint32_t force_wakeup_by_tps3 : 1; 326 327 /** 328 * Back to back flip, therefore cannot power down PHY 329 */ 330 uint32_t back_to_back_flip : 1; 331 332 } bitfields; 333 334 /** 335 * Union for debug flags. 336 */ 337 uint32_t u32All; 338 }; 339 340 /** 341 * Flags that can be set by driver to change some Replay behaviour. 342 */ 343 union replay_debug_flags { 344 struct { 345 /** 346 * 0x1 (bit 0) 347 * Enable visual confirm in FW. 348 */ 349 uint32_t visual_confirm : 1; 350 351 /** 352 * 0x2 (bit 1) 353 * @skip_crc: Set if need to skip CRC. 354 */ 355 uint32_t skip_crc : 1; 356 357 /** 358 * 0x4 (bit 2) 359 * @force_link_power_on: Force disable ALPM control 360 */ 361 uint32_t force_link_power_on : 1; 362 363 /** 364 * 0x8 (bit 3) 365 * @force_phy_power_on: Force phy power on 366 */ 367 uint32_t force_phy_power_on : 1; 368 369 /** 370 * 0x10 (bit 4) 371 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 372 */ 373 uint32_t timing_resync_disabled : 1; 374 375 /** 376 * 0x20 (bit 5) 377 * @skip_crtc_disabled: CRTC disable skipped 378 */ 379 uint32_t skip_crtc_disabled : 1; 380 381 /** 382 * 0x40 (bit 6) 383 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 384 */ 385 uint32_t force_defer_one_frame_update : 1; 386 387 /** 388 * 0x80 (bit 7) 389 * @disable_delay_alpm_on: Force disable delay alpm on 390 */ 391 uint32_t disable_delay_alpm_on : 1; 392 393 /** 394 * 0x100 (bit 8) 395 * @disable_desync_error_check: Force disable desync error check 396 */ 397 uint32_t disable_desync_error_check : 1; 398 399 /** 400 * 0x200 (bit 9) 401 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 402 */ 403 uint32_t force_self_update_when_abm_non_steady : 1; 404 405 /** 406 * 0x400 (bit 10) 407 * @force_disable_ips1: Force disable IPS1 state 408 */ 409 uint32_t force_disable_ips1 : 1; 410 411 /** 412 * 0x800 (bit 11) 413 * @force_disable_ips2: Force disable IPS2 state 414 */ 415 uint32_t force_disable_ips2 : 1; 416 417 uint32_t reserved : 20; 418 } bitfields; 419 420 uint32_t u32All; 421 }; 422 423 union replay_hw_flags { 424 struct { 425 /** 426 * @allow_alpm_fw_standby_mode: To indicate whether the 427 * ALPM FW standby mode is allowed 428 */ 429 uint32_t allow_alpm_fw_standby_mode : 1; 430 431 /* 432 * @dsc_enable_status: DSC enable status in driver 433 */ 434 uint32_t dsc_enable_status : 1; 435 436 /** 437 * @fec_enable_status: receive fec enable/disable status from driver 438 */ 439 uint32_t fec_enable_status : 1; 440 441 /* 442 * @smu_optimizations_en: SMU power optimization. 443 * Only when active display is Replay capable and display enters Replay. 444 * Trigger interrupt to SMU to powerup/down. 445 */ 446 uint32_t smu_optimizations_en : 1; 447 448 /** 449 * @phy_power_state: Indicates current phy power state 450 */ 451 uint32_t phy_power_state : 1; 452 453 /** 454 * @link_power_state: Indicates current link power state 455 */ 456 uint32_t link_power_state : 1; 457 /** 458 * Use TPS3 signal when restore main link. 459 */ 460 uint32_t force_wakeup_by_tps3 : 1; 461 } bitfields; 462 463 uint32_t u32All; 464 }; 465 466 /** 467 * DMUB feature capabilities. 468 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 469 */ 470 struct dmub_feature_caps { 471 /** 472 * Max PSR version supported by FW. 473 */ 474 uint8_t psr; 475 uint8_t fw_assisted_mclk_switch; 476 uint8_t reserved[4]; 477 uint8_t subvp_psr_support; 478 uint8_t gecc_enable; 479 uint8_t replay_supported; 480 uint8_t replay_reserved[3]; 481 }; 482 483 struct dmub_visual_confirm_color { 484 /** 485 * Maximum 10 bits color value 486 */ 487 uint16_t color_r_cr; 488 uint16_t color_g_y; 489 uint16_t color_b_cb; 490 uint16_t panel_inst; 491 }; 492 493 #if defined(__cplusplus) 494 } 495 #endif 496 497 //============================================================================== 498 //</DMUB_TYPES>================================================================= 499 //============================================================================== 500 //< DMUB_META>================================================================== 501 //============================================================================== 502 #pragma pack(push, 1) 503 504 /* Magic value for identifying dmub_fw_meta_info */ 505 #define DMUB_FW_META_MAGIC 0x444D5542 506 507 /* Offset from the end of the file to the dmub_fw_meta_info */ 508 #define DMUB_FW_META_OFFSET 0x24 509 510 /** 511 * struct dmub_fw_meta_info - metadata associated with fw binary 512 * 513 * NOTE: This should be considered a stable API. Fields should 514 * not be repurposed or reordered. New fields should be 515 * added instead to extend the structure. 516 * 517 * @magic_value: magic value identifying DMUB firmware meta info 518 * @fw_region_size: size of the firmware state region 519 * @trace_buffer_size: size of the tracebuffer region 520 * @fw_version: the firmware version information 521 * @dal_fw: 1 if the firmware is DAL 522 */ 523 struct dmub_fw_meta_info { 524 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 525 uint32_t fw_region_size; /**< size of the firmware state region */ 526 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 527 uint32_t fw_version; /**< the firmware version information */ 528 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 529 uint8_t reserved[3]; /**< padding bits */ 530 }; 531 532 /** 533 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 534 */ 535 union dmub_fw_meta { 536 struct dmub_fw_meta_info info; /**< metadata info */ 537 uint8_t reserved[64]; /**< padding bits */ 538 }; 539 540 #pragma pack(pop) 541 542 //============================================================================== 543 //< DMUB Trace Buffer>================================================================ 544 //============================================================================== 545 /** 546 * dmub_trace_code_t - firmware trace code, 32-bits 547 */ 548 typedef uint32_t dmub_trace_code_t; 549 550 /** 551 * struct dmcub_trace_buf_entry - Firmware trace entry 552 */ 553 struct dmcub_trace_buf_entry { 554 dmub_trace_code_t trace_code; /**< trace code for the event */ 555 uint32_t tick_count; /**< the tick count at time of trace */ 556 uint32_t param0; /**< trace defined parameter 0 */ 557 uint32_t param1; /**< trace defined parameter 1 */ 558 }; 559 560 //============================================================================== 561 //< DMUB_STATUS>================================================================ 562 //============================================================================== 563 564 /** 565 * DMCUB scratch registers can be used to determine firmware status. 566 * Current scratch register usage is as follows: 567 * 568 * SCRATCH0: FW Boot Status register 569 * SCRATCH5: LVTMA Status Register 570 * SCRATCH15: FW Boot Options register 571 */ 572 573 /** 574 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 575 */ 576 union dmub_fw_boot_status { 577 struct { 578 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 579 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 580 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 581 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 582 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 583 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 584 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 585 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 586 } bits; /**< status bits */ 587 uint32_t all; /**< 32-bit access to status bits */ 588 }; 589 590 /** 591 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 592 */ 593 enum dmub_fw_boot_status_bit { 594 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 595 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 596 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 597 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 598 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 599 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 600 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 601 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 602 }; 603 604 /* Register bit definition for SCRATCH5 */ 605 union dmub_lvtma_status { 606 struct { 607 uint32_t psp_ok : 1; 608 uint32_t edp_on : 1; 609 uint32_t reserved : 30; 610 } bits; 611 uint32_t all; 612 }; 613 614 enum dmub_lvtma_status_bit { 615 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 616 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 617 }; 618 619 enum dmub_ips_disable_type { 620 DMUB_IPS_DISABLE_IPS1 = 1, 621 DMUB_IPS_DISABLE_IPS2 = 2, 622 DMUB_IPS_DISABLE_IPS2_Z10 = 3, 623 }; 624 625 #define DMUB_IPS1_ALLOW_MASK 0x00000001 626 #define DMUB_IPS2_ALLOW_MASK 0x00000002 627 #define DMUB_IPS1_COMMIT_MASK 0x00000004 628 #define DMUB_IPS2_COMMIT_MASK 0x00000008 629 630 /** 631 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 632 */ 633 union dmub_fw_boot_options { 634 struct { 635 uint32_t pemu_env : 1; /**< 1 if PEMU */ 636 uint32_t fpga_env : 1; /**< 1 if FPGA */ 637 uint32_t optimized_init : 1; /**< 1 if optimized init */ 638 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 639 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 640 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 641 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 642 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 643 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 644 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 645 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 646 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 647 uint32_t power_optimization: 1; 648 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 649 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 650 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 651 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 652 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 653 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 654 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 655 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 656 uint32_t ips_disable: 2; /* options to disable ips support*/ 657 uint32_t reserved : 10; /**< reserved */ 658 } bits; /**< boot bits */ 659 uint32_t all; /**< 32-bit access to bits */ 660 }; 661 662 enum dmub_fw_boot_options_bit { 663 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 664 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 665 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 666 }; 667 668 //============================================================================== 669 //</DMUB_STATUS>================================================================ 670 //============================================================================== 671 //< DMUB_VBIOS>================================================================= 672 //============================================================================== 673 674 /* 675 * enum dmub_cmd_vbios_type - VBIOS commands. 676 * 677 * Command IDs should be treated as stable ABI. 678 * Do not reuse or modify IDs. 679 */ 680 enum dmub_cmd_vbios_type { 681 /** 682 * Configures the DIG encoder. 683 */ 684 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 685 /** 686 * Controls the PHY. 687 */ 688 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 689 /** 690 * Sets the pixel clock/symbol clock. 691 */ 692 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 693 /** 694 * Enables or disables power gating. 695 */ 696 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 697 /** 698 * Controls embedded panels. 699 */ 700 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 701 /** 702 * Query DP alt status on a transmitter. 703 */ 704 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 705 /** 706 * Controls domain power gating 707 */ 708 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 709 }; 710 711 //============================================================================== 712 //</DMUB_VBIOS>================================================================= 713 //============================================================================== 714 //< DMUB_GPINT>================================================================= 715 //============================================================================== 716 717 /** 718 * The shifts and masks below may alternatively be used to format and read 719 * the command register bits. 720 */ 721 722 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 723 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 724 725 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 726 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 727 728 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 729 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 730 731 /** 732 * Command responses. 733 */ 734 735 /** 736 * Return response for DMUB_GPINT__STOP_FW command. 737 */ 738 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 739 740 /** 741 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 742 */ 743 union dmub_gpint_data_register { 744 struct { 745 uint32_t param : 16; /**< 16-bit parameter */ 746 uint32_t command_code : 12; /**< GPINT command */ 747 uint32_t status : 4; /**< Command status bit */ 748 } bits; /**< GPINT bit access */ 749 uint32_t all; /**< GPINT 32-bit access */ 750 }; 751 752 /* 753 * enum dmub_gpint_command - GPINT command to DMCUB FW 754 * 755 * Command IDs should be treated as stable ABI. 756 * Do not reuse or modify IDs. 757 */ 758 enum dmub_gpint_command { 759 /** 760 * Invalid command, ignored. 761 */ 762 DMUB_GPINT__INVALID_COMMAND = 0, 763 /** 764 * DESC: Queries the firmware version. 765 * RETURN: Firmware version. 766 */ 767 DMUB_GPINT__GET_FW_VERSION = 1, 768 /** 769 * DESC: Halts the firmware. 770 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 771 */ 772 DMUB_GPINT__STOP_FW = 2, 773 /** 774 * DESC: Get PSR state from FW. 775 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 776 */ 777 DMUB_GPINT__GET_PSR_STATE = 7, 778 /** 779 * DESC: Notifies DMCUB of the currently active streams. 780 * ARGS: Stream mask, 1 bit per active stream index. 781 */ 782 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 783 /** 784 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 785 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 786 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 787 * RETURN: PSR residency in milli-percent. 788 */ 789 DMUB_GPINT__PSR_RESIDENCY = 9, 790 791 /** 792 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 793 */ 794 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 795 796 /** 797 * DESC: Get REPLAY state from FW. 798 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 799 */ 800 DMUB_GPINT__GET_REPLAY_STATE = 13, 801 802 /** 803 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 804 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 805 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 806 * RETURN: REPLAY residency in milli-percent. 807 */ 808 DMUB_GPINT__REPLAY_RESIDENCY = 14, 809 810 /** 811 * DESC: Updates the trace buffer lower 32-bit mask. 812 * ARGS: The new mask 813 * RETURN: Lower 32-bit mask. 814 */ 815 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 816 /** 817 * DESC: Updates the trace buffer lower 32-bit mask. 818 * ARGS: The new mask 819 * RETURN: Lower 32-bit mask. 820 */ 821 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 822 /** 823 * DESC: Updates the trace buffer mask bi0~bit15. 824 * ARGS: The new mask 825 * RETURN: Lower 32-bit mask. 826 */ 827 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 828 }; 829 830 /** 831 * INBOX0 generic command definition 832 */ 833 union dmub_inbox0_cmd_common { 834 struct { 835 uint32_t command_code: 8; /**< INBOX0 command code */ 836 uint32_t param: 24; /**< 24-bit parameter */ 837 } bits; 838 uint32_t all; 839 }; 840 841 /** 842 * INBOX0 hw_lock command definition 843 */ 844 union dmub_inbox0_cmd_lock_hw { 845 struct { 846 uint32_t command_code: 8; 847 848 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 849 uint32_t hw_lock_client: 2; 850 851 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 852 uint32_t otg_inst: 3; 853 uint32_t opp_inst: 3; 854 uint32_t dig_inst: 3; 855 856 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 857 uint32_t lock_pipe: 1; 858 uint32_t lock_cursor: 1; 859 uint32_t lock_dig: 1; 860 uint32_t triple_buffer_lock: 1; 861 862 uint32_t lock: 1; /**< Lock */ 863 uint32_t should_release: 1; /**< Release */ 864 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 865 } bits; 866 uint32_t all; 867 }; 868 869 union dmub_inbox0_data_register { 870 union dmub_inbox0_cmd_common inbox0_cmd_common; 871 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 872 }; 873 874 enum dmub_inbox0_command { 875 /** 876 * DESC: Invalid command, ignored. 877 */ 878 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 879 /** 880 * DESC: Notification to acquire/release HW lock 881 * ARGS: 882 */ 883 DMUB_INBOX0_CMD__HW_LOCK = 1, 884 }; 885 //============================================================================== 886 //</DMUB_GPINT>================================================================= 887 //============================================================================== 888 //< DMUB_CMD>=================================================================== 889 //============================================================================== 890 891 /** 892 * Size in bytes of each DMUB command. 893 */ 894 #define DMUB_RB_CMD_SIZE 64 895 896 /** 897 * Maximum number of items in the DMUB ringbuffer. 898 */ 899 #define DMUB_RB_MAX_ENTRY 128 900 901 /** 902 * Ringbuffer size in bytes. 903 */ 904 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 905 906 /** 907 * REG_SET mask for reg offload. 908 */ 909 #define REG_SET_MASK 0xFFFF 910 911 /* 912 * enum dmub_cmd_type - DMUB inbox command. 913 * 914 * Command IDs should be treated as stable ABI. 915 * Do not reuse or modify IDs. 916 */ 917 enum dmub_cmd_type { 918 /** 919 * Invalid command. 920 */ 921 DMUB_CMD__NULL = 0, 922 /** 923 * Read modify write register sequence offload. 924 */ 925 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 926 /** 927 * Field update register sequence offload. 928 */ 929 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 930 /** 931 * Burst write sequence offload. 932 */ 933 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 934 /** 935 * Reg wait sequence offload. 936 */ 937 DMUB_CMD__REG_REG_WAIT = 4, 938 /** 939 * Workaround to avoid HUBP underflow during NV12 playback. 940 */ 941 DMUB_CMD__PLAT_54186_WA = 5, 942 /** 943 * Command type used to query FW feature caps. 944 */ 945 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 946 /** 947 * Command type used to get visual confirm color. 948 */ 949 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 950 /** 951 * Command type used for all PSR commands. 952 */ 953 DMUB_CMD__PSR = 64, 954 /** 955 * Command type used for all MALL commands. 956 */ 957 DMUB_CMD__MALL = 65, 958 /** 959 * Command type used for all ABM commands. 960 */ 961 DMUB_CMD__ABM = 66, 962 /** 963 * Command type used to update dirty rects in FW. 964 */ 965 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 966 /** 967 * Command type used to update cursor info in FW. 968 */ 969 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 970 /** 971 * Command type used for HW locking in FW. 972 */ 973 DMUB_CMD__HW_LOCK = 69, 974 /** 975 * Command type used to access DP AUX. 976 */ 977 DMUB_CMD__DP_AUX_ACCESS = 70, 978 /** 979 * Command type used for OUTBOX1 notification enable 980 */ 981 DMUB_CMD__OUTBOX1_ENABLE = 71, 982 983 /** 984 * Command type used for all idle optimization commands. 985 */ 986 DMUB_CMD__IDLE_OPT = 72, 987 /** 988 * Command type used for all clock manager commands. 989 */ 990 DMUB_CMD__CLK_MGR = 73, 991 /** 992 * Command type used for all panel control commands. 993 */ 994 DMUB_CMD__PANEL_CNTL = 74, 995 996 /** 997 * Command type used for all CAB commands. 998 */ 999 DMUB_CMD__CAB_FOR_SS = 75, 1000 1001 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1002 1003 /** 1004 * Command type used for interfacing with DPIA. 1005 */ 1006 DMUB_CMD__DPIA = 77, 1007 /** 1008 * Command type used for EDID CEA parsing 1009 */ 1010 DMUB_CMD__EDID_CEA = 79, 1011 /** 1012 * Command type used for getting usbc cable ID 1013 */ 1014 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1015 /** 1016 * Command type used to query HPD state. 1017 */ 1018 DMUB_CMD__QUERY_HPD_STATE = 82, 1019 /** 1020 * Command type used for all VBIOS interface commands. 1021 */ 1022 /** 1023 * Command type used for all REPLAY commands. 1024 */ 1025 DMUB_CMD__REPLAY = 83, 1026 1027 /** 1028 * Command type used for all SECURE_DISPLAY commands. 1029 */ 1030 DMUB_CMD__SECURE_DISPLAY = 85, 1031 1032 /** 1033 * Command type used to set DPIA HPD interrupt state 1034 */ 1035 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1036 1037 DMUB_CMD__VBIOS = 128, 1038 }; 1039 1040 /** 1041 * enum dmub_out_cmd_type - DMUB outbox commands. 1042 */ 1043 enum dmub_out_cmd_type { 1044 /** 1045 * Invalid outbox command, ignored. 1046 */ 1047 DMUB_OUT_CMD__NULL = 0, 1048 /** 1049 * Command type used for DP AUX Reply data notification 1050 */ 1051 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1052 /** 1053 * Command type used for DP HPD event notification 1054 */ 1055 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1056 /** 1057 * Command type used for SET_CONFIG Reply notification 1058 */ 1059 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1060 /** 1061 * Command type used for USB4 DPIA notification 1062 */ 1063 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1064 }; 1065 1066 /* DMUB_CMD__DPIA command sub-types. */ 1067 enum dmub_cmd_dpia_type { 1068 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1069 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1070 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1071 }; 1072 1073 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1074 enum dmub_cmd_dpia_notification_type { 1075 DPIA_NOTIFY__BW_ALLOCATION = 0, 1076 }; 1077 1078 #pragma pack(push, 1) 1079 1080 /** 1081 * struct dmub_cmd_header - Common command header fields. 1082 */ 1083 struct dmub_cmd_header { 1084 unsigned int type : 8; /**< command type */ 1085 unsigned int sub_type : 8; /**< command sub type */ 1086 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1087 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1088 unsigned int reserved0 : 6; /**< reserved bits */ 1089 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1090 unsigned int reserved1 : 2; /**< reserved bits */ 1091 }; 1092 1093 /* 1094 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1095 * 1096 * 60 payload bytes can hold up to 5 sets of read modify writes, 1097 * each take 3 dwords. 1098 * 1099 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1100 * 1101 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1102 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1103 */ 1104 struct dmub_cmd_read_modify_write_sequence { 1105 uint32_t addr; /**< register address */ 1106 uint32_t modify_mask; /**< modify mask */ 1107 uint32_t modify_value; /**< modify value */ 1108 }; 1109 1110 /** 1111 * Maximum number of ops in read modify write sequence. 1112 */ 1113 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1114 1115 /** 1116 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1117 */ 1118 struct dmub_rb_cmd_read_modify_write { 1119 struct dmub_cmd_header header; /**< command header */ 1120 /** 1121 * Read modify write sequence. 1122 */ 1123 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1124 }; 1125 1126 /* 1127 * Update a register with specified masks and values sequeunce 1128 * 1129 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1130 * 1131 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1132 * 1133 * 1134 * USE CASE: 1135 * 1. auto-increment register where additional read would update pointer and produce wrong result 1136 * 2. toggle a bit without read in the middle 1137 */ 1138 1139 struct dmub_cmd_reg_field_update_sequence { 1140 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1141 uint32_t modify_value; /**< value to update with */ 1142 }; 1143 1144 /** 1145 * Maximum number of ops in field update sequence. 1146 */ 1147 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1148 1149 /** 1150 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1151 */ 1152 struct dmub_rb_cmd_reg_field_update_sequence { 1153 struct dmub_cmd_header header; /**< command header */ 1154 uint32_t addr; /**< register address */ 1155 /** 1156 * Field update sequence. 1157 */ 1158 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1159 }; 1160 1161 1162 /** 1163 * Maximum number of burst write values. 1164 */ 1165 #define DMUB_BURST_WRITE_VALUES__MAX 14 1166 1167 /* 1168 * struct dmub_rb_cmd_burst_write - Burst write 1169 * 1170 * support use case such as writing out LUTs. 1171 * 1172 * 60 payload bytes can hold up to 14 values to write to given address 1173 * 1174 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1175 */ 1176 struct dmub_rb_cmd_burst_write { 1177 struct dmub_cmd_header header; /**< command header */ 1178 uint32_t addr; /**< register start address */ 1179 /** 1180 * Burst write register values. 1181 */ 1182 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1183 }; 1184 1185 /** 1186 * struct dmub_rb_cmd_common - Common command header 1187 */ 1188 struct dmub_rb_cmd_common { 1189 struct dmub_cmd_header header; /**< command header */ 1190 /** 1191 * Padding to RB_CMD_SIZE 1192 */ 1193 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1194 }; 1195 1196 /** 1197 * struct dmub_cmd_reg_wait_data - Register wait data 1198 */ 1199 struct dmub_cmd_reg_wait_data { 1200 uint32_t addr; /**< Register address */ 1201 uint32_t mask; /**< Mask for register bits */ 1202 uint32_t condition_field_value; /**< Value to wait for */ 1203 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1204 }; 1205 1206 /** 1207 * struct dmub_rb_cmd_reg_wait - Register wait command 1208 */ 1209 struct dmub_rb_cmd_reg_wait { 1210 struct dmub_cmd_header header; /**< Command header */ 1211 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1212 }; 1213 1214 /** 1215 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1216 * 1217 * Reprograms surface parameters to avoid underflow. 1218 */ 1219 struct dmub_cmd_PLAT_54186_wa { 1220 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1221 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1222 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1223 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1224 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1225 struct { 1226 uint8_t hubp_inst : 4; /**< HUBP instance */ 1227 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 1228 uint8_t immediate :1; /**< Immediate flip */ 1229 uint8_t vmid : 4; /**< VMID */ 1230 uint8_t grph_stereo : 1; /**< 1 if stereo */ 1231 uint32_t reserved : 21; /**< Reserved */ 1232 } flip_params; /**< Pageflip parameters */ 1233 uint32_t reserved[9]; /**< Reserved bits */ 1234 }; 1235 1236 /** 1237 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1238 */ 1239 struct dmub_rb_cmd_PLAT_54186_wa { 1240 struct dmub_cmd_header header; /**< Command header */ 1241 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1242 }; 1243 1244 /** 1245 * enum dmub_cmd_mall_type - MALL commands 1246 */ 1247 enum dmub_cmd_mall_type { 1248 /** 1249 * Allows display refresh from MALL. 1250 */ 1251 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1252 /** 1253 * Disallows display refresh from MALL. 1254 */ 1255 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1256 /** 1257 * Cursor copy for MALL. 1258 */ 1259 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1260 /** 1261 * Controls DF requests. 1262 */ 1263 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1264 }; 1265 1266 /** 1267 * struct dmub_rb_cmd_mall - MALL command data. 1268 */ 1269 struct dmub_rb_cmd_mall { 1270 struct dmub_cmd_header header; /**< Common command header */ 1271 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1272 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1273 uint32_t tmr_delay; /**< Timer delay */ 1274 uint32_t tmr_scale; /**< Timer scale */ 1275 uint16_t cursor_width; /**< Cursor width in pixels */ 1276 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1277 uint16_t cursor_height; /**< Cursor height in pixels */ 1278 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1279 uint8_t debug_bits; /**< Debug bits */ 1280 1281 uint8_t reserved1; /**< Reserved bits */ 1282 uint8_t reserved2; /**< Reserved bits */ 1283 }; 1284 1285 /** 1286 * enum dmub_cmd_cab_type - CAB command data. 1287 */ 1288 enum dmub_cmd_cab_type { 1289 /** 1290 * No idle optimizations (i.e. no CAB) 1291 */ 1292 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1293 /** 1294 * No DCN requests for memory 1295 */ 1296 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1297 /** 1298 * Fit surfaces in CAB (i.e. CAB enable) 1299 */ 1300 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1301 }; 1302 1303 /** 1304 * struct dmub_rb_cmd_cab - CAB command data. 1305 */ 1306 struct dmub_rb_cmd_cab_for_ss { 1307 struct dmub_cmd_header header; 1308 uint8_t cab_alloc_ways; /* total number of ways */ 1309 uint8_t debug_bits; /* debug bits */ 1310 }; 1311 1312 /** 1313 * Enum for indicating which MCLK switch mode per pipe 1314 */ 1315 enum mclk_switch_mode { 1316 NONE = 0, 1317 FPO = 1, 1318 SUBVP = 2, 1319 VBLANK = 3, 1320 }; 1321 1322 /* Per pipe struct which stores the MCLK switch mode 1323 * data to be sent to DMUB. 1324 * Named "v2" for now -- once FPO and SUBVP are fully merged 1325 * the type name can be updated 1326 */ 1327 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1328 union { 1329 struct { 1330 uint32_t pix_clk_100hz; 1331 uint16_t main_vblank_start; 1332 uint16_t main_vblank_end; 1333 uint16_t mall_region_lines; 1334 uint16_t prefetch_lines; 1335 uint16_t prefetch_to_mall_start_lines; 1336 uint16_t processing_delay_lines; 1337 uint16_t htotal; // required to calculate line time for multi-display cases 1338 uint16_t vtotal; 1339 uint8_t main_pipe_index; 1340 uint8_t phantom_pipe_index; 1341 /* Since the microschedule is calculated in terms of OTG lines, 1342 * include any scaling factors to make sure when we get accurate 1343 * conversion when programming MALL_START_LINE (which is in terms 1344 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1345 * is 1/2 (numerator = 1, denominator = 2). 1346 */ 1347 uint8_t scale_factor_numerator; 1348 uint8_t scale_factor_denominator; 1349 uint8_t is_drr; 1350 uint8_t main_split_pipe_index; 1351 uint8_t phantom_split_pipe_index; 1352 } subvp_data; 1353 1354 struct { 1355 uint32_t pix_clk_100hz; 1356 uint16_t vblank_start; 1357 uint16_t vblank_end; 1358 uint16_t vstartup_start; 1359 uint16_t vtotal; 1360 uint16_t htotal; 1361 uint8_t vblank_pipe_index; 1362 uint8_t padding[1]; 1363 struct { 1364 uint8_t drr_in_use; 1365 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1366 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1367 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1368 uint8_t use_ramping; // Use ramping or not 1369 uint8_t drr_vblank_start_margin; 1370 } drr_info; // DRR considered as part of SubVP + VBLANK case 1371 } vblank_data; 1372 } pipe_config; 1373 1374 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1375 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1376 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1377 */ 1378 uint8_t mode; // enum mclk_switch_mode 1379 }; 1380 1381 /** 1382 * Config data for Sub-VP and FPO 1383 * Named "v2" for now -- once FPO and SUBVP are fully merged 1384 * the type name can be updated 1385 */ 1386 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1387 uint16_t watermark_a_cache; 1388 uint8_t vertical_int_margin_us; 1389 uint8_t pstate_allow_width_us; 1390 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1391 }; 1392 1393 /** 1394 * DMUB rb command definition for Sub-VP and FPO 1395 * Named "v2" for now -- once FPO and SUBVP are fully merged 1396 * the type name can be updated 1397 */ 1398 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1399 struct dmub_cmd_header header; 1400 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1401 }; 1402 1403 /** 1404 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1405 */ 1406 enum dmub_cmd_idle_opt_type { 1407 /** 1408 * DCN hardware restore. 1409 */ 1410 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1411 1412 /** 1413 * DCN hardware save. 1414 */ 1415 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1416 1417 /** 1418 * DCN hardware notify idle. 1419 */ 1420 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1421 }; 1422 1423 /** 1424 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1425 */ 1426 struct dmub_rb_cmd_idle_opt_dcn_restore { 1427 struct dmub_cmd_header header; /**< header */ 1428 }; 1429 1430 /** 1431 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1432 */ 1433 struct dmub_dcn_notify_idle_cntl_data { 1434 uint8_t driver_idle; 1435 uint8_t pad[1]; 1436 }; 1437 1438 /** 1439 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1440 */ 1441 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1442 struct dmub_cmd_header header; /**< header */ 1443 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1444 }; 1445 1446 /** 1447 * struct dmub_clocks - Clock update notification. 1448 */ 1449 struct dmub_clocks { 1450 uint32_t dispclk_khz; /**< dispclk kHz */ 1451 uint32_t dppclk_khz; /**< dppclk kHz */ 1452 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1453 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1454 }; 1455 1456 /** 1457 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1458 */ 1459 enum dmub_cmd_clk_mgr_type { 1460 /** 1461 * Notify DMCUB of clock update. 1462 */ 1463 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1464 }; 1465 1466 /** 1467 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1468 */ 1469 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1470 struct dmub_cmd_header header; /**< header */ 1471 struct dmub_clocks clocks; /**< clock data */ 1472 }; 1473 1474 /** 1475 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1476 */ 1477 struct dmub_cmd_digx_encoder_control_data { 1478 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1479 }; 1480 1481 /** 1482 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1483 */ 1484 struct dmub_rb_cmd_digx_encoder_control { 1485 struct dmub_cmd_header header; /**< header */ 1486 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1487 }; 1488 1489 /** 1490 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1491 */ 1492 struct dmub_cmd_set_pixel_clock_data { 1493 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1494 }; 1495 1496 /** 1497 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1498 */ 1499 struct dmub_rb_cmd_set_pixel_clock { 1500 struct dmub_cmd_header header; /**< header */ 1501 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1502 }; 1503 1504 /** 1505 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1506 */ 1507 struct dmub_cmd_enable_disp_power_gating_data { 1508 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1509 }; 1510 1511 /** 1512 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1513 */ 1514 struct dmub_rb_cmd_enable_disp_power_gating { 1515 struct dmub_cmd_header header; /**< header */ 1516 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1517 }; 1518 1519 /** 1520 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1521 */ 1522 struct dmub_dig_transmitter_control_data_v1_7 { 1523 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1524 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1525 union { 1526 uint8_t digmode; /**< enum atom_encode_mode_def */ 1527 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1528 } mode_laneset; 1529 uint8_t lanenum; /**< Number of lanes */ 1530 union { 1531 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1532 } symclk_units; 1533 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1534 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1535 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1536 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1537 uint8_t reserved1; /**< For future use */ 1538 uint8_t reserved2[3]; /**< For future use */ 1539 uint32_t reserved3[11]; /**< For future use */ 1540 }; 1541 1542 /** 1543 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1544 */ 1545 union dmub_cmd_dig1_transmitter_control_data { 1546 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1547 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1548 }; 1549 1550 /** 1551 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1552 */ 1553 struct dmub_rb_cmd_dig1_transmitter_control { 1554 struct dmub_cmd_header header; /**< header */ 1555 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1556 }; 1557 1558 /** 1559 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1560 */ 1561 struct dmub_rb_cmd_domain_control_data { 1562 uint8_t inst : 6; /**< DOMAIN instance to control */ 1563 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1564 uint8_t reserved[3]; /**< Reserved for future use */ 1565 }; 1566 1567 /** 1568 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1569 */ 1570 struct dmub_rb_cmd_domain_control { 1571 struct dmub_cmd_header header; /**< header */ 1572 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1573 }; 1574 1575 /** 1576 * DPIA tunnel command parameters. 1577 */ 1578 struct dmub_cmd_dig_dpia_control_data { 1579 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1580 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1581 union { 1582 uint8_t digmode; /** enum atom_encode_mode_def */ 1583 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1584 } mode_laneset; 1585 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1586 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1587 uint8_t hpdsel; /** =0: HPD is not assigned */ 1588 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1589 uint8_t dpia_id; /** Index of DPIA */ 1590 uint8_t fec_rdy : 1; 1591 uint8_t reserved : 7; 1592 uint32_t reserved1; 1593 }; 1594 1595 /** 1596 * DMUB command for DPIA tunnel control. 1597 */ 1598 struct dmub_rb_cmd_dig1_dpia_control { 1599 struct dmub_cmd_header header; 1600 struct dmub_cmd_dig_dpia_control_data dpia_control; 1601 }; 1602 1603 /** 1604 * SET_CONFIG Command Payload 1605 */ 1606 struct set_config_cmd_payload { 1607 uint8_t msg_type; /* set config message type */ 1608 uint8_t msg_data; /* set config message data */ 1609 }; 1610 1611 /** 1612 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1613 */ 1614 struct dmub_cmd_set_config_control_data { 1615 struct set_config_cmd_payload cmd_pkt; 1616 uint8_t instance; /* DPIA instance */ 1617 uint8_t immed_status; /* Immediate status returned in case of error */ 1618 }; 1619 1620 /** 1621 * DMUB command structure for SET_CONFIG command. 1622 */ 1623 struct dmub_rb_cmd_set_config_access { 1624 struct dmub_cmd_header header; /* header */ 1625 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1626 }; 1627 1628 /** 1629 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1630 */ 1631 struct dmub_cmd_mst_alloc_slots_control_data { 1632 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1633 uint8_t instance; /* DPIA instance */ 1634 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1635 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1636 }; 1637 1638 /** 1639 * DMUB command structure for SET_ command. 1640 */ 1641 struct dmub_rb_cmd_set_mst_alloc_slots { 1642 struct dmub_cmd_header header; /* header */ 1643 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1644 }; 1645 1646 /** 1647 * DMUB command structure for DPIA HPD int enable control. 1648 */ 1649 struct dmub_rb_cmd_dpia_hpd_int_enable { 1650 struct dmub_cmd_header header; /* header */ 1651 uint32_t enable; /* dpia hpd interrupt enable */ 1652 }; 1653 1654 /** 1655 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1656 */ 1657 struct dmub_rb_cmd_dpphy_init { 1658 struct dmub_cmd_header header; /**< header */ 1659 uint8_t reserved[60]; /**< reserved bits */ 1660 }; 1661 1662 /** 1663 * enum dp_aux_request_action - DP AUX request command listing. 1664 * 1665 * 4 AUX request command bits are shifted to high nibble. 1666 */ 1667 enum dp_aux_request_action { 1668 /** I2C-over-AUX write request */ 1669 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1670 /** I2C-over-AUX read request */ 1671 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1672 /** I2C-over-AUX write status request */ 1673 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1674 /** I2C-over-AUX write request with MOT=1 */ 1675 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1676 /** I2C-over-AUX read request with MOT=1 */ 1677 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1678 /** I2C-over-AUX write status request with MOT=1 */ 1679 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1680 /** Native AUX write request */ 1681 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1682 /** Native AUX read request */ 1683 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1684 }; 1685 1686 /** 1687 * enum aux_return_code_type - DP AUX process return code listing. 1688 */ 1689 enum aux_return_code_type { 1690 /** AUX process succeeded */ 1691 AUX_RET_SUCCESS = 0, 1692 /** AUX process failed with unknown reason */ 1693 AUX_RET_ERROR_UNKNOWN, 1694 /** AUX process completed with invalid reply */ 1695 AUX_RET_ERROR_INVALID_REPLY, 1696 /** AUX process timed out */ 1697 AUX_RET_ERROR_TIMEOUT, 1698 /** HPD was low during AUX process */ 1699 AUX_RET_ERROR_HPD_DISCON, 1700 /** Failed to acquire AUX engine */ 1701 AUX_RET_ERROR_ENGINE_ACQUIRE, 1702 /** AUX request not supported */ 1703 AUX_RET_ERROR_INVALID_OPERATION, 1704 /** AUX process not available */ 1705 AUX_RET_ERROR_PROTOCOL_ERROR, 1706 }; 1707 1708 /** 1709 * enum aux_channel_type - DP AUX channel type listing. 1710 */ 1711 enum aux_channel_type { 1712 /** AUX thru Legacy DP AUX */ 1713 AUX_CHANNEL_LEGACY_DDC, 1714 /** AUX thru DPIA DP tunneling */ 1715 AUX_CHANNEL_DPIA 1716 }; 1717 1718 /** 1719 * struct aux_transaction_parameters - DP AUX request transaction data 1720 */ 1721 struct aux_transaction_parameters { 1722 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1723 uint8_t action; /**< enum dp_aux_request_action */ 1724 uint8_t length; /**< DP AUX request data length */ 1725 uint8_t reserved; /**< For future use */ 1726 uint32_t address; /**< DP AUX address */ 1727 uint8_t data[16]; /**< DP AUX write data */ 1728 }; 1729 1730 /** 1731 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1732 */ 1733 struct dmub_cmd_dp_aux_control_data { 1734 uint8_t instance; /**< AUX instance or DPIA instance */ 1735 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1736 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1737 uint8_t reserved0; /**< For future use */ 1738 uint16_t timeout; /**< timeout time in us */ 1739 uint16_t reserved1; /**< For future use */ 1740 enum aux_channel_type type; /**< enum aux_channel_type */ 1741 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1742 }; 1743 1744 /** 1745 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1746 */ 1747 struct dmub_rb_cmd_dp_aux_access { 1748 /** 1749 * Command header. 1750 */ 1751 struct dmub_cmd_header header; 1752 /** 1753 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1754 */ 1755 struct dmub_cmd_dp_aux_control_data aux_control; 1756 }; 1757 1758 /** 1759 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1760 */ 1761 struct dmub_rb_cmd_outbox1_enable { 1762 /** 1763 * Command header. 1764 */ 1765 struct dmub_cmd_header header; 1766 /** 1767 * enable: 0x0 -> disable outbox1 notification (default value) 1768 * 0x1 -> enable outbox1 notification 1769 */ 1770 uint32_t enable; 1771 }; 1772 1773 /* DP AUX Reply command - OutBox Cmd */ 1774 /** 1775 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1776 */ 1777 struct aux_reply_data { 1778 /** 1779 * Aux cmd 1780 */ 1781 uint8_t command; 1782 /** 1783 * Aux reply data length (max: 16 bytes) 1784 */ 1785 uint8_t length; 1786 /** 1787 * Alignment only 1788 */ 1789 uint8_t pad[2]; 1790 /** 1791 * Aux reply data 1792 */ 1793 uint8_t data[16]; 1794 }; 1795 1796 /** 1797 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1798 */ 1799 struct aux_reply_control_data { 1800 /** 1801 * Reserved for future use 1802 */ 1803 uint32_t handle; 1804 /** 1805 * Aux Instance 1806 */ 1807 uint8_t instance; 1808 /** 1809 * Aux transaction result: definition in enum aux_return_code_type 1810 */ 1811 uint8_t result; 1812 /** 1813 * Alignment only 1814 */ 1815 uint16_t pad; 1816 }; 1817 1818 /** 1819 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1820 */ 1821 struct dmub_rb_cmd_dp_aux_reply { 1822 /** 1823 * Command header. 1824 */ 1825 struct dmub_cmd_header header; 1826 /** 1827 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1828 */ 1829 struct aux_reply_control_data control; 1830 /** 1831 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1832 */ 1833 struct aux_reply_data reply_data; 1834 }; 1835 1836 /* DP HPD Notify command - OutBox Cmd */ 1837 /** 1838 * DP HPD Type 1839 */ 1840 enum dp_hpd_type { 1841 /** 1842 * Normal DP HPD 1843 */ 1844 DP_HPD = 0, 1845 /** 1846 * DP HPD short pulse 1847 */ 1848 DP_IRQ 1849 }; 1850 1851 /** 1852 * DP HPD Status 1853 */ 1854 enum dp_hpd_status { 1855 /** 1856 * DP_HPD status low 1857 */ 1858 DP_HPD_UNPLUG = 0, 1859 /** 1860 * DP_HPD status high 1861 */ 1862 DP_HPD_PLUG 1863 }; 1864 1865 /** 1866 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1867 */ 1868 struct dp_hpd_data { 1869 /** 1870 * DP HPD instance 1871 */ 1872 uint8_t instance; 1873 /** 1874 * HPD type 1875 */ 1876 uint8_t hpd_type; 1877 /** 1878 * HPD status: only for type: DP_HPD to indicate status 1879 */ 1880 uint8_t hpd_status; 1881 /** 1882 * Alignment only 1883 */ 1884 uint8_t pad; 1885 }; 1886 1887 /** 1888 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1889 */ 1890 struct dmub_rb_cmd_dp_hpd_notify { 1891 /** 1892 * Command header. 1893 */ 1894 struct dmub_cmd_header header; 1895 /** 1896 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1897 */ 1898 struct dp_hpd_data hpd_data; 1899 }; 1900 1901 /** 1902 * Definition of a SET_CONFIG reply from DPOA. 1903 */ 1904 enum set_config_status { 1905 SET_CONFIG_PENDING = 0, 1906 SET_CONFIG_ACK_RECEIVED, 1907 SET_CONFIG_RX_TIMEOUT, 1908 SET_CONFIG_UNKNOWN_ERROR, 1909 }; 1910 1911 /** 1912 * Definition of a set_config reply 1913 */ 1914 struct set_config_reply_control_data { 1915 uint8_t instance; /* DPIA Instance */ 1916 uint8_t status; /* Set Config reply */ 1917 uint16_t pad; /* Alignment */ 1918 }; 1919 1920 /** 1921 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1922 */ 1923 struct dmub_rb_cmd_dp_set_config_reply { 1924 struct dmub_cmd_header header; 1925 struct set_config_reply_control_data set_config_reply_control; 1926 }; 1927 1928 /** 1929 * Definition of a DPIA notification header 1930 */ 1931 struct dpia_notification_header { 1932 uint8_t instance; /**< DPIA Instance */ 1933 uint8_t reserved[3]; 1934 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1935 }; 1936 1937 /** 1938 * Definition of the common data struct of DPIA notification 1939 */ 1940 struct dpia_notification_common { 1941 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1942 - sizeof(struct dpia_notification_header)]; 1943 }; 1944 1945 /** 1946 * Definition of a DPIA notification data 1947 */ 1948 struct dpia_bw_allocation_notify_data { 1949 union { 1950 struct { 1951 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1952 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1953 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1954 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1955 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1956 uint16_t reserved: 11; /**< Reserved */ 1957 } bits; 1958 1959 uint16_t flags; 1960 }; 1961 1962 uint8_t cm_id; /**< CM ID */ 1963 uint8_t group_id; /**< Group ID */ 1964 uint8_t granularity; /**< BW Allocation Granularity */ 1965 uint8_t estimated_bw; /**< Estimated_BW */ 1966 uint8_t allocated_bw; /**< Allocated_BW */ 1967 uint8_t reserved; 1968 }; 1969 1970 /** 1971 * union dpia_notify_data_type - DPIA Notification in Outbox command 1972 */ 1973 union dpia_notification_data { 1974 /** 1975 * DPIA Notification for common data struct 1976 */ 1977 struct dpia_notification_common common_data; 1978 1979 /** 1980 * DPIA Notification for DP BW Allocation support 1981 */ 1982 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1983 }; 1984 1985 /** 1986 * Definition of a DPIA notification payload 1987 */ 1988 struct dpia_notification_payload { 1989 struct dpia_notification_header header; 1990 union dpia_notification_data data; /**< DPIA notification payload data */ 1991 }; 1992 1993 /** 1994 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1995 */ 1996 struct dmub_rb_cmd_dpia_notification { 1997 struct dmub_cmd_header header; /**< DPIA notification header */ 1998 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1999 }; 2000 2001 /** 2002 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2003 */ 2004 struct dmub_cmd_hpd_state_query_data { 2005 uint8_t instance; /**< HPD instance or DPIA instance */ 2006 uint8_t result; /**< For returning HPD state */ 2007 uint16_t pad; /** < Alignment */ 2008 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2009 enum aux_return_code_type status; /**< for returning the status of command */ 2010 }; 2011 2012 /** 2013 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2014 */ 2015 struct dmub_rb_cmd_query_hpd_state { 2016 /** 2017 * Command header. 2018 */ 2019 struct dmub_cmd_header header; 2020 /** 2021 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2022 */ 2023 struct dmub_cmd_hpd_state_query_data data; 2024 }; 2025 2026 /* 2027 * Command IDs should be treated as stable ABI. 2028 * Do not reuse or modify IDs. 2029 */ 2030 2031 /** 2032 * PSR command sub-types. 2033 */ 2034 enum dmub_cmd_psr_type { 2035 /** 2036 * Set PSR version support. 2037 */ 2038 DMUB_CMD__PSR_SET_VERSION = 0, 2039 /** 2040 * Copy driver-calculated parameters to PSR state. 2041 */ 2042 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2043 /** 2044 * Enable PSR. 2045 */ 2046 DMUB_CMD__PSR_ENABLE = 2, 2047 2048 /** 2049 * Disable PSR. 2050 */ 2051 DMUB_CMD__PSR_DISABLE = 3, 2052 2053 /** 2054 * Set PSR level. 2055 * PSR level is a 16-bit value dicated by driver that 2056 * will enable/disable different functionality. 2057 */ 2058 DMUB_CMD__PSR_SET_LEVEL = 4, 2059 2060 /** 2061 * Forces PSR enabled until an explicit PSR disable call. 2062 */ 2063 DMUB_CMD__PSR_FORCE_STATIC = 5, 2064 /** 2065 * Set vtotal in psr active for FreeSync PSR. 2066 */ 2067 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2068 /** 2069 * Set PSR power option 2070 */ 2071 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2072 }; 2073 2074 enum dmub_cmd_fams_type { 2075 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2076 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2077 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2078 /** 2079 * For SubVP set manual trigger in FW because it 2080 * triggers DRR_UPDATE_PENDING which SubVP relies 2081 * on (for any SubVP cases that use a DRR display) 2082 */ 2083 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2084 }; 2085 2086 /** 2087 * PSR versions. 2088 */ 2089 enum psr_version { 2090 /** 2091 * PSR version 1. 2092 */ 2093 PSR_VERSION_1 = 0, 2094 /** 2095 * Freesync PSR SU. 2096 */ 2097 PSR_VERSION_SU_1 = 1, 2098 /** 2099 * PSR not supported. 2100 */ 2101 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 2102 }; 2103 2104 /** 2105 * PHY Link rate for DP. 2106 */ 2107 enum phy_link_rate { 2108 /** 2109 * not supported. 2110 */ 2111 PHY_RATE_UNKNOWN = 0, 2112 /** 2113 * Rate_1 (RBR) - 1.62 Gbps/Lane 2114 */ 2115 PHY_RATE_162 = 1, 2116 /** 2117 * Rate_2 - 2.16 Gbps/Lane 2118 */ 2119 PHY_RATE_216 = 2, 2120 /** 2121 * Rate_3 - 2.43 Gbps/Lane 2122 */ 2123 PHY_RATE_243 = 3, 2124 /** 2125 * Rate_4 (HBR) - 2.70 Gbps/Lane 2126 */ 2127 PHY_RATE_270 = 4, 2128 /** 2129 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2130 */ 2131 PHY_RATE_324 = 5, 2132 /** 2133 * Rate_6 - 4.32 Gbps/Lane 2134 */ 2135 PHY_RATE_432 = 6, 2136 /** 2137 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2138 */ 2139 PHY_RATE_540 = 7, 2140 /** 2141 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2142 */ 2143 PHY_RATE_810 = 8, 2144 /** 2145 * UHBR10 - 10.0 Gbps/Lane 2146 */ 2147 PHY_RATE_1000 = 9, 2148 /** 2149 * UHBR13.5 - 13.5 Gbps/Lane 2150 */ 2151 PHY_RATE_1350 = 10, 2152 /** 2153 * UHBR10 - 20.0 Gbps/Lane 2154 */ 2155 PHY_RATE_2000 = 11, 2156 }; 2157 2158 /** 2159 * enum dmub_phy_fsm_state - PHY FSM states. 2160 * PHY FSM state to transit to during PSR enable/disable. 2161 */ 2162 enum dmub_phy_fsm_state { 2163 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2164 DMUB_PHY_FSM_RESET, 2165 DMUB_PHY_FSM_RESET_RELEASED, 2166 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2167 DMUB_PHY_FSM_INITIALIZED, 2168 DMUB_PHY_FSM_CALIBRATED, 2169 DMUB_PHY_FSM_CALIBRATED_LP, 2170 DMUB_PHY_FSM_CALIBRATED_PG, 2171 DMUB_PHY_FSM_POWER_DOWN, 2172 DMUB_PHY_FSM_PLL_EN, 2173 DMUB_PHY_FSM_TX_EN, 2174 DMUB_PHY_FSM_FAST_LP, 2175 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2176 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2177 DMUB_PHY_FSM_P2_PLL_OFF, 2178 DMUB_PHY_FSM_P2_PLL_ON, 2179 }; 2180 2181 /** 2182 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2183 */ 2184 struct dmub_cmd_psr_copy_settings_data { 2185 /** 2186 * Flags that can be set by driver to change some PSR behaviour. 2187 */ 2188 union dmub_psr_debug_flags debug; 2189 /** 2190 * 16-bit value dicated by driver that will enable/disable different functionality. 2191 */ 2192 uint16_t psr_level; 2193 /** 2194 * DPP HW instance. 2195 */ 2196 uint8_t dpp_inst; 2197 /** 2198 * MPCC HW instance. 2199 * Not used in dmub fw, 2200 * dmub fw will get active opp by reading odm registers. 2201 */ 2202 uint8_t mpcc_inst; 2203 /** 2204 * OPP HW instance. 2205 * Not used in dmub fw, 2206 * dmub fw will get active opp by reading odm registers. 2207 */ 2208 uint8_t opp_inst; 2209 /** 2210 * OTG HW instance. 2211 */ 2212 uint8_t otg_inst; 2213 /** 2214 * DIG FE HW instance. 2215 */ 2216 uint8_t digfe_inst; 2217 /** 2218 * DIG BE HW instance. 2219 */ 2220 uint8_t digbe_inst; 2221 /** 2222 * DP PHY HW instance. 2223 */ 2224 uint8_t dpphy_inst; 2225 /** 2226 * AUX HW instance. 2227 */ 2228 uint8_t aux_inst; 2229 /** 2230 * Determines if SMU optimzations are enabled/disabled. 2231 */ 2232 uint8_t smu_optimizations_en; 2233 /** 2234 * Unused. 2235 * TODO: Remove. 2236 */ 2237 uint8_t frame_delay; 2238 /** 2239 * If RFB setup time is greater than the total VBLANK time, 2240 * it is not possible for the sink to capture the video frame 2241 * in the same frame the SDP is sent. In this case, 2242 * the frame capture indication bit should be set and an extra 2243 * static frame should be transmitted to the sink. 2244 */ 2245 uint8_t frame_cap_ind; 2246 /** 2247 * Granularity of Y offset supported by sink. 2248 */ 2249 uint8_t su_y_granularity; 2250 /** 2251 * Indicates whether sink should start capturing 2252 * immediately following active scan line, 2253 * or starting with the 2nd active scan line. 2254 */ 2255 uint8_t line_capture_indication; 2256 /** 2257 * Multi-display optimizations are implemented on certain ASICs. 2258 */ 2259 uint8_t multi_disp_optimizations_en; 2260 /** 2261 * The last possible line SDP may be transmitted without violating 2262 * the RFB setup time or entering the active video frame. 2263 */ 2264 uint16_t init_sdp_deadline; 2265 /** 2266 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2267 */ 2268 uint8_t rate_control_caps ; 2269 /* 2270 * Force PSRSU always doing full frame update 2271 */ 2272 uint8_t force_ffu_mode; 2273 /** 2274 * Length of each horizontal line in us. 2275 */ 2276 uint32_t line_time_in_us; 2277 /** 2278 * FEC enable status in driver 2279 */ 2280 uint8_t fec_enable_status; 2281 /** 2282 * FEC re-enable delay when PSR exit. 2283 * unit is 100us, range form 0~255(0xFF). 2284 */ 2285 uint8_t fec_enable_delay_in100us; 2286 /** 2287 * PSR control version. 2288 */ 2289 uint8_t cmd_version; 2290 /** 2291 * Panel Instance. 2292 * Panel instance to identify which psr_state to use 2293 * Currently the support is only for 0 or 1 2294 */ 2295 uint8_t panel_inst; 2296 /* 2297 * DSC enable status in driver 2298 */ 2299 uint8_t dsc_enable_status; 2300 /* 2301 * Use FSM state for PSR power up/down 2302 */ 2303 uint8_t use_phy_fsm; 2304 /** 2305 * frame delay for frame re-lock 2306 */ 2307 uint8_t relock_delay_frame_cnt; 2308 /** 2309 * Explicit padding to 4 byte boundary. 2310 */ 2311 uint8_t pad3; 2312 /** 2313 * DSC Slice height. 2314 */ 2315 uint16_t dsc_slice_height; 2316 /** 2317 * Some panels request main link off before xth vertical line 2318 */ 2319 uint16_t poweroff_before_vertical_line; 2320 }; 2321 2322 /** 2323 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2324 */ 2325 struct dmub_rb_cmd_psr_copy_settings { 2326 /** 2327 * Command header. 2328 */ 2329 struct dmub_cmd_header header; 2330 /** 2331 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2332 */ 2333 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2334 }; 2335 2336 /** 2337 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2338 */ 2339 struct dmub_cmd_psr_set_level_data { 2340 /** 2341 * 16-bit value dicated by driver that will enable/disable different functionality. 2342 */ 2343 uint16_t psr_level; 2344 /** 2345 * PSR control version. 2346 */ 2347 uint8_t cmd_version; 2348 /** 2349 * Panel Instance. 2350 * Panel instance to identify which psr_state to use 2351 * Currently the support is only for 0 or 1 2352 */ 2353 uint8_t panel_inst; 2354 }; 2355 2356 /** 2357 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2358 */ 2359 struct dmub_rb_cmd_psr_set_level { 2360 /** 2361 * Command header. 2362 */ 2363 struct dmub_cmd_header header; 2364 /** 2365 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2366 */ 2367 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2368 }; 2369 2370 struct dmub_rb_cmd_psr_enable_data { 2371 /** 2372 * PSR control version. 2373 */ 2374 uint8_t cmd_version; 2375 /** 2376 * Panel Instance. 2377 * Panel instance to identify which psr_state to use 2378 * Currently the support is only for 0 or 1 2379 */ 2380 uint8_t panel_inst; 2381 /** 2382 * Phy state to enter. 2383 * Values to use are defined in dmub_phy_fsm_state 2384 */ 2385 uint8_t phy_fsm_state; 2386 /** 2387 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2388 * Set this using enum phy_link_rate. 2389 * This does not support HDMI/DP2 for now. 2390 */ 2391 uint8_t phy_rate; 2392 }; 2393 2394 /** 2395 * Definition of a DMUB_CMD__PSR_ENABLE command. 2396 * PSR enable/disable is controlled using the sub_type. 2397 */ 2398 struct dmub_rb_cmd_psr_enable { 2399 /** 2400 * Command header. 2401 */ 2402 struct dmub_cmd_header header; 2403 2404 struct dmub_rb_cmd_psr_enable_data data; 2405 }; 2406 2407 /** 2408 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2409 */ 2410 struct dmub_cmd_psr_set_version_data { 2411 /** 2412 * PSR version that FW should implement. 2413 */ 2414 enum psr_version version; 2415 /** 2416 * PSR control version. 2417 */ 2418 uint8_t cmd_version; 2419 /** 2420 * Panel Instance. 2421 * Panel instance to identify which psr_state to use 2422 * Currently the support is only for 0 or 1 2423 */ 2424 uint8_t panel_inst; 2425 /** 2426 * Explicit padding to 4 byte boundary. 2427 */ 2428 uint8_t pad[2]; 2429 }; 2430 2431 /** 2432 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2433 */ 2434 struct dmub_rb_cmd_psr_set_version { 2435 /** 2436 * Command header. 2437 */ 2438 struct dmub_cmd_header header; 2439 /** 2440 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2441 */ 2442 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2443 }; 2444 2445 struct dmub_cmd_psr_force_static_data { 2446 /** 2447 * PSR control version. 2448 */ 2449 uint8_t cmd_version; 2450 /** 2451 * Panel Instance. 2452 * Panel instance to identify which psr_state to use 2453 * Currently the support is only for 0 or 1 2454 */ 2455 uint8_t panel_inst; 2456 /** 2457 * Explicit padding to 4 byte boundary. 2458 */ 2459 uint8_t pad[2]; 2460 }; 2461 2462 /** 2463 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2464 */ 2465 struct dmub_rb_cmd_psr_force_static { 2466 /** 2467 * Command header. 2468 */ 2469 struct dmub_cmd_header header; 2470 /** 2471 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2472 */ 2473 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2474 }; 2475 2476 /** 2477 * PSR SU debug flags. 2478 */ 2479 union dmub_psr_su_debug_flags { 2480 /** 2481 * PSR SU debug flags. 2482 */ 2483 struct { 2484 /** 2485 * Update dirty rect in SW only. 2486 */ 2487 uint8_t update_dirty_rect_only : 1; 2488 /** 2489 * Reset the cursor/plane state before processing the call. 2490 */ 2491 uint8_t reset_state : 1; 2492 } bitfields; 2493 2494 /** 2495 * Union for debug flags. 2496 */ 2497 uint32_t u32All; 2498 }; 2499 2500 /** 2501 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2502 * This triggers a selective update for PSR SU. 2503 */ 2504 struct dmub_cmd_update_dirty_rect_data { 2505 /** 2506 * Dirty rects from OS. 2507 */ 2508 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2509 /** 2510 * PSR SU debug flags. 2511 */ 2512 union dmub_psr_su_debug_flags debug_flags; 2513 /** 2514 * OTG HW instance. 2515 */ 2516 uint8_t pipe_idx; 2517 /** 2518 * Number of dirty rects. 2519 */ 2520 uint8_t dirty_rect_count; 2521 /** 2522 * PSR control version. 2523 */ 2524 uint8_t cmd_version; 2525 /** 2526 * Panel Instance. 2527 * Panel instance to identify which psr_state to use 2528 * Currently the support is only for 0 or 1 2529 */ 2530 uint8_t panel_inst; 2531 }; 2532 2533 /** 2534 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2535 */ 2536 struct dmub_rb_cmd_update_dirty_rect { 2537 /** 2538 * Command header. 2539 */ 2540 struct dmub_cmd_header header; 2541 /** 2542 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2543 */ 2544 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2545 }; 2546 2547 /** 2548 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2549 */ 2550 union dmub_reg_cursor_control_cfg { 2551 struct { 2552 uint32_t cur_enable: 1; 2553 uint32_t reser0: 3; 2554 uint32_t cur_2x_magnify: 1; 2555 uint32_t reser1: 3; 2556 uint32_t mode: 3; 2557 uint32_t reser2: 5; 2558 uint32_t pitch: 2; 2559 uint32_t reser3: 6; 2560 uint32_t line_per_chunk: 5; 2561 uint32_t reser4: 3; 2562 } bits; 2563 uint32_t raw; 2564 }; 2565 struct dmub_cursor_position_cache_hubp { 2566 union dmub_reg_cursor_control_cfg cur_ctl; 2567 union dmub_reg_position_cfg { 2568 struct { 2569 uint32_t cur_x_pos: 16; 2570 uint32_t cur_y_pos: 16; 2571 } bits; 2572 uint32_t raw; 2573 } position; 2574 union dmub_reg_hot_spot_cfg { 2575 struct { 2576 uint32_t hot_x: 16; 2577 uint32_t hot_y: 16; 2578 } bits; 2579 uint32_t raw; 2580 } hot_spot; 2581 union dmub_reg_dst_offset_cfg { 2582 struct { 2583 uint32_t dst_x_offset: 13; 2584 uint32_t reserved: 19; 2585 } bits; 2586 uint32_t raw; 2587 } dst_offset; 2588 }; 2589 2590 union dmub_reg_cur0_control_cfg { 2591 struct { 2592 uint32_t cur0_enable: 1; 2593 uint32_t expansion_mode: 1; 2594 uint32_t reser0: 1; 2595 uint32_t cur0_rom_en: 1; 2596 uint32_t mode: 3; 2597 uint32_t reserved: 25; 2598 } bits; 2599 uint32_t raw; 2600 }; 2601 struct dmub_cursor_position_cache_dpp { 2602 union dmub_reg_cur0_control_cfg cur0_ctl; 2603 }; 2604 struct dmub_cursor_position_cfg { 2605 struct dmub_cursor_position_cache_hubp pHubp; 2606 struct dmub_cursor_position_cache_dpp pDpp; 2607 uint8_t pipe_idx; 2608 /* 2609 * Padding is required. To be 4 Bytes Aligned. 2610 */ 2611 uint8_t padding[3]; 2612 }; 2613 2614 struct dmub_cursor_attribute_cache_hubp { 2615 uint32_t SURFACE_ADDR_HIGH; 2616 uint32_t SURFACE_ADDR; 2617 union dmub_reg_cursor_control_cfg cur_ctl; 2618 union dmub_reg_cursor_size_cfg { 2619 struct { 2620 uint32_t width: 16; 2621 uint32_t height: 16; 2622 } bits; 2623 uint32_t raw; 2624 } size; 2625 union dmub_reg_cursor_settings_cfg { 2626 struct { 2627 uint32_t dst_y_offset: 8; 2628 uint32_t chunk_hdl_adjust: 2; 2629 uint32_t reserved: 22; 2630 } bits; 2631 uint32_t raw; 2632 } settings; 2633 }; 2634 struct dmub_cursor_attribute_cache_dpp { 2635 union dmub_reg_cur0_control_cfg cur0_ctl; 2636 }; 2637 struct dmub_cursor_attributes_cfg { 2638 struct dmub_cursor_attribute_cache_hubp aHubp; 2639 struct dmub_cursor_attribute_cache_dpp aDpp; 2640 }; 2641 2642 struct dmub_cmd_update_cursor_payload0 { 2643 /** 2644 * Cursor dirty rects. 2645 */ 2646 struct dmub_rect cursor_rect; 2647 /** 2648 * PSR SU debug flags. 2649 */ 2650 union dmub_psr_su_debug_flags debug_flags; 2651 /** 2652 * Cursor enable/disable. 2653 */ 2654 uint8_t enable; 2655 /** 2656 * OTG HW instance. 2657 */ 2658 uint8_t pipe_idx; 2659 /** 2660 * PSR control version. 2661 */ 2662 uint8_t cmd_version; 2663 /** 2664 * Panel Instance. 2665 * Panel instance to identify which psr_state to use 2666 * Currently the support is only for 0 or 1 2667 */ 2668 uint8_t panel_inst; 2669 /** 2670 * Cursor Position Register. 2671 * Registers contains Hubp & Dpp modules 2672 */ 2673 struct dmub_cursor_position_cfg position_cfg; 2674 }; 2675 2676 struct dmub_cmd_update_cursor_payload1 { 2677 struct dmub_cursor_attributes_cfg attribute_cfg; 2678 }; 2679 2680 union dmub_cmd_update_cursor_info_data { 2681 struct dmub_cmd_update_cursor_payload0 payload0; 2682 struct dmub_cmd_update_cursor_payload1 payload1; 2683 }; 2684 /** 2685 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2686 */ 2687 struct dmub_rb_cmd_update_cursor_info { 2688 /** 2689 * Command header. 2690 */ 2691 struct dmub_cmd_header header; 2692 /** 2693 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2694 */ 2695 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2696 }; 2697 2698 /** 2699 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2700 */ 2701 struct dmub_cmd_psr_set_vtotal_data { 2702 /** 2703 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2704 */ 2705 uint16_t psr_vtotal_idle; 2706 /** 2707 * PSR control version. 2708 */ 2709 uint8_t cmd_version; 2710 /** 2711 * Panel Instance. 2712 * Panel instance to identify which psr_state to use 2713 * Currently the support is only for 0 or 1 2714 */ 2715 uint8_t panel_inst; 2716 /* 2717 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2718 */ 2719 uint16_t psr_vtotal_su; 2720 /** 2721 * Explicit padding to 4 byte boundary. 2722 */ 2723 uint8_t pad2[2]; 2724 }; 2725 2726 /** 2727 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2728 */ 2729 struct dmub_rb_cmd_psr_set_vtotal { 2730 /** 2731 * Command header. 2732 */ 2733 struct dmub_cmd_header header; 2734 /** 2735 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2736 */ 2737 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2738 }; 2739 2740 /** 2741 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2742 */ 2743 struct dmub_cmd_psr_set_power_opt_data { 2744 /** 2745 * PSR control version. 2746 */ 2747 uint8_t cmd_version; 2748 /** 2749 * Panel Instance. 2750 * Panel instance to identify which psr_state to use 2751 * Currently the support is only for 0 or 1 2752 */ 2753 uint8_t panel_inst; 2754 /** 2755 * Explicit padding to 4 byte boundary. 2756 */ 2757 uint8_t pad[2]; 2758 /** 2759 * PSR power option 2760 */ 2761 uint32_t power_opt; 2762 }; 2763 2764 /** 2765 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2766 */ 2767 struct dmub_rb_cmd_psr_set_power_opt { 2768 /** 2769 * Command header. 2770 */ 2771 struct dmub_cmd_header header; 2772 /** 2773 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2774 */ 2775 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2776 }; 2777 2778 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 2779 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 2780 2781 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2782 # define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 2783 # define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2784 2785 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2786 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2787 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2788 2789 enum replay_state { 2790 REPLAY_STATE_0 = 0x0, 2791 REPLAY_STATE_1 = 0x10, 2792 REPLAY_STATE_1A = 0x11, 2793 REPLAY_STATE_2 = 0x20, 2794 REPLAY_STATE_3 = 0x30, 2795 REPLAY_STATE_3INIT = 0x31, 2796 REPLAY_STATE_4 = 0x40, 2797 REPLAY_STATE_4A = 0x41, 2798 REPLAY_STATE_4B = 0x42, 2799 REPLAY_STATE_4C = 0x43, 2800 REPLAY_STATE_4D = 0x44, 2801 REPLAY_STATE_4B_LOCKED = 0x4A, 2802 REPLAY_STATE_4C_UNLOCKED = 0x4B, 2803 REPLAY_STATE_5 = 0x50, 2804 REPLAY_STATE_5A = 0x51, 2805 REPLAY_STATE_5B = 0x52, 2806 REPLAY_STATE_5A_LOCKED = 0x5A, 2807 REPLAY_STATE_5B_UNLOCKED = 0x5B, 2808 REPLAY_STATE_6 = 0x60, 2809 REPLAY_STATE_6A = 0x61, 2810 REPLAY_STATE_6B = 0x62, 2811 REPLAY_STATE_INVALID = 0xFF, 2812 }; 2813 2814 /** 2815 * Replay command sub-types. 2816 */ 2817 enum dmub_cmd_replay_type { 2818 /** 2819 * Copy driver-calculated parameters to REPLAY state. 2820 */ 2821 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 2822 /** 2823 * Enable REPLAY. 2824 */ 2825 DMUB_CMD__REPLAY_ENABLE = 1, 2826 /** 2827 * Set Replay power option. 2828 */ 2829 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 2830 /** 2831 * Set coasting vtotal. 2832 */ 2833 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 2834 /** 2835 * Set power opt and coasting vtotal. 2836 */ 2837 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 2838 }; 2839 2840 /** 2841 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2842 */ 2843 struct dmub_cmd_replay_copy_settings_data { 2844 /** 2845 * Flags that can be set by driver to change some replay behaviour. 2846 */ 2847 union replay_debug_flags debug; 2848 2849 /** 2850 * @flags: Flags used to determine feature functionality. 2851 */ 2852 union replay_hw_flags flags; 2853 2854 /** 2855 * DPP HW instance. 2856 */ 2857 uint8_t dpp_inst; 2858 /** 2859 * OTG HW instance. 2860 */ 2861 uint8_t otg_inst; 2862 /** 2863 * DIG FE HW instance. 2864 */ 2865 uint8_t digfe_inst; 2866 /** 2867 * DIG BE HW instance. 2868 */ 2869 uint8_t digbe_inst; 2870 /** 2871 * AUX HW instance. 2872 */ 2873 uint8_t aux_inst; 2874 /** 2875 * Panel Instance. 2876 * Panel isntance to identify which psr_state to use 2877 * Currently the support is only for 0 or 1 2878 */ 2879 uint8_t panel_inst; 2880 /** 2881 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 2882 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 2883 */ 2884 uint8_t pixel_deviation_per_line; 2885 /** 2886 * @max_deviation_line: The max number of deviation line that can keep the timing 2887 * synchronized between the Source and Sink during Replay normal sleep mode. 2888 */ 2889 uint8_t max_deviation_line; 2890 /** 2891 * Length of each horizontal line in ns. 2892 */ 2893 uint32_t line_time_in_ns; 2894 /** 2895 * PHY instance. 2896 */ 2897 uint8_t dpphy_inst; 2898 /** 2899 * Determines if SMU optimzations are enabled/disabled. 2900 */ 2901 uint8_t smu_optimizations_en; 2902 /** 2903 * Determines if timing sync are enabled/disabled. 2904 */ 2905 uint8_t replay_timing_sync_supported; 2906 /* 2907 * Use FSM state for Replay power up/down 2908 */ 2909 uint8_t use_phy_fsm; 2910 }; 2911 2912 /** 2913 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2914 */ 2915 struct dmub_rb_cmd_replay_copy_settings { 2916 /** 2917 * Command header. 2918 */ 2919 struct dmub_cmd_header header; 2920 /** 2921 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2922 */ 2923 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 2924 }; 2925 2926 /** 2927 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 2928 */ 2929 enum replay_enable { 2930 /** 2931 * Disable REPLAY. 2932 */ 2933 REPLAY_DISABLE = 0, 2934 /** 2935 * Enable REPLAY. 2936 */ 2937 REPLAY_ENABLE = 1, 2938 }; 2939 2940 /** 2941 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 2942 */ 2943 struct dmub_rb_cmd_replay_enable_data { 2944 /** 2945 * Replay enable or disable. 2946 */ 2947 uint8_t enable; 2948 /** 2949 * Panel Instance. 2950 * Panel isntance to identify which replay_state to use 2951 * Currently the support is only for 0 or 1 2952 */ 2953 uint8_t panel_inst; 2954 /** 2955 * Phy state to enter. 2956 * Values to use are defined in dmub_phy_fsm_state 2957 */ 2958 uint8_t phy_fsm_state; 2959 /** 2960 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2961 * Set this using enum phy_link_rate. 2962 * This does not support HDMI/DP2 for now. 2963 */ 2964 uint8_t phy_rate; 2965 }; 2966 2967 /** 2968 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 2969 * Replay enable/disable is controlled using action in data. 2970 */ 2971 struct dmub_rb_cmd_replay_enable { 2972 /** 2973 * Command header. 2974 */ 2975 struct dmub_cmd_header header; 2976 2977 struct dmub_rb_cmd_replay_enable_data data; 2978 }; 2979 2980 /** 2981 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 2982 */ 2983 struct dmub_cmd_replay_set_power_opt_data { 2984 /** 2985 * Panel Instance. 2986 * Panel isntance to identify which replay_state to use 2987 * Currently the support is only for 0 or 1 2988 */ 2989 uint8_t panel_inst; 2990 /** 2991 * Explicit padding to 4 byte boundary. 2992 */ 2993 uint8_t pad[3]; 2994 /** 2995 * REPLAY power option 2996 */ 2997 uint32_t power_opt; 2998 }; 2999 3000 /** 3001 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3002 */ 3003 struct dmub_rb_cmd_replay_set_power_opt { 3004 /** 3005 * Command header. 3006 */ 3007 struct dmub_cmd_header header; 3008 /** 3009 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3010 */ 3011 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3012 }; 3013 3014 /** 3015 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3016 */ 3017 struct dmub_cmd_replay_set_coasting_vtotal_data { 3018 /** 3019 * 16-bit value dicated by driver that indicates the coasting vtotal. 3020 */ 3021 uint16_t coasting_vtotal; 3022 /** 3023 * REPLAY control version. 3024 */ 3025 uint8_t cmd_version; 3026 /** 3027 * Panel Instance. 3028 * Panel isntance to identify which replay_state to use 3029 * Currently the support is only for 0 or 1 3030 */ 3031 uint8_t panel_inst; 3032 }; 3033 3034 /** 3035 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3036 */ 3037 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3038 /** 3039 * Command header. 3040 */ 3041 struct dmub_cmd_header header; 3042 /** 3043 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3044 */ 3045 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3046 }; 3047 3048 /** 3049 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3050 */ 3051 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3052 /** 3053 * Command header. 3054 */ 3055 struct dmub_cmd_header header; 3056 /** 3057 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3058 */ 3059 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3060 /** 3061 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3062 */ 3063 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3064 }; 3065 3066 /** 3067 * Set of HW components that can be locked. 3068 * 3069 * Note: If updating with more HW components, fields 3070 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3071 */ 3072 union dmub_hw_lock_flags { 3073 /** 3074 * Set of HW components that can be locked. 3075 */ 3076 struct { 3077 /** 3078 * Lock/unlock OTG master update lock. 3079 */ 3080 uint8_t lock_pipe : 1; 3081 /** 3082 * Lock/unlock cursor. 3083 */ 3084 uint8_t lock_cursor : 1; 3085 /** 3086 * Lock/unlock global update lock. 3087 */ 3088 uint8_t lock_dig : 1; 3089 /** 3090 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3091 */ 3092 uint8_t triple_buffer_lock : 1; 3093 } bits; 3094 3095 /** 3096 * Union for HW Lock flags. 3097 */ 3098 uint8_t u8All; 3099 }; 3100 3101 /** 3102 * Instances of HW to be locked. 3103 * 3104 * Note: If updating with more HW components, fields 3105 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3106 */ 3107 struct dmub_hw_lock_inst_flags { 3108 /** 3109 * OTG HW instance for OTG master update lock. 3110 */ 3111 uint8_t otg_inst; 3112 /** 3113 * OPP instance for cursor lock. 3114 */ 3115 uint8_t opp_inst; 3116 /** 3117 * OTG HW instance for global update lock. 3118 * TODO: Remove, and re-use otg_inst. 3119 */ 3120 uint8_t dig_inst; 3121 /** 3122 * Explicit pad to 4 byte boundary. 3123 */ 3124 uint8_t pad; 3125 }; 3126 3127 /** 3128 * Clients that can acquire the HW Lock Manager. 3129 * 3130 * Note: If updating with more clients, fields in 3131 * dmub_inbox0_cmd_lock_hw must be updated to match. 3132 */ 3133 enum hw_lock_client { 3134 /** 3135 * Driver is the client of HW Lock Manager. 3136 */ 3137 HW_LOCK_CLIENT_DRIVER = 0, 3138 /** 3139 * PSR SU is the client of HW Lock Manager. 3140 */ 3141 HW_LOCK_CLIENT_PSR_SU = 1, 3142 HW_LOCK_CLIENT_SUBVP = 3, 3143 /** 3144 * Replay is the client of HW Lock Manager. 3145 */ 3146 HW_LOCK_CLIENT_REPLAY = 4, 3147 /** 3148 * Invalid client. 3149 */ 3150 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3151 }; 3152 3153 /** 3154 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3155 */ 3156 struct dmub_cmd_lock_hw_data { 3157 /** 3158 * Specifies the client accessing HW Lock Manager. 3159 */ 3160 enum hw_lock_client client; 3161 /** 3162 * HW instances to be locked. 3163 */ 3164 struct dmub_hw_lock_inst_flags inst_flags; 3165 /** 3166 * Which components to be locked. 3167 */ 3168 union dmub_hw_lock_flags hw_locks; 3169 /** 3170 * Specifies lock/unlock. 3171 */ 3172 uint8_t lock; 3173 /** 3174 * HW can be unlocked separately from releasing the HW Lock Mgr. 3175 * This flag is set if the client wishes to release the object. 3176 */ 3177 uint8_t should_release; 3178 /** 3179 * Explicit padding to 4 byte boundary. 3180 */ 3181 uint8_t pad; 3182 }; 3183 3184 /** 3185 * Definition of a DMUB_CMD__HW_LOCK command. 3186 * Command is used by driver and FW. 3187 */ 3188 struct dmub_rb_cmd_lock_hw { 3189 /** 3190 * Command header. 3191 */ 3192 struct dmub_cmd_header header; 3193 /** 3194 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3195 */ 3196 struct dmub_cmd_lock_hw_data lock_hw_data; 3197 }; 3198 3199 /** 3200 * ABM command sub-types. 3201 */ 3202 enum dmub_cmd_abm_type { 3203 /** 3204 * Initialize parameters for ABM algorithm. 3205 * Data is passed through an indirect buffer. 3206 */ 3207 DMUB_CMD__ABM_INIT_CONFIG = 0, 3208 /** 3209 * Set OTG and panel HW instance. 3210 */ 3211 DMUB_CMD__ABM_SET_PIPE = 1, 3212 /** 3213 * Set user requested backklight level. 3214 */ 3215 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3216 /** 3217 * Set ABM operating/aggression level. 3218 */ 3219 DMUB_CMD__ABM_SET_LEVEL = 3, 3220 /** 3221 * Set ambient light level. 3222 */ 3223 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 3224 /** 3225 * Enable/disable fractional duty cycle for backlight PWM. 3226 */ 3227 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 3228 3229 /** 3230 * unregister vertical interrupt after steady state is reached 3231 */ 3232 DMUB_CMD__ABM_PAUSE = 6, 3233 3234 /** 3235 * Save and Restore ABM state. On save we save parameters, and 3236 * on restore we update state with passed in data. 3237 */ 3238 DMUB_CMD__ABM_SAVE_RESTORE = 7, 3239 }; 3240 3241 /** 3242 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 3243 * Requirements: 3244 * - Padded explicitly to 32-bit boundary. 3245 * - Must ensure this structure matches the one on driver-side, 3246 * otherwise it won't be aligned. 3247 */ 3248 struct abm_config_table { 3249 /** 3250 * Gamma curve thresholds, used for crgb conversion. 3251 */ 3252 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 3253 /** 3254 * Gamma curve offsets, used for crgb conversion. 3255 */ 3256 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 3257 /** 3258 * Gamma curve slopes, used for crgb conversion. 3259 */ 3260 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 3261 /** 3262 * Custom backlight curve thresholds. 3263 */ 3264 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 3265 /** 3266 * Custom backlight curve offsets. 3267 */ 3268 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 3269 /** 3270 * Ambient light thresholds. 3271 */ 3272 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 3273 /** 3274 * Minimum programmable backlight. 3275 */ 3276 uint16_t min_abm_backlight; // 122B 3277 /** 3278 * Minimum reduction values. 3279 */ 3280 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 3281 /** 3282 * Maximum reduction values. 3283 */ 3284 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 3285 /** 3286 * Bright positive gain. 3287 */ 3288 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 3289 /** 3290 * Dark negative gain. 3291 */ 3292 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 3293 /** 3294 * Hybrid factor. 3295 */ 3296 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 3297 /** 3298 * Contrast factor. 3299 */ 3300 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 3301 /** 3302 * Deviation gain. 3303 */ 3304 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 3305 /** 3306 * Minimum knee. 3307 */ 3308 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 3309 /** 3310 * Maximum knee. 3311 */ 3312 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 3313 /** 3314 * Unused. 3315 */ 3316 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 3317 /** 3318 * Explicit padding to 4 byte boundary. 3319 */ 3320 uint8_t pad3[3]; // 229B 3321 /** 3322 * Backlight ramp reduction. 3323 */ 3324 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 3325 /** 3326 * Backlight ramp start. 3327 */ 3328 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 3329 }; 3330 3331 /** 3332 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3333 */ 3334 struct dmub_cmd_abm_set_pipe_data { 3335 /** 3336 * OTG HW instance. 3337 */ 3338 uint8_t otg_inst; 3339 3340 /** 3341 * Panel Control HW instance. 3342 */ 3343 uint8_t panel_inst; 3344 3345 /** 3346 * Controls how ABM will interpret a set pipe or set level command. 3347 */ 3348 uint8_t set_pipe_option; 3349 3350 /** 3351 * Unused. 3352 * TODO: Remove. 3353 */ 3354 uint8_t ramping_boundary; 3355 }; 3356 3357 /** 3358 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3359 */ 3360 struct dmub_rb_cmd_abm_set_pipe { 3361 /** 3362 * Command header. 3363 */ 3364 struct dmub_cmd_header header; 3365 3366 /** 3367 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3368 */ 3369 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 3370 }; 3371 3372 /** 3373 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3374 */ 3375 struct dmub_cmd_abm_set_backlight_data { 3376 /** 3377 * Number of frames to ramp to backlight user level. 3378 */ 3379 uint32_t frame_ramp; 3380 3381 /** 3382 * Requested backlight level from user. 3383 */ 3384 uint32_t backlight_user_level; 3385 3386 /** 3387 * ABM control version. 3388 */ 3389 uint8_t version; 3390 3391 /** 3392 * Panel Control HW instance mask. 3393 * Bit 0 is Panel Control HW instance 0. 3394 * Bit 1 is Panel Control HW instance 1. 3395 */ 3396 uint8_t panel_mask; 3397 3398 /** 3399 * Explicit padding to 4 byte boundary. 3400 */ 3401 uint8_t pad[2]; 3402 }; 3403 3404 /** 3405 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3406 */ 3407 struct dmub_rb_cmd_abm_set_backlight { 3408 /** 3409 * Command header. 3410 */ 3411 struct dmub_cmd_header header; 3412 3413 /** 3414 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3415 */ 3416 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 3417 }; 3418 3419 /** 3420 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3421 */ 3422 struct dmub_cmd_abm_set_level_data { 3423 /** 3424 * Set current ABM operating/aggression level. 3425 */ 3426 uint32_t level; 3427 3428 /** 3429 * ABM control version. 3430 */ 3431 uint8_t version; 3432 3433 /** 3434 * Panel Control HW instance mask. 3435 * Bit 0 is Panel Control HW instance 0. 3436 * Bit 1 is Panel Control HW instance 1. 3437 */ 3438 uint8_t panel_mask; 3439 3440 /** 3441 * Explicit padding to 4 byte boundary. 3442 */ 3443 uint8_t pad[2]; 3444 }; 3445 3446 /** 3447 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3448 */ 3449 struct dmub_rb_cmd_abm_set_level { 3450 /** 3451 * Command header. 3452 */ 3453 struct dmub_cmd_header header; 3454 3455 /** 3456 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3457 */ 3458 struct dmub_cmd_abm_set_level_data abm_set_level_data; 3459 }; 3460 3461 /** 3462 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3463 */ 3464 struct dmub_cmd_abm_set_ambient_level_data { 3465 /** 3466 * Ambient light sensor reading from OS. 3467 */ 3468 uint32_t ambient_lux; 3469 3470 /** 3471 * ABM control version. 3472 */ 3473 uint8_t version; 3474 3475 /** 3476 * Panel Control HW instance mask. 3477 * Bit 0 is Panel Control HW instance 0. 3478 * Bit 1 is Panel Control HW instance 1. 3479 */ 3480 uint8_t panel_mask; 3481 3482 /** 3483 * Explicit padding to 4 byte boundary. 3484 */ 3485 uint8_t pad[2]; 3486 }; 3487 3488 /** 3489 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3490 */ 3491 struct dmub_rb_cmd_abm_set_ambient_level { 3492 /** 3493 * Command header. 3494 */ 3495 struct dmub_cmd_header header; 3496 3497 /** 3498 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3499 */ 3500 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 3501 }; 3502 3503 /** 3504 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3505 */ 3506 struct dmub_cmd_abm_set_pwm_frac_data { 3507 /** 3508 * Enable/disable fractional duty cycle for backlight PWM. 3509 * TODO: Convert to uint8_t. 3510 */ 3511 uint32_t fractional_pwm; 3512 3513 /** 3514 * ABM control version. 3515 */ 3516 uint8_t version; 3517 3518 /** 3519 * Panel Control HW instance mask. 3520 * Bit 0 is Panel Control HW instance 0. 3521 * Bit 1 is Panel Control HW instance 1. 3522 */ 3523 uint8_t panel_mask; 3524 3525 /** 3526 * Explicit padding to 4 byte boundary. 3527 */ 3528 uint8_t pad[2]; 3529 }; 3530 3531 /** 3532 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3533 */ 3534 struct dmub_rb_cmd_abm_set_pwm_frac { 3535 /** 3536 * Command header. 3537 */ 3538 struct dmub_cmd_header header; 3539 3540 /** 3541 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3542 */ 3543 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 3544 }; 3545 3546 /** 3547 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3548 */ 3549 struct dmub_cmd_abm_init_config_data { 3550 /** 3551 * Location of indirect buffer used to pass init data to ABM. 3552 */ 3553 union dmub_addr src; 3554 3555 /** 3556 * Indirect buffer length. 3557 */ 3558 uint16_t bytes; 3559 3560 3561 /** 3562 * ABM control version. 3563 */ 3564 uint8_t version; 3565 3566 /** 3567 * Panel Control HW instance mask. 3568 * Bit 0 is Panel Control HW instance 0. 3569 * Bit 1 is Panel Control HW instance 1. 3570 */ 3571 uint8_t panel_mask; 3572 3573 /** 3574 * Explicit padding to 4 byte boundary. 3575 */ 3576 uint8_t pad[2]; 3577 }; 3578 3579 /** 3580 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3581 */ 3582 struct dmub_rb_cmd_abm_init_config { 3583 /** 3584 * Command header. 3585 */ 3586 struct dmub_cmd_header header; 3587 3588 /** 3589 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3590 */ 3591 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3592 }; 3593 3594 /** 3595 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3596 */ 3597 3598 struct dmub_cmd_abm_pause_data { 3599 3600 /** 3601 * Panel Control HW instance mask. 3602 * Bit 0 is Panel Control HW instance 0. 3603 * Bit 1 is Panel Control HW instance 1. 3604 */ 3605 uint8_t panel_mask; 3606 3607 /** 3608 * OTG hw instance 3609 */ 3610 uint8_t otg_inst; 3611 3612 /** 3613 * Enable or disable ABM pause 3614 */ 3615 uint8_t enable; 3616 3617 /** 3618 * Explicit padding to 4 byte boundary. 3619 */ 3620 uint8_t pad[1]; 3621 }; 3622 3623 3624 /** 3625 * Definition of a DMUB_CMD__ABM_PAUSE command. 3626 */ 3627 struct dmub_rb_cmd_abm_pause { 3628 /** 3629 * Command header. 3630 */ 3631 struct dmub_cmd_header header; 3632 3633 /** 3634 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3635 */ 3636 struct dmub_cmd_abm_pause_data abm_pause_data; 3637 }; 3638 3639 /** 3640 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 3641 */ 3642 struct dmub_rb_cmd_abm_save_restore { 3643 /** 3644 * Command header. 3645 */ 3646 struct dmub_cmd_header header; 3647 3648 /** 3649 * OTG hw instance 3650 */ 3651 uint8_t otg_inst; 3652 3653 /** 3654 * Enable or disable ABM pause 3655 */ 3656 uint8_t freeze; 3657 3658 /** 3659 * Explicit padding to 4 byte boundary. 3660 */ 3661 uint8_t debug; 3662 3663 /** 3664 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3665 */ 3666 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3667 }; 3668 3669 /** 3670 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3671 */ 3672 struct dmub_cmd_query_feature_caps_data { 3673 /** 3674 * DMUB feature capabilities. 3675 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3676 */ 3677 struct dmub_feature_caps feature_caps; 3678 }; 3679 3680 /** 3681 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3682 */ 3683 struct dmub_rb_cmd_query_feature_caps { 3684 /** 3685 * Command header. 3686 */ 3687 struct dmub_cmd_header header; 3688 /** 3689 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3690 */ 3691 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3692 }; 3693 3694 /** 3695 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3696 */ 3697 struct dmub_cmd_visual_confirm_color_data { 3698 /** 3699 * DMUB visual confirm color 3700 */ 3701 struct dmub_visual_confirm_color visual_confirm_color; 3702 }; 3703 3704 /** 3705 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3706 */ 3707 struct dmub_rb_cmd_get_visual_confirm_color { 3708 /** 3709 * Command header. 3710 */ 3711 struct dmub_cmd_header header; 3712 /** 3713 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3714 */ 3715 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3716 }; 3717 3718 /** 3719 * enum dmub_cmd_panel_cntl_type - Panel control command. 3720 */ 3721 enum dmub_cmd_panel_cntl_type { 3722 /** 3723 * Initializes embedded panel hardware blocks. 3724 */ 3725 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3726 /** 3727 * Queries backlight info for the embedded panel. 3728 */ 3729 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3730 }; 3731 3732 /** 3733 * struct dmub_cmd_panel_cntl_data - Panel control data. 3734 */ 3735 struct dmub_cmd_panel_cntl_data { 3736 uint32_t inst; /**< panel instance */ 3737 uint32_t current_backlight; /* in/out */ 3738 uint32_t bl_pwm_cntl; /* in/out */ 3739 uint32_t bl_pwm_period_cntl; /* in/out */ 3740 uint32_t bl_pwm_ref_div1; /* in/out */ 3741 uint8_t is_backlight_on : 1; /* in/out */ 3742 uint8_t is_powered_on : 1; /* in/out */ 3743 uint8_t padding[3]; 3744 uint32_t bl_pwm_ref_div2; /* in/out */ 3745 uint8_t reserved[4]; 3746 }; 3747 3748 /** 3749 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3750 */ 3751 struct dmub_rb_cmd_panel_cntl { 3752 struct dmub_cmd_header header; /**< header */ 3753 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3754 }; 3755 3756 struct dmub_optc_state { 3757 uint32_t v_total_max; 3758 uint32_t v_total_min; 3759 uint32_t tg_inst; 3760 }; 3761 3762 struct dmub_rb_cmd_drr_update { 3763 struct dmub_cmd_header header; 3764 struct dmub_optc_state dmub_optc_state_req; 3765 }; 3766 3767 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3768 uint32_t pix_clk_100hz; 3769 uint8_t max_ramp_step; 3770 uint8_t pipes; 3771 uint8_t min_refresh_in_hz; 3772 uint8_t pipe_count; 3773 uint8_t pipe_index[4]; 3774 }; 3775 3776 struct dmub_cmd_fw_assisted_mclk_switch_config { 3777 uint8_t fams_enabled; 3778 uint8_t visual_confirm_enabled; 3779 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3780 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3781 }; 3782 3783 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3784 struct dmub_cmd_header header; 3785 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3786 }; 3787 3788 /** 3789 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3790 */ 3791 struct dmub_cmd_lvtma_control_data { 3792 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3793 uint8_t bypass_panel_control_wait; 3794 uint8_t reserved_0[2]; /**< For future use */ 3795 uint8_t panel_inst; /**< LVTMA control instance */ 3796 uint8_t reserved_1[3]; /**< For future use */ 3797 }; 3798 3799 /** 3800 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3801 */ 3802 struct dmub_rb_cmd_lvtma_control { 3803 /** 3804 * Command header. 3805 */ 3806 struct dmub_cmd_header header; 3807 /** 3808 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3809 */ 3810 struct dmub_cmd_lvtma_control_data data; 3811 }; 3812 3813 /** 3814 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3815 */ 3816 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3817 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3818 uint8_t is_usb; /**< is phy is usb */ 3819 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3820 uint8_t is_dp4; /**< is dp in 4 lane */ 3821 }; 3822 3823 /** 3824 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3825 */ 3826 struct dmub_rb_cmd_transmitter_query_dp_alt { 3827 struct dmub_cmd_header header; /**< header */ 3828 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3829 }; 3830 3831 /** 3832 * Maximum number of bytes a chunk sent to DMUB for parsing 3833 */ 3834 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3835 3836 /** 3837 * Represent a chunk of CEA blocks sent to DMUB for parsing 3838 */ 3839 struct dmub_cmd_send_edid_cea { 3840 uint16_t offset; /**< offset into the CEA block */ 3841 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3842 uint16_t cea_total_length; /**< total length of the CEA block */ 3843 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3844 uint8_t pad[3]; /**< padding and for future expansion */ 3845 }; 3846 3847 /** 3848 * Result of VSDB parsing from CEA block 3849 */ 3850 struct dmub_cmd_edid_cea_amd_vsdb { 3851 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3852 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3853 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3854 uint16_t min_frame_rate; /**< Maximum frame rate */ 3855 uint16_t max_frame_rate; /**< Minimum frame rate */ 3856 }; 3857 3858 /** 3859 * Result of sending a CEA chunk 3860 */ 3861 struct dmub_cmd_edid_cea_ack { 3862 uint16_t offset; /**< offset of the chunk into the CEA block */ 3863 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3864 uint8_t pad; /**< padding and for future expansion */ 3865 }; 3866 3867 /** 3868 * Specify whether the result is an ACK/NACK or the parsing has finished 3869 */ 3870 enum dmub_cmd_edid_cea_reply_type { 3871 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3872 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3873 }; 3874 3875 /** 3876 * Definition of a DMUB_CMD__EDID_CEA command. 3877 */ 3878 struct dmub_rb_cmd_edid_cea { 3879 struct dmub_cmd_header header; /**< Command header */ 3880 union dmub_cmd_edid_cea_data { 3881 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3882 struct dmub_cmd_edid_cea_output { /**< output with results */ 3883 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3884 union { 3885 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3886 struct dmub_cmd_edid_cea_ack ack; 3887 }; 3888 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3889 } data; /**< Command data */ 3890 3891 }; 3892 3893 /** 3894 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3895 */ 3896 struct dmub_cmd_cable_id_input { 3897 uint8_t phy_inst; /**< phy inst for cable id data */ 3898 }; 3899 3900 /** 3901 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3902 */ 3903 struct dmub_cmd_cable_id_output { 3904 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3905 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3906 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3907 uint8_t RESERVED :2; /**< reserved means not defined */ 3908 }; 3909 3910 /** 3911 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3912 */ 3913 struct dmub_rb_cmd_get_usbc_cable_id { 3914 struct dmub_cmd_header header; /**< Command header */ 3915 /** 3916 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3917 */ 3918 union dmub_cmd_cable_id_data { 3919 struct dmub_cmd_cable_id_input input; /**< Input */ 3920 struct dmub_cmd_cable_id_output output; /**< Output */ 3921 uint8_t output_raw; /**< Raw data output */ 3922 } data; 3923 }; 3924 3925 /** 3926 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3927 */ 3928 enum dmub_cmd_secure_display_type { 3929 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3930 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3931 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3932 }; 3933 3934 /** 3935 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3936 */ 3937 struct dmub_rb_cmd_secure_display { 3938 struct dmub_cmd_header header; 3939 /** 3940 * Data passed from driver to dmub firmware. 3941 */ 3942 struct dmub_cmd_roi_info { 3943 uint16_t x_start; 3944 uint16_t x_end; 3945 uint16_t y_start; 3946 uint16_t y_end; 3947 uint8_t otg_id; 3948 uint8_t phy_id; 3949 } roi_info; 3950 }; 3951 3952 /** 3953 * union dmub_rb_cmd - DMUB inbox command. 3954 */ 3955 union dmub_rb_cmd { 3956 /** 3957 * Elements shared with all commands. 3958 */ 3959 struct dmub_rb_cmd_common cmd_common; 3960 /** 3961 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3962 */ 3963 struct dmub_rb_cmd_read_modify_write read_modify_write; 3964 /** 3965 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3966 */ 3967 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3968 /** 3969 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3970 */ 3971 struct dmub_rb_cmd_burst_write burst_write; 3972 /** 3973 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3974 */ 3975 struct dmub_rb_cmd_reg_wait reg_wait; 3976 /** 3977 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3978 */ 3979 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3980 /** 3981 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3982 */ 3983 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3984 /** 3985 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3986 */ 3987 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3988 /** 3989 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3990 */ 3991 struct dmub_rb_cmd_dpphy_init dpphy_init; 3992 /** 3993 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3994 */ 3995 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3996 /** 3997 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3998 */ 3999 struct dmub_rb_cmd_domain_control domain_control; 4000 /** 4001 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 4002 */ 4003 struct dmub_rb_cmd_psr_set_version psr_set_version; 4004 /** 4005 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 4006 */ 4007 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 4008 /** 4009 * Definition of a DMUB_CMD__PSR_ENABLE command. 4010 */ 4011 struct dmub_rb_cmd_psr_enable psr_enable; 4012 /** 4013 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 4014 */ 4015 struct dmub_rb_cmd_psr_set_level psr_set_level; 4016 /** 4017 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 4018 */ 4019 struct dmub_rb_cmd_psr_force_static psr_force_static; 4020 /** 4021 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 4022 */ 4023 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 4024 /** 4025 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4026 */ 4027 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 4028 /** 4029 * Definition of a DMUB_CMD__HW_LOCK command. 4030 * Command is used by driver and FW. 4031 */ 4032 struct dmub_rb_cmd_lock_hw lock_hw; 4033 /** 4034 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4035 */ 4036 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 4037 /** 4038 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4039 */ 4040 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 4041 /** 4042 * Definition of a DMUB_CMD__PLAT_54186_WA command. 4043 */ 4044 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 4045 /** 4046 * Definition of a DMUB_CMD__MALL command. 4047 */ 4048 struct dmub_rb_cmd_mall mall; 4049 /** 4050 * Definition of a DMUB_CMD__CAB command. 4051 */ 4052 struct dmub_rb_cmd_cab_for_ss cab; 4053 4054 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 4055 4056 /** 4057 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 4058 */ 4059 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 4060 4061 /** 4062 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 4063 */ 4064 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 4065 4066 /** 4067 * Definition of DMUB_CMD__PANEL_CNTL commands. 4068 */ 4069 struct dmub_rb_cmd_panel_cntl panel_cntl; 4070 /** 4071 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4072 */ 4073 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 4074 4075 /** 4076 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4077 */ 4078 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 4079 4080 /** 4081 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4082 */ 4083 struct dmub_rb_cmd_abm_set_level abm_set_level; 4084 4085 /** 4086 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4087 */ 4088 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 4089 4090 /** 4091 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4092 */ 4093 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 4094 4095 /** 4096 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4097 */ 4098 struct dmub_rb_cmd_abm_init_config abm_init_config; 4099 4100 /** 4101 * Definition of a DMUB_CMD__ABM_PAUSE command. 4102 */ 4103 struct dmub_rb_cmd_abm_pause abm_pause; 4104 4105 /** 4106 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4107 */ 4108 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 4109 4110 /** 4111 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 4112 */ 4113 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 4114 4115 /** 4116 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 4117 */ 4118 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 4119 4120 /** 4121 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4122 */ 4123 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 4124 4125 /** 4126 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4127 */ 4128 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 4129 struct dmub_rb_cmd_drr_update drr_update; 4130 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 4131 4132 /** 4133 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4134 */ 4135 struct dmub_rb_cmd_lvtma_control lvtma_control; 4136 /** 4137 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4138 */ 4139 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 4140 /** 4141 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 4142 */ 4143 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 4144 /** 4145 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 4146 */ 4147 struct dmub_rb_cmd_set_config_access set_config_access; 4148 /** 4149 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 4150 */ 4151 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 4152 /** 4153 * Definition of a DMUB_CMD__EDID_CEA command. 4154 */ 4155 struct dmub_rb_cmd_edid_cea edid_cea; 4156 /** 4157 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 4158 */ 4159 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 4160 4161 /** 4162 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 4163 */ 4164 struct dmub_rb_cmd_query_hpd_state query_hpd; 4165 /** 4166 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 4167 */ 4168 struct dmub_rb_cmd_secure_display secure_display; 4169 4170 /** 4171 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 4172 */ 4173 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 4174 /** 4175 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 4176 */ 4177 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 4178 /* 4179 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4180 */ 4181 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 4182 /** 4183 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4184 */ 4185 struct dmub_rb_cmd_replay_enable replay_enable; 4186 /** 4187 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4188 */ 4189 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 4190 /** 4191 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4192 */ 4193 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 4194 /** 4195 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4196 */ 4197 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 4198 }; 4199 4200 /** 4201 * union dmub_rb_out_cmd - Outbox command 4202 */ 4203 union dmub_rb_out_cmd { 4204 /** 4205 * Parameters common to every command. 4206 */ 4207 struct dmub_rb_cmd_common cmd_common; 4208 /** 4209 * AUX reply command. 4210 */ 4211 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 4212 /** 4213 * HPD notify command. 4214 */ 4215 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 4216 /** 4217 * SET_CONFIG reply command. 4218 */ 4219 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 4220 /** 4221 * DPIA notification command. 4222 */ 4223 struct dmub_rb_cmd_dpia_notification dpia_notification; 4224 }; 4225 #pragma pack(pop) 4226 4227 4228 //============================================================================== 4229 //</DMUB_CMD>=================================================================== 4230 //============================================================================== 4231 //< DMUB_RB>==================================================================== 4232 //============================================================================== 4233 4234 #if defined(__cplusplus) 4235 extern "C" { 4236 #endif 4237 4238 /** 4239 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 4240 */ 4241 struct dmub_rb_init_params { 4242 void *ctx; /**< Caller provided context pointer */ 4243 void *base_address; /**< CPU base address for ring's data */ 4244 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4245 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 4246 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 4247 }; 4248 4249 /** 4250 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 4251 */ 4252 struct dmub_rb { 4253 void *base_address; /**< CPU address for the ring's data */ 4254 uint32_t rptr; /**< Read pointer for consumer in bytes */ 4255 uint32_t wrpt; /**< Write pointer for producer in bytes */ 4256 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4257 4258 void *ctx; /**< Caller provided context pointer */ 4259 void *dmub; /**< Pointer to the DMUB interface */ 4260 }; 4261 4262 /** 4263 * @brief Checks if the ringbuffer is empty. 4264 * 4265 * @param rb DMUB Ringbuffer 4266 * @return true if empty 4267 * @return false otherwise 4268 */ 4269 static inline bool dmub_rb_empty(struct dmub_rb *rb) 4270 { 4271 return (rb->wrpt == rb->rptr); 4272 } 4273 4274 /** 4275 * @brief Checks if the ringbuffer is full 4276 * 4277 * @param rb DMUB Ringbuffer 4278 * @return true if full 4279 * @return false otherwise 4280 */ 4281 static inline bool dmub_rb_full(struct dmub_rb *rb) 4282 { 4283 uint32_t data_count; 4284 4285 if (rb->wrpt >= rb->rptr) 4286 data_count = rb->wrpt - rb->rptr; 4287 else 4288 data_count = rb->capacity - (rb->rptr - rb->wrpt); 4289 4290 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 4291 } 4292 4293 /** 4294 * @brief Pushes a command into the ringbuffer 4295 * 4296 * @param rb DMUB ringbuffer 4297 * @param cmd The command to push 4298 * @return true if the ringbuffer was not full 4299 * @return false otherwise 4300 */ 4301 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 4302 const union dmub_rb_cmd *cmd) 4303 { 4304 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 4305 const uint64_t *src = (const uint64_t *)cmd; 4306 uint8_t i; 4307 4308 if (dmub_rb_full(rb)) 4309 return false; 4310 4311 // copying data 4312 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4313 *dst++ = *src++; 4314 4315 rb->wrpt += DMUB_RB_CMD_SIZE; 4316 4317 if (rb->wrpt >= rb->capacity) 4318 rb->wrpt %= rb->capacity; 4319 4320 return true; 4321 } 4322 4323 /** 4324 * @brief Pushes a command into the DMUB outbox ringbuffer 4325 * 4326 * @param rb DMUB outbox ringbuffer 4327 * @param cmd Outbox command 4328 * @return true if not full 4329 * @return false otherwise 4330 */ 4331 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 4332 const union dmub_rb_out_cmd *cmd) 4333 { 4334 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 4335 const uint8_t *src = (const uint8_t *)cmd; 4336 4337 if (dmub_rb_full(rb)) 4338 return false; 4339 4340 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 4341 4342 rb->wrpt += DMUB_RB_CMD_SIZE; 4343 4344 if (rb->wrpt >= rb->capacity) 4345 rb->wrpt %= rb->capacity; 4346 4347 return true; 4348 } 4349 4350 /** 4351 * @brief Returns the next unprocessed command in the ringbuffer. 4352 * 4353 * @param rb DMUB ringbuffer 4354 * @param cmd The command to return 4355 * @return true if not empty 4356 * @return false otherwise 4357 */ 4358 static inline bool dmub_rb_front(struct dmub_rb *rb, 4359 union dmub_rb_cmd **cmd) 4360 { 4361 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 4362 4363 if (dmub_rb_empty(rb)) 4364 return false; 4365 4366 *cmd = (union dmub_rb_cmd *)rb_cmd; 4367 4368 return true; 4369 } 4370 4371 /** 4372 * @brief Determines the next ringbuffer offset. 4373 * 4374 * @param rb DMUB inbox ringbuffer 4375 * @param num_cmds Number of commands 4376 * @param next_rptr The next offset in the ringbuffer 4377 */ 4378 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 4379 uint32_t num_cmds, 4380 uint32_t *next_rptr) 4381 { 4382 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 4383 4384 if (*next_rptr >= rb->capacity) 4385 *next_rptr %= rb->capacity; 4386 } 4387 4388 /** 4389 * @brief Returns a pointer to a command in the inbox. 4390 * 4391 * @param rb DMUB inbox ringbuffer 4392 * @param cmd The inbox command to return 4393 * @param rptr The ringbuffer offset 4394 * @return true if not empty 4395 * @return false otherwise 4396 */ 4397 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 4398 union dmub_rb_cmd **cmd, 4399 uint32_t rptr) 4400 { 4401 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 4402 4403 if (dmub_rb_empty(rb)) 4404 return false; 4405 4406 *cmd = (union dmub_rb_cmd *)rb_cmd; 4407 4408 return true; 4409 } 4410 4411 /** 4412 * @brief Returns the next unprocessed command in the outbox. 4413 * 4414 * @param rb DMUB outbox ringbuffer 4415 * @param cmd The outbox command to return 4416 * @return true if not empty 4417 * @return false otherwise 4418 */ 4419 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 4420 union dmub_rb_out_cmd *cmd) 4421 { 4422 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 4423 uint64_t *dst = (uint64_t *)cmd; 4424 uint8_t i; 4425 4426 if (dmub_rb_empty(rb)) 4427 return false; 4428 4429 // copying data 4430 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4431 *dst++ = *src++; 4432 4433 return true; 4434 } 4435 4436 /** 4437 * @brief Removes the front entry in the ringbuffer. 4438 * 4439 * @param rb DMUB ringbuffer 4440 * @return true if the command was removed 4441 * @return false if there were no commands 4442 */ 4443 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 4444 { 4445 if (dmub_rb_empty(rb)) 4446 return false; 4447 4448 rb->rptr += DMUB_RB_CMD_SIZE; 4449 4450 if (rb->rptr >= rb->capacity) 4451 rb->rptr %= rb->capacity; 4452 4453 return true; 4454 } 4455 4456 /** 4457 * @brief Flushes commands in the ringbuffer to framebuffer memory. 4458 * 4459 * Avoids a race condition where DMCUB accesses memory while 4460 * there are still writes in flight to framebuffer. 4461 * 4462 * @param rb DMUB ringbuffer 4463 */ 4464 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 4465 { 4466 uint32_t rptr = rb->rptr; 4467 uint32_t wptr = rb->wrpt; 4468 4469 while (rptr != wptr) { 4470 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 4471 uint8_t i; 4472 4473 /* Don't remove this. 4474 * The contents need to actually be read from the ring buffer 4475 * for this function to be effective. 4476 */ 4477 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4478 (void)READ_ONCE(*data++); 4479 4480 rptr += DMUB_RB_CMD_SIZE; 4481 if (rptr >= rb->capacity) 4482 rptr %= rb->capacity; 4483 } 4484 } 4485 4486 /** 4487 * @brief Initializes a DMCUB ringbuffer 4488 * 4489 * @param rb DMUB ringbuffer 4490 * @param init_params initial configuration for the ringbuffer 4491 */ 4492 static inline void dmub_rb_init(struct dmub_rb *rb, 4493 struct dmub_rb_init_params *init_params) 4494 { 4495 rb->base_address = init_params->base_address; 4496 rb->capacity = init_params->capacity; 4497 rb->rptr = init_params->read_ptr; 4498 rb->wrpt = init_params->write_ptr; 4499 } 4500 4501 /** 4502 * @brief Copies output data from in/out commands into the given command. 4503 * 4504 * @param rb DMUB ringbuffer 4505 * @param cmd Command to copy data into 4506 */ 4507 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 4508 union dmub_rb_cmd *cmd) 4509 { 4510 // Copy rb entry back into command 4511 uint8_t *rd_ptr = (rb->rptr == 0) ? 4512 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 4513 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 4514 4515 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 4516 } 4517 4518 #if defined(__cplusplus) 4519 } 4520 #endif 4521 4522 //============================================================================== 4523 //</DMUB_RB>==================================================================== 4524 //============================================================================== 4525 4526 #endif /* _DMUB_CMD_H_ */ 4527