1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /* Maximum number of SubVP streams */ 85 #define DMUB_MAX_SUBVP_STREAMS 2 86 87 /* Define max FPO streams as 4 for now. Current implementation today 88 * only supports 1, but could be more in the future. Reduce array 89 * size to ensure the command size remains less than 64 bytes if 90 * adding new fields. 91 */ 92 #define DMUB_MAX_FPO_STREAMS 4 93 94 /* Maximum number of streams on any ASIC. */ 95 #define DMUB_MAX_STREAMS 6 96 97 /* Maximum number of planes on any ASIC. */ 98 #define DMUB_MAX_PLANES 6 99 100 /* Maximum number of phantom planes on any ASIC */ 101 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 102 103 /* Trace buffer offset for entry */ 104 #define TRACE_BUFFER_ENTRY_OFFSET 16 105 106 /** 107 * Maximum number of dirty rects supported by FW. 108 */ 109 #define DMUB_MAX_DIRTY_RECTS 3 110 111 /** 112 * 113 * PSR control version legacy 114 */ 115 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 116 /** 117 * PSR control version with multi edp support 118 */ 119 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 120 121 122 /** 123 * ABM control version legacy 124 */ 125 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 126 127 /** 128 * ABM control version with multi edp support 129 */ 130 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 131 132 /** 133 * Physical framebuffer address location, 64-bit. 134 */ 135 #ifndef PHYSICAL_ADDRESS_LOC 136 #define PHYSICAL_ADDRESS_LOC union large_integer 137 #endif 138 139 /** 140 * OS/FW agnostic memcpy 141 */ 142 #ifndef dmub_memcpy 143 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 144 #endif 145 146 /** 147 * OS/FW agnostic memset 148 */ 149 #ifndef dmub_memset 150 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 151 #endif 152 153 #if defined(__cplusplus) 154 extern "C" { 155 #endif 156 157 /** 158 * OS/FW agnostic udelay 159 */ 160 #ifndef dmub_udelay 161 #define dmub_udelay(microseconds) udelay(microseconds) 162 #endif 163 164 #pragma pack(push, 1) 165 #define ABM_NUM_OF_ACE_SEGMENTS 5 166 167 union abm_flags { 168 struct { 169 /** 170 * @abm_enabled: Indicates if ABM is enabled. 171 */ 172 unsigned int abm_enabled : 1; 173 174 /** 175 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 176 */ 177 unsigned int disable_abm_requested : 1; 178 179 /** 180 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 181 */ 182 unsigned int disable_abm_immediately : 1; 183 184 /** 185 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 186 * to be disabled immediately and keep gain. 187 */ 188 unsigned int disable_abm_immediate_keep_gain : 1; 189 190 /** 191 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 192 */ 193 unsigned int fractional_pwm : 1; 194 195 /** 196 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 197 * of user backlight level. 198 */ 199 unsigned int abm_gradual_bl_change : 1; 200 201 /** 202 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 203 */ 204 unsigned int abm_new_frame : 1; 205 } bitfields; 206 207 unsigned int u32All; 208 }; 209 210 struct abm_save_restore { 211 /** 212 * @flags: Misc. ABM flags. 213 */ 214 union abm_flags flags; 215 216 /** 217 * @pause: true: pause ABM and get state 218 * false: unpause ABM after setting state 219 */ 220 uint32_t pause; 221 222 /** 223 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 224 */ 225 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 226 227 /** 228 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 229 */ 230 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 231 232 /** 233 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 234 */ 235 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 236 237 238 /** 239 * @knee_threshold: Current x-position of ACE knee (u0.16). 240 */ 241 uint32_t knee_threshold; 242 /** 243 * @current_gain: Current backlight reduction (u16.16). 244 */ 245 uint32_t current_gain; 246 /** 247 * @curr_bl_level: Current actual backlight level converging to target backlight level. 248 */ 249 uint16_t curr_bl_level; 250 251 /** 252 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 253 */ 254 uint16_t curr_user_bl_level; 255 256 }; 257 258 /** 259 * union dmub_addr - DMUB physical/virtual 64-bit address. 260 */ 261 union dmub_addr { 262 struct { 263 uint32_t low_part; /**< Lower 32 bits */ 264 uint32_t high_part; /**< Upper 32 bits */ 265 } u; /*<< Low/high bit access */ 266 uint64_t quad_part; /*<< 64 bit address */ 267 }; 268 #pragma pack(pop) 269 270 /** 271 * Dirty rect definition. 272 */ 273 struct dmub_rect { 274 /** 275 * Dirty rect x offset. 276 */ 277 uint32_t x; 278 279 /** 280 * Dirty rect y offset. 281 */ 282 uint32_t y; 283 284 /** 285 * Dirty rect width. 286 */ 287 uint32_t width; 288 289 /** 290 * Dirty rect height. 291 */ 292 uint32_t height; 293 }; 294 295 /** 296 * Flags that can be set by driver to change some PSR behaviour. 297 */ 298 union dmub_psr_debug_flags { 299 /** 300 * Debug flags. 301 */ 302 struct { 303 /** 304 * Enable visual confirm in FW. 305 */ 306 uint32_t visual_confirm : 1; 307 308 /** 309 * Force all selective updates to bw full frame updates. 310 */ 311 uint32_t force_full_frame_update : 1; 312 313 /** 314 * Use HW Lock Mgr object to do HW locking in FW. 315 */ 316 uint32_t use_hw_lock_mgr : 1; 317 318 /** 319 * Use TPS3 signal when restore main link. 320 */ 321 uint32_t force_wakeup_by_tps3 : 1; 322 323 /** 324 * Back to back flip, therefore cannot power down PHY 325 */ 326 uint32_t back_to_back_flip : 1; 327 328 } bitfields; 329 330 /** 331 * Union for debug flags. 332 */ 333 uint32_t u32All; 334 }; 335 336 /** 337 * Flags that can be set by driver to change some Replay behaviour. 338 */ 339 union replay_debug_flags { 340 struct { 341 /** 342 * 0x1 (bit 0) 343 * Enable visual confirm in FW. 344 */ 345 uint32_t visual_confirm : 1; 346 347 /** 348 * 0x2 (bit 1) 349 * @skip_crc: Set if need to skip CRC. 350 */ 351 uint32_t skip_crc : 1; 352 353 /** 354 * 0x4 (bit 2) 355 * @force_link_power_on: Force disable ALPM control 356 */ 357 uint32_t force_link_power_on : 1; 358 359 /** 360 * 0x8 (bit 3) 361 * @force_phy_power_on: Force phy power on 362 */ 363 uint32_t force_phy_power_on : 1; 364 365 /** 366 * 0x10 (bit 4) 367 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 368 */ 369 uint32_t timing_resync_disabled : 1; 370 371 /** 372 * 0x20 (bit 5) 373 * @skip_crtc_disabled: CRTC disable skipped 374 */ 375 uint32_t skip_crtc_disabled : 1; 376 377 /** 378 * 0x40 (bit 6) 379 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 380 */ 381 uint32_t force_defer_one_frame_update : 1; 382 383 /** 384 * 0x80 (bit 7) 385 * @disable_delay_alpm_on: Force disable delay alpm on 386 */ 387 uint32_t disable_delay_alpm_on : 1; 388 389 /** 390 * 0x100 (bit 8) 391 * @disable_desync_error_check: Force disable desync error check 392 */ 393 uint32_t disable_desync_error_check : 1; 394 395 /** 396 * 0x200 (bit 9) 397 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 398 */ 399 uint32_t force_self_update_when_abm_non_steady : 1; 400 401 /** 402 * 0x400 (bit 10) 403 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 404 * If we enter IPS2, the Visual confirm bar will change to yellow 405 */ 406 uint32_t enable_ips_visual_confirm : 1; 407 408 /** 409 * 0x800 (bit 11) 410 * @enable_ips_residency_profiling: Enable IPS residency profiling 411 */ 412 uint32_t enable_ips_residency_profiling : 1; 413 414 uint32_t reserved : 20; 415 } bitfields; 416 417 uint32_t u32All; 418 }; 419 420 union replay_hw_flags { 421 struct { 422 /** 423 * @allow_alpm_fw_standby_mode: To indicate whether the 424 * ALPM FW standby mode is allowed 425 */ 426 uint32_t allow_alpm_fw_standby_mode : 1; 427 428 /* 429 * @dsc_enable_status: DSC enable status in driver 430 */ 431 uint32_t dsc_enable_status : 1; 432 433 /** 434 * @fec_enable_status: receive fec enable/disable status from driver 435 */ 436 uint32_t fec_enable_status : 1; 437 438 /* 439 * @smu_optimizations_en: SMU power optimization. 440 * Only when active display is Replay capable and display enters Replay. 441 * Trigger interrupt to SMU to powerup/down. 442 */ 443 uint32_t smu_optimizations_en : 1; 444 445 /** 446 * @phy_power_state: Indicates current phy power state 447 */ 448 uint32_t phy_power_state : 1; 449 450 /** 451 * @link_power_state: Indicates current link power state 452 */ 453 uint32_t link_power_state : 1; 454 /** 455 * Use TPS3 signal when restore main link. 456 */ 457 uint32_t force_wakeup_by_tps3 : 1; 458 } bitfields; 459 460 uint32_t u32All; 461 }; 462 463 /** 464 * DMUB feature capabilities. 465 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 466 */ 467 struct dmub_feature_caps { 468 /** 469 * Max PSR version supported by FW. 470 */ 471 uint8_t psr; 472 uint8_t fw_assisted_mclk_switch_ver; 473 uint8_t reserved[4]; 474 uint8_t subvp_psr_support; 475 uint8_t gecc_enable; 476 uint8_t replay_supported; 477 uint8_t replay_reserved[3]; 478 }; 479 480 struct dmub_visual_confirm_color { 481 /** 482 * Maximum 10 bits color value 483 */ 484 uint16_t color_r_cr; 485 uint16_t color_g_y; 486 uint16_t color_b_cb; 487 uint16_t panel_inst; 488 }; 489 490 #if defined(__cplusplus) 491 } 492 #endif 493 494 //============================================================================== 495 //</DMUB_TYPES>================================================================= 496 //============================================================================== 497 //< DMUB_META>================================================================== 498 //============================================================================== 499 #pragma pack(push, 1) 500 501 /* Magic value for identifying dmub_fw_meta_info */ 502 #define DMUB_FW_META_MAGIC 0x444D5542 503 504 /* Offset from the end of the file to the dmub_fw_meta_info */ 505 #define DMUB_FW_META_OFFSET 0x24 506 507 /** 508 * struct dmub_fw_meta_info - metadata associated with fw binary 509 * 510 * NOTE: This should be considered a stable API. Fields should 511 * not be repurposed or reordered. New fields should be 512 * added instead to extend the structure. 513 * 514 * @magic_value: magic value identifying DMUB firmware meta info 515 * @fw_region_size: size of the firmware state region 516 * @trace_buffer_size: size of the tracebuffer region 517 * @fw_version: the firmware version information 518 * @dal_fw: 1 if the firmware is DAL 519 * @shared_state_size: size of the shared state region in bytes 520 * @shared_state_features: number of shared state features 521 */ 522 struct dmub_fw_meta_info { 523 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 524 uint32_t fw_region_size; /**< size of the firmware state region */ 525 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 526 uint32_t fw_version; /**< the firmware version information */ 527 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 528 uint8_t reserved[3]; /**< padding bits */ 529 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 530 uint16_t shared_state_features; /**< number of shared state features */ 531 uint16_t reserved2; /**< padding bytes */ 532 }; 533 534 /** 535 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 536 */ 537 union dmub_fw_meta { 538 struct dmub_fw_meta_info info; /**< metadata info */ 539 uint8_t reserved[64]; /**< padding bits */ 540 }; 541 542 #pragma pack(pop) 543 544 //============================================================================== 545 //< DMUB Trace Buffer>================================================================ 546 //============================================================================== 547 /** 548 * dmub_trace_code_t - firmware trace code, 32-bits 549 */ 550 typedef uint32_t dmub_trace_code_t; 551 552 /** 553 * struct dmcub_trace_buf_entry - Firmware trace entry 554 */ 555 struct dmcub_trace_buf_entry { 556 dmub_trace_code_t trace_code; /**< trace code for the event */ 557 uint32_t tick_count; /**< the tick count at time of trace */ 558 uint32_t param0; /**< trace defined parameter 0 */ 559 uint32_t param1; /**< trace defined parameter 1 */ 560 }; 561 562 //============================================================================== 563 //< DMUB_STATUS>================================================================ 564 //============================================================================== 565 566 /** 567 * DMCUB scratch registers can be used to determine firmware status. 568 * Current scratch register usage is as follows: 569 * 570 * SCRATCH0: FW Boot Status register 571 * SCRATCH5: LVTMA Status Register 572 * SCRATCH15: FW Boot Options register 573 */ 574 575 /** 576 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 577 */ 578 union dmub_fw_boot_status { 579 struct { 580 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 581 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 582 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 583 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 584 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 585 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 586 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 587 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 588 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 589 } bits; /**< status bits */ 590 uint32_t all; /**< 32-bit access to status bits */ 591 }; 592 593 /** 594 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 595 */ 596 enum dmub_fw_boot_status_bit { 597 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 598 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 599 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 600 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 601 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 602 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 603 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 604 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 605 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 606 }; 607 608 /* Register bit definition for SCRATCH5 */ 609 union dmub_lvtma_status { 610 struct { 611 uint32_t psp_ok : 1; 612 uint32_t edp_on : 1; 613 uint32_t reserved : 30; 614 } bits; 615 uint32_t all; 616 }; 617 618 enum dmub_lvtma_status_bit { 619 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 620 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 621 }; 622 623 enum dmub_ips_disable_type { 624 DMUB_IPS_ENABLE = 0, 625 DMUB_IPS_DISABLE_ALL = 1, 626 DMUB_IPS_DISABLE_IPS1 = 2, 627 DMUB_IPS_DISABLE_IPS2 = 3, 628 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 629 DMUB_IPS_DISABLE_DYNAMIC = 5, 630 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 631 }; 632 633 #define DMUB_IPS1_ALLOW_MASK 0x00000001 634 #define DMUB_IPS2_ALLOW_MASK 0x00000002 635 #define DMUB_IPS1_COMMIT_MASK 0x00000004 636 #define DMUB_IPS2_COMMIT_MASK 0x00000008 637 638 /** 639 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 640 */ 641 union dmub_fw_boot_options { 642 struct { 643 uint32_t pemu_env : 1; /**< 1 if PEMU */ 644 uint32_t fpga_env : 1; /**< 1 if FPGA */ 645 uint32_t optimized_init : 1; /**< 1 if optimized init */ 646 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 647 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 648 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 649 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 650 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 651 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 652 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 653 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 654 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 655 uint32_t power_optimization: 1; 656 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 657 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 658 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 659 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 660 uint32_t reserved0: 1; 661 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 662 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 663 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 664 uint32_t ips_disable: 3; /* options to disable ips support*/ 665 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 666 uint32_t reserved : 9; /**< reserved */ 667 } bits; /**< boot bits */ 668 uint32_t all; /**< 32-bit access to bits */ 669 }; 670 671 enum dmub_fw_boot_options_bit { 672 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 673 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 674 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 675 }; 676 677 //============================================================================== 678 //< DMUB_SHARED_STATE>========================================================== 679 //============================================================================== 680 681 /** 682 * Shared firmware state between driver and firmware for lockless communication 683 * in situations where the inbox/outbox may be unavailable. 684 * 685 * Each structure *must* be at most 256-bytes in size. The layout allocation is 686 * described below: 687 * 688 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 689 */ 690 691 /** 692 * enum dmub_shared_state_feature_id - List of shared state features. 693 */ 694 enum dmub_shared_state_feature_id { 695 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 696 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 697 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 698 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 699 }; 700 701 /** 702 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 703 */ 704 union dmub_shared_state_ips_fw_signals { 705 struct { 706 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 707 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 708 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 709 uint32_t reserved_bits : 29; /**< Reversed */ 710 } bits; 711 uint32_t all; 712 }; 713 714 /** 715 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 716 */ 717 union dmub_shared_state_ips_driver_signals { 718 struct { 719 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 720 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 721 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 722 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 723 uint32_t reserved_bits : 28; /**< Reversed bits */ 724 } bits; 725 uint32_t all; 726 }; 727 728 /** 729 * IPS FW Version 730 */ 731 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 732 733 /** 734 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 735 */ 736 struct dmub_shared_state_ips_fw { 737 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 738 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 739 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 740 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 741 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 742 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 743 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 744 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 745 }; /* 248-bytes, fixed */ 746 747 /** 748 * IPS Driver Version 749 */ 750 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 751 752 /** 753 * struct dmub_shared_state_ips_driver - Driver state for IPS. 754 */ 755 struct dmub_shared_state_ips_driver { 756 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 757 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 758 }; /* 248-bytes, fixed */ 759 760 /** 761 * enum dmub_shared_state_feature_common - Generic payload. 762 */ 763 struct dmub_shared_state_feature_common { 764 uint32_t padding[62]; 765 }; /* 248-bytes, fixed */ 766 767 /** 768 * enum dmub_shared_state_feature_header - Feature description. 769 */ 770 struct dmub_shared_state_feature_header { 771 uint16_t id; /**< Feature ID */ 772 uint16_t version; /**< Feature version */ 773 uint32_t reserved; /**< Reserved bytes. */ 774 }; /* 8 bytes, fixed */ 775 776 /** 777 * struct dmub_shared_state_feature_block - Feature block. 778 */ 779 struct dmub_shared_state_feature_block { 780 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 781 union dmub_shared_feature_state_union { 782 struct dmub_shared_state_feature_common common; /**< Generic data */ 783 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 784 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 785 } data; /**< Shared state data. */ 786 }; /* 256-bytes, fixed */ 787 788 /** 789 * Shared state size in bytes. 790 */ 791 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 792 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 793 794 //============================================================================== 795 //</DMUB_STATUS>================================================================ 796 //============================================================================== 797 //< DMUB_VBIOS>================================================================= 798 //============================================================================== 799 800 /* 801 * enum dmub_cmd_vbios_type - VBIOS commands. 802 * 803 * Command IDs should be treated as stable ABI. 804 * Do not reuse or modify IDs. 805 */ 806 enum dmub_cmd_vbios_type { 807 /** 808 * Configures the DIG encoder. 809 */ 810 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 811 /** 812 * Controls the PHY. 813 */ 814 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 815 /** 816 * Sets the pixel clock/symbol clock. 817 */ 818 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 819 /** 820 * Enables or disables power gating. 821 */ 822 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 823 /** 824 * Controls embedded panels. 825 */ 826 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 827 /** 828 * Query DP alt status on a transmitter. 829 */ 830 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 831 /** 832 * Control PHY FSM 833 */ 834 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 835 /** 836 * Controls domain power gating 837 */ 838 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 839 }; 840 841 //============================================================================== 842 //</DMUB_VBIOS>================================================================= 843 //============================================================================== 844 //< DMUB_GPINT>================================================================= 845 //============================================================================== 846 847 /** 848 * The shifts and masks below may alternatively be used to format and read 849 * the command register bits. 850 */ 851 852 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 853 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 854 855 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 856 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 857 858 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 859 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 860 861 /** 862 * Command responses. 863 */ 864 865 /** 866 * Return response for DMUB_GPINT__STOP_FW command. 867 */ 868 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 869 870 /** 871 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 872 */ 873 union dmub_gpint_data_register { 874 struct { 875 uint32_t param : 16; /**< 16-bit parameter */ 876 uint32_t command_code : 12; /**< GPINT command */ 877 uint32_t status : 4; /**< Command status bit */ 878 } bits; /**< GPINT bit access */ 879 uint32_t all; /**< GPINT 32-bit access */ 880 }; 881 882 /* 883 * enum dmub_gpint_command - GPINT command to DMCUB FW 884 * 885 * Command IDs should be treated as stable ABI. 886 * Do not reuse or modify IDs. 887 */ 888 enum dmub_gpint_command { 889 /** 890 * Invalid command, ignored. 891 */ 892 DMUB_GPINT__INVALID_COMMAND = 0, 893 /** 894 * DESC: Queries the firmware version. 895 * RETURN: Firmware version. 896 */ 897 DMUB_GPINT__GET_FW_VERSION = 1, 898 /** 899 * DESC: Halts the firmware. 900 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 901 */ 902 DMUB_GPINT__STOP_FW = 2, 903 /** 904 * DESC: Get PSR state from FW. 905 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 906 */ 907 DMUB_GPINT__GET_PSR_STATE = 7, 908 /** 909 * DESC: Notifies DMCUB of the currently active streams. 910 * ARGS: Stream mask, 1 bit per active stream index. 911 */ 912 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 913 /** 914 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 915 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 916 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 917 * RETURN: PSR residency in milli-percent. 918 */ 919 DMUB_GPINT__PSR_RESIDENCY = 9, 920 921 /** 922 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 923 */ 924 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 925 926 /** 927 * DESC: Get REPLAY state from FW. 928 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 929 */ 930 DMUB_GPINT__GET_REPLAY_STATE = 13, 931 932 /** 933 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 934 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 935 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 936 * RETURN: REPLAY residency in milli-percent. 937 */ 938 DMUB_GPINT__REPLAY_RESIDENCY = 14, 939 940 /** 941 * DESC: Updates the trace buffer lower 32-bit mask. 942 * ARGS: The new mask 943 * RETURN: Lower 32-bit mask. 944 */ 945 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 946 947 /** 948 * DESC: Updates the trace buffer mask bit0~bit15. 949 * ARGS: The new mask 950 * RETURN: Lower 32-bit mask. 951 */ 952 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 953 954 /** 955 * DESC: Updates the trace buffer mask bit16~bit31. 956 * ARGS: The new mask 957 * RETURN: Lower 32-bit mask. 958 */ 959 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 960 961 /** 962 * DESC: Updates the trace buffer mask bit32~bit47. 963 * ARGS: The new mask 964 * RETURN: Lower 32-bit mask. 965 */ 966 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 967 968 /** 969 * DESC: Updates the trace buffer mask bit48~bit63. 970 * ARGS: The new mask 971 * RETURN: Lower 32-bit mask. 972 */ 973 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 974 975 /** 976 * DESC: Read the trace buffer mask bi0~bit15. 977 */ 978 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 979 980 /** 981 * DESC: Read the trace buffer mask bit16~bit31. 982 */ 983 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 984 985 /** 986 * DESC: Read the trace buffer mask bi32~bit47. 987 */ 988 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 989 990 /** 991 * DESC: Updates the trace buffer mask bit32~bit63. 992 */ 993 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 994 995 /** 996 * DESC: Enable measurements for various task duration 997 * ARGS: 0 - Disable measurement 998 * 1 - Enable measurement 999 */ 1000 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1001 }; 1002 1003 /** 1004 * INBOX0 generic command definition 1005 */ 1006 union dmub_inbox0_cmd_common { 1007 struct { 1008 uint32_t command_code: 8; /**< INBOX0 command code */ 1009 uint32_t param: 24; /**< 24-bit parameter */ 1010 } bits; 1011 uint32_t all; 1012 }; 1013 1014 /** 1015 * INBOX0 hw_lock command definition 1016 */ 1017 union dmub_inbox0_cmd_lock_hw { 1018 struct { 1019 uint32_t command_code: 8; 1020 1021 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1022 uint32_t hw_lock_client: 2; 1023 1024 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1025 uint32_t otg_inst: 3; 1026 uint32_t opp_inst: 3; 1027 uint32_t dig_inst: 3; 1028 1029 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1030 uint32_t lock_pipe: 1; 1031 uint32_t lock_cursor: 1; 1032 uint32_t lock_dig: 1; 1033 uint32_t triple_buffer_lock: 1; 1034 1035 uint32_t lock: 1; /**< Lock */ 1036 uint32_t should_release: 1; /**< Release */ 1037 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1038 } bits; 1039 uint32_t all; 1040 }; 1041 1042 union dmub_inbox0_data_register { 1043 union dmub_inbox0_cmd_common inbox0_cmd_common; 1044 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1045 }; 1046 1047 enum dmub_inbox0_command { 1048 /** 1049 * DESC: Invalid command, ignored. 1050 */ 1051 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1052 /** 1053 * DESC: Notification to acquire/release HW lock 1054 * ARGS: 1055 */ 1056 DMUB_INBOX0_CMD__HW_LOCK = 1, 1057 }; 1058 //============================================================================== 1059 //</DMUB_GPINT>================================================================= 1060 //============================================================================== 1061 //< DMUB_CMD>=================================================================== 1062 //============================================================================== 1063 1064 /** 1065 * Size in bytes of each DMUB command. 1066 */ 1067 #define DMUB_RB_CMD_SIZE 64 1068 1069 /** 1070 * Maximum number of items in the DMUB ringbuffer. 1071 */ 1072 #define DMUB_RB_MAX_ENTRY 128 1073 1074 /** 1075 * Ringbuffer size in bytes. 1076 */ 1077 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1078 1079 /** 1080 * REG_SET mask for reg offload. 1081 */ 1082 #define REG_SET_MASK 0xFFFF 1083 1084 /* 1085 * enum dmub_cmd_type - DMUB inbox command. 1086 * 1087 * Command IDs should be treated as stable ABI. 1088 * Do not reuse or modify IDs. 1089 */ 1090 enum dmub_cmd_type { 1091 /** 1092 * Invalid command. 1093 */ 1094 DMUB_CMD__NULL = 0, 1095 /** 1096 * Read modify write register sequence offload. 1097 */ 1098 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1099 /** 1100 * Field update register sequence offload. 1101 */ 1102 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1103 /** 1104 * Burst write sequence offload. 1105 */ 1106 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1107 /** 1108 * Reg wait sequence offload. 1109 */ 1110 DMUB_CMD__REG_REG_WAIT = 4, 1111 /** 1112 * Workaround to avoid HUBP underflow during NV12 playback. 1113 */ 1114 DMUB_CMD__PLAT_54186_WA = 5, 1115 /** 1116 * Command type used to query FW feature caps. 1117 */ 1118 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1119 /** 1120 * Command type used to get visual confirm color. 1121 */ 1122 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1123 /** 1124 * Command type used for all PSR commands. 1125 */ 1126 DMUB_CMD__PSR = 64, 1127 /** 1128 * Command type used for all MALL commands. 1129 */ 1130 DMUB_CMD__MALL = 65, 1131 /** 1132 * Command type used for all ABM commands. 1133 */ 1134 DMUB_CMD__ABM = 66, 1135 /** 1136 * Command type used to update dirty rects in FW. 1137 */ 1138 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1139 /** 1140 * Command type used to update cursor info in FW. 1141 */ 1142 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1143 /** 1144 * Command type used for HW locking in FW. 1145 */ 1146 DMUB_CMD__HW_LOCK = 69, 1147 /** 1148 * Command type used to access DP AUX. 1149 */ 1150 DMUB_CMD__DP_AUX_ACCESS = 70, 1151 /** 1152 * Command type used for OUTBOX1 notification enable 1153 */ 1154 DMUB_CMD__OUTBOX1_ENABLE = 71, 1155 1156 /** 1157 * Command type used for all idle optimization commands. 1158 */ 1159 DMUB_CMD__IDLE_OPT = 72, 1160 /** 1161 * Command type used for all clock manager commands. 1162 */ 1163 DMUB_CMD__CLK_MGR = 73, 1164 /** 1165 * Command type used for all panel control commands. 1166 */ 1167 DMUB_CMD__PANEL_CNTL = 74, 1168 1169 /** 1170 * Command type used for all CAB commands. 1171 */ 1172 DMUB_CMD__CAB_FOR_SS = 75, 1173 1174 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1175 1176 /** 1177 * Command type used for interfacing with DPIA. 1178 */ 1179 DMUB_CMD__DPIA = 77, 1180 /** 1181 * Command type used for EDID CEA parsing 1182 */ 1183 DMUB_CMD__EDID_CEA = 79, 1184 /** 1185 * Command type used for getting usbc cable ID 1186 */ 1187 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1188 /** 1189 * Command type used to query HPD state. 1190 */ 1191 DMUB_CMD__QUERY_HPD_STATE = 82, 1192 /** 1193 * Command type used for all VBIOS interface commands. 1194 */ 1195 /** 1196 * Command type used for all REPLAY commands. 1197 */ 1198 DMUB_CMD__REPLAY = 83, 1199 1200 /** 1201 * Command type used for all SECURE_DISPLAY commands. 1202 */ 1203 DMUB_CMD__SECURE_DISPLAY = 85, 1204 1205 /** 1206 * Command type used to set DPIA HPD interrupt state 1207 */ 1208 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1209 1210 /** 1211 * Command type used for all PSP commands. 1212 */ 1213 DMUB_CMD__PSP = 88, 1214 1215 DMUB_CMD__VBIOS = 128, 1216 }; 1217 1218 /** 1219 * enum dmub_out_cmd_type - DMUB outbox commands. 1220 */ 1221 enum dmub_out_cmd_type { 1222 /** 1223 * Invalid outbox command, ignored. 1224 */ 1225 DMUB_OUT_CMD__NULL = 0, 1226 /** 1227 * Command type used for DP AUX Reply data notification 1228 */ 1229 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1230 /** 1231 * Command type used for DP HPD event notification 1232 */ 1233 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1234 /** 1235 * Command type used for SET_CONFIG Reply notification 1236 */ 1237 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1238 /** 1239 * Command type used for USB4 DPIA notification 1240 */ 1241 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1242 }; 1243 1244 /* DMUB_CMD__DPIA command sub-types. */ 1245 enum dmub_cmd_dpia_type { 1246 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1247 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1248 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1249 }; 1250 1251 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1252 enum dmub_cmd_dpia_notification_type { 1253 DPIA_NOTIFY__BW_ALLOCATION = 0, 1254 }; 1255 1256 #pragma pack(push, 1) 1257 1258 /** 1259 * struct dmub_cmd_header - Common command header fields. 1260 */ 1261 struct dmub_cmd_header { 1262 unsigned int type : 8; /**< command type */ 1263 unsigned int sub_type : 8; /**< command sub type */ 1264 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1265 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1266 unsigned int reserved0 : 6; /**< reserved bits */ 1267 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1268 unsigned int reserved1 : 2; /**< reserved bits */ 1269 }; 1270 1271 /* 1272 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1273 * 1274 * 60 payload bytes can hold up to 5 sets of read modify writes, 1275 * each take 3 dwords. 1276 * 1277 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1278 * 1279 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1280 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1281 */ 1282 struct dmub_cmd_read_modify_write_sequence { 1283 uint32_t addr; /**< register address */ 1284 uint32_t modify_mask; /**< modify mask */ 1285 uint32_t modify_value; /**< modify value */ 1286 }; 1287 1288 /** 1289 * Maximum number of ops in read modify write sequence. 1290 */ 1291 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1292 1293 /** 1294 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1295 */ 1296 struct dmub_rb_cmd_read_modify_write { 1297 struct dmub_cmd_header header; /**< command header */ 1298 /** 1299 * Read modify write sequence. 1300 */ 1301 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1302 }; 1303 1304 /* 1305 * Update a register with specified masks and values sequeunce 1306 * 1307 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1308 * 1309 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1310 * 1311 * 1312 * USE CASE: 1313 * 1. auto-increment register where additional read would update pointer and produce wrong result 1314 * 2. toggle a bit without read in the middle 1315 */ 1316 1317 struct dmub_cmd_reg_field_update_sequence { 1318 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1319 uint32_t modify_value; /**< value to update with */ 1320 }; 1321 1322 /** 1323 * Maximum number of ops in field update sequence. 1324 */ 1325 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1326 1327 /** 1328 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1329 */ 1330 struct dmub_rb_cmd_reg_field_update_sequence { 1331 struct dmub_cmd_header header; /**< command header */ 1332 uint32_t addr; /**< register address */ 1333 /** 1334 * Field update sequence. 1335 */ 1336 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1337 }; 1338 1339 1340 /** 1341 * Maximum number of burst write values. 1342 */ 1343 #define DMUB_BURST_WRITE_VALUES__MAX 14 1344 1345 /* 1346 * struct dmub_rb_cmd_burst_write - Burst write 1347 * 1348 * support use case such as writing out LUTs. 1349 * 1350 * 60 payload bytes can hold up to 14 values to write to given address 1351 * 1352 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1353 */ 1354 struct dmub_rb_cmd_burst_write { 1355 struct dmub_cmd_header header; /**< command header */ 1356 uint32_t addr; /**< register start address */ 1357 /** 1358 * Burst write register values. 1359 */ 1360 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1361 }; 1362 1363 /** 1364 * struct dmub_rb_cmd_common - Common command header 1365 */ 1366 struct dmub_rb_cmd_common { 1367 struct dmub_cmd_header header; /**< command header */ 1368 /** 1369 * Padding to RB_CMD_SIZE 1370 */ 1371 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1372 }; 1373 1374 /** 1375 * struct dmub_cmd_reg_wait_data - Register wait data 1376 */ 1377 struct dmub_cmd_reg_wait_data { 1378 uint32_t addr; /**< Register address */ 1379 uint32_t mask; /**< Mask for register bits */ 1380 uint32_t condition_field_value; /**< Value to wait for */ 1381 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1382 }; 1383 1384 /** 1385 * struct dmub_rb_cmd_reg_wait - Register wait command 1386 */ 1387 struct dmub_rb_cmd_reg_wait { 1388 struct dmub_cmd_header header; /**< Command header */ 1389 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1390 }; 1391 1392 /** 1393 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1394 * 1395 * Reprograms surface parameters to avoid underflow. 1396 */ 1397 struct dmub_cmd_PLAT_54186_wa { 1398 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1399 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1400 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1401 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1402 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1403 struct { 1404 uint32_t hubp_inst : 4; /**< HUBP instance */ 1405 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1406 uint32_t immediate :1; /**< Immediate flip */ 1407 uint32_t vmid : 4; /**< VMID */ 1408 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1409 uint32_t reserved : 21; /**< Reserved */ 1410 } flip_params; /**< Pageflip parameters */ 1411 uint32_t reserved[9]; /**< Reserved bits */ 1412 }; 1413 1414 /** 1415 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1416 */ 1417 struct dmub_rb_cmd_PLAT_54186_wa { 1418 struct dmub_cmd_header header; /**< Command header */ 1419 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1420 }; 1421 1422 /** 1423 * enum dmub_cmd_mall_type - MALL commands 1424 */ 1425 enum dmub_cmd_mall_type { 1426 /** 1427 * Allows display refresh from MALL. 1428 */ 1429 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1430 /** 1431 * Disallows display refresh from MALL. 1432 */ 1433 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1434 /** 1435 * Cursor copy for MALL. 1436 */ 1437 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1438 /** 1439 * Controls DF requests. 1440 */ 1441 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1442 }; 1443 1444 /** 1445 * struct dmub_rb_cmd_mall - MALL command data. 1446 */ 1447 struct dmub_rb_cmd_mall { 1448 struct dmub_cmd_header header; /**< Common command header */ 1449 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1450 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1451 uint32_t tmr_delay; /**< Timer delay */ 1452 uint32_t tmr_scale; /**< Timer scale */ 1453 uint16_t cursor_width; /**< Cursor width in pixels */ 1454 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1455 uint16_t cursor_height; /**< Cursor height in pixels */ 1456 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1457 uint8_t debug_bits; /**< Debug bits */ 1458 1459 uint8_t reserved1; /**< Reserved bits */ 1460 uint8_t reserved2; /**< Reserved bits */ 1461 }; 1462 1463 /** 1464 * enum dmub_cmd_cab_type - CAB command data. 1465 */ 1466 enum dmub_cmd_cab_type { 1467 /** 1468 * No idle optimizations (i.e. no CAB) 1469 */ 1470 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1471 /** 1472 * No DCN requests for memory 1473 */ 1474 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1475 /** 1476 * Fit surfaces in CAB (i.e. CAB enable) 1477 */ 1478 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1479 /** 1480 * Do not fit surfaces in CAB (i.e. no CAB) 1481 */ 1482 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1483 }; 1484 1485 /** 1486 * struct dmub_rb_cmd_cab - CAB command data. 1487 */ 1488 struct dmub_rb_cmd_cab_for_ss { 1489 struct dmub_cmd_header header; 1490 uint8_t cab_alloc_ways; /* total number of ways */ 1491 uint8_t debug_bits; /* debug bits */ 1492 }; 1493 1494 /** 1495 * Enum for indicating which MCLK switch mode per pipe 1496 */ 1497 enum mclk_switch_mode { 1498 NONE = 0, 1499 FPO = 1, 1500 SUBVP = 2, 1501 VBLANK = 3, 1502 }; 1503 1504 /* Per pipe struct which stores the MCLK switch mode 1505 * data to be sent to DMUB. 1506 * Named "v2" for now -- once FPO and SUBVP are fully merged 1507 * the type name can be updated 1508 */ 1509 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1510 union { 1511 struct { 1512 uint32_t pix_clk_100hz; 1513 uint16_t main_vblank_start; 1514 uint16_t main_vblank_end; 1515 uint16_t mall_region_lines; 1516 uint16_t prefetch_lines; 1517 uint16_t prefetch_to_mall_start_lines; 1518 uint16_t processing_delay_lines; 1519 uint16_t htotal; // required to calculate line time for multi-display cases 1520 uint16_t vtotal; 1521 uint8_t main_pipe_index; 1522 uint8_t phantom_pipe_index; 1523 /* Since the microschedule is calculated in terms of OTG lines, 1524 * include any scaling factors to make sure when we get accurate 1525 * conversion when programming MALL_START_LINE (which is in terms 1526 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1527 * is 1/2 (numerator = 1, denominator = 2). 1528 */ 1529 uint8_t scale_factor_numerator; 1530 uint8_t scale_factor_denominator; 1531 uint8_t is_drr; 1532 uint8_t main_split_pipe_index; 1533 uint8_t phantom_split_pipe_index; 1534 } subvp_data; 1535 1536 struct { 1537 uint32_t pix_clk_100hz; 1538 uint16_t vblank_start; 1539 uint16_t vblank_end; 1540 uint16_t vstartup_start; 1541 uint16_t vtotal; 1542 uint16_t htotal; 1543 uint8_t vblank_pipe_index; 1544 uint8_t padding[1]; 1545 struct { 1546 uint8_t drr_in_use; 1547 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1548 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1549 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1550 uint8_t use_ramping; // Use ramping or not 1551 uint8_t drr_vblank_start_margin; 1552 } drr_info; // DRR considered as part of SubVP + VBLANK case 1553 } vblank_data; 1554 } pipe_config; 1555 1556 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1557 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1558 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1559 */ 1560 uint8_t mode; // enum mclk_switch_mode 1561 }; 1562 1563 /** 1564 * Config data for Sub-VP and FPO 1565 * Named "v2" for now -- once FPO and SUBVP are fully merged 1566 * the type name can be updated 1567 */ 1568 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1569 uint16_t watermark_a_cache; 1570 uint8_t vertical_int_margin_us; 1571 uint8_t pstate_allow_width_us; 1572 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1573 }; 1574 1575 /** 1576 * DMUB rb command definition for Sub-VP and FPO 1577 * Named "v2" for now -- once FPO and SUBVP are fully merged 1578 * the type name can be updated 1579 */ 1580 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1581 struct dmub_cmd_header header; 1582 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1583 }; 1584 1585 /** 1586 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1587 */ 1588 enum dmub_cmd_idle_opt_type { 1589 /** 1590 * DCN hardware restore. 1591 */ 1592 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1593 1594 /** 1595 * DCN hardware save. 1596 */ 1597 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1598 1599 /** 1600 * DCN hardware notify idle. 1601 */ 1602 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1603 }; 1604 1605 /** 1606 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1607 */ 1608 struct dmub_rb_cmd_idle_opt_dcn_restore { 1609 struct dmub_cmd_header header; /**< header */ 1610 }; 1611 1612 /** 1613 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1614 */ 1615 struct dmub_dcn_notify_idle_cntl_data { 1616 uint8_t driver_idle; 1617 uint8_t reserved[59]; 1618 }; 1619 1620 /** 1621 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1622 */ 1623 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1624 struct dmub_cmd_header header; /**< header */ 1625 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1626 }; 1627 1628 /** 1629 * struct dmub_clocks - Clock update notification. 1630 */ 1631 struct dmub_clocks { 1632 uint32_t dispclk_khz; /**< dispclk kHz */ 1633 uint32_t dppclk_khz; /**< dppclk kHz */ 1634 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1635 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1636 }; 1637 1638 /** 1639 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1640 */ 1641 enum dmub_cmd_clk_mgr_type { 1642 /** 1643 * Notify DMCUB of clock update. 1644 */ 1645 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1646 }; 1647 1648 /** 1649 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1650 */ 1651 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1652 struct dmub_cmd_header header; /**< header */ 1653 struct dmub_clocks clocks; /**< clock data */ 1654 }; 1655 1656 /** 1657 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1658 */ 1659 struct dmub_cmd_digx_encoder_control_data { 1660 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1661 }; 1662 1663 /** 1664 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1665 */ 1666 struct dmub_rb_cmd_digx_encoder_control { 1667 struct dmub_cmd_header header; /**< header */ 1668 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1669 }; 1670 1671 /** 1672 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1673 */ 1674 struct dmub_cmd_set_pixel_clock_data { 1675 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1676 }; 1677 1678 /** 1679 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1680 */ 1681 struct dmub_rb_cmd_set_pixel_clock { 1682 struct dmub_cmd_header header; /**< header */ 1683 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1684 }; 1685 1686 /** 1687 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1688 */ 1689 struct dmub_cmd_enable_disp_power_gating_data { 1690 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1691 }; 1692 1693 /** 1694 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1695 */ 1696 struct dmub_rb_cmd_enable_disp_power_gating { 1697 struct dmub_cmd_header header; /**< header */ 1698 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1699 }; 1700 1701 /** 1702 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1703 */ 1704 struct dmub_dig_transmitter_control_data_v1_7 { 1705 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1706 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1707 union { 1708 uint8_t digmode; /**< enum atom_encode_mode_def */ 1709 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1710 } mode_laneset; 1711 uint8_t lanenum; /**< Number of lanes */ 1712 union { 1713 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1714 } symclk_units; 1715 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1716 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1717 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1718 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1719 uint8_t reserved1; /**< For future use */ 1720 uint8_t reserved2[3]; /**< For future use */ 1721 uint32_t reserved3[11]; /**< For future use */ 1722 }; 1723 1724 /** 1725 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1726 */ 1727 union dmub_cmd_dig1_transmitter_control_data { 1728 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1729 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1730 }; 1731 1732 /** 1733 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1734 */ 1735 struct dmub_rb_cmd_dig1_transmitter_control { 1736 struct dmub_cmd_header header; /**< header */ 1737 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1738 }; 1739 1740 /** 1741 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1742 */ 1743 struct dmub_rb_cmd_domain_control_data { 1744 uint8_t inst : 6; /**< DOMAIN instance to control */ 1745 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1746 uint8_t reserved[3]; /**< Reserved for future use */ 1747 }; 1748 1749 /** 1750 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1751 */ 1752 struct dmub_rb_cmd_domain_control { 1753 struct dmub_cmd_header header; /**< header */ 1754 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1755 }; 1756 1757 /** 1758 * DPIA tunnel command parameters. 1759 */ 1760 struct dmub_cmd_dig_dpia_control_data { 1761 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1762 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1763 union { 1764 uint8_t digmode; /** enum atom_encode_mode_def */ 1765 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1766 } mode_laneset; 1767 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1768 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1769 uint8_t hpdsel; /** =0: HPD is not assigned */ 1770 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1771 uint8_t dpia_id; /** Index of DPIA */ 1772 uint8_t fec_rdy : 1; 1773 uint8_t reserved : 7; 1774 uint32_t reserved1; 1775 }; 1776 1777 /** 1778 * DMUB command for DPIA tunnel control. 1779 */ 1780 struct dmub_rb_cmd_dig1_dpia_control { 1781 struct dmub_cmd_header header; 1782 struct dmub_cmd_dig_dpia_control_data dpia_control; 1783 }; 1784 1785 /** 1786 * SET_CONFIG Command Payload 1787 */ 1788 struct set_config_cmd_payload { 1789 uint8_t msg_type; /* set config message type */ 1790 uint8_t msg_data; /* set config message data */ 1791 }; 1792 1793 /** 1794 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1795 */ 1796 struct dmub_cmd_set_config_control_data { 1797 struct set_config_cmd_payload cmd_pkt; 1798 uint8_t instance; /* DPIA instance */ 1799 uint8_t immed_status; /* Immediate status returned in case of error */ 1800 }; 1801 1802 /** 1803 * DMUB command structure for SET_CONFIG command. 1804 */ 1805 struct dmub_rb_cmd_set_config_access { 1806 struct dmub_cmd_header header; /* header */ 1807 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1808 }; 1809 1810 /** 1811 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1812 */ 1813 struct dmub_cmd_mst_alloc_slots_control_data { 1814 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1815 uint8_t instance; /* DPIA instance */ 1816 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1817 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1818 }; 1819 1820 /** 1821 * DMUB command structure for SET_ command. 1822 */ 1823 struct dmub_rb_cmd_set_mst_alloc_slots { 1824 struct dmub_cmd_header header; /* header */ 1825 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1826 }; 1827 1828 /** 1829 * DMUB command structure for DPIA HPD int enable control. 1830 */ 1831 struct dmub_rb_cmd_dpia_hpd_int_enable { 1832 struct dmub_cmd_header header; /* header */ 1833 uint32_t enable; /* dpia hpd interrupt enable */ 1834 }; 1835 1836 /** 1837 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1838 */ 1839 struct dmub_rb_cmd_dpphy_init { 1840 struct dmub_cmd_header header; /**< header */ 1841 uint8_t reserved[60]; /**< reserved bits */ 1842 }; 1843 1844 /** 1845 * enum dp_aux_request_action - DP AUX request command listing. 1846 * 1847 * 4 AUX request command bits are shifted to high nibble. 1848 */ 1849 enum dp_aux_request_action { 1850 /** I2C-over-AUX write request */ 1851 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1852 /** I2C-over-AUX read request */ 1853 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1854 /** I2C-over-AUX write status request */ 1855 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1856 /** I2C-over-AUX write request with MOT=1 */ 1857 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1858 /** I2C-over-AUX read request with MOT=1 */ 1859 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1860 /** I2C-over-AUX write status request with MOT=1 */ 1861 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1862 /** Native AUX write request */ 1863 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1864 /** Native AUX read request */ 1865 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1866 }; 1867 1868 /** 1869 * enum aux_return_code_type - DP AUX process return code listing. 1870 */ 1871 enum aux_return_code_type { 1872 /** AUX process succeeded */ 1873 AUX_RET_SUCCESS = 0, 1874 /** AUX process failed with unknown reason */ 1875 AUX_RET_ERROR_UNKNOWN, 1876 /** AUX process completed with invalid reply */ 1877 AUX_RET_ERROR_INVALID_REPLY, 1878 /** AUX process timed out */ 1879 AUX_RET_ERROR_TIMEOUT, 1880 /** HPD was low during AUX process */ 1881 AUX_RET_ERROR_HPD_DISCON, 1882 /** Failed to acquire AUX engine */ 1883 AUX_RET_ERROR_ENGINE_ACQUIRE, 1884 /** AUX request not supported */ 1885 AUX_RET_ERROR_INVALID_OPERATION, 1886 /** AUX process not available */ 1887 AUX_RET_ERROR_PROTOCOL_ERROR, 1888 }; 1889 1890 /** 1891 * enum aux_channel_type - DP AUX channel type listing. 1892 */ 1893 enum aux_channel_type { 1894 /** AUX thru Legacy DP AUX */ 1895 AUX_CHANNEL_LEGACY_DDC, 1896 /** AUX thru DPIA DP tunneling */ 1897 AUX_CHANNEL_DPIA 1898 }; 1899 1900 /** 1901 * struct aux_transaction_parameters - DP AUX request transaction data 1902 */ 1903 struct aux_transaction_parameters { 1904 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1905 uint8_t action; /**< enum dp_aux_request_action */ 1906 uint8_t length; /**< DP AUX request data length */ 1907 uint8_t reserved; /**< For future use */ 1908 uint32_t address; /**< DP AUX address */ 1909 uint8_t data[16]; /**< DP AUX write data */ 1910 }; 1911 1912 /** 1913 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1914 */ 1915 struct dmub_cmd_dp_aux_control_data { 1916 uint8_t instance; /**< AUX instance or DPIA instance */ 1917 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1918 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1919 uint8_t reserved0; /**< For future use */ 1920 uint16_t timeout; /**< timeout time in us */ 1921 uint16_t reserved1; /**< For future use */ 1922 enum aux_channel_type type; /**< enum aux_channel_type */ 1923 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1924 }; 1925 1926 /** 1927 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1928 */ 1929 struct dmub_rb_cmd_dp_aux_access { 1930 /** 1931 * Command header. 1932 */ 1933 struct dmub_cmd_header header; 1934 /** 1935 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1936 */ 1937 struct dmub_cmd_dp_aux_control_data aux_control; 1938 }; 1939 1940 /** 1941 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1942 */ 1943 struct dmub_rb_cmd_outbox1_enable { 1944 /** 1945 * Command header. 1946 */ 1947 struct dmub_cmd_header header; 1948 /** 1949 * enable: 0x0 -> disable outbox1 notification (default value) 1950 * 0x1 -> enable outbox1 notification 1951 */ 1952 uint32_t enable; 1953 }; 1954 1955 /* DP AUX Reply command - OutBox Cmd */ 1956 /** 1957 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1958 */ 1959 struct aux_reply_data { 1960 /** 1961 * Aux cmd 1962 */ 1963 uint8_t command; 1964 /** 1965 * Aux reply data length (max: 16 bytes) 1966 */ 1967 uint8_t length; 1968 /** 1969 * Alignment only 1970 */ 1971 uint8_t pad[2]; 1972 /** 1973 * Aux reply data 1974 */ 1975 uint8_t data[16]; 1976 }; 1977 1978 /** 1979 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1980 */ 1981 struct aux_reply_control_data { 1982 /** 1983 * Reserved for future use 1984 */ 1985 uint32_t handle; 1986 /** 1987 * Aux Instance 1988 */ 1989 uint8_t instance; 1990 /** 1991 * Aux transaction result: definition in enum aux_return_code_type 1992 */ 1993 uint8_t result; 1994 /** 1995 * Alignment only 1996 */ 1997 uint16_t pad; 1998 }; 1999 2000 /** 2001 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2002 */ 2003 struct dmub_rb_cmd_dp_aux_reply { 2004 /** 2005 * Command header. 2006 */ 2007 struct dmub_cmd_header header; 2008 /** 2009 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2010 */ 2011 struct aux_reply_control_data control; 2012 /** 2013 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2014 */ 2015 struct aux_reply_data reply_data; 2016 }; 2017 2018 /* DP HPD Notify command - OutBox Cmd */ 2019 /** 2020 * DP HPD Type 2021 */ 2022 enum dp_hpd_type { 2023 /** 2024 * Normal DP HPD 2025 */ 2026 DP_HPD = 0, 2027 /** 2028 * DP HPD short pulse 2029 */ 2030 DP_IRQ 2031 }; 2032 2033 /** 2034 * DP HPD Status 2035 */ 2036 enum dp_hpd_status { 2037 /** 2038 * DP_HPD status low 2039 */ 2040 DP_HPD_UNPLUG = 0, 2041 /** 2042 * DP_HPD status high 2043 */ 2044 DP_HPD_PLUG 2045 }; 2046 2047 /** 2048 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2049 */ 2050 struct dp_hpd_data { 2051 /** 2052 * DP HPD instance 2053 */ 2054 uint8_t instance; 2055 /** 2056 * HPD type 2057 */ 2058 uint8_t hpd_type; 2059 /** 2060 * HPD status: only for type: DP_HPD to indicate status 2061 */ 2062 uint8_t hpd_status; 2063 /** 2064 * Alignment only 2065 */ 2066 uint8_t pad; 2067 }; 2068 2069 /** 2070 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2071 */ 2072 struct dmub_rb_cmd_dp_hpd_notify { 2073 /** 2074 * Command header. 2075 */ 2076 struct dmub_cmd_header header; 2077 /** 2078 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2079 */ 2080 struct dp_hpd_data hpd_data; 2081 }; 2082 2083 /** 2084 * Definition of a SET_CONFIG reply from DPOA. 2085 */ 2086 enum set_config_status { 2087 SET_CONFIG_PENDING = 0, 2088 SET_CONFIG_ACK_RECEIVED, 2089 SET_CONFIG_RX_TIMEOUT, 2090 SET_CONFIG_UNKNOWN_ERROR, 2091 }; 2092 2093 /** 2094 * Definition of a set_config reply 2095 */ 2096 struct set_config_reply_control_data { 2097 uint8_t instance; /* DPIA Instance */ 2098 uint8_t status; /* Set Config reply */ 2099 uint16_t pad; /* Alignment */ 2100 }; 2101 2102 /** 2103 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2104 */ 2105 struct dmub_rb_cmd_dp_set_config_reply { 2106 struct dmub_cmd_header header; 2107 struct set_config_reply_control_data set_config_reply_control; 2108 }; 2109 2110 /** 2111 * Definition of a DPIA notification header 2112 */ 2113 struct dpia_notification_header { 2114 uint8_t instance; /**< DPIA Instance */ 2115 uint8_t reserved[3]; 2116 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2117 }; 2118 2119 /** 2120 * Definition of the common data struct of DPIA notification 2121 */ 2122 struct dpia_notification_common { 2123 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2124 - sizeof(struct dpia_notification_header)]; 2125 }; 2126 2127 /** 2128 * Definition of a DPIA notification data 2129 */ 2130 struct dpia_bw_allocation_notify_data { 2131 union { 2132 struct { 2133 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2134 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2135 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2136 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2137 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2138 uint16_t reserved: 11; /**< Reserved */ 2139 } bits; 2140 2141 uint16_t flags; 2142 }; 2143 2144 uint8_t cm_id; /**< CM ID */ 2145 uint8_t group_id; /**< Group ID */ 2146 uint8_t granularity; /**< BW Allocation Granularity */ 2147 uint8_t estimated_bw; /**< Estimated_BW */ 2148 uint8_t allocated_bw; /**< Allocated_BW */ 2149 uint8_t reserved; 2150 }; 2151 2152 /** 2153 * union dpia_notify_data_type - DPIA Notification in Outbox command 2154 */ 2155 union dpia_notification_data { 2156 /** 2157 * DPIA Notification for common data struct 2158 */ 2159 struct dpia_notification_common common_data; 2160 2161 /** 2162 * DPIA Notification for DP BW Allocation support 2163 */ 2164 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2165 }; 2166 2167 /** 2168 * Definition of a DPIA notification payload 2169 */ 2170 struct dpia_notification_payload { 2171 struct dpia_notification_header header; 2172 union dpia_notification_data data; /**< DPIA notification payload data */ 2173 }; 2174 2175 /** 2176 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2177 */ 2178 struct dmub_rb_cmd_dpia_notification { 2179 struct dmub_cmd_header header; /**< DPIA notification header */ 2180 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2181 }; 2182 2183 /** 2184 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2185 */ 2186 struct dmub_cmd_hpd_state_query_data { 2187 uint8_t instance; /**< HPD instance or DPIA instance */ 2188 uint8_t result; /**< For returning HPD state */ 2189 uint16_t pad; /** < Alignment */ 2190 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2191 enum aux_return_code_type status; /**< for returning the status of command */ 2192 }; 2193 2194 /** 2195 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2196 */ 2197 struct dmub_rb_cmd_query_hpd_state { 2198 /** 2199 * Command header. 2200 */ 2201 struct dmub_cmd_header header; 2202 /** 2203 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2204 */ 2205 struct dmub_cmd_hpd_state_query_data data; 2206 }; 2207 2208 /* 2209 * Command IDs should be treated as stable ABI. 2210 * Do not reuse or modify IDs. 2211 */ 2212 2213 /** 2214 * PSR command sub-types. 2215 */ 2216 enum dmub_cmd_psr_type { 2217 /** 2218 * Set PSR version support. 2219 */ 2220 DMUB_CMD__PSR_SET_VERSION = 0, 2221 /** 2222 * Copy driver-calculated parameters to PSR state. 2223 */ 2224 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2225 /** 2226 * Enable PSR. 2227 */ 2228 DMUB_CMD__PSR_ENABLE = 2, 2229 2230 /** 2231 * Disable PSR. 2232 */ 2233 DMUB_CMD__PSR_DISABLE = 3, 2234 2235 /** 2236 * Set PSR level. 2237 * PSR level is a 16-bit value dicated by driver that 2238 * will enable/disable different functionality. 2239 */ 2240 DMUB_CMD__PSR_SET_LEVEL = 4, 2241 2242 /** 2243 * Forces PSR enabled until an explicit PSR disable call. 2244 */ 2245 DMUB_CMD__PSR_FORCE_STATIC = 5, 2246 /** 2247 * Set vtotal in psr active for FreeSync PSR. 2248 */ 2249 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2250 /** 2251 * Set PSR power option 2252 */ 2253 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2254 }; 2255 2256 enum dmub_cmd_fams_type { 2257 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2258 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2259 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2260 /** 2261 * For SubVP set manual trigger in FW because it 2262 * triggers DRR_UPDATE_PENDING which SubVP relies 2263 * on (for any SubVP cases that use a DRR display) 2264 */ 2265 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2266 }; 2267 2268 /** 2269 * PSR versions. 2270 */ 2271 enum psr_version { 2272 /** 2273 * PSR version 1. 2274 */ 2275 PSR_VERSION_1 = 0, 2276 /** 2277 * Freesync PSR SU. 2278 */ 2279 PSR_VERSION_SU_1 = 1, 2280 /** 2281 * PSR not supported. 2282 */ 2283 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2284 }; 2285 2286 /** 2287 * PHY Link rate for DP. 2288 */ 2289 enum phy_link_rate { 2290 /** 2291 * not supported. 2292 */ 2293 PHY_RATE_UNKNOWN = 0, 2294 /** 2295 * Rate_1 (RBR) - 1.62 Gbps/Lane 2296 */ 2297 PHY_RATE_162 = 1, 2298 /** 2299 * Rate_2 - 2.16 Gbps/Lane 2300 */ 2301 PHY_RATE_216 = 2, 2302 /** 2303 * Rate_3 - 2.43 Gbps/Lane 2304 */ 2305 PHY_RATE_243 = 3, 2306 /** 2307 * Rate_4 (HBR) - 2.70 Gbps/Lane 2308 */ 2309 PHY_RATE_270 = 4, 2310 /** 2311 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2312 */ 2313 PHY_RATE_324 = 5, 2314 /** 2315 * Rate_6 - 4.32 Gbps/Lane 2316 */ 2317 PHY_RATE_432 = 6, 2318 /** 2319 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2320 */ 2321 PHY_RATE_540 = 7, 2322 /** 2323 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2324 */ 2325 PHY_RATE_810 = 8, 2326 /** 2327 * UHBR10 - 10.0 Gbps/Lane 2328 */ 2329 PHY_RATE_1000 = 9, 2330 /** 2331 * UHBR13.5 - 13.5 Gbps/Lane 2332 */ 2333 PHY_RATE_1350 = 10, 2334 /** 2335 * UHBR10 - 20.0 Gbps/Lane 2336 */ 2337 PHY_RATE_2000 = 11, 2338 2339 PHY_RATE_675 = 12, 2340 /** 2341 * Rate 12 - 6.75 Gbps/Lane 2342 */ 2343 }; 2344 2345 /** 2346 * enum dmub_phy_fsm_state - PHY FSM states. 2347 * PHY FSM state to transit to during PSR enable/disable. 2348 */ 2349 enum dmub_phy_fsm_state { 2350 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2351 DMUB_PHY_FSM_RESET, 2352 DMUB_PHY_FSM_RESET_RELEASED, 2353 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2354 DMUB_PHY_FSM_INITIALIZED, 2355 DMUB_PHY_FSM_CALIBRATED, 2356 DMUB_PHY_FSM_CALIBRATED_LP, 2357 DMUB_PHY_FSM_CALIBRATED_PG, 2358 DMUB_PHY_FSM_POWER_DOWN, 2359 DMUB_PHY_FSM_PLL_EN, 2360 DMUB_PHY_FSM_TX_EN, 2361 DMUB_PHY_FSM_TX_EN_TEST_MODE, 2362 DMUB_PHY_FSM_FAST_LP, 2363 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2364 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2365 DMUB_PHY_FSM_P2_PLL_OFF, 2366 DMUB_PHY_FSM_P2_PLL_ON, 2367 }; 2368 2369 /** 2370 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2371 */ 2372 struct dmub_cmd_psr_copy_settings_data { 2373 /** 2374 * Flags that can be set by driver to change some PSR behaviour. 2375 */ 2376 union dmub_psr_debug_flags debug; 2377 /** 2378 * 16-bit value dicated by driver that will enable/disable different functionality. 2379 */ 2380 uint16_t psr_level; 2381 /** 2382 * DPP HW instance. 2383 */ 2384 uint8_t dpp_inst; 2385 /** 2386 * MPCC HW instance. 2387 * Not used in dmub fw, 2388 * dmub fw will get active opp by reading odm registers. 2389 */ 2390 uint8_t mpcc_inst; 2391 /** 2392 * OPP HW instance. 2393 * Not used in dmub fw, 2394 * dmub fw will get active opp by reading odm registers. 2395 */ 2396 uint8_t opp_inst; 2397 /** 2398 * OTG HW instance. 2399 */ 2400 uint8_t otg_inst; 2401 /** 2402 * DIG FE HW instance. 2403 */ 2404 uint8_t digfe_inst; 2405 /** 2406 * DIG BE HW instance. 2407 */ 2408 uint8_t digbe_inst; 2409 /** 2410 * DP PHY HW instance. 2411 */ 2412 uint8_t dpphy_inst; 2413 /** 2414 * AUX HW instance. 2415 */ 2416 uint8_t aux_inst; 2417 /** 2418 * Determines if SMU optimzations are enabled/disabled. 2419 */ 2420 uint8_t smu_optimizations_en; 2421 /** 2422 * Unused. 2423 * TODO: Remove. 2424 */ 2425 uint8_t frame_delay; 2426 /** 2427 * If RFB setup time is greater than the total VBLANK time, 2428 * it is not possible for the sink to capture the video frame 2429 * in the same frame the SDP is sent. In this case, 2430 * the frame capture indication bit should be set and an extra 2431 * static frame should be transmitted to the sink. 2432 */ 2433 uint8_t frame_cap_ind; 2434 /** 2435 * Granularity of Y offset supported by sink. 2436 */ 2437 uint8_t su_y_granularity; 2438 /** 2439 * Indicates whether sink should start capturing 2440 * immediately following active scan line, 2441 * or starting with the 2nd active scan line. 2442 */ 2443 uint8_t line_capture_indication; 2444 /** 2445 * Multi-display optimizations are implemented on certain ASICs. 2446 */ 2447 uint8_t multi_disp_optimizations_en; 2448 /** 2449 * The last possible line SDP may be transmitted without violating 2450 * the RFB setup time or entering the active video frame. 2451 */ 2452 uint16_t init_sdp_deadline; 2453 /** 2454 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2455 */ 2456 uint8_t rate_control_caps ; 2457 /* 2458 * Force PSRSU always doing full frame update 2459 */ 2460 uint8_t force_ffu_mode; 2461 /** 2462 * Length of each horizontal line in us. 2463 */ 2464 uint32_t line_time_in_us; 2465 /** 2466 * FEC enable status in driver 2467 */ 2468 uint8_t fec_enable_status; 2469 /** 2470 * FEC re-enable delay when PSR exit. 2471 * unit is 100us, range form 0~255(0xFF). 2472 */ 2473 uint8_t fec_enable_delay_in100us; 2474 /** 2475 * PSR control version. 2476 */ 2477 uint8_t cmd_version; 2478 /** 2479 * Panel Instance. 2480 * Panel instance to identify which psr_state to use 2481 * Currently the support is only for 0 or 1 2482 */ 2483 uint8_t panel_inst; 2484 /* 2485 * DSC enable status in driver 2486 */ 2487 uint8_t dsc_enable_status; 2488 /* 2489 * Use FSM state for PSR power up/down 2490 */ 2491 uint8_t use_phy_fsm; 2492 /** 2493 * frame delay for frame re-lock 2494 */ 2495 uint8_t relock_delay_frame_cnt; 2496 /** 2497 * Explicit padding to 4 byte boundary. 2498 */ 2499 uint8_t pad3; 2500 /** 2501 * DSC Slice height. 2502 */ 2503 uint16_t dsc_slice_height; 2504 /** 2505 * Some panels request main link off before xth vertical line 2506 */ 2507 uint16_t poweroff_before_vertical_line; 2508 }; 2509 2510 /** 2511 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2512 */ 2513 struct dmub_rb_cmd_psr_copy_settings { 2514 /** 2515 * Command header. 2516 */ 2517 struct dmub_cmd_header header; 2518 /** 2519 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2520 */ 2521 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2522 }; 2523 2524 /** 2525 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2526 */ 2527 struct dmub_cmd_psr_set_level_data { 2528 /** 2529 * 16-bit value dicated by driver that will enable/disable different functionality. 2530 */ 2531 uint16_t psr_level; 2532 /** 2533 * PSR control version. 2534 */ 2535 uint8_t cmd_version; 2536 /** 2537 * Panel Instance. 2538 * Panel instance to identify which psr_state to use 2539 * Currently the support is only for 0 or 1 2540 */ 2541 uint8_t panel_inst; 2542 }; 2543 2544 /** 2545 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2546 */ 2547 struct dmub_rb_cmd_psr_set_level { 2548 /** 2549 * Command header. 2550 */ 2551 struct dmub_cmd_header header; 2552 /** 2553 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2554 */ 2555 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2556 }; 2557 2558 struct dmub_rb_cmd_psr_enable_data { 2559 /** 2560 * PSR control version. 2561 */ 2562 uint8_t cmd_version; 2563 /** 2564 * Panel Instance. 2565 * Panel instance to identify which psr_state to use 2566 * Currently the support is only for 0 or 1 2567 */ 2568 uint8_t panel_inst; 2569 /** 2570 * Phy state to enter. 2571 * Values to use are defined in dmub_phy_fsm_state 2572 */ 2573 uint8_t phy_fsm_state; 2574 /** 2575 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2576 * Set this using enum phy_link_rate. 2577 * This does not support HDMI/DP2 for now. 2578 */ 2579 uint8_t phy_rate; 2580 }; 2581 2582 /** 2583 * Definition of a DMUB_CMD__PSR_ENABLE command. 2584 * PSR enable/disable is controlled using the sub_type. 2585 */ 2586 struct dmub_rb_cmd_psr_enable { 2587 /** 2588 * Command header. 2589 */ 2590 struct dmub_cmd_header header; 2591 2592 struct dmub_rb_cmd_psr_enable_data data; 2593 }; 2594 2595 /** 2596 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2597 */ 2598 struct dmub_cmd_psr_set_version_data { 2599 /** 2600 * PSR version that FW should implement. 2601 */ 2602 enum psr_version version; 2603 /** 2604 * PSR control version. 2605 */ 2606 uint8_t cmd_version; 2607 /** 2608 * Panel Instance. 2609 * Panel instance to identify which psr_state to use 2610 * Currently the support is only for 0 or 1 2611 */ 2612 uint8_t panel_inst; 2613 /** 2614 * Explicit padding to 4 byte boundary. 2615 */ 2616 uint8_t pad[2]; 2617 }; 2618 2619 /** 2620 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2621 */ 2622 struct dmub_rb_cmd_psr_set_version { 2623 /** 2624 * Command header. 2625 */ 2626 struct dmub_cmd_header header; 2627 /** 2628 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2629 */ 2630 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2631 }; 2632 2633 struct dmub_cmd_psr_force_static_data { 2634 /** 2635 * PSR control version. 2636 */ 2637 uint8_t cmd_version; 2638 /** 2639 * Panel Instance. 2640 * Panel instance to identify which psr_state to use 2641 * Currently the support is only for 0 or 1 2642 */ 2643 uint8_t panel_inst; 2644 /** 2645 * Explicit padding to 4 byte boundary. 2646 */ 2647 uint8_t pad[2]; 2648 }; 2649 2650 /** 2651 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2652 */ 2653 struct dmub_rb_cmd_psr_force_static { 2654 /** 2655 * Command header. 2656 */ 2657 struct dmub_cmd_header header; 2658 /** 2659 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2660 */ 2661 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2662 }; 2663 2664 /** 2665 * PSR SU debug flags. 2666 */ 2667 union dmub_psr_su_debug_flags { 2668 /** 2669 * PSR SU debug flags. 2670 */ 2671 struct { 2672 /** 2673 * Update dirty rect in SW only. 2674 */ 2675 uint8_t update_dirty_rect_only : 1; 2676 /** 2677 * Reset the cursor/plane state before processing the call. 2678 */ 2679 uint8_t reset_state : 1; 2680 } bitfields; 2681 2682 /** 2683 * Union for debug flags. 2684 */ 2685 uint32_t u32All; 2686 }; 2687 2688 /** 2689 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2690 * This triggers a selective update for PSR SU. 2691 */ 2692 struct dmub_cmd_update_dirty_rect_data { 2693 /** 2694 * Dirty rects from OS. 2695 */ 2696 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2697 /** 2698 * PSR SU debug flags. 2699 */ 2700 union dmub_psr_su_debug_flags debug_flags; 2701 /** 2702 * OTG HW instance. 2703 */ 2704 uint8_t pipe_idx; 2705 /** 2706 * Number of dirty rects. 2707 */ 2708 uint8_t dirty_rect_count; 2709 /** 2710 * PSR control version. 2711 */ 2712 uint8_t cmd_version; 2713 /** 2714 * Panel Instance. 2715 * Panel instance to identify which psr_state to use 2716 * Currently the support is only for 0 or 1 2717 */ 2718 uint8_t panel_inst; 2719 }; 2720 2721 /** 2722 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2723 */ 2724 struct dmub_rb_cmd_update_dirty_rect { 2725 /** 2726 * Command header. 2727 */ 2728 struct dmub_cmd_header header; 2729 /** 2730 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2731 */ 2732 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2733 }; 2734 2735 /** 2736 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2737 */ 2738 union dmub_reg_cursor_control_cfg { 2739 struct { 2740 uint32_t cur_enable: 1; 2741 uint32_t reser0: 3; 2742 uint32_t cur_2x_magnify: 1; 2743 uint32_t reser1: 3; 2744 uint32_t mode: 3; 2745 uint32_t reser2: 5; 2746 uint32_t pitch: 2; 2747 uint32_t reser3: 6; 2748 uint32_t line_per_chunk: 5; 2749 uint32_t reser4: 3; 2750 } bits; 2751 uint32_t raw; 2752 }; 2753 struct dmub_cursor_position_cache_hubp { 2754 union dmub_reg_cursor_control_cfg cur_ctl; 2755 union dmub_reg_position_cfg { 2756 struct { 2757 uint32_t cur_x_pos: 16; 2758 uint32_t cur_y_pos: 16; 2759 } bits; 2760 uint32_t raw; 2761 } position; 2762 union dmub_reg_hot_spot_cfg { 2763 struct { 2764 uint32_t hot_x: 16; 2765 uint32_t hot_y: 16; 2766 } bits; 2767 uint32_t raw; 2768 } hot_spot; 2769 union dmub_reg_dst_offset_cfg { 2770 struct { 2771 uint32_t dst_x_offset: 13; 2772 uint32_t reserved: 19; 2773 } bits; 2774 uint32_t raw; 2775 } dst_offset; 2776 }; 2777 2778 union dmub_reg_cur0_control_cfg { 2779 struct { 2780 uint32_t cur0_enable: 1; 2781 uint32_t expansion_mode: 1; 2782 uint32_t reser0: 1; 2783 uint32_t cur0_rom_en: 1; 2784 uint32_t mode: 3; 2785 uint32_t reserved: 25; 2786 } bits; 2787 uint32_t raw; 2788 }; 2789 struct dmub_cursor_position_cache_dpp { 2790 union dmub_reg_cur0_control_cfg cur0_ctl; 2791 }; 2792 struct dmub_cursor_position_cfg { 2793 struct dmub_cursor_position_cache_hubp pHubp; 2794 struct dmub_cursor_position_cache_dpp pDpp; 2795 uint8_t pipe_idx; 2796 /* 2797 * Padding is required. To be 4 Bytes Aligned. 2798 */ 2799 uint8_t padding[3]; 2800 }; 2801 2802 struct dmub_cursor_attribute_cache_hubp { 2803 uint32_t SURFACE_ADDR_HIGH; 2804 uint32_t SURFACE_ADDR; 2805 union dmub_reg_cursor_control_cfg cur_ctl; 2806 union dmub_reg_cursor_size_cfg { 2807 struct { 2808 uint32_t width: 16; 2809 uint32_t height: 16; 2810 } bits; 2811 uint32_t raw; 2812 } size; 2813 union dmub_reg_cursor_settings_cfg { 2814 struct { 2815 uint32_t dst_y_offset: 8; 2816 uint32_t chunk_hdl_adjust: 2; 2817 uint32_t reserved: 22; 2818 } bits; 2819 uint32_t raw; 2820 } settings; 2821 }; 2822 struct dmub_cursor_attribute_cache_dpp { 2823 union dmub_reg_cur0_control_cfg cur0_ctl; 2824 }; 2825 struct dmub_cursor_attributes_cfg { 2826 struct dmub_cursor_attribute_cache_hubp aHubp; 2827 struct dmub_cursor_attribute_cache_dpp aDpp; 2828 }; 2829 2830 struct dmub_cmd_update_cursor_payload0 { 2831 /** 2832 * Cursor dirty rects. 2833 */ 2834 struct dmub_rect cursor_rect; 2835 /** 2836 * PSR SU debug flags. 2837 */ 2838 union dmub_psr_su_debug_flags debug_flags; 2839 /** 2840 * Cursor enable/disable. 2841 */ 2842 uint8_t enable; 2843 /** 2844 * OTG HW instance. 2845 */ 2846 uint8_t pipe_idx; 2847 /** 2848 * PSR control version. 2849 */ 2850 uint8_t cmd_version; 2851 /** 2852 * Panel Instance. 2853 * Panel instance to identify which psr_state to use 2854 * Currently the support is only for 0 or 1 2855 */ 2856 uint8_t panel_inst; 2857 /** 2858 * Cursor Position Register. 2859 * Registers contains Hubp & Dpp modules 2860 */ 2861 struct dmub_cursor_position_cfg position_cfg; 2862 }; 2863 2864 struct dmub_cmd_update_cursor_payload1 { 2865 struct dmub_cursor_attributes_cfg attribute_cfg; 2866 }; 2867 2868 union dmub_cmd_update_cursor_info_data { 2869 struct dmub_cmd_update_cursor_payload0 payload0; 2870 struct dmub_cmd_update_cursor_payload1 payload1; 2871 }; 2872 /** 2873 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2874 */ 2875 struct dmub_rb_cmd_update_cursor_info { 2876 /** 2877 * Command header. 2878 */ 2879 struct dmub_cmd_header header; 2880 /** 2881 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2882 */ 2883 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2884 }; 2885 2886 /** 2887 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2888 */ 2889 struct dmub_cmd_psr_set_vtotal_data { 2890 /** 2891 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2892 */ 2893 uint16_t psr_vtotal_idle; 2894 /** 2895 * PSR control version. 2896 */ 2897 uint8_t cmd_version; 2898 /** 2899 * Panel Instance. 2900 * Panel instance to identify which psr_state to use 2901 * Currently the support is only for 0 or 1 2902 */ 2903 uint8_t panel_inst; 2904 /* 2905 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2906 */ 2907 uint16_t psr_vtotal_su; 2908 /** 2909 * Explicit padding to 4 byte boundary. 2910 */ 2911 uint8_t pad2[2]; 2912 }; 2913 2914 /** 2915 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2916 */ 2917 struct dmub_rb_cmd_psr_set_vtotal { 2918 /** 2919 * Command header. 2920 */ 2921 struct dmub_cmd_header header; 2922 /** 2923 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2924 */ 2925 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2926 }; 2927 2928 /** 2929 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2930 */ 2931 struct dmub_cmd_psr_set_power_opt_data { 2932 /** 2933 * PSR control version. 2934 */ 2935 uint8_t cmd_version; 2936 /** 2937 * Panel Instance. 2938 * Panel instance to identify which psr_state to use 2939 * Currently the support is only for 0 or 1 2940 */ 2941 uint8_t panel_inst; 2942 /** 2943 * Explicit padding to 4 byte boundary. 2944 */ 2945 uint8_t pad[2]; 2946 /** 2947 * PSR power option 2948 */ 2949 uint32_t power_opt; 2950 }; 2951 2952 /** 2953 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2954 */ 2955 struct dmub_rb_cmd_psr_set_power_opt { 2956 /** 2957 * Command header. 2958 */ 2959 struct dmub_cmd_header header; 2960 /** 2961 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2962 */ 2963 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2964 }; 2965 2966 /** 2967 * Definition of Replay Residency GPINT command. 2968 * Bit[0] - Residency mode for Revision 0 2969 * Bit[1] - Enable/Disable state 2970 * Bit[2-3] - Revision number 2971 * Bit[4-7] - Residency mode for Revision 1 2972 * Bit[8] - Panel instance 2973 * Bit[9-15] - Reserved 2974 */ 2975 2976 enum pr_residency_mode { 2977 PR_RESIDENCY_MODE_PHY = 0x0, 2978 PR_RESIDENCY_MODE_ALPM, 2979 PR_RESIDENCY_MODE_IPS2, 2980 PR_RESIDENCY_MODE_FRAME_CNT, 2981 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2982 }; 2983 2984 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 2985 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 2986 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 2987 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 2988 2989 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2990 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 2991 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2992 2993 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 2994 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 2995 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 2996 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 2997 2998 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2999 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3000 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3001 3002 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3003 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3004 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3005 3006 /** 3007 * Definition of a replay_state. 3008 */ 3009 enum replay_state { 3010 REPLAY_STATE_0 = 0x0, 3011 REPLAY_STATE_1 = 0x10, 3012 REPLAY_STATE_1A = 0x11, 3013 REPLAY_STATE_2 = 0x20, 3014 REPLAY_STATE_3 = 0x30, 3015 REPLAY_STATE_3INIT = 0x31, 3016 REPLAY_STATE_4 = 0x40, 3017 REPLAY_STATE_4A = 0x41, 3018 REPLAY_STATE_4B = 0x42, 3019 REPLAY_STATE_4C = 0x43, 3020 REPLAY_STATE_4D = 0x44, 3021 REPLAY_STATE_4B_LOCKED = 0x4A, 3022 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3023 REPLAY_STATE_5 = 0x50, 3024 REPLAY_STATE_5A = 0x51, 3025 REPLAY_STATE_5B = 0x52, 3026 REPLAY_STATE_5A_LOCKED = 0x5A, 3027 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3028 REPLAY_STATE_6 = 0x60, 3029 REPLAY_STATE_6A = 0x61, 3030 REPLAY_STATE_6B = 0x62, 3031 REPLAY_STATE_INVALID = 0xFF, 3032 }; 3033 3034 /** 3035 * Replay command sub-types. 3036 */ 3037 enum dmub_cmd_replay_type { 3038 /** 3039 * Copy driver-calculated parameters to REPLAY state. 3040 */ 3041 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3042 /** 3043 * Enable REPLAY. 3044 */ 3045 DMUB_CMD__REPLAY_ENABLE = 1, 3046 /** 3047 * Set Replay power option. 3048 */ 3049 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3050 /** 3051 * Set coasting vtotal. 3052 */ 3053 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3054 /** 3055 * Set power opt and coasting vtotal. 3056 */ 3057 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3058 /** 3059 * Set disabled iiming sync. 3060 */ 3061 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3062 /** 3063 * Set Residency Frameupdate Timer. 3064 */ 3065 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3066 /** 3067 * Set pseudo vtotal 3068 */ 3069 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3070 /** 3071 * Set adaptive sync sdp enabled 3072 */ 3073 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3074 3075 }; 3076 3077 /** 3078 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3079 */ 3080 struct dmub_cmd_replay_copy_settings_data { 3081 /** 3082 * Flags that can be set by driver to change some replay behaviour. 3083 */ 3084 union replay_debug_flags debug; 3085 3086 /** 3087 * @flags: Flags used to determine feature functionality. 3088 */ 3089 union replay_hw_flags flags; 3090 3091 /** 3092 * DPP HW instance. 3093 */ 3094 uint8_t dpp_inst; 3095 /** 3096 * OTG HW instance. 3097 */ 3098 uint8_t otg_inst; 3099 /** 3100 * DIG FE HW instance. 3101 */ 3102 uint8_t digfe_inst; 3103 /** 3104 * DIG BE HW instance. 3105 */ 3106 uint8_t digbe_inst; 3107 /** 3108 * AUX HW instance. 3109 */ 3110 uint8_t aux_inst; 3111 /** 3112 * Panel Instance. 3113 * Panel isntance to identify which psr_state to use 3114 * Currently the support is only for 0 or 1 3115 */ 3116 uint8_t panel_inst; 3117 /** 3118 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3119 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3120 */ 3121 uint8_t pixel_deviation_per_line; 3122 /** 3123 * @max_deviation_line: The max number of deviation line that can keep the timing 3124 * synchronized between the Source and Sink during Replay normal sleep mode. 3125 */ 3126 uint8_t max_deviation_line; 3127 /** 3128 * Length of each horizontal line in ns. 3129 */ 3130 uint32_t line_time_in_ns; 3131 /** 3132 * PHY instance. 3133 */ 3134 uint8_t dpphy_inst; 3135 /** 3136 * Determines if SMU optimzations are enabled/disabled. 3137 */ 3138 uint8_t smu_optimizations_en; 3139 /** 3140 * Determines if timing sync are enabled/disabled. 3141 */ 3142 uint8_t replay_timing_sync_supported; 3143 /* 3144 * Use FSM state for Replay power up/down 3145 */ 3146 uint8_t use_phy_fsm; 3147 }; 3148 3149 /** 3150 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3151 */ 3152 struct dmub_rb_cmd_replay_copy_settings { 3153 /** 3154 * Command header. 3155 */ 3156 struct dmub_cmd_header header; 3157 /** 3158 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3159 */ 3160 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3161 }; 3162 3163 /** 3164 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3165 */ 3166 enum replay_enable { 3167 /** 3168 * Disable REPLAY. 3169 */ 3170 REPLAY_DISABLE = 0, 3171 /** 3172 * Enable REPLAY. 3173 */ 3174 REPLAY_ENABLE = 1, 3175 }; 3176 3177 /** 3178 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3179 */ 3180 struct dmub_rb_cmd_replay_enable_data { 3181 /** 3182 * Replay enable or disable. 3183 */ 3184 uint8_t enable; 3185 /** 3186 * Panel Instance. 3187 * Panel isntance to identify which replay_state to use 3188 * Currently the support is only for 0 or 1 3189 */ 3190 uint8_t panel_inst; 3191 /** 3192 * Phy state to enter. 3193 * Values to use are defined in dmub_phy_fsm_state 3194 */ 3195 uint8_t phy_fsm_state; 3196 /** 3197 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3198 * Set this using enum phy_link_rate. 3199 * This does not support HDMI/DP2 for now. 3200 */ 3201 uint8_t phy_rate; 3202 }; 3203 3204 /** 3205 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3206 * Replay enable/disable is controlled using action in data. 3207 */ 3208 struct dmub_rb_cmd_replay_enable { 3209 /** 3210 * Command header. 3211 */ 3212 struct dmub_cmd_header header; 3213 3214 struct dmub_rb_cmd_replay_enable_data data; 3215 }; 3216 3217 /** 3218 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3219 */ 3220 struct dmub_cmd_replay_set_power_opt_data { 3221 /** 3222 * Panel Instance. 3223 * Panel isntance to identify which replay_state to use 3224 * Currently the support is only for 0 or 1 3225 */ 3226 uint8_t panel_inst; 3227 /** 3228 * Explicit padding to 4 byte boundary. 3229 */ 3230 uint8_t pad[3]; 3231 /** 3232 * REPLAY power option 3233 */ 3234 uint32_t power_opt; 3235 }; 3236 3237 /** 3238 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3239 */ 3240 struct dmub_cmd_replay_set_timing_sync_data { 3241 /** 3242 * Panel Instance. 3243 * Panel isntance to identify which replay_state to use 3244 * Currently the support is only for 0 or 1 3245 */ 3246 uint8_t panel_inst; 3247 /** 3248 * REPLAY set_timing_sync 3249 */ 3250 uint8_t timing_sync_supported; 3251 /** 3252 * Explicit padding to 4 byte boundary. 3253 */ 3254 uint8_t pad[2]; 3255 }; 3256 3257 /** 3258 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3259 */ 3260 struct dmub_cmd_replay_set_pseudo_vtotal { 3261 /** 3262 * Panel Instance. 3263 * Panel isntance to identify which replay_state to use 3264 * Currently the support is only for 0 or 1 3265 */ 3266 uint8_t panel_inst; 3267 /** 3268 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3269 */ 3270 uint16_t vtotal; 3271 /** 3272 * Explicit padding to 4 byte boundary. 3273 */ 3274 uint8_t pad; 3275 }; 3276 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3277 /** 3278 * Panel Instance. 3279 * Panel isntance to identify which replay_state to use 3280 * Currently the support is only for 0 or 1 3281 */ 3282 uint8_t panel_inst; 3283 /** 3284 * enabled: set adaptive sync sdp enabled 3285 */ 3286 uint8_t force_disabled; 3287 3288 uint8_t pad[2]; 3289 }; 3290 3291 /** 3292 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3293 */ 3294 struct dmub_rb_cmd_replay_set_power_opt { 3295 /** 3296 * Command header. 3297 */ 3298 struct dmub_cmd_header header; 3299 /** 3300 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3301 */ 3302 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3303 }; 3304 3305 /** 3306 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3307 */ 3308 struct dmub_cmd_replay_set_coasting_vtotal_data { 3309 /** 3310 * 16-bit value dicated by driver that indicates the coasting vtotal. 3311 */ 3312 uint16_t coasting_vtotal; 3313 /** 3314 * REPLAY control version. 3315 */ 3316 uint8_t cmd_version; 3317 /** 3318 * Panel Instance. 3319 * Panel isntance to identify which replay_state to use 3320 * Currently the support is only for 0 or 1 3321 */ 3322 uint8_t panel_inst; 3323 /** 3324 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3325 */ 3326 uint16_t coasting_vtotal_high; 3327 /** 3328 * Explicit padding to 4 byte boundary. 3329 */ 3330 uint8_t pad[2]; 3331 }; 3332 3333 /** 3334 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3335 */ 3336 struct dmub_rb_cmd_replay_set_coasting_vtotal { 3337 /** 3338 * Command header. 3339 */ 3340 struct dmub_cmd_header header; 3341 /** 3342 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3343 */ 3344 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3345 }; 3346 3347 /** 3348 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3349 */ 3350 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3351 /** 3352 * Command header. 3353 */ 3354 struct dmub_cmd_header header; 3355 /** 3356 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3357 */ 3358 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3359 /** 3360 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3361 */ 3362 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3363 }; 3364 3365 /** 3366 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3367 */ 3368 struct dmub_rb_cmd_replay_set_timing_sync { 3369 /** 3370 * Command header. 3371 */ 3372 struct dmub_cmd_header header; 3373 /** 3374 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3375 */ 3376 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3377 }; 3378 3379 /** 3380 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3381 */ 3382 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3383 /** 3384 * Command header. 3385 */ 3386 struct dmub_cmd_header header; 3387 /** 3388 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3389 */ 3390 struct dmub_cmd_replay_set_pseudo_vtotal data; 3391 }; 3392 3393 /** 3394 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3395 */ 3396 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 3397 /** 3398 * Command header. 3399 */ 3400 struct dmub_cmd_header header; 3401 /** 3402 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 3403 */ 3404 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 3405 }; 3406 3407 /** 3408 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3409 */ 3410 struct dmub_cmd_replay_frameupdate_timer_data { 3411 /** 3412 * Panel Instance. 3413 * Panel isntance to identify which replay_state to use 3414 * Currently the support is only for 0 or 1 3415 */ 3416 uint8_t panel_inst; 3417 /** 3418 * Replay Frameupdate Timer Enable or not 3419 */ 3420 uint8_t enable; 3421 /** 3422 * REPLAY force reflash frame update number 3423 */ 3424 uint16_t frameupdate_count; 3425 }; 3426 /** 3427 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3428 */ 3429 struct dmub_rb_cmd_replay_set_frameupdate_timer { 3430 /** 3431 * Command header. 3432 */ 3433 struct dmub_cmd_header header; 3434 /** 3435 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3436 */ 3437 struct dmub_cmd_replay_frameupdate_timer_data data; 3438 }; 3439 3440 /** 3441 * Definition union of replay command set 3442 */ 3443 union dmub_replay_cmd_set { 3444 /** 3445 * Panel Instance. 3446 * Panel isntance to identify which replay_state to use 3447 * Currently the support is only for 0 or 1 3448 */ 3449 uint8_t panel_inst; 3450 /** 3451 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 3452 */ 3453 struct dmub_cmd_replay_set_timing_sync_data sync_data; 3454 /** 3455 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 3456 */ 3457 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 3458 /** 3459 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 3460 */ 3461 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 3462 /** 3463 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 3464 */ 3465 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 3466 3467 }; 3468 3469 /** 3470 * Set of HW components that can be locked. 3471 * 3472 * Note: If updating with more HW components, fields 3473 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3474 */ 3475 union dmub_hw_lock_flags { 3476 /** 3477 * Set of HW components that can be locked. 3478 */ 3479 struct { 3480 /** 3481 * Lock/unlock OTG master update lock. 3482 */ 3483 uint8_t lock_pipe : 1; 3484 /** 3485 * Lock/unlock cursor. 3486 */ 3487 uint8_t lock_cursor : 1; 3488 /** 3489 * Lock/unlock global update lock. 3490 */ 3491 uint8_t lock_dig : 1; 3492 /** 3493 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3494 */ 3495 uint8_t triple_buffer_lock : 1; 3496 } bits; 3497 3498 /** 3499 * Union for HW Lock flags. 3500 */ 3501 uint8_t u8All; 3502 }; 3503 3504 /** 3505 * Instances of HW to be locked. 3506 * 3507 * Note: If updating with more HW components, fields 3508 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3509 */ 3510 struct dmub_hw_lock_inst_flags { 3511 /** 3512 * OTG HW instance for OTG master update lock. 3513 */ 3514 uint8_t otg_inst; 3515 /** 3516 * OPP instance for cursor lock. 3517 */ 3518 uint8_t opp_inst; 3519 /** 3520 * OTG HW instance for global update lock. 3521 * TODO: Remove, and re-use otg_inst. 3522 */ 3523 uint8_t dig_inst; 3524 /** 3525 * Explicit pad to 4 byte boundary. 3526 */ 3527 uint8_t pad; 3528 }; 3529 3530 /** 3531 * Clients that can acquire the HW Lock Manager. 3532 * 3533 * Note: If updating with more clients, fields in 3534 * dmub_inbox0_cmd_lock_hw must be updated to match. 3535 */ 3536 enum hw_lock_client { 3537 /** 3538 * Driver is the client of HW Lock Manager. 3539 */ 3540 HW_LOCK_CLIENT_DRIVER = 0, 3541 /** 3542 * PSR SU is the client of HW Lock Manager. 3543 */ 3544 HW_LOCK_CLIENT_PSR_SU = 1, 3545 HW_LOCK_CLIENT_SUBVP = 3, 3546 /** 3547 * Replay is the client of HW Lock Manager. 3548 */ 3549 HW_LOCK_CLIENT_REPLAY = 4, 3550 /** 3551 * Invalid client. 3552 */ 3553 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3554 }; 3555 3556 /** 3557 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3558 */ 3559 struct dmub_cmd_lock_hw_data { 3560 /** 3561 * Specifies the client accessing HW Lock Manager. 3562 */ 3563 enum hw_lock_client client; 3564 /** 3565 * HW instances to be locked. 3566 */ 3567 struct dmub_hw_lock_inst_flags inst_flags; 3568 /** 3569 * Which components to be locked. 3570 */ 3571 union dmub_hw_lock_flags hw_locks; 3572 /** 3573 * Specifies lock/unlock. 3574 */ 3575 uint8_t lock; 3576 /** 3577 * HW can be unlocked separately from releasing the HW Lock Mgr. 3578 * This flag is set if the client wishes to release the object. 3579 */ 3580 uint8_t should_release; 3581 /** 3582 * Explicit padding to 4 byte boundary. 3583 */ 3584 uint8_t pad; 3585 }; 3586 3587 /** 3588 * Definition of a DMUB_CMD__HW_LOCK command. 3589 * Command is used by driver and FW. 3590 */ 3591 struct dmub_rb_cmd_lock_hw { 3592 /** 3593 * Command header. 3594 */ 3595 struct dmub_cmd_header header; 3596 /** 3597 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3598 */ 3599 struct dmub_cmd_lock_hw_data lock_hw_data; 3600 }; 3601 3602 /** 3603 * ABM command sub-types. 3604 */ 3605 enum dmub_cmd_abm_type { 3606 /** 3607 * Initialize parameters for ABM algorithm. 3608 * Data is passed through an indirect buffer. 3609 */ 3610 DMUB_CMD__ABM_INIT_CONFIG = 0, 3611 /** 3612 * Set OTG and panel HW instance. 3613 */ 3614 DMUB_CMD__ABM_SET_PIPE = 1, 3615 /** 3616 * Set user requested backklight level. 3617 */ 3618 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3619 /** 3620 * Set ABM operating/aggression level. 3621 */ 3622 DMUB_CMD__ABM_SET_LEVEL = 3, 3623 /** 3624 * Set ambient light level. 3625 */ 3626 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 3627 /** 3628 * Enable/disable fractional duty cycle for backlight PWM. 3629 */ 3630 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 3631 3632 /** 3633 * unregister vertical interrupt after steady state is reached 3634 */ 3635 DMUB_CMD__ABM_PAUSE = 6, 3636 3637 /** 3638 * Save and Restore ABM state. On save we save parameters, and 3639 * on restore we update state with passed in data. 3640 */ 3641 DMUB_CMD__ABM_SAVE_RESTORE = 7, 3642 }; 3643 3644 /** 3645 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 3646 * Requirements: 3647 * - Padded explicitly to 32-bit boundary. 3648 * - Must ensure this structure matches the one on driver-side, 3649 * otherwise it won't be aligned. 3650 */ 3651 struct abm_config_table { 3652 /** 3653 * Gamma curve thresholds, used for crgb conversion. 3654 */ 3655 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 3656 /** 3657 * Gamma curve offsets, used for crgb conversion. 3658 */ 3659 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 3660 /** 3661 * Gamma curve slopes, used for crgb conversion. 3662 */ 3663 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 3664 /** 3665 * Custom backlight curve thresholds. 3666 */ 3667 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 3668 /** 3669 * Custom backlight curve offsets. 3670 */ 3671 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 3672 /** 3673 * Ambient light thresholds. 3674 */ 3675 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 3676 /** 3677 * Minimum programmable backlight. 3678 */ 3679 uint16_t min_abm_backlight; // 122B 3680 /** 3681 * Minimum reduction values. 3682 */ 3683 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 3684 /** 3685 * Maximum reduction values. 3686 */ 3687 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 3688 /** 3689 * Bright positive gain. 3690 */ 3691 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 3692 /** 3693 * Dark negative gain. 3694 */ 3695 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 3696 /** 3697 * Hybrid factor. 3698 */ 3699 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 3700 /** 3701 * Contrast factor. 3702 */ 3703 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 3704 /** 3705 * Deviation gain. 3706 */ 3707 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 3708 /** 3709 * Minimum knee. 3710 */ 3711 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 3712 /** 3713 * Maximum knee. 3714 */ 3715 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 3716 /** 3717 * Unused. 3718 */ 3719 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 3720 /** 3721 * Explicit padding to 4 byte boundary. 3722 */ 3723 uint8_t pad3[3]; // 229B 3724 /** 3725 * Backlight ramp reduction. 3726 */ 3727 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 3728 /** 3729 * Backlight ramp start. 3730 */ 3731 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 3732 }; 3733 3734 /** 3735 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3736 */ 3737 struct dmub_cmd_abm_set_pipe_data { 3738 /** 3739 * OTG HW instance. 3740 */ 3741 uint8_t otg_inst; 3742 3743 /** 3744 * Panel Control HW instance. 3745 */ 3746 uint8_t panel_inst; 3747 3748 /** 3749 * Controls how ABM will interpret a set pipe or set level command. 3750 */ 3751 uint8_t set_pipe_option; 3752 3753 /** 3754 * Unused. 3755 * TODO: Remove. 3756 */ 3757 uint8_t ramping_boundary; 3758 3759 /** 3760 * PwrSeq HW Instance. 3761 */ 3762 uint8_t pwrseq_inst; 3763 3764 /** 3765 * Explicit padding to 4 byte boundary. 3766 */ 3767 uint8_t pad[3]; 3768 }; 3769 3770 /** 3771 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3772 */ 3773 struct dmub_rb_cmd_abm_set_pipe { 3774 /** 3775 * Command header. 3776 */ 3777 struct dmub_cmd_header header; 3778 3779 /** 3780 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3781 */ 3782 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 3783 }; 3784 3785 /** 3786 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3787 */ 3788 struct dmub_cmd_abm_set_backlight_data { 3789 /** 3790 * Number of frames to ramp to backlight user level. 3791 */ 3792 uint32_t frame_ramp; 3793 3794 /** 3795 * Requested backlight level from user. 3796 */ 3797 uint32_t backlight_user_level; 3798 3799 /** 3800 * ABM control version. 3801 */ 3802 uint8_t version; 3803 3804 /** 3805 * Panel Control HW instance mask. 3806 * Bit 0 is Panel Control HW instance 0. 3807 * Bit 1 is Panel Control HW instance 1. 3808 */ 3809 uint8_t panel_mask; 3810 3811 /** 3812 * Explicit padding to 4 byte boundary. 3813 */ 3814 uint8_t pad[2]; 3815 }; 3816 3817 /** 3818 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3819 */ 3820 struct dmub_rb_cmd_abm_set_backlight { 3821 /** 3822 * Command header. 3823 */ 3824 struct dmub_cmd_header header; 3825 3826 /** 3827 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3828 */ 3829 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 3830 }; 3831 3832 /** 3833 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3834 */ 3835 struct dmub_cmd_abm_set_level_data { 3836 /** 3837 * Set current ABM operating/aggression level. 3838 */ 3839 uint32_t level; 3840 3841 /** 3842 * ABM control version. 3843 */ 3844 uint8_t version; 3845 3846 /** 3847 * Panel Control HW instance mask. 3848 * Bit 0 is Panel Control HW instance 0. 3849 * Bit 1 is Panel Control HW instance 1. 3850 */ 3851 uint8_t panel_mask; 3852 3853 /** 3854 * Explicit padding to 4 byte boundary. 3855 */ 3856 uint8_t pad[2]; 3857 }; 3858 3859 /** 3860 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3861 */ 3862 struct dmub_rb_cmd_abm_set_level { 3863 /** 3864 * Command header. 3865 */ 3866 struct dmub_cmd_header header; 3867 3868 /** 3869 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3870 */ 3871 struct dmub_cmd_abm_set_level_data abm_set_level_data; 3872 }; 3873 3874 /** 3875 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3876 */ 3877 struct dmub_cmd_abm_set_ambient_level_data { 3878 /** 3879 * Ambient light sensor reading from OS. 3880 */ 3881 uint32_t ambient_lux; 3882 3883 /** 3884 * ABM control version. 3885 */ 3886 uint8_t version; 3887 3888 /** 3889 * Panel Control HW instance mask. 3890 * Bit 0 is Panel Control HW instance 0. 3891 * Bit 1 is Panel Control HW instance 1. 3892 */ 3893 uint8_t panel_mask; 3894 3895 /** 3896 * Explicit padding to 4 byte boundary. 3897 */ 3898 uint8_t pad[2]; 3899 }; 3900 3901 /** 3902 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3903 */ 3904 struct dmub_rb_cmd_abm_set_ambient_level { 3905 /** 3906 * Command header. 3907 */ 3908 struct dmub_cmd_header header; 3909 3910 /** 3911 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3912 */ 3913 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 3914 }; 3915 3916 /** 3917 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3918 */ 3919 struct dmub_cmd_abm_set_pwm_frac_data { 3920 /** 3921 * Enable/disable fractional duty cycle for backlight PWM. 3922 * TODO: Convert to uint8_t. 3923 */ 3924 uint32_t fractional_pwm; 3925 3926 /** 3927 * ABM control version. 3928 */ 3929 uint8_t version; 3930 3931 /** 3932 * Panel Control HW instance mask. 3933 * Bit 0 is Panel Control HW instance 0. 3934 * Bit 1 is Panel Control HW instance 1. 3935 */ 3936 uint8_t panel_mask; 3937 3938 /** 3939 * Explicit padding to 4 byte boundary. 3940 */ 3941 uint8_t pad[2]; 3942 }; 3943 3944 /** 3945 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3946 */ 3947 struct dmub_rb_cmd_abm_set_pwm_frac { 3948 /** 3949 * Command header. 3950 */ 3951 struct dmub_cmd_header header; 3952 3953 /** 3954 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3955 */ 3956 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 3957 }; 3958 3959 /** 3960 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3961 */ 3962 struct dmub_cmd_abm_init_config_data { 3963 /** 3964 * Location of indirect buffer used to pass init data to ABM. 3965 */ 3966 union dmub_addr src; 3967 3968 /** 3969 * Indirect buffer length. 3970 */ 3971 uint16_t bytes; 3972 3973 3974 /** 3975 * ABM control version. 3976 */ 3977 uint8_t version; 3978 3979 /** 3980 * Panel Control HW instance mask. 3981 * Bit 0 is Panel Control HW instance 0. 3982 * Bit 1 is Panel Control HW instance 1. 3983 */ 3984 uint8_t panel_mask; 3985 3986 /** 3987 * Explicit padding to 4 byte boundary. 3988 */ 3989 uint8_t pad[2]; 3990 }; 3991 3992 /** 3993 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3994 */ 3995 struct dmub_rb_cmd_abm_init_config { 3996 /** 3997 * Command header. 3998 */ 3999 struct dmub_cmd_header header; 4000 4001 /** 4002 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4003 */ 4004 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4005 }; 4006 4007 /** 4008 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4009 */ 4010 4011 struct dmub_cmd_abm_pause_data { 4012 4013 /** 4014 * Panel Control HW instance mask. 4015 * Bit 0 is Panel Control HW instance 0. 4016 * Bit 1 is Panel Control HW instance 1. 4017 */ 4018 uint8_t panel_mask; 4019 4020 /** 4021 * OTG hw instance 4022 */ 4023 uint8_t otg_inst; 4024 4025 /** 4026 * Enable or disable ABM pause 4027 */ 4028 uint8_t enable; 4029 4030 /** 4031 * Explicit padding to 4 byte boundary. 4032 */ 4033 uint8_t pad[1]; 4034 }; 4035 4036 /** 4037 * Definition of a DMUB_CMD__ABM_PAUSE command. 4038 */ 4039 struct dmub_rb_cmd_abm_pause { 4040 /** 4041 * Command header. 4042 */ 4043 struct dmub_cmd_header header; 4044 4045 /** 4046 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4047 */ 4048 struct dmub_cmd_abm_pause_data abm_pause_data; 4049 }; 4050 4051 /** 4052 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4053 */ 4054 struct dmub_rb_cmd_abm_save_restore { 4055 /** 4056 * Command header. 4057 */ 4058 struct dmub_cmd_header header; 4059 4060 /** 4061 * OTG hw instance 4062 */ 4063 uint8_t otg_inst; 4064 4065 /** 4066 * Enable or disable ABM pause 4067 */ 4068 uint8_t freeze; 4069 4070 /** 4071 * Explicit padding to 4 byte boundary. 4072 */ 4073 uint8_t debug; 4074 4075 /** 4076 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4077 */ 4078 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4079 }; 4080 4081 /** 4082 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4083 */ 4084 struct dmub_cmd_query_feature_caps_data { 4085 /** 4086 * DMUB feature capabilities. 4087 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 4088 */ 4089 struct dmub_feature_caps feature_caps; 4090 }; 4091 4092 /** 4093 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4094 */ 4095 struct dmub_rb_cmd_query_feature_caps { 4096 /** 4097 * Command header. 4098 */ 4099 struct dmub_cmd_header header; 4100 /** 4101 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4102 */ 4103 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4104 }; 4105 4106 /** 4107 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4108 */ 4109 struct dmub_cmd_visual_confirm_color_data { 4110 /** 4111 * DMUB visual confirm color 4112 */ 4113 struct dmub_visual_confirm_color visual_confirm_color; 4114 }; 4115 4116 /** 4117 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4118 */ 4119 struct dmub_rb_cmd_get_visual_confirm_color { 4120 /** 4121 * Command header. 4122 */ 4123 struct dmub_cmd_header header; 4124 /** 4125 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4126 */ 4127 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4128 }; 4129 4130 /** 4131 * enum dmub_cmd_panel_cntl_type - Panel control command. 4132 */ 4133 enum dmub_cmd_panel_cntl_type { 4134 /** 4135 * Initializes embedded panel hardware blocks. 4136 */ 4137 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4138 /** 4139 * Queries backlight info for the embedded panel. 4140 */ 4141 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4142 /** 4143 * Sets the PWM Freq as per user's requirement. 4144 */ 4145 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 4146 }; 4147 4148 /** 4149 * struct dmub_cmd_panel_cntl_data - Panel control data. 4150 */ 4151 struct dmub_cmd_panel_cntl_data { 4152 uint32_t pwrseq_inst; /**< pwrseq instance */ 4153 uint32_t current_backlight; /* in/out */ 4154 uint32_t bl_pwm_cntl; /* in/out */ 4155 uint32_t bl_pwm_period_cntl; /* in/out */ 4156 uint32_t bl_pwm_ref_div1; /* in/out */ 4157 uint8_t is_backlight_on : 1; /* in/out */ 4158 uint8_t is_powered_on : 1; /* in/out */ 4159 uint8_t padding[3]; 4160 uint32_t bl_pwm_ref_div2; /* in/out */ 4161 uint8_t reserved[4]; 4162 }; 4163 4164 /** 4165 * struct dmub_rb_cmd_panel_cntl - Panel control command. 4166 */ 4167 struct dmub_rb_cmd_panel_cntl { 4168 struct dmub_cmd_header header; /**< header */ 4169 struct dmub_cmd_panel_cntl_data data; /**< payload */ 4170 }; 4171 4172 struct dmub_optc_state { 4173 uint32_t v_total_max; 4174 uint32_t v_total_min; 4175 uint32_t tg_inst; 4176 }; 4177 4178 struct dmub_rb_cmd_drr_update { 4179 struct dmub_cmd_header header; 4180 struct dmub_optc_state dmub_optc_state_req; 4181 }; 4182 4183 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 4184 uint32_t pix_clk_100hz; 4185 uint8_t max_ramp_step; 4186 uint8_t pipes; 4187 uint8_t min_refresh_in_hz; 4188 uint8_t pipe_count; 4189 uint8_t pipe_index[4]; 4190 }; 4191 4192 struct dmub_cmd_fw_assisted_mclk_switch_config { 4193 uint8_t fams_enabled; 4194 uint8_t visual_confirm_enabled; 4195 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 4196 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 4197 }; 4198 4199 struct dmub_rb_cmd_fw_assisted_mclk_switch { 4200 struct dmub_cmd_header header; 4201 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 4202 }; 4203 4204 /** 4205 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4206 */ 4207 struct dmub_cmd_lvtma_control_data { 4208 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 4209 uint8_t bypass_panel_control_wait; 4210 uint8_t reserved_0[2]; /**< For future use */ 4211 uint8_t pwrseq_inst; /**< LVTMA control instance */ 4212 uint8_t reserved_1[3]; /**< For future use */ 4213 }; 4214 4215 /** 4216 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4217 */ 4218 struct dmub_rb_cmd_lvtma_control { 4219 /** 4220 * Command header. 4221 */ 4222 struct dmub_cmd_header header; 4223 /** 4224 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4225 */ 4226 struct dmub_cmd_lvtma_control_data data; 4227 }; 4228 4229 /** 4230 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4231 */ 4232 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 4233 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4234 uint8_t is_usb; /**< is phy is usb */ 4235 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 4236 uint8_t is_dp4; /**< is dp in 4 lane */ 4237 }; 4238 4239 /** 4240 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4241 */ 4242 struct dmub_rb_cmd_transmitter_query_dp_alt { 4243 struct dmub_cmd_header header; /**< header */ 4244 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 4245 }; 4246 4247 struct phy_test_mode { 4248 uint8_t mode; 4249 uint8_t pat0; 4250 uint8_t pad[2]; 4251 }; 4252 4253 /** 4254 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4255 */ 4256 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 4257 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4258 uint8_t mode; /**< HDMI/DP/DP2 etc */ 4259 uint8_t lane_num; /**< Number of lanes */ 4260 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 4261 struct phy_test_mode test_mode; 4262 enum dmub_phy_fsm_state state; 4263 uint32_t status; 4264 uint8_t pad; 4265 }; 4266 4267 /** 4268 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4269 */ 4270 struct dmub_rb_cmd_transmitter_set_phy_fsm { 4271 struct dmub_cmd_header header; /**< header */ 4272 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 4273 }; 4274 4275 /** 4276 * Maximum number of bytes a chunk sent to DMUB for parsing 4277 */ 4278 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 4279 4280 /** 4281 * Represent a chunk of CEA blocks sent to DMUB for parsing 4282 */ 4283 struct dmub_cmd_send_edid_cea { 4284 uint16_t offset; /**< offset into the CEA block */ 4285 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 4286 uint16_t cea_total_length; /**< total length of the CEA block */ 4287 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 4288 uint8_t pad[3]; /**< padding and for future expansion */ 4289 }; 4290 4291 /** 4292 * Result of VSDB parsing from CEA block 4293 */ 4294 struct dmub_cmd_edid_cea_amd_vsdb { 4295 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 4296 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 4297 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 4298 uint16_t min_frame_rate; /**< Maximum frame rate */ 4299 uint16_t max_frame_rate; /**< Minimum frame rate */ 4300 }; 4301 4302 /** 4303 * Result of sending a CEA chunk 4304 */ 4305 struct dmub_cmd_edid_cea_ack { 4306 uint16_t offset; /**< offset of the chunk into the CEA block */ 4307 uint8_t success; /**< 1 if this sending of chunk succeeded */ 4308 uint8_t pad; /**< padding and for future expansion */ 4309 }; 4310 4311 /** 4312 * Specify whether the result is an ACK/NACK or the parsing has finished 4313 */ 4314 enum dmub_cmd_edid_cea_reply_type { 4315 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 4316 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 4317 }; 4318 4319 /** 4320 * Definition of a DMUB_CMD__EDID_CEA command. 4321 */ 4322 struct dmub_rb_cmd_edid_cea { 4323 struct dmub_cmd_header header; /**< Command header */ 4324 union dmub_cmd_edid_cea_data { 4325 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 4326 struct dmub_cmd_edid_cea_output { /**< output with results */ 4327 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 4328 union { 4329 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 4330 struct dmub_cmd_edid_cea_ack ack; 4331 }; 4332 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 4333 } data; /**< Command data */ 4334 4335 }; 4336 4337 /** 4338 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 4339 */ 4340 struct dmub_cmd_cable_id_input { 4341 uint8_t phy_inst; /**< phy inst for cable id data */ 4342 }; 4343 4344 /** 4345 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 4346 */ 4347 struct dmub_cmd_cable_id_output { 4348 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 4349 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 4350 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 4351 uint8_t RESERVED :2; /**< reserved means not defined */ 4352 }; 4353 4354 /** 4355 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 4356 */ 4357 struct dmub_rb_cmd_get_usbc_cable_id { 4358 struct dmub_cmd_header header; /**< Command header */ 4359 /** 4360 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 4361 */ 4362 union dmub_cmd_cable_id_data { 4363 struct dmub_cmd_cable_id_input input; /**< Input */ 4364 struct dmub_cmd_cable_id_output output; /**< Output */ 4365 uint8_t output_raw; /**< Raw data output */ 4366 } data; 4367 }; 4368 4369 /** 4370 * Command type of a DMUB_CMD__SECURE_DISPLAY command 4371 */ 4372 enum dmub_cmd_secure_display_type { 4373 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 4374 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 4375 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 4376 }; 4377 4378 /** 4379 * Definition of a DMUB_CMD__SECURE_DISPLAY command 4380 */ 4381 struct dmub_rb_cmd_secure_display { 4382 struct dmub_cmd_header header; 4383 /** 4384 * Data passed from driver to dmub firmware. 4385 */ 4386 struct dmub_cmd_roi_info { 4387 uint16_t x_start; 4388 uint16_t x_end; 4389 uint16_t y_start; 4390 uint16_t y_end; 4391 uint8_t otg_id; 4392 uint8_t phy_id; 4393 } roi_info; 4394 }; 4395 4396 /** 4397 * Command type of a DMUB_CMD__PSP command 4398 */ 4399 enum dmub_cmd_psp_type { 4400 DMUB_CMD__PSP_ASSR_ENABLE = 0 4401 }; 4402 4403 /** 4404 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 4405 */ 4406 struct dmub_cmd_assr_enable_data { 4407 /** 4408 * ASSR enable or disable. 4409 */ 4410 uint8_t enable; 4411 /** 4412 * PHY port type. 4413 * Indicates eDP / non-eDP port type 4414 */ 4415 uint8_t phy_port_type; 4416 /** 4417 * PHY port ID. 4418 */ 4419 uint8_t phy_port_id; 4420 /** 4421 * Link encoder index. 4422 */ 4423 uint8_t link_enc_index; 4424 /** 4425 * HPO mode. 4426 */ 4427 uint8_t hpo_mode; 4428 4429 /** 4430 * Reserved field. 4431 */ 4432 uint8_t reserved[7]; 4433 }; 4434 4435 /** 4436 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 4437 */ 4438 struct dmub_rb_cmd_assr_enable { 4439 /** 4440 * Command header. 4441 */ 4442 struct dmub_cmd_header header; 4443 4444 /** 4445 * Assr data. 4446 */ 4447 struct dmub_cmd_assr_enable_data assr_data; 4448 4449 /** 4450 * Reserved field. 4451 */ 4452 uint32_t reserved[3]; 4453 }; 4454 4455 /** 4456 * union dmub_rb_cmd - DMUB inbox command. 4457 */ 4458 union dmub_rb_cmd { 4459 /** 4460 * Elements shared with all commands. 4461 */ 4462 struct dmub_rb_cmd_common cmd_common; 4463 /** 4464 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 4465 */ 4466 struct dmub_rb_cmd_read_modify_write read_modify_write; 4467 /** 4468 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 4469 */ 4470 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 4471 /** 4472 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 4473 */ 4474 struct dmub_rb_cmd_burst_write burst_write; 4475 /** 4476 * Definition of a DMUB_CMD__REG_REG_WAIT command. 4477 */ 4478 struct dmub_rb_cmd_reg_wait reg_wait; 4479 /** 4480 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 4481 */ 4482 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 4483 /** 4484 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 4485 */ 4486 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 4487 /** 4488 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 4489 */ 4490 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 4491 /** 4492 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 4493 */ 4494 struct dmub_rb_cmd_dpphy_init dpphy_init; 4495 /** 4496 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 4497 */ 4498 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 4499 /** 4500 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 4501 */ 4502 struct dmub_rb_cmd_domain_control domain_control; 4503 /** 4504 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 4505 */ 4506 struct dmub_rb_cmd_psr_set_version psr_set_version; 4507 /** 4508 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 4509 */ 4510 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 4511 /** 4512 * Definition of a DMUB_CMD__PSR_ENABLE command. 4513 */ 4514 struct dmub_rb_cmd_psr_enable psr_enable; 4515 /** 4516 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 4517 */ 4518 struct dmub_rb_cmd_psr_set_level psr_set_level; 4519 /** 4520 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 4521 */ 4522 struct dmub_rb_cmd_psr_force_static psr_force_static; 4523 /** 4524 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 4525 */ 4526 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 4527 /** 4528 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4529 */ 4530 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 4531 /** 4532 * Definition of a DMUB_CMD__HW_LOCK command. 4533 * Command is used by driver and FW. 4534 */ 4535 struct dmub_rb_cmd_lock_hw lock_hw; 4536 /** 4537 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4538 */ 4539 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 4540 /** 4541 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4542 */ 4543 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 4544 /** 4545 * Definition of a DMUB_CMD__PLAT_54186_WA command. 4546 */ 4547 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 4548 /** 4549 * Definition of a DMUB_CMD__MALL command. 4550 */ 4551 struct dmub_rb_cmd_mall mall; 4552 4553 /** 4554 * Definition of a DMUB_CMD__CAB command. 4555 */ 4556 struct dmub_rb_cmd_cab_for_ss cab; 4557 4558 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 4559 4560 /** 4561 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 4562 */ 4563 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 4564 4565 /** 4566 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 4567 */ 4568 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 4569 4570 /** 4571 * Definition of DMUB_CMD__PANEL_CNTL commands. 4572 */ 4573 struct dmub_rb_cmd_panel_cntl panel_cntl; 4574 4575 /** 4576 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4577 */ 4578 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 4579 4580 /** 4581 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4582 */ 4583 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 4584 4585 /** 4586 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4587 */ 4588 struct dmub_rb_cmd_abm_set_level abm_set_level; 4589 4590 /** 4591 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4592 */ 4593 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 4594 4595 /** 4596 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4597 */ 4598 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 4599 4600 /** 4601 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4602 */ 4603 struct dmub_rb_cmd_abm_init_config abm_init_config; 4604 4605 /** 4606 * Definition of a DMUB_CMD__ABM_PAUSE command. 4607 */ 4608 struct dmub_rb_cmd_abm_pause abm_pause; 4609 4610 /** 4611 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4612 */ 4613 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 4614 4615 /** 4616 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 4617 */ 4618 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 4619 4620 /** 4621 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 4622 */ 4623 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 4624 4625 /** 4626 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4627 */ 4628 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 4629 4630 /** 4631 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4632 */ 4633 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 4634 struct dmub_rb_cmd_drr_update drr_update; 4635 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 4636 4637 /** 4638 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4639 */ 4640 struct dmub_rb_cmd_lvtma_control lvtma_control; 4641 /** 4642 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4643 */ 4644 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 4645 /** 4646 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 4647 */ 4648 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 4649 /** 4650 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 4651 */ 4652 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 4653 /** 4654 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 4655 */ 4656 struct dmub_rb_cmd_set_config_access set_config_access; 4657 /** 4658 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 4659 */ 4660 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 4661 /** 4662 * Definition of a DMUB_CMD__EDID_CEA command. 4663 */ 4664 struct dmub_rb_cmd_edid_cea edid_cea; 4665 /** 4666 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 4667 */ 4668 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 4669 4670 /** 4671 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 4672 */ 4673 struct dmub_rb_cmd_query_hpd_state query_hpd; 4674 /** 4675 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 4676 */ 4677 struct dmub_rb_cmd_secure_display secure_display; 4678 4679 /** 4680 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 4681 */ 4682 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 4683 /** 4684 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 4685 */ 4686 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 4687 /* 4688 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4689 */ 4690 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 4691 /** 4692 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4693 */ 4694 struct dmub_rb_cmd_replay_enable replay_enable; 4695 /** 4696 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4697 */ 4698 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 4699 /** 4700 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4701 */ 4702 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 4703 /** 4704 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4705 */ 4706 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 4707 4708 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 4709 /** 4710 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4711 */ 4712 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 4713 /** 4714 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4715 */ 4716 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 4717 /** 4718 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4719 */ 4720 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 4721 /** 4722 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 4723 */ 4724 struct dmub_rb_cmd_assr_enable assr_enable; 4725 4726 }; 4727 4728 /** 4729 * union dmub_rb_out_cmd - Outbox command 4730 */ 4731 union dmub_rb_out_cmd { 4732 /** 4733 * Parameters common to every command. 4734 */ 4735 struct dmub_rb_cmd_common cmd_common; 4736 /** 4737 * AUX reply command. 4738 */ 4739 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 4740 /** 4741 * HPD notify command. 4742 */ 4743 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 4744 /** 4745 * SET_CONFIG reply command. 4746 */ 4747 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 4748 /** 4749 * DPIA notification command. 4750 */ 4751 struct dmub_rb_cmd_dpia_notification dpia_notification; 4752 }; 4753 #pragma pack(pop) 4754 4755 4756 //============================================================================== 4757 //</DMUB_CMD>=================================================================== 4758 //============================================================================== 4759 //< DMUB_RB>==================================================================== 4760 //============================================================================== 4761 4762 #if defined(__cplusplus) 4763 extern "C" { 4764 #endif 4765 4766 /** 4767 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 4768 */ 4769 struct dmub_rb_init_params { 4770 void *ctx; /**< Caller provided context pointer */ 4771 void *base_address; /**< CPU base address for ring's data */ 4772 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4773 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 4774 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 4775 }; 4776 4777 /** 4778 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 4779 */ 4780 struct dmub_rb { 4781 void *base_address; /**< CPU address for the ring's data */ 4782 uint32_t rptr; /**< Read pointer for consumer in bytes */ 4783 uint32_t wrpt; /**< Write pointer for producer in bytes */ 4784 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4785 4786 void *ctx; /**< Caller provided context pointer */ 4787 void *dmub; /**< Pointer to the DMUB interface */ 4788 }; 4789 4790 /** 4791 * @brief Checks if the ringbuffer is empty. 4792 * 4793 * @param rb DMUB Ringbuffer 4794 * @return true if empty 4795 * @return false otherwise 4796 */ 4797 static inline bool dmub_rb_empty(struct dmub_rb *rb) 4798 { 4799 return (rb->wrpt == rb->rptr); 4800 } 4801 4802 /** 4803 * @brief Checks if the ringbuffer is full 4804 * 4805 * @param rb DMUB Ringbuffer 4806 * @return true if full 4807 * @return false otherwise 4808 */ 4809 static inline bool dmub_rb_full(struct dmub_rb *rb) 4810 { 4811 uint32_t data_count; 4812 4813 if (rb->wrpt >= rb->rptr) 4814 data_count = rb->wrpt - rb->rptr; 4815 else 4816 data_count = rb->capacity - (rb->rptr - rb->wrpt); 4817 4818 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 4819 } 4820 4821 /** 4822 * @brief Pushes a command into the ringbuffer 4823 * 4824 * @param rb DMUB ringbuffer 4825 * @param cmd The command to push 4826 * @return true if the ringbuffer was not full 4827 * @return false otherwise 4828 */ 4829 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 4830 const union dmub_rb_cmd *cmd) 4831 { 4832 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 4833 const uint64_t *src = (const uint64_t *)cmd; 4834 uint8_t i; 4835 4836 if (dmub_rb_full(rb)) 4837 return false; 4838 4839 // copying data 4840 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4841 *dst++ = *src++; 4842 4843 rb->wrpt += DMUB_RB_CMD_SIZE; 4844 4845 if (rb->wrpt >= rb->capacity) 4846 rb->wrpt %= rb->capacity; 4847 4848 return true; 4849 } 4850 4851 /** 4852 * @brief Pushes a command into the DMUB outbox ringbuffer 4853 * 4854 * @param rb DMUB outbox ringbuffer 4855 * @param cmd Outbox command 4856 * @return true if not full 4857 * @return false otherwise 4858 */ 4859 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 4860 const union dmub_rb_out_cmd *cmd) 4861 { 4862 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 4863 const uint8_t *src = (const uint8_t *)cmd; 4864 4865 if (dmub_rb_full(rb)) 4866 return false; 4867 4868 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 4869 4870 rb->wrpt += DMUB_RB_CMD_SIZE; 4871 4872 if (rb->wrpt >= rb->capacity) 4873 rb->wrpt %= rb->capacity; 4874 4875 return true; 4876 } 4877 4878 /** 4879 * @brief Returns the next unprocessed command in the ringbuffer. 4880 * 4881 * @param rb DMUB ringbuffer 4882 * @param cmd The command to return 4883 * @return true if not empty 4884 * @return false otherwise 4885 */ 4886 static inline bool dmub_rb_front(struct dmub_rb *rb, 4887 union dmub_rb_cmd **cmd) 4888 { 4889 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 4890 4891 if (dmub_rb_empty(rb)) 4892 return false; 4893 4894 *cmd = (union dmub_rb_cmd *)rb_cmd; 4895 4896 return true; 4897 } 4898 4899 /** 4900 * @brief Determines the next ringbuffer offset. 4901 * 4902 * @param rb DMUB inbox ringbuffer 4903 * @param num_cmds Number of commands 4904 * @param next_rptr The next offset in the ringbuffer 4905 */ 4906 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 4907 uint32_t num_cmds, 4908 uint32_t *next_rptr) 4909 { 4910 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 4911 4912 if (*next_rptr >= rb->capacity) 4913 *next_rptr %= rb->capacity; 4914 } 4915 4916 /** 4917 * @brief Returns a pointer to a command in the inbox. 4918 * 4919 * @param rb DMUB inbox ringbuffer 4920 * @param cmd The inbox command to return 4921 * @param rptr The ringbuffer offset 4922 * @return true if not empty 4923 * @return false otherwise 4924 */ 4925 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 4926 union dmub_rb_cmd **cmd, 4927 uint32_t rptr) 4928 { 4929 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 4930 4931 if (dmub_rb_empty(rb)) 4932 return false; 4933 4934 *cmd = (union dmub_rb_cmd *)rb_cmd; 4935 4936 return true; 4937 } 4938 4939 /** 4940 * @brief Returns the next unprocessed command in the outbox. 4941 * 4942 * @param rb DMUB outbox ringbuffer 4943 * @param cmd The outbox command to return 4944 * @return true if not empty 4945 * @return false otherwise 4946 */ 4947 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 4948 union dmub_rb_out_cmd *cmd) 4949 { 4950 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 4951 uint64_t *dst = (uint64_t *)cmd; 4952 uint8_t i; 4953 4954 if (dmub_rb_empty(rb)) 4955 return false; 4956 4957 // copying data 4958 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4959 *dst++ = *src++; 4960 4961 return true; 4962 } 4963 4964 /** 4965 * @brief Removes the front entry in the ringbuffer. 4966 * 4967 * @param rb DMUB ringbuffer 4968 * @return true if the command was removed 4969 * @return false if there were no commands 4970 */ 4971 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 4972 { 4973 if (dmub_rb_empty(rb)) 4974 return false; 4975 4976 rb->rptr += DMUB_RB_CMD_SIZE; 4977 4978 if (rb->rptr >= rb->capacity) 4979 rb->rptr %= rb->capacity; 4980 4981 return true; 4982 } 4983 4984 /** 4985 * @brief Flushes commands in the ringbuffer to framebuffer memory. 4986 * 4987 * Avoids a race condition where DMCUB accesses memory while 4988 * there are still writes in flight to framebuffer. 4989 * 4990 * @param rb DMUB ringbuffer 4991 */ 4992 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 4993 { 4994 uint32_t rptr = rb->rptr; 4995 uint32_t wptr = rb->wrpt; 4996 4997 while (rptr != wptr) { 4998 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 4999 uint8_t i; 5000 5001 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5002 (void)READ_ONCE(*data++); 5003 5004 rptr += DMUB_RB_CMD_SIZE; 5005 if (rptr >= rb->capacity) 5006 rptr %= rb->capacity; 5007 } 5008 } 5009 5010 /** 5011 * @brief Initializes a DMCUB ringbuffer 5012 * 5013 * @param rb DMUB ringbuffer 5014 * @param init_params initial configuration for the ringbuffer 5015 */ 5016 static inline void dmub_rb_init(struct dmub_rb *rb, 5017 struct dmub_rb_init_params *init_params) 5018 { 5019 rb->base_address = init_params->base_address; 5020 rb->capacity = init_params->capacity; 5021 rb->rptr = init_params->read_ptr; 5022 rb->wrpt = init_params->write_ptr; 5023 } 5024 5025 /** 5026 * @brief Copies output data from in/out commands into the given command. 5027 * 5028 * @param rb DMUB ringbuffer 5029 * @param cmd Command to copy data into 5030 */ 5031 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 5032 union dmub_rb_cmd *cmd) 5033 { 5034 // Copy rb entry back into command 5035 uint8_t *rd_ptr = (rb->rptr == 0) ? 5036 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 5037 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 5038 5039 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 5040 } 5041 5042 #if defined(__cplusplus) 5043 } 5044 #endif 5045 5046 //============================================================================== 5047 //</DMUB_RB>==================================================================== 5048 //============================================================================== 5049 #endif /* _DMUB_CMD_H_ */ 5050