1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_SRV_H_ 27 #define _DMUB_SRV_H_ 28 29 /** 30 * DOC: DMUB interface and operation 31 * 32 * DMUB is the interface to the display DMCUB microcontroller on DCN hardware. 33 * It delegates hardware initialization and command submission to the 34 * microcontroller. DMUB is the shortname for DMCUB. 35 * 36 * This interface is not thread-safe. Ensure that all access to the interface 37 * is properly synchronized by the caller. 38 * 39 * Initialization and usage of the DMUB service should be done in the 40 * steps given below: 41 * 42 * 1. dmub_srv_create() 43 * 2. dmub_srv_has_hw_support() 44 * 3. dmub_srv_calc_region_info() 45 * 4. dmub_srv_hw_init() 46 * 47 * The call to dmub_srv_create() is required to use the server. 48 * 49 * The calls to dmub_srv_has_hw_support() and dmub_srv_calc_region_info() 50 * are helpers to query cache window size and allocate framebuffer(s) 51 * for the cache windows. 52 * 53 * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare 54 * for command submission. Commands can be queued via dmub_srv_fb_cmd_queue() 55 * and executed via dmub_srv_fb_cmd_execute(). 56 * 57 * If the queue is full the dmub_srv_wait_for_idle() call can be used to 58 * wait until the queue has been cleared. 59 * 60 * Destroying the DMUB service can be done by calling dmub_srv_destroy(). 61 * This does not clear DMUB hardware state, only software state. 62 * 63 * The interface is intended to be standalone and should not depend on any 64 * other component within DAL. 65 */ 66 67 #include "inc/dmub_cmd.h" 68 #include "dc/dc_types.h" 69 70 #define DMUB_PC_SNAPSHOT_COUNT 10 71 72 /* Default tracebuffer size if meta is absent. */ 73 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 74 75 /* Forward declarations */ 76 struct dmub_srv; 77 struct dmub_srv_common_regs; 78 struct dmub_srv_dcn31_regs; 79 80 struct dmcub_trace_buf_entry; 81 82 /* enum dmub_window_memory_type - memory location type specification for windows */ 83 enum dmub_window_memory_type { 84 DMUB_WINDOW_MEMORY_TYPE_FB = 0, 85 DMUB_WINDOW_MEMORY_TYPE_GART 86 }; 87 88 /* enum dmub_status - return code for dmcub functions */ 89 enum dmub_status { 90 DMUB_STATUS_OK = 0, 91 DMUB_STATUS_NO_CTX, 92 DMUB_STATUS_QUEUE_FULL, 93 DMUB_STATUS_TIMEOUT, 94 DMUB_STATUS_INVALID, 95 DMUB_STATUS_HW_FAILURE, 96 DMUB_STATUS_POWER_STATE_D3 97 }; 98 99 /* enum dmub_asic - dmub asic identifier */ 100 enum dmub_asic { 101 DMUB_ASIC_NONE = 0, 102 DMUB_ASIC_DCN20, 103 DMUB_ASIC_DCN21, 104 DMUB_ASIC_DCN30, 105 DMUB_ASIC_DCN301, 106 DMUB_ASIC_DCN302, 107 DMUB_ASIC_DCN303, 108 DMUB_ASIC_DCN31, 109 DMUB_ASIC_DCN31B, 110 DMUB_ASIC_DCN314, 111 DMUB_ASIC_DCN315, 112 DMUB_ASIC_DCN316, 113 DMUB_ASIC_DCN32, 114 DMUB_ASIC_DCN321, 115 DMUB_ASIC_DCN35, 116 DMUB_ASIC_DCN351, 117 DMUB_ASIC_DCN36, 118 DMUB_ASIC_DCN401, 119 DMUB_ASIC_MAX, 120 }; 121 122 /* enum dmub_window_id - dmub window identifier */ 123 enum dmub_window_id { 124 DMUB_WINDOW_0_INST_CONST = 0, 125 DMUB_WINDOW_1_STACK, 126 DMUB_WINDOW_2_BSS_DATA, 127 DMUB_WINDOW_3_VBIOS, 128 DMUB_WINDOW_4_MAILBOX, 129 DMUB_WINDOW_5_TRACEBUFF, 130 DMUB_WINDOW_6_FW_STATE, 131 DMUB_WINDOW_7_SCRATCH_MEM, 132 DMUB_WINDOW_IB_MEM, 133 DMUB_WINDOW_SHARED_STATE, 134 DMUB_WINDOW_TOTAL, 135 }; 136 137 /* enum dmub_notification_type - dmub outbox notification identifier */ 138 enum dmub_notification_type { 139 DMUB_NOTIFICATION_NO_DATA = 0, 140 DMUB_NOTIFICATION_AUX_REPLY, 141 DMUB_NOTIFICATION_HPD, 142 DMUB_NOTIFICATION_HPD_IRQ, 143 DMUB_NOTIFICATION_SET_CONFIG_REPLY, 144 DMUB_NOTIFICATION_DPIA_NOTIFICATION, 145 DMUB_NOTIFICATION_HPD_SENSE_NOTIFY, 146 DMUB_NOTIFICATION_FUSED_IO, 147 DMUB_NOTIFICATION_MAX 148 }; 149 150 /** 151 * DPIA NOTIFICATION Response Type 152 */ 153 enum dpia_notify_bw_alloc_status { 154 155 DPIA_BW_REQ_FAILED = 0, 156 DPIA_BW_REQ_SUCCESS, 157 DPIA_EST_BW_CHANGED, 158 DPIA_BW_ALLOC_CAPS_CHANGED 159 }; 160 161 /* enum dmub_memory_access_type - memory access method */ 162 enum dmub_memory_access_type { 163 DMUB_MEMORY_ACCESS_DEFAULT, 164 DMUB_MEMORY_ACCESS_CPU = DMUB_MEMORY_ACCESS_DEFAULT, 165 DMUB_MEMORY_ACCESS_DMA 166 }; 167 168 /* enum dmub_power_state type - to track DC power state in dmub_srv */ 169 enum dmub_srv_power_state_type { 170 DMUB_POWER_STATE_UNDEFINED = 0, 171 DMUB_POWER_STATE_D0 = 1, 172 DMUB_POWER_STATE_D3 = 8 173 }; 174 175 /* enum dmub_inbox_cmd_interface type - defines default interface for host->dmub commands */ 176 enum dmub_inbox_cmd_interface_type { 177 DMUB_CMD_INTERFACE_DEFAULT = 0, 178 DMUB_CMD_INTERFACE_FB = 1, 179 DMUB_CMD_INTERFACE_REG = 2, 180 }; 181 182 /** 183 * struct dmub_region - dmub hw memory region 184 * @base: base address for region, must be 256 byte aligned 185 * @top: top address for region 186 */ 187 struct dmub_region { 188 uint32_t base; 189 uint32_t top; 190 }; 191 192 /** 193 * struct dmub_window - dmub hw cache window 194 * @off: offset to the fb memory in gpu address space 195 * @r: region in uc address space for cache window 196 */ 197 struct dmub_window { 198 union dmub_addr offset; 199 struct dmub_region region; 200 }; 201 202 /** 203 * struct dmub_fb - defines a dmub framebuffer memory region 204 * @cpu_addr: cpu virtual address for the region, NULL if invalid 205 * @gpu_addr: gpu virtual address for the region, NULL if invalid 206 * @size: size of the region in bytes, zero if invalid 207 */ 208 struct dmub_fb { 209 void *cpu_addr; 210 uint64_t gpu_addr; 211 uint32_t size; 212 }; 213 214 /** 215 * struct dmub_srv_region_params - params used for calculating dmub regions 216 * @inst_const_size: size of the fw inst const section 217 * @bss_data_size: size of the fw bss data section 218 * @vbios_size: size of the vbios data 219 * @fw_bss_data: raw firmware bss data section 220 */ 221 struct dmub_srv_region_params { 222 uint32_t inst_const_size; 223 uint32_t bss_data_size; 224 uint32_t vbios_size; 225 const uint8_t *fw_inst_const; 226 const uint8_t *fw_bss_data; 227 const enum dmub_window_memory_type *window_memory_type; 228 }; 229 230 /** 231 * struct dmub_srv_region_info - output region info from the dmub service 232 * @fb_size: required minimum fb size for all regions, aligned to 4096 bytes 233 * @num_regions: number of regions used by the dmub service 234 * @regions: region info 235 * 236 * The regions are aligned such that they can be all placed within the 237 * same framebuffer but they can also be placed into different framebuffers. 238 * 239 * The size of each region can be calculated by the caller: 240 * size = reg.top - reg.base 241 * 242 * Care must be taken when performing custom allocations to ensure that each 243 * region base address is 256 byte aligned. 244 */ 245 struct dmub_srv_region_info { 246 uint32_t fb_size; 247 uint32_t gart_size; 248 uint8_t num_regions; 249 struct dmub_region regions[DMUB_WINDOW_TOTAL]; 250 }; 251 252 /** 253 * struct dmub_srv_memory_params - parameters used for driver fb setup 254 * @region_info: region info calculated by dmub service 255 * @cpu_fb_addr: base cpu address for the framebuffer 256 * @cpu_inbox_addr: base cpu address for the gart 257 * @gpu_fb_addr: base gpu virtual address for the framebuffer 258 * @gpu_inbox_addr: base gpu virtual address for the gart 259 */ 260 struct dmub_srv_memory_params { 261 const struct dmub_srv_region_info *region_info; 262 void *cpu_fb_addr; 263 void *cpu_gart_addr; 264 uint64_t gpu_fb_addr; 265 uint64_t gpu_gart_addr; 266 const enum dmub_window_memory_type *window_memory_type; 267 }; 268 269 /** 270 * struct dmub_srv_fb_info - output fb info from the dmub service 271 * @num_fbs: number of required dmub framebuffers 272 * @fbs: fb data for each region 273 * 274 * Output from the dmub service helper that can be used by the 275 * driver to prepare dmub_fb that can be passed into the dmub 276 * hw init service. 277 * 278 * Assumes that all regions are within the same framebuffer 279 * and have been setup according to the region_info generated 280 * by the dmub service. 281 */ 282 struct dmub_srv_fb_info { 283 uint8_t num_fb; 284 struct dmub_fb fb[DMUB_WINDOW_TOTAL]; 285 }; 286 287 /* 288 * struct dmub_srv_hw_params - params for dmub hardware initialization 289 * @fb: framebuffer info for each region 290 * @fb_base: base of the framebuffer aperture 291 * @fb_offset: offset of the framebuffer aperture 292 * @psp_version: psp version to pass for DMCU init 293 * @load_inst_const: true if DMUB should load inst const fw 294 */ 295 struct dmub_srv_hw_params { 296 struct dmub_fb *fb[DMUB_WINDOW_TOTAL]; 297 uint64_t fb_base; 298 uint64_t fb_offset; 299 uint32_t psp_version; 300 bool load_inst_const; 301 bool skip_panel_power_sequence; 302 bool disable_z10; 303 bool power_optimization; 304 bool dpia_supported; 305 bool disable_dpia; 306 bool usb4_cm_version; 307 bool fw_in_system_memory; 308 bool dpia_hpd_int_enable_supported; 309 bool disable_clock_gate; 310 bool disallow_dispclk_dppclk_ds; 311 bool ips_sequential_ono; 312 enum dmub_memory_access_type mem_access_type; 313 enum dmub_ips_disable_type disable_ips; 314 bool disallow_phy_access; 315 bool disable_sldo_opt; 316 bool enable_non_transparent_setconfig; 317 bool lower_hbr3_phy_ssc; 318 }; 319 320 /** 321 * struct dmub_srv_debug - Debug info for dmub_srv 322 * @timeout_occured: Indicates a timeout occured on any message from driver to dmub 323 * @timeout_cmd: first cmd sent from driver that timed out - subsequent timeouts are not stored 324 */ 325 struct dmub_timeout_info { 326 bool timeout_occured; 327 union dmub_rb_cmd timeout_cmd; 328 unsigned long long timestamp; 329 }; 330 331 /** 332 * struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for 333 * debugging purposes, including logging, crash analysis, etc. 334 */ 335 struct dmub_diagnostic_data { 336 uint32_t dmcub_version; 337 uint32_t scratch[17]; 338 uint32_t pc[DMUB_PC_SNAPSHOT_COUNT]; 339 uint32_t undefined_address_fault_addr; 340 uint32_t inst_fetch_fault_addr; 341 uint32_t data_write_fault_addr; 342 uint32_t inbox1_rptr; 343 uint32_t inbox1_wptr; 344 uint32_t inbox1_size; 345 uint32_t inbox0_rptr; 346 uint32_t inbox0_wptr; 347 uint32_t inbox0_size; 348 uint32_t outbox1_rptr; 349 uint32_t outbox1_wptr; 350 uint32_t outbox1_size; 351 uint32_t gpint_datain0; 352 struct dmub_timeout_info timeout_info; 353 uint8_t is_dmcub_enabled : 1; 354 uint8_t is_dmcub_soft_reset : 1; 355 uint8_t is_dmcub_secure_reset : 1; 356 uint8_t is_traceport_en : 1; 357 uint8_t is_cw0_enabled : 1; 358 uint8_t is_cw6_enabled : 1; 359 }; 360 361 struct dmub_srv_inbox { 362 /* generic status */ 363 uint64_t num_submitted; 364 uint64_t num_reported; 365 union { 366 /* frame buffer mailbox status */ 367 struct dmub_rb rb; 368 /* register mailbox status */ 369 struct { 370 bool is_pending; 371 bool is_multi_pending; 372 }; 373 }; 374 }; 375 376 /** 377 * struct dmub_srv_base_funcs - Driver specific base callbacks 378 */ 379 struct dmub_srv_base_funcs { 380 /** 381 * @reg_read: 382 * 383 * Hook for reading a register. 384 * 385 * Return: The 32-bit register value from the given address. 386 */ 387 uint32_t (*reg_read)(void *ctx, uint32_t address); 388 389 /** 390 * @reg_write: 391 * 392 * Hook for writing a value to the register specified by address. 393 */ 394 void (*reg_write)(void *ctx, uint32_t address, uint32_t value); 395 }; 396 397 /** 398 * struct dmub_srv_hw_funcs - hardware sequencer funcs for dmub 399 */ 400 struct dmub_srv_hw_funcs { 401 /* private: internal use only */ 402 403 void (*init)(struct dmub_srv *dmub); 404 405 void (*reset)(struct dmub_srv *dmub); 406 407 void (*reset_release)(struct dmub_srv *dmub); 408 409 void (*backdoor_load)(struct dmub_srv *dmub, 410 const struct dmub_window *cw0, 411 const struct dmub_window *cw1); 412 413 void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub, 414 const struct dmub_window *cw0, 415 const struct dmub_window *cw1); 416 void (*setup_windows)(struct dmub_srv *dmub, 417 const struct dmub_window *cw2, 418 const struct dmub_window *cw3, 419 const struct dmub_window *cw4, 420 const struct dmub_window *cw5, 421 const struct dmub_window *cw6, 422 const struct dmub_window *region6); 423 424 void (*setup_mailbox)(struct dmub_srv *dmub, 425 const struct dmub_region *inbox1); 426 427 uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub); 428 429 uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub); 430 431 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 432 433 void (*setup_out_mailbox)(struct dmub_srv *dmub, 434 const struct dmub_region *outbox1); 435 436 uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub); 437 438 void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 439 440 void (*setup_outbox0)(struct dmub_srv *dmub, 441 const struct dmub_region *outbox0); 442 443 uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub); 444 445 void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 446 447 uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub); 448 449 uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub); 450 451 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 452 453 bool (*is_supported)(struct dmub_srv *dmub); 454 455 bool (*is_psrsu_supported)(struct dmub_srv *dmub); 456 457 bool (*is_hw_init)(struct dmub_srv *dmub); 458 bool (*is_hw_powered_up)(struct dmub_srv *dmub); 459 460 void (*enable_dmub_boot_options)(struct dmub_srv *dmub, 461 const struct dmub_srv_hw_params *params); 462 463 void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip); 464 465 union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub); 466 467 union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub); 468 469 void (*set_gpint)(struct dmub_srv *dmub, 470 union dmub_gpint_data_register reg); 471 472 bool (*is_gpint_acked)(struct dmub_srv *dmub, 473 union dmub_gpint_data_register reg); 474 475 uint32_t (*get_gpint_response)(struct dmub_srv *dmub); 476 477 uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub); 478 479 void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub); 480 void (*clear_inbox0_ack_register)(struct dmub_srv *dmub); 481 uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub); 482 void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 483 uint32_t (*get_current_time)(struct dmub_srv *dmub); 484 485 void (*get_diagnostic_data)(struct dmub_srv *dmub); 486 487 bool (*should_detect)(struct dmub_srv *dmub); 488 void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx); 489 490 void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 491 492 void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub, 493 union dmub_rb_cmd *cmd); 494 uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub); 495 void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub, 496 union dmub_rb_cmd *cmd); 497 void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 498 void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 499 void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable); 500 501 uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub); 502 void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub); 503 void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg); 504 void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp); 505 uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub); 506 void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable); 507 }; 508 509 /** 510 * struct dmub_srv_create_params - params for dmub service creation 511 * @base_funcs: driver supplied base routines 512 * @hw_funcs: optional overrides for hw funcs 513 * @user_ctx: context data for callback funcs 514 * @asic: driver supplied asic 515 * @fw_version: the current firmware version, if any 516 * @is_virtual: false for hw support only 517 */ 518 struct dmub_srv_create_params { 519 struct dmub_srv_base_funcs funcs; 520 struct dmub_srv_hw_funcs *hw_funcs; 521 void *user_ctx; 522 enum dmub_asic asic; 523 uint32_t fw_version; 524 bool is_virtual; 525 enum dmub_inbox_cmd_interface_type inbox_type; 526 }; 527 528 /** 529 * struct dmub_srv - software state for dmcub 530 * @asic: dmub asic identifier 531 * @user_ctx: user provided context for the dmub_srv 532 * @fw_version: the current firmware version, if any 533 * @is_virtual: false if hardware support only 534 * @shared_state: dmub shared state between firmware and driver 535 * @fw_state: dmub firmware state pointer 536 */ 537 struct dmub_srv { 538 enum dmub_asic asic; 539 void *user_ctx; 540 uint32_t fw_version; 541 bool is_virtual; 542 struct dmub_fb scratch_mem_fb; 543 struct dmub_fb ib_mem_gart; 544 volatile struct dmub_shared_state_feature_block *shared_state; 545 volatile const struct dmub_fw_state *fw_state; 546 547 /* private: internal use only */ 548 const struct dmub_srv_common_regs *regs; 549 const struct dmub_srv_dcn31_regs *regs_dcn31; 550 struct dmub_srv_dcn32_regs *regs_dcn32; 551 struct dmub_srv_dcn35_regs *regs_dcn35; 552 const struct dmub_srv_dcn401_regs *regs_dcn401; 553 struct dmub_srv_base_funcs funcs; 554 struct dmub_srv_hw_funcs hw_funcs; 555 struct dmub_srv_inbox inbox1; 556 uint32_t inbox1_last_wptr; 557 struct dmub_srv_inbox reg_inbox0; 558 /** 559 * outbox1_rb is accessed without locks (dal & dc) 560 * and to be used only in dmub_srv_stat_get_notification() 561 */ 562 struct dmub_rb outbox1_rb; 563 564 struct dmub_rb outbox0_rb; 565 566 bool sw_init; 567 bool hw_init; 568 569 uint64_t fb_base; 570 uint64_t fb_offset; 571 uint32_t psp_version; 572 573 /* Feature capabilities reported by fw */ 574 struct dmub_fw_meta_info meta_info; 575 struct dmub_feature_caps feature_caps; 576 struct dmub_visual_confirm_color visual_confirm_color; 577 enum dmub_inbox_cmd_interface_type inbox_type; 578 579 enum dmub_srv_power_state_type power_state; 580 struct dmub_diagnostic_data debug; 581 }; 582 583 /** 584 * struct dmub_notification - dmub notification data 585 * @type: dmub notification type 586 * @link_index: link index to identify aux connection 587 * @result: USB4 status returned from dmub 588 * @pending_notification: Indicates there are other pending notifications 589 * @aux_reply: aux reply 590 * @hpd_status: hpd status 591 * @bw_alloc_reply: BW Allocation reply from CM/DPIA 592 */ 593 struct dmub_notification { 594 enum dmub_notification_type type; 595 uint8_t link_index; 596 uint8_t result; 597 bool pending_notification; 598 union { 599 struct aux_reply_data aux_reply; 600 enum dp_hpd_status hpd_status; 601 enum set_config_status sc_status; 602 struct dmub_rb_cmd_hpd_sense_notify_data hpd_sense_notify; 603 struct dmub_cmd_fused_request fused_request; 604 }; 605 }; 606 607 /* enum dmub_ips_mode - IPS mode identifier */ 608 enum dmub_ips_mode { 609 DMUB_IPS_MODE_IPS1_MAX = 0, 610 DMUB_IPS_MODE_IPS2, 611 DMUB_IPS_MODE_IPS1_RCG, 612 DMUB_IPS_MODE_IPS1_ONO2_ON 613 }; 614 615 /** 616 * DMUB firmware version helper macro - useful for checking if the version 617 * of a firmware to know if feature or functionality is supported or present. 618 */ 619 #define DMUB_FW_VERSION(major, minor, revision) \ 620 ((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | (((revision) & 0xFF) << 8)) 621 622 /** 623 * dmub_srv_create() - creates the DMUB service. 624 * @dmub: the dmub service 625 * @params: creation parameters for the service 626 * 627 * Return: 628 * DMUB_STATUS_OK - success 629 * DMUB_STATUS_INVALID - unspecified error 630 */ 631 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 632 const struct dmub_srv_create_params *params); 633 634 /** 635 * dmub_srv_destroy() - destroys the DMUB service. 636 * @dmub: the dmub service 637 */ 638 void dmub_srv_destroy(struct dmub_srv *dmub); 639 640 /** 641 * dmub_srv_calc_region_info() - retreives region info from the dmub service 642 * @dmub: the dmub service 643 * @params: parameters used to calculate region locations 644 * @info_out: the output region info from dmub 645 * 646 * Calculates the base and top address for all relevant dmub regions 647 * using the parameters given (if any). 648 * 649 * Return: 650 * DMUB_STATUS_OK - success 651 * DMUB_STATUS_INVALID - unspecified error 652 */ 653 enum dmub_status 654 dmub_srv_calc_region_info(struct dmub_srv *dmub, 655 const struct dmub_srv_region_params *params, 656 struct dmub_srv_region_info *out); 657 658 /** 659 * dmub_srv_calc_region_info() - retreives fb info from the dmub service 660 * @dmub: the dmub service 661 * @params: parameters used to calculate fb locations 662 * @info_out: the output fb info from dmub 663 * 664 * Calculates the base and top address for all relevant dmub regions 665 * using the parameters given (if any). 666 * 667 * Return: 668 * DMUB_STATUS_OK - success 669 * DMUB_STATUS_INVALID - unspecified error 670 */ 671 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 672 const struct dmub_srv_memory_params *params, 673 struct dmub_srv_fb_info *out); 674 675 /** 676 * dmub_srv_has_hw_support() - returns hw support state for dmcub 677 * @dmub: the dmub service 678 * @is_supported: hw support state 679 * 680 * Queries the hardware for DMCUB support and returns the result. 681 * 682 * Can be called before dmub_srv_hw_init(). 683 * 684 * Return: 685 * DMUB_STATUS_OK - success 686 * DMUB_STATUS_INVALID - unspecified error 687 */ 688 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 689 bool *is_supported); 690 691 /** 692 * dmub_srv_is_hw_init() - returns hardware init state 693 * 694 * Return: 695 * DMUB_STATUS_OK - success 696 * DMUB_STATUS_INVALID - unspecified error 697 */ 698 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init); 699 700 /** 701 * dmub_srv_hw_init() - initializes the underlying DMUB hardware 702 * @dmub: the dmub service 703 * @params: params for hardware initialization 704 * 705 * Resets the DMUB hardware and performs backdoor loading of the 706 * required cache regions based on the input framebuffer regions. 707 * 708 * Return: 709 * DMUB_STATUS_OK - success 710 * DMUB_STATUS_NO_CTX - dmcub context not initialized 711 * DMUB_STATUS_INVALID - unspecified error 712 */ 713 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 714 const struct dmub_srv_hw_params *params); 715 716 /** 717 * dmub_srv_hw_reset() - puts the DMUB hardware in reset state if initialized 718 * @dmub: the dmub service 719 * 720 * Before destroying the DMUB service or releasing the backing framebuffer 721 * memory we'll need to put the DMCUB into reset first. 722 * 723 * A subsequent call to dmub_srv_hw_init() will re-enable the DMCUB. 724 * 725 * Return: 726 * DMUB_STATUS_OK - success 727 * DMUB_STATUS_INVALID - unspecified error 728 */ 729 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub); 730 731 /** 732 * dmub_srv_fb_cmd_queue() - queues a command to the DMUB 733 * @dmub: the dmub service 734 * @cmd: the command to queue 735 * 736 * Queues a command to the DMUB service but does not begin execution 737 * immediately. 738 * 739 * Return: 740 * DMUB_STATUS_OK - success 741 * DMUB_STATUS_QUEUE_FULL - no remaining room in queue 742 * DMUB_STATUS_INVALID - unspecified error 743 */ 744 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 745 const union dmub_rb_cmd *cmd); 746 747 /** 748 * dmub_srv_fb_cmd_execute() - Executes a queued sequence to the dmub 749 * @dmub: the dmub service 750 * 751 * Begins execution of queued commands on the dmub. 752 * 753 * Return: 754 * DMUB_STATUS_OK - success 755 * DMUB_STATUS_INVALID - unspecified error 756 */ 757 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub); 758 759 /** 760 * dmub_srv_wait_for_hw_pwr_up() - Waits for firmware hardware power up is completed 761 * @dmub: the dmub service 762 * @timeout_us: the maximum number of microseconds to wait 763 * 764 * Waits until firmware hardware is powered up. The maximum 765 * wait time is given in microseconds to prevent spinning forever. 766 * 767 * Return: 768 * DMUB_STATUS_OK - success 769 * DMUB_STATUS_TIMEOUT - timed out 770 * DMUB_STATUS_INVALID - unspecified error 771 */ 772 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 773 uint32_t timeout_us); 774 775 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub); 776 777 /** 778 * dmub_srv_wait_for_auto_load() - Waits for firmware auto load to complete 779 * @dmub: the dmub service 780 * @timeout_us: the maximum number of microseconds to wait 781 * 782 * Waits until firmware has been autoloaded by the DMCUB. The maximum 783 * wait time is given in microseconds to prevent spinning forever. 784 * 785 * On ASICs without firmware autoload support this function will return 786 * immediately. 787 * 788 * Return: 789 * DMUB_STATUS_OK - success 790 * DMUB_STATUS_TIMEOUT - wait for phy init timed out 791 * DMUB_STATUS_INVALID - unspecified error 792 */ 793 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 794 uint32_t timeout_us); 795 796 /** 797 * dmub_srv_wait_for_phy_init() - Waits for DMUB PHY init to complete 798 * @dmub: the dmub service 799 * @timeout_us: the maximum number of microseconds to wait 800 * 801 * Waits until the PHY has been initialized by the DMUB. The maximum 802 * wait time is given in microseconds to prevent spinning forever. 803 * 804 * On ASICs without PHY init support this function will return 805 * immediately. 806 * 807 * Return: 808 * DMUB_STATUS_OK - success 809 * DMUB_STATUS_TIMEOUT - wait for phy init timed out 810 * DMUB_STATUS_INVALID - unspecified error 811 */ 812 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 813 uint32_t timeout_us); 814 815 /** 816 * dmub_srv_wait_for_pending() - Re-entrant wait for messages currently pending 817 * @dmub: the dmub service 818 * @timeout_us: the maximum number of microseconds to wait 819 * 820 * Waits until the commands queued prior to this call are complete. 821 * If interfaces remain busy due to additional work being submitted 822 * concurrently, this function will not continue to wait. 823 * 824 * Return: 825 * DMUB_STATUS_OK - success 826 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 827 * DMUB_STATUS_INVALID - unspecified error 828 */ 829 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 830 uint32_t timeout_us); 831 832 /** 833 * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle 834 * @dmub: the dmub service 835 * @timeout_us: the maximum number of microseconds to wait 836 * 837 * Waits until the DMUB buffer is empty and all commands have 838 * finished processing. The maximum wait time is given in 839 * microseconds to prevent spinning forever. 840 * 841 * Return: 842 * DMUB_STATUS_OK - success 843 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 844 * DMUB_STATUS_INVALID - unspecified error 845 */ 846 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 847 uint32_t timeout_us); 848 849 /** 850 * dmub_srv_send_gpint_command() - Sends a GPINT based command. 851 * @dmub: the dmub service 852 * @command_code: the command code to send 853 * @param: the command parameter to send 854 * @timeout_us: the maximum number of microseconds to wait 855 * 856 * Sends a command via the general purpose interrupt (GPINT). 857 * Waits for the number of microseconds specified by timeout_us 858 * for the command ACK before returning. 859 * 860 * Can be called after software initialization. 861 * 862 * Return: 863 * DMUB_STATUS_OK - success 864 * DMUB_STATUS_TIMEOUT - wait for ACK timed out 865 * DMUB_STATUS_INVALID - unspecified error 866 */ 867 enum dmub_status 868 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 869 enum dmub_gpint_command command_code, 870 uint16_t param, uint32_t timeout_us); 871 872 /** 873 * dmub_srv_get_gpint_response() - Queries the GPINT response. 874 * @dmub: the dmub service 875 * @response: the response for the last GPINT 876 * 877 * Returns the response code for the last GPINT interrupt. 878 * 879 * Can be called after software initialization. 880 * 881 * Return: 882 * DMUB_STATUS_OK - success 883 * DMUB_STATUS_INVALID - unspecified error 884 */ 885 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 886 uint32_t *response); 887 888 /** 889 * dmub_srv_get_gpint_dataout() - Queries the GPINT DATAOUT. 890 * @dmub: the dmub service 891 * @dataout: the data for the GPINT DATAOUT 892 * 893 * Returns the response code for the last GPINT DATAOUT interrupt. 894 * 895 * Can be called after software initialization. 896 * 897 * Return: 898 * DMUB_STATUS_OK - success 899 * DMUB_STATUS_INVALID - unspecified error 900 */ 901 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 902 uint32_t *dataout); 903 904 /** 905 * dmub_flush_buffer_mem() - Read back entire frame buffer region. 906 * This ensures that the write from x86 has been flushed and will not 907 * hang the DMCUB. 908 * @fb: frame buffer to flush 909 * 910 * Can be called after software initialization. 911 */ 912 void dmub_flush_buffer_mem(const struct dmub_fb *fb); 913 914 /** 915 * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits. 916 * 917 * @dmub: the dmub service 918 * @status: out pointer for firmware status 919 * 920 * Return: 921 * DMUB_STATUS_OK - success 922 * DMUB_STATUS_INVALID - unspecified error, unsupported 923 */ 924 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 925 union dmub_fw_boot_status *status); 926 927 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 928 union dmub_fw_boot_options *option); 929 930 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 931 bool skip); 932 933 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry); 934 935 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub); 936 937 bool dmub_srv_should_detect(struct dmub_srv *dmub); 938 939 /** 940 * dmub_srv_send_inbox0_cmd() - Send command to DMUB using INBOX0 941 * @dmub: the dmub service 942 * @data: the data to be sent in the INBOX0 command 943 * 944 * Send command by writing directly to INBOX0 WPTR 945 * 946 * Return: 947 * DMUB_STATUS_OK - success 948 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 949 */ 950 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 951 952 /** 953 * dmub_srv_wait_for_inbox0_ack() - wait for DMUB to ACK INBOX0 command 954 * @dmub: the dmub service 955 * @timeout_us: the maximum number of microseconds to wait 956 * 957 * Wait for DMUB to ACK the INBOX0 message 958 * 959 * Return: 960 * DMUB_STATUS_OK - success 961 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 962 * DMUB_STATUS_TIMEOUT - wait for ack timed out 963 */ 964 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us); 965 966 /** 967 * dmub_srv_wait_for_inbox0_ack() - clear ACK register for INBOX0 968 * @dmub: the dmub service 969 * 970 * Clear ACK register for INBOX0 971 * 972 * Return: 973 * DMUB_STATUS_OK - success 974 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 975 */ 976 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub); 977 978 /** 979 * dmub_srv_subvp_save_surf_addr() - Save primary and meta address for subvp on each flip 980 * @dmub: The dmub service 981 * @addr: The surface address to be programmed on the current flip 982 * @subvp_index: Index of subvp pipe, indicates which subvp pipe the address should be saved for 983 * 984 * Function to save the surface flip addr into scratch registers. This is to fix a race condition 985 * between FW and driver reading / writing to the surface address at the same time. This is 986 * required because there is no EARLIEST_IN_USE_META. 987 * 988 * Return: 989 * void 990 */ 991 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 992 993 /** 994 * dmub_srv_set_power_state() - Track DC power state in dmub_srv 995 * @dmub: The dmub service 996 * @power_state: DC power state setting 997 * 998 * Store DC power state in dmub_srv. If dmub_srv is in D3, then don't send messages to DMUB 999 * 1000 * Return: 1001 * void 1002 */ 1003 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state); 1004 1005 /** 1006 * dmub_srv_reg_cmd_execute() - Executes provided command to the dmub 1007 * @dmub: the dmub service 1008 * @cmd: the command packet to be executed 1009 * 1010 * Executes a single command for the dmub. 1011 * 1012 * Return: 1013 * DMUB_STATUS_OK - success 1014 * DMUB_STATUS_INVALID - unspecified error 1015 */ 1016 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 1017 1018 1019 /** 1020 * dmub_srv_cmd_get_response() - Copies return data for command into buffer 1021 * @dmub: the dmub service 1022 * @cmd_rsp: response buffer 1023 * 1024 * Copies return data for command into buffer 1025 */ 1026 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1027 union dmub_rb_cmd *cmd_rsp); 1028 1029 /** 1030 * dmub_srv_sync_inboxes() - Sync inbox state 1031 * @dmub: the dmub service 1032 * 1033 * Sync inbox state 1034 * 1035 * Return: 1036 * DMUB_STATUS_OK - success 1037 * DMUB_STATUS_INVALID - unspecified error 1038 */ 1039 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub); 1040 1041 /** 1042 * dmub_srv_wait_for_inbox_free() - Waits for space in the DMUB inbox to free up 1043 * @dmub: the dmub service 1044 * @timeout_us: the maximum number of microseconds to wait 1045 * @num_free_required: number of free entries required 1046 * 1047 * Waits until the DMUB buffer is freed to the specified number. 1048 * The maximum wait time is given in microseconds to prevent spinning 1049 * forever. 1050 * 1051 * Return: 1052 * DMUB_STATUS_OK - success 1053 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 1054 * DMUB_STATUS_INVALID - unspecified error 1055 */ 1056 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1057 uint32_t timeout_us, 1058 uint32_t num_free_required); 1059 1060 /** 1061 * dmub_srv_update_inbox_status() - Updates pending status for inbox & reg inbox0 1062 * @dmub: the dmub service 1063 * 1064 * Return: 1065 * DMUB_STATUS_OK - success 1066 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 1067 * DMUB_STATUS_HW_FAILURE - issue with HW programming 1068 * DMUB_STATUS_INVALID - unspecified error 1069 */ 1070 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub); 1071 1072 #endif /* _DMUB_SRV_H_ */ 1073