1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_SRV_H_ 27 #define _DMUB_SRV_H_ 28 29 /** 30 * DOC: DMUB interface and operation 31 * 32 * DMUB is the interface to the display DMCUB microcontroller on DCN hardware. 33 * It delegates hardware initialization and command submission to the 34 * microcontroller. DMUB is the shortname for DMCUB. 35 * 36 * This interface is not thread-safe. Ensure that all access to the interface 37 * is properly synchronized by the caller. 38 * 39 * Initialization and usage of the DMUB service should be done in the 40 * steps given below: 41 * 42 * 1. dmub_srv_create() 43 * 2. dmub_srv_has_hw_support() 44 * 3. dmub_srv_calc_region_info() 45 * 4. dmub_srv_hw_init() 46 * 47 * The call to dmub_srv_create() is required to use the server. 48 * 49 * The calls to dmub_srv_has_hw_support() and dmub_srv_calc_region_info() 50 * are helpers to query cache window size and allocate framebuffer(s) 51 * for the cache windows. 52 * 53 * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare 54 * for command submission. Commands can be queued via dmub_srv_fb_cmd_queue() 55 * and executed via dmub_srv_fb_cmd_execute(). 56 * 57 * If the queue is full the dmub_srv_wait_for_idle() call can be used to 58 * wait until the queue has been cleared. 59 * 60 * Destroying the DMUB service can be done by calling dmub_srv_destroy(). 61 * This does not clear DMUB hardware state, only software state. 62 * 63 * The interface is intended to be standalone and should not depend on any 64 * other component within DAL. 65 */ 66 67 #include "inc/dmub_cmd.h" 68 #include "dc/dc_types.h" 69 70 #define DMUB_PC_SNAPSHOT_COUNT 10 71 72 /* Default tracebuffer size if meta is absent. */ 73 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 74 75 /* Forward declarations */ 76 struct dmub_srv; 77 struct dmub_srv_common_regs; 78 struct dmub_srv_dcn31_regs; 79 80 struct dmcub_trace_buf_entry; 81 82 /* enum dmub_window_memory_type - memory location type specification for windows */ 83 enum dmub_window_memory_type { 84 DMUB_WINDOW_MEMORY_TYPE_FB = 0, 85 DMUB_WINDOW_MEMORY_TYPE_GART 86 }; 87 88 /* enum dmub_status - return code for dmcub functions */ 89 enum dmub_status { 90 DMUB_STATUS_OK = 0, 91 DMUB_STATUS_NO_CTX, 92 DMUB_STATUS_QUEUE_FULL, 93 DMUB_STATUS_TIMEOUT, 94 DMUB_STATUS_INVALID, 95 DMUB_STATUS_HW_FAILURE, 96 DMUB_STATUS_POWER_STATE_D3 97 }; 98 99 /* enum dmub_asic - dmub asic identifier */ 100 enum dmub_asic { 101 DMUB_ASIC_NONE = 0, 102 DMUB_ASIC_DCN20, 103 DMUB_ASIC_DCN21, 104 DMUB_ASIC_DCN30, 105 DMUB_ASIC_DCN301, 106 DMUB_ASIC_DCN302, 107 DMUB_ASIC_DCN303, 108 DMUB_ASIC_DCN31, 109 DMUB_ASIC_DCN31B, 110 DMUB_ASIC_DCN314, 111 DMUB_ASIC_DCN315, 112 DMUB_ASIC_DCN316, 113 DMUB_ASIC_DCN32, 114 DMUB_ASIC_DCN321, 115 DMUB_ASIC_DCN35, 116 DMUB_ASIC_DCN351, 117 DMUB_ASIC_DCN36, 118 DMUB_ASIC_DCN401, 119 DMUB_ASIC_MAX, 120 }; 121 122 /* enum dmub_window_id - dmub window identifier */ 123 enum dmub_window_id { 124 DMUB_WINDOW_0_INST_CONST = 0, 125 DMUB_WINDOW_1_STACK, 126 DMUB_WINDOW_2_BSS_DATA, 127 DMUB_WINDOW_3_VBIOS, 128 DMUB_WINDOW_4_MAILBOX, 129 DMUB_WINDOW_5_TRACEBUFF, 130 DMUB_WINDOW_6_FW_STATE, 131 DMUB_WINDOW_7_SCRATCH_MEM, 132 DMUB_WINDOW_IB_MEM, 133 DMUB_WINDOW_SHARED_STATE, 134 DMUB_WINDOW_LSDMA_BUFFER, 135 DMUB_WINDOW_TOTAL, 136 }; 137 138 /* enum dmub_notification_type - dmub outbox notification identifier */ 139 enum dmub_notification_type { 140 DMUB_NOTIFICATION_NO_DATA = 0, 141 DMUB_NOTIFICATION_AUX_REPLY, 142 DMUB_NOTIFICATION_HPD, 143 DMUB_NOTIFICATION_HPD_IRQ, 144 DMUB_NOTIFICATION_SET_CONFIG_REPLY, 145 DMUB_NOTIFICATION_DPIA_NOTIFICATION, 146 DMUB_NOTIFICATION_HPD_SENSE_NOTIFY, 147 DMUB_NOTIFICATION_FUSED_IO, 148 DMUB_NOTIFICATION_MAX 149 }; 150 151 /** 152 * DPIA NOTIFICATION Response Type 153 */ 154 enum dpia_notify_bw_alloc_status { 155 156 DPIA_BW_REQ_FAILED = 0, 157 DPIA_BW_REQ_SUCCESS, 158 DPIA_EST_BW_CHANGED, 159 DPIA_BW_ALLOC_CAPS_CHANGED 160 }; 161 162 /* enum dmub_memory_access_type - memory access method */ 163 enum dmub_memory_access_type { 164 DMUB_MEMORY_ACCESS_DEFAULT, 165 DMUB_MEMORY_ACCESS_CPU = DMUB_MEMORY_ACCESS_DEFAULT, 166 DMUB_MEMORY_ACCESS_DMA 167 }; 168 169 /* enum dmub_power_state type - to track DC power state in dmub_srv */ 170 enum dmub_srv_power_state_type { 171 DMUB_POWER_STATE_UNDEFINED = 0, 172 DMUB_POWER_STATE_D0 = 1, 173 DMUB_POWER_STATE_D3 = 8 174 }; 175 176 /* enum dmub_inbox_cmd_interface type - defines default interface for host->dmub commands */ 177 enum dmub_inbox_cmd_interface_type { 178 DMUB_CMD_INTERFACE_DEFAULT = 0, 179 DMUB_CMD_INTERFACE_FB = 1, 180 DMUB_CMD_INTERFACE_REG = 2, 181 }; 182 183 /** 184 * struct dmub_region - dmub hw memory region 185 * @base: base address for region, must be 256 byte aligned 186 * @top: top address for region 187 */ 188 struct dmub_region { 189 uint32_t base; 190 uint32_t top; 191 }; 192 193 /** 194 * struct dmub_window - dmub hw cache window 195 * @off: offset to the fb memory in gpu address space 196 * @r: region in uc address space for cache window 197 */ 198 struct dmub_window { 199 union dmub_addr offset; 200 struct dmub_region region; 201 }; 202 203 /** 204 * struct dmub_fb - defines a dmub framebuffer memory region 205 * @cpu_addr: cpu virtual address for the region, NULL if invalid 206 * @gpu_addr: gpu virtual address for the region, NULL if invalid 207 * @size: size of the region in bytes, zero if invalid 208 */ 209 struct dmub_fb { 210 void *cpu_addr; 211 uint64_t gpu_addr; 212 uint32_t size; 213 }; 214 215 /** 216 * struct dmub_srv_region_params - params used for calculating dmub regions 217 * @inst_const_size: size of the fw inst const section 218 * @bss_data_size: size of the fw bss data section 219 * @vbios_size: size of the vbios data 220 * @fw_bss_data: raw firmware bss data section 221 */ 222 struct dmub_srv_region_params { 223 uint32_t inst_const_size; 224 uint32_t bss_data_size; 225 uint32_t vbios_size; 226 const uint8_t *fw_inst_const; 227 const uint8_t *fw_bss_data; 228 const enum dmub_window_memory_type *window_memory_type; 229 }; 230 231 /** 232 * struct dmub_srv_region_info - output region info from the dmub service 233 * @fb_size: required minimum fb size for all regions, aligned to 4096 bytes 234 * @num_regions: number of regions used by the dmub service 235 * @regions: region info 236 * 237 * The regions are aligned such that they can be all placed within the 238 * same framebuffer but they can also be placed into different framebuffers. 239 * 240 * The size of each region can be calculated by the caller: 241 * size = reg.top - reg.base 242 * 243 * Care must be taken when performing custom allocations to ensure that each 244 * region base address is 256 byte aligned. 245 */ 246 struct dmub_srv_region_info { 247 uint32_t fb_size; 248 uint32_t gart_size; 249 uint8_t num_regions; 250 struct dmub_region regions[DMUB_WINDOW_TOTAL]; 251 }; 252 253 /** 254 * struct dmub_srv_memory_params - parameters used for driver fb setup 255 * @region_info: region info calculated by dmub service 256 * @cpu_fb_addr: base cpu address for the framebuffer 257 * @cpu_inbox_addr: base cpu address for the gart 258 * @gpu_fb_addr: base gpu virtual address for the framebuffer 259 * @gpu_inbox_addr: base gpu virtual address for the gart 260 */ 261 struct dmub_srv_memory_params { 262 const struct dmub_srv_region_info *region_info; 263 void *cpu_fb_addr; 264 void *cpu_gart_addr; 265 uint64_t gpu_fb_addr; 266 uint64_t gpu_gart_addr; 267 const enum dmub_window_memory_type *window_memory_type; 268 }; 269 270 /** 271 * struct dmub_srv_fb_info - output fb info from the dmub service 272 * @num_fbs: number of required dmub framebuffers 273 * @fbs: fb data for each region 274 * 275 * Output from the dmub service helper that can be used by the 276 * driver to prepare dmub_fb that can be passed into the dmub 277 * hw init service. 278 * 279 * Assumes that all regions are within the same framebuffer 280 * and have been setup according to the region_info generated 281 * by the dmub service. 282 */ 283 struct dmub_srv_fb_info { 284 uint8_t num_fb; 285 struct dmub_fb fb[DMUB_WINDOW_TOTAL]; 286 }; 287 288 /* 289 * struct dmub_srv_hw_params - params for dmub hardware initialization 290 * @fb: framebuffer info for each region 291 * @fb_base: base of the framebuffer aperture 292 * @fb_offset: offset of the framebuffer aperture 293 * @psp_version: psp version to pass for DMCU init 294 * @load_inst_const: true if DMUB should load inst const fw 295 */ 296 struct dmub_srv_hw_params { 297 struct dmub_fb *fb[DMUB_WINDOW_TOTAL]; 298 uint64_t fb_base; 299 uint64_t fb_offset; 300 uint32_t psp_version; 301 bool load_inst_const; 302 bool skip_panel_power_sequence; 303 bool disable_z10; 304 bool power_optimization; 305 bool dpia_supported; 306 bool disable_dpia; 307 bool usb4_cm_version; 308 bool fw_in_system_memory; 309 bool dpia_hpd_int_enable_supported; 310 bool disable_clock_gate; 311 bool disallow_dispclk_dppclk_ds; 312 bool ips_sequential_ono; 313 enum dmub_memory_access_type mem_access_type; 314 enum dmub_ips_disable_type disable_ips; 315 bool disallow_phy_access; 316 bool disable_sldo_opt; 317 bool enable_non_transparent_setconfig; 318 bool lower_hbr3_phy_ssc; 319 }; 320 321 /** 322 * struct dmub_srv_debug - Debug info for dmub_srv 323 * @timeout_occured: Indicates a timeout occured on any message from driver to dmub 324 * @timeout_cmd: first cmd sent from driver that timed out - subsequent timeouts are not stored 325 */ 326 struct dmub_timeout_info { 327 bool timeout_occured; 328 union dmub_rb_cmd timeout_cmd; 329 unsigned long long timestamp; 330 }; 331 332 /** 333 * struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for 334 * debugging purposes, including logging, crash analysis, etc. 335 */ 336 struct dmub_diagnostic_data { 337 uint32_t dmcub_version; 338 uint32_t scratch[17]; 339 uint32_t pc[DMUB_PC_SNAPSHOT_COUNT]; 340 uint32_t undefined_address_fault_addr; 341 uint32_t inst_fetch_fault_addr; 342 uint32_t data_write_fault_addr; 343 uint32_t inbox1_rptr; 344 uint32_t inbox1_wptr; 345 uint32_t inbox1_size; 346 uint32_t inbox0_rptr; 347 uint32_t inbox0_wptr; 348 uint32_t inbox0_size; 349 uint32_t outbox1_rptr; 350 uint32_t outbox1_wptr; 351 uint32_t outbox1_size; 352 uint32_t gpint_datain0; 353 struct dmub_timeout_info timeout_info; 354 uint8_t is_dmcub_enabled : 1; 355 uint8_t is_dmcub_soft_reset : 1; 356 uint8_t is_dmcub_secure_reset : 1; 357 uint8_t is_traceport_en : 1; 358 uint8_t is_cw0_enabled : 1; 359 uint8_t is_cw6_enabled : 1; 360 uint8_t is_pwait : 1; 361 }; 362 363 struct dmub_srv_inbox { 364 /* generic status */ 365 uint64_t num_submitted; 366 uint64_t num_reported; 367 union { 368 /* frame buffer mailbox status */ 369 struct dmub_rb rb; 370 /* register mailbox status */ 371 struct { 372 bool is_pending; 373 bool is_multi_pending; 374 }; 375 }; 376 }; 377 378 /** 379 * struct dmub_srv_base_funcs - Driver specific base callbacks 380 */ 381 struct dmub_srv_base_funcs { 382 /** 383 * @reg_read: 384 * 385 * Hook for reading a register. 386 * 387 * Return: The 32-bit register value from the given address. 388 */ 389 uint32_t (*reg_read)(void *ctx, uint32_t address); 390 391 /** 392 * @reg_write: 393 * 394 * Hook for writing a value to the register specified by address. 395 */ 396 void (*reg_write)(void *ctx, uint32_t address, uint32_t value); 397 }; 398 399 /** 400 * struct dmub_srv_hw_funcs - hardware sequencer funcs for dmub 401 */ 402 struct dmub_srv_hw_funcs { 403 /* private: internal use only */ 404 405 void (*init)(struct dmub_srv *dmub); 406 407 void (*reset)(struct dmub_srv *dmub); 408 409 void (*reset_release)(struct dmub_srv *dmub); 410 411 void (*backdoor_load)(struct dmub_srv *dmub, 412 const struct dmub_window *cw0, 413 const struct dmub_window *cw1); 414 415 void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub, 416 const struct dmub_window *cw0, 417 const struct dmub_window *cw1); 418 void (*setup_windows)(struct dmub_srv *dmub, 419 const struct dmub_window *cw2, 420 const struct dmub_window *cw3, 421 const struct dmub_window *cw4, 422 const struct dmub_window *cw5, 423 const struct dmub_window *cw6, 424 const struct dmub_window *region6); 425 426 void (*setup_mailbox)(struct dmub_srv *dmub, 427 const struct dmub_region *inbox1); 428 429 uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub); 430 431 uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub); 432 433 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 434 435 void (*setup_out_mailbox)(struct dmub_srv *dmub, 436 const struct dmub_region *outbox1); 437 438 uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub); 439 440 void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 441 442 void (*setup_outbox0)(struct dmub_srv *dmub, 443 const struct dmub_region *outbox0); 444 445 uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub); 446 447 void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 448 449 uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub); 450 451 uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub); 452 453 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 454 455 bool (*is_supported)(struct dmub_srv *dmub); 456 457 bool (*is_psrsu_supported)(struct dmub_srv *dmub); 458 459 bool (*is_hw_init)(struct dmub_srv *dmub); 460 bool (*is_hw_powered_up)(struct dmub_srv *dmub); 461 462 void (*enable_dmub_boot_options)(struct dmub_srv *dmub, 463 const struct dmub_srv_hw_params *params); 464 465 void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip); 466 467 union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub); 468 469 union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub); 470 471 void (*set_gpint)(struct dmub_srv *dmub, 472 union dmub_gpint_data_register reg); 473 474 bool (*is_gpint_acked)(struct dmub_srv *dmub, 475 union dmub_gpint_data_register reg); 476 477 uint32_t (*get_gpint_response)(struct dmub_srv *dmub); 478 479 uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub); 480 481 void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub); 482 void (*clear_inbox0_ack_register)(struct dmub_srv *dmub); 483 uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub); 484 void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 485 uint32_t (*get_current_time)(struct dmub_srv *dmub); 486 487 void (*get_diagnostic_data)(struct dmub_srv *dmub); 488 489 bool (*should_detect)(struct dmub_srv *dmub); 490 void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx); 491 492 void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 493 494 void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub, 495 union dmub_rb_cmd *cmd); 496 uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub); 497 void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub, 498 union dmub_rb_cmd *cmd); 499 void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 500 void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 501 void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable); 502 503 uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub); 504 void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub); 505 void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg); 506 void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp); 507 uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub); 508 void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable); 509 }; 510 511 /** 512 * struct dmub_srv_create_params - params for dmub service creation 513 * @base_funcs: driver supplied base routines 514 * @hw_funcs: optional overrides for hw funcs 515 * @user_ctx: context data for callback funcs 516 * @asic: driver supplied asic 517 * @fw_version: the current firmware version, if any 518 * @is_virtual: false for hw support only 519 */ 520 struct dmub_srv_create_params { 521 struct dmub_srv_base_funcs funcs; 522 struct dmub_srv_hw_funcs *hw_funcs; 523 void *user_ctx; 524 enum dmub_asic asic; 525 uint32_t fw_version; 526 bool is_virtual; 527 enum dmub_inbox_cmd_interface_type inbox_type; 528 }; 529 530 /** 531 * struct dmub_srv - software state for dmcub 532 * @asic: dmub asic identifier 533 * @user_ctx: user provided context for the dmub_srv 534 * @fw_version: the current firmware version, if any 535 * @is_virtual: false if hardware support only 536 * @shared_state: dmub shared state between firmware and driver 537 * @fw_state: dmub firmware state pointer 538 */ 539 struct dmub_srv { 540 enum dmub_asic asic; 541 void *user_ctx; 542 uint32_t fw_version; 543 bool is_virtual; 544 struct dmub_fb scratch_mem_fb; 545 struct dmub_fb ib_mem_gart; 546 volatile struct dmub_shared_state_feature_block *shared_state; 547 volatile const struct dmub_fw_state *fw_state; 548 549 /* private: internal use only */ 550 const struct dmub_srv_common_regs *regs; 551 const struct dmub_srv_dcn31_regs *regs_dcn31; 552 struct dmub_srv_dcn32_regs *regs_dcn32; 553 struct dmub_srv_dcn35_regs *regs_dcn35; 554 const struct dmub_srv_dcn401_regs *regs_dcn401; 555 struct dmub_srv_base_funcs funcs; 556 struct dmub_srv_hw_funcs hw_funcs; 557 struct dmub_srv_inbox inbox1; 558 uint32_t inbox1_last_wptr; 559 struct dmub_srv_inbox reg_inbox0; 560 /** 561 * outbox1_rb is accessed without locks (dal & dc) 562 * and to be used only in dmub_srv_stat_get_notification() 563 */ 564 struct dmub_rb outbox1_rb; 565 566 struct dmub_rb outbox0_rb; 567 568 bool sw_init; 569 bool hw_init; 570 571 uint64_t fb_base; 572 uint64_t fb_offset; 573 uint32_t psp_version; 574 575 /* Feature capabilities reported by fw */ 576 struct dmub_fw_meta_info meta_info; 577 struct dmub_feature_caps feature_caps; 578 struct dmub_visual_confirm_color visual_confirm_color; 579 enum dmub_inbox_cmd_interface_type inbox_type; 580 581 enum dmub_srv_power_state_type power_state; 582 struct dmub_diagnostic_data debug; 583 struct dmub_fb lsdma_rb_fb; 584 }; 585 586 /** 587 * struct dmub_notification - dmub notification data 588 * @type: dmub notification type 589 * @link_index: link index to identify aux connection 590 * @result: USB4 status returned from dmub 591 * @pending_notification: Indicates there are other pending notifications 592 * @aux_reply: aux reply 593 * @hpd_status: hpd status 594 * @bw_alloc_reply: BW Allocation reply from CM/DPIA 595 */ 596 struct dmub_notification { 597 enum dmub_notification_type type; 598 uint8_t link_index; 599 uint8_t result; 600 bool pending_notification; 601 union { 602 struct aux_reply_data aux_reply; 603 enum dp_hpd_status hpd_status; 604 enum set_config_status sc_status; 605 struct dmub_rb_cmd_hpd_sense_notify_data hpd_sense_notify; 606 struct dmub_cmd_fused_request fused_request; 607 }; 608 }; 609 610 /* enum dmub_ips_mode - IPS mode identifier */ 611 enum dmub_ips_mode { 612 DMUB_IPS_MODE_IPS1_MAX = 0, 613 DMUB_IPS_MODE_IPS2, 614 DMUB_IPS_MODE_IPS1_RCG, 615 DMUB_IPS_MODE_IPS1_ONO2_ON 616 }; 617 618 /** 619 * DMUB firmware version helper macro - useful for checking if the version 620 * of a firmware to know if feature or functionality is supported or present. 621 */ 622 #define DMUB_FW_VERSION(major, minor, revision) \ 623 ((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | (((revision) & 0xFF) << 8)) 624 625 /** 626 * dmub_srv_create() - creates the DMUB service. 627 * @dmub: the dmub service 628 * @params: creation parameters for the service 629 * 630 * Return: 631 * DMUB_STATUS_OK - success 632 * DMUB_STATUS_INVALID - unspecified error 633 */ 634 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 635 const struct dmub_srv_create_params *params); 636 637 /** 638 * dmub_srv_destroy() - destroys the DMUB service. 639 * @dmub: the dmub service 640 */ 641 void dmub_srv_destroy(struct dmub_srv *dmub); 642 643 /** 644 * dmub_srv_calc_region_info() - retreives region info from the dmub service 645 * @dmub: the dmub service 646 * @params: parameters used to calculate region locations 647 * @info_out: the output region info from dmub 648 * 649 * Calculates the base and top address for all relevant dmub regions 650 * using the parameters given (if any). 651 * 652 * Return: 653 * DMUB_STATUS_OK - success 654 * DMUB_STATUS_INVALID - unspecified error 655 */ 656 enum dmub_status 657 dmub_srv_calc_region_info(struct dmub_srv *dmub, 658 const struct dmub_srv_region_params *params, 659 struct dmub_srv_region_info *out); 660 661 /** 662 * dmub_srv_calc_region_info() - retreives fb info from the dmub service 663 * @dmub: the dmub service 664 * @params: parameters used to calculate fb locations 665 * @info_out: the output fb info from dmub 666 * 667 * Calculates the base and top address for all relevant dmub regions 668 * using the parameters given (if any). 669 * 670 * Return: 671 * DMUB_STATUS_OK - success 672 * DMUB_STATUS_INVALID - unspecified error 673 */ 674 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 675 const struct dmub_srv_memory_params *params, 676 struct dmub_srv_fb_info *out); 677 678 /** 679 * dmub_srv_has_hw_support() - returns hw support state for dmcub 680 * @dmub: the dmub service 681 * @is_supported: hw support state 682 * 683 * Queries the hardware for DMCUB support and returns the result. 684 * 685 * Can be called before dmub_srv_hw_init(). 686 * 687 * Return: 688 * DMUB_STATUS_OK - success 689 * DMUB_STATUS_INVALID - unspecified error 690 */ 691 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 692 bool *is_supported); 693 694 /** 695 * dmub_srv_is_hw_init() - returns hardware init state 696 * 697 * Return: 698 * DMUB_STATUS_OK - success 699 * DMUB_STATUS_INVALID - unspecified error 700 */ 701 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init); 702 703 /** 704 * dmub_srv_hw_init() - initializes the underlying DMUB hardware 705 * @dmub: the dmub service 706 * @params: params for hardware initialization 707 * 708 * Resets the DMUB hardware and performs backdoor loading of the 709 * required cache regions based on the input framebuffer regions. 710 * 711 * Return: 712 * DMUB_STATUS_OK - success 713 * DMUB_STATUS_NO_CTX - dmcub context not initialized 714 * DMUB_STATUS_INVALID - unspecified error 715 */ 716 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 717 const struct dmub_srv_hw_params *params); 718 719 /** 720 * dmub_srv_hw_reset() - puts the DMUB hardware in reset state if initialized 721 * @dmub: the dmub service 722 * 723 * Before destroying the DMUB service or releasing the backing framebuffer 724 * memory we'll need to put the DMCUB into reset first. 725 * 726 * A subsequent call to dmub_srv_hw_init() will re-enable the DMCUB. 727 * 728 * Return: 729 * DMUB_STATUS_OK - success 730 * DMUB_STATUS_INVALID - unspecified error 731 */ 732 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub); 733 734 /** 735 * dmub_srv_fb_cmd_queue() - queues a command to the DMUB 736 * @dmub: the dmub service 737 * @cmd: the command to queue 738 * 739 * Queues a command to the DMUB service but does not begin execution 740 * immediately. 741 * 742 * Return: 743 * DMUB_STATUS_OK - success 744 * DMUB_STATUS_QUEUE_FULL - no remaining room in queue 745 * DMUB_STATUS_INVALID - unspecified error 746 */ 747 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 748 const union dmub_rb_cmd *cmd); 749 750 /** 751 * dmub_srv_fb_cmd_execute() - Executes a queued sequence to the dmub 752 * @dmub: the dmub service 753 * 754 * Begins execution of queued commands on the dmub. 755 * 756 * Return: 757 * DMUB_STATUS_OK - success 758 * DMUB_STATUS_INVALID - unspecified error 759 */ 760 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub); 761 762 /** 763 * dmub_srv_wait_for_hw_pwr_up() - Waits for firmware hardware power up is completed 764 * @dmub: the dmub service 765 * @timeout_us: the maximum number of microseconds to wait 766 * 767 * Waits until firmware hardware is powered up. The maximum 768 * wait time is given in microseconds to prevent spinning forever. 769 * 770 * Return: 771 * DMUB_STATUS_OK - success 772 * DMUB_STATUS_TIMEOUT - timed out 773 * DMUB_STATUS_INVALID - unspecified error 774 */ 775 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 776 uint32_t timeout_us); 777 778 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub); 779 780 /** 781 * dmub_srv_wait_for_auto_load() - Waits for firmware auto load to complete 782 * @dmub: the dmub service 783 * @timeout_us: the maximum number of microseconds to wait 784 * 785 * Waits until firmware has been autoloaded by the DMCUB. The maximum 786 * wait time is given in microseconds to prevent spinning forever. 787 * 788 * On ASICs without firmware autoload support this function will return 789 * immediately. 790 * 791 * Return: 792 * DMUB_STATUS_OK - success 793 * DMUB_STATUS_TIMEOUT - wait for phy init timed out 794 * DMUB_STATUS_INVALID - unspecified error 795 */ 796 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 797 uint32_t timeout_us); 798 799 /** 800 * dmub_srv_wait_for_phy_init() - Waits for DMUB PHY init to complete 801 * @dmub: the dmub service 802 * @timeout_us: the maximum number of microseconds to wait 803 * 804 * Waits until the PHY has been initialized by the DMUB. The maximum 805 * wait time is given in microseconds to prevent spinning forever. 806 * 807 * On ASICs without PHY init support this function will return 808 * immediately. 809 * 810 * Return: 811 * DMUB_STATUS_OK - success 812 * DMUB_STATUS_TIMEOUT - wait for phy init timed out 813 * DMUB_STATUS_INVALID - unspecified error 814 */ 815 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 816 uint32_t timeout_us); 817 818 /** 819 * dmub_srv_wait_for_pending() - Re-entrant wait for messages currently pending 820 * @dmub: the dmub service 821 * @timeout_us: the maximum number of microseconds to wait 822 * 823 * Waits until the commands queued prior to this call are complete. 824 * If interfaces remain busy due to additional work being submitted 825 * concurrently, this function will not continue to wait. 826 * 827 * Return: 828 * DMUB_STATUS_OK - success 829 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 830 * DMUB_STATUS_INVALID - unspecified error 831 */ 832 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 833 uint32_t timeout_us); 834 835 /** 836 * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle 837 * @dmub: the dmub service 838 * @timeout_us: the maximum number of microseconds to wait 839 * 840 * Waits until the DMUB buffer is empty and all commands have 841 * finished processing. The maximum wait time is given in 842 * microseconds to prevent spinning forever. 843 * 844 * Return: 845 * DMUB_STATUS_OK - success 846 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 847 * DMUB_STATUS_INVALID - unspecified error 848 */ 849 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 850 uint32_t timeout_us); 851 852 /** 853 * dmub_srv_send_gpint_command() - Sends a GPINT based command. 854 * @dmub: the dmub service 855 * @command_code: the command code to send 856 * @param: the command parameter to send 857 * @timeout_us: the maximum number of microseconds to wait 858 * 859 * Sends a command via the general purpose interrupt (GPINT). 860 * Waits for the number of microseconds specified by timeout_us 861 * for the command ACK before returning. 862 * 863 * Can be called after software initialization. 864 * 865 * Return: 866 * DMUB_STATUS_OK - success 867 * DMUB_STATUS_TIMEOUT - wait for ACK timed out 868 * DMUB_STATUS_INVALID - unspecified error 869 */ 870 enum dmub_status 871 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 872 enum dmub_gpint_command command_code, 873 uint16_t param, uint32_t timeout_us); 874 875 /** 876 * dmub_srv_get_gpint_response() - Queries the GPINT response. 877 * @dmub: the dmub service 878 * @response: the response for the last GPINT 879 * 880 * Returns the response code for the last GPINT interrupt. 881 * 882 * Can be called after software initialization. 883 * 884 * Return: 885 * DMUB_STATUS_OK - success 886 * DMUB_STATUS_INVALID - unspecified error 887 */ 888 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 889 uint32_t *response); 890 891 /** 892 * dmub_srv_get_gpint_dataout() - Queries the GPINT DATAOUT. 893 * @dmub: the dmub service 894 * @dataout: the data for the GPINT DATAOUT 895 * 896 * Returns the response code for the last GPINT DATAOUT interrupt. 897 * 898 * Can be called after software initialization. 899 * 900 * Return: 901 * DMUB_STATUS_OK - success 902 * DMUB_STATUS_INVALID - unspecified error 903 */ 904 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 905 uint32_t *dataout); 906 907 /** 908 * dmub_flush_buffer_mem() - Read back entire frame buffer region. 909 * This ensures that the write from x86 has been flushed and will not 910 * hang the DMCUB. 911 * @fb: frame buffer to flush 912 * 913 * Can be called after software initialization. 914 */ 915 void dmub_flush_buffer_mem(const struct dmub_fb *fb); 916 917 /** 918 * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits. 919 * 920 * @dmub: the dmub service 921 * @status: out pointer for firmware status 922 * 923 * Return: 924 * DMUB_STATUS_OK - success 925 * DMUB_STATUS_INVALID - unspecified error, unsupported 926 */ 927 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 928 union dmub_fw_boot_status *status); 929 930 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 931 union dmub_fw_boot_options *option); 932 933 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 934 bool skip); 935 936 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry); 937 938 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub); 939 940 bool dmub_srv_should_detect(struct dmub_srv *dmub); 941 942 /** 943 * dmub_srv_send_inbox0_cmd() - Send command to DMUB using INBOX0 944 * @dmub: the dmub service 945 * @data: the data to be sent in the INBOX0 command 946 * 947 * Send command by writing directly to INBOX0 WPTR 948 * 949 * Return: 950 * DMUB_STATUS_OK - success 951 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 952 */ 953 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 954 955 /** 956 * dmub_srv_wait_for_inbox0_ack() - wait for DMUB to ACK INBOX0 command 957 * @dmub: the dmub service 958 * @timeout_us: the maximum number of microseconds to wait 959 * 960 * Wait for DMUB to ACK the INBOX0 message 961 * 962 * Return: 963 * DMUB_STATUS_OK - success 964 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 965 * DMUB_STATUS_TIMEOUT - wait for ack timed out 966 */ 967 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us); 968 969 /** 970 * dmub_srv_wait_for_inbox0_ack() - clear ACK register for INBOX0 971 * @dmub: the dmub service 972 * 973 * Clear ACK register for INBOX0 974 * 975 * Return: 976 * DMUB_STATUS_OK - success 977 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 978 */ 979 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub); 980 981 /** 982 * dmub_srv_subvp_save_surf_addr() - Save primary and meta address for subvp on each flip 983 * @dmub: The dmub service 984 * @addr: The surface address to be programmed on the current flip 985 * @subvp_index: Index of subvp pipe, indicates which subvp pipe the address should be saved for 986 * 987 * Function to save the surface flip addr into scratch registers. This is to fix a race condition 988 * between FW and driver reading / writing to the surface address at the same time. This is 989 * required because there is no EARLIEST_IN_USE_META. 990 * 991 * Return: 992 * void 993 */ 994 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 995 996 /** 997 * dmub_srv_set_power_state() - Track DC power state in dmub_srv 998 * @dmub: The dmub service 999 * @power_state: DC power state setting 1000 * 1001 * Store DC power state in dmub_srv. If dmub_srv is in D3, then don't send messages to DMUB 1002 * 1003 * Return: 1004 * void 1005 */ 1006 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state); 1007 1008 /** 1009 * dmub_srv_reg_cmd_execute() - Executes provided command to the dmub 1010 * @dmub: the dmub service 1011 * @cmd: the command packet to be executed 1012 * 1013 * Executes a single command for the dmub. 1014 * 1015 * Return: 1016 * DMUB_STATUS_OK - success 1017 * DMUB_STATUS_INVALID - unspecified error 1018 */ 1019 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 1020 1021 1022 /** 1023 * dmub_srv_cmd_get_response() - Copies return data for command into buffer 1024 * @dmub: the dmub service 1025 * @cmd_rsp: response buffer 1026 * 1027 * Copies return data for command into buffer 1028 */ 1029 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1030 union dmub_rb_cmd *cmd_rsp); 1031 1032 /** 1033 * dmub_srv_sync_inboxes() - Sync inbox state 1034 * @dmub: the dmub service 1035 * 1036 * Sync inbox state 1037 * 1038 * Return: 1039 * DMUB_STATUS_OK - success 1040 * DMUB_STATUS_INVALID - unspecified error 1041 */ 1042 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub); 1043 1044 /** 1045 * dmub_srv_wait_for_inbox_free() - Waits for space in the DMUB inbox to free up 1046 * @dmub: the dmub service 1047 * @timeout_us: the maximum number of microseconds to wait 1048 * @num_free_required: number of free entries required 1049 * 1050 * Waits until the DMUB buffer is freed to the specified number. 1051 * The maximum wait time is given in microseconds to prevent spinning 1052 * forever. 1053 * 1054 * Return: 1055 * DMUB_STATUS_OK - success 1056 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 1057 * DMUB_STATUS_INVALID - unspecified error 1058 */ 1059 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1060 uint32_t timeout_us, 1061 uint32_t num_free_required); 1062 1063 /** 1064 * dmub_srv_update_inbox_status() - Updates pending status for inbox & reg inbox0 1065 * @dmub: the dmub service 1066 * 1067 * Return: 1068 * DMUB_STATUS_OK - success 1069 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 1070 * DMUB_STATUS_HW_FAILURE - issue with HW programming 1071 * DMUB_STATUS_INVALID - unspecified error 1072 */ 1073 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub); 1074 1075 #endif /* _DMUB_SRV_H_ */ 1076