1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_SRV_H_ 27 #define _DMUB_SRV_H_ 28 29 /** 30 * DOC: DMUB interface and operation 31 * 32 * DMUB is the interface to the display DMCUB microcontroller on DCN hardware. 33 * It delegates hardware initialization and command submission to the 34 * microcontroller. DMUB is the shortname for DMCUB. 35 * 36 * This interface is not thread-safe. Ensure that all access to the interface 37 * is properly synchronized by the caller. 38 * 39 * Initialization and usage of the DMUB service should be done in the 40 * steps given below: 41 * 42 * 1. dmub_srv_create() 43 * 2. dmub_srv_has_hw_support() 44 * 3. dmub_srv_calc_region_info() 45 * 4. dmub_srv_hw_init() 46 * 47 * The call to dmub_srv_create() is required to use the server. 48 * 49 * The calls to dmub_srv_has_hw_support() and dmub_srv_calc_region_info() 50 * are helpers to query cache window size and allocate framebuffer(s) 51 * for the cache windows. 52 * 53 * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare 54 * for command submission. Commands can be queued via dmub_srv_fb_cmd_queue() 55 * and executed via dmub_srv_fb_cmd_execute(). 56 * 57 * If the queue is full the dmub_srv_wait_for_idle() call can be used to 58 * wait until the queue has been cleared. 59 * 60 * Destroying the DMUB service can be done by calling dmub_srv_destroy(). 61 * This does not clear DMUB hardware state, only software state. 62 * 63 * The interface is intended to be standalone and should not depend on any 64 * other component within DAL. 65 */ 66 67 #include "inc/dmub_cmd.h" 68 #include "dc/dc_types.h" 69 70 #define DMUB_PC_SNAPSHOT_COUNT 10 71 72 /* Default tracebuffer size if meta is absent. */ 73 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 74 75 /* Forward declarations */ 76 struct dmub_srv; 77 struct dmub_srv_common_regs; 78 struct dmub_srv_dcn31_regs; 79 80 struct dmcub_trace_buf_entry; 81 82 /* enum dmub_window_memory_type - memory location type specification for windows */ 83 enum dmub_window_memory_type { 84 DMUB_WINDOW_MEMORY_TYPE_FB = 0, 85 DMUB_WINDOW_MEMORY_TYPE_GART 86 }; 87 88 /* enum dmub_status - return code for dmcub functions */ 89 enum dmub_status { 90 DMUB_STATUS_OK = 0, 91 DMUB_STATUS_NO_CTX, 92 DMUB_STATUS_QUEUE_FULL, 93 DMUB_STATUS_TIMEOUT, 94 DMUB_STATUS_INVALID, 95 DMUB_STATUS_HW_FAILURE, 96 DMUB_STATUS_POWER_STATE_D3 97 }; 98 99 /* enum dmub_asic - dmub asic identifier */ 100 enum dmub_asic { 101 DMUB_ASIC_NONE = 0, 102 DMUB_ASIC_DCN20, 103 DMUB_ASIC_DCN21, 104 DMUB_ASIC_DCN30, 105 DMUB_ASIC_DCN301, 106 DMUB_ASIC_DCN302, 107 DMUB_ASIC_DCN303, 108 DMUB_ASIC_DCN31, 109 DMUB_ASIC_DCN31B, 110 DMUB_ASIC_DCN314, 111 DMUB_ASIC_DCN315, 112 DMUB_ASIC_DCN316, 113 DMUB_ASIC_DCN32, 114 DMUB_ASIC_DCN321, 115 DMUB_ASIC_DCN35, 116 DMUB_ASIC_DCN351, 117 DMUB_ASIC_DCN36, 118 DMUB_ASIC_DCN401, 119 DMUB_ASIC_MAX, 120 }; 121 122 /* enum dmub_window_id - dmub window identifier */ 123 enum dmub_window_id { 124 DMUB_WINDOW_0_INST_CONST = 0, 125 DMUB_WINDOW_1_STACK, 126 DMUB_WINDOW_2_BSS_DATA, 127 DMUB_WINDOW_3_VBIOS, 128 DMUB_WINDOW_4_MAILBOX, 129 DMUB_WINDOW_5_TRACEBUFF, 130 DMUB_WINDOW_6_FW_STATE, 131 DMUB_WINDOW_7_SCRATCH_MEM, 132 DMUB_WINDOW_IB_MEM, 133 DMUB_WINDOW_SHARED_STATE, 134 DMUB_WINDOW_TOTAL, 135 }; 136 137 /* enum dmub_notification_type - dmub outbox notification identifier */ 138 enum dmub_notification_type { 139 DMUB_NOTIFICATION_NO_DATA = 0, 140 DMUB_NOTIFICATION_AUX_REPLY, 141 DMUB_NOTIFICATION_HPD, 142 DMUB_NOTIFICATION_HPD_IRQ, 143 DMUB_NOTIFICATION_SET_CONFIG_REPLY, 144 DMUB_NOTIFICATION_DPIA_NOTIFICATION, 145 DMUB_NOTIFICATION_HPD_SENSE_NOTIFY, 146 DMUB_NOTIFICATION_FUSED_IO, 147 DMUB_NOTIFICATION_MAX 148 }; 149 150 /** 151 * DPIA NOTIFICATION Response Type 152 */ 153 enum dpia_notify_bw_alloc_status { 154 155 DPIA_BW_REQ_FAILED = 0, 156 DPIA_BW_REQ_SUCCESS, 157 DPIA_EST_BW_CHANGED, 158 DPIA_BW_ALLOC_CAPS_CHANGED 159 }; 160 161 /* enum dmub_memory_access_type - memory access method */ 162 enum dmub_memory_access_type { 163 DMUB_MEMORY_ACCESS_DEFAULT, 164 DMUB_MEMORY_ACCESS_CPU = DMUB_MEMORY_ACCESS_DEFAULT, 165 DMUB_MEMORY_ACCESS_DMA 166 }; 167 168 /* enum dmub_power_state type - to track DC power state in dmub_srv */ 169 enum dmub_srv_power_state_type { 170 DMUB_POWER_STATE_UNDEFINED = 0, 171 DMUB_POWER_STATE_D0 = 1, 172 DMUB_POWER_STATE_D3 = 8 173 }; 174 175 /* enum dmub_inbox_cmd_interface type - defines default interface for host->dmub commands */ 176 enum dmub_inbox_cmd_interface_type { 177 DMUB_CMD_INTERFACE_DEFAULT = 0, 178 DMUB_CMD_INTERFACE_FB = 1, 179 DMUB_CMD_INTERFACE_REG = 2, 180 }; 181 182 /** 183 * struct dmub_region - dmub hw memory region 184 * @base: base address for region, must be 256 byte aligned 185 * @top: top address for region 186 */ 187 struct dmub_region { 188 uint32_t base; 189 uint32_t top; 190 }; 191 192 /** 193 * struct dmub_window - dmub hw cache window 194 * @off: offset to the fb memory in gpu address space 195 * @r: region in uc address space for cache window 196 */ 197 struct dmub_window { 198 union dmub_addr offset; 199 struct dmub_region region; 200 }; 201 202 /** 203 * struct dmub_fb - defines a dmub framebuffer memory region 204 * @cpu_addr: cpu virtual address for the region, NULL if invalid 205 * @gpu_addr: gpu virtual address for the region, NULL if invalid 206 * @size: size of the region in bytes, zero if invalid 207 */ 208 struct dmub_fb { 209 void *cpu_addr; 210 uint64_t gpu_addr; 211 uint32_t size; 212 }; 213 214 /** 215 * struct dmub_srv_region_params - params used for calculating dmub regions 216 * @inst_const_size: size of the fw inst const section 217 * @bss_data_size: size of the fw bss data section 218 * @vbios_size: size of the vbios data 219 * @fw_bss_data: raw firmware bss data section 220 */ 221 struct dmub_srv_region_params { 222 uint32_t inst_const_size; 223 uint32_t bss_data_size; 224 uint32_t vbios_size; 225 const uint8_t *fw_inst_const; 226 const uint8_t *fw_bss_data; 227 const enum dmub_window_memory_type *window_memory_type; 228 }; 229 230 /** 231 * struct dmub_srv_region_info - output region info from the dmub service 232 * @fb_size: required minimum fb size for all regions, aligned to 4096 bytes 233 * @num_regions: number of regions used by the dmub service 234 * @regions: region info 235 * 236 * The regions are aligned such that they can be all placed within the 237 * same framebuffer but they can also be placed into different framebuffers. 238 * 239 * The size of each region can be calculated by the caller: 240 * size = reg.top - reg.base 241 * 242 * Care must be taken when performing custom allocations to ensure that each 243 * region base address is 256 byte aligned. 244 */ 245 struct dmub_srv_region_info { 246 uint32_t fb_size; 247 uint32_t gart_size; 248 uint8_t num_regions; 249 struct dmub_region regions[DMUB_WINDOW_TOTAL]; 250 }; 251 252 /** 253 * struct dmub_srv_memory_params - parameters used for driver fb setup 254 * @region_info: region info calculated by dmub service 255 * @cpu_fb_addr: base cpu address for the framebuffer 256 * @cpu_inbox_addr: base cpu address for the gart 257 * @gpu_fb_addr: base gpu virtual address for the framebuffer 258 * @gpu_inbox_addr: base gpu virtual address for the gart 259 */ 260 struct dmub_srv_memory_params { 261 const struct dmub_srv_region_info *region_info; 262 void *cpu_fb_addr; 263 void *cpu_gart_addr; 264 uint64_t gpu_fb_addr; 265 uint64_t gpu_gart_addr; 266 const enum dmub_window_memory_type *window_memory_type; 267 }; 268 269 /** 270 * struct dmub_srv_fb_info - output fb info from the dmub service 271 * @num_fbs: number of required dmub framebuffers 272 * @fbs: fb data for each region 273 * 274 * Output from the dmub service helper that can be used by the 275 * driver to prepare dmub_fb that can be passed into the dmub 276 * hw init service. 277 * 278 * Assumes that all regions are within the same framebuffer 279 * and have been setup according to the region_info generated 280 * by the dmub service. 281 */ 282 struct dmub_srv_fb_info { 283 uint8_t num_fb; 284 struct dmub_fb fb[DMUB_WINDOW_TOTAL]; 285 }; 286 287 /* 288 * struct dmub_srv_hw_params - params for dmub hardware initialization 289 * @fb: framebuffer info for each region 290 * @fb_base: base of the framebuffer aperture 291 * @fb_offset: offset of the framebuffer aperture 292 * @psp_version: psp version to pass for DMCU init 293 * @load_inst_const: true if DMUB should load inst const fw 294 */ 295 struct dmub_srv_hw_params { 296 struct dmub_fb *fb[DMUB_WINDOW_TOTAL]; 297 uint64_t fb_base; 298 uint64_t fb_offset; 299 uint32_t psp_version; 300 bool load_inst_const; 301 bool skip_panel_power_sequence; 302 bool disable_z10; 303 bool power_optimization; 304 bool dpia_supported; 305 bool disable_dpia; 306 bool usb4_cm_version; 307 bool fw_in_system_memory; 308 bool dpia_hpd_int_enable_supported; 309 bool disable_clock_gate; 310 bool disallow_dispclk_dppclk_ds; 311 bool ips_sequential_ono; 312 enum dmub_memory_access_type mem_access_type; 313 enum dmub_ips_disable_type disable_ips; 314 bool disallow_phy_access; 315 bool disable_sldo_opt; 316 bool enable_non_transparent_setconfig; 317 bool lower_hbr3_phy_ssc; 318 }; 319 320 /** 321 * struct dmub_srv_debug - Debug info for dmub_srv 322 * @timeout_occured: Indicates a timeout occured on any message from driver to dmub 323 * @timeout_cmd: first cmd sent from driver that timed out - subsequent timeouts are not stored 324 */ 325 struct dmub_timeout_info { 326 bool timeout_occured; 327 union dmub_rb_cmd timeout_cmd; 328 unsigned long long timestamp; 329 }; 330 331 /** 332 * struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for 333 * debugging purposes, including logging, crash analysis, etc. 334 */ 335 struct dmub_diagnostic_data { 336 uint32_t dmcub_version; 337 uint32_t scratch[17]; 338 uint32_t pc[DMUB_PC_SNAPSHOT_COUNT]; 339 uint32_t undefined_address_fault_addr; 340 uint32_t inst_fetch_fault_addr; 341 uint32_t data_write_fault_addr; 342 uint32_t inbox1_rptr; 343 uint32_t inbox1_wptr; 344 uint32_t inbox1_size; 345 uint32_t inbox0_rptr; 346 uint32_t inbox0_wptr; 347 uint32_t inbox0_size; 348 uint32_t outbox1_rptr; 349 uint32_t outbox1_wptr; 350 uint32_t outbox1_size; 351 uint32_t gpint_datain0; 352 struct dmub_timeout_info timeout_info; 353 uint8_t is_dmcub_enabled : 1; 354 uint8_t is_dmcub_soft_reset : 1; 355 uint8_t is_dmcub_secure_reset : 1; 356 uint8_t is_traceport_en : 1; 357 uint8_t is_cw0_enabled : 1; 358 uint8_t is_cw6_enabled : 1; 359 uint8_t is_pwait : 1; 360 }; 361 362 struct dmub_srv_inbox { 363 /* generic status */ 364 uint64_t num_submitted; 365 uint64_t num_reported; 366 union { 367 /* frame buffer mailbox status */ 368 struct dmub_rb rb; 369 /* register mailbox status */ 370 struct { 371 bool is_pending; 372 bool is_multi_pending; 373 }; 374 }; 375 }; 376 377 /** 378 * struct dmub_srv_base_funcs - Driver specific base callbacks 379 */ 380 struct dmub_srv_base_funcs { 381 /** 382 * @reg_read: 383 * 384 * Hook for reading a register. 385 * 386 * Return: The 32-bit register value from the given address. 387 */ 388 uint32_t (*reg_read)(void *ctx, uint32_t address); 389 390 /** 391 * @reg_write: 392 * 393 * Hook for writing a value to the register specified by address. 394 */ 395 void (*reg_write)(void *ctx, uint32_t address, uint32_t value); 396 }; 397 398 /** 399 * struct dmub_srv_hw_funcs - hardware sequencer funcs for dmub 400 */ 401 struct dmub_srv_hw_funcs { 402 /* private: internal use only */ 403 404 void (*init)(struct dmub_srv *dmub); 405 406 void (*reset)(struct dmub_srv *dmub); 407 408 void (*reset_release)(struct dmub_srv *dmub); 409 410 void (*backdoor_load)(struct dmub_srv *dmub, 411 const struct dmub_window *cw0, 412 const struct dmub_window *cw1); 413 414 void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub, 415 const struct dmub_window *cw0, 416 const struct dmub_window *cw1); 417 void (*setup_windows)(struct dmub_srv *dmub, 418 const struct dmub_window *cw2, 419 const struct dmub_window *cw3, 420 const struct dmub_window *cw4, 421 const struct dmub_window *cw5, 422 const struct dmub_window *cw6, 423 const struct dmub_window *region6); 424 425 void (*setup_mailbox)(struct dmub_srv *dmub, 426 const struct dmub_region *inbox1); 427 428 uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub); 429 430 uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub); 431 432 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 433 434 void (*setup_out_mailbox)(struct dmub_srv *dmub, 435 const struct dmub_region *outbox1); 436 437 uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub); 438 439 void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 440 441 void (*setup_outbox0)(struct dmub_srv *dmub, 442 const struct dmub_region *outbox0); 443 444 uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub); 445 446 void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 447 448 uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub); 449 450 uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub); 451 452 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 453 454 bool (*is_supported)(struct dmub_srv *dmub); 455 456 bool (*is_psrsu_supported)(struct dmub_srv *dmub); 457 458 bool (*is_hw_init)(struct dmub_srv *dmub); 459 bool (*is_hw_powered_up)(struct dmub_srv *dmub); 460 461 void (*enable_dmub_boot_options)(struct dmub_srv *dmub, 462 const struct dmub_srv_hw_params *params); 463 464 void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip); 465 466 union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub); 467 468 union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub); 469 470 void (*set_gpint)(struct dmub_srv *dmub, 471 union dmub_gpint_data_register reg); 472 473 bool (*is_gpint_acked)(struct dmub_srv *dmub, 474 union dmub_gpint_data_register reg); 475 476 uint32_t (*get_gpint_response)(struct dmub_srv *dmub); 477 478 uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub); 479 480 void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub); 481 void (*clear_inbox0_ack_register)(struct dmub_srv *dmub); 482 uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub); 483 void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 484 uint32_t (*get_current_time)(struct dmub_srv *dmub); 485 486 void (*get_diagnostic_data)(struct dmub_srv *dmub); 487 488 bool (*should_detect)(struct dmub_srv *dmub); 489 void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx); 490 491 void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 492 493 void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub, 494 union dmub_rb_cmd *cmd); 495 uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub); 496 void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub, 497 union dmub_rb_cmd *cmd); 498 void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 499 void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 500 void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable); 501 502 uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub); 503 void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub); 504 void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg); 505 void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp); 506 uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub); 507 void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable); 508 }; 509 510 /** 511 * struct dmub_srv_create_params - params for dmub service creation 512 * @base_funcs: driver supplied base routines 513 * @hw_funcs: optional overrides for hw funcs 514 * @user_ctx: context data for callback funcs 515 * @asic: driver supplied asic 516 * @fw_version: the current firmware version, if any 517 * @is_virtual: false for hw support only 518 */ 519 struct dmub_srv_create_params { 520 struct dmub_srv_base_funcs funcs; 521 struct dmub_srv_hw_funcs *hw_funcs; 522 void *user_ctx; 523 enum dmub_asic asic; 524 uint32_t fw_version; 525 bool is_virtual; 526 enum dmub_inbox_cmd_interface_type inbox_type; 527 }; 528 529 /** 530 * struct dmub_srv - software state for dmcub 531 * @asic: dmub asic identifier 532 * @user_ctx: user provided context for the dmub_srv 533 * @fw_version: the current firmware version, if any 534 * @is_virtual: false if hardware support only 535 * @shared_state: dmub shared state between firmware and driver 536 * @fw_state: dmub firmware state pointer 537 */ 538 struct dmub_srv { 539 enum dmub_asic asic; 540 void *user_ctx; 541 uint32_t fw_version; 542 bool is_virtual; 543 struct dmub_fb scratch_mem_fb; 544 struct dmub_fb ib_mem_gart; 545 volatile struct dmub_shared_state_feature_block *shared_state; 546 volatile const struct dmub_fw_state *fw_state; 547 548 /* private: internal use only */ 549 const struct dmub_srv_common_regs *regs; 550 const struct dmub_srv_dcn31_regs *regs_dcn31; 551 struct dmub_srv_dcn32_regs *regs_dcn32; 552 struct dmub_srv_dcn35_regs *regs_dcn35; 553 const struct dmub_srv_dcn401_regs *regs_dcn401; 554 struct dmub_srv_base_funcs funcs; 555 struct dmub_srv_hw_funcs hw_funcs; 556 struct dmub_srv_inbox inbox1; 557 uint32_t inbox1_last_wptr; 558 struct dmub_srv_inbox reg_inbox0; 559 /** 560 * outbox1_rb is accessed without locks (dal & dc) 561 * and to be used only in dmub_srv_stat_get_notification() 562 */ 563 struct dmub_rb outbox1_rb; 564 565 struct dmub_rb outbox0_rb; 566 567 bool sw_init; 568 bool hw_init; 569 570 uint64_t fb_base; 571 uint64_t fb_offset; 572 uint32_t psp_version; 573 574 /* Feature capabilities reported by fw */ 575 struct dmub_fw_meta_info meta_info; 576 struct dmub_feature_caps feature_caps; 577 struct dmub_visual_confirm_color visual_confirm_color; 578 enum dmub_inbox_cmd_interface_type inbox_type; 579 580 enum dmub_srv_power_state_type power_state; 581 struct dmub_diagnostic_data debug; 582 }; 583 584 /** 585 * struct dmub_notification - dmub notification data 586 * @type: dmub notification type 587 * @link_index: link index to identify aux connection 588 * @result: USB4 status returned from dmub 589 * @pending_notification: Indicates there are other pending notifications 590 * @aux_reply: aux reply 591 * @hpd_status: hpd status 592 * @bw_alloc_reply: BW Allocation reply from CM/DPIA 593 */ 594 struct dmub_notification { 595 enum dmub_notification_type type; 596 uint8_t link_index; 597 uint8_t result; 598 bool pending_notification; 599 union { 600 struct aux_reply_data aux_reply; 601 enum dp_hpd_status hpd_status; 602 enum set_config_status sc_status; 603 struct dmub_rb_cmd_hpd_sense_notify_data hpd_sense_notify; 604 struct dmub_cmd_fused_request fused_request; 605 }; 606 }; 607 608 /* enum dmub_ips_mode - IPS mode identifier */ 609 enum dmub_ips_mode { 610 DMUB_IPS_MODE_IPS1_MAX = 0, 611 DMUB_IPS_MODE_IPS2, 612 DMUB_IPS_MODE_IPS1_RCG, 613 DMUB_IPS_MODE_IPS1_ONO2_ON 614 }; 615 616 /** 617 * DMUB firmware version helper macro - useful for checking if the version 618 * of a firmware to know if feature or functionality is supported or present. 619 */ 620 #define DMUB_FW_VERSION(major, minor, revision) \ 621 ((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | (((revision) & 0xFF) << 8)) 622 623 /** 624 * dmub_srv_create() - creates the DMUB service. 625 * @dmub: the dmub service 626 * @params: creation parameters for the service 627 * 628 * Return: 629 * DMUB_STATUS_OK - success 630 * DMUB_STATUS_INVALID - unspecified error 631 */ 632 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 633 const struct dmub_srv_create_params *params); 634 635 /** 636 * dmub_srv_destroy() - destroys the DMUB service. 637 * @dmub: the dmub service 638 */ 639 void dmub_srv_destroy(struct dmub_srv *dmub); 640 641 /** 642 * dmub_srv_calc_region_info() - retreives region info from the dmub service 643 * @dmub: the dmub service 644 * @params: parameters used to calculate region locations 645 * @info_out: the output region info from dmub 646 * 647 * Calculates the base and top address for all relevant dmub regions 648 * using the parameters given (if any). 649 * 650 * Return: 651 * DMUB_STATUS_OK - success 652 * DMUB_STATUS_INVALID - unspecified error 653 */ 654 enum dmub_status 655 dmub_srv_calc_region_info(struct dmub_srv *dmub, 656 const struct dmub_srv_region_params *params, 657 struct dmub_srv_region_info *out); 658 659 /** 660 * dmub_srv_calc_region_info() - retreives fb info from the dmub service 661 * @dmub: the dmub service 662 * @params: parameters used to calculate fb locations 663 * @info_out: the output fb info from dmub 664 * 665 * Calculates the base and top address for all relevant dmub regions 666 * using the parameters given (if any). 667 * 668 * Return: 669 * DMUB_STATUS_OK - success 670 * DMUB_STATUS_INVALID - unspecified error 671 */ 672 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 673 const struct dmub_srv_memory_params *params, 674 struct dmub_srv_fb_info *out); 675 676 /** 677 * dmub_srv_has_hw_support() - returns hw support state for dmcub 678 * @dmub: the dmub service 679 * @is_supported: hw support state 680 * 681 * Queries the hardware for DMCUB support and returns the result. 682 * 683 * Can be called before dmub_srv_hw_init(). 684 * 685 * Return: 686 * DMUB_STATUS_OK - success 687 * DMUB_STATUS_INVALID - unspecified error 688 */ 689 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 690 bool *is_supported); 691 692 /** 693 * dmub_srv_is_hw_init() - returns hardware init state 694 * 695 * Return: 696 * DMUB_STATUS_OK - success 697 * DMUB_STATUS_INVALID - unspecified error 698 */ 699 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init); 700 701 /** 702 * dmub_srv_hw_init() - initializes the underlying DMUB hardware 703 * @dmub: the dmub service 704 * @params: params for hardware initialization 705 * 706 * Resets the DMUB hardware and performs backdoor loading of the 707 * required cache regions based on the input framebuffer regions. 708 * 709 * Return: 710 * DMUB_STATUS_OK - success 711 * DMUB_STATUS_NO_CTX - dmcub context not initialized 712 * DMUB_STATUS_INVALID - unspecified error 713 */ 714 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 715 const struct dmub_srv_hw_params *params); 716 717 /** 718 * dmub_srv_hw_reset() - puts the DMUB hardware in reset state if initialized 719 * @dmub: the dmub service 720 * 721 * Before destroying the DMUB service or releasing the backing framebuffer 722 * memory we'll need to put the DMCUB into reset first. 723 * 724 * A subsequent call to dmub_srv_hw_init() will re-enable the DMCUB. 725 * 726 * Return: 727 * DMUB_STATUS_OK - success 728 * DMUB_STATUS_INVALID - unspecified error 729 */ 730 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub); 731 732 /** 733 * dmub_srv_fb_cmd_queue() - queues a command to the DMUB 734 * @dmub: the dmub service 735 * @cmd: the command to queue 736 * 737 * Queues a command to the DMUB service but does not begin execution 738 * immediately. 739 * 740 * Return: 741 * DMUB_STATUS_OK - success 742 * DMUB_STATUS_QUEUE_FULL - no remaining room in queue 743 * DMUB_STATUS_INVALID - unspecified error 744 */ 745 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 746 const union dmub_rb_cmd *cmd); 747 748 /** 749 * dmub_srv_fb_cmd_execute() - Executes a queued sequence to the dmub 750 * @dmub: the dmub service 751 * 752 * Begins execution of queued commands on the dmub. 753 * 754 * Return: 755 * DMUB_STATUS_OK - success 756 * DMUB_STATUS_INVALID - unspecified error 757 */ 758 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub); 759 760 /** 761 * dmub_srv_wait_for_hw_pwr_up() - Waits for firmware hardware power up is completed 762 * @dmub: the dmub service 763 * @timeout_us: the maximum number of microseconds to wait 764 * 765 * Waits until firmware hardware is powered up. The maximum 766 * wait time is given in microseconds to prevent spinning forever. 767 * 768 * Return: 769 * DMUB_STATUS_OK - success 770 * DMUB_STATUS_TIMEOUT - timed out 771 * DMUB_STATUS_INVALID - unspecified error 772 */ 773 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 774 uint32_t timeout_us); 775 776 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub); 777 778 /** 779 * dmub_srv_wait_for_auto_load() - Waits for firmware auto load to complete 780 * @dmub: the dmub service 781 * @timeout_us: the maximum number of microseconds to wait 782 * 783 * Waits until firmware has been autoloaded by the DMCUB. The maximum 784 * wait time is given in microseconds to prevent spinning forever. 785 * 786 * On ASICs without firmware autoload support this function will return 787 * immediately. 788 * 789 * Return: 790 * DMUB_STATUS_OK - success 791 * DMUB_STATUS_TIMEOUT - wait for phy init timed out 792 * DMUB_STATUS_INVALID - unspecified error 793 */ 794 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 795 uint32_t timeout_us); 796 797 /** 798 * dmub_srv_wait_for_phy_init() - Waits for DMUB PHY init to complete 799 * @dmub: the dmub service 800 * @timeout_us: the maximum number of microseconds to wait 801 * 802 * Waits until the PHY has been initialized by the DMUB. The maximum 803 * wait time is given in microseconds to prevent spinning forever. 804 * 805 * On ASICs without PHY init support this function will return 806 * immediately. 807 * 808 * Return: 809 * DMUB_STATUS_OK - success 810 * DMUB_STATUS_TIMEOUT - wait for phy init timed out 811 * DMUB_STATUS_INVALID - unspecified error 812 */ 813 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 814 uint32_t timeout_us); 815 816 /** 817 * dmub_srv_wait_for_pending() - Re-entrant wait for messages currently pending 818 * @dmub: the dmub service 819 * @timeout_us: the maximum number of microseconds to wait 820 * 821 * Waits until the commands queued prior to this call are complete. 822 * If interfaces remain busy due to additional work being submitted 823 * concurrently, this function will not continue to wait. 824 * 825 * Return: 826 * DMUB_STATUS_OK - success 827 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 828 * DMUB_STATUS_INVALID - unspecified error 829 */ 830 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 831 uint32_t timeout_us); 832 833 /** 834 * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle 835 * @dmub: the dmub service 836 * @timeout_us: the maximum number of microseconds to wait 837 * 838 * Waits until the DMUB buffer is empty and all commands have 839 * finished processing. The maximum wait time is given in 840 * microseconds to prevent spinning forever. 841 * 842 * Return: 843 * DMUB_STATUS_OK - success 844 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 845 * DMUB_STATUS_INVALID - unspecified error 846 */ 847 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 848 uint32_t timeout_us); 849 850 /** 851 * dmub_srv_send_gpint_command() - Sends a GPINT based command. 852 * @dmub: the dmub service 853 * @command_code: the command code to send 854 * @param: the command parameter to send 855 * @timeout_us: the maximum number of microseconds to wait 856 * 857 * Sends a command via the general purpose interrupt (GPINT). 858 * Waits for the number of microseconds specified by timeout_us 859 * for the command ACK before returning. 860 * 861 * Can be called after software initialization. 862 * 863 * Return: 864 * DMUB_STATUS_OK - success 865 * DMUB_STATUS_TIMEOUT - wait for ACK timed out 866 * DMUB_STATUS_INVALID - unspecified error 867 */ 868 enum dmub_status 869 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 870 enum dmub_gpint_command command_code, 871 uint16_t param, uint32_t timeout_us); 872 873 /** 874 * dmub_srv_get_gpint_response() - Queries the GPINT response. 875 * @dmub: the dmub service 876 * @response: the response for the last GPINT 877 * 878 * Returns the response code for the last GPINT interrupt. 879 * 880 * Can be called after software initialization. 881 * 882 * Return: 883 * DMUB_STATUS_OK - success 884 * DMUB_STATUS_INVALID - unspecified error 885 */ 886 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 887 uint32_t *response); 888 889 /** 890 * dmub_srv_get_gpint_dataout() - Queries the GPINT DATAOUT. 891 * @dmub: the dmub service 892 * @dataout: the data for the GPINT DATAOUT 893 * 894 * Returns the response code for the last GPINT DATAOUT interrupt. 895 * 896 * Can be called after software initialization. 897 * 898 * Return: 899 * DMUB_STATUS_OK - success 900 * DMUB_STATUS_INVALID - unspecified error 901 */ 902 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 903 uint32_t *dataout); 904 905 /** 906 * dmub_flush_buffer_mem() - Read back entire frame buffer region. 907 * This ensures that the write from x86 has been flushed and will not 908 * hang the DMCUB. 909 * @fb: frame buffer to flush 910 * 911 * Can be called after software initialization. 912 */ 913 void dmub_flush_buffer_mem(const struct dmub_fb *fb); 914 915 /** 916 * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits. 917 * 918 * @dmub: the dmub service 919 * @status: out pointer for firmware status 920 * 921 * Return: 922 * DMUB_STATUS_OK - success 923 * DMUB_STATUS_INVALID - unspecified error, unsupported 924 */ 925 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 926 union dmub_fw_boot_status *status); 927 928 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 929 union dmub_fw_boot_options *option); 930 931 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 932 bool skip); 933 934 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry); 935 936 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub); 937 938 bool dmub_srv_should_detect(struct dmub_srv *dmub); 939 940 /** 941 * dmub_srv_send_inbox0_cmd() - Send command to DMUB using INBOX0 942 * @dmub: the dmub service 943 * @data: the data to be sent in the INBOX0 command 944 * 945 * Send command by writing directly to INBOX0 WPTR 946 * 947 * Return: 948 * DMUB_STATUS_OK - success 949 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 950 */ 951 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 952 953 /** 954 * dmub_srv_wait_for_inbox0_ack() - wait for DMUB to ACK INBOX0 command 955 * @dmub: the dmub service 956 * @timeout_us: the maximum number of microseconds to wait 957 * 958 * Wait for DMUB to ACK the INBOX0 message 959 * 960 * Return: 961 * DMUB_STATUS_OK - success 962 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 963 * DMUB_STATUS_TIMEOUT - wait for ack timed out 964 */ 965 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us); 966 967 /** 968 * dmub_srv_wait_for_inbox0_ack() - clear ACK register for INBOX0 969 * @dmub: the dmub service 970 * 971 * Clear ACK register for INBOX0 972 * 973 * Return: 974 * DMUB_STATUS_OK - success 975 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 976 */ 977 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub); 978 979 /** 980 * dmub_srv_subvp_save_surf_addr() - Save primary and meta address for subvp on each flip 981 * @dmub: The dmub service 982 * @addr: The surface address to be programmed on the current flip 983 * @subvp_index: Index of subvp pipe, indicates which subvp pipe the address should be saved for 984 * 985 * Function to save the surface flip addr into scratch registers. This is to fix a race condition 986 * between FW and driver reading / writing to the surface address at the same time. This is 987 * required because there is no EARLIEST_IN_USE_META. 988 * 989 * Return: 990 * void 991 */ 992 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 993 994 /** 995 * dmub_srv_set_power_state() - Track DC power state in dmub_srv 996 * @dmub: The dmub service 997 * @power_state: DC power state setting 998 * 999 * Store DC power state in dmub_srv. If dmub_srv is in D3, then don't send messages to DMUB 1000 * 1001 * Return: 1002 * void 1003 */ 1004 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state); 1005 1006 /** 1007 * dmub_srv_reg_cmd_execute() - Executes provided command to the dmub 1008 * @dmub: the dmub service 1009 * @cmd: the command packet to be executed 1010 * 1011 * Executes a single command for the dmub. 1012 * 1013 * Return: 1014 * DMUB_STATUS_OK - success 1015 * DMUB_STATUS_INVALID - unspecified error 1016 */ 1017 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 1018 1019 1020 /** 1021 * dmub_srv_cmd_get_response() - Copies return data for command into buffer 1022 * @dmub: the dmub service 1023 * @cmd_rsp: response buffer 1024 * 1025 * Copies return data for command into buffer 1026 */ 1027 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1028 union dmub_rb_cmd *cmd_rsp); 1029 1030 /** 1031 * dmub_srv_sync_inboxes() - Sync inbox state 1032 * @dmub: the dmub service 1033 * 1034 * Sync inbox state 1035 * 1036 * Return: 1037 * DMUB_STATUS_OK - success 1038 * DMUB_STATUS_INVALID - unspecified error 1039 */ 1040 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub); 1041 1042 /** 1043 * dmub_srv_wait_for_inbox_free() - Waits for space in the DMUB inbox to free up 1044 * @dmub: the dmub service 1045 * @timeout_us: the maximum number of microseconds to wait 1046 * @num_free_required: number of free entries required 1047 * 1048 * Waits until the DMUB buffer is freed to the specified number. 1049 * The maximum wait time is given in microseconds to prevent spinning 1050 * forever. 1051 * 1052 * Return: 1053 * DMUB_STATUS_OK - success 1054 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 1055 * DMUB_STATUS_INVALID - unspecified error 1056 */ 1057 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1058 uint32_t timeout_us, 1059 uint32_t num_free_required); 1060 1061 /** 1062 * dmub_srv_update_inbox_status() - Updates pending status for inbox & reg inbox0 1063 * @dmub: the dmub service 1064 * 1065 * Return: 1066 * DMUB_STATUS_OK - success 1067 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 1068 * DMUB_STATUS_HW_FAILURE - issue with HW programming 1069 * DMUB_STATUS_INVALID - unspecified error 1070 */ 1071 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub); 1072 1073 #endif /* _DMUB_SRV_H_ */ 1074