1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns timing validation against various link limitations. (ex. 28 * link bandwidth, receiver capability or our hardware capability) It also 29 * provides helper functions exposing bandwidth formulas used in validation. 30 */ 31 #include "link_validation.h" 32 #include "protocols/link_dp_capability.h" 33 #include "protocols/link_dp_dpia_bw.h" 34 #include "protocols/link_hdmi_frl.h" 35 #include "resource.h" 36 37 #define DC_LOGGER_INIT(logger) 38 39 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) 40 { 41 42 uint32_t pxl_clk = timing->pix_clk_100hz; 43 44 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 45 pxl_clk /= 2; 46 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 47 pxl_clk = pxl_clk * 2 / 3; 48 49 if (timing->display_color_depth == COLOR_DEPTH_101010) 50 pxl_clk = pxl_clk * 10 / 8; 51 else if (timing->display_color_depth == COLOR_DEPTH_121212) 52 pxl_clk = pxl_clk * 12 / 8; 53 54 return pxl_clk; 55 } 56 57 static bool dp_active_dongle_validate_timing( 58 const struct dc_crtc_timing *timing, 59 const struct dpcd_caps *dpcd_caps) 60 { 61 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps; 62 63 switch (dpcd_caps->dongle_type) { 64 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 65 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 66 case DISPLAY_DONGLE_DP_DVI_DONGLE: 67 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) 68 return true; 69 else 70 return false; 71 default: 72 break; 73 } 74 75 if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER && 76 dongle_caps->extendedCapValid == true) { 77 /* Check Pixel Encoding */ 78 switch (timing->pixel_encoding) { 79 case PIXEL_ENCODING_RGB: 80 case PIXEL_ENCODING_YCBCR444: 81 break; 82 case PIXEL_ENCODING_YCBCR422: 83 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through) 84 return false; 85 break; 86 case PIXEL_ENCODING_YCBCR420: 87 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through) 88 return false; 89 break; 90 case PIXEL_ENCODING_UNDEFINED: 91 /* These color depths are currently not supported */ 92 ASSERT(false); 93 break; 94 default: 95 /* Invalid Pixel Encoding*/ 96 return false; 97 } 98 99 switch (timing->display_color_depth) { 100 case COLOR_DEPTH_666: 101 case COLOR_DEPTH_888: 102 /*888 and 666 should always be supported*/ 103 break; 104 case COLOR_DEPTH_101010: 105 if (dongle_caps->dp_hdmi_max_bpc < 10) 106 return false; 107 break; 108 case COLOR_DEPTH_121212: 109 if (dongle_caps->dp_hdmi_max_bpc < 12) 110 return false; 111 break; 112 case COLOR_DEPTH_UNDEFINED: 113 /* These color depths are currently not supported */ 114 ASSERT(false); 115 break; 116 case COLOR_DEPTH_141414: 117 case COLOR_DEPTH_161616: 118 default: 119 /* These color depths are currently not supported */ 120 return false; 121 } 122 123 /* Check 3D format */ 124 switch (timing->timing_3d_format) { 125 case TIMING_3D_FORMAT_NONE: 126 case TIMING_3D_FORMAT_FRAME_ALTERNATE: 127 /*Only frame alternate 3D is supported on active dongle*/ 128 break; 129 default: 130 /*other 3D formats are not supported due to bad infoframe translation */ 131 return false; 132 } 133 134 if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter 135 struct dc_crtc_timing outputTiming = *timing; 136 137 if (timing->flags.DSC && !timing->dsc_cfg.is_frl) 138 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */ 139 outputTiming.flags.DSC = 0; 140 if (dc_bandwidth_in_kbps_from_timing(&outputTiming, DC_LINK_ENCODING_HDMI_FRL) > 141 dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps) 142 return false; 143 } else { // DP to HDMI TMDS converter 144 if (get_tmds_output_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10)) 145 return false; 146 } 147 } 148 149 if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 && 150 dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 && 151 dongle_caps->dfp_cap_ext.supported) { 152 153 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000)) 154 return false; 155 156 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable) 157 return false; 158 159 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable) 160 return false; 161 162 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) { 163 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb) 164 return false; 165 if (timing->display_color_depth == COLOR_DEPTH_666 && 166 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc) 167 return false; 168 else if (timing->display_color_depth == COLOR_DEPTH_888 && 169 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc) 170 return false; 171 else if (timing->display_color_depth == COLOR_DEPTH_101010 && 172 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc) 173 return false; 174 else if (timing->display_color_depth == COLOR_DEPTH_121212 && 175 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc) 176 return false; 177 else if (timing->display_color_depth == COLOR_DEPTH_161616 && 178 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc) 179 return false; 180 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) { 181 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb) 182 return false; 183 if (timing->display_color_depth == COLOR_DEPTH_888 && 184 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc) 185 return false; 186 else if (timing->display_color_depth == COLOR_DEPTH_101010 && 187 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc) 188 return false; 189 else if (timing->display_color_depth == COLOR_DEPTH_121212 && 190 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc) 191 return false; 192 else if (timing->display_color_depth == COLOR_DEPTH_161616 && 193 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc) 194 return false; 195 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 196 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb) 197 return false; 198 if (timing->display_color_depth == COLOR_DEPTH_888 && 199 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc) 200 return false; 201 else if (timing->display_color_depth == COLOR_DEPTH_101010 && 202 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc) 203 return false; 204 else if (timing->display_color_depth == COLOR_DEPTH_121212 && 205 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc) 206 return false; 207 else if (timing->display_color_depth == COLOR_DEPTH_161616 && 208 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc) 209 return false; 210 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) { 211 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb) 212 return false; 213 if (timing->display_color_depth == COLOR_DEPTH_888 && 214 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc) 215 return false; 216 else if (timing->display_color_depth == COLOR_DEPTH_101010 && 217 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc) 218 return false; 219 else if (timing->display_color_depth == COLOR_DEPTH_121212 && 220 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc) 221 return false; 222 else if (timing->display_color_depth == COLOR_DEPTH_161616 && 223 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc) 224 return false; 225 } 226 } 227 228 return true; 229 } 230 231 uint32_t dp_link_bandwidth_kbps( 232 const struct dc_link *link, 233 const struct dc_link_settings *link_settings) 234 { 235 uint32_t total_data_bw_efficiency_x10000 = 0; 236 uint32_t link_rate_per_lane_kbps = 0; 237 238 switch (link_dp_get_encoding_format(link_settings)) { 239 case DP_8b_10b_ENCODING: 240 /* For 8b/10b encoding: 241 * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane. 242 * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported. 243 */ 244 link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE; 245 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000; 246 if (dp_should_enable_fec(link)) { 247 total_data_bw_efficiency_x10000 /= 100; 248 total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100; 249 } 250 break; 251 case DP_128b_132b_ENCODING: 252 /* For 128b/132b encoding: 253 * link rate is defined in the unit of 10mbps per lane. 254 * total data bandwidth efficiency is always 96.71%. 255 */ 256 link_rate_per_lane_kbps = link_settings->link_rate * 10000; 257 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000; 258 break; 259 default: 260 break; 261 } 262 263 /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */ 264 return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000; 265 } 266 267 uint32_t frl_link_bandwidth_kbps(enum hdmi_frl_link_rate link_rate) 268 { 269 switch (link_rate) { 270 case HDMI_FRL_LINK_RATE_3GBPS: 271 return 9000000; 272 case HDMI_FRL_LINK_RATE_6GBPS: 273 return 18000000; 274 case HDMI_FRL_LINK_RATE_6GBPS_4LANE: 275 return 24000000; 276 case HDMI_FRL_LINK_RATE_8GBPS: 277 return 32000000; 278 case HDMI_FRL_LINK_RATE_10GBPS: 279 return 40000000; 280 case HDMI_FRL_LINK_RATE_12GBPS: 281 return 48000000; 282 case HDMI_FRL_LINK_RATE_16GBPS: 283 return 64000000; 284 case HDMI_FRL_LINK_RATE_20GBPS: 285 return 80000000; 286 case HDMI_FRL_LINK_RATE_24GBPS: 287 return 96000000; 288 default: 289 return 0; 290 } 291 } 292 293 bool frl_capacity_computations_common(struct frl_cap_chk_params_fixed31_32 *params, 294 struct frl_cap_chk_intermediates_fixed31_32 *inter) 295 { 296 struct fixed31_32 audio_bw_reserve = dc_fixpt_from_int((params->compressed ? 192000 : 0)); 297 struct fixed31_32 pixel_rate_tolerance = dc_fixpt_div_int(dc_fixpt_from_int(5), 1000); 298 struct fixed31_32 max_audio_tol_rate; 299 struct fixed31_32 overhead_m; 300 301 inter->c_frl_sb = 4 * C_FRL_CB + params->lanes; 302 inter->overhead_sb = dc_fixpt_div_int(dc_fixpt_from_int(params->lanes), inter->c_frl_sb); 303 inter->overhead_rs = dc_fixpt_div_int(dc_fixpt_from_int(32), inter->c_frl_sb); 304 inter->overhead_map = dc_fixpt_div_int(dc_fixpt_from_int(25), (inter->c_frl_sb * 10)); 305 306 inter->overhead_min = dc_fixpt_add(inter->overhead_sb, inter->overhead_rs); 307 inter->overhead_min = dc_fixpt_add(inter->overhead_min, inter->overhead_map); 308 overhead_m = dc_fixpt_div_int(dc_fixpt_from_int(3), 1000); 309 inter->overhead_max = dc_fixpt_add(inter->overhead_min, overhead_m); 310 311 pixel_rate_tolerance = dc_fixpt_add_int(pixel_rate_tolerance, 1); 312 313 inter->f_pixel_clock_max = dc_fixpt_mul(params->f_pixel_clock_nominal, pixel_rate_tolerance); 314 inter->t_line = dc_fixpt_div(dc_fixpt_from_int(params->h_active + params->h_blank), inter->f_pixel_clock_max); 315 inter->r_bit_min = dc_fixpt_div_int(dc_fixpt_from_int(TOLERANCE_FRL_BIT), 1000000); 316 inter->r_bit_min = dc_fixpt_sub(dc_fixpt_from_int(1), inter->r_bit_min); 317 inter->r_bit_min = dc_fixpt_mul(params->r_bit_nominal, inter->r_bit_min); 318 319 inter->r_frl_char_min = dc_fixpt_div_int(inter->r_bit_min, 18); 320 inter->c_frl_line = dc_fixpt_mul(inter->t_line, inter->r_frl_char_min); 321 inter->c_frl_line = dc_fixpt_mul_int(inter->c_frl_line, params->lanes); 322 323 switch (params->audio_packet_type) { 324 case 0x02: 325 if (params->layout == 0) 326 inter->ap = dc_fixpt_div_int(dc_fixpt_from_int(25), 100); 327 else if (params->layout == 1) 328 inter->ap = dc_fixpt_from_int(1); 329 break; 330 case 0x08: 331 inter->ap = dc_fixpt_div_int(dc_fixpt_from_int(25), 100); 332 break; 333 case 0x09: 334 inter->ap = dc_fixpt_from_int(1); 335 break; 336 case 0x07: 337 case 0x0e: 338 case 0x0f: 339 case 0x0b: 340 case 0x0c: 341 /* Unsupported audio format */ 342 return false; 343 default: 344 inter->ap = dc_fixpt_from_int(0); 345 } 346 347 inter->r_ap = dc_fixpt_max(audio_bw_reserve, dc_fixpt_mul(params->f_audio, inter->ap)); 348 inter->r_ap = dc_fixpt_add(inter->r_ap, dc_fixpt_from_int(2 * ACR_RATE_MAX)); 349 max_audio_tol_rate = dc_fixpt_div_int(dc_fixpt_from_int(TOLERANCE_AUDIO_CLOCK), 1000000); 350 max_audio_tol_rate = dc_fixpt_add(dc_fixpt_from_int(1), max_audio_tol_rate); 351 inter->r_ap = dc_fixpt_mul(inter->r_ap, max_audio_tol_rate); 352 353 inter->avg_audio_packets_line = dc_fixpt_mul(inter->r_ap, inter->t_line); 354 inter->avg_audio_packets_line = dc_fixpt_div_int(inter->avg_audio_packets_line, 1000000); 355 inter->audio_packets_line = dc_fixpt_ceil(inter->avg_audio_packets_line); 356 357 inter->blank_audio_min = 32 + 32 * inter->audio_packets_line; 358 359 params->borrow_params.audio_packets_line = inter->audio_packets_line; 360 361 return true; 362 } 363 364 bool frl_capacity_computations_uncompressed_video(struct frl_cap_chk_params_fixed31_32 *params, 365 struct frl_cap_chk_intermediates_fixed31_32 *inter) 366 { 367 bool res; 368 int k_420; 369 struct fixed31_32 k_cd; 370 struct fixed31_32 c_frl_free; 371 int c_frl_free_int; 372 int c_frl_rc_margin; 373 struct fixed31_32 c_frl_rc_savings; 374 int c_frl_rc_savings_int; 375 int bpp; 376 struct fixed31_32 bytes_line; 377 int tb_active; 378 int tb_blank; 379 struct fixed31_32 f_tb_average; 380 struct fixed31_32 t_active_ref; 381 struct fixed31_32 t_blank_ref; 382 struct fixed31_32 t_active_min; 383 struct fixed31_32 t_blank_min; 384 int c_frl_actual_payload; 385 struct fixed31_32 utilization; 386 387 res = frl_capacity_computations_common(params, inter); 388 if (res != true) 389 return res; 390 391 k_420 = params->pixel_encoding == HDMI_FRL_PIXEL_ENCODING_420 ? 2 : 1; 392 if (params->pixel_encoding == HDMI_FRL_PIXEL_ENCODING_422) 393 k_cd = dc_fixpt_from_int(1); 394 else 395 k_cd = dc_fixpt_div_int(dc_fixpt_from_int(params->bpc), 8); 396 397 c_frl_free = dc_fixpt_div_int(dc_fixpt_mul_int(k_cd, params->h_blank), k_420); 398 c_frl_free = dc_fixpt_sub_int(c_frl_free, 32 * (1 + inter->audio_packets_line) + 7); 399 c_frl_free = dc_fixpt_max(c_frl_free, dc_fixpt_from_int(0)); 400 c_frl_free_int = dc_fixpt_ceil(c_frl_free); 401 c_frl_rc_margin = 4; 402 c_frl_rc_savings = dc_fixpt_mul_int(dc_fixpt_div_int(dc_fixpt_from_int(7), 8), c_frl_free_int); 403 c_frl_rc_savings = dc_fixpt_sub_int(c_frl_rc_savings, c_frl_rc_margin); 404 c_frl_rc_savings_int = dc_fixpt_floor(dc_fixpt_max(c_frl_rc_savings, dc_fixpt_from_int(0))); 405 406 bpp = dc_fixpt_ceil(dc_fixpt_mul_int(dc_fixpt_div_int(k_cd, k_420), 24)); 407 bytes_line = dc_fixpt_div_int(dc_fixpt_from_int(bpp * params->h_active), 8); 408 tb_active = dc_fixpt_ceil(dc_fixpt_div_int(bytes_line, 3)); 409 tb_blank = dc_fixpt_ceil(dc_fixpt_div_int(dc_fixpt_mul_int(k_cd, params->h_blank), k_420)); 410 411 if (!(inter->blank_audio_min <= tb_blank)) { 412 return false; 413 } 414 415 f_tb_average = dc_fixpt_div_int(inter->f_pixel_clock_max, (params->h_active + params->h_blank)); 416 f_tb_average = dc_fixpt_mul_int(f_tb_average, (tb_active + tb_blank)); 417 418 t_active_ref = dc_fixpt_div(dc_fixpt_from_int(params->h_active), dc_fixpt_from_int(params->h_active + params->h_blank)); 419 t_active_ref = dc_fixpt_mul(inter->t_line, t_active_ref); 420 421 t_blank_ref = dc_fixpt_div(dc_fixpt_from_int(params->h_blank), dc_fixpt_from_int(params->h_active + params->h_blank)); 422 t_blank_ref = dc_fixpt_mul(inter->t_line, t_blank_ref); 423 424 t_active_min = dc_fixpt_sub(dc_fixpt_from_int(1), inter->overhead_max); 425 t_active_min = dc_fixpt_mul(t_active_min, inter->r_frl_char_min); 426 t_active_min = dc_fixpt_mul_int(t_active_min, params->lanes); 427 t_active_min = dc_fixpt_div_int(t_active_min, 1000); 428 t_blank_min = t_active_min; 429 430 t_active_min = dc_fixpt_div(dc_fixpt_mul_int(dc_fixpt_div(dc_fixpt_from_int(3), dc_fixpt_from_int(2)), tb_active), t_active_min); 431 432 t_blank_min = dc_fixpt_div(dc_fixpt_from_int(tb_blank), t_blank_min); 433 434 if (dc_fixpt_le(t_active_min, t_active_ref) && dc_fixpt_le(t_blank_min, t_blank_ref)) { 435 params->borrow_params.borrow_mode = FRL_BORROW_MODE_NONE; 436 } else if (dc_fixpt_lt(t_active_ref, t_active_min) && dc_fixpt_le(t_blank_min, t_blank_ref)) { 437 params->borrow_params.borrow_mode = FRL_BORROW_MODE_FROM_BLANK; 438 } else { 439 return false; 440 } 441 442 443 c_frl_actual_payload = dc_fixpt_ceil(dc_fixpt_mul_int(dc_fixpt_div(dc_fixpt_from_int(3), dc_fixpt_from_int(2)), tb_active)) + tb_blank - c_frl_rc_savings_int; 444 445 utilization = dc_fixpt_div(dc_fixpt_from_int(c_frl_actual_payload), inter->c_frl_line); 446 utilization = dc_fixpt_mul_int(utilization, 1000); 447 448 inter->margin = dc_fixpt_sub(dc_fixpt_from_int(1), dc_fixpt_add(utilization, inter->overhead_max)); 449 450 if (dc_fixpt_lt(inter->margin, dc_fixpt_from_int(0)) && dc_fixpt_lt(dc_fixpt_from_fraction(1, 100), dc_fixpt_abs(inter->margin))) 451 return false; 452 453 return true; 454 } 455 456 static uint32_t dp_get_timing_bandwidth_kbps( 457 const struct dc_crtc_timing *timing, 458 const struct dc_link *link) 459 { 460 return dc_bandwidth_in_kbps_from_timing(timing, 461 dc_link_get_highest_encoding_format(link)); 462 } 463 464 static bool dp_validate_mode_timing( 465 struct dc_link *link, 466 const struct dc_crtc_timing *timing) 467 { 468 uint32_t req_bw; 469 uint32_t max_bw; 470 471 const struct dc_link_settings *link_setting; 472 473 /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */ 474 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && 475 !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && 476 dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL) 477 return false; 478 479 /*always DP fail safe mode*/ 480 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 && 481 timing->h_addressable == (uint32_t) 640 && 482 timing->v_addressable == (uint32_t) 480) 483 return true; 484 485 link_setting = dp_get_verified_link_cap(link); 486 487 /* TODO: DYNAMIC_VALIDATION needs to be implemented */ 488 /*if (flags.DYNAMIC_VALIDATION == 1 && 489 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) 490 link_setting = &link->verified_link_cap; 491 */ 492 493 req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link)); 494 max_bw = dp_link_bandwidth_kbps(link, link_setting); 495 uint32_t max_uncompressed_pixel_rate_100hz = 496 link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000U; 497 498 bool is_max_uncompressed_pixel_rate_exceeded = link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.valid && 499 timing->pix_clk_100hz > max_uncompressed_pixel_rate_100hz; 500 501 if (is_max_uncompressed_pixel_rate_exceeded && !timing->flags.DSC) { 502 return false; 503 } 504 505 if (req_bw <= max_bw) { 506 /* remember the biggest mode here, during 507 * initial link training (to get 508 * verified_link_cap), LS sends event about 509 * cannot train at reported cap to upper 510 * layer and upper layer will re-enumerate modes. 511 * this is not necessary if the lower 512 * verified_link_cap is enough to drive 513 * all the modes */ 514 515 /* TODO: DYNAMIC_VALIDATION needs to be implemented */ 516 /* if (flags.DYNAMIC_VALIDATION == 1) 517 dpsst->max_req_bw_for_verified_linkcap = dal_max( 518 dpsst->max_req_bw_for_verified_linkcap, req_bw); */ 519 return true; 520 } else 521 return false; 522 } 523 524 bool frl_validate_mode_timing( 525 struct dc_link *link, 526 const struct dc_crtc_timing *timing, 527 struct dc_hdmi_frl_link_settings *frl_link_settings) 528 { 529 uint32_t req_bw; 530 uint32_t max_bw; 531 enum engine_id hpo_eng_id; 532 unsigned int i; 533 unsigned int hpo_frl_stream_enc_index = 0; 534 bool frl_output_valid = false; 535 536 if (!link) 537 return false; 538 if (!link->local_sink) 539 return false; 540 541 req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link)); 542 max_bw = frl_link_bandwidth_kbps(frl_link_settings->frl_link_rate); 543 544 /* Use Engine ID to determine which hpo stream 545 * encoder should be used. 546 */ 547 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) 548 frl_output_valid = true; 549 else { 550 struct audio_check audio_frl_check = {0}; 551 struct audio_info audio_info = {0}; 552 hpo_eng_id = ENGINE_ID_HPO_0; 553 554 for (i = 0; i < link->dc->res_pool->hpo_frl_stream_enc_count; i++) { 555 if (link->dc->res_pool->hpo_frl_stream_enc[i]->id == hpo_eng_id) { 556 hpo_frl_stream_enc_index = i; 557 break; 558 } 559 } 560 /*add audio check*/ 561 for (i = 0; i < (link->local_sink->edid_caps.audio_mode_count); i++) { 562 audio_info.modes[i].channel_count = link->local_sink->edid_caps.audio_modes[i].channel_count; 563 audio_info.modes[i].format_code = link->local_sink->edid_caps.audio_modes[i].format_code; 564 audio_info.modes[i].sample_rates.all = link->local_sink->edid_caps.audio_modes[i].sample_rate; 565 audio_info.modes[i].sample_size = link->local_sink->edid_caps.audio_modes[i].sample_size; 566 } 567 audio_info.mode_count = link->local_sink->edid_caps.audio_mode_count; 568 get_audio_check(&audio_info, &audio_frl_check); 569 570 frl_output_valid = 571 link->dc->res_pool->hpo_frl_stream_enc[hpo_frl_stream_enc_index]->funcs->validate_hdmi_frl_output( 572 link->dc->res_pool->hpo_frl_stream_enc[hpo_frl_stream_enc_index], 573 timing, &audio_frl_check, 574 frl_link_settings, 575 link->local_sink->edid_caps.frl_dsc_max_frl_rate); 576 } 577 578 if (req_bw <= max_bw && frl_output_valid) { 579 /* remember the biggest mode here, during 580 * initial link training (to get 581 * verified_link_cap), LS sends event about 582 * cannot train at reported cap to upper 583 * layer and upper layer will re-enumerate modes. 584 * this is not necessary if the lower 585 * verified_link_cap is enough to drive 586 * all the modes 587 */ 588 589 /* TODO: DYNAMIC_VALIDATION needs to be implemented */ 590 /* if (flags.DYNAMIC_VALIDATION == 1) 591 * dpsst->max_req_bw_for_verified_linkcap = dal_max( 592 * dpsst->max_req_bw_for_verified_linkcap, req_bw); 593 */ 594 return true; 595 } else if (frl_output_valid && timing->dsc_cfg.is_frl) { 596 /* HDMI DSC calculation is validated within frl_output_valid 597 * and req_bw may exceed max_bw 598 */ 599 return true; 600 } else 601 return false; 602 } 603 604 enum dc_status link_validate_mode_timing( 605 const struct dc_stream_state *stream, 606 struct dc_link *link, 607 const struct dc_crtc_timing *timing) 608 { 609 uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10; 610 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 611 612 /* A hack to avoid failing any modes for EDID override feature on 613 * topology change such as lower quality cable for DP or different dongle 614 */ 615 if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL) 616 return DC_OK; 617 618 /* If DSC is supported, but native 422 DSC is not supported, 619 * HDMI 2.1a specification requires that all 422 format be disabled (7.7.1) 620 */ 621 if (dc_is_hdmi_signal(stream->signal)) { 622 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && link->dc->config.no_native422_support) { 623 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 624 } 625 } 626 627 /* Passive Dongle */ 628 if (max_pix_clk != 0 && get_tmds_output_pixel_clock_100hz(timing) > max_pix_clk) 629 return DC_EXCEED_DONGLE_CAP; 630 631 /* Active Dongle*/ 632 if (!dp_active_dongle_validate_timing(timing, dpcd_caps)) 633 return DC_EXCEED_DONGLE_CAP; 634 635 switch (stream->signal) { 636 case SIGNAL_TYPE_EDP: 637 case SIGNAL_TYPE_DISPLAY_PORT: 638 if (!dp_validate_mode_timing( 639 link, 640 timing)) 641 return DC_NO_DP_LINK_BANDWIDTH; 642 break; 643 644 case SIGNAL_TYPE_HDMI_FRL: 645 { 646 uint32_t pxl_clk_mhz; 647 /* Limit pixel clock to DTBCLK Limit (Base Pix > 4 * DTBCLK) */ 648 pxl_clk_mhz = (timing->pix_clk_100hz + 10000 - 1) / 10000 ; 649 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 650 pxl_clk_mhz /= 2; 651 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 652 pxl_clk_mhz = pxl_clk_mhz * 2 / 3; 653 if (pxl_clk_mhz > DTBCLK_LIMIT && link->ctx->dce_version < DCN_VERSION_3_1) 654 return DC_NO_HDMI_FRL_LINK_BANDWIDTH; 655 } 656 657 if (!frl_validate_mode_timing( 658 link, 659 timing, 660 hdmi_frl_get_verified_link_cap(link))) 661 return DC_NO_HDMI_FRL_LINK_BANDWIDTH; 662 break; 663 default: 664 break; 665 } 666 667 return DC_OK; 668 } 669 670 static const struct dc_tunnel_settings *get_dp_tunnel_settings(const struct dc_state *context, 671 const struct dc_stream_state *stream) 672 { 673 int i; 674 const struct dc_tunnel_settings *dp_tunnel_settings = NULL; 675 676 for (i = 0; i < MAX_PIPES; i++) { 677 if (context->res_ctx.pipe_ctx[i].stream && (context->res_ctx.pipe_ctx[i].stream == stream)) { 678 dp_tunnel_settings = &context->res_ctx.pipe_ctx[i].link_config.dp_tunnel_settings; 679 break; 680 } 681 } 682 683 return dp_tunnel_settings; 684 } 685 686 /* 687 * Calculates the DP tunneling bandwidth required for the stream timing 688 * and aggregates the stream bandwidth for the respective DP tunneling link 689 * 690 * return: dc_status 691 */ 692 enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const struct dc_state *new_ctx) 693 { 694 (void)dc; 695 struct dc_validation_dpia_set dpia_link_sets[MAX_DPIA_NUM] = { 0 }; 696 uint8_t link_count = 0; 697 enum dc_status result = DC_OK; 698 699 // Iterate through streams in the new context 700 for (uint8_t i = 0; (i < MAX_PIPES && i < new_ctx->stream_count); i++) { 701 const struct dc_stream_state *stream = new_ctx->streams[i]; 702 const struct dc_link *link; 703 const struct dc_tunnel_settings *dp_tunnel_settings; 704 uint32_t timing_bw; 705 706 if (stream == NULL) 707 continue; 708 709 link = stream->link; 710 711 if (!(link && (stream->signal == SIGNAL_TYPE_DISPLAY_PORT 712 || stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST))) 713 continue; 714 715 if ((link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) && (link->hpd_status == false)) 716 continue; 717 718 dp_tunnel_settings = get_dp_tunnel_settings(new_ctx, stream); 719 720 if ((dp_tunnel_settings == NULL) || (dp_tunnel_settings->should_use_dp_bw_allocation == false)) 721 continue; 722 723 timing_bw = dp_get_timing_bandwidth_kbps(&stream->timing, link); 724 725 // Find an existing entry for this 'link' in 'dpia_link_sets' 726 for (uint8_t j = 0; j < MAX_DPIA_NUM; j++) { 727 bool is_new_slot = false; 728 729 if (dpia_link_sets[j].link == NULL) { 730 is_new_slot = true; 731 link_count++; 732 dpia_link_sets[j].required_bw = 0; 733 dpia_link_sets[j].link = link; 734 } 735 736 if (is_new_slot || (dpia_link_sets[j].link == link)) { 737 dpia_link_sets[j].tunnel_settings = dp_tunnel_settings; 738 dpia_link_sets[j].required_bw += timing_bw; 739 break; 740 } 741 } 742 } 743 744 if (link_count && link_dpia_validate_dp_tunnel_bandwidth(dpia_link_sets, link_count) == false) 745 result = DC_FAIL_DP_TUNNEL_BW_VALIDATE; 746 747 return result; 748 } 749 750 struct dp_audio_layout_config { 751 uint8_t layouts_per_sample_denom; 752 uint8_t symbols_per_layout; 753 uint8_t max_layouts_per_audio_sdp; 754 }; 755 756 static void get_audio_layout_config( 757 uint32_t channel_count, 758 enum dp_link_encoding encoding, 759 struct dp_audio_layout_config *output) 760 { 761 memset(output, 0, sizeof(struct dp_audio_layout_config)); 762 763 /* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP, 764 * with each layout being the same size (8ch layout). 765 */ 766 if (encoding == DP_8b_10b_ENCODING) { 767 if (channel_count == 2) { 768 output->layouts_per_sample_denom = 4; 769 output->symbols_per_layout = 40; 770 output->max_layouts_per_audio_sdp = 1; 771 } else if (channel_count == 8 || channel_count == 6) { 772 output->layouts_per_sample_denom = 1; 773 output->symbols_per_layout = 40; 774 output->max_layouts_per_audio_sdp = 1; 775 } 776 } else if (encoding == DP_128b_132b_ENCODING) { 777 if (channel_count == 2) { 778 output->layouts_per_sample_denom = 4; 779 output->symbols_per_layout = 10; 780 output->max_layouts_per_audio_sdp = 1; 781 } else if (channel_count == 8 || channel_count == 6) { 782 output->layouts_per_sample_denom = 1; 783 output->symbols_per_layout = 10; 784 output->max_layouts_per_audio_sdp = 1; 785 } 786 } 787 } 788 789 static uint32_t get_av_stream_map_lane_count( 790 enum dp_link_encoding encoding, 791 enum dc_lane_count lane_count, 792 bool is_mst) 793 { 794 uint32_t av_stream_map_lane_count = 0; 795 796 if (encoding == DP_8b_10b_ENCODING) { 797 if (!is_mst) 798 av_stream_map_lane_count = lane_count; 799 else 800 av_stream_map_lane_count = 4; 801 } else if (encoding == DP_128b_132b_ENCODING) { 802 av_stream_map_lane_count = 4; 803 } 804 805 ASSERT(av_stream_map_lane_count != 0); 806 807 return av_stream_map_lane_count; 808 } 809 810 static uint32_t get_audio_sdp_overhead( 811 enum dp_link_encoding encoding, 812 enum dc_lane_count lane_count, 813 bool is_mst) 814 { 815 uint32_t audio_sdp_overhead = 0; 816 817 if (encoding == DP_8b_10b_ENCODING) { 818 if (is_mst) 819 audio_sdp_overhead = 16; /* 4 * 2 + 8 */ 820 else 821 audio_sdp_overhead = lane_count * 2 + 8; 822 } else if (encoding == DP_128b_132b_ENCODING) { 823 audio_sdp_overhead = 10; /* 4 x 2.5 */ 824 } 825 826 ASSERT(audio_sdp_overhead != 0); 827 828 return audio_sdp_overhead; 829 } 830 831 /* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST. 832 */ 833 static uint32_t calculate_overhead_hblank_bw_in_symbols( 834 uint32_t max_slice_h) 835 { 836 uint32_t overhead_hblank_bw = 0; /* in stream symbols */ 837 838 overhead_hblank_bw += max_slice_h * 4; /* EOC overhead */ 839 overhead_hblank_bw += 12; /* Main link overhead (VBID, BS/BE) */ 840 841 return overhead_hblank_bw; 842 } 843 844 uint32_t dp_required_hblank_size_bytes( 845 const struct dc_link *link, 846 struct dp_audio_bandwidth_params *audio_params) 847 { 848 /* Main logic from dce_audio is duplicated here, with the main 849 * difference being: 850 * - Pre-determined lane count of 4 851 * - Assumed 16 dsc slices for worst case 852 * - Assumed SDP split disabled for worst case 853 * TODO: Unify logic from dce_audio to prevent duplicated logic. 854 */ 855 856 const struct dc_crtc_timing *timing = audio_params->crtc_timing; 857 const uint32_t channel_count = audio_params->channel_count; 858 const uint32_t sample_rate_hz = audio_params->sample_rate_hz; 859 const enum dp_link_encoding link_encoding = audio_params->link_encoding; 860 861 // 8b/10b MST and 128b/132b are always 4 logical lanes. 862 const uint32_t lane_count = 4; 863 const bool is_mst = (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT); 864 // Maximum slice count is with ODM 4:1, 4 slices per DSC 865 const uint32_t max_slices_h = 16; 866 867 const uint32_t av_stream_map_lane_count = get_av_stream_map_lane_count( 868 link_encoding, lane_count, is_mst); 869 const uint32_t audio_sdp_overhead = get_audio_sdp_overhead( 870 link_encoding, lane_count, is_mst); 871 struct dp_audio_layout_config layout_config; 872 873 if (link_encoding == DP_8b_10b_ENCODING && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) 874 return 0; 875 876 get_audio_layout_config( 877 channel_count, link_encoding, &layout_config); 878 879 /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */ 880 struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100); 881 struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction( 882 timing->pix_clk_100hz, (long long)timing->h_total * 10); 883 struct fixed31_32 samples_per_line; 884 struct fixed31_32 layouts_per_line; 885 struct fixed31_32 symbols_per_sdp_max_layout; 886 struct fixed31_32 remainder; 887 uint32_t num_sdp_with_max_layouts; 888 uint32_t required_symbols_per_hblank; 889 uint32_t required_bytes_per_hblank = 0; 890 891 samples_per_line = dc_fixpt_from_fraction(sample_rate_hz, 1000); 892 samples_per_line = dc_fixpt_div(samples_per_line, horizontal_line_freq_khz); 893 layouts_per_line = dc_fixpt_div_int(samples_per_line, layout_config.layouts_per_sample_denom); 894 // HBlank expansion usage assumes SDP split disabled to allow for worst case. 895 layouts_per_line = dc_fixpt_from_int(dc_fixpt_ceil(layouts_per_line)); 896 897 num_sdp_with_max_layouts = dc_fixpt_floor( 898 dc_fixpt_div_int(layouts_per_line, layout_config.max_layouts_per_audio_sdp)); 899 symbols_per_sdp_max_layout = dc_fixpt_from_int( 900 layout_config.max_layouts_per_audio_sdp * layout_config.symbols_per_layout); 901 symbols_per_sdp_max_layout = dc_fixpt_add_int(symbols_per_sdp_max_layout, audio_sdp_overhead); 902 symbols_per_sdp_max_layout = dc_fixpt_mul(symbols_per_sdp_max_layout, audio_sdp_margin); 903 required_symbols_per_hblank = num_sdp_with_max_layouts; 904 required_symbols_per_hblank *= ((dc_fixpt_ceil(symbols_per_sdp_max_layout) + av_stream_map_lane_count) / 905 av_stream_map_lane_count) * av_stream_map_lane_count; 906 907 if (num_sdp_with_max_layouts != dc_fixpt_ceil( 908 dc_fixpt_div_int(layouts_per_line, layout_config.max_layouts_per_audio_sdp))) { 909 remainder = dc_fixpt_sub_int(layouts_per_line, 910 num_sdp_with_max_layouts * layout_config.max_layouts_per_audio_sdp); 911 remainder = dc_fixpt_mul_int(remainder, layout_config.symbols_per_layout); 912 remainder = dc_fixpt_add_int(remainder, audio_sdp_overhead); 913 remainder = dc_fixpt_mul(remainder, audio_sdp_margin); 914 required_symbols_per_hblank += ((dc_fixpt_ceil(remainder) + av_stream_map_lane_count) / 915 av_stream_map_lane_count) * av_stream_map_lane_count; 916 } 917 918 required_symbols_per_hblank += calculate_overhead_hblank_bw_in_symbols(max_slices_h); 919 920 if (link_encoding == DP_8b_10b_ENCODING) 921 required_bytes_per_hblank = required_symbols_per_hblank; // 8 bits per 8b/10b symbol 922 else if (link_encoding == DP_128b_132b_ENCODING) 923 required_bytes_per_hblank = required_symbols_per_hblank * 4; // 32 bits per 128b/132b symbol 924 925 return required_bytes_per_hblank; 926 } 927 928