1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) && 144 (link->type != dc_connection_none)) 145 dpcd_write_rx_power_ctrl(link, false); 146 } 147 } 148 149 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 150 { 151 struct pipe_ctx *pipes[MAX_PIPES]; 152 struct dc_stream_state *streams[MAX_PIPES]; 153 struct dc_state *state = link->dc->current_state; 154 uint8_t count; 155 int i; 156 struct dc_stream_update stream_update; 157 bool dpms_off = true; 158 struct link_resource link_res = {0}; 159 160 memset(&stream_update, 0, sizeof(stream_update)); 161 stream_update.dpms_off = &dpms_off; 162 163 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 164 165 /* The subsequent call to dc_commit_updates_for_stream for a full update 166 * will release the current state and swap to a new state. Releasing the 167 * current state results in the stream pointers in the pipe_ctx structs 168 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream. 169 */ 170 for (i = 0; i < count; i++) 171 streams[i] = pipes[i]->stream; 172 173 for (i = 0; i < count; i++) { 174 stream_update.stream = streams[i]; 175 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 176 streams[i], &stream_update, 177 state); 178 } 179 180 /* link can be also enabled by vbios. In this case it is not recorded 181 * in pipe_ctx. Disable link phy here to make sure it is completely off 182 */ 183 dp_disable_link_phy(link, &link_res, link->connector_signal); 184 } 185 186 void link_resume(struct dc_link *link) 187 { 188 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 189 program_hpd_filter(link); 190 } 191 192 /* This function returns true if the pipe is used to feed video signal directly 193 * to the link. 194 */ 195 static bool is_master_pipe_for_link(const struct dc_link *link, 196 const struct pipe_ctx *pipe) 197 { 198 return resource_is_pipe_type(pipe, OTG_MASTER) && 199 pipe->stream->link == link; 200 } 201 202 /* 203 * This function finds all master pipes feeding to a given link with dpms set to 204 * on in given dc state. 205 */ 206 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 207 struct dc_state *state, 208 uint8_t *count, 209 struct pipe_ctx *pipes[MAX_PIPES]) 210 { 211 int i; 212 struct pipe_ctx *pipe = NULL; 213 214 *count = 0; 215 for (i = 0; i < MAX_PIPES; i++) { 216 pipe = &state->res_ctx.pipe_ctx[i]; 217 218 if (is_master_pipe_for_link(link, pipe) && 219 pipe->stream->dpms_off == false) { 220 pipes[(*count)++] = pipe; 221 } 222 } 223 } 224 225 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 226 enum engine_id eng_id, 227 struct ext_hdmi_settings *settings) 228 { 229 bool result = false; 230 int i = 0; 231 struct integrated_info *integrated_info = 232 pipe_ctx->stream->ctx->dc_bios->integrated_info; 233 234 if (integrated_info == NULL) 235 return false; 236 237 /* 238 * Get retimer settings from sbios for passing SI eye test for DCE11 239 * The setting values are varied based on board revision and port id 240 * Therefore the setting values of each ports is passed by sbios. 241 */ 242 243 // Check if current bios contains ext Hdmi settings 244 if (integrated_info->gpu_cap_info & 0x20) { 245 switch (eng_id) { 246 case ENGINE_ID_DIGA: 247 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 248 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 249 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 250 memmove(settings->reg_settings, 251 integrated_info->dp0_ext_hdmi_reg_settings, 252 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 253 memmove(settings->reg_settings_6g, 254 integrated_info->dp0_ext_hdmi_6g_reg_settings, 255 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 256 result = true; 257 break; 258 case ENGINE_ID_DIGB: 259 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 260 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 261 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 262 memmove(settings->reg_settings, 263 integrated_info->dp1_ext_hdmi_reg_settings, 264 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 265 memmove(settings->reg_settings_6g, 266 integrated_info->dp1_ext_hdmi_6g_reg_settings, 267 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 268 result = true; 269 break; 270 case ENGINE_ID_DIGC: 271 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 272 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 273 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 274 memmove(settings->reg_settings, 275 integrated_info->dp2_ext_hdmi_reg_settings, 276 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 277 memmove(settings->reg_settings_6g, 278 integrated_info->dp2_ext_hdmi_6g_reg_settings, 279 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 280 result = true; 281 break; 282 case ENGINE_ID_DIGD: 283 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 284 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 285 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 286 memmove(settings->reg_settings, 287 integrated_info->dp3_ext_hdmi_reg_settings, 288 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 289 memmove(settings->reg_settings_6g, 290 integrated_info->dp3_ext_hdmi_6g_reg_settings, 291 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 292 result = true; 293 break; 294 default: 295 break; 296 } 297 298 if (result == true) { 299 // Validate settings from bios integrated info table 300 if (settings->slv_addr == 0) 301 return false; 302 if (settings->reg_num > 9) 303 return false; 304 if (settings->reg_num_6g > 3) 305 return false; 306 307 for (i = 0; i < settings->reg_num; i++) { 308 if (settings->reg_settings[i].i2c_reg_index > 0x20) 309 return false; 310 } 311 312 for (i = 0; i < settings->reg_num_6g; i++) { 313 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 314 return false; 315 } 316 } 317 } 318 319 return result; 320 } 321 322 static bool write_i2c(struct pipe_ctx *pipe_ctx, 323 uint8_t address, uint8_t *buffer, uint32_t length) 324 { 325 struct i2c_command cmd = {0}; 326 struct i2c_payload payload = {0}; 327 328 memset(&payload, 0, sizeof(payload)); 329 memset(&cmd, 0, sizeof(cmd)); 330 331 cmd.number_of_payloads = 1; 332 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 333 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 334 335 payload.address = address; 336 payload.data = buffer; 337 payload.length = length; 338 payload.write = true; 339 cmd.payloads = &payload; 340 341 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 342 pipe_ctx->stream->link, &cmd)) 343 return true; 344 345 return false; 346 } 347 348 static void write_i2c_retimer_setting( 349 struct pipe_ctx *pipe_ctx, 350 bool is_vga_mode, 351 bool is_over_340mhz, 352 struct ext_hdmi_settings *settings) 353 { 354 uint8_t slave_address = (settings->slv_addr >> 1); 355 uint8_t buffer[2]; 356 const uint8_t apply_rx_tx_change = 0x4; 357 uint8_t offset = 0xA; 358 uint8_t value = 0; 359 int i = 0; 360 bool i2c_success = false; 361 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 362 363 memset(&buffer, 0, sizeof(buffer)); 364 365 /* Start Ext-Hdmi programming*/ 366 367 for (i = 0; i < settings->reg_num; i++) { 368 /* Apply 3G settings */ 369 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 370 371 buffer[0] = settings->reg_settings[i].i2c_reg_index; 372 buffer[1] = settings->reg_settings[i].i2c_reg_val; 373 i2c_success = write_i2c(pipe_ctx, slave_address, 374 buffer, sizeof(buffer)); 375 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 376 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 377 slave_address, buffer[0], buffer[1], i2c_success?1:0); 378 379 if (!i2c_success) 380 goto i2c_write_fail; 381 382 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 383 * needs to be set to 1 on every 0xA-0xC write. 384 */ 385 if (settings->reg_settings[i].i2c_reg_index == 0xA || 386 settings->reg_settings[i].i2c_reg_index == 0xB || 387 settings->reg_settings[i].i2c_reg_index == 0xC) { 388 389 /* Query current value from offset 0xA */ 390 if (settings->reg_settings[i].i2c_reg_index == 0xA) 391 value = settings->reg_settings[i].i2c_reg_val; 392 else { 393 i2c_success = 394 link_query_ddc_data( 395 pipe_ctx->stream->link->ddc, 396 slave_address, &offset, 1, &value, 1); 397 if (!i2c_success) 398 goto i2c_write_fail; 399 } 400 401 buffer[0] = offset; 402 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 403 buffer[1] = value | apply_rx_tx_change; 404 i2c_success = write_i2c(pipe_ctx, slave_address, 405 buffer, sizeof(buffer)); 406 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 407 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 408 slave_address, buffer[0], buffer[1], i2c_success?1:0); 409 if (!i2c_success) 410 goto i2c_write_fail; 411 } 412 } 413 } 414 415 /* Apply 3G settings */ 416 if (is_over_340mhz) { 417 for (i = 0; i < settings->reg_num_6g; i++) { 418 /* Apply 3G settings */ 419 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 420 421 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 422 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 423 i2c_success = write_i2c(pipe_ctx, slave_address, 424 buffer, sizeof(buffer)); 425 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 426 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 427 slave_address, buffer[0], buffer[1], i2c_success?1:0); 428 429 if (!i2c_success) 430 goto i2c_write_fail; 431 432 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 433 * needs to be set to 1 on every 0xA-0xC write. 434 */ 435 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 436 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 437 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 438 439 /* Query current value from offset 0xA */ 440 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 441 value = settings->reg_settings_6g[i].i2c_reg_val; 442 else { 443 i2c_success = 444 link_query_ddc_data( 445 pipe_ctx->stream->link->ddc, 446 slave_address, &offset, 1, &value, 1); 447 if (!i2c_success) 448 goto i2c_write_fail; 449 } 450 451 buffer[0] = offset; 452 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 453 buffer[1] = value | apply_rx_tx_change; 454 i2c_success = write_i2c(pipe_ctx, slave_address, 455 buffer, sizeof(buffer)); 456 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 457 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 458 slave_address, buffer[0], buffer[1], i2c_success?1:0); 459 if (!i2c_success) 460 goto i2c_write_fail; 461 } 462 } 463 } 464 } 465 466 if (is_vga_mode) { 467 /* Program additional settings if using 640x480 resolution */ 468 469 /* Write offset 0xFF to 0x01 */ 470 buffer[0] = 0xff; 471 buffer[1] = 0x01; 472 i2c_success = write_i2c(pipe_ctx, slave_address, 473 buffer, sizeof(buffer)); 474 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 475 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 476 slave_address, buffer[0], buffer[1], i2c_success?1:0); 477 if (!i2c_success) 478 goto i2c_write_fail; 479 480 /* Write offset 0x00 to 0x23 */ 481 buffer[0] = 0x00; 482 buffer[1] = 0x23; 483 i2c_success = write_i2c(pipe_ctx, slave_address, 484 buffer, sizeof(buffer)); 485 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 486 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 487 slave_address, buffer[0], buffer[1], i2c_success?1:0); 488 if (!i2c_success) 489 goto i2c_write_fail; 490 491 /* Write offset 0xff to 0x00 */ 492 buffer[0] = 0xff; 493 buffer[1] = 0x00; 494 i2c_success = write_i2c(pipe_ctx, slave_address, 495 buffer, sizeof(buffer)); 496 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 497 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 498 slave_address, buffer[0], buffer[1], i2c_success?1:0); 499 if (!i2c_success) 500 goto i2c_write_fail; 501 502 } 503 504 return; 505 506 i2c_write_fail: 507 DC_LOG_DEBUG("Set retimer failed"); 508 } 509 510 static void write_i2c_default_retimer_setting( 511 struct pipe_ctx *pipe_ctx, 512 bool is_vga_mode, 513 bool is_over_340mhz) 514 { 515 uint8_t slave_address = (0xBA >> 1); 516 uint8_t buffer[2]; 517 bool i2c_success = false; 518 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 519 520 memset(&buffer, 0, sizeof(buffer)); 521 522 /* Program Slave Address for tuning single integrity */ 523 /* Write offset 0x0A to 0x13 */ 524 buffer[0] = 0x0A; 525 buffer[1] = 0x13; 526 i2c_success = write_i2c(pipe_ctx, slave_address, 527 buffer, sizeof(buffer)); 528 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 529 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 530 slave_address, buffer[0], buffer[1], i2c_success?1:0); 531 if (!i2c_success) 532 goto i2c_write_fail; 533 534 /* Write offset 0x0A to 0x17 */ 535 buffer[0] = 0x0A; 536 buffer[1] = 0x17; 537 i2c_success = write_i2c(pipe_ctx, slave_address, 538 buffer, sizeof(buffer)); 539 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 540 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 541 slave_address, buffer[0], buffer[1], i2c_success?1:0); 542 if (!i2c_success) 543 goto i2c_write_fail; 544 545 /* Write offset 0x0B to 0xDA or 0xD8 */ 546 buffer[0] = 0x0B; 547 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 548 i2c_success = write_i2c(pipe_ctx, slave_address, 549 buffer, sizeof(buffer)); 550 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 551 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 552 slave_address, buffer[0], buffer[1], i2c_success?1:0); 553 if (!i2c_success) 554 goto i2c_write_fail; 555 556 /* Write offset 0x0A to 0x17 */ 557 buffer[0] = 0x0A; 558 buffer[1] = 0x17; 559 i2c_success = write_i2c(pipe_ctx, slave_address, 560 buffer, sizeof(buffer)); 561 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 562 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 563 slave_address, buffer[0], buffer[1], i2c_success?1:0); 564 if (!i2c_success) 565 goto i2c_write_fail; 566 567 /* Write offset 0x0C to 0x1D or 0x91 */ 568 buffer[0] = 0x0C; 569 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 570 i2c_success = write_i2c(pipe_ctx, slave_address, 571 buffer, sizeof(buffer)); 572 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 573 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 574 slave_address, buffer[0], buffer[1], i2c_success?1:0); 575 if (!i2c_success) 576 goto i2c_write_fail; 577 578 /* Write offset 0x0A to 0x17 */ 579 buffer[0] = 0x0A; 580 buffer[1] = 0x17; 581 i2c_success = write_i2c(pipe_ctx, slave_address, 582 buffer, sizeof(buffer)); 583 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 584 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 585 slave_address, buffer[0], buffer[1], i2c_success?1:0); 586 if (!i2c_success) 587 goto i2c_write_fail; 588 589 590 if (is_vga_mode) { 591 /* Program additional settings if using 640x480 resolution */ 592 593 /* Write offset 0xFF to 0x01 */ 594 buffer[0] = 0xff; 595 buffer[1] = 0x01; 596 i2c_success = write_i2c(pipe_ctx, slave_address, 597 buffer, sizeof(buffer)); 598 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 599 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 600 slave_address, buffer[0], buffer[1], i2c_success?1:0); 601 if (!i2c_success) 602 goto i2c_write_fail; 603 604 /* Write offset 0x00 to 0x23 */ 605 buffer[0] = 0x00; 606 buffer[1] = 0x23; 607 i2c_success = write_i2c(pipe_ctx, slave_address, 608 buffer, sizeof(buffer)); 609 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 610 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 611 slave_address, buffer[0], buffer[1], i2c_success?1:0); 612 if (!i2c_success) 613 goto i2c_write_fail; 614 615 /* Write offset 0xff to 0x00 */ 616 buffer[0] = 0xff; 617 buffer[1] = 0x00; 618 i2c_success = write_i2c(pipe_ctx, slave_address, 619 buffer, sizeof(buffer)); 620 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 621 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 622 slave_address, buffer[0], buffer[1], i2c_success?1:0); 623 if (!i2c_success) 624 goto i2c_write_fail; 625 } 626 627 return; 628 629 i2c_write_fail: 630 DC_LOG_DEBUG("Set default retimer failed"); 631 } 632 633 static void write_i2c_redriver_setting( 634 struct pipe_ctx *pipe_ctx, 635 bool is_over_340mhz) 636 { 637 uint8_t slave_address = (0xF0 >> 1); 638 uint8_t buffer[16]; 639 bool i2c_success = false; 640 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 641 642 memset(&buffer, 0, sizeof(buffer)); 643 644 // Program Slave Address for tuning single integrity 645 buffer[3] = 0x4E; 646 buffer[4] = 0x4E; 647 buffer[5] = 0x4E; 648 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 649 650 i2c_success = write_i2c(pipe_ctx, slave_address, 651 buffer, sizeof(buffer)); 652 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 653 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 654 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 655 i2c_success = %d\n", 656 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 657 658 if (!i2c_success) 659 DC_LOG_DEBUG("Set redriver failed"); 660 } 661 662 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 663 { 664 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 665 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 666 struct cp_psp_stream_config config = {0}; 667 enum dp_panel_mode panel_mode = 668 dp_get_panel_mode(pipe_ctx->stream->link); 669 670 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 671 return; 672 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 673 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 674 ASSERT(link_enc); 675 if (link_enc == NULL) 676 return; 677 678 /* otg instance */ 679 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 680 681 /* dig front end */ 682 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 683 684 /* stream encoder index */ 685 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 686 if (dp_is_128b_132b_signal(pipe_ctx)) 687 config.stream_enc_idx = 688 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 689 690 /* dig back end */ 691 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 692 693 /* link encoder index */ 694 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 695 if (dp_is_128b_132b_signal(pipe_ctx)) 696 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 697 698 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 699 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 700 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 701 else 702 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 703 704 705 /* phy index */ 706 config.phy_idx = resource_transmitter_to_phy_idx( 707 pipe_ctx->stream->link->dc, link_enc->transmitter); 708 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 709 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 710 config.phy_idx = 0; 711 712 /* stream properties */ 713 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 714 config.mst_enabled = (pipe_ctx->stream->signal == 715 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 716 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 717 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 718 1 : 0; 719 config.dpms_off = dpms_off; 720 721 /* dm stream context */ 722 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 723 724 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 725 } 726 727 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 728 { 729 struct dc *dc = pipe_ctx->stream->ctx->dc; 730 731 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 732 return; 733 734 dc->hwss.set_avmute(pipe_ctx, enable); 735 } 736 737 static void enable_mst_on_sink(struct dc_link *link, bool enable) 738 { 739 unsigned char mstmCntl = 0; 740 741 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 742 if (enable) 743 mstmCntl |= DP_MST_EN; 744 else 745 mstmCntl &= (~DP_MST_EN); 746 747 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 748 } 749 750 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 751 struct dsc_optc_config *config) 752 { 753 uint32_t precision = 1 << 28; 754 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 755 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 756 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 757 DC_LOGGER_INIT(dsc->ctx->logger); 758 759 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 760 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 761 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 762 */ 763 ll_bytes_per_pix_fraq *= 10000000; 764 ll_bytes_per_pix_fraq /= precision; 765 766 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 767 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 768 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 769 DC_LOG_DSC("\tslice_width %d", config->slice_width); 770 } 771 772 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 773 { 774 struct dc *dc = pipe_ctx->stream->ctx->dc; 775 struct dc_stream_state *stream = pipe_ctx->stream; 776 bool result = false; 777 778 if (dc_is_virtual_signal(stream->signal)) 779 result = true; 780 else 781 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 782 return result; 783 } 784 785 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 786 { 787 struct dc *dc = pipe_ctx->stream->ctx->dc; 788 struct dc_stream_state *stream = pipe_ctx->stream; 789 bool result = false; 790 791 if (dc_is_virtual_signal(stream->signal)) 792 result = true; 793 else 794 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 795 return result; 796 } 797 798 799 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 800 * i.e. after dp_enable_dsc_on_rx() had been called 801 */ 802 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 803 { 804 /* TODO: Move this to HWSS as this is hardware programming sequence not a 805 * link layer sequence 806 */ 807 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 808 struct dc *dc = pipe_ctx->stream->ctx->dc; 809 struct dc_stream_state *stream = pipe_ctx->stream; 810 struct pipe_ctx *odm_pipe; 811 int opp_cnt = 1; 812 struct dccg *dccg = dc->res_pool->dccg; 813 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 814 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 815 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 816 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 817 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 818 * this problem. We are implementing a workaround here to keep using dscclk 819 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 820 * 48Mhz) pixel clock to avoid hitting this problem. 821 */ 822 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 823 stream->timing.pix_clk_100hz > 480000; 824 DC_LOGGER_INIT(dsc->ctx->logger); 825 826 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 827 opp_cnt++; 828 829 if (enable) { 830 struct dsc_config dsc_cfg; 831 struct dsc_optc_config dsc_optc_cfg = {0}; 832 enum optc_dsc_mode optc_dsc_mode; 833 834 /* Enable DSC hw block */ 835 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + 836 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 837 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 838 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 839 dsc_cfg.color_depth = stream->timing.display_color_depth; 840 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 841 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 842 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 843 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 844 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 845 846 if (should_use_dto_dscclk) 847 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 848 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 849 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 850 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 851 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 852 853 if (should_use_dto_dscclk) 854 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 855 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 856 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 857 } 858 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 859 dsc_cfg.pic_width *= opp_cnt; 860 861 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 862 863 /* Enable DSC in encoder */ 864 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 865 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 866 dsc_optc_config_log(dsc, &dsc_optc_cfg); 867 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 868 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 869 optc_dsc_mode, 870 dsc_optc_cfg.bytes_per_pixel, 871 dsc_optc_cfg.slice_width); 872 873 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 874 } 875 876 /* Enable DSC in OPTC */ 877 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 878 dsc_optc_config_log(dsc, &dsc_optc_cfg); 879 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 880 optc_dsc_mode, 881 dsc_optc_cfg.bytes_per_pixel, 882 dsc_optc_cfg.slice_width); 883 } else { 884 /* disable DSC in OPTC */ 885 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 886 pipe_ctx->stream_res.tg, 887 OPTC_DSC_DISABLED, 0, 0); 888 889 /* disable DSC in stream encoder */ 890 if (dc_is_dp_signal(stream->signal)) { 891 if (dp_is_128b_132b_signal(pipe_ctx)) 892 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 893 pipe_ctx->stream_res.hpo_dp_stream_enc, 894 false, 895 NULL, 896 true); 897 else { 898 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 899 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 900 pipe_ctx->stream_res.stream_enc, 901 OPTC_DSC_DISABLED, 0, 0); 902 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 903 pipe_ctx->stream_res.stream_enc, false, NULL, true); 904 } 905 } 906 907 /* disable DSC block */ 908 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 909 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 910 /* 911 * TODO - dsc_disconnect is a double buffered register. 912 * by the time we call dsc_disable, dsc may still remain 913 * connected to OPP. In this case OPTC will no longer 914 * get correct pixel data because DSCC is off. However 915 * we also can't wait for the disconnect pending 916 * complete, because this function can be called 917 * with/without OTG master lock acquired. When the lock 918 * is acquired we will never get pending complete until 919 * we release the lock later. So there is no easy way to 920 * solve this problem especially when the lock is 921 * acquired. DSC is a front end hw block it should be 922 * programmed as part of front end sequence, where the 923 * commit sequence without lock and update sequence 924 * with lock are completely separated. However because 925 * we are programming dsc as part of back end link 926 * programming sequence, we don't know if front end OPTC 927 * master lock is acquired. The back end should be 928 * agnostic to front end lock. DSC programming shouldn't 929 * belong to this sequence. 930 */ 931 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 932 if (dccg->funcs->set_ref_dscclk) 933 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 934 } 935 } 936 } 937 938 /* 939 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 940 * hence PPS info packet update need to use frame update instead of immediate update. 941 * Added parameter immediate_update for this purpose. 942 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 943 * which is the only place where a "false" would be passed in for param immediate_update. 944 * 945 * immediate_update is only applicable when DSC is enabled. 946 */ 947 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 948 { 949 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 950 struct dc_stream_state *stream = pipe_ctx->stream; 951 952 if (!pipe_ctx->stream->timing.flags.DSC) 953 return false; 954 955 if (!dsc) 956 return false; 957 958 DC_LOGGER_INIT(dsc->ctx->logger); 959 960 if (enable) { 961 struct dsc_config dsc_cfg; 962 uint8_t dsc_packed_pps[128]; 963 964 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 965 memset(dsc_packed_pps, 0, 128); 966 967 /* Enable DSC hw block */ 968 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 969 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 970 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 971 dsc_cfg.color_depth = stream->timing.display_color_depth; 972 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 973 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 974 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 975 976 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 977 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 978 if (dc_is_dp_signal(stream->signal)) { 979 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 980 if (dp_is_128b_132b_signal(pipe_ctx)) 981 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 982 pipe_ctx->stream_res.hpo_dp_stream_enc, 983 true, 984 &dsc_packed_pps[0], 985 immediate_update); 986 else 987 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 988 pipe_ctx->stream_res.stream_enc, 989 true, 990 &dsc_packed_pps[0], 991 immediate_update); 992 } 993 } else { 994 /* disable DSC PPS in stream encoder */ 995 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 996 if (dc_is_dp_signal(stream->signal)) { 997 if (dp_is_128b_132b_signal(pipe_ctx)) 998 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 999 pipe_ctx->stream_res.hpo_dp_stream_enc, 1000 false, 1001 NULL, 1002 true); 1003 else 1004 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 1005 pipe_ctx->stream_res.stream_enc, false, NULL, true); 1006 } 1007 } 1008 1009 return true; 1010 } 1011 1012 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 1013 { 1014 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1015 bool result = false; 1016 1017 if (!pipe_ctx->stream->timing.flags.DSC) 1018 goto out; 1019 if (!dsc) 1020 goto out; 1021 1022 if (enable) { 1023 { 1024 link_set_dsc_on_stream(pipe_ctx, true); 1025 result = true; 1026 } 1027 } else { 1028 dp_set_dsc_on_rx(pipe_ctx, false); 1029 link_set_dsc_on_stream(pipe_ctx, false); 1030 result = true; 1031 } 1032 out: 1033 return result; 1034 } 1035 1036 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 1037 { 1038 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1039 1040 if (!pipe_ctx->stream->timing.flags.DSC) 1041 return false; 1042 if (!dsc) 1043 return false; 1044 1045 link_set_dsc_on_stream(pipe_ctx, true); 1046 link_set_dsc_pps_packet(pipe_ctx, true, false); 1047 return true; 1048 } 1049 1050 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1051 { 1052 struct dc_stream_state *stream = pipe_ctx->stream; 1053 1054 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1055 struct dc_link *link = stream->link; 1056 union down_spread_ctrl old_downspread; 1057 union down_spread_ctrl new_downspread; 1058 1059 memset(&old_downspread, 0, sizeof(old_downspread)); 1060 1061 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1062 &old_downspread.raw, sizeof(old_downspread)); 1063 1064 new_downspread.raw = old_downspread.raw; 1065 1066 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1067 (stream->ignore_msa_timing_param) ? 1 : 0; 1068 1069 if (new_downspread.raw != old_downspread.raw) { 1070 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1071 &new_downspread.raw, sizeof(new_downspread)); 1072 } 1073 1074 } else { 1075 dm_helpers_mst_enable_stream_features(stream); 1076 } 1077 } 1078 1079 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1080 { 1081 const uint32_t VCP_Y_PRECISION = 1000; 1082 uint64_t vcp_x, vcp_y; 1083 DC_LOGGER_INIT(link->ctx->logger); 1084 1085 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1086 avg_time_slots_per_mtp = dc_fixpt_add( 1087 avg_time_slots_per_mtp, 1088 dc_fixpt_from_fraction( 1089 1, 1090 2*VCP_Y_PRECISION)); 1091 1092 vcp_x = dc_fixpt_floor( 1093 avg_time_slots_per_mtp); 1094 vcp_y = dc_fixpt_floor( 1095 dc_fixpt_mul_int( 1096 dc_fixpt_sub_int( 1097 avg_time_slots_per_mtp, 1098 dc_fixpt_floor( 1099 avg_time_slots_per_mtp)), 1100 VCP_Y_PRECISION)); 1101 1102 1103 if (link->type == dc_connection_mst_branch) 1104 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1105 "X: %llu " 1106 "Y: %llu/%d", 1107 vcp_x, 1108 vcp_y, 1109 VCP_Y_PRECISION); 1110 else 1111 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1112 "X: %llu " 1113 "Y: %llu/%d", 1114 vcp_x, 1115 vcp_y, 1116 VCP_Y_PRECISION); 1117 } 1118 1119 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1120 { 1121 struct fixed31_32 mbytes_per_sec; 1122 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1123 &stream->link->cur_link_settings); 1124 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1125 1126 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1127 1128 return dc_fixpt_div_int(mbytes_per_sec, 54); 1129 } 1130 1131 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1132 { 1133 struct fixed31_32 peak_kbps; 1134 uint32_t numerator = 0; 1135 uint32_t denominator = 1; 1136 1137 /* 1138 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1139 * required when determining PBN/time slot utilization on the link between 1140 * us and the branch, since that overhead is already accounted for in 1141 * the get_pbn_per_slot function. 1142 * 1143 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1144 * common multiplier to render an integer PBN for all link rate/lane 1145 * counts combinations 1146 * calculate 1147 * peak_kbps *= (64/54) 1148 * peak_kbps /= (8 * 1000) convert to bytes 1149 */ 1150 1151 numerator = 64; 1152 denominator = 54 * 8 * 1000; 1153 kbps *= numerator; 1154 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1155 1156 return peak_kbps; 1157 } 1158 1159 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1160 { 1161 uint64_t kbps; 1162 enum dc_link_encoding_format link_encoding; 1163 1164 if (dp_is_128b_132b_signal(pipe_ctx)) 1165 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1166 else 1167 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1168 1169 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1170 return get_pbn_from_bw_in_kbps(kbps); 1171 } 1172 1173 1174 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1175 static void get_lane_status( 1176 struct dc_link *link, 1177 uint32_t lane_count, 1178 union lane_status *status, 1179 union lane_align_status_updated *status_updated) 1180 { 1181 unsigned int lane; 1182 uint8_t dpcd_buf[3] = {0}; 1183 1184 if (status == NULL || status_updated == NULL) { 1185 return; 1186 } 1187 1188 core_link_read_dpcd( 1189 link, 1190 DP_LANE0_1_STATUS, 1191 dpcd_buf, 1192 sizeof(dpcd_buf)); 1193 1194 for (lane = 0; lane < lane_count; lane++) { 1195 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1196 } 1197 1198 status_updated->raw = dpcd_buf[2]; 1199 } 1200 1201 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1202 { 1203 /* 1204 * wait for ACT handled 1205 */ 1206 int i; 1207 const int act_retries = 30; 1208 enum act_return_status result = ACT_FAILED; 1209 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1210 union payload_table_update_status update_status = {0}; 1211 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1212 union lane_align_status_updated lane_status_updated; 1213 DC_LOGGER_INIT(link->ctx->logger); 1214 1215 if (!display_connected || link->aux_access_disabled) 1216 return true; 1217 for (i = 0; i < act_retries; i++) { 1218 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1219 1220 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1221 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1222 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1223 !dp_is_interlane_aligned(lane_status_updated)) { 1224 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1225 "polling for ACT handled."); 1226 result = ACT_LINK_LOST; 1227 break; 1228 } 1229 core_link_read_dpcd( 1230 link, 1231 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1232 &update_status.raw, 1233 1); 1234 1235 if (update_status.bits.ACT_HANDLED == 1) { 1236 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1237 result = ACT_SUCCESS; 1238 break; 1239 } 1240 1241 fsleep(5000); 1242 } 1243 1244 if (result == ACT_FAILED) { 1245 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1246 "continue on. Something is wrong with the branch."); 1247 } 1248 1249 return (result == ACT_SUCCESS); 1250 } 1251 1252 static void update_mst_stream_alloc_table( 1253 struct dc_link *link, 1254 struct stream_encoder *stream_enc, 1255 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1256 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1257 { 1258 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1259 struct link_mst_stream_allocation *dc_alloc; 1260 1261 int i; 1262 int j; 1263 1264 /* if DRM proposed_table has more than one new payload */ 1265 ASSERT(proposed_table->stream_count - 1266 link->mst_stream_alloc_table.stream_count < 2); 1267 1268 /* copy proposed_table to link, add stream encoder */ 1269 for (i = 0; i < proposed_table->stream_count; i++) { 1270 1271 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1272 dc_alloc = 1273 &link->mst_stream_alloc_table.stream_allocations[j]; 1274 1275 if (dc_alloc->vcp_id == 1276 proposed_table->stream_allocations[i].vcp_id) { 1277 1278 work_table[i] = *dc_alloc; 1279 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1280 break; /* exit j loop */ 1281 } 1282 } 1283 1284 /* new vcp_id */ 1285 if (j == link->mst_stream_alloc_table.stream_count) { 1286 work_table[i].vcp_id = 1287 proposed_table->stream_allocations[i].vcp_id; 1288 work_table[i].slot_count = 1289 proposed_table->stream_allocations[i].slot_count; 1290 work_table[i].stream_enc = stream_enc; 1291 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1292 } 1293 } 1294 1295 /* update link->mst_stream_alloc_table with work_table */ 1296 link->mst_stream_alloc_table.stream_count = 1297 proposed_table->stream_count; 1298 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1299 link->mst_stream_alloc_table.stream_allocations[i] = 1300 work_table[i]; 1301 } 1302 1303 static void remove_stream_from_alloc_table( 1304 struct dc_link *link, 1305 struct stream_encoder *dio_stream_enc, 1306 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1307 { 1308 int i = 0; 1309 struct link_mst_stream_allocation_table *table = 1310 &link->mst_stream_alloc_table; 1311 1312 if (hpo_dp_stream_enc) { 1313 for (; i < table->stream_count; i++) 1314 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1315 break; 1316 } else { 1317 for (; i < table->stream_count; i++) 1318 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1319 break; 1320 } 1321 1322 if (i < table->stream_count) { 1323 i++; 1324 for (; i < table->stream_count; i++) 1325 table->stream_allocations[i-1] = table->stream_allocations[i]; 1326 memset(&table->stream_allocations[table->stream_count-1], 0, 1327 sizeof(struct link_mst_stream_allocation)); 1328 table->stream_count--; 1329 } 1330 } 1331 1332 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1333 { 1334 struct dc_stream_state *stream = pipe_ctx->stream; 1335 struct dc_link *link = stream->link; 1336 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1337 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1338 int i; 1339 bool mst_mode = (link->type == dc_connection_mst_branch); 1340 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1341 const struct dc_link_settings empty_link_settings = {0}; 1342 DC_LOGGER_INIT(link->ctx->logger); 1343 1344 /* deallocate_mst_payload is called before disable link. When mode or 1345 * disable/enable monitor, new stream is created which is not in link 1346 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1347 * should not done. For new mode set, map_resources will get engine 1348 * for new stream, so stream_enc->id should be validated until here. 1349 */ 1350 1351 /* slot X.Y */ 1352 if (link_hwss->ext.set_throttled_vcp_size) 1353 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1354 if (link_hwss->ext.set_hblank_min_symbol_width) 1355 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1356 &empty_link_settings, 1357 avg_time_slots_per_mtp); 1358 1359 if (mst_mode) { 1360 /* when link is in mst mode, reply on mst manager to remove 1361 * payload 1362 */ 1363 if (dm_helpers_dp_mst_write_payload_allocation_table( 1364 stream->ctx, 1365 stream, 1366 &proposed_table, 1367 false)) 1368 update_mst_stream_alloc_table( 1369 link, 1370 pipe_ctx->stream_res.stream_enc, 1371 pipe_ctx->stream_res.hpo_dp_stream_enc, 1372 &proposed_table); 1373 else 1374 DC_LOG_WARNING("Failed to update" 1375 "MST allocation table for" 1376 "pipe idx:%d\n", 1377 pipe_ctx->pipe_idx); 1378 } else { 1379 /* when link is no longer in mst mode (mst hub unplugged), 1380 * remove payload with default dc logic 1381 */ 1382 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1383 pipe_ctx->stream_res.hpo_dp_stream_enc); 1384 } 1385 1386 DC_LOG_MST("%s" 1387 "stream_count: %d: ", 1388 __func__, 1389 link->mst_stream_alloc_table.stream_count); 1390 1391 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1392 DC_LOG_MST("stream_enc[%d]: %p " 1393 "stream[%d].hpo_dp_stream_enc: %p " 1394 "stream[%d].vcp_id: %d " 1395 "stream[%d].slot_count: %d\n", 1396 i, 1397 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1398 i, 1399 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1400 i, 1401 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1402 i, 1403 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1404 } 1405 1406 /* update mst stream allocation table hardware state */ 1407 if (link_hwss->ext.update_stream_allocation_table == NULL || 1408 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1409 DC_LOG_DEBUG("Unknown encoding format\n"); 1410 return DC_ERROR_UNEXPECTED; 1411 } 1412 1413 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1414 &link->mst_stream_alloc_table); 1415 1416 if (mst_mode) 1417 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1418 stream->ctx, 1419 stream); 1420 1421 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1422 stream->ctx, 1423 stream); 1424 1425 return DC_OK; 1426 } 1427 1428 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1429 * because stream_encoder is not exposed to dm 1430 */ 1431 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1432 { 1433 struct dc_stream_state *stream = pipe_ctx->stream; 1434 struct dc_link *link = stream->link; 1435 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1436 struct fixed31_32 avg_time_slots_per_mtp; 1437 struct fixed31_32 pbn; 1438 struct fixed31_32 pbn_per_slot; 1439 int i; 1440 enum act_return_status ret; 1441 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1442 DC_LOGGER_INIT(link->ctx->logger); 1443 1444 /* enable_link_dp_mst already check link->enabled_stream_count 1445 * and stream is in link->stream[]. This is called during set mode, 1446 * stream_enc is available. 1447 */ 1448 1449 /* get calculate VC payload for stream: stream_alloc */ 1450 if (dm_helpers_dp_mst_write_payload_allocation_table( 1451 stream->ctx, 1452 stream, 1453 &proposed_table, 1454 true)) 1455 update_mst_stream_alloc_table( 1456 link, 1457 pipe_ctx->stream_res.stream_enc, 1458 pipe_ctx->stream_res.hpo_dp_stream_enc, 1459 &proposed_table); 1460 else 1461 DC_LOG_WARNING("Failed to update" 1462 "MST allocation table for" 1463 "pipe idx:%d\n", 1464 pipe_ctx->pipe_idx); 1465 1466 DC_LOG_MST("%s " 1467 "stream_count: %d: \n ", 1468 __func__, 1469 link->mst_stream_alloc_table.stream_count); 1470 1471 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1472 DC_LOG_MST("stream_enc[%d]: %p " 1473 "stream[%d].hpo_dp_stream_enc: %p " 1474 "stream[%d].vcp_id: %d " 1475 "stream[%d].slot_count: %d\n", 1476 i, 1477 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1478 i, 1479 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1480 i, 1481 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1482 i, 1483 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1484 } 1485 1486 ASSERT(proposed_table.stream_count > 0); 1487 1488 /* program DP source TX for payload */ 1489 if (link_hwss->ext.update_stream_allocation_table == NULL || 1490 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1491 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1492 return DC_ERROR_UNEXPECTED; 1493 } 1494 1495 link_hwss->ext.update_stream_allocation_table(link, 1496 &pipe_ctx->link_res, 1497 &link->mst_stream_alloc_table); 1498 1499 /* send down message */ 1500 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1501 stream->ctx, 1502 stream); 1503 1504 if (ret != ACT_LINK_LOST) 1505 dm_helpers_dp_mst_send_payload_allocation( 1506 stream->ctx, 1507 stream); 1508 1509 /* slot X.Y for only current stream */ 1510 pbn_per_slot = get_pbn_per_slot(stream); 1511 if (pbn_per_slot.value == 0) { 1512 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1513 return DC_UNSUPPORTED_VALUE; 1514 } 1515 pbn = get_pbn_from_timing(pipe_ctx); 1516 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1517 1518 log_vcp_x_y(link, avg_time_slots_per_mtp); 1519 1520 if (link_hwss->ext.set_throttled_vcp_size) 1521 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1522 if (link_hwss->ext.set_hblank_min_symbol_width) 1523 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1524 &link->cur_link_settings, 1525 avg_time_slots_per_mtp); 1526 1527 return DC_OK; 1528 } 1529 1530 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1531 const struct dc_stream_state *stream, 1532 const struct dc_link *link) 1533 { 1534 struct fixed31_32 link_bw_effective = 1535 dc_fixpt_from_int( 1536 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1537 struct fixed31_32 timeslot_bw_effective = 1538 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1539 struct fixed31_32 timing_bw = 1540 dc_fixpt_from_int( 1541 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1542 dc_link_get_highest_encoding_format(link))); 1543 struct fixed31_32 avg_time_slots_per_mtp = 1544 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1545 1546 return avg_time_slots_per_mtp; 1547 } 1548 1549 1550 static bool write_128b_132b_sst_payload_allocation_table( 1551 const struct dc_stream_state *stream, 1552 struct dc_link *link, 1553 struct link_mst_stream_allocation_table *proposed_table, 1554 bool allocate) 1555 { 1556 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1557 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1558 bool result = false; 1559 uint8_t req_slot_count = 0; 1560 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1561 union payload_table_update_status update_status = { 0 }; 1562 const uint32_t max_retries = 30; 1563 uint32_t retries = 0; 1564 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1565 DC_LOGGER_INIT(link->ctx->logger); 1566 1567 if (allocate) { 1568 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1569 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1570 /// Validation should filter out modes that exceed link BW 1571 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1572 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1573 return false; 1574 } else { 1575 /// Leave req_slot_count = 0 if allocate is false. 1576 } 1577 1578 proposed_table->stream_count = 1; /// Always 1 stream for SST 1579 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1580 proposed_table->stream_allocations[0].vcp_id = vc_id; 1581 1582 if (!display_connected || link->aux_access_disabled) 1583 return true; 1584 1585 /// Write DPCD 2C0 = 1 to start updating 1586 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1587 core_link_write_dpcd( 1588 link, 1589 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1590 &update_status.raw, 1591 1); 1592 1593 /// Program the changes in DPCD 1C0 - 1C2 1594 ASSERT(vc_id == 1); 1595 core_link_write_dpcd( 1596 link, 1597 DP_PAYLOAD_ALLOCATE_SET, 1598 &vc_id, 1599 1); 1600 1601 ASSERT(start_time_slot == 0); 1602 core_link_write_dpcd( 1603 link, 1604 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1605 &start_time_slot, 1606 1); 1607 1608 core_link_write_dpcd( 1609 link, 1610 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1611 &req_slot_count, 1612 1); 1613 1614 /// Poll till DPCD 2C0 read 1 1615 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1616 1617 while (retries < max_retries) { 1618 if (core_link_read_dpcd( 1619 link, 1620 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1621 &update_status.raw, 1622 1) == DC_OK) { 1623 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1624 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1625 result = true; 1626 break; 1627 } 1628 } else { 1629 union dpcd_rev dpcdRev = {0}; 1630 1631 if (core_link_read_dpcd( 1632 link, 1633 DP_DPCD_REV, 1634 &dpcdRev.raw, 1635 1) != DC_OK) { 1636 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1637 "of sink while polling payload table " 1638 "updated status bit."); 1639 break; 1640 } 1641 } 1642 retries++; 1643 fsleep(5000); 1644 } 1645 1646 if (!result && retries == max_retries) { 1647 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1648 "continue on. Something is wrong with the branch."); 1649 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1650 } 1651 1652 return result; 1653 } 1654 1655 /* 1656 * Payload allocation/deallocation for SST introduced in DP2.0 1657 */ 1658 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1659 bool allocate) 1660 { 1661 struct dc_stream_state *stream = pipe_ctx->stream; 1662 struct dc_link *link = stream->link; 1663 struct link_mst_stream_allocation_table proposed_table = {0}; 1664 struct fixed31_32 avg_time_slots_per_mtp; 1665 const struct dc_link_settings empty_link_settings = {0}; 1666 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1667 DC_LOGGER_INIT(link->ctx->logger); 1668 1669 /* slot X.Y for SST payload deallocate */ 1670 if (!allocate) { 1671 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1672 1673 log_vcp_x_y(link, avg_time_slots_per_mtp); 1674 1675 if (link_hwss->ext.set_throttled_vcp_size) 1676 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1677 avg_time_slots_per_mtp); 1678 if (link_hwss->ext.set_hblank_min_symbol_width) 1679 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1680 &empty_link_settings, 1681 avg_time_slots_per_mtp); 1682 } 1683 1684 /* calculate VC payload and update branch with new payload allocation table*/ 1685 if (!write_128b_132b_sst_payload_allocation_table( 1686 stream, 1687 link, 1688 &proposed_table, 1689 allocate)) { 1690 DC_LOG_ERROR("SST Update Payload: Failed to update " 1691 "allocation table for " 1692 "pipe idx: %d\n", 1693 pipe_ctx->pipe_idx); 1694 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1695 } 1696 1697 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1698 1699 ASSERT(proposed_table.stream_count == 1); 1700 1701 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1702 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1703 "vcp_id: %d " 1704 "slot_count: %d\n", 1705 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1706 proposed_table.stream_allocations[0].vcp_id, 1707 proposed_table.stream_allocations[0].slot_count); 1708 1709 /* program DP source TX for payload */ 1710 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1711 &proposed_table); 1712 1713 /* poll for ACT handled */ 1714 if (!poll_for_allocation_change_trigger(link)) { 1715 // Failures will result in blackscreen and errors logged 1716 BREAK_TO_DEBUGGER(); 1717 } 1718 1719 /* slot X.Y for SST payload allocate */ 1720 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1721 DP_128b_132b_ENCODING) { 1722 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1723 1724 log_vcp_x_y(link, avg_time_slots_per_mtp); 1725 1726 if (link_hwss->ext.set_throttled_vcp_size) 1727 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1728 avg_time_slots_per_mtp); 1729 if (link_hwss->ext.set_hblank_min_symbol_width) 1730 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1731 &link->cur_link_settings, 1732 avg_time_slots_per_mtp); 1733 } 1734 1735 /* Always return DC_OK. 1736 * If part of sequence fails, log failure(s) and show blackscreen 1737 */ 1738 return DC_OK; 1739 } 1740 1741 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1742 { 1743 struct dc_stream_state *stream = pipe_ctx->stream; 1744 struct dc_link *link = stream->link; 1745 struct fixed31_32 avg_time_slots_per_mtp; 1746 struct fixed31_32 pbn; 1747 struct fixed31_32 pbn_per_slot; 1748 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1749 uint8_t i; 1750 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1751 DC_LOGGER_INIT(link->ctx->logger); 1752 1753 /* decrease throttled vcp size */ 1754 pbn_per_slot = get_pbn_per_slot(stream); 1755 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1756 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1757 1758 if (link_hwss->ext.set_throttled_vcp_size) 1759 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1760 if (link_hwss->ext.set_hblank_min_symbol_width) 1761 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1762 &link->cur_link_settings, 1763 avg_time_slots_per_mtp); 1764 1765 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1766 dm_helpers_dp_mst_send_payload_allocation( 1767 stream->ctx, 1768 stream); 1769 1770 /* notify immediate branch device table update */ 1771 if (dm_helpers_dp_mst_write_payload_allocation_table( 1772 stream->ctx, 1773 stream, 1774 &proposed_table, 1775 true)) { 1776 /* update mst stream allocation table software state */ 1777 update_mst_stream_alloc_table( 1778 link, 1779 pipe_ctx->stream_res.stream_enc, 1780 pipe_ctx->stream_res.hpo_dp_stream_enc, 1781 &proposed_table); 1782 } else { 1783 DC_LOG_WARNING("Failed to update" 1784 "MST allocation table for" 1785 "pipe idx:%d\n", 1786 pipe_ctx->pipe_idx); 1787 } 1788 1789 DC_LOG_MST("%s " 1790 "stream_count: %d: \n ", 1791 __func__, 1792 link->mst_stream_alloc_table.stream_count); 1793 1794 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1795 DC_LOG_MST("stream_enc[%d]: %p " 1796 "stream[%d].hpo_dp_stream_enc: %p " 1797 "stream[%d].vcp_id: %d " 1798 "stream[%d].slot_count: %d\n", 1799 i, 1800 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1801 i, 1802 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1803 i, 1804 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1805 i, 1806 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1807 } 1808 1809 ASSERT(proposed_table.stream_count > 0); 1810 1811 /* update mst stream allocation table hardware state */ 1812 if (link_hwss->ext.update_stream_allocation_table == NULL || 1813 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1814 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1815 return DC_ERROR_UNEXPECTED; 1816 } 1817 1818 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1819 &link->mst_stream_alloc_table); 1820 1821 /* poll for immediate branch device ACT handled */ 1822 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1823 stream->ctx, 1824 stream); 1825 1826 return DC_OK; 1827 } 1828 1829 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1830 { 1831 struct dc_stream_state *stream = pipe_ctx->stream; 1832 struct dc_link *link = stream->link; 1833 struct fixed31_32 avg_time_slots_per_mtp; 1834 struct fixed31_32 pbn; 1835 struct fixed31_32 pbn_per_slot; 1836 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1837 uint8_t i; 1838 enum act_return_status ret; 1839 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1840 DC_LOGGER_INIT(link->ctx->logger); 1841 1842 /* notify immediate branch device table update */ 1843 if (dm_helpers_dp_mst_write_payload_allocation_table( 1844 stream->ctx, 1845 stream, 1846 &proposed_table, 1847 true)) { 1848 /* update mst stream allocation table software state */ 1849 update_mst_stream_alloc_table( 1850 link, 1851 pipe_ctx->stream_res.stream_enc, 1852 pipe_ctx->stream_res.hpo_dp_stream_enc, 1853 &proposed_table); 1854 } 1855 1856 DC_LOG_MST("%s " 1857 "stream_count: %d: \n ", 1858 __func__, 1859 link->mst_stream_alloc_table.stream_count); 1860 1861 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1862 DC_LOG_MST("stream_enc[%d]: %p " 1863 "stream[%d].hpo_dp_stream_enc: %p " 1864 "stream[%d].vcp_id: %d " 1865 "stream[%d].slot_count: %d\n", 1866 i, 1867 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1868 i, 1869 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1870 i, 1871 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1872 i, 1873 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1874 } 1875 1876 ASSERT(proposed_table.stream_count > 0); 1877 1878 /* update mst stream allocation table hardware state */ 1879 if (link_hwss->ext.update_stream_allocation_table == NULL || 1880 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1881 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1882 return DC_ERROR_UNEXPECTED; 1883 } 1884 1885 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1886 &link->mst_stream_alloc_table); 1887 1888 /* poll for immediate branch device ACT handled */ 1889 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1890 stream->ctx, 1891 stream); 1892 1893 if (ret != ACT_LINK_LOST) { 1894 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1895 dm_helpers_dp_mst_send_payload_allocation( 1896 stream->ctx, 1897 stream); 1898 } 1899 1900 /* increase throttled vcp size */ 1901 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1902 pbn_per_slot = get_pbn_per_slot(stream); 1903 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1904 1905 if (link_hwss->ext.set_throttled_vcp_size) 1906 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1907 if (link_hwss->ext.set_hblank_min_symbol_width) 1908 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1909 &link->cur_link_settings, 1910 avg_time_slots_per_mtp); 1911 1912 return DC_OK; 1913 } 1914 1915 static void disable_link_dp(struct dc_link *link, 1916 const struct link_resource *link_res, 1917 enum signal_type signal) 1918 { 1919 struct dc_link_settings link_settings = link->cur_link_settings; 1920 1921 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1922 link->mst_stream_alloc_table.stream_count > 0) 1923 /* disable MST link only when last vc payload is deallocated */ 1924 return; 1925 1926 dp_disable_link_phy(link, link_res, signal); 1927 1928 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1929 if (!link->skip_implict_edp_power_control) 1930 link->dc->hwss.edp_power_control(link, false); 1931 } 1932 1933 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1934 /* set the sink to SST mode after disabling the link */ 1935 enable_mst_on_sink(link, false); 1936 1937 if (link_dp_get_encoding_format(&link_settings) == 1938 DP_8b_10b_ENCODING) { 1939 dp_set_fec_enable(link, link_res, false); 1940 dp_set_fec_ready(link, link_res, false); 1941 } 1942 } 1943 1944 static void disable_link(struct dc_link *link, 1945 const struct link_resource *link_res, 1946 enum signal_type signal) 1947 { 1948 if (dc_is_dp_signal(signal)) { 1949 disable_link_dp(link, link_res, signal); 1950 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1951 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1952 } else { 1953 link->dc->hwss.disable_link_output(link, link_res, signal); 1954 } 1955 1956 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1957 /* MST disable link only when no stream use the link */ 1958 if (link->mst_stream_alloc_table.stream_count <= 0) 1959 link->link_status.link_active = false; 1960 } else { 1961 link->link_status.link_active = false; 1962 } 1963 } 1964 1965 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1966 { 1967 struct dc_stream_state *stream = pipe_ctx->stream; 1968 struct dc_link *link = stream->link; 1969 enum dc_color_depth display_color_depth; 1970 enum engine_id eng_id; 1971 struct ext_hdmi_settings settings = {0}; 1972 bool is_over_340mhz = false; 1973 bool is_vga_mode = (stream->timing.h_addressable == 640) 1974 && (stream->timing.v_addressable == 480); 1975 struct dc *dc = pipe_ctx->stream->ctx->dc; 1976 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1977 1978 if (stream->phy_pix_clk == 0) 1979 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1980 if (stream->phy_pix_clk > 340000) 1981 is_over_340mhz = true; 1982 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1983 ASSERT(false); 1984 return; 1985 } 1986 1987 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1988 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1989 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1990 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1991 /* DP159, Retimer settings */ 1992 eng_id = pipe_ctx->stream_res.stream_enc->id; 1993 1994 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1995 write_i2c_retimer_setting(pipe_ctx, 1996 is_vga_mode, is_over_340mhz, &settings); 1997 } else { 1998 write_i2c_default_retimer_setting(pipe_ctx, 1999 is_vga_mode, is_over_340mhz); 2000 } 2001 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2002 /* PI3EQX1204, Redriver settings */ 2003 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 2004 } 2005 } 2006 2007 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2008 write_scdc_data( 2009 stream->link->ddc, 2010 stream->phy_pix_clk, 2011 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2012 2013 memset(&stream->link->cur_link_settings, 0, 2014 sizeof(struct dc_link_settings)); 2015 2016 display_color_depth = stream->timing.display_color_depth; 2017 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2018 display_color_depth = COLOR_DEPTH_888; 2019 2020 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 2021 * character clock in case that beyond 340MHz. 2022 */ 2023 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 2024 link_hwss->setup_stream_encoder(pipe_ctx); 2025 2026 dc->hwss.enable_tmds_link_output( 2027 link, 2028 &pipe_ctx->link_res, 2029 pipe_ctx->stream->signal, 2030 pipe_ctx->clock_source->id, 2031 display_color_depth, 2032 stream->phy_pix_clk); 2033 2034 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2035 read_scdc_data(link->ddc); 2036 } 2037 2038 static enum dc_status enable_link_dp(struct dc_state *state, 2039 struct pipe_ctx *pipe_ctx) 2040 { 2041 struct dc_stream_state *stream = pipe_ctx->stream; 2042 enum dc_status status; 2043 bool skip_video_pattern; 2044 struct dc_link *link = stream->link; 2045 const struct dc_link_settings *link_settings = 2046 &pipe_ctx->link_config.dp_link_settings; 2047 bool fec_enable; 2048 int i; 2049 bool apply_seamless_boot_optimization = false; 2050 uint32_t bl_oled_enable_delay = 50; // in ms 2051 uint32_t post_oui_delay = 30; // 30ms 2052 /* Reduce link bandwidth between failed link training attempts. */ 2053 bool do_fallback = false; 2054 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2055 2056 // Increase retry count if attempting DP1.x on FIXED_VS link 2057 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2058 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2059 lt_attempts = 10; 2060 2061 // check for seamless boot 2062 for (i = 0; i < state->stream_count; i++) { 2063 if (state->streams[i]->apply_seamless_boot_optimization) { 2064 apply_seamless_boot_optimization = true; 2065 break; 2066 } 2067 } 2068 2069 /* Train with fallback when enabling DPIA link. Conventional links are 2070 * trained with fallback during sink detection. 2071 */ 2072 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2073 !link->dc->config.enable_dpia_pre_training) 2074 do_fallback = true; 2075 2076 /* 2077 * Temporary w/a to get DP2.0 link rates to work with SST. 2078 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2079 */ 2080 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2081 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2082 link->dc->debug.set_mst_en_for_sst) { 2083 enable_mst_on_sink(link, true); 2084 } 2085 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2086 /*in case it is not on*/ 2087 if (!link->dc->config.edp_no_power_sequencing) 2088 link->dc->hwss.edp_power_control(link, true); 2089 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2090 } 2091 2092 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2093 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2094 } else { 2095 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2096 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2097 if (state->clk_mgr && !apply_seamless_boot_optimization) 2098 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2099 state, false); 2100 } 2101 2102 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2103 dpcd_set_source_specific_data(link); 2104 if (link->dpcd_sink_ext_caps.raw != 0) { 2105 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2106 msleep(post_oui_delay); 2107 } 2108 2109 // similarly, mode switch can cause loss of cable ID 2110 dpcd_write_cable_id_to_dprx(link); 2111 2112 skip_video_pattern = true; 2113 2114 if (link_settings->link_rate == LINK_RATE_LOW) 2115 skip_video_pattern = false; 2116 2117 if (stream->sink_patches.oled_optimize_display_on) 2118 set_default_brightness_aux(link); 2119 2120 if (perform_link_training_with_retries(link_settings, 2121 skip_video_pattern, 2122 lt_attempts, 2123 pipe_ctx, 2124 pipe_ctx->stream->signal, 2125 do_fallback)) { 2126 status = DC_OK; 2127 } else { 2128 status = DC_FAIL_DP_LINK_TRAINING; 2129 } 2130 2131 if (link->preferred_training_settings.fec_enable) 2132 fec_enable = *link->preferred_training_settings.fec_enable; 2133 else 2134 fec_enable = true; 2135 2136 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2137 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 2138 2139 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2140 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2141 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2142 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2143 if (!stream->sink_patches.oled_optimize_display_on) { 2144 set_default_brightness_aux(link); 2145 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2146 msleep(bl_oled_enable_delay); 2147 edp_backlight_enable_aux(link, true); 2148 } else { 2149 edp_backlight_enable_aux(link, true); 2150 } 2151 } 2152 2153 return status; 2154 } 2155 2156 static enum dc_status enable_link_edp( 2157 struct dc_state *state, 2158 struct pipe_ctx *pipe_ctx) 2159 { 2160 return enable_link_dp(state, pipe_ctx); 2161 } 2162 2163 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2164 { 2165 struct dc_stream_state *stream = pipe_ctx->stream; 2166 struct dc_link *link = stream->link; 2167 struct dc *dc = stream->ctx->dc; 2168 2169 if (stream->phy_pix_clk == 0) 2170 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2171 2172 memset(&stream->link->cur_link_settings, 0, 2173 sizeof(struct dc_link_settings)); 2174 dc->hwss.enable_lvds_link_output( 2175 link, 2176 &pipe_ctx->link_res, 2177 pipe_ctx->clock_source->id, 2178 stream->phy_pix_clk); 2179 2180 } 2181 2182 static enum dc_status enable_link_dp_mst( 2183 struct dc_state *state, 2184 struct pipe_ctx *pipe_ctx) 2185 { 2186 struct dc_link *link = pipe_ctx->stream->link; 2187 unsigned char mstm_cntl = 0; 2188 2189 /* sink signal type after MST branch is MST. Multiple MST sinks 2190 * share one link. Link DP PHY is enable or training only once. 2191 */ 2192 if (link->link_status.link_active) 2193 return DC_OK; 2194 2195 /* clear payload table */ 2196 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2197 if (mstm_cntl & DP_MST_EN) 2198 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2199 2200 /* to make sure the pending down rep can be processed 2201 * before enabling the link 2202 */ 2203 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2204 2205 /* set the sink to MST mode before enabling the link */ 2206 enable_mst_on_sink(link, true); 2207 2208 return enable_link_dp(state, pipe_ctx); 2209 } 2210 2211 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2212 { 2213 struct dc_link *link = pipe_ctx->stream->link; 2214 2215 link->dc->hwss.enable_dp_link_output(link, 2216 &pipe_ctx->link_res, 2217 SIGNAL_TYPE_DISPLAY_PORT, 2218 pipe_ctx->clock_source->id, 2219 &pipe_ctx->link_config.dp_link_settings); 2220 return DC_OK; 2221 } 2222 2223 static enum dc_status enable_link( 2224 struct dc_state *state, 2225 struct pipe_ctx *pipe_ctx) 2226 { 2227 enum dc_status status = DC_ERROR_UNEXPECTED; 2228 struct dc_stream_state *stream = pipe_ctx->stream; 2229 struct dc_link *link = stream->link; 2230 2231 /* There's some scenarios where driver is unloaded with display 2232 * still enabled. When driver is reloaded, it may cause a display 2233 * to not light up if there is a mismatch between old and new 2234 * link settings. Need to call disable first before enabling at 2235 * new link settings. 2236 */ 2237 if (link->link_status.link_active) 2238 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2239 2240 switch (pipe_ctx->stream->signal) { 2241 case SIGNAL_TYPE_DISPLAY_PORT: 2242 status = enable_link_dp(state, pipe_ctx); 2243 break; 2244 case SIGNAL_TYPE_EDP: 2245 status = enable_link_edp(state, pipe_ctx); 2246 break; 2247 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2248 status = enable_link_dp_mst(state, pipe_ctx); 2249 msleep(200); 2250 break; 2251 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2252 case SIGNAL_TYPE_DVI_DUAL_LINK: 2253 case SIGNAL_TYPE_HDMI_TYPE_A: 2254 enable_link_hdmi(pipe_ctx); 2255 status = DC_OK; 2256 break; 2257 case SIGNAL_TYPE_LVDS: 2258 enable_link_lvds(pipe_ctx); 2259 status = DC_OK; 2260 break; 2261 case SIGNAL_TYPE_RGB: 2262 status = DC_OK; 2263 break; 2264 case SIGNAL_TYPE_VIRTUAL: 2265 status = enable_link_virtual(pipe_ctx); 2266 break; 2267 default: 2268 break; 2269 } 2270 2271 if (status == DC_OK) { 2272 pipe_ctx->stream->link->link_status.link_active = true; 2273 } 2274 2275 return status; 2276 } 2277 2278 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2279 { 2280 struct dc_link *link = stream->sink->link; 2281 int req_bw = bw; 2282 2283 DC_LOGGER_INIT(link->ctx->logger); 2284 2285 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2286 return false; 2287 2288 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2289 int sink_index = 0; 2290 int i = 0; 2291 2292 for (i = 0; i < link->sink_count; i++) { 2293 if (link->remote_sinks[i] == NULL) 2294 continue; 2295 2296 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2297 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2298 else 2299 sink_index = i; 2300 } 2301 2302 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2303 } 2304 2305 link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); 2306 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2307 2308 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2309 2310 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2311 int i = 0; 2312 2313 for (i = 0; i < link->sink_count; i++) { 2314 if (link->remote_sinks[i] == NULL) 2315 continue; 2316 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2317 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2318 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2319 } 2320 } 2321 2322 return true; 2323 } 2324 2325 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2326 { 2327 bool ret; 2328 2329 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2330 dc_link_get_highest_encoding_format(stream->sink->link)); 2331 2332 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2333 2334 return ret; 2335 } 2336 2337 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2338 { 2339 bool ret; 2340 2341 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2342 2343 return ret; 2344 } 2345 2346 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2347 { 2348 struct dc *dc = pipe_ctx->stream->ctx->dc; 2349 struct dc_stream_state *stream = pipe_ctx->stream; 2350 struct dc_link *link = stream->sink->link; 2351 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2352 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2353 2354 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2355 2356 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2357 2358 if (dp_is_128b_132b_signal(pipe_ctx)) 2359 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2360 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2361 return; 2362 2363 if (pipe_ctx->stream->sink) { 2364 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2365 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2366 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__, 2367 pipe_ctx->stream->sink->edid_caps.display_name, 2368 pipe_ctx->stream->signal, link->link_index); 2369 } 2370 } 2371 2372 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2373 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2374 set_avmute(pipe_ctx, true); 2375 } 2376 2377 if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) 2378 dc->hwss.disable_audio_stream(pipe_ctx); 2379 2380 update_psp_stream_config(pipe_ctx, true); 2381 dc->hwss.blank_stream(pipe_ctx); 2382 2383 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2384 deallocate_usb4_bandwidth(pipe_ctx->stream); 2385 2386 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2387 deallocate_mst_payload(pipe_ctx); 2388 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2389 dp_is_128b_132b_signal(pipe_ctx)) 2390 update_sst_payload(pipe_ctx, false); 2391 2392 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2393 struct ext_hdmi_settings settings = {0}; 2394 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2395 2396 unsigned short masked_chip_caps = link->chip_caps & 2397 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2398 //Need to inform that sink is going to use legacy HDMI mode. 2399 write_scdc_data( 2400 link->ddc, 2401 165000,//vbios only handles 165Mhz. 2402 false); 2403 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2404 /* DP159, Retimer settings */ 2405 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2406 write_i2c_retimer_setting(pipe_ctx, 2407 false, false, &settings); 2408 else 2409 write_i2c_default_retimer_setting(pipe_ctx, 2410 false, false); 2411 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2412 /* PI3EQX1204, Redriver settings */ 2413 write_i2c_redriver_setting(pipe_ctx, false); 2414 } 2415 } 2416 2417 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2418 !dp_is_128b_132b_signal(pipe_ctx)) { 2419 2420 /* In DP1.x SST mode, our encoder will go to TPS1 2421 * when link is on but stream is off. 2422 * Disabling link before stream will avoid exposing TPS1 pattern 2423 * during the disable sequence as it will confuse some receivers 2424 * state machine. 2425 * In DP2 or MST mode, our encoder will stay video active 2426 */ 2427 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2428 dc->hwss.disable_stream(pipe_ctx); 2429 } else { 2430 dc->hwss.disable_stream(pipe_ctx); 2431 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2432 } 2433 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2434 2435 if (pipe_ctx->stream->timing.flags.DSC) { 2436 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2437 link_set_dsc_enable(pipe_ctx, false); 2438 } 2439 if (dp_is_128b_132b_signal(pipe_ctx)) { 2440 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2441 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2442 } 2443 2444 if (vpg && vpg->funcs->vpg_powerdown) 2445 vpg->funcs->vpg_powerdown(vpg); 2446 2447 /* for psp not exist case */ 2448 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2449 /* reset internal save state to default since eDP is off */ 2450 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2451 /* since current psp not loaded, we need to reset it to default */ 2452 link->panel_mode = panel_mode; 2453 } 2454 } 2455 2456 void link_set_dpms_on( 2457 struct dc_state *state, 2458 struct pipe_ctx *pipe_ctx) 2459 { 2460 struct dc *dc = pipe_ctx->stream->ctx->dc; 2461 struct dc_stream_state *stream = pipe_ctx->stream; 2462 struct dc_link *link = stream->sink->link; 2463 enum dc_status status; 2464 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 2465 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2466 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2467 bool apply_edp_fast_boot_optimization = 2468 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2469 2470 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2471 2472 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2473 2474 if (dp_is_128b_132b_signal(pipe_ctx)) 2475 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2476 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2477 return; 2478 2479 if (pipe_ctx->stream->sink) { 2480 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2481 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2482 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__, 2483 pipe_ctx->stream->sink->edid_caps.display_name, 2484 pipe_ctx->stream->signal, 2485 link->link_index); 2486 } 2487 } 2488 2489 if (!dc->config.unify_link_enc_assignment) 2490 link_enc = link_enc_cfg_get_link_enc(link); 2491 ASSERT(link_enc); 2492 2493 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2494 && !dp_is_128b_132b_signal(pipe_ctx)) { 2495 if (link_enc) 2496 link_enc->funcs->setup( 2497 link_enc, 2498 pipe_ctx->stream->signal); 2499 } 2500 2501 pipe_ctx->stream->link->link_state_valid = true; 2502 2503 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2504 if (dp_is_128b_132b_signal(pipe_ctx)) 2505 otg_out_dest = OUT_MUX_HPO_DP; 2506 else 2507 otg_out_dest = OUT_MUX_DIO; 2508 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2509 } 2510 2511 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2512 2513 // Enable VPG before building infoframe 2514 if (vpg && vpg->funcs->vpg_poweron) 2515 vpg->funcs->vpg_poweron(vpg); 2516 2517 resource_build_info_frame(pipe_ctx); 2518 dc->hwss.update_info_frame(pipe_ctx); 2519 2520 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2521 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2522 2523 /* Do not touch link on seamless boot optimization. */ 2524 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2525 pipe_ctx->stream->dpms_off = false; 2526 2527 /* Still enable stream features & audio on seamless boot for DP external displays */ 2528 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2529 enable_stream_features(pipe_ctx); 2530 dc->hwss.enable_audio_stream(pipe_ctx); 2531 } 2532 2533 update_psp_stream_config(pipe_ctx, false); 2534 return; 2535 } 2536 2537 /* eDP lit up by bios already, no need to enable again. */ 2538 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2539 apply_edp_fast_boot_optimization && 2540 !pipe_ctx->stream->timing.flags.DSC && 2541 !pipe_ctx->next_odm_pipe) { 2542 pipe_ctx->stream->dpms_off = false; 2543 update_psp_stream_config(pipe_ctx, false); 2544 2545 if (link->is_dds) { 2546 uint32_t post_oui_delay = 30; // 30ms 2547 2548 dpcd_set_source_specific_data(link); 2549 msleep(post_oui_delay); 2550 } 2551 2552 return; 2553 } 2554 2555 if (pipe_ctx->stream->dpms_off) 2556 return; 2557 2558 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2559 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2560 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2561 */ 2562 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2563 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2564 return; 2565 } 2566 2567 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2568 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2569 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2570 * will be automatically set at a later time when the video is enabled 2571 * (DP_VID_STREAM_EN = 1). 2572 */ 2573 if (pipe_ctx->stream->timing.flags.DSC) { 2574 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2575 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2576 link_set_dsc_enable(pipe_ctx, true); 2577 } 2578 2579 status = enable_link(state, pipe_ctx); 2580 2581 if (status != DC_OK) { 2582 DC_LOG_WARNING("enabling link %u failed: %d\n", 2583 pipe_ctx->stream->link->link_index, 2584 status); 2585 2586 /* Abort stream enable *unless* the failure was due to 2587 * DP link training - some DP monitors will recover and 2588 * show the stream anyway. But MST displays can't proceed 2589 * without link training. 2590 */ 2591 if (status != DC_FAIL_DP_LINK_TRAINING || 2592 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2593 if (false == stream->link->link_status.link_active) 2594 disable_link(stream->link, &pipe_ctx->link_res, 2595 pipe_ctx->stream->signal); 2596 BREAK_TO_DEBUGGER(); 2597 return; 2598 } 2599 } 2600 2601 /* turn off otg test pattern if enable */ 2602 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2603 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2604 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2605 COLOR_DEPTH_UNDEFINED); 2606 2607 /* This second call is needed to reconfigure the DIG 2608 * as a workaround for the incorrect value being applied 2609 * from transmitter control. 2610 */ 2611 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2612 dp_is_128b_132b_signal(pipe_ctx))) { 2613 2614 if (link_enc) 2615 link_enc->funcs->setup( 2616 link_enc, 2617 pipe_ctx->stream->signal); 2618 2619 } 2620 2621 dc->hwss.enable_stream(pipe_ctx); 2622 2623 /* Set DPS PPS SDP (AKA "info frames") */ 2624 if (pipe_ctx->stream->timing.flags.DSC) { 2625 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2626 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2627 dp_set_dsc_on_rx(pipe_ctx, true); 2628 link_set_dsc_pps_packet(pipe_ctx, true, true); 2629 } 2630 } 2631 2632 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2633 dp_set_hblank_reduction_on_rx(pipe_ctx); 2634 2635 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2636 allocate_usb4_bandwidth(pipe_ctx->stream); 2637 2638 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2639 allocate_mst_payload(pipe_ctx); 2640 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2641 dp_is_128b_132b_signal(pipe_ctx)) 2642 update_sst_payload(pipe_ctx, true); 2643 2644 /* Corruption was observed on systems with display mux when stream gets 2645 * enabled after the mux switch. Having a small delay between link 2646 * training and stream unblank resolves the corruption issue. 2647 * This is workaround. 2648 */ 2649 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2650 link->is_display_mux_present) 2651 msleep(20); 2652 2653 dc->hwss.unblank_stream(pipe_ctx, 2654 &pipe_ctx->stream->link->cur_link_settings); 2655 2656 if (stream->sink_patches.delay_ignore_msa > 0) 2657 msleep(stream->sink_patches.delay_ignore_msa); 2658 2659 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2660 enable_stream_features(pipe_ctx); 2661 update_psp_stream_config(pipe_ctx, false); 2662 2663 if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) 2664 dc->hwss.enable_audio_stream(pipe_ctx); 2665 2666 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2667 set_avmute(pipe_ctx, false); 2668 } 2669 } 2670