1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) && 144 (link->type != dc_connection_none)) 145 dpcd_write_rx_power_ctrl(link, false); 146 } 147 } 148 149 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 150 { 151 struct pipe_ctx *pipes[MAX_PIPES]; 152 struct dc_stream_state *streams[MAX_PIPES]; 153 struct dc_state *state = link->dc->current_state; 154 uint8_t count; 155 int i; 156 struct dc_stream_update stream_update; 157 bool dpms_off = true; 158 struct link_resource link_res = {0}; 159 160 memset(&stream_update, 0, sizeof(stream_update)); 161 stream_update.dpms_off = &dpms_off; 162 163 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 164 165 /* The subsequent call to dc_commit_updates_for_stream for a full update 166 * will release the current state and swap to a new state. Releasing the 167 * current state results in the stream pointers in the pipe_ctx structs 168 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream. 169 */ 170 for (i = 0; i < count; i++) 171 streams[i] = pipes[i]->stream; 172 173 for (i = 0; i < count; i++) { 174 stream_update.stream = streams[i]; 175 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 176 streams[i], &stream_update, 177 state); 178 } 179 180 /* link can be also enabled by vbios. In this case it is not recorded 181 * in pipe_ctx. Disable link phy here to make sure it is completely off 182 */ 183 dp_disable_link_phy(link, &link_res, link->connector_signal); 184 } 185 186 void link_resume(struct dc_link *link) 187 { 188 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 189 program_hpd_filter(link); 190 } 191 192 /* This function returns true if the pipe is used to feed video signal directly 193 * to the link. 194 */ 195 static bool is_master_pipe_for_link(const struct dc_link *link, 196 const struct pipe_ctx *pipe) 197 { 198 return resource_is_pipe_type(pipe, OTG_MASTER) && 199 pipe->stream->link == link; 200 } 201 202 /* 203 * This function finds all master pipes feeding to a given link with dpms set to 204 * on in given dc state. 205 */ 206 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 207 struct dc_state *state, 208 uint8_t *count, 209 struct pipe_ctx *pipes[MAX_PIPES]) 210 { 211 int i; 212 struct pipe_ctx *pipe = NULL; 213 214 *count = 0; 215 for (i = 0; i < MAX_PIPES; i++) { 216 pipe = &state->res_ctx.pipe_ctx[i]; 217 218 if (is_master_pipe_for_link(link, pipe) && 219 pipe->stream->dpms_off == false) { 220 pipes[(*count)++] = pipe; 221 } 222 } 223 } 224 225 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 226 enum engine_id eng_id, 227 struct ext_hdmi_settings *settings) 228 { 229 bool result = false; 230 int i = 0; 231 struct integrated_info *integrated_info = 232 pipe_ctx->stream->ctx->dc_bios->integrated_info; 233 234 if (integrated_info == NULL) 235 return false; 236 237 /* 238 * Get retimer settings from sbios for passing SI eye test for DCE11 239 * The setting values are varied based on board revision and port id 240 * Therefore the setting values of each ports is passed by sbios. 241 */ 242 243 // Check if current bios contains ext Hdmi settings 244 if (integrated_info->gpu_cap_info & 0x20) { 245 switch (eng_id) { 246 case ENGINE_ID_DIGA: 247 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 248 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 249 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 250 memmove(settings->reg_settings, 251 integrated_info->dp0_ext_hdmi_reg_settings, 252 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 253 memmove(settings->reg_settings_6g, 254 integrated_info->dp0_ext_hdmi_6g_reg_settings, 255 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 256 result = true; 257 break; 258 case ENGINE_ID_DIGB: 259 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 260 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 261 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 262 memmove(settings->reg_settings, 263 integrated_info->dp1_ext_hdmi_reg_settings, 264 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 265 memmove(settings->reg_settings_6g, 266 integrated_info->dp1_ext_hdmi_6g_reg_settings, 267 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 268 result = true; 269 break; 270 case ENGINE_ID_DIGC: 271 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 272 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 273 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 274 memmove(settings->reg_settings, 275 integrated_info->dp2_ext_hdmi_reg_settings, 276 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 277 memmove(settings->reg_settings_6g, 278 integrated_info->dp2_ext_hdmi_6g_reg_settings, 279 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 280 result = true; 281 break; 282 case ENGINE_ID_DIGD: 283 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 284 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 285 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 286 memmove(settings->reg_settings, 287 integrated_info->dp3_ext_hdmi_reg_settings, 288 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 289 memmove(settings->reg_settings_6g, 290 integrated_info->dp3_ext_hdmi_6g_reg_settings, 291 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 292 result = true; 293 break; 294 default: 295 break; 296 } 297 298 if (result == true) { 299 // Validate settings from bios integrated info table 300 if (settings->slv_addr == 0) 301 return false; 302 if (settings->reg_num > 9) 303 return false; 304 if (settings->reg_num_6g > 3) 305 return false; 306 307 for (i = 0; i < settings->reg_num; i++) { 308 if (settings->reg_settings[i].i2c_reg_index > 0x20) 309 return false; 310 } 311 312 for (i = 0; i < settings->reg_num_6g; i++) { 313 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 314 return false; 315 } 316 } 317 } 318 319 return result; 320 } 321 322 static bool write_i2c(struct pipe_ctx *pipe_ctx, 323 uint8_t address, uint8_t *buffer, uint32_t length) 324 { 325 struct i2c_command cmd = {0}; 326 struct i2c_payload payload = {0}; 327 328 memset(&payload, 0, sizeof(payload)); 329 memset(&cmd, 0, sizeof(cmd)); 330 331 cmd.number_of_payloads = 1; 332 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 333 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 334 335 payload.address = address; 336 payload.data = buffer; 337 payload.length = length; 338 payload.write = true; 339 cmd.payloads = &payload; 340 341 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 342 pipe_ctx->stream->link, &cmd)) 343 return true; 344 345 return false; 346 } 347 348 static void write_i2c_retimer_setting( 349 struct pipe_ctx *pipe_ctx, 350 bool is_vga_mode, 351 bool is_over_340mhz, 352 struct ext_hdmi_settings *settings) 353 { 354 uint8_t slave_address = (settings->slv_addr >> 1); 355 uint8_t buffer[2]; 356 const uint8_t apply_rx_tx_change = 0x4; 357 uint8_t offset = 0xA; 358 uint8_t value = 0; 359 int i = 0; 360 bool i2c_success = false; 361 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 362 363 memset(&buffer, 0, sizeof(buffer)); 364 365 /* Start Ext-Hdmi programming*/ 366 367 for (i = 0; i < settings->reg_num; i++) { 368 /* Apply 3G settings */ 369 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 370 371 buffer[0] = settings->reg_settings[i].i2c_reg_index; 372 buffer[1] = settings->reg_settings[i].i2c_reg_val; 373 i2c_success = write_i2c(pipe_ctx, slave_address, 374 buffer, sizeof(buffer)); 375 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 376 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 377 slave_address, buffer[0], buffer[1], i2c_success?1:0); 378 379 if (!i2c_success) 380 goto i2c_write_fail; 381 382 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 383 * needs to be set to 1 on every 0xA-0xC write. 384 */ 385 if (settings->reg_settings[i].i2c_reg_index == 0xA || 386 settings->reg_settings[i].i2c_reg_index == 0xB || 387 settings->reg_settings[i].i2c_reg_index == 0xC) { 388 389 /* Query current value from offset 0xA */ 390 if (settings->reg_settings[i].i2c_reg_index == 0xA) 391 value = settings->reg_settings[i].i2c_reg_val; 392 else { 393 i2c_success = 394 link_query_ddc_data( 395 pipe_ctx->stream->link->ddc, 396 slave_address, &offset, 1, &value, 1); 397 if (!i2c_success) 398 goto i2c_write_fail; 399 } 400 401 buffer[0] = offset; 402 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 403 buffer[1] = value | apply_rx_tx_change; 404 i2c_success = write_i2c(pipe_ctx, slave_address, 405 buffer, sizeof(buffer)); 406 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 407 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 408 slave_address, buffer[0], buffer[1], i2c_success?1:0); 409 if (!i2c_success) 410 goto i2c_write_fail; 411 } 412 } 413 } 414 415 /* Apply 3G settings */ 416 if (is_over_340mhz) { 417 for (i = 0; i < settings->reg_num_6g; i++) { 418 /* Apply 3G settings */ 419 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 420 421 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 422 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 423 i2c_success = write_i2c(pipe_ctx, slave_address, 424 buffer, sizeof(buffer)); 425 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 426 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 427 slave_address, buffer[0], buffer[1], i2c_success?1:0); 428 429 if (!i2c_success) 430 goto i2c_write_fail; 431 432 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 433 * needs to be set to 1 on every 0xA-0xC write. 434 */ 435 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 436 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 437 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 438 439 /* Query current value from offset 0xA */ 440 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 441 value = settings->reg_settings_6g[i].i2c_reg_val; 442 else { 443 i2c_success = 444 link_query_ddc_data( 445 pipe_ctx->stream->link->ddc, 446 slave_address, &offset, 1, &value, 1); 447 if (!i2c_success) 448 goto i2c_write_fail; 449 } 450 451 buffer[0] = offset; 452 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 453 buffer[1] = value | apply_rx_tx_change; 454 i2c_success = write_i2c(pipe_ctx, slave_address, 455 buffer, sizeof(buffer)); 456 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 457 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 458 slave_address, buffer[0], buffer[1], i2c_success?1:0); 459 if (!i2c_success) 460 goto i2c_write_fail; 461 } 462 } 463 } 464 } 465 466 if (is_vga_mode) { 467 /* Program additional settings if using 640x480 resolution */ 468 469 /* Write offset 0xFF to 0x01 */ 470 buffer[0] = 0xff; 471 buffer[1] = 0x01; 472 i2c_success = write_i2c(pipe_ctx, slave_address, 473 buffer, sizeof(buffer)); 474 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 475 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 476 slave_address, buffer[0], buffer[1], i2c_success?1:0); 477 if (!i2c_success) 478 goto i2c_write_fail; 479 480 /* Write offset 0x00 to 0x23 */ 481 buffer[0] = 0x00; 482 buffer[1] = 0x23; 483 i2c_success = write_i2c(pipe_ctx, slave_address, 484 buffer, sizeof(buffer)); 485 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 486 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 487 slave_address, buffer[0], buffer[1], i2c_success?1:0); 488 if (!i2c_success) 489 goto i2c_write_fail; 490 491 /* Write offset 0xff to 0x00 */ 492 buffer[0] = 0xff; 493 buffer[1] = 0x00; 494 i2c_success = write_i2c(pipe_ctx, slave_address, 495 buffer, sizeof(buffer)); 496 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 497 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 498 slave_address, buffer[0], buffer[1], i2c_success?1:0); 499 if (!i2c_success) 500 goto i2c_write_fail; 501 502 } 503 504 return; 505 506 i2c_write_fail: 507 DC_LOG_DEBUG("Set retimer failed"); 508 } 509 510 static void write_i2c_default_retimer_setting( 511 struct pipe_ctx *pipe_ctx, 512 bool is_vga_mode, 513 bool is_over_340mhz) 514 { 515 uint8_t slave_address = (0xBA >> 1); 516 uint8_t buffer[2]; 517 bool i2c_success = false; 518 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 519 520 memset(&buffer, 0, sizeof(buffer)); 521 522 /* Program Slave Address for tuning single integrity */ 523 /* Write offset 0x0A to 0x13 */ 524 buffer[0] = 0x0A; 525 buffer[1] = 0x13; 526 i2c_success = write_i2c(pipe_ctx, slave_address, 527 buffer, sizeof(buffer)); 528 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 529 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 530 slave_address, buffer[0], buffer[1], i2c_success?1:0); 531 if (!i2c_success) 532 goto i2c_write_fail; 533 534 /* Write offset 0x0A to 0x17 */ 535 buffer[0] = 0x0A; 536 buffer[1] = 0x17; 537 i2c_success = write_i2c(pipe_ctx, slave_address, 538 buffer, sizeof(buffer)); 539 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 540 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 541 slave_address, buffer[0], buffer[1], i2c_success?1:0); 542 if (!i2c_success) 543 goto i2c_write_fail; 544 545 /* Write offset 0x0B to 0xDA or 0xD8 */ 546 buffer[0] = 0x0B; 547 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 548 i2c_success = write_i2c(pipe_ctx, slave_address, 549 buffer, sizeof(buffer)); 550 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 551 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 552 slave_address, buffer[0], buffer[1], i2c_success?1:0); 553 if (!i2c_success) 554 goto i2c_write_fail; 555 556 /* Write offset 0x0A to 0x17 */ 557 buffer[0] = 0x0A; 558 buffer[1] = 0x17; 559 i2c_success = write_i2c(pipe_ctx, slave_address, 560 buffer, sizeof(buffer)); 561 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 562 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 563 slave_address, buffer[0], buffer[1], i2c_success?1:0); 564 if (!i2c_success) 565 goto i2c_write_fail; 566 567 /* Write offset 0x0C to 0x1D or 0x91 */ 568 buffer[0] = 0x0C; 569 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 570 i2c_success = write_i2c(pipe_ctx, slave_address, 571 buffer, sizeof(buffer)); 572 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 573 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 574 slave_address, buffer[0], buffer[1], i2c_success?1:0); 575 if (!i2c_success) 576 goto i2c_write_fail; 577 578 /* Write offset 0x0A to 0x17 */ 579 buffer[0] = 0x0A; 580 buffer[1] = 0x17; 581 i2c_success = write_i2c(pipe_ctx, slave_address, 582 buffer, sizeof(buffer)); 583 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 584 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 585 slave_address, buffer[0], buffer[1], i2c_success?1:0); 586 if (!i2c_success) 587 goto i2c_write_fail; 588 589 590 if (is_vga_mode) { 591 /* Program additional settings if using 640x480 resolution */ 592 593 /* Write offset 0xFF to 0x01 */ 594 buffer[0] = 0xff; 595 buffer[1] = 0x01; 596 i2c_success = write_i2c(pipe_ctx, slave_address, 597 buffer, sizeof(buffer)); 598 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 599 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 600 slave_address, buffer[0], buffer[1], i2c_success?1:0); 601 if (!i2c_success) 602 goto i2c_write_fail; 603 604 /* Write offset 0x00 to 0x23 */ 605 buffer[0] = 0x00; 606 buffer[1] = 0x23; 607 i2c_success = write_i2c(pipe_ctx, slave_address, 608 buffer, sizeof(buffer)); 609 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 610 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 611 slave_address, buffer[0], buffer[1], i2c_success?1:0); 612 if (!i2c_success) 613 goto i2c_write_fail; 614 615 /* Write offset 0xff to 0x00 */ 616 buffer[0] = 0xff; 617 buffer[1] = 0x00; 618 i2c_success = write_i2c(pipe_ctx, slave_address, 619 buffer, sizeof(buffer)); 620 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 621 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 622 slave_address, buffer[0], buffer[1], i2c_success?1:0); 623 if (!i2c_success) 624 goto i2c_write_fail; 625 } 626 627 return; 628 629 i2c_write_fail: 630 DC_LOG_DEBUG("Set default retimer failed"); 631 } 632 633 static void write_i2c_redriver_setting( 634 struct pipe_ctx *pipe_ctx, 635 bool is_over_340mhz) 636 { 637 uint8_t slave_address = (0xF0 >> 1); 638 uint8_t buffer[16]; 639 bool i2c_success = false; 640 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 641 642 memset(&buffer, 0, sizeof(buffer)); 643 644 // Program Slave Address for tuning single integrity 645 buffer[3] = 0x4E; 646 buffer[4] = 0x4E; 647 buffer[5] = 0x4E; 648 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 649 650 i2c_success = write_i2c(pipe_ctx, slave_address, 651 buffer, sizeof(buffer)); 652 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 653 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 654 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 655 i2c_success = %d\n", 656 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 657 658 if (!i2c_success) 659 DC_LOG_DEBUG("Set redriver failed"); 660 } 661 662 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 663 { 664 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 665 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 666 struct cp_psp_stream_config config = {0}; 667 enum dp_panel_mode panel_mode = 668 dp_get_panel_mode(pipe_ctx->stream->link); 669 670 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 671 return; 672 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 673 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 674 ASSERT(link_enc); 675 if (link_enc == NULL) 676 return; 677 678 /* otg instance */ 679 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 680 681 /* dig front end */ 682 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 683 684 /* stream encoder index */ 685 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 686 if (dp_is_128b_132b_signal(pipe_ctx)) 687 config.stream_enc_idx = 688 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 689 690 /* dig back end */ 691 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 692 693 /* link encoder index */ 694 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 695 if (dp_is_128b_132b_signal(pipe_ctx)) 696 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 697 698 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 699 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 700 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 701 else 702 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 703 704 705 /* phy index */ 706 config.phy_idx = resource_transmitter_to_phy_idx( 707 pipe_ctx->stream->link->dc, link_enc->transmitter); 708 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 709 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 710 config.phy_idx = 0; 711 712 /* stream properties */ 713 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 714 config.mst_enabled = (pipe_ctx->stream->signal == 715 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 716 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 717 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 718 1 : 0; 719 config.dpms_off = dpms_off; 720 721 /* dm stream context */ 722 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 723 724 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 725 } 726 727 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 728 { 729 struct dc *dc = pipe_ctx->stream->ctx->dc; 730 731 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 732 return; 733 734 dc->hwss.set_avmute(pipe_ctx, enable); 735 } 736 737 static void enable_mst_on_sink(struct dc_link *link, bool enable) 738 { 739 unsigned char mstmCntl = 0; 740 741 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 742 if (enable) 743 mstmCntl |= DP_MST_EN; 744 else 745 mstmCntl &= (~DP_MST_EN); 746 747 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 748 } 749 750 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 751 struct dsc_optc_config *config) 752 { 753 uint32_t precision = 1 << 28; 754 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 755 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 756 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 757 DC_LOGGER_INIT(dsc->ctx->logger); 758 759 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 760 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 761 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 762 */ 763 ll_bytes_per_pix_fraq *= 10000000; 764 ll_bytes_per_pix_fraq /= precision; 765 766 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 767 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 768 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 769 DC_LOG_DSC("\tslice_width %d", config->slice_width); 770 } 771 772 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 773 { 774 struct dc *dc = pipe_ctx->stream->ctx->dc; 775 struct dc_stream_state *stream = pipe_ctx->stream; 776 bool result = false; 777 778 if (dc_is_virtual_signal(stream->signal)) 779 result = true; 780 else 781 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 782 return result; 783 } 784 785 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 786 { 787 struct dc *dc = pipe_ctx->stream->ctx->dc; 788 struct dc_stream_state *stream = pipe_ctx->stream; 789 bool result = false; 790 791 if (dc_is_virtual_signal(stream->signal)) 792 result = true; 793 else 794 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 795 return result; 796 } 797 798 799 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 800 * i.e. after dp_enable_dsc_on_rx() had been called 801 */ 802 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 803 { 804 /* TODO: Move this to HWSS as this is hardware programming sequence not a 805 * link layer sequence 806 */ 807 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 808 struct dc *dc = pipe_ctx->stream->ctx->dc; 809 struct dc_stream_state *stream = pipe_ctx->stream; 810 struct pipe_ctx *odm_pipe; 811 int opp_cnt = 1; 812 struct dccg *dccg = dc->res_pool->dccg; 813 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 814 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 815 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 816 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 817 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 818 * this problem. We are implementing a workaround here to keep using dscclk 819 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 820 * 48Mhz) pixel clock to avoid hitting this problem. 821 */ 822 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 823 stream->timing.pix_clk_100hz > 480000; 824 DC_LOGGER_INIT(dsc->ctx->logger); 825 826 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 827 opp_cnt++; 828 829 if (enable) { 830 struct dsc_config dsc_cfg; 831 struct dsc_optc_config dsc_optc_cfg = {0}; 832 enum optc_dsc_mode optc_dsc_mode; 833 834 /* Enable DSC hw block */ 835 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + 836 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 837 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 838 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 839 dsc_cfg.color_depth = stream->timing.display_color_depth; 840 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 841 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 842 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 843 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 844 dsc_cfg.dsc_padding = 0; 845 846 if (should_use_dto_dscclk) 847 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 848 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 849 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 850 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 851 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 852 853 if (should_use_dto_dscclk) 854 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 855 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 856 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 857 } 858 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 859 dsc_cfg.pic_width *= opp_cnt; 860 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 861 862 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 863 864 /* Enable DSC in encoder */ 865 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 866 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 867 dsc_optc_config_log(dsc, &dsc_optc_cfg); 868 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 869 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 870 optc_dsc_mode, 871 dsc_optc_cfg.bytes_per_pixel, 872 dsc_optc_cfg.slice_width); 873 874 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 875 } 876 877 /* Enable DSC in OPTC */ 878 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 879 dsc_optc_config_log(dsc, &dsc_optc_cfg); 880 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 881 optc_dsc_mode, 882 dsc_optc_cfg.bytes_per_pixel, 883 dsc_optc_cfg.slice_width); 884 } else { 885 /* disable DSC in OPTC */ 886 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 887 pipe_ctx->stream_res.tg, 888 OPTC_DSC_DISABLED, 0, 0); 889 890 /* disable DSC in stream encoder */ 891 if (dc_is_dp_signal(stream->signal)) { 892 if (dp_is_128b_132b_signal(pipe_ctx)) 893 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 894 pipe_ctx->stream_res.hpo_dp_stream_enc, 895 false, 896 NULL, 897 true); 898 else { 899 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 900 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 901 pipe_ctx->stream_res.stream_enc, 902 OPTC_DSC_DISABLED, 0, 0); 903 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 904 pipe_ctx->stream_res.stream_enc, false, NULL, true); 905 } 906 } 907 908 /* disable DSC block */ 909 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 910 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 911 /* 912 * TODO - dsc_disconnect is a double buffered register. 913 * by the time we call dsc_disable, dsc may still remain 914 * connected to OPP. In this case OPTC will no longer 915 * get correct pixel data because DSCC is off. However 916 * we also can't wait for the disconnect pending 917 * complete, because this function can be called 918 * with/without OTG master lock acquired. When the lock 919 * is acquired we will never get pending complete until 920 * we release the lock later. So there is no easy way to 921 * solve this problem especially when the lock is 922 * acquired. DSC is a front end hw block it should be 923 * programmed as part of front end sequence, where the 924 * commit sequence without lock and update sequence 925 * with lock are completely separated. However because 926 * we are programming dsc as part of back end link 927 * programming sequence, we don't know if front end OPTC 928 * master lock is acquired. The back end should be 929 * agnostic to front end lock. DSC programming shouldn't 930 * belong to this sequence. 931 */ 932 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 933 if (dccg->funcs->set_ref_dscclk) 934 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 935 } 936 } 937 } 938 939 /* 940 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 941 * hence PPS info packet update need to use frame update instead of immediate update. 942 * Added parameter immediate_update for this purpose. 943 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 944 * which is the only place where a "false" would be passed in for param immediate_update. 945 * 946 * immediate_update is only applicable when DSC is enabled. 947 */ 948 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 949 { 950 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 951 struct dc_stream_state *stream = pipe_ctx->stream; 952 953 if (!pipe_ctx->stream->timing.flags.DSC) 954 return false; 955 956 if (!dsc) 957 return false; 958 959 DC_LOGGER_INIT(dsc->ctx->logger); 960 961 if (enable) { 962 struct dsc_config dsc_cfg; 963 uint8_t dsc_packed_pps[128]; 964 965 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 966 memset(dsc_packed_pps, 0, 128); 967 968 /* Enable DSC hw block */ 969 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 970 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 971 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 972 dsc_cfg.color_depth = stream->timing.display_color_depth; 973 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 974 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 975 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 976 977 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 978 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 979 if (dc_is_dp_signal(stream->signal)) { 980 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 981 if (dp_is_128b_132b_signal(pipe_ctx)) 982 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 983 pipe_ctx->stream_res.hpo_dp_stream_enc, 984 true, 985 &dsc_packed_pps[0], 986 immediate_update); 987 else 988 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 989 pipe_ctx->stream_res.stream_enc, 990 true, 991 &dsc_packed_pps[0], 992 immediate_update); 993 } 994 } else { 995 /* disable DSC PPS in stream encoder */ 996 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 997 if (dc_is_dp_signal(stream->signal)) { 998 if (dp_is_128b_132b_signal(pipe_ctx)) 999 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 1000 pipe_ctx->stream_res.hpo_dp_stream_enc, 1001 false, 1002 NULL, 1003 true); 1004 else 1005 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 1006 pipe_ctx->stream_res.stream_enc, false, NULL, true); 1007 } 1008 } 1009 1010 return true; 1011 } 1012 1013 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 1014 { 1015 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1016 bool result = false; 1017 1018 if (!pipe_ctx->stream->timing.flags.DSC) 1019 goto out; 1020 if (!dsc) 1021 goto out; 1022 1023 if (enable) { 1024 { 1025 link_set_dsc_on_stream(pipe_ctx, true); 1026 result = true; 1027 } 1028 } else { 1029 dp_set_dsc_on_rx(pipe_ctx, false); 1030 link_set_dsc_on_stream(pipe_ctx, false); 1031 result = true; 1032 } 1033 out: 1034 return result; 1035 } 1036 1037 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 1038 { 1039 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1040 1041 if (!pipe_ctx->stream->timing.flags.DSC) 1042 return false; 1043 if (!dsc) 1044 return false; 1045 1046 link_set_dsc_on_stream(pipe_ctx, true); 1047 link_set_dsc_pps_packet(pipe_ctx, true, false); 1048 return true; 1049 } 1050 1051 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1052 { 1053 struct dc_stream_state *stream = pipe_ctx->stream; 1054 1055 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1056 struct dc_link *link = stream->link; 1057 union down_spread_ctrl old_downspread; 1058 union down_spread_ctrl new_downspread; 1059 1060 memset(&old_downspread, 0, sizeof(old_downspread)); 1061 1062 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1063 &old_downspread.raw, sizeof(old_downspread)); 1064 1065 new_downspread.raw = old_downspread.raw; 1066 1067 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1068 (stream->ignore_msa_timing_param) ? 1 : 0; 1069 1070 if (new_downspread.raw != old_downspread.raw) { 1071 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1072 &new_downspread.raw, sizeof(new_downspread)); 1073 } 1074 1075 } else { 1076 dm_helpers_mst_enable_stream_features(stream); 1077 } 1078 } 1079 1080 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1081 { 1082 const uint32_t VCP_Y_PRECISION = 1000; 1083 uint64_t vcp_x, vcp_y; 1084 DC_LOGGER_INIT(link->ctx->logger); 1085 1086 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1087 avg_time_slots_per_mtp = dc_fixpt_add( 1088 avg_time_slots_per_mtp, 1089 dc_fixpt_from_fraction( 1090 1, 1091 2*VCP_Y_PRECISION)); 1092 1093 vcp_x = dc_fixpt_floor( 1094 avg_time_slots_per_mtp); 1095 vcp_y = dc_fixpt_floor( 1096 dc_fixpt_mul_int( 1097 dc_fixpt_sub_int( 1098 avg_time_slots_per_mtp, 1099 dc_fixpt_floor( 1100 avg_time_slots_per_mtp)), 1101 VCP_Y_PRECISION)); 1102 1103 1104 if (link->type == dc_connection_mst_branch) 1105 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1106 "X: %llu " 1107 "Y: %llu/%d", 1108 vcp_x, 1109 vcp_y, 1110 VCP_Y_PRECISION); 1111 else 1112 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1113 "X: %llu " 1114 "Y: %llu/%d", 1115 vcp_x, 1116 vcp_y, 1117 VCP_Y_PRECISION); 1118 } 1119 1120 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1121 { 1122 struct fixed31_32 mbytes_per_sec; 1123 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1124 &stream->link->cur_link_settings); 1125 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1126 1127 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1128 1129 return dc_fixpt_div_int(mbytes_per_sec, 54); 1130 } 1131 1132 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1133 { 1134 struct fixed31_32 peak_kbps; 1135 uint32_t numerator = 0; 1136 uint32_t denominator = 1; 1137 1138 /* 1139 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1140 * required when determining PBN/time slot utilization on the link between 1141 * us and the branch, since that overhead is already accounted for in 1142 * the get_pbn_per_slot function. 1143 * 1144 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1145 * common multiplier to render an integer PBN for all link rate/lane 1146 * counts combinations 1147 * calculate 1148 * peak_kbps *= (64/54) 1149 * peak_kbps /= (8 * 1000) convert to bytes 1150 */ 1151 1152 numerator = 64; 1153 denominator = 54 * 8 * 1000; 1154 kbps *= numerator; 1155 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1156 1157 return peak_kbps; 1158 } 1159 1160 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1161 { 1162 uint64_t kbps; 1163 enum dc_link_encoding_format link_encoding; 1164 1165 if (dp_is_128b_132b_signal(pipe_ctx)) 1166 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1167 else 1168 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1169 1170 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1171 return get_pbn_from_bw_in_kbps(kbps); 1172 } 1173 1174 1175 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1176 static void get_lane_status( 1177 struct dc_link *link, 1178 uint32_t lane_count, 1179 union lane_status *status, 1180 union lane_align_status_updated *status_updated) 1181 { 1182 unsigned int lane; 1183 uint8_t dpcd_buf[3] = {0}; 1184 1185 if (status == NULL || status_updated == NULL) { 1186 return; 1187 } 1188 1189 core_link_read_dpcd( 1190 link, 1191 DP_LANE0_1_STATUS, 1192 dpcd_buf, 1193 sizeof(dpcd_buf)); 1194 1195 for (lane = 0; lane < lane_count; lane++) { 1196 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1197 } 1198 1199 status_updated->raw = dpcd_buf[2]; 1200 } 1201 1202 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1203 { 1204 /* 1205 * wait for ACT handled 1206 */ 1207 int i; 1208 const int act_retries = 30; 1209 enum act_return_status result = ACT_FAILED; 1210 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1211 union payload_table_update_status update_status = {0}; 1212 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1213 union lane_align_status_updated lane_status_updated; 1214 DC_LOGGER_INIT(link->ctx->logger); 1215 1216 if (!display_connected || link->aux_access_disabled) 1217 return true; 1218 for (i = 0; i < act_retries; i++) { 1219 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1220 1221 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1222 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1223 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1224 !dp_is_interlane_aligned(lane_status_updated)) { 1225 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1226 "polling for ACT handled."); 1227 result = ACT_LINK_LOST; 1228 break; 1229 } 1230 core_link_read_dpcd( 1231 link, 1232 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1233 &update_status.raw, 1234 1); 1235 1236 if (update_status.bits.ACT_HANDLED == 1) { 1237 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1238 result = ACT_SUCCESS; 1239 break; 1240 } 1241 1242 fsleep(5000); 1243 } 1244 1245 if (result == ACT_FAILED) { 1246 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1247 "continue on. Something is wrong with the branch."); 1248 } 1249 1250 return (result == ACT_SUCCESS); 1251 } 1252 1253 static void update_mst_stream_alloc_table( 1254 struct dc_link *link, 1255 struct stream_encoder *stream_enc, 1256 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1257 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1258 { 1259 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1260 struct link_mst_stream_allocation *dc_alloc; 1261 1262 int i; 1263 int j; 1264 1265 /* if DRM proposed_table has more than one new payload */ 1266 ASSERT(proposed_table->stream_count - 1267 link->mst_stream_alloc_table.stream_count < 2); 1268 1269 /* copy proposed_table to link, add stream encoder */ 1270 for (i = 0; i < proposed_table->stream_count; i++) { 1271 1272 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1273 dc_alloc = 1274 &link->mst_stream_alloc_table.stream_allocations[j]; 1275 1276 if (dc_alloc->vcp_id == 1277 proposed_table->stream_allocations[i].vcp_id) { 1278 1279 work_table[i] = *dc_alloc; 1280 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1281 break; /* exit j loop */ 1282 } 1283 } 1284 1285 /* new vcp_id */ 1286 if (j == link->mst_stream_alloc_table.stream_count) { 1287 work_table[i].vcp_id = 1288 proposed_table->stream_allocations[i].vcp_id; 1289 work_table[i].slot_count = 1290 proposed_table->stream_allocations[i].slot_count; 1291 work_table[i].stream_enc = stream_enc; 1292 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1293 } 1294 } 1295 1296 /* update link->mst_stream_alloc_table with work_table */ 1297 link->mst_stream_alloc_table.stream_count = 1298 proposed_table->stream_count; 1299 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1300 link->mst_stream_alloc_table.stream_allocations[i] = 1301 work_table[i]; 1302 } 1303 1304 static void remove_stream_from_alloc_table( 1305 struct dc_link *link, 1306 struct stream_encoder *dio_stream_enc, 1307 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1308 { 1309 int i = 0; 1310 struct link_mst_stream_allocation_table *table = 1311 &link->mst_stream_alloc_table; 1312 1313 if (hpo_dp_stream_enc) { 1314 for (; i < table->stream_count; i++) 1315 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1316 break; 1317 } else { 1318 for (; i < table->stream_count; i++) 1319 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1320 break; 1321 } 1322 1323 if (i < table->stream_count) { 1324 i++; 1325 for (; i < table->stream_count; i++) 1326 table->stream_allocations[i-1] = table->stream_allocations[i]; 1327 memset(&table->stream_allocations[table->stream_count-1], 0, 1328 sizeof(struct link_mst_stream_allocation)); 1329 table->stream_count--; 1330 } 1331 } 1332 1333 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1334 { 1335 struct dc_stream_state *stream = pipe_ctx->stream; 1336 struct dc_link *link = stream->link; 1337 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1338 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1339 int i; 1340 bool mst_mode = (link->type == dc_connection_mst_branch); 1341 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1342 const struct dc_link_settings empty_link_settings = {0}; 1343 DC_LOGGER_INIT(link->ctx->logger); 1344 1345 /* deallocate_mst_payload is called before disable link. When mode or 1346 * disable/enable monitor, new stream is created which is not in link 1347 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1348 * should not done. For new mode set, map_resources will get engine 1349 * for new stream, so stream_enc->id should be validated until here. 1350 */ 1351 1352 /* slot X.Y */ 1353 if (link_hwss->ext.set_throttled_vcp_size) 1354 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1355 if (link_hwss->ext.set_hblank_min_symbol_width) 1356 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1357 &empty_link_settings, 1358 avg_time_slots_per_mtp); 1359 1360 if (mst_mode) { 1361 /* when link is in mst mode, reply on mst manager to remove 1362 * payload 1363 */ 1364 if (dm_helpers_dp_mst_write_payload_allocation_table( 1365 stream->ctx, 1366 stream, 1367 &proposed_table, 1368 false)) 1369 update_mst_stream_alloc_table( 1370 link, 1371 pipe_ctx->stream_res.stream_enc, 1372 pipe_ctx->stream_res.hpo_dp_stream_enc, 1373 &proposed_table); 1374 else 1375 DC_LOG_WARNING("Failed to update" 1376 "MST allocation table for" 1377 "pipe idx:%d\n", 1378 pipe_ctx->pipe_idx); 1379 } else { 1380 /* when link is no longer in mst mode (mst hub unplugged), 1381 * remove payload with default dc logic 1382 */ 1383 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1384 pipe_ctx->stream_res.hpo_dp_stream_enc); 1385 } 1386 1387 DC_LOG_MST("%s" 1388 "stream_count: %d: ", 1389 __func__, 1390 link->mst_stream_alloc_table.stream_count); 1391 1392 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1393 DC_LOG_MST("stream_enc[%d]: %p " 1394 "stream[%d].hpo_dp_stream_enc: %p " 1395 "stream[%d].vcp_id: %d " 1396 "stream[%d].slot_count: %d\n", 1397 i, 1398 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1399 i, 1400 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1401 i, 1402 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1403 i, 1404 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1405 } 1406 1407 /* update mst stream allocation table hardware state */ 1408 if (link_hwss->ext.update_stream_allocation_table == NULL || 1409 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1410 DC_LOG_DEBUG("Unknown encoding format\n"); 1411 return DC_ERROR_UNEXPECTED; 1412 } 1413 1414 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1415 &link->mst_stream_alloc_table); 1416 1417 if (mst_mode) 1418 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1419 stream->ctx, 1420 stream); 1421 1422 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1423 stream->ctx, 1424 stream); 1425 1426 return DC_OK; 1427 } 1428 1429 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1430 * because stream_encoder is not exposed to dm 1431 */ 1432 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1433 { 1434 struct dc_stream_state *stream = pipe_ctx->stream; 1435 struct dc_link *link = stream->link; 1436 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1437 struct fixed31_32 avg_time_slots_per_mtp; 1438 struct fixed31_32 pbn; 1439 struct fixed31_32 pbn_per_slot; 1440 int i; 1441 enum act_return_status ret; 1442 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1443 DC_LOGGER_INIT(link->ctx->logger); 1444 1445 /* enable_link_dp_mst already check link->enabled_stream_count 1446 * and stream is in link->stream[]. This is called during set mode, 1447 * stream_enc is available. 1448 */ 1449 1450 /* get calculate VC payload for stream: stream_alloc */ 1451 if (dm_helpers_dp_mst_write_payload_allocation_table( 1452 stream->ctx, 1453 stream, 1454 &proposed_table, 1455 true)) 1456 update_mst_stream_alloc_table( 1457 link, 1458 pipe_ctx->stream_res.stream_enc, 1459 pipe_ctx->stream_res.hpo_dp_stream_enc, 1460 &proposed_table); 1461 else 1462 DC_LOG_WARNING("Failed to update" 1463 "MST allocation table for" 1464 "pipe idx:%d\n", 1465 pipe_ctx->pipe_idx); 1466 1467 DC_LOG_MST("%s " 1468 "stream_count: %d: \n ", 1469 __func__, 1470 link->mst_stream_alloc_table.stream_count); 1471 1472 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1473 DC_LOG_MST("stream_enc[%d]: %p " 1474 "stream[%d].hpo_dp_stream_enc: %p " 1475 "stream[%d].vcp_id: %d " 1476 "stream[%d].slot_count: %d\n", 1477 i, 1478 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1479 i, 1480 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1481 i, 1482 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1483 i, 1484 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1485 } 1486 1487 ASSERT(proposed_table.stream_count > 0); 1488 1489 /* program DP source TX for payload */ 1490 if (link_hwss->ext.update_stream_allocation_table == NULL || 1491 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1492 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1493 return DC_ERROR_UNEXPECTED; 1494 } 1495 1496 link_hwss->ext.update_stream_allocation_table(link, 1497 &pipe_ctx->link_res, 1498 &link->mst_stream_alloc_table); 1499 1500 /* send down message */ 1501 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1502 stream->ctx, 1503 stream); 1504 1505 if (ret != ACT_LINK_LOST) 1506 dm_helpers_dp_mst_send_payload_allocation( 1507 stream->ctx, 1508 stream); 1509 1510 /* slot X.Y for only current stream */ 1511 pbn_per_slot = get_pbn_per_slot(stream); 1512 if (pbn_per_slot.value == 0) { 1513 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1514 return DC_UNSUPPORTED_VALUE; 1515 } 1516 pbn = get_pbn_from_timing(pipe_ctx); 1517 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1518 1519 log_vcp_x_y(link, avg_time_slots_per_mtp); 1520 1521 if (link_hwss->ext.set_throttled_vcp_size) 1522 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1523 if (link_hwss->ext.set_hblank_min_symbol_width) 1524 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1525 &link->cur_link_settings, 1526 avg_time_slots_per_mtp); 1527 1528 return DC_OK; 1529 } 1530 1531 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1532 const struct dc_stream_state *stream, 1533 const struct dc_link *link) 1534 { 1535 struct fixed31_32 link_bw_effective = 1536 dc_fixpt_from_int( 1537 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1538 struct fixed31_32 timeslot_bw_effective = 1539 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1540 struct fixed31_32 timing_bw = 1541 dc_fixpt_from_int( 1542 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1543 dc_link_get_highest_encoding_format(link))); 1544 struct fixed31_32 avg_time_slots_per_mtp = 1545 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1546 1547 return avg_time_slots_per_mtp; 1548 } 1549 1550 1551 static bool write_128b_132b_sst_payload_allocation_table( 1552 const struct dc_stream_state *stream, 1553 struct dc_link *link, 1554 struct link_mst_stream_allocation_table *proposed_table, 1555 bool allocate) 1556 { 1557 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1558 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1559 bool result = false; 1560 uint8_t req_slot_count = 0; 1561 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1562 union payload_table_update_status update_status = { 0 }; 1563 const uint32_t max_retries = 30; 1564 uint32_t retries = 0; 1565 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1566 DC_LOGGER_INIT(link->ctx->logger); 1567 1568 if (allocate) { 1569 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1570 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1571 /// Validation should filter out modes that exceed link BW 1572 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1573 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1574 return false; 1575 } else { 1576 /// Leave req_slot_count = 0 if allocate is false. 1577 } 1578 1579 proposed_table->stream_count = 1; /// Always 1 stream for SST 1580 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1581 proposed_table->stream_allocations[0].vcp_id = vc_id; 1582 1583 if (!display_connected || link->aux_access_disabled) 1584 return true; 1585 1586 /// Write DPCD 2C0 = 1 to start updating 1587 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1588 core_link_write_dpcd( 1589 link, 1590 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1591 &update_status.raw, 1592 1); 1593 1594 /// Program the changes in DPCD 1C0 - 1C2 1595 ASSERT(vc_id == 1); 1596 core_link_write_dpcd( 1597 link, 1598 DP_PAYLOAD_ALLOCATE_SET, 1599 &vc_id, 1600 1); 1601 1602 ASSERT(start_time_slot == 0); 1603 core_link_write_dpcd( 1604 link, 1605 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1606 &start_time_slot, 1607 1); 1608 1609 core_link_write_dpcd( 1610 link, 1611 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1612 &req_slot_count, 1613 1); 1614 1615 /// Poll till DPCD 2C0 read 1 1616 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1617 1618 while (retries < max_retries) { 1619 if (core_link_read_dpcd( 1620 link, 1621 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1622 &update_status.raw, 1623 1) == DC_OK) { 1624 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1625 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1626 result = true; 1627 break; 1628 } 1629 } else { 1630 union dpcd_rev dpcdRev = {0}; 1631 1632 if (core_link_read_dpcd( 1633 link, 1634 DP_DPCD_REV, 1635 &dpcdRev.raw, 1636 1) != DC_OK) { 1637 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1638 "of sink while polling payload table " 1639 "updated status bit."); 1640 break; 1641 } 1642 } 1643 retries++; 1644 fsleep(5000); 1645 } 1646 1647 if (!result && retries == max_retries) { 1648 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1649 "continue on. Something is wrong with the branch."); 1650 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1651 } 1652 1653 return result; 1654 } 1655 1656 /* 1657 * Payload allocation/deallocation for SST introduced in DP2.0 1658 */ 1659 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1660 bool allocate) 1661 { 1662 struct dc_stream_state *stream = pipe_ctx->stream; 1663 struct dc_link *link = stream->link; 1664 struct link_mst_stream_allocation_table proposed_table = {0}; 1665 struct fixed31_32 avg_time_slots_per_mtp; 1666 const struct dc_link_settings empty_link_settings = {0}; 1667 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1668 DC_LOGGER_INIT(link->ctx->logger); 1669 1670 /* slot X.Y for SST payload deallocate */ 1671 if (!allocate) { 1672 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1673 1674 log_vcp_x_y(link, avg_time_slots_per_mtp); 1675 1676 if (link_hwss->ext.set_throttled_vcp_size) 1677 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1678 avg_time_slots_per_mtp); 1679 if (link_hwss->ext.set_hblank_min_symbol_width) 1680 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1681 &empty_link_settings, 1682 avg_time_slots_per_mtp); 1683 } 1684 1685 /* calculate VC payload and update branch with new payload allocation table*/ 1686 if (!write_128b_132b_sst_payload_allocation_table( 1687 stream, 1688 link, 1689 &proposed_table, 1690 allocate)) { 1691 DC_LOG_ERROR("SST Update Payload: Failed to update " 1692 "allocation table for " 1693 "pipe idx: %d\n", 1694 pipe_ctx->pipe_idx); 1695 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1696 } 1697 1698 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1699 1700 ASSERT(proposed_table.stream_count == 1); 1701 1702 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1703 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1704 "vcp_id: %d " 1705 "slot_count: %d\n", 1706 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1707 proposed_table.stream_allocations[0].vcp_id, 1708 proposed_table.stream_allocations[0].slot_count); 1709 1710 /* program DP source TX for payload */ 1711 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1712 &proposed_table); 1713 1714 /* poll for ACT handled */ 1715 if (!poll_for_allocation_change_trigger(link)) { 1716 // Failures will result in blackscreen and errors logged 1717 BREAK_TO_DEBUGGER(); 1718 } 1719 1720 /* slot X.Y for SST payload allocate */ 1721 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1722 DP_128b_132b_ENCODING) { 1723 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1724 1725 log_vcp_x_y(link, avg_time_slots_per_mtp); 1726 1727 if (link_hwss->ext.set_throttled_vcp_size) 1728 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1729 avg_time_slots_per_mtp); 1730 if (link_hwss->ext.set_hblank_min_symbol_width) 1731 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1732 &link->cur_link_settings, 1733 avg_time_slots_per_mtp); 1734 } 1735 1736 /* Always return DC_OK. 1737 * If part of sequence fails, log failure(s) and show blackscreen 1738 */ 1739 return DC_OK; 1740 } 1741 1742 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1743 { 1744 struct dc_stream_state *stream = pipe_ctx->stream; 1745 struct dc_link *link = stream->link; 1746 struct fixed31_32 avg_time_slots_per_mtp; 1747 struct fixed31_32 pbn; 1748 struct fixed31_32 pbn_per_slot; 1749 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1750 uint8_t i; 1751 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1752 DC_LOGGER_INIT(link->ctx->logger); 1753 1754 /* decrease throttled vcp size */ 1755 pbn_per_slot = get_pbn_per_slot(stream); 1756 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1757 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1758 1759 if (link_hwss->ext.set_throttled_vcp_size) 1760 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1761 if (link_hwss->ext.set_hblank_min_symbol_width) 1762 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1763 &link->cur_link_settings, 1764 avg_time_slots_per_mtp); 1765 1766 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1767 dm_helpers_dp_mst_send_payload_allocation( 1768 stream->ctx, 1769 stream); 1770 1771 /* notify immediate branch device table update */ 1772 if (dm_helpers_dp_mst_write_payload_allocation_table( 1773 stream->ctx, 1774 stream, 1775 &proposed_table, 1776 true)) { 1777 /* update mst stream allocation table software state */ 1778 update_mst_stream_alloc_table( 1779 link, 1780 pipe_ctx->stream_res.stream_enc, 1781 pipe_ctx->stream_res.hpo_dp_stream_enc, 1782 &proposed_table); 1783 } else { 1784 DC_LOG_WARNING("Failed to update" 1785 "MST allocation table for" 1786 "pipe idx:%d\n", 1787 pipe_ctx->pipe_idx); 1788 } 1789 1790 DC_LOG_MST("%s " 1791 "stream_count: %d: \n ", 1792 __func__, 1793 link->mst_stream_alloc_table.stream_count); 1794 1795 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1796 DC_LOG_MST("stream_enc[%d]: %p " 1797 "stream[%d].hpo_dp_stream_enc: %p " 1798 "stream[%d].vcp_id: %d " 1799 "stream[%d].slot_count: %d\n", 1800 i, 1801 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1802 i, 1803 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1804 i, 1805 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1806 i, 1807 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1808 } 1809 1810 ASSERT(proposed_table.stream_count > 0); 1811 1812 /* update mst stream allocation table hardware state */ 1813 if (link_hwss->ext.update_stream_allocation_table == NULL || 1814 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1815 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1816 return DC_ERROR_UNEXPECTED; 1817 } 1818 1819 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1820 &link->mst_stream_alloc_table); 1821 1822 /* poll for immediate branch device ACT handled */ 1823 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1824 stream->ctx, 1825 stream); 1826 1827 return DC_OK; 1828 } 1829 1830 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1831 { 1832 struct dc_stream_state *stream = pipe_ctx->stream; 1833 struct dc_link *link = stream->link; 1834 struct fixed31_32 avg_time_slots_per_mtp; 1835 struct fixed31_32 pbn; 1836 struct fixed31_32 pbn_per_slot; 1837 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1838 uint8_t i; 1839 enum act_return_status ret; 1840 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1841 DC_LOGGER_INIT(link->ctx->logger); 1842 1843 /* notify immediate branch device table update */ 1844 if (dm_helpers_dp_mst_write_payload_allocation_table( 1845 stream->ctx, 1846 stream, 1847 &proposed_table, 1848 true)) { 1849 /* update mst stream allocation table software state */ 1850 update_mst_stream_alloc_table( 1851 link, 1852 pipe_ctx->stream_res.stream_enc, 1853 pipe_ctx->stream_res.hpo_dp_stream_enc, 1854 &proposed_table); 1855 } 1856 1857 DC_LOG_MST("%s " 1858 "stream_count: %d: \n ", 1859 __func__, 1860 link->mst_stream_alloc_table.stream_count); 1861 1862 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1863 DC_LOG_MST("stream_enc[%d]: %p " 1864 "stream[%d].hpo_dp_stream_enc: %p " 1865 "stream[%d].vcp_id: %d " 1866 "stream[%d].slot_count: %d\n", 1867 i, 1868 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1869 i, 1870 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1871 i, 1872 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1873 i, 1874 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1875 } 1876 1877 ASSERT(proposed_table.stream_count > 0); 1878 1879 /* update mst stream allocation table hardware state */ 1880 if (link_hwss->ext.update_stream_allocation_table == NULL || 1881 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1882 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1883 return DC_ERROR_UNEXPECTED; 1884 } 1885 1886 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1887 &link->mst_stream_alloc_table); 1888 1889 /* poll for immediate branch device ACT handled */ 1890 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1891 stream->ctx, 1892 stream); 1893 1894 if (ret != ACT_LINK_LOST) { 1895 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1896 dm_helpers_dp_mst_send_payload_allocation( 1897 stream->ctx, 1898 stream); 1899 } 1900 1901 /* increase throttled vcp size */ 1902 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1903 pbn_per_slot = get_pbn_per_slot(stream); 1904 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1905 1906 if (link_hwss->ext.set_throttled_vcp_size) 1907 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1908 if (link_hwss->ext.set_hblank_min_symbol_width) 1909 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1910 &link->cur_link_settings, 1911 avg_time_slots_per_mtp); 1912 1913 return DC_OK; 1914 } 1915 1916 static void disable_link_dp(struct dc_link *link, 1917 const struct link_resource *link_res, 1918 enum signal_type signal) 1919 { 1920 struct dc_link_settings link_settings = link->cur_link_settings; 1921 1922 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1923 link->mst_stream_alloc_table.stream_count > 0) 1924 /* disable MST link only when last vc payload is deallocated */ 1925 return; 1926 1927 dp_disable_link_phy(link, link_res, signal); 1928 1929 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1930 if (!link->skip_implict_edp_power_control) 1931 link->dc->hwss.edp_power_control(link, false); 1932 } 1933 1934 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->sink_count == 0) 1935 /* set the sink to SST mode after disabling the link */ 1936 enable_mst_on_sink(link, false); 1937 1938 if (link_dp_get_encoding_format(&link_settings) == 1939 DP_8b_10b_ENCODING) { 1940 dp_set_fec_enable(link, link_res, false); 1941 dp_set_fec_ready(link, link_res, false); 1942 } 1943 } 1944 1945 static void disable_link(struct dc_link *link, 1946 const struct link_resource *link_res, 1947 enum signal_type signal) 1948 { 1949 if (dc_is_dp_signal(signal)) { 1950 disable_link_dp(link, link_res, signal); 1951 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1952 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1953 } else { 1954 link->dc->hwss.disable_link_output(link, link_res, signal); 1955 } 1956 1957 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1958 /* MST disable link only when no stream use the link */ 1959 if (link->mst_stream_alloc_table.stream_count <= 0) 1960 link->link_status.link_active = false; 1961 } else { 1962 link->link_status.link_active = false; 1963 } 1964 } 1965 1966 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1967 { 1968 struct dc_stream_state *stream = pipe_ctx->stream; 1969 struct dc_link *link = stream->link; 1970 enum dc_color_depth display_color_depth; 1971 enum engine_id eng_id; 1972 struct ext_hdmi_settings settings = {0}; 1973 bool is_over_340mhz = false; 1974 bool is_vga_mode = (stream->timing.h_addressable == 640) 1975 && (stream->timing.v_addressable == 480); 1976 struct dc *dc = pipe_ctx->stream->ctx->dc; 1977 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1978 1979 if (stream->phy_pix_clk == 0) 1980 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1981 if (stream->phy_pix_clk > 340000) 1982 is_over_340mhz = true; 1983 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1984 ASSERT(false); 1985 return; 1986 } 1987 1988 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1989 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1990 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1991 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1992 /* DP159, Retimer settings */ 1993 eng_id = pipe_ctx->stream_res.stream_enc->id; 1994 1995 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1996 write_i2c_retimer_setting(pipe_ctx, 1997 is_vga_mode, is_over_340mhz, &settings); 1998 } else { 1999 write_i2c_default_retimer_setting(pipe_ctx, 2000 is_vga_mode, is_over_340mhz); 2001 } 2002 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2003 /* PI3EQX1204, Redriver settings */ 2004 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 2005 } 2006 } 2007 2008 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2009 write_scdc_data( 2010 stream->link->ddc, 2011 stream->phy_pix_clk, 2012 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2013 2014 memset(&stream->link->cur_link_settings, 0, 2015 sizeof(struct dc_link_settings)); 2016 2017 display_color_depth = stream->timing.display_color_depth; 2018 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2019 display_color_depth = COLOR_DEPTH_888; 2020 2021 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 2022 * character clock in case that beyond 340MHz. 2023 */ 2024 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 2025 link_hwss->setup_stream_encoder(pipe_ctx); 2026 2027 dc->hwss.enable_tmds_link_output( 2028 link, 2029 &pipe_ctx->link_res, 2030 pipe_ctx->stream->signal, 2031 pipe_ctx->clock_source->id, 2032 display_color_depth, 2033 stream->phy_pix_clk); 2034 2035 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2036 read_scdc_data(link->ddc); 2037 } 2038 2039 static enum dc_status enable_link_dp(struct dc_state *state, 2040 struct pipe_ctx *pipe_ctx) 2041 { 2042 struct dc_stream_state *stream = pipe_ctx->stream; 2043 enum dc_status status; 2044 bool skip_video_pattern; 2045 struct dc_link *link = stream->link; 2046 const struct dc_link_settings *link_settings = 2047 &pipe_ctx->link_config.dp_link_settings; 2048 bool fec_enable; 2049 int i; 2050 bool apply_seamless_boot_optimization = false; 2051 uint32_t bl_oled_enable_delay = 50; // in ms 2052 uint32_t post_oui_delay = 30; // 30ms 2053 /* Reduce link bandwidth between failed link training attempts. */ 2054 bool do_fallback = false; 2055 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2056 2057 // Increase retry count if attempting DP1.x on FIXED_VS link 2058 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2059 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2060 lt_attempts = 10; 2061 2062 // check for seamless boot 2063 for (i = 0; i < state->stream_count; i++) { 2064 if (state->streams[i]->apply_seamless_boot_optimization) { 2065 apply_seamless_boot_optimization = true; 2066 break; 2067 } 2068 } 2069 2070 /* Train with fallback when enabling DPIA link. Conventional links are 2071 * trained with fallback during sink detection. 2072 */ 2073 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2074 !link->dc->config.enable_dpia_pre_training) 2075 do_fallback = true; 2076 2077 /* 2078 * Temporary w/a to get DP2.0 link rates to work with SST. 2079 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2080 */ 2081 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2082 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2083 link->dc->debug.set_mst_en_for_sst) { 2084 enable_mst_on_sink(link, true); 2085 } else if (link->dpcd_caps.is_mst_capable && 2086 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2087 /* disable mst on sink */ 2088 enable_mst_on_sink(link, false); 2089 } 2090 2091 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2092 /*in case it is not on*/ 2093 if (!link->dc->config.edp_no_power_sequencing) 2094 link->dc->hwss.edp_power_control(link, true); 2095 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2096 } 2097 2098 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2099 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2100 } else { 2101 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2102 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2103 if (state->clk_mgr && !apply_seamless_boot_optimization) 2104 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2105 state, false); 2106 } 2107 2108 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2109 dpcd_set_source_specific_data(link); 2110 if (link->dpcd_sink_ext_caps.raw != 0) { 2111 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2112 msleep(post_oui_delay); 2113 } 2114 2115 // similarly, mode switch can cause loss of cable ID 2116 dpcd_write_cable_id_to_dprx(link); 2117 2118 skip_video_pattern = true; 2119 2120 if (link_settings->link_rate == LINK_RATE_LOW) 2121 skip_video_pattern = false; 2122 2123 if (stream->sink_patches.oled_optimize_display_on) 2124 set_default_brightness(link); 2125 2126 if (perform_link_training_with_retries(link_settings, 2127 skip_video_pattern, 2128 lt_attempts, 2129 pipe_ctx, 2130 pipe_ctx->stream->signal, 2131 do_fallback)) { 2132 status = DC_OK; 2133 } else { 2134 status = DC_FAIL_DP_LINK_TRAINING; 2135 } 2136 2137 if (link->preferred_training_settings.fec_enable) 2138 fec_enable = *link->preferred_training_settings.fec_enable; 2139 else 2140 fec_enable = true; 2141 2142 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2143 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 2144 2145 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2146 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2147 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2148 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2149 if (!stream->sink_patches.oled_optimize_display_on) { 2150 set_default_brightness(link); 2151 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2152 msleep(bl_oled_enable_delay); 2153 edp_backlight_enable_aux(link, true); 2154 } else { 2155 edp_backlight_enable_aux(link, true); 2156 } 2157 } 2158 2159 return status; 2160 } 2161 2162 static enum dc_status enable_link_edp( 2163 struct dc_state *state, 2164 struct pipe_ctx *pipe_ctx) 2165 { 2166 return enable_link_dp(state, pipe_ctx); 2167 } 2168 2169 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2170 { 2171 struct dc_stream_state *stream = pipe_ctx->stream; 2172 struct dc_link *link = stream->link; 2173 struct dc *dc = stream->ctx->dc; 2174 2175 if (stream->phy_pix_clk == 0) 2176 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2177 2178 memset(&stream->link->cur_link_settings, 0, 2179 sizeof(struct dc_link_settings)); 2180 dc->hwss.enable_lvds_link_output( 2181 link, 2182 &pipe_ctx->link_res, 2183 pipe_ctx->clock_source->id, 2184 stream->phy_pix_clk); 2185 2186 } 2187 2188 static enum dc_status enable_link_dp_mst( 2189 struct dc_state *state, 2190 struct pipe_ctx *pipe_ctx) 2191 { 2192 struct dc_link *link = pipe_ctx->stream->link; 2193 unsigned char mstm_cntl = 0; 2194 2195 /* sink signal type after MST branch is MST. Multiple MST sinks 2196 * share one link. Link DP PHY is enable or training only once. 2197 */ 2198 if (link->link_status.link_active) 2199 return DC_OK; 2200 2201 /* clear payload table */ 2202 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2203 if (mstm_cntl & DP_MST_EN) 2204 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2205 2206 /* to make sure the pending down rep can be processed 2207 * before enabling the link 2208 */ 2209 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2210 2211 /* set the sink to MST mode before enabling the link */ 2212 enable_mst_on_sink(link, true); 2213 2214 return enable_link_dp(state, pipe_ctx); 2215 } 2216 2217 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2218 { 2219 struct dc_link *link = pipe_ctx->stream->link; 2220 2221 link->dc->hwss.enable_dp_link_output(link, 2222 &pipe_ctx->link_res, 2223 SIGNAL_TYPE_DISPLAY_PORT, 2224 pipe_ctx->clock_source->id, 2225 &pipe_ctx->link_config.dp_link_settings); 2226 return DC_OK; 2227 } 2228 2229 static enum dc_status enable_link( 2230 struct dc_state *state, 2231 struct pipe_ctx *pipe_ctx) 2232 { 2233 enum dc_status status = DC_ERROR_UNEXPECTED; 2234 struct dc_stream_state *stream = pipe_ctx->stream; 2235 struct dc_link *link = NULL; 2236 2237 if (stream == NULL) 2238 return DC_ERROR_UNEXPECTED; 2239 link = stream->link; 2240 2241 /* There's some scenarios where driver is unloaded with display 2242 * still enabled. When driver is reloaded, it may cause a display 2243 * to not light up if there is a mismatch between old and new 2244 * link settings. Need to call disable first before enabling at 2245 * new link settings. 2246 */ 2247 if (link->link_status.link_active) 2248 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2249 2250 switch (pipe_ctx->stream->signal) { 2251 case SIGNAL_TYPE_DISPLAY_PORT: 2252 status = enable_link_dp(state, pipe_ctx); 2253 break; 2254 case SIGNAL_TYPE_EDP: 2255 status = enable_link_edp(state, pipe_ctx); 2256 break; 2257 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2258 status = enable_link_dp_mst(state, pipe_ctx); 2259 msleep(200); 2260 break; 2261 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2262 case SIGNAL_TYPE_DVI_DUAL_LINK: 2263 case SIGNAL_TYPE_HDMI_TYPE_A: 2264 enable_link_hdmi(pipe_ctx); 2265 status = DC_OK; 2266 break; 2267 case SIGNAL_TYPE_LVDS: 2268 enable_link_lvds(pipe_ctx); 2269 status = DC_OK; 2270 break; 2271 case SIGNAL_TYPE_RGB: 2272 status = DC_OK; 2273 break; 2274 case SIGNAL_TYPE_VIRTUAL: 2275 status = enable_link_virtual(pipe_ctx); 2276 break; 2277 default: 2278 break; 2279 } 2280 2281 if (status == DC_OK) { 2282 pipe_ctx->stream->link->link_status.link_active = true; 2283 } 2284 2285 return status; 2286 } 2287 2288 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2289 { 2290 struct dc_link *link = stream->sink->link; 2291 int req_bw = bw; 2292 2293 DC_LOGGER_INIT(link->ctx->logger); 2294 2295 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2296 return false; 2297 2298 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2299 int sink_index = 0; 2300 int i = 0; 2301 2302 for (i = 0; i < link->sink_count; i++) { 2303 if (link->remote_sinks[i] == NULL) 2304 continue; 2305 2306 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2307 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2308 else 2309 sink_index = i; 2310 } 2311 2312 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2313 } 2314 2315 link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); 2316 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2317 2318 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2319 2320 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2321 int i = 0; 2322 2323 for (i = 0; i < link->sink_count; i++) { 2324 if (link->remote_sinks[i] == NULL) 2325 continue; 2326 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2327 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2328 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2329 } 2330 } 2331 2332 return true; 2333 } 2334 2335 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2336 { 2337 bool ret; 2338 2339 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2340 dc_link_get_highest_encoding_format(stream->sink->link)); 2341 2342 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2343 2344 return ret; 2345 } 2346 2347 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2348 { 2349 bool ret; 2350 2351 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2352 2353 return ret; 2354 } 2355 2356 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2357 { 2358 struct dc *dc = pipe_ctx->stream->ctx->dc; 2359 struct dc_stream_state *stream = pipe_ctx->stream; 2360 struct dc_link *link = stream->sink->link; 2361 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2362 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2363 2364 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2365 2366 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2367 2368 if (dp_is_128b_132b_signal(pipe_ctx)) 2369 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2370 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2371 return; 2372 2373 if (pipe_ctx->stream->sink) { 2374 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2375 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2376 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2377 pipe_ctx->stream->sink->edid_caps.display_name, 2378 pipe_ctx->stream->signal, link->link_index, link->sink_count); 2379 } 2380 } 2381 2382 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2383 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2384 set_avmute(pipe_ctx, true); 2385 } 2386 2387 dc->hwss.disable_audio_stream(pipe_ctx); 2388 2389 update_psp_stream_config(pipe_ctx, true); 2390 dc->hwss.blank_stream(pipe_ctx); 2391 2392 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2393 deallocate_usb4_bandwidth(pipe_ctx->stream); 2394 2395 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2396 deallocate_mst_payload(pipe_ctx); 2397 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2398 dp_is_128b_132b_signal(pipe_ctx)) 2399 update_sst_payload(pipe_ctx, false); 2400 2401 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2402 struct ext_hdmi_settings settings = {0}; 2403 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2404 2405 unsigned short masked_chip_caps = link->chip_caps & 2406 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2407 //Need to inform that sink is going to use legacy HDMI mode. 2408 write_scdc_data( 2409 link->ddc, 2410 165000,//vbios only handles 165Mhz. 2411 false); 2412 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2413 /* DP159, Retimer settings */ 2414 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2415 write_i2c_retimer_setting(pipe_ctx, 2416 false, false, &settings); 2417 else 2418 write_i2c_default_retimer_setting(pipe_ctx, 2419 false, false); 2420 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2421 /* PI3EQX1204, Redriver settings */ 2422 write_i2c_redriver_setting(pipe_ctx, false); 2423 } 2424 } 2425 2426 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2427 !dp_is_128b_132b_signal(pipe_ctx)) { 2428 2429 /* In DP1.x SST mode, our encoder will go to TPS1 2430 * when link is on but stream is off. 2431 * Disabling link before stream will avoid exposing TPS1 pattern 2432 * during the disable sequence as it will confuse some receivers 2433 * state machine. 2434 * In DP2 or MST mode, our encoder will stay video active 2435 */ 2436 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2437 dc->hwss.disable_stream(pipe_ctx); 2438 } else { 2439 dc->hwss.disable_stream(pipe_ctx); 2440 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2441 } 2442 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2443 2444 if (pipe_ctx->stream->timing.flags.DSC) { 2445 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2446 link_set_dsc_enable(pipe_ctx, false); 2447 } 2448 if (dp_is_128b_132b_signal(pipe_ctx)) { 2449 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2450 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2451 } 2452 2453 if (vpg && vpg->funcs->vpg_powerdown) 2454 vpg->funcs->vpg_powerdown(vpg); 2455 2456 /* for psp not exist case */ 2457 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2458 /* reset internal save state to default since eDP is off */ 2459 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2460 /* since current psp not loaded, we need to reset it to default */ 2461 link->panel_mode = panel_mode; 2462 } 2463 } 2464 2465 void link_set_dpms_on( 2466 struct dc_state *state, 2467 struct pipe_ctx *pipe_ctx) 2468 { 2469 struct dc *dc = pipe_ctx->stream->ctx->dc; 2470 struct dc_stream_state *stream = pipe_ctx->stream; 2471 struct dc_link *link = stream->sink->link; 2472 enum dc_status status; 2473 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 2474 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2475 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2476 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2477 bool apply_edp_fast_boot_optimization = 2478 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2479 2480 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2481 2482 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2483 2484 if (dp_is_128b_132b_signal(pipe_ctx)) 2485 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2486 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2487 return; 2488 2489 if (pipe_ctx->stream->sink) { 2490 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2491 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2492 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2493 pipe_ctx->stream->sink->edid_caps.display_name, 2494 pipe_ctx->stream->signal, 2495 link->link_index, 2496 link->sink_count); 2497 } 2498 } 2499 2500 if (!dc->config.unify_link_enc_assignment) 2501 link_enc = link_enc_cfg_get_link_enc(link); 2502 ASSERT(link_enc); 2503 2504 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2505 && !dp_is_128b_132b_signal(pipe_ctx)) { 2506 if (link_enc) 2507 link_enc->funcs->setup( 2508 link_enc, 2509 pipe_ctx->stream->signal); 2510 } 2511 2512 pipe_ctx->stream->link->link_state_valid = true; 2513 2514 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2515 if (dp_is_128b_132b_signal(pipe_ctx)) 2516 otg_out_dest = OUT_MUX_HPO_DP; 2517 else 2518 otg_out_dest = OUT_MUX_DIO; 2519 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2520 } 2521 2522 link_hwss->setup_stream_attribute(pipe_ctx); 2523 2524 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2525 2526 // Enable VPG before building infoframe 2527 if (vpg && vpg->funcs->vpg_poweron) 2528 vpg->funcs->vpg_poweron(vpg); 2529 2530 resource_build_info_frame(pipe_ctx); 2531 dc->hwss.update_info_frame(pipe_ctx); 2532 2533 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2534 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2535 2536 /* Do not touch link on seamless boot optimization. */ 2537 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2538 pipe_ctx->stream->dpms_off = false; 2539 2540 /* Still enable stream features & audio on seamless boot for DP external displays */ 2541 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2542 enable_stream_features(pipe_ctx); 2543 dc->hwss.enable_audio_stream(pipe_ctx); 2544 } 2545 2546 update_psp_stream_config(pipe_ctx, false); 2547 return; 2548 } 2549 2550 /* eDP lit up by bios already, no need to enable again. */ 2551 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2552 apply_edp_fast_boot_optimization && 2553 !pipe_ctx->stream->timing.flags.DSC && 2554 !pipe_ctx->next_odm_pipe) { 2555 pipe_ctx->stream->dpms_off = false; 2556 update_psp_stream_config(pipe_ctx, false); 2557 2558 if (link->is_dds) { 2559 uint32_t post_oui_delay = 30; // 30ms 2560 2561 dpcd_set_source_specific_data(link); 2562 msleep(post_oui_delay); 2563 } 2564 2565 return; 2566 } 2567 2568 if (pipe_ctx->stream->dpms_off) 2569 return; 2570 2571 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2572 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2573 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2574 */ 2575 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2576 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2577 return; 2578 } 2579 2580 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2581 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2582 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2583 * will be automatically set at a later time when the video is enabled 2584 * (DP_VID_STREAM_EN = 1). 2585 */ 2586 if (pipe_ctx->stream->timing.flags.DSC) { 2587 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2588 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2589 link_set_dsc_enable(pipe_ctx, true); 2590 } 2591 2592 status = enable_link(state, pipe_ctx); 2593 2594 if (status != DC_OK) { 2595 DC_LOG_WARNING("enabling link %u failed: %d\n", 2596 pipe_ctx->stream->link->link_index, 2597 status); 2598 2599 /* Abort stream enable *unless* the failure was due to 2600 * DP link training - some DP monitors will recover and 2601 * show the stream anyway. But MST displays can't proceed 2602 * without link training. 2603 */ 2604 if (status != DC_FAIL_DP_LINK_TRAINING || 2605 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2606 if (false == stream->link->link_status.link_active) 2607 disable_link(stream->link, &pipe_ctx->link_res, 2608 pipe_ctx->stream->signal); 2609 BREAK_TO_DEBUGGER(); 2610 return; 2611 } 2612 } 2613 2614 /* turn off otg test pattern if enable */ 2615 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2616 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2617 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2618 COLOR_DEPTH_UNDEFINED); 2619 2620 /* This second call is needed to reconfigure the DIG 2621 * as a workaround for the incorrect value being applied 2622 * from transmitter control. 2623 */ 2624 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2625 dp_is_128b_132b_signal(pipe_ctx))) { 2626 2627 if (link_enc) 2628 link_enc->funcs->setup( 2629 link_enc, 2630 pipe_ctx->stream->signal); 2631 2632 } 2633 2634 dc->hwss.enable_stream(pipe_ctx); 2635 2636 /* Set DPS PPS SDP (AKA "info frames") */ 2637 if (pipe_ctx->stream->timing.flags.DSC) { 2638 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2639 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2640 dp_set_dsc_on_rx(pipe_ctx, true); 2641 link_set_dsc_pps_packet(pipe_ctx, true, true); 2642 } 2643 } 2644 2645 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2646 dp_set_hblank_reduction_on_rx(pipe_ctx); 2647 2648 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2649 allocate_usb4_bandwidth(pipe_ctx->stream); 2650 2651 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2652 allocate_mst_payload(pipe_ctx); 2653 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2654 dp_is_128b_132b_signal(pipe_ctx)) 2655 update_sst_payload(pipe_ctx, true); 2656 2657 /* Corruption was observed on systems with display mux when stream gets 2658 * enabled after the mux switch. Having a small delay between link 2659 * training and stream unblank resolves the corruption issue. 2660 * This is workaround. 2661 */ 2662 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2663 link->is_display_mux_present) 2664 msleep(20); 2665 2666 dc->hwss.unblank_stream(pipe_ctx, 2667 &pipe_ctx->stream->link->cur_link_settings); 2668 2669 if (stream->sink_patches.delay_ignore_msa > 0) 2670 msleep(stream->sink_patches.delay_ignore_msa); 2671 2672 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2673 enable_stream_features(pipe_ctx); 2674 update_psp_stream_config(pipe_ctx, false); 2675 2676 dc->hwss.enable_audio_stream(pipe_ctx); 2677 2678 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2679 set_avmute(pipe_ctx, false); 2680 } 2681 } 2682