1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_panel_replay.h" 50 #include "protocols/link_dp_dpia_bw.h" 51 52 #include "dm_helpers.h" 53 #include "link_enc_cfg.h" 54 #include "resource.h" 55 #include "dsc.h" 56 #include "dccg.h" 57 #include "clk_mgr.h" 58 #include "atomfirmware.h" 59 #include "vpg.h" 60 61 #define DC_LOGGER \ 62 dc_logger 63 #define DC_LOGGER_INIT(logger) \ 64 struct dal_logger *dc_logger = logger 65 66 #define LINK_INFO(...) \ 67 DC_LOG_HW_HOTPLUG( \ 68 __VA_ARGS__) 69 70 #define RETIMER_REDRIVER_INFO(...) \ 71 DC_LOG_RETIMER_REDRIVER( \ 72 __VA_ARGS__) 73 74 #define MAX_MTP_SLOT_COUNT 64 75 #define LINK_TRAINING_ATTEMPTS 4 76 #define PEAK_FACTOR_X1000 1006 77 78 void link_blank_all_dp_displays(struct dc *dc) 79 { 80 unsigned int i; 81 uint8_t dpcd_power_state = '\0'; 82 enum dc_status status = DC_ERROR_UNEXPECTED; 83 84 for (i = 0; i < dc->link_count; i++) { 85 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 86 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 87 continue; 88 89 /* DP 2.0 spec requires that we read LTTPR caps first */ 90 dp_retrieve_lttpr_cap(dc->links[i]); 91 /* if any of the displays are lit up turn them off */ 92 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 93 &dpcd_power_state, sizeof(dpcd_power_state)); 94 95 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 96 link_blank_dp_stream(dc->links[i], true); 97 } 98 99 } 100 101 void link_blank_all_edp_displays(struct dc *dc) 102 { 103 unsigned int i; 104 uint8_t dpcd_power_state = '\0'; 105 enum dc_status status = DC_ERROR_UNEXPECTED; 106 107 for (i = 0; i < dc->link_count; i++) { 108 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 109 (!dc->links[i]->edp_sink_present)) 110 continue; 111 112 /* if any of the displays are lit up turn them off */ 113 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 114 &dpcd_power_state, sizeof(dpcd_power_state)); 115 116 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 117 link_blank_dp_stream(dc->links[i], true); 118 } 119 } 120 121 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 122 { 123 unsigned int j; 124 struct dc *dc = link->ctx->dc; 125 enum signal_type signal = link->connector_signal; 126 127 if ((signal == SIGNAL_TYPE_EDP) || 128 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 129 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 130 link->link_enc->funcs->get_dig_frontend && 131 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 132 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 133 134 if (fe != ENGINE_ID_UNKNOWN) 135 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 136 if (fe == dc->res_pool->stream_enc[j]->id) { 137 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 138 dc->res_pool->stream_enc[j]); 139 break; 140 } 141 } 142 } 143 144 if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) && 145 (link->type != dc_connection_none)) 146 dpcd_write_rx_power_ctrl(link, false); 147 } 148 } 149 150 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 151 { 152 struct pipe_ctx *pipes[MAX_PIPES]; 153 struct dc_stream_state *streams[MAX_PIPES]; 154 struct dc_state *state = link->dc->current_state; 155 uint8_t count; 156 int i; 157 struct dc_stream_update stream_update; 158 bool dpms_off = true; 159 struct link_resource link_res = {0}; 160 161 memset(&stream_update, 0, sizeof(stream_update)); 162 stream_update.dpms_off = &dpms_off; 163 164 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 165 166 /* The subsequent call to dc_commit_updates_for_stream for a full update 167 * will release the current state and swap to a new state. Releasing the 168 * current state results in the stream pointers in the pipe_ctx structs 169 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream. 170 */ 171 for (i = 0; i < count; i++) 172 streams[i] = pipes[i]->stream; 173 174 for (i = 0; i < count; i++) { 175 stream_update.stream = streams[i]; 176 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 177 streams[i], &stream_update, 178 state); 179 } 180 181 /* link can be also enabled by vbios. In this case it is not recorded 182 * in pipe_ctx. Disable link phy here to make sure it is completely off 183 */ 184 if (dc_is_dp_signal(link->connector_signal)) 185 dp_disable_link_phy(link, &link_res, link->connector_signal); 186 } 187 188 void link_resume(struct dc_link *link) 189 { 190 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 191 program_hpd_filter(link); 192 } 193 194 /* This function returns true if the pipe is used to feed video signal directly 195 * to the link. 196 */ 197 static bool is_master_pipe_for_link(const struct dc_link *link, 198 const struct pipe_ctx *pipe) 199 { 200 return resource_is_pipe_type(pipe, OTG_MASTER) && 201 pipe->stream->link == link; 202 } 203 204 /* 205 * This function finds all master pipes feeding to a given link with dpms set to 206 * on in given dc state. 207 */ 208 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 209 struct dc_state *state, 210 uint8_t *count, 211 struct pipe_ctx *pipes[MAX_PIPES]) 212 { 213 int i; 214 struct pipe_ctx *pipe = NULL; 215 216 *count = 0; 217 for (i = 0; i < MAX_PIPES; i++) { 218 pipe = &state->res_ctx.pipe_ctx[i]; 219 220 if (is_master_pipe_for_link(link, pipe) && 221 pipe->stream->dpms_off == false) { 222 pipes[(*count)++] = pipe; 223 } 224 } 225 } 226 227 static struct ext_hdmi_settings create_ext_hdmi_settings( 228 uint8_t address, 229 uint8_t reg_num, 230 uint8_t reg_num_6g, 231 const struct i2c_reg_info *reg_settings, 232 const struct i2c_reg_info *reg_settings_6g 233 ) 234 { 235 struct ext_hdmi_settings result = { 236 .slv_addr = address, 237 .reg_num = reg_num, 238 .reg_num_6g = reg_num_6g, 239 }; 240 241 memcpy(result.reg_settings, reg_settings, sizeof(result.reg_settings)); 242 memcpy(result.reg_settings_6g, reg_settings_6g, sizeof(result.reg_settings_6g)); 243 return result; 244 } 245 246 static bool get_ext_hdmi_settings( 247 const struct integrated_info *info, 248 enum engine_id eng_id, 249 struct ext_hdmi_settings *settings 250 ) 251 { 252 if (!settings || !info) 253 return false; 254 255 /* 256 * Get retimer settings from sbios for passing SI eye test for DCE11 257 * The setting values are varied based on board revision and port id 258 * Therefore the setting values of each ports is passed by sbios. 259 */ 260 261 // Check if current bios contains ext Hdmi settings 262 if (!(info->gpu_cap_info & 0x20)) 263 return false; 264 265 switch (eng_id) { 266 case ENGINE_ID_DIGA: 267 *settings = create_ext_hdmi_settings( 268 info->dp0_ext_hdmi_slv_addr, 269 info->dp0_ext_hdmi_reg_num, 270 info->dp0_ext_hdmi_6g_reg_num, 271 info->dp0_ext_hdmi_reg_settings, 272 info->dp0_ext_hdmi_6g_reg_settings 273 ); 274 break; 275 case ENGINE_ID_DIGB: 276 *settings = create_ext_hdmi_settings( 277 info->dp1_ext_hdmi_slv_addr, 278 info->dp1_ext_hdmi_reg_num, 279 info->dp1_ext_hdmi_6g_reg_num, 280 info->dp1_ext_hdmi_reg_settings, 281 info->dp1_ext_hdmi_6g_reg_settings 282 ); 283 break; 284 case ENGINE_ID_DIGC: 285 *settings = create_ext_hdmi_settings( 286 info->dp2_ext_hdmi_slv_addr, 287 info->dp2_ext_hdmi_reg_num, 288 info->dp2_ext_hdmi_6g_reg_num, 289 info->dp2_ext_hdmi_reg_settings, 290 info->dp2_ext_hdmi_6g_reg_settings 291 ); 292 break; 293 case ENGINE_ID_DIGD: 294 *settings = create_ext_hdmi_settings( 295 info->dp3_ext_hdmi_slv_addr, 296 info->dp3_ext_hdmi_reg_num, 297 info->dp3_ext_hdmi_6g_reg_num, 298 info->dp3_ext_hdmi_reg_settings, 299 info->dp3_ext_hdmi_6g_reg_settings 300 ); 301 break; 302 default: 303 return false; 304 } 305 306 // Validate settings from bios integrated info table 307 if ( 308 !settings->slv_addr 309 || settings->reg_num > ARRAY_SIZE(settings->reg_settings) 310 || settings->reg_num_6g > ARRAY_SIZE(settings->reg_settings_6g) 311 ) { 312 return false; 313 } 314 315 for (size_t i = 0; i < settings->reg_num; i++) { 316 if (settings->reg_settings[i].i2c_reg_index > 0x20) 317 return false; 318 } 319 320 for (size_t i = 0; i < settings->reg_num_6g; i++) { 321 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 322 return false; 323 } 324 return true; 325 } 326 327 static bool write_i2c( 328 const struct dc_link *link, 329 uint8_t address, 330 uint8_t *buffer, 331 uint32_t length 332 ) 333 { 334 struct i2c_payload payload = { 335 .write = true, 336 .address = address, 337 .length = length, 338 .data = buffer, 339 }; 340 struct i2c_command cmd = { 341 .payloads = &payload, 342 .number_of_payloads = 1, 343 .engine = I2C_COMMAND_ENGINE_DEFAULT, 344 .speed = link->ctx->dc->caps.i2c_speed_in_khz, 345 }; 346 347 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 348 } 349 350 static bool write_i2c_retimer_offset_value( 351 const struct dc_link *link, 352 uint8_t address, 353 uint8_t offset, 354 uint8_t value 355 ) 356 { 357 DC_LOGGER_INIT(link->ctx->logger); 358 uint8_t buffer[] = { offset, value }; 359 const bool success = write_i2c(link, address, buffer, sizeof(buffer)); 360 361 RETIMER_REDRIVER_INFO( 362 "Retimer write, address: 0x%x, offset: 0x%x, value: 0x%x, success: %d\n", 363 address, offset, value, success 364 ); 365 return success; 366 } 367 368 static bool write_i2c_retimer_vga( 369 const struct dc_link *link, 370 uint8_t address 371 ) 372 { 373 DC_LOGGER_INIT(link->ctx->logger); 374 const uint8_t vga_data[][2] = { 375 { 0xFF, 0x01 }, 376 { 0x00, 0x23 }, 377 { 0xFF, 0x00 }, 378 }; 379 380 for (size_t i = 0; i < ARRAY_SIZE(vga_data); i++) { 381 if (!write_i2c_retimer_offset_value(link, address, vga_data[i][0], vga_data[i][1])) { 382 DC_LOG_ERROR("Set retimer failed, vga index: %zu\n", i); 383 return false; 384 } 385 } 386 return true; 387 } 388 389 static bool write_i2c_retimer_byte( 390 const struct dc_link *link, 391 uint8_t address, 392 uint8_t index, 393 uint8_t value 394 ) 395 { 396 DC_LOGGER_INIT(link->ctx->logger); 397 const uint8_t apply_rx_tx_change = 0x4; 398 399 if (index > 0x20) 400 return true; 401 402 if (!write_i2c_retimer_offset_value(link, address, index, value)) { 403 DC_LOG_ERROR("Set retimer failed, 3g index: 0x%x, value: 0x%x\n", index, value); 404 return false; 405 } 406 407 // Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 408 // needs to be set to 1 on every 0x0A-0x0C write. 409 if (0x0A <= index && index <= 0x0C) { 410 uint8_t offset = 0x0A; 411 412 // Query current value from offset 0x0A 413 if (index == 0x0A) { 414 // Just written correct value, so no need to read it back 415 } else { 416 if (!link_query_ddc_data( 417 link->ddc, address, &offset, 1, &value, 1 418 )) { 419 DC_LOG_ERROR("Set retimer failed, link_query_ddc_data\n"); 420 return false; 421 } 422 } 423 424 value |= apply_rx_tx_change; 425 if (!write_i2c_retimer_offset_value(link, address, offset, value)) { 426 DC_LOG_ERROR("Set retimer failed, 3g offset: 0x%x, value: 0x%x\n", offset, value); 427 return false; 428 } 429 } 430 return true; 431 } 432 433 static bool write_i2c_retimer_setting( 434 const struct dc_link *link, 435 bool is_vga_mode, 436 bool is_over_340mhz, 437 struct ext_hdmi_settings *settings) 438 { 439 DC_LOGGER_INIT(link->ctx->logger); 440 const uint8_t address = settings->slv_addr >> 1; 441 442 for (size_t i = 0; i < settings->reg_num; i++) { 443 const uint8_t index = settings->reg_settings[i].i2c_reg_index; 444 uint8_t value = settings->reg_settings[i].i2c_reg_val; 445 446 if (!write_i2c_retimer_byte(link, address, index, value)) { 447 DC_LOG_ERROR("Set retimer failed, index: %zu\n", i); 448 return false; 449 } 450 } 451 452 if (is_over_340mhz) { 453 for (size_t i = 0; i < settings->reg_num_6g; i++) { 454 const uint8_t index = settings->reg_settings_6g[i].i2c_reg_index; 455 uint8_t value = settings->reg_settings_6g[i].i2c_reg_val; 456 457 if (!write_i2c_retimer_byte(link, address, index, value)) { 458 DC_LOG_ERROR("Set retimer failed, 6g index: %zu\n", i); 459 return false; 460 } 461 } 462 } 463 464 if (is_vga_mode) { 465 return write_i2c_retimer_vga(link, address); 466 } 467 return true; 468 } 469 470 static bool write_i2c_default_retimer_setting( 471 const struct dc_link *link, 472 bool is_vga_mode, 473 bool is_over_340mhz) 474 { 475 const uint8_t address = 0xBA >> 1; 476 477 DC_LOGGER_INIT(link->ctx->logger); 478 479 const uint8_t data[][2] = { 480 { 0x0A, 0x13 }, 481 { 0x0A, 0x17 }, 482 { 0x0B, is_over_340mhz ? 0xDA : 0xD8 }, 483 { 0x0A, 0x17 }, 484 { 0x0C, is_over_340mhz ? 0x1D : 0x91 }, 485 { 0x0A, 0x17 }, 486 }; 487 488 for (size_t i = 0; i < ARRAY_SIZE(data); i++) { 489 if (!write_i2c_retimer_offset_value(link, address, data[i][0], data[i][1])) { 490 DC_LOG_ERROR("Set default retimer failed, index: %zu\n", i); 491 return false; 492 } 493 } 494 495 if (is_vga_mode) { 496 return write_i2c_retimer_vga(link, address); 497 } 498 return true; 499 } 500 501 static bool write_i2c_redriver_setting( 502 const struct dc_link *link, 503 bool is_over_340mhz) 504 { 505 DC_LOGGER_INIT(link->ctx->logger); 506 const uint8_t address = 0xF0 >> 1; 507 uint8_t buffer[16] = { 508 [3] = 0x4E, 509 [4] = 0x4E, 510 [5] = 0x4E, 511 [6] = is_over_340mhz ? 0x4E : 0x4A, 512 }; 513 514 const bool success = write_i2c(link, address, buffer, sizeof(buffer)); 515 516 RETIMER_REDRIVER_INFO( 517 "Redriver write, address: 0x%x, buffer: { [3]: 0x%x, 0x%x, 0x%x, 0x%x }, success: %d\n", 518 address, buffer[3], buffer[4], buffer[5], buffer[6], success 519 ); 520 521 if (!success) 522 DC_LOG_ERROR("Set redriver failed"); 523 return success; 524 } 525 526 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 527 { 528 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 529 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 530 struct cp_psp_stream_config config = {0}; 531 enum dp_panel_mode panel_mode = 532 dp_get_panel_mode(pipe_ctx->stream->link); 533 534 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 535 return; 536 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 537 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 538 ASSERT(link_enc); 539 if (link_enc == NULL) 540 return; 541 542 /* otg instance */ 543 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 544 545 /* dig front end */ 546 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 547 548 /* stream encoder index */ 549 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 550 if (dp_is_128b_132b_signal(pipe_ctx)) 551 config.stream_enc_idx = 552 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 553 554 /* dig back end */ 555 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 556 557 /* link encoder index */ 558 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 559 if (dp_is_128b_132b_signal(pipe_ctx)) 560 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 561 562 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 563 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 564 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 565 else 566 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 567 568 569 /* phy index */ 570 config.phy_idx = resource_transmitter_to_phy_idx( 571 pipe_ctx->stream->link->dc, link_enc->transmitter); 572 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 573 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 574 config.phy_idx = 0; 575 576 /* stream properties */ 577 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 578 config.mst_enabled = (pipe_ctx->stream->signal == 579 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 580 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 581 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 582 1 : 0; 583 config.dpms_off = dpms_off; 584 585 /* dm stream context */ 586 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 587 588 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 589 } 590 591 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 592 { 593 struct dc *dc = pipe_ctx->stream->ctx->dc; 594 595 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 596 return; 597 598 dc->hwss.set_avmute(pipe_ctx, enable); 599 } 600 601 static void enable_mst_on_sink(struct dc_link *link, bool enable) 602 { 603 unsigned char mstmCntl = 0; 604 605 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 606 if (enable) 607 mstmCntl |= DP_MST_EN; 608 else 609 mstmCntl &= (~DP_MST_EN); 610 611 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 612 } 613 614 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 615 struct dsc_optc_config *config) 616 { 617 uint32_t precision = 1 << 28; 618 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 619 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 620 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 621 DC_LOGGER_INIT(dsc->ctx->logger); 622 623 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 624 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 625 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 626 */ 627 ll_bytes_per_pix_fraq *= 10000000; 628 ll_bytes_per_pix_fraq /= precision; 629 630 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 631 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 632 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 633 DC_LOG_DSC("\tslice_width %d", config->slice_width); 634 } 635 636 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 637 { 638 struct dc *dc = pipe_ctx->stream->ctx->dc; 639 struct dc_stream_state *stream = pipe_ctx->stream; 640 bool result = false; 641 642 if (dc_is_virtual_signal(stream->signal)) 643 result = true; 644 else 645 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 646 return result; 647 } 648 649 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 650 { 651 struct dc *dc = pipe_ctx->stream->ctx->dc; 652 struct dc_stream_state *stream = pipe_ctx->stream; 653 bool result = false; 654 655 if (dc_is_virtual_signal(stream->signal)) 656 result = true; 657 else 658 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 659 return result; 660 } 661 662 663 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 664 * i.e. after dp_enable_dsc_on_rx() had been called 665 */ 666 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 667 { 668 /* TODO: Move this to HWSS as this is hardware programming sequence not a 669 * link layer sequence 670 */ 671 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 672 struct dc *dc = pipe_ctx->stream->ctx->dc; 673 struct dc_stream_state *stream = pipe_ctx->stream; 674 struct pipe_ctx *odm_pipe; 675 int opp_cnt = 1; 676 struct dccg *dccg = dc->res_pool->dccg; 677 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 678 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 679 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 680 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 681 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 682 * this problem. We are implementing a workaround here to keep using dscclk 683 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 684 * 48Mhz) pixel clock to avoid hitting this problem. 685 */ 686 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 687 stream->timing.pix_clk_100hz > 480000; 688 DC_LOGGER_INIT(dsc->ctx->logger); 689 690 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 691 opp_cnt++; 692 693 if (enable) { 694 struct dsc_config dsc_cfg; 695 struct dsc_optc_config dsc_optc_cfg = {0}; 696 enum optc_dsc_mode optc_dsc_mode; 697 698 /* Enable DSC hw block */ 699 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + 700 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 701 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 702 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 703 dsc_cfg.color_depth = stream->timing.display_color_depth; 704 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 705 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 706 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 707 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 708 dsc_cfg.dsc_padding = 0; 709 710 if (should_use_dto_dscclk) 711 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 712 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 713 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 714 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 715 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 716 717 if (should_use_dto_dscclk) 718 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 719 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 720 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 721 } 722 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 723 dsc_cfg.pic_width *= opp_cnt; 724 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 725 726 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 727 728 /* Enable DSC in encoder */ 729 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 730 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 731 dsc_optc_config_log(dsc, &dsc_optc_cfg); 732 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 733 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 734 optc_dsc_mode, 735 dsc_optc_cfg.bytes_per_pixel, 736 dsc_optc_cfg.slice_width); 737 738 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 739 } 740 741 /* Enable DSC in OPTC */ 742 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 743 dsc_optc_config_log(dsc, &dsc_optc_cfg); 744 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 745 optc_dsc_mode, 746 dsc_optc_cfg.bytes_per_pixel, 747 dsc_optc_cfg.slice_width); 748 } else { 749 /* disable DSC in OPTC */ 750 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 751 pipe_ctx->stream_res.tg, 752 OPTC_DSC_DISABLED, 0, 0); 753 754 /* disable DSC in stream encoder */ 755 if (dc_is_dp_signal(stream->signal)) { 756 if (dp_is_128b_132b_signal(pipe_ctx)) 757 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 758 pipe_ctx->stream_res.hpo_dp_stream_enc, 759 false, 760 NULL, 761 true); 762 else { 763 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 764 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 765 pipe_ctx->stream_res.stream_enc, 766 OPTC_DSC_DISABLED, 0, 0); 767 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 768 pipe_ctx->stream_res.stream_enc, false, NULL, true); 769 } 770 } 771 772 /* disable DSC block */ 773 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 774 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 775 /* 776 * TODO - dsc_disconnect is a double buffered register. 777 * by the time we call dsc_disable, dsc may still remain 778 * connected to OPP. In this case OPTC will no longer 779 * get correct pixel data because DSCC is off. However 780 * we also can't wait for the disconnect pending 781 * complete, because this function can be called 782 * with/without OTG master lock acquired. When the lock 783 * is acquired we will never get pending complete until 784 * we release the lock later. So there is no easy way to 785 * solve this problem especially when the lock is 786 * acquired. DSC is a front end hw block it should be 787 * programmed as part of front end sequence, where the 788 * commit sequence without lock and update sequence 789 * with lock are completely separated. However because 790 * we are programming dsc as part of back end link 791 * programming sequence, we don't know if front end OPTC 792 * master lock is acquired. The back end should be 793 * agnostic to front end lock. DSC programming shouldn't 794 * belong to this sequence. 795 */ 796 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 797 if (dccg->funcs->set_ref_dscclk) 798 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 799 } 800 } 801 } 802 803 /* 804 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 805 * hence PPS info packet update need to use frame update instead of immediate update. 806 * Added parameter immediate_update for this purpose. 807 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 808 * which is the only place where a "false" would be passed in for param immediate_update. 809 * 810 * immediate_update is only applicable when DSC is enabled. 811 */ 812 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 813 { 814 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 815 struct dc_stream_state *stream = pipe_ctx->stream; 816 817 if (!pipe_ctx->stream->timing.flags.DSC) 818 return false; 819 820 if (!dsc) 821 return false; 822 823 DC_LOGGER_INIT(dsc->ctx->logger); 824 825 if (enable) { 826 struct dsc_config dsc_cfg; 827 uint8_t dsc_packed_pps[128]; 828 829 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 830 memset(dsc_packed_pps, 0, 128); 831 832 /* Enable DSC hw block */ 833 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 834 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 835 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 836 dsc_cfg.color_depth = stream->timing.display_color_depth; 837 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 838 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 839 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 840 841 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 842 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 843 if (dc_is_dp_signal(stream->signal)) { 844 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 845 if (dp_is_128b_132b_signal(pipe_ctx)) 846 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 847 pipe_ctx->stream_res.hpo_dp_stream_enc, 848 true, 849 &dsc_packed_pps[0], 850 immediate_update); 851 else 852 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 853 pipe_ctx->stream_res.stream_enc, 854 true, 855 &dsc_packed_pps[0], 856 immediate_update); 857 } 858 } else { 859 /* disable DSC PPS in stream encoder */ 860 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 861 if (dc_is_dp_signal(stream->signal)) { 862 if (dp_is_128b_132b_signal(pipe_ctx)) 863 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 864 pipe_ctx->stream_res.hpo_dp_stream_enc, 865 false, 866 NULL, 867 true); 868 else 869 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 870 pipe_ctx->stream_res.stream_enc, false, NULL, true); 871 } 872 } 873 874 return true; 875 } 876 877 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 878 { 879 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 880 bool result = false; 881 882 if (!pipe_ctx->stream->timing.flags.DSC) 883 goto out; 884 if (!dsc) 885 goto out; 886 887 if (enable) { 888 { 889 link_set_dsc_on_stream(pipe_ctx, true); 890 result = true; 891 } 892 } else { 893 dp_set_dsc_on_rx(pipe_ctx, false); 894 link_set_dsc_on_stream(pipe_ctx, false); 895 result = true; 896 } 897 out: 898 return result; 899 } 900 901 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 902 { 903 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 904 905 if (!pipe_ctx->stream->timing.flags.DSC) 906 return false; 907 if (!dsc) 908 return false; 909 910 link_set_dsc_on_stream(pipe_ctx, true); 911 link_set_dsc_pps_packet(pipe_ctx, true, false); 912 return true; 913 } 914 915 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 916 { 917 struct dc_stream_state *stream = pipe_ctx->stream; 918 919 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 920 struct dc_link *link = stream->link; 921 union down_spread_ctrl old_downspread; 922 union down_spread_ctrl new_downspread; 923 924 memset(&old_downspread, 0, sizeof(old_downspread)); 925 926 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 927 &old_downspread.raw, sizeof(old_downspread)); 928 929 new_downspread.raw = old_downspread.raw; 930 931 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 932 (stream->ignore_msa_timing_param) ? 1 : 0; 933 934 if (new_downspread.raw != old_downspread.raw) { 935 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 936 &new_downspread.raw, sizeof(new_downspread)); 937 } 938 939 } else { 940 dm_helpers_mst_enable_stream_features(stream); 941 } 942 } 943 944 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 945 { 946 const uint32_t VCP_Y_PRECISION = 1000; 947 uint64_t vcp_x, vcp_y; 948 DC_LOGGER_INIT(link->ctx->logger); 949 950 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 951 avg_time_slots_per_mtp = dc_fixpt_add( 952 avg_time_slots_per_mtp, 953 dc_fixpt_from_fraction( 954 1, 955 2*VCP_Y_PRECISION)); 956 957 vcp_x = dc_fixpt_floor( 958 avg_time_slots_per_mtp); 959 vcp_y = dc_fixpt_floor( 960 dc_fixpt_mul_int( 961 dc_fixpt_sub_int( 962 avg_time_slots_per_mtp, 963 dc_fixpt_floor( 964 avg_time_slots_per_mtp)), 965 VCP_Y_PRECISION)); 966 967 968 if (link->type == dc_connection_mst_branch) 969 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 970 "X: %llu " 971 "Y: %llu/%d", 972 vcp_x, 973 vcp_y, 974 VCP_Y_PRECISION); 975 else 976 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 977 "X: %llu " 978 "Y: %llu/%d", 979 vcp_x, 980 vcp_y, 981 VCP_Y_PRECISION); 982 } 983 984 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 985 { 986 struct fixed31_32 mbytes_per_sec; 987 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 988 &stream->link->cur_link_settings); 989 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 990 991 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 992 993 return dc_fixpt_div_int(mbytes_per_sec, 54); 994 } 995 996 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 997 { 998 struct fixed31_32 peak_kbps; 999 uint32_t numerator = 0; 1000 uint32_t denominator = 1; 1001 1002 /* 1003 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1004 * required when determining PBN/time slot utilization on the link between 1005 * us and the branch, since that overhead is already accounted for in 1006 * the get_pbn_per_slot function. 1007 * 1008 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1009 * common multiplier to render an integer PBN for all link rate/lane 1010 * counts combinations 1011 * calculate 1012 * peak_kbps *= (64/54) 1013 * peak_kbps /= (8 * 1000) convert to bytes 1014 */ 1015 1016 numerator = 64; 1017 denominator = 54 * 8 * 1000; 1018 kbps *= numerator; 1019 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1020 1021 return peak_kbps; 1022 } 1023 1024 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1025 { 1026 uint64_t kbps; 1027 enum dc_link_encoding_format link_encoding; 1028 1029 if (dp_is_128b_132b_signal(pipe_ctx)) 1030 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1031 else 1032 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1033 1034 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1035 return get_pbn_from_bw_in_kbps(kbps); 1036 } 1037 1038 1039 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1040 static void get_lane_status( 1041 struct dc_link *link, 1042 uint32_t lane_count, 1043 union lane_status *status, 1044 union lane_align_status_updated *status_updated) 1045 { 1046 unsigned int lane; 1047 uint8_t dpcd_buf[3] = {0}; 1048 1049 if (status == NULL || status_updated == NULL) { 1050 return; 1051 } 1052 1053 core_link_read_dpcd( 1054 link, 1055 DP_LANE0_1_STATUS, 1056 dpcd_buf, 1057 sizeof(dpcd_buf)); 1058 1059 for (lane = 0; lane < lane_count; lane++) { 1060 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1061 } 1062 1063 status_updated->raw = dpcd_buf[2]; 1064 } 1065 1066 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1067 { 1068 /* 1069 * wait for ACT handled 1070 */ 1071 int i; 1072 const int act_retries = 30; 1073 enum act_return_status result = ACT_FAILED; 1074 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1075 union payload_table_update_status update_status = {0}; 1076 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1077 union lane_align_status_updated lane_status_updated; 1078 DC_LOGGER_INIT(link->ctx->logger); 1079 1080 if (!display_connected || link->aux_access_disabled) 1081 return true; 1082 for (i = 0; i < act_retries; i++) { 1083 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1084 1085 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1086 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1087 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1088 !dp_is_interlane_aligned(lane_status_updated)) { 1089 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1090 "polling for ACT handled."); 1091 result = ACT_LINK_LOST; 1092 break; 1093 } 1094 core_link_read_dpcd( 1095 link, 1096 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1097 &update_status.raw, 1098 1); 1099 1100 if (update_status.bits.ACT_HANDLED == 1) { 1101 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1102 result = ACT_SUCCESS; 1103 break; 1104 } 1105 1106 fsleep(5000); 1107 } 1108 1109 if (result == ACT_FAILED) { 1110 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1111 "continue on. Something is wrong with the branch."); 1112 } 1113 1114 return (result == ACT_SUCCESS); 1115 } 1116 1117 static void update_mst_stream_alloc_table( 1118 struct dc_link *link, 1119 struct stream_encoder *stream_enc, 1120 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1121 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1122 { 1123 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1124 struct link_mst_stream_allocation *dc_alloc; 1125 1126 int i; 1127 int j; 1128 1129 /* if DRM proposed_table has more than one new payload */ 1130 ASSERT(proposed_table->stream_count - 1131 link->mst_stream_alloc_table.stream_count < 2); 1132 1133 /* copy proposed_table to link, add stream encoder */ 1134 for (i = 0; i < proposed_table->stream_count; i++) { 1135 1136 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1137 dc_alloc = 1138 &link->mst_stream_alloc_table.stream_allocations[j]; 1139 1140 if (dc_alloc->vcp_id == 1141 proposed_table->stream_allocations[i].vcp_id) { 1142 1143 work_table[i] = *dc_alloc; 1144 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1145 break; /* exit j loop */ 1146 } 1147 } 1148 1149 /* new vcp_id */ 1150 if (j == link->mst_stream_alloc_table.stream_count) { 1151 work_table[i].vcp_id = 1152 proposed_table->stream_allocations[i].vcp_id; 1153 work_table[i].slot_count = 1154 proposed_table->stream_allocations[i].slot_count; 1155 work_table[i].stream_enc = stream_enc; 1156 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1157 } 1158 } 1159 1160 /* update link->mst_stream_alloc_table with work_table */ 1161 link->mst_stream_alloc_table.stream_count = 1162 proposed_table->stream_count; 1163 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1164 link->mst_stream_alloc_table.stream_allocations[i] = 1165 work_table[i]; 1166 } 1167 1168 static void remove_stream_from_alloc_table( 1169 struct dc_link *link, 1170 struct stream_encoder *dio_stream_enc, 1171 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1172 { 1173 int i = 0; 1174 struct link_mst_stream_allocation_table *table = 1175 &link->mst_stream_alloc_table; 1176 1177 if (hpo_dp_stream_enc) { 1178 for (; i < table->stream_count; i++) 1179 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1180 break; 1181 } else { 1182 for (; i < table->stream_count; i++) 1183 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1184 break; 1185 } 1186 1187 if (i < table->stream_count) { 1188 i++; 1189 for (; i < table->stream_count; i++) 1190 table->stream_allocations[i-1] = table->stream_allocations[i]; 1191 memset(&table->stream_allocations[table->stream_count-1], 0, 1192 sizeof(struct link_mst_stream_allocation)); 1193 table->stream_count--; 1194 } 1195 } 1196 1197 static void print_mst_streams(struct dc_link *link) 1198 { 1199 int i; 1200 1201 DC_LOGGER_INIT(link->ctx->logger); 1202 1203 DC_LOG_MST("%s stream_count: %d:\n", 1204 __func__, 1205 link->mst_stream_alloc_table.stream_count); 1206 1207 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1208 DC_LOG_MST("stream_enc[%d]: %p\n", i, 1209 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc); 1210 DC_LOG_MST("stream[%d].hpo_dp_stream_enc: %p\n", i, 1211 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc); 1212 DC_LOG_MST("stream[%d].vcp_id: %d\n", i, 1213 link->mst_stream_alloc_table.stream_allocations[i].vcp_id); 1214 DC_LOG_MST("stream[%d].slot_count: %d\n", i, 1215 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1216 } 1217 } 1218 1219 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1220 { 1221 struct dc_stream_state *stream = pipe_ctx->stream; 1222 struct dc_link *link = stream->link; 1223 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1224 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1225 bool mst_mode = (link->type == dc_connection_mst_branch); 1226 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1227 const struct dc_link_settings empty_link_settings = {0}; 1228 DC_LOGGER_INIT(link->ctx->logger); 1229 1230 /* deallocate_mst_payload is called before disable link. When mode or 1231 * disable/enable monitor, new stream is created which is not in link 1232 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1233 * should not done. For new mode set, map_resources will get engine 1234 * for new stream, so stream_enc->id should be validated until here. 1235 */ 1236 1237 /* slot X.Y */ 1238 if (link_hwss->ext.set_throttled_vcp_size) 1239 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1240 if (link_hwss->ext.set_hblank_min_symbol_width) 1241 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1242 &empty_link_settings, 1243 avg_time_slots_per_mtp); 1244 1245 if (mst_mode) { 1246 /* when link is in mst mode, reply on mst manager to remove 1247 * payload 1248 */ 1249 if (dm_helpers_dp_mst_write_payload_allocation_table( 1250 stream->ctx, 1251 stream, 1252 &proposed_table, 1253 false)) 1254 update_mst_stream_alloc_table( 1255 link, 1256 pipe_ctx->stream_res.stream_enc, 1257 pipe_ctx->stream_res.hpo_dp_stream_enc, 1258 &proposed_table); 1259 else 1260 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1261 pipe_ctx->pipe_idx); 1262 } else { 1263 /* when link is no longer in mst mode (mst hub unplugged), 1264 * remove payload with default dc logic 1265 */ 1266 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1267 pipe_ctx->stream_res.hpo_dp_stream_enc); 1268 } 1269 1270 print_mst_streams(link); 1271 1272 /* update mst stream allocation table hardware state */ 1273 if (link_hwss->ext.update_stream_allocation_table == NULL || 1274 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1275 DC_LOG_DEBUG("Unknown encoding format\n"); 1276 return DC_ERROR_UNEXPECTED; 1277 } 1278 1279 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1280 &link->mst_stream_alloc_table); 1281 1282 if (mst_mode) 1283 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1284 stream->ctx, 1285 stream); 1286 1287 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1288 stream->ctx, 1289 stream); 1290 1291 return DC_OK; 1292 } 1293 1294 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1295 * because stream_encoder is not exposed to dm 1296 */ 1297 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1298 { 1299 struct dc_stream_state *stream = pipe_ctx->stream; 1300 struct dc_link *link = stream->link; 1301 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1302 struct fixed31_32 avg_time_slots_per_mtp; 1303 struct fixed31_32 pbn; 1304 struct fixed31_32 pbn_per_slot; 1305 enum act_return_status ret; 1306 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1307 DC_LOGGER_INIT(link->ctx->logger); 1308 1309 /* enable_link_dp_mst already check link->enabled_stream_count 1310 * and stream is in link->stream[]. This is called during set mode, 1311 * stream_enc is available. 1312 */ 1313 1314 /* get calculate VC payload for stream: stream_alloc */ 1315 if (dm_helpers_dp_mst_write_payload_allocation_table( 1316 stream->ctx, 1317 stream, 1318 &proposed_table, 1319 true)) 1320 update_mst_stream_alloc_table( 1321 link, 1322 pipe_ctx->stream_res.stream_enc, 1323 pipe_ctx->stream_res.hpo_dp_stream_enc, 1324 &proposed_table); 1325 else 1326 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1327 pipe_ctx->pipe_idx); 1328 1329 print_mst_streams(link); 1330 1331 ASSERT(proposed_table.stream_count > 0); 1332 1333 /* program DP source TX for payload */ 1334 if (link_hwss->ext.update_stream_allocation_table == NULL || 1335 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1336 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1337 return DC_ERROR_UNEXPECTED; 1338 } 1339 1340 link_hwss->ext.update_stream_allocation_table(link, 1341 &pipe_ctx->link_res, 1342 &link->mst_stream_alloc_table); 1343 1344 /* send down message */ 1345 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1346 stream->ctx, 1347 stream); 1348 1349 if (ret != ACT_LINK_LOST) 1350 dm_helpers_dp_mst_send_payload_allocation( 1351 stream->ctx, 1352 stream); 1353 1354 /* slot X.Y for only current stream */ 1355 pbn_per_slot = get_pbn_per_slot(stream); 1356 if (pbn_per_slot.value == 0) { 1357 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1358 return DC_UNSUPPORTED_VALUE; 1359 } 1360 pbn = get_pbn_from_timing(pipe_ctx); 1361 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1362 1363 log_vcp_x_y(link, avg_time_slots_per_mtp); 1364 1365 if (link_hwss->ext.set_throttled_vcp_size) 1366 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1367 if (link_hwss->ext.set_hblank_min_symbol_width) 1368 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1369 &link->cur_link_settings, 1370 avg_time_slots_per_mtp); 1371 1372 return DC_OK; 1373 } 1374 1375 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1376 const struct dc_stream_state *stream, 1377 const struct dc_link *link) 1378 { 1379 struct fixed31_32 link_bw_effective = 1380 dc_fixpt_from_int( 1381 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1382 struct fixed31_32 timeslot_bw_effective = 1383 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1384 struct fixed31_32 timing_bw = 1385 dc_fixpt_from_int( 1386 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1387 dc_link_get_highest_encoding_format(link))); 1388 struct fixed31_32 avg_time_slots_per_mtp = 1389 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1390 1391 return avg_time_slots_per_mtp; 1392 } 1393 1394 1395 static bool write_128b_132b_sst_payload_allocation_table( 1396 const struct dc_stream_state *stream, 1397 struct dc_link *link, 1398 struct link_mst_stream_allocation_table *proposed_table, 1399 bool allocate) 1400 { 1401 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1402 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1403 bool result = false; 1404 uint8_t req_slot_count = 0; 1405 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1406 union payload_table_update_status update_status = { 0 }; 1407 const uint32_t max_retries = 30; 1408 uint32_t retries = 0; 1409 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1410 DC_LOGGER_INIT(link->ctx->logger); 1411 1412 if (allocate) { 1413 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1414 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1415 /// Validation should filter out modes that exceed link BW 1416 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1417 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1418 return false; 1419 } else { 1420 /// Leave req_slot_count = 0 if allocate is false. 1421 } 1422 1423 proposed_table->stream_count = 1; /// Always 1 stream for SST 1424 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1425 proposed_table->stream_allocations[0].vcp_id = vc_id; 1426 1427 if (!display_connected || link->aux_access_disabled) 1428 return true; 1429 1430 /// Write DPCD 2C0 = 1 to start updating 1431 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1432 core_link_write_dpcd( 1433 link, 1434 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1435 &update_status.raw, 1436 1); 1437 1438 /// Program the changes in DPCD 1C0 - 1C2 1439 ASSERT(vc_id == 1); 1440 core_link_write_dpcd( 1441 link, 1442 DP_PAYLOAD_ALLOCATE_SET, 1443 &vc_id, 1444 1); 1445 1446 ASSERT(start_time_slot == 0); 1447 core_link_write_dpcd( 1448 link, 1449 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1450 &start_time_slot, 1451 1); 1452 1453 core_link_write_dpcd( 1454 link, 1455 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1456 &req_slot_count, 1457 1); 1458 1459 /// Poll till DPCD 2C0 read 1 1460 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1461 1462 while (retries < max_retries) { 1463 if (core_link_read_dpcd( 1464 link, 1465 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1466 &update_status.raw, 1467 1) == DC_OK) { 1468 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1469 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1470 result = true; 1471 break; 1472 } 1473 } else { 1474 union dpcd_rev dpcdRev = {0}; 1475 1476 if (core_link_read_dpcd( 1477 link, 1478 DP_DPCD_REV, 1479 &dpcdRev.raw, 1480 1) != DC_OK) { 1481 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1482 "of sink while polling payload table " 1483 "updated status bit."); 1484 break; 1485 } 1486 } 1487 retries++; 1488 fsleep(5000); 1489 } 1490 1491 if (!result && retries == max_retries) { 1492 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1493 "continue on. Something is wrong with the branch."); 1494 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1495 } 1496 1497 return result; 1498 } 1499 1500 /* 1501 * Payload allocation/deallocation for SST introduced in DP2.0 1502 */ 1503 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1504 bool allocate) 1505 { 1506 struct dc_stream_state *stream = pipe_ctx->stream; 1507 struct dc_link *link = stream->link; 1508 struct link_mst_stream_allocation_table proposed_table = {0}; 1509 struct fixed31_32 avg_time_slots_per_mtp; 1510 const struct dc_link_settings empty_link_settings = {0}; 1511 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1512 DC_LOGGER_INIT(link->ctx->logger); 1513 1514 /* slot X.Y for SST payload deallocate */ 1515 if (!allocate) { 1516 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1517 1518 log_vcp_x_y(link, avg_time_slots_per_mtp); 1519 1520 if (link_hwss->ext.set_throttled_vcp_size) 1521 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1522 avg_time_slots_per_mtp); 1523 if (link_hwss->ext.set_hblank_min_symbol_width) 1524 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1525 &empty_link_settings, 1526 avg_time_slots_per_mtp); 1527 } 1528 1529 /* calculate VC payload and update branch with new payload allocation table*/ 1530 if (!write_128b_132b_sst_payload_allocation_table( 1531 stream, 1532 link, 1533 &proposed_table, 1534 allocate)) { 1535 DC_LOG_ERROR("SST Update Payload: Failed to update " 1536 "allocation table for " 1537 "pipe idx: %d\n", 1538 pipe_ctx->pipe_idx); 1539 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1540 } 1541 1542 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1543 1544 ASSERT(proposed_table.stream_count == 1); 1545 1546 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1547 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1548 "vcp_id: %d " 1549 "slot_count: %d\n", 1550 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1551 proposed_table.stream_allocations[0].vcp_id, 1552 proposed_table.stream_allocations[0].slot_count); 1553 1554 /* program DP source TX for payload */ 1555 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1556 &proposed_table); 1557 1558 /* poll for ACT handled */ 1559 if (!poll_for_allocation_change_trigger(link)) { 1560 // Failures will result in blackscreen and errors logged 1561 BREAK_TO_DEBUGGER(); 1562 } 1563 1564 /* slot X.Y for SST payload allocate */ 1565 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1566 DP_128b_132b_ENCODING) { 1567 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1568 1569 log_vcp_x_y(link, avg_time_slots_per_mtp); 1570 1571 if (link_hwss->ext.set_throttled_vcp_size) 1572 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1573 avg_time_slots_per_mtp); 1574 if (link_hwss->ext.set_hblank_min_symbol_width) 1575 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1576 &link->cur_link_settings, 1577 avg_time_slots_per_mtp); 1578 } 1579 1580 /* Always return DC_OK. 1581 * If part of sequence fails, log failure(s) and show blackscreen 1582 */ 1583 return DC_OK; 1584 } 1585 1586 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1587 { 1588 struct dc_stream_state *stream = pipe_ctx->stream; 1589 struct dc_link *link = stream->link; 1590 struct fixed31_32 avg_time_slots_per_mtp; 1591 struct fixed31_32 pbn; 1592 struct fixed31_32 pbn_per_slot; 1593 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1594 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1595 DC_LOGGER_INIT(link->ctx->logger); 1596 1597 /* decrease throttled vcp size */ 1598 pbn_per_slot = get_pbn_per_slot(stream); 1599 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1600 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1601 1602 if (link_hwss->ext.set_throttled_vcp_size) 1603 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1604 if (link_hwss->ext.set_hblank_min_symbol_width) 1605 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1606 &link->cur_link_settings, 1607 avg_time_slots_per_mtp); 1608 1609 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1610 dm_helpers_dp_mst_send_payload_allocation( 1611 stream->ctx, 1612 stream); 1613 1614 /* notify immediate branch device table update */ 1615 if (dm_helpers_dp_mst_write_payload_allocation_table( 1616 stream->ctx, 1617 stream, 1618 &proposed_table, 1619 true)) { 1620 /* update mst stream allocation table software state */ 1621 update_mst_stream_alloc_table( 1622 link, 1623 pipe_ctx->stream_res.stream_enc, 1624 pipe_ctx->stream_res.hpo_dp_stream_enc, 1625 &proposed_table); 1626 } else { 1627 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1628 pipe_ctx->pipe_idx); 1629 } 1630 1631 print_mst_streams(link); 1632 1633 ASSERT(proposed_table.stream_count > 0); 1634 1635 /* update mst stream allocation table hardware state */ 1636 if (link_hwss->ext.update_stream_allocation_table == NULL || 1637 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1638 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1639 return DC_ERROR_UNEXPECTED; 1640 } 1641 1642 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1643 &link->mst_stream_alloc_table); 1644 1645 /* poll for immediate branch device ACT handled */ 1646 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1647 stream->ctx, 1648 stream); 1649 1650 return DC_OK; 1651 } 1652 1653 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1654 { 1655 struct dc_stream_state *stream = pipe_ctx->stream; 1656 struct dc_link *link = stream->link; 1657 struct fixed31_32 avg_time_slots_per_mtp; 1658 struct fixed31_32 pbn; 1659 struct fixed31_32 pbn_per_slot; 1660 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1661 enum act_return_status ret; 1662 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1663 DC_LOGGER_INIT(link->ctx->logger); 1664 1665 /* notify immediate branch device table update */ 1666 if (dm_helpers_dp_mst_write_payload_allocation_table( 1667 stream->ctx, 1668 stream, 1669 &proposed_table, 1670 true)) { 1671 /* update mst stream allocation table software state */ 1672 update_mst_stream_alloc_table( 1673 link, 1674 pipe_ctx->stream_res.stream_enc, 1675 pipe_ctx->stream_res.hpo_dp_stream_enc, 1676 &proposed_table); 1677 } 1678 1679 print_mst_streams(link); 1680 1681 ASSERT(proposed_table.stream_count > 0); 1682 1683 /* update mst stream allocation table hardware state */ 1684 if (link_hwss->ext.update_stream_allocation_table == NULL || 1685 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1686 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1687 return DC_ERROR_UNEXPECTED; 1688 } 1689 1690 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1691 &link->mst_stream_alloc_table); 1692 1693 /* poll for immediate branch device ACT handled */ 1694 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1695 stream->ctx, 1696 stream); 1697 1698 if (ret != ACT_LINK_LOST) { 1699 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1700 dm_helpers_dp_mst_send_payload_allocation( 1701 stream->ctx, 1702 stream); 1703 } 1704 1705 /* increase throttled vcp size */ 1706 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1707 pbn_per_slot = get_pbn_per_slot(stream); 1708 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1709 1710 if (link_hwss->ext.set_throttled_vcp_size) 1711 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1712 if (link_hwss->ext.set_hblank_min_symbol_width) 1713 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1714 &link->cur_link_settings, 1715 avg_time_slots_per_mtp); 1716 1717 return DC_OK; 1718 } 1719 1720 static void disable_link_dp(struct dc_link *link, 1721 const struct link_resource *link_res, 1722 enum signal_type signal) 1723 { 1724 struct dc_link_settings link_settings = link->cur_link_settings; 1725 1726 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1727 link->mst_stream_alloc_table.stream_count > 0) 1728 /* disable MST link only when last vc payload is deallocated */ 1729 return; 1730 1731 dp_disable_link_phy(link, link_res, signal); 1732 1733 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1734 if (!link->skip_implict_edp_power_control) 1735 link->dc->hwss.edp_power_control(link, false); 1736 } 1737 1738 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->sink_count == 0) 1739 /* set the sink to SST mode after disabling the link */ 1740 enable_mst_on_sink(link, false); 1741 1742 if (link_dp_get_encoding_format(&link_settings) == 1743 DP_8b_10b_ENCODING) { 1744 dp_set_fec_enable(link, link_res, false); 1745 dp_set_fec_ready(link, link_res, false); 1746 } 1747 } 1748 1749 static void disable_link(struct dc_link *link, 1750 const struct link_resource *link_res, 1751 enum signal_type signal) 1752 { 1753 if (dc_is_dp_signal(signal)) { 1754 disable_link_dp(link, link_res, signal); 1755 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1756 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1757 } else { 1758 link->dc->hwss.disable_link_output(link, link_res, signal); 1759 } 1760 1761 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1762 /* MST disable link only when no stream use the link */ 1763 if (link->mst_stream_alloc_table.stream_count <= 0) 1764 link->link_status.link_active = false; 1765 } else { 1766 link->link_status.link_active = false; 1767 } 1768 } 1769 1770 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1771 { 1772 struct dc_stream_state *stream = pipe_ctx->stream; 1773 struct dc_link *link = stream->link; 1774 enum dc_color_depth display_color_depth; 1775 enum engine_id eng_id; 1776 struct ext_hdmi_settings settings = {0}; 1777 bool is_over_340mhz = false; 1778 bool is_vga_mode = (stream->timing.h_addressable == 640) 1779 && (stream->timing.v_addressable == 480); 1780 struct dc *dc = pipe_ctx->stream->ctx->dc; 1781 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1782 1783 if (stream->phy_pix_clk == 0) 1784 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1785 if (stream->phy_pix_clk > 340000) 1786 is_over_340mhz = true; 1787 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1788 ASSERT(false); 1789 return; 1790 } 1791 1792 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1793 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1794 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1795 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1796 /* DP159, Retimer settings */ 1797 eng_id = pipe_ctx->stream_res.stream_enc->id; 1798 1799 if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) { 1800 write_i2c_retimer_setting(link, is_vga_mode, is_over_340mhz, &settings); 1801 } else { 1802 write_i2c_default_retimer_setting(link, is_vga_mode, is_over_340mhz); 1803 } 1804 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1805 /* PI3EQX1204, Redriver settings */ 1806 write_i2c_redriver_setting(link, is_over_340mhz); 1807 } 1808 } 1809 1810 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1811 write_scdc_data( 1812 stream->link->ddc, 1813 stream->phy_pix_clk, 1814 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 1815 1816 memset(&stream->link->cur_link_settings, 0, 1817 sizeof(struct dc_link_settings)); 1818 1819 display_color_depth = stream->timing.display_color_depth; 1820 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1821 display_color_depth = COLOR_DEPTH_888; 1822 1823 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 1824 * character clock in case that beyond 340MHz. 1825 */ 1826 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 1827 link_hwss->setup_stream_encoder(pipe_ctx); 1828 1829 dc->hwss.enable_tmds_link_output( 1830 link, 1831 &pipe_ctx->link_res, 1832 pipe_ctx->stream->signal, 1833 pipe_ctx->clock_source->id, 1834 display_color_depth, 1835 stream->phy_pix_clk); 1836 1837 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1838 read_scdc_data(link->ddc); 1839 } 1840 1841 static enum dc_status enable_link_dp(struct dc_state *state, 1842 struct pipe_ctx *pipe_ctx) 1843 { 1844 struct dc_stream_state *stream = pipe_ctx->stream; 1845 enum dc_status status; 1846 bool skip_video_pattern; 1847 struct dc_link *link = stream->link; 1848 const struct dc_link_settings *link_settings = 1849 &pipe_ctx->link_config.dp_link_settings; 1850 bool fec_enable; 1851 int i; 1852 bool apply_seamless_boot_optimization = false; 1853 uint32_t bl_oled_enable_delay = 50; // in ms 1854 uint32_t post_oui_delay = 30; // 30ms 1855 /* Reduce link bandwidth between failed link training attempts. */ 1856 bool do_fallback = false; 1857 int lt_attempts = LINK_TRAINING_ATTEMPTS; 1858 1859 // Increase retry count if attempting DP1.x on FIXED_VS link 1860 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 1861 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 1862 lt_attempts = 10; 1863 1864 // check for seamless boot 1865 for (i = 0; i < state->stream_count; i++) { 1866 if (state->streams[i]->apply_seamless_boot_optimization) { 1867 apply_seamless_boot_optimization = true; 1868 break; 1869 } 1870 } 1871 1872 /* Train with fallback when enabling DPIA link. Conventional links are 1873 * trained with fallback during sink detection. 1874 */ 1875 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 1876 !link->dc->config.enable_dpia_pre_training) 1877 do_fallback = true; 1878 1879 /* 1880 * Temporary w/a to get DP2.0 link rates to work with SST. 1881 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 1882 */ 1883 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 1884 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 1885 link->dc->debug.set_mst_en_for_sst) { 1886 enable_mst_on_sink(link, true); 1887 } else if (link->dpcd_caps.is_mst_capable && 1888 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 1889 /* disable mst on sink */ 1890 enable_mst_on_sink(link, false); 1891 } 1892 1893 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 1894 /*in case it is not on*/ 1895 if (!link->dc->config.edp_no_power_sequencing) 1896 link->dc->hwss.edp_power_control(link, true); 1897 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 1898 } 1899 1900 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 1901 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 1902 } else { 1903 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1904 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 1905 if (state->clk_mgr && !apply_seamless_boot_optimization) 1906 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 1907 state, false); 1908 } 1909 1910 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 1911 dpcd_set_source_specific_data(link); 1912 if (link->dpcd_sink_ext_caps.raw != 0) { 1913 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 1914 msleep(post_oui_delay); 1915 } 1916 1917 // similarly, mode switch can cause loss of cable ID 1918 dpcd_write_cable_id_to_dprx(link); 1919 1920 skip_video_pattern = true; 1921 1922 if (link_settings->link_rate == LINK_RATE_LOW) 1923 skip_video_pattern = false; 1924 1925 if (stream->sink_patches.oled_optimize_display_on) 1926 set_default_brightness_aux(link); 1927 1928 if (perform_link_training_with_retries(link_settings, 1929 skip_video_pattern, 1930 lt_attempts, 1931 pipe_ctx, 1932 pipe_ctx->stream->signal, 1933 do_fallback)) { 1934 status = DC_OK; 1935 } else { 1936 status = DC_FAIL_DP_LINK_TRAINING; 1937 } 1938 1939 if (link->preferred_training_settings.fec_enable) 1940 fec_enable = *link->preferred_training_settings.fec_enable; 1941 else 1942 fec_enable = true; 1943 1944 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 1945 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 1946 1947 // during mode set we do DP_SET_POWER off then on, aux writes are lost 1948 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 1949 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 1950 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 1951 if (!stream->sink_patches.oled_optimize_display_on) { 1952 set_default_brightness_aux(link); 1953 if (link->dpcd_sink_ext_caps.bits.oled == 1) 1954 msleep(bl_oled_enable_delay); 1955 edp_backlight_enable_aux(link, true); 1956 } else { 1957 edp_backlight_enable_aux(link, true); 1958 } 1959 } 1960 1961 return status; 1962 } 1963 1964 static enum dc_status enable_link_edp( 1965 struct dc_state *state, 1966 struct pipe_ctx *pipe_ctx) 1967 { 1968 return enable_link_dp(state, pipe_ctx); 1969 } 1970 1971 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 1972 { 1973 struct dc_stream_state *stream = pipe_ctx->stream; 1974 struct dc_link *link = stream->link; 1975 struct dc *dc = stream->ctx->dc; 1976 1977 if (stream->phy_pix_clk == 0) 1978 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1979 1980 memset(&stream->link->cur_link_settings, 0, 1981 sizeof(struct dc_link_settings)); 1982 dc->hwss.enable_lvds_link_output( 1983 link, 1984 &pipe_ctx->link_res, 1985 pipe_ctx->clock_source->id, 1986 stream->phy_pix_clk); 1987 1988 } 1989 1990 static enum dc_status enable_link_dp_mst( 1991 struct dc_state *state, 1992 struct pipe_ctx *pipe_ctx) 1993 { 1994 struct dc_link *link = pipe_ctx->stream->link; 1995 unsigned char mstm_cntl = 0; 1996 1997 /* sink signal type after MST branch is MST. Multiple MST sinks 1998 * share one link. Link DP PHY is enable or training only once. 1999 */ 2000 if (link->link_status.link_active) 2001 return DC_OK; 2002 2003 /* clear payload table */ 2004 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2005 if (mstm_cntl & DP_MST_EN) 2006 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2007 2008 /* to make sure the pending down rep can be processed 2009 * before enabling the link 2010 */ 2011 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2012 2013 /* set the sink to MST mode before enabling the link */ 2014 enable_mst_on_sink(link, true); 2015 2016 return enable_link_dp(state, pipe_ctx); 2017 } 2018 2019 static enum dc_status enable_link_analog( 2020 struct dc_state *state, 2021 struct pipe_ctx *pipe_ctx) 2022 { 2023 struct dc_link *link = pipe_ctx->stream->link; 2024 2025 link->dc->hwss.enable_analog_link_output( 2026 link, pipe_ctx->stream->timing.pix_clk_100hz); 2027 2028 return DC_OK; 2029 } 2030 2031 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2032 { 2033 struct dc_link *link = pipe_ctx->stream->link; 2034 2035 link->dc->hwss.enable_dp_link_output(link, 2036 &pipe_ctx->link_res, 2037 SIGNAL_TYPE_DISPLAY_PORT, 2038 pipe_ctx->clock_source->id, 2039 &pipe_ctx->link_config.dp_link_settings); 2040 return DC_OK; 2041 } 2042 2043 static enum dc_status enable_link( 2044 struct dc_state *state, 2045 struct pipe_ctx *pipe_ctx) 2046 { 2047 enum dc_status status = DC_ERROR_UNEXPECTED; 2048 struct dc_stream_state *stream = pipe_ctx->stream; 2049 struct dc_link *link = NULL; 2050 2051 if (stream == NULL) 2052 return DC_ERROR_UNEXPECTED; 2053 link = stream->link; 2054 2055 /* There's some scenarios where driver is unloaded with display 2056 * still enabled. When driver is reloaded, it may cause a display 2057 * to not light up if there is a mismatch between old and new 2058 * link settings. Need to call disable first before enabling at 2059 * new link settings. 2060 */ 2061 if (link->link_status.link_active) 2062 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2063 2064 switch (pipe_ctx->stream->signal) { 2065 case SIGNAL_TYPE_DISPLAY_PORT: 2066 status = enable_link_dp(state, pipe_ctx); 2067 break; 2068 case SIGNAL_TYPE_EDP: 2069 status = enable_link_edp(state, pipe_ctx); 2070 break; 2071 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2072 status = enable_link_dp_mst(state, pipe_ctx); 2073 msleep(200); 2074 break; 2075 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2076 case SIGNAL_TYPE_DVI_DUAL_LINK: 2077 case SIGNAL_TYPE_HDMI_TYPE_A: 2078 enable_link_hdmi(pipe_ctx); 2079 status = DC_OK; 2080 break; 2081 case SIGNAL_TYPE_LVDS: 2082 enable_link_lvds(pipe_ctx); 2083 status = DC_OK; 2084 break; 2085 case SIGNAL_TYPE_RGB: 2086 status = enable_link_analog(state, pipe_ctx); 2087 break; 2088 case SIGNAL_TYPE_VIRTUAL: 2089 status = enable_link_virtual(pipe_ctx); 2090 break; 2091 default: 2092 break; 2093 } 2094 2095 if (status == DC_OK) { 2096 pipe_ctx->stream->link->link_status.link_active = true; 2097 } 2098 2099 return status; 2100 } 2101 2102 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2103 { 2104 struct dc_link *link = stream->sink->link; 2105 int req_bw = bw; 2106 2107 DC_LOGGER_INIT(link->ctx->logger); 2108 2109 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2110 return false; 2111 2112 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2113 int sink_index = 0; 2114 int i = 0; 2115 2116 for (i = 0; i < link->sink_count; i++) { 2117 if (link->remote_sinks[i] == NULL) 2118 continue; 2119 2120 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2121 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2122 else 2123 sink_index = i; 2124 } 2125 2126 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2127 } 2128 2129 link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); 2130 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2131 2132 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2133 2134 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2135 int i = 0; 2136 2137 for (i = 0; i < link->sink_count; i++) { 2138 if (link->remote_sinks[i] == NULL) 2139 continue; 2140 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2141 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2142 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2143 } 2144 } 2145 2146 return true; 2147 } 2148 2149 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2150 { 2151 bool ret; 2152 2153 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2154 dc_link_get_highest_encoding_format(stream->sink->link)); 2155 2156 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2157 2158 return ret; 2159 } 2160 2161 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2162 { 2163 bool ret; 2164 2165 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2166 2167 return ret; 2168 } 2169 2170 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2171 { 2172 struct dc *dc = pipe_ctx->stream->ctx->dc; 2173 struct dc_stream_state *stream = pipe_ctx->stream; 2174 struct dc_link *link = stream->sink->link; 2175 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2176 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2177 2178 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2179 2180 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2181 2182 if (dp_is_128b_132b_signal(pipe_ctx)) 2183 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2184 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2185 return; 2186 2187 if (pipe_ctx->stream->sink) { 2188 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2189 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2190 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2191 pipe_ctx->stream->sink->edid_caps.display_name, 2192 pipe_ctx->stream->signal, link->link_index, link->sink_count); 2193 } 2194 } 2195 2196 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2197 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2198 set_avmute(pipe_ctx, true); 2199 } 2200 2201 dc->hwss.disable_audio_stream(pipe_ctx); 2202 2203 update_psp_stream_config(pipe_ctx, true); 2204 dc->hwss.blank_stream(pipe_ctx); 2205 2206 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2207 deallocate_usb4_bandwidth(pipe_ctx->stream); 2208 2209 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2210 deallocate_mst_payload(pipe_ctx); 2211 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2212 dp_is_128b_132b_signal(pipe_ctx)) 2213 update_sst_payload(pipe_ctx, false); 2214 2215 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2216 struct ext_hdmi_settings settings = {0}; 2217 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2218 2219 unsigned short masked_chip_caps = link->chip_caps & 2220 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2221 //Need to inform that sink is going to use legacy HDMI mode. 2222 write_scdc_data( 2223 link->ddc, 2224 165000,//vbios only handles 165Mhz. 2225 false); 2226 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2227 /* DP159, Retimer settings */ 2228 if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) 2229 write_i2c_retimer_setting(link, false, false, &settings); 2230 else 2231 write_i2c_default_retimer_setting(link, false, false); 2232 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2233 /* PI3EQX1204, Redriver settings */ 2234 write_i2c_redriver_setting(link, false); 2235 } 2236 } 2237 2238 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2239 !dp_is_128b_132b_signal(pipe_ctx)) { 2240 2241 /* In DP1.x SST mode, our encoder will go to TPS1 2242 * when link is on but stream is off. 2243 * Disabling link before stream will avoid exposing TPS1 pattern 2244 * during the disable sequence as it will confuse some receivers 2245 * state machine. 2246 * In DP2 or MST mode, our encoder will stay video active 2247 */ 2248 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2249 dc->hwss.disable_stream(pipe_ctx); 2250 } else { 2251 dc->hwss.disable_stream(pipe_ctx); 2252 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2253 } 2254 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2255 2256 if (pipe_ctx->stream->timing.flags.DSC) { 2257 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2258 link_set_dsc_enable(pipe_ctx, false); 2259 } 2260 if (dp_is_128b_132b_signal(pipe_ctx)) { 2261 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2262 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2263 } 2264 2265 if (vpg && vpg->funcs->vpg_powerdown) 2266 vpg->funcs->vpg_powerdown(vpg); 2267 2268 /* for psp not exist case */ 2269 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2270 /* reset internal save state to default since eDP is off */ 2271 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2272 /* since current psp not loaded, we need to reset it to default */ 2273 link->panel_mode = panel_mode; 2274 } 2275 } 2276 2277 void link_set_dpms_on( 2278 struct dc_state *state, 2279 struct pipe_ctx *pipe_ctx) 2280 { 2281 struct dc *dc = pipe_ctx->stream->ctx->dc; 2282 struct dc_stream_state *stream = pipe_ctx->stream; 2283 struct dc_link *link = stream->sink->link; 2284 enum dc_status status; 2285 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 2286 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2287 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2288 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2289 bool apply_edp_fast_boot_optimization = 2290 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2291 2292 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2293 2294 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2295 2296 if (dp_is_128b_132b_signal(pipe_ctx)) 2297 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2298 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2299 return; 2300 2301 if (pipe_ctx->stream->sink) { 2302 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2303 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2304 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2305 pipe_ctx->stream->sink->edid_caps.display_name, 2306 pipe_ctx->stream->signal, 2307 link->link_index, 2308 link->sink_count); 2309 } 2310 } 2311 2312 if (!dc->config.unify_link_enc_assignment) 2313 link_enc = link_enc_cfg_get_link_enc(link); 2314 ASSERT(link_enc); 2315 2316 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2317 && !dp_is_128b_132b_signal(pipe_ctx)) { 2318 if (link_enc) 2319 link_enc->funcs->setup( 2320 link_enc, 2321 pipe_ctx->stream->signal); 2322 } 2323 2324 pipe_ctx->stream->link->link_state_valid = true; 2325 2326 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2327 if (dp_is_128b_132b_signal(pipe_ctx)) 2328 otg_out_dest = OUT_MUX_HPO_DP; 2329 else 2330 otg_out_dest = OUT_MUX_DIO; 2331 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2332 } 2333 2334 link_hwss->setup_stream_attribute(pipe_ctx); 2335 2336 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2337 2338 // Enable VPG before building infoframe 2339 if (vpg && vpg->funcs->vpg_poweron) 2340 vpg->funcs->vpg_poweron(vpg); 2341 2342 resource_build_info_frame(pipe_ctx); 2343 dc->hwss.update_info_frame(pipe_ctx); 2344 2345 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2346 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2347 2348 /* Do not touch link on seamless boot optimization. */ 2349 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2350 pipe_ctx->stream->dpms_off = false; 2351 2352 /* Still enable stream features & audio on seamless boot for DP external displays */ 2353 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2354 enable_stream_features(pipe_ctx); 2355 dc->hwss.enable_audio_stream(pipe_ctx); 2356 } 2357 2358 update_psp_stream_config(pipe_ctx, false); 2359 return; 2360 } 2361 2362 /* eDP lit up by bios already, no need to enable again. */ 2363 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2364 apply_edp_fast_boot_optimization && 2365 !pipe_ctx->stream->timing.flags.DSC && 2366 !pipe_ctx->next_odm_pipe) { 2367 pipe_ctx->stream->dpms_off = false; 2368 update_psp_stream_config(pipe_ctx, false); 2369 2370 if (link->is_dds) { 2371 uint32_t post_oui_delay = 30; // 30ms 2372 2373 dpcd_set_source_specific_data(link); 2374 msleep(post_oui_delay); 2375 } 2376 2377 return; 2378 } 2379 2380 if (pipe_ctx->stream->dpms_off) 2381 return; 2382 2383 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2384 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2385 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2386 */ 2387 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2388 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2389 return; 2390 } 2391 2392 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2393 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2394 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2395 * will be automatically set at a later time when the video is enabled 2396 * (DP_VID_STREAM_EN = 1). 2397 */ 2398 if (pipe_ctx->stream->timing.flags.DSC) { 2399 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2400 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2401 link_set_dsc_enable(pipe_ctx, true); 2402 } 2403 2404 if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal)) 2405 dp_setup_replay(link, stream); 2406 2407 status = enable_link(state, pipe_ctx); 2408 2409 if (status != DC_OK) { 2410 DC_LOG_WARNING("enabling link %u failed: %d\n", 2411 pipe_ctx->stream->link->link_index, 2412 status); 2413 2414 /* Abort stream enable *unless* the failure was due to 2415 * DP link training - some DP monitors will recover and 2416 * show the stream anyway. But MST displays can't proceed 2417 * without link training. 2418 */ 2419 if (status != DC_FAIL_DP_LINK_TRAINING || 2420 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2421 if (false == stream->link->link_status.link_active) 2422 disable_link(stream->link, &pipe_ctx->link_res, 2423 pipe_ctx->stream->signal); 2424 BREAK_TO_DEBUGGER(); 2425 return; 2426 } 2427 } 2428 2429 /* turn off otg test pattern if enable */ 2430 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2431 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2432 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2433 COLOR_DEPTH_UNDEFINED); 2434 2435 /* This second call is needed to reconfigure the DIG 2436 * as a workaround for the incorrect value being applied 2437 * from transmitter control. 2438 */ 2439 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2440 dp_is_128b_132b_signal(pipe_ctx))) { 2441 2442 if (link_enc) 2443 link_enc->funcs->setup( 2444 link_enc, 2445 pipe_ctx->stream->signal); 2446 2447 } 2448 2449 dc->hwss.enable_stream(pipe_ctx); 2450 2451 /* Set DPS PPS SDP (AKA "info frames") */ 2452 if (pipe_ctx->stream->timing.flags.DSC) { 2453 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2454 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2455 dp_set_dsc_on_rx(pipe_ctx, true); 2456 link_set_dsc_pps_packet(pipe_ctx, true, true); 2457 } 2458 } 2459 2460 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2461 dp_set_hblank_reduction_on_rx(pipe_ctx); 2462 2463 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2464 allocate_usb4_bandwidth(pipe_ctx->stream); 2465 2466 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2467 allocate_mst_payload(pipe_ctx); 2468 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2469 dp_is_128b_132b_signal(pipe_ctx)) 2470 update_sst_payload(pipe_ctx, true); 2471 2472 /* Corruption was observed on systems with display mux when stream gets 2473 * enabled after the mux switch. Having a small delay between link 2474 * training and stream unblank resolves the corruption issue. 2475 * This is workaround. 2476 */ 2477 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2478 link->is_display_mux_present) 2479 msleep(20); 2480 2481 dc->hwss.unblank_stream(pipe_ctx, 2482 &pipe_ctx->stream->link->cur_link_settings); 2483 2484 if (stream->sink_patches.delay_ignore_msa > 0) 2485 msleep(stream->sink_patches.delay_ignore_msa); 2486 2487 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2488 enable_stream_features(pipe_ctx); 2489 update_psp_stream_config(pipe_ctx, false); 2490 2491 dc->hwss.enable_audio_stream(pipe_ctx); 2492 2493 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2494 set_avmute(pipe_ctx, false); 2495 } 2496 } 2497