1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) && 144 (link->type != dc_connection_none)) 145 dpcd_write_rx_power_ctrl(link, false); 146 } 147 } 148 149 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 150 { 151 struct pipe_ctx *pipes[MAX_PIPES]; 152 struct dc_stream_state *streams[MAX_PIPES]; 153 struct dc_state *state = link->dc->current_state; 154 uint8_t count; 155 int i; 156 struct dc_stream_update stream_update; 157 bool dpms_off = true; 158 struct link_resource link_res = {0}; 159 160 memset(&stream_update, 0, sizeof(stream_update)); 161 stream_update.dpms_off = &dpms_off; 162 163 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 164 165 /* The subsequent call to dc_commit_updates_for_stream for a full update 166 * will release the current state and swap to a new state. Releasing the 167 * current state results in the stream pointers in the pipe_ctx structs 168 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream. 169 */ 170 for (i = 0; i < count; i++) 171 streams[i] = pipes[i]->stream; 172 173 for (i = 0; i < count; i++) { 174 stream_update.stream = streams[i]; 175 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 176 streams[i], &stream_update, 177 state); 178 } 179 180 /* link can be also enabled by vbios. In this case it is not recorded 181 * in pipe_ctx. Disable link phy here to make sure it is completely off 182 */ 183 dp_disable_link_phy(link, &link_res, link->connector_signal); 184 } 185 186 void link_resume(struct dc_link *link) 187 { 188 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 189 program_hpd_filter(link); 190 } 191 192 /* This function returns true if the pipe is used to feed video signal directly 193 * to the link. 194 */ 195 static bool is_master_pipe_for_link(const struct dc_link *link, 196 const struct pipe_ctx *pipe) 197 { 198 return resource_is_pipe_type(pipe, OTG_MASTER) && 199 pipe->stream->link == link; 200 } 201 202 /* 203 * This function finds all master pipes feeding to a given link with dpms set to 204 * on in given dc state. 205 */ 206 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 207 struct dc_state *state, 208 uint8_t *count, 209 struct pipe_ctx *pipes[MAX_PIPES]) 210 { 211 int i; 212 struct pipe_ctx *pipe = NULL; 213 214 *count = 0; 215 for (i = 0; i < MAX_PIPES; i++) { 216 pipe = &state->res_ctx.pipe_ctx[i]; 217 218 if (is_master_pipe_for_link(link, pipe) && 219 pipe->stream->dpms_off == false) { 220 pipes[(*count)++] = pipe; 221 } 222 } 223 } 224 225 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 226 enum engine_id eng_id, 227 struct ext_hdmi_settings *settings) 228 { 229 bool result = false; 230 int i = 0; 231 struct integrated_info *integrated_info = 232 pipe_ctx->stream->ctx->dc_bios->integrated_info; 233 234 if (integrated_info == NULL) 235 return false; 236 237 /* 238 * Get retimer settings from sbios for passing SI eye test for DCE11 239 * The setting values are varied based on board revision and port id 240 * Therefore the setting values of each ports is passed by sbios. 241 */ 242 243 // Check if current bios contains ext Hdmi settings 244 if (integrated_info->gpu_cap_info & 0x20) { 245 switch (eng_id) { 246 case ENGINE_ID_DIGA: 247 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 248 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 249 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 250 memmove(settings->reg_settings, 251 integrated_info->dp0_ext_hdmi_reg_settings, 252 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 253 memmove(settings->reg_settings_6g, 254 integrated_info->dp0_ext_hdmi_6g_reg_settings, 255 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 256 result = true; 257 break; 258 case ENGINE_ID_DIGB: 259 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 260 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 261 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 262 memmove(settings->reg_settings, 263 integrated_info->dp1_ext_hdmi_reg_settings, 264 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 265 memmove(settings->reg_settings_6g, 266 integrated_info->dp1_ext_hdmi_6g_reg_settings, 267 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 268 result = true; 269 break; 270 case ENGINE_ID_DIGC: 271 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 272 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 273 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 274 memmove(settings->reg_settings, 275 integrated_info->dp2_ext_hdmi_reg_settings, 276 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 277 memmove(settings->reg_settings_6g, 278 integrated_info->dp2_ext_hdmi_6g_reg_settings, 279 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 280 result = true; 281 break; 282 case ENGINE_ID_DIGD: 283 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 284 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 285 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 286 memmove(settings->reg_settings, 287 integrated_info->dp3_ext_hdmi_reg_settings, 288 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 289 memmove(settings->reg_settings_6g, 290 integrated_info->dp3_ext_hdmi_6g_reg_settings, 291 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 292 result = true; 293 break; 294 default: 295 break; 296 } 297 298 if (result == true) { 299 // Validate settings from bios integrated info table 300 if (settings->slv_addr == 0) 301 return false; 302 if (settings->reg_num > 9) 303 return false; 304 if (settings->reg_num_6g > 3) 305 return false; 306 307 for (i = 0; i < settings->reg_num; i++) { 308 if (settings->reg_settings[i].i2c_reg_index > 0x20) 309 return false; 310 } 311 312 for (i = 0; i < settings->reg_num_6g; i++) { 313 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 314 return false; 315 } 316 } 317 } 318 319 return result; 320 } 321 322 static bool write_i2c(struct pipe_ctx *pipe_ctx, 323 uint8_t address, uint8_t *buffer, uint32_t length) 324 { 325 struct i2c_command cmd = {0}; 326 struct i2c_payload payload = {0}; 327 328 memset(&payload, 0, sizeof(payload)); 329 memset(&cmd, 0, sizeof(cmd)); 330 331 cmd.number_of_payloads = 1; 332 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 333 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 334 335 payload.address = address; 336 payload.data = buffer; 337 payload.length = length; 338 payload.write = true; 339 cmd.payloads = &payload; 340 341 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 342 pipe_ctx->stream->link, &cmd)) 343 return true; 344 345 return false; 346 } 347 348 static void write_i2c_retimer_setting( 349 struct pipe_ctx *pipe_ctx, 350 bool is_vga_mode, 351 bool is_over_340mhz, 352 struct ext_hdmi_settings *settings) 353 { 354 uint8_t slave_address = (settings->slv_addr >> 1); 355 uint8_t buffer[2]; 356 const uint8_t apply_rx_tx_change = 0x4; 357 uint8_t offset = 0xA; 358 uint8_t value = 0; 359 int i = 0; 360 bool i2c_success = false; 361 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 362 363 memset(&buffer, 0, sizeof(buffer)); 364 365 /* Start Ext-Hdmi programming*/ 366 367 for (i = 0; i < settings->reg_num; i++) { 368 /* Apply 3G settings */ 369 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 370 371 buffer[0] = settings->reg_settings[i].i2c_reg_index; 372 buffer[1] = settings->reg_settings[i].i2c_reg_val; 373 i2c_success = write_i2c(pipe_ctx, slave_address, 374 buffer, sizeof(buffer)); 375 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 376 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 377 slave_address, buffer[0], buffer[1], i2c_success?1:0); 378 379 if (!i2c_success) 380 goto i2c_write_fail; 381 382 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 383 * needs to be set to 1 on every 0xA-0xC write. 384 */ 385 if (settings->reg_settings[i].i2c_reg_index == 0xA || 386 settings->reg_settings[i].i2c_reg_index == 0xB || 387 settings->reg_settings[i].i2c_reg_index == 0xC) { 388 389 /* Query current value from offset 0xA */ 390 if (settings->reg_settings[i].i2c_reg_index == 0xA) 391 value = settings->reg_settings[i].i2c_reg_val; 392 else { 393 i2c_success = 394 link_query_ddc_data( 395 pipe_ctx->stream->link->ddc, 396 slave_address, &offset, 1, &value, 1); 397 if (!i2c_success) 398 goto i2c_write_fail; 399 } 400 401 buffer[0] = offset; 402 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 403 buffer[1] = value | apply_rx_tx_change; 404 i2c_success = write_i2c(pipe_ctx, slave_address, 405 buffer, sizeof(buffer)); 406 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 407 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 408 slave_address, buffer[0], buffer[1], i2c_success?1:0); 409 if (!i2c_success) 410 goto i2c_write_fail; 411 } 412 } 413 } 414 415 /* Apply 3G settings */ 416 if (is_over_340mhz) { 417 for (i = 0; i < settings->reg_num_6g; i++) { 418 /* Apply 3G settings */ 419 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 420 421 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 422 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 423 i2c_success = write_i2c(pipe_ctx, slave_address, 424 buffer, sizeof(buffer)); 425 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 426 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 427 slave_address, buffer[0], buffer[1], i2c_success?1:0); 428 429 if (!i2c_success) 430 goto i2c_write_fail; 431 432 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 433 * needs to be set to 1 on every 0xA-0xC write. 434 */ 435 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 436 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 437 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 438 439 /* Query current value from offset 0xA */ 440 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 441 value = settings->reg_settings_6g[i].i2c_reg_val; 442 else { 443 i2c_success = 444 link_query_ddc_data( 445 pipe_ctx->stream->link->ddc, 446 slave_address, &offset, 1, &value, 1); 447 if (!i2c_success) 448 goto i2c_write_fail; 449 } 450 451 buffer[0] = offset; 452 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 453 buffer[1] = value | apply_rx_tx_change; 454 i2c_success = write_i2c(pipe_ctx, slave_address, 455 buffer, sizeof(buffer)); 456 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 457 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 458 slave_address, buffer[0], buffer[1], i2c_success?1:0); 459 if (!i2c_success) 460 goto i2c_write_fail; 461 } 462 } 463 } 464 } 465 466 if (is_vga_mode) { 467 /* Program additional settings if using 640x480 resolution */ 468 469 /* Write offset 0xFF to 0x01 */ 470 buffer[0] = 0xff; 471 buffer[1] = 0x01; 472 i2c_success = write_i2c(pipe_ctx, slave_address, 473 buffer, sizeof(buffer)); 474 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 475 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 476 slave_address, buffer[0], buffer[1], i2c_success?1:0); 477 if (!i2c_success) 478 goto i2c_write_fail; 479 480 /* Write offset 0x00 to 0x23 */ 481 buffer[0] = 0x00; 482 buffer[1] = 0x23; 483 i2c_success = write_i2c(pipe_ctx, slave_address, 484 buffer, sizeof(buffer)); 485 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 486 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 487 slave_address, buffer[0], buffer[1], i2c_success?1:0); 488 if (!i2c_success) 489 goto i2c_write_fail; 490 491 /* Write offset 0xff to 0x00 */ 492 buffer[0] = 0xff; 493 buffer[1] = 0x00; 494 i2c_success = write_i2c(pipe_ctx, slave_address, 495 buffer, sizeof(buffer)); 496 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 497 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 498 slave_address, buffer[0], buffer[1], i2c_success?1:0); 499 if (!i2c_success) 500 goto i2c_write_fail; 501 502 } 503 504 return; 505 506 i2c_write_fail: 507 DC_LOG_DEBUG("Set retimer failed"); 508 } 509 510 static void write_i2c_default_retimer_setting( 511 struct pipe_ctx *pipe_ctx, 512 bool is_vga_mode, 513 bool is_over_340mhz) 514 { 515 uint8_t slave_address = (0xBA >> 1); 516 uint8_t buffer[2]; 517 bool i2c_success = false; 518 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 519 520 memset(&buffer, 0, sizeof(buffer)); 521 522 /* Program Slave Address for tuning single integrity */ 523 /* Write offset 0x0A to 0x13 */ 524 buffer[0] = 0x0A; 525 buffer[1] = 0x13; 526 i2c_success = write_i2c(pipe_ctx, slave_address, 527 buffer, sizeof(buffer)); 528 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 529 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 530 slave_address, buffer[0], buffer[1], i2c_success?1:0); 531 if (!i2c_success) 532 goto i2c_write_fail; 533 534 /* Write offset 0x0A to 0x17 */ 535 buffer[0] = 0x0A; 536 buffer[1] = 0x17; 537 i2c_success = write_i2c(pipe_ctx, slave_address, 538 buffer, sizeof(buffer)); 539 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 540 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 541 slave_address, buffer[0], buffer[1], i2c_success?1:0); 542 if (!i2c_success) 543 goto i2c_write_fail; 544 545 /* Write offset 0x0B to 0xDA or 0xD8 */ 546 buffer[0] = 0x0B; 547 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 548 i2c_success = write_i2c(pipe_ctx, slave_address, 549 buffer, sizeof(buffer)); 550 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 551 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 552 slave_address, buffer[0], buffer[1], i2c_success?1:0); 553 if (!i2c_success) 554 goto i2c_write_fail; 555 556 /* Write offset 0x0A to 0x17 */ 557 buffer[0] = 0x0A; 558 buffer[1] = 0x17; 559 i2c_success = write_i2c(pipe_ctx, slave_address, 560 buffer, sizeof(buffer)); 561 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 562 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 563 slave_address, buffer[0], buffer[1], i2c_success?1:0); 564 if (!i2c_success) 565 goto i2c_write_fail; 566 567 /* Write offset 0x0C to 0x1D or 0x91 */ 568 buffer[0] = 0x0C; 569 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 570 i2c_success = write_i2c(pipe_ctx, slave_address, 571 buffer, sizeof(buffer)); 572 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 573 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 574 slave_address, buffer[0], buffer[1], i2c_success?1:0); 575 if (!i2c_success) 576 goto i2c_write_fail; 577 578 /* Write offset 0x0A to 0x17 */ 579 buffer[0] = 0x0A; 580 buffer[1] = 0x17; 581 i2c_success = write_i2c(pipe_ctx, slave_address, 582 buffer, sizeof(buffer)); 583 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 584 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 585 slave_address, buffer[0], buffer[1], i2c_success?1:0); 586 if (!i2c_success) 587 goto i2c_write_fail; 588 589 590 if (is_vga_mode) { 591 /* Program additional settings if using 640x480 resolution */ 592 593 /* Write offset 0xFF to 0x01 */ 594 buffer[0] = 0xff; 595 buffer[1] = 0x01; 596 i2c_success = write_i2c(pipe_ctx, slave_address, 597 buffer, sizeof(buffer)); 598 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 599 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 600 slave_address, buffer[0], buffer[1], i2c_success?1:0); 601 if (!i2c_success) 602 goto i2c_write_fail; 603 604 /* Write offset 0x00 to 0x23 */ 605 buffer[0] = 0x00; 606 buffer[1] = 0x23; 607 i2c_success = write_i2c(pipe_ctx, slave_address, 608 buffer, sizeof(buffer)); 609 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 610 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 611 slave_address, buffer[0], buffer[1], i2c_success?1:0); 612 if (!i2c_success) 613 goto i2c_write_fail; 614 615 /* Write offset 0xff to 0x00 */ 616 buffer[0] = 0xff; 617 buffer[1] = 0x00; 618 i2c_success = write_i2c(pipe_ctx, slave_address, 619 buffer, sizeof(buffer)); 620 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 621 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 622 slave_address, buffer[0], buffer[1], i2c_success?1:0); 623 if (!i2c_success) 624 goto i2c_write_fail; 625 } 626 627 return; 628 629 i2c_write_fail: 630 DC_LOG_DEBUG("Set default retimer failed"); 631 } 632 633 static void write_i2c_redriver_setting( 634 struct pipe_ctx *pipe_ctx, 635 bool is_over_340mhz) 636 { 637 uint8_t slave_address = (0xF0 >> 1); 638 uint8_t buffer[16]; 639 bool i2c_success = false; 640 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 641 642 memset(&buffer, 0, sizeof(buffer)); 643 644 // Program Slave Address for tuning single integrity 645 buffer[3] = 0x4E; 646 buffer[4] = 0x4E; 647 buffer[5] = 0x4E; 648 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 649 650 i2c_success = write_i2c(pipe_ctx, slave_address, 651 buffer, sizeof(buffer)); 652 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 653 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 654 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 655 i2c_success = %d\n", 656 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 657 658 if (!i2c_success) 659 DC_LOG_DEBUG("Set redriver failed"); 660 } 661 662 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 663 { 664 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 665 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 666 struct cp_psp_stream_config config = {0}; 667 enum dp_panel_mode panel_mode = 668 dp_get_panel_mode(pipe_ctx->stream->link); 669 670 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 671 return; 672 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 673 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 674 ASSERT(link_enc); 675 if (link_enc == NULL) 676 return; 677 678 /* otg instance */ 679 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 680 681 /* dig front end */ 682 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 683 684 /* stream encoder index */ 685 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 686 if (dp_is_128b_132b_signal(pipe_ctx)) 687 config.stream_enc_idx = 688 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 689 690 /* dig back end */ 691 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 692 693 /* link encoder index */ 694 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 695 if (dp_is_128b_132b_signal(pipe_ctx)) 696 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 697 698 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 699 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 700 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 701 else 702 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 703 704 705 /* phy index */ 706 config.phy_idx = resource_transmitter_to_phy_idx( 707 pipe_ctx->stream->link->dc, link_enc->transmitter); 708 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 709 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 710 config.phy_idx = 0; 711 712 /* stream properties */ 713 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 714 config.mst_enabled = (pipe_ctx->stream->signal == 715 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 716 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 717 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 718 1 : 0; 719 config.dpms_off = dpms_off; 720 721 /* dm stream context */ 722 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 723 724 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 725 } 726 727 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 728 { 729 struct dc *dc = pipe_ctx->stream->ctx->dc; 730 731 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 732 return; 733 734 dc->hwss.set_avmute(pipe_ctx, enable); 735 } 736 737 static void enable_mst_on_sink(struct dc_link *link, bool enable) 738 { 739 unsigned char mstmCntl = 0; 740 741 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 742 if (enable) 743 mstmCntl |= DP_MST_EN; 744 else 745 mstmCntl &= (~DP_MST_EN); 746 747 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 748 } 749 750 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 751 struct dsc_optc_config *config) 752 { 753 uint32_t precision = 1 << 28; 754 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 755 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 756 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 757 DC_LOGGER_INIT(dsc->ctx->logger); 758 759 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 760 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 761 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 762 */ 763 ll_bytes_per_pix_fraq *= 10000000; 764 ll_bytes_per_pix_fraq /= precision; 765 766 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 767 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 768 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 769 DC_LOG_DSC("\tslice_width %d", config->slice_width); 770 } 771 772 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 773 { 774 struct dc *dc = pipe_ctx->stream->ctx->dc; 775 struct dc_stream_state *stream = pipe_ctx->stream; 776 bool result = false; 777 778 if (dc_is_virtual_signal(stream->signal)) 779 result = true; 780 else 781 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 782 return result; 783 } 784 785 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 786 { 787 struct dc *dc = pipe_ctx->stream->ctx->dc; 788 struct dc_stream_state *stream = pipe_ctx->stream; 789 bool result = false; 790 791 if (dc_is_virtual_signal(stream->signal)) 792 result = true; 793 else 794 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 795 return result; 796 } 797 798 799 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 800 * i.e. after dp_enable_dsc_on_rx() had been called 801 */ 802 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 803 { 804 /* TODO: Move this to HWSS as this is hardware programming sequence not a 805 * link layer sequence 806 */ 807 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 808 struct dc *dc = pipe_ctx->stream->ctx->dc; 809 struct dc_stream_state *stream = pipe_ctx->stream; 810 struct pipe_ctx *odm_pipe; 811 int opp_cnt = 1; 812 struct dccg *dccg = dc->res_pool->dccg; 813 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 814 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 815 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 816 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 817 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 818 * this problem. We are implementing a workaround here to keep using dscclk 819 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 820 * 48Mhz) pixel clock to avoid hitting this problem. 821 */ 822 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 823 stream->timing.pix_clk_100hz > 480000; 824 DC_LOGGER_INIT(dsc->ctx->logger); 825 826 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 827 opp_cnt++; 828 829 if (enable) { 830 struct dsc_config dsc_cfg; 831 struct dsc_optc_config dsc_optc_cfg = {0}; 832 enum optc_dsc_mode optc_dsc_mode; 833 834 /* Enable DSC hw block */ 835 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + 836 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 837 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 838 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 839 dsc_cfg.color_depth = stream->timing.display_color_depth; 840 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 841 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 842 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 843 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 844 dsc_cfg.dsc_padding = 0; 845 846 if (should_use_dto_dscclk) 847 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 848 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 849 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 850 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 851 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 852 853 if (should_use_dto_dscclk) 854 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 855 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 856 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 857 } 858 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 859 dsc_cfg.pic_width *= opp_cnt; 860 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 861 862 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 863 864 /* Enable DSC in encoder */ 865 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 866 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 867 dsc_optc_config_log(dsc, &dsc_optc_cfg); 868 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 869 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 870 optc_dsc_mode, 871 dsc_optc_cfg.bytes_per_pixel, 872 dsc_optc_cfg.slice_width); 873 874 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 875 } 876 877 /* Enable DSC in OPTC */ 878 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 879 dsc_optc_config_log(dsc, &dsc_optc_cfg); 880 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 881 optc_dsc_mode, 882 dsc_optc_cfg.bytes_per_pixel, 883 dsc_optc_cfg.slice_width); 884 } else { 885 /* disable DSC in OPTC */ 886 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 887 pipe_ctx->stream_res.tg, 888 OPTC_DSC_DISABLED, 0, 0); 889 890 /* disable DSC in stream encoder */ 891 if (dc_is_dp_signal(stream->signal)) { 892 if (dp_is_128b_132b_signal(pipe_ctx)) 893 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 894 pipe_ctx->stream_res.hpo_dp_stream_enc, 895 false, 896 NULL, 897 true); 898 else { 899 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 900 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 901 pipe_ctx->stream_res.stream_enc, 902 OPTC_DSC_DISABLED, 0, 0); 903 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 904 pipe_ctx->stream_res.stream_enc, false, NULL, true); 905 } 906 } 907 908 /* disable DSC block */ 909 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 910 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 911 /* 912 * TODO - dsc_disconnect is a double buffered register. 913 * by the time we call dsc_disable, dsc may still remain 914 * connected to OPP. In this case OPTC will no longer 915 * get correct pixel data because DSCC is off. However 916 * we also can't wait for the disconnect pending 917 * complete, because this function can be called 918 * with/without OTG master lock acquired. When the lock 919 * is acquired we will never get pending complete until 920 * we release the lock later. So there is no easy way to 921 * solve this problem especially when the lock is 922 * acquired. DSC is a front end hw block it should be 923 * programmed as part of front end sequence, where the 924 * commit sequence without lock and update sequence 925 * with lock are completely separated. However because 926 * we are programming dsc as part of back end link 927 * programming sequence, we don't know if front end OPTC 928 * master lock is acquired. The back end should be 929 * agnostic to front end lock. DSC programming shouldn't 930 * belong to this sequence. 931 */ 932 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 933 if (dccg->funcs->set_ref_dscclk) 934 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 935 } 936 } 937 } 938 939 /* 940 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 941 * hence PPS info packet update need to use frame update instead of immediate update. 942 * Added parameter immediate_update for this purpose. 943 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 944 * which is the only place where a "false" would be passed in for param immediate_update. 945 * 946 * immediate_update is only applicable when DSC is enabled. 947 */ 948 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 949 { 950 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 951 struct dc_stream_state *stream = pipe_ctx->stream; 952 953 if (!pipe_ctx->stream->timing.flags.DSC) 954 return false; 955 956 if (!dsc) 957 return false; 958 959 DC_LOGGER_INIT(dsc->ctx->logger); 960 961 if (enable) { 962 struct dsc_config dsc_cfg; 963 uint8_t dsc_packed_pps[128]; 964 965 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 966 memset(dsc_packed_pps, 0, 128); 967 968 /* Enable DSC hw block */ 969 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 970 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 971 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 972 dsc_cfg.color_depth = stream->timing.display_color_depth; 973 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 974 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 975 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 976 977 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 978 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 979 if (dc_is_dp_signal(stream->signal)) { 980 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 981 if (dp_is_128b_132b_signal(pipe_ctx)) 982 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 983 pipe_ctx->stream_res.hpo_dp_stream_enc, 984 true, 985 &dsc_packed_pps[0], 986 immediate_update); 987 else 988 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 989 pipe_ctx->stream_res.stream_enc, 990 true, 991 &dsc_packed_pps[0], 992 immediate_update); 993 } 994 } else { 995 /* disable DSC PPS in stream encoder */ 996 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 997 if (dc_is_dp_signal(stream->signal)) { 998 if (dp_is_128b_132b_signal(pipe_ctx)) 999 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 1000 pipe_ctx->stream_res.hpo_dp_stream_enc, 1001 false, 1002 NULL, 1003 true); 1004 else 1005 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 1006 pipe_ctx->stream_res.stream_enc, false, NULL, true); 1007 } 1008 } 1009 1010 return true; 1011 } 1012 1013 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 1014 { 1015 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1016 bool result = false; 1017 1018 if (!pipe_ctx->stream->timing.flags.DSC) 1019 goto out; 1020 if (!dsc) 1021 goto out; 1022 1023 if (enable) { 1024 { 1025 link_set_dsc_on_stream(pipe_ctx, true); 1026 result = true; 1027 } 1028 } else { 1029 dp_set_dsc_on_rx(pipe_ctx, false); 1030 link_set_dsc_on_stream(pipe_ctx, false); 1031 result = true; 1032 } 1033 out: 1034 return result; 1035 } 1036 1037 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 1038 { 1039 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1040 1041 if (!pipe_ctx->stream->timing.flags.DSC) 1042 return false; 1043 if (!dsc) 1044 return false; 1045 1046 link_set_dsc_on_stream(pipe_ctx, true); 1047 link_set_dsc_pps_packet(pipe_ctx, true, false); 1048 return true; 1049 } 1050 1051 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1052 { 1053 struct dc_stream_state *stream = pipe_ctx->stream; 1054 1055 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1056 struct dc_link *link = stream->link; 1057 union down_spread_ctrl old_downspread; 1058 union down_spread_ctrl new_downspread; 1059 1060 memset(&old_downspread, 0, sizeof(old_downspread)); 1061 1062 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1063 &old_downspread.raw, sizeof(old_downspread)); 1064 1065 new_downspread.raw = old_downspread.raw; 1066 1067 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1068 (stream->ignore_msa_timing_param) ? 1 : 0; 1069 1070 if (new_downspread.raw != old_downspread.raw) { 1071 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1072 &new_downspread.raw, sizeof(new_downspread)); 1073 } 1074 1075 } else { 1076 dm_helpers_mst_enable_stream_features(stream); 1077 } 1078 } 1079 1080 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1081 { 1082 const uint32_t VCP_Y_PRECISION = 1000; 1083 uint64_t vcp_x, vcp_y; 1084 DC_LOGGER_INIT(link->ctx->logger); 1085 1086 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1087 avg_time_slots_per_mtp = dc_fixpt_add( 1088 avg_time_slots_per_mtp, 1089 dc_fixpt_from_fraction( 1090 1, 1091 2*VCP_Y_PRECISION)); 1092 1093 vcp_x = dc_fixpt_floor( 1094 avg_time_slots_per_mtp); 1095 vcp_y = dc_fixpt_floor( 1096 dc_fixpt_mul_int( 1097 dc_fixpt_sub_int( 1098 avg_time_slots_per_mtp, 1099 dc_fixpt_floor( 1100 avg_time_slots_per_mtp)), 1101 VCP_Y_PRECISION)); 1102 1103 1104 if (link->type == dc_connection_mst_branch) 1105 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1106 "X: %llu " 1107 "Y: %llu/%d", 1108 vcp_x, 1109 vcp_y, 1110 VCP_Y_PRECISION); 1111 else 1112 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1113 "X: %llu " 1114 "Y: %llu/%d", 1115 vcp_x, 1116 vcp_y, 1117 VCP_Y_PRECISION); 1118 } 1119 1120 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1121 { 1122 struct fixed31_32 mbytes_per_sec; 1123 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1124 &stream->link->cur_link_settings); 1125 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1126 1127 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1128 1129 return dc_fixpt_div_int(mbytes_per_sec, 54); 1130 } 1131 1132 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1133 { 1134 struct fixed31_32 peak_kbps; 1135 uint32_t numerator = 0; 1136 uint32_t denominator = 1; 1137 1138 /* 1139 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1140 * required when determining PBN/time slot utilization on the link between 1141 * us and the branch, since that overhead is already accounted for in 1142 * the get_pbn_per_slot function. 1143 * 1144 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1145 * common multiplier to render an integer PBN for all link rate/lane 1146 * counts combinations 1147 * calculate 1148 * peak_kbps *= (64/54) 1149 * peak_kbps /= (8 * 1000) convert to bytes 1150 */ 1151 1152 numerator = 64; 1153 denominator = 54 * 8 * 1000; 1154 kbps *= numerator; 1155 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1156 1157 return peak_kbps; 1158 } 1159 1160 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1161 { 1162 uint64_t kbps; 1163 enum dc_link_encoding_format link_encoding; 1164 1165 if (dp_is_128b_132b_signal(pipe_ctx)) 1166 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1167 else 1168 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1169 1170 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1171 return get_pbn_from_bw_in_kbps(kbps); 1172 } 1173 1174 1175 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1176 static void get_lane_status( 1177 struct dc_link *link, 1178 uint32_t lane_count, 1179 union lane_status *status, 1180 union lane_align_status_updated *status_updated) 1181 { 1182 unsigned int lane; 1183 uint8_t dpcd_buf[3] = {0}; 1184 1185 if (status == NULL || status_updated == NULL) { 1186 return; 1187 } 1188 1189 core_link_read_dpcd( 1190 link, 1191 DP_LANE0_1_STATUS, 1192 dpcd_buf, 1193 sizeof(dpcd_buf)); 1194 1195 for (lane = 0; lane < lane_count; lane++) { 1196 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1197 } 1198 1199 status_updated->raw = dpcd_buf[2]; 1200 } 1201 1202 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1203 { 1204 /* 1205 * wait for ACT handled 1206 */ 1207 int i; 1208 const int act_retries = 30; 1209 enum act_return_status result = ACT_FAILED; 1210 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1211 union payload_table_update_status update_status = {0}; 1212 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1213 union lane_align_status_updated lane_status_updated; 1214 DC_LOGGER_INIT(link->ctx->logger); 1215 1216 if (!display_connected || link->aux_access_disabled) 1217 return true; 1218 for (i = 0; i < act_retries; i++) { 1219 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1220 1221 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1222 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1223 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1224 !dp_is_interlane_aligned(lane_status_updated)) { 1225 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1226 "polling for ACT handled."); 1227 result = ACT_LINK_LOST; 1228 break; 1229 } 1230 core_link_read_dpcd( 1231 link, 1232 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1233 &update_status.raw, 1234 1); 1235 1236 if (update_status.bits.ACT_HANDLED == 1) { 1237 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1238 result = ACT_SUCCESS; 1239 break; 1240 } 1241 1242 fsleep(5000); 1243 } 1244 1245 if (result == ACT_FAILED) { 1246 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1247 "continue on. Something is wrong with the branch."); 1248 } 1249 1250 return (result == ACT_SUCCESS); 1251 } 1252 1253 static void update_mst_stream_alloc_table( 1254 struct dc_link *link, 1255 struct stream_encoder *stream_enc, 1256 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1257 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1258 { 1259 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1260 struct link_mst_stream_allocation *dc_alloc; 1261 1262 int i; 1263 int j; 1264 1265 /* if DRM proposed_table has more than one new payload */ 1266 ASSERT(proposed_table->stream_count - 1267 link->mst_stream_alloc_table.stream_count < 2); 1268 1269 /* copy proposed_table to link, add stream encoder */ 1270 for (i = 0; i < proposed_table->stream_count; i++) { 1271 1272 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1273 dc_alloc = 1274 &link->mst_stream_alloc_table.stream_allocations[j]; 1275 1276 if (dc_alloc->vcp_id == 1277 proposed_table->stream_allocations[i].vcp_id) { 1278 1279 work_table[i] = *dc_alloc; 1280 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1281 break; /* exit j loop */ 1282 } 1283 } 1284 1285 /* new vcp_id */ 1286 if (j == link->mst_stream_alloc_table.stream_count) { 1287 work_table[i].vcp_id = 1288 proposed_table->stream_allocations[i].vcp_id; 1289 work_table[i].slot_count = 1290 proposed_table->stream_allocations[i].slot_count; 1291 work_table[i].stream_enc = stream_enc; 1292 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1293 } 1294 } 1295 1296 /* update link->mst_stream_alloc_table with work_table */ 1297 link->mst_stream_alloc_table.stream_count = 1298 proposed_table->stream_count; 1299 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1300 link->mst_stream_alloc_table.stream_allocations[i] = 1301 work_table[i]; 1302 } 1303 1304 static void remove_stream_from_alloc_table( 1305 struct dc_link *link, 1306 struct stream_encoder *dio_stream_enc, 1307 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1308 { 1309 int i = 0; 1310 struct link_mst_stream_allocation_table *table = 1311 &link->mst_stream_alloc_table; 1312 1313 if (hpo_dp_stream_enc) { 1314 for (; i < table->stream_count; i++) 1315 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1316 break; 1317 } else { 1318 for (; i < table->stream_count; i++) 1319 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1320 break; 1321 } 1322 1323 if (i < table->stream_count) { 1324 i++; 1325 for (; i < table->stream_count; i++) 1326 table->stream_allocations[i-1] = table->stream_allocations[i]; 1327 memset(&table->stream_allocations[table->stream_count-1], 0, 1328 sizeof(struct link_mst_stream_allocation)); 1329 table->stream_count--; 1330 } 1331 } 1332 1333 static void print_mst_streams(struct dc_link *link) 1334 { 1335 int i; 1336 1337 DC_LOGGER_INIT(link->ctx->logger); 1338 1339 DC_LOG_MST("%s stream_count: %d:\n", 1340 __func__, 1341 link->mst_stream_alloc_table.stream_count); 1342 1343 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1344 DC_LOG_MST("stream_enc[%d]: %p\n", i, 1345 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc); 1346 DC_LOG_MST("stream[%d].hpo_dp_stream_enc: %p\n", i, 1347 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc); 1348 DC_LOG_MST("stream[%d].vcp_id: %d\n", i, 1349 link->mst_stream_alloc_table.stream_allocations[i].vcp_id); 1350 DC_LOG_MST("stream[%d].slot_count: %d\n", i, 1351 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1352 } 1353 } 1354 1355 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1356 { 1357 struct dc_stream_state *stream = pipe_ctx->stream; 1358 struct dc_link *link = stream->link; 1359 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1360 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1361 bool mst_mode = (link->type == dc_connection_mst_branch); 1362 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1363 const struct dc_link_settings empty_link_settings = {0}; 1364 DC_LOGGER_INIT(link->ctx->logger); 1365 1366 /* deallocate_mst_payload is called before disable link. When mode or 1367 * disable/enable monitor, new stream is created which is not in link 1368 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1369 * should not done. For new mode set, map_resources will get engine 1370 * for new stream, so stream_enc->id should be validated until here. 1371 */ 1372 1373 /* slot X.Y */ 1374 if (link_hwss->ext.set_throttled_vcp_size) 1375 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1376 if (link_hwss->ext.set_hblank_min_symbol_width) 1377 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1378 &empty_link_settings, 1379 avg_time_slots_per_mtp); 1380 1381 if (mst_mode) { 1382 /* when link is in mst mode, reply on mst manager to remove 1383 * payload 1384 */ 1385 if (dm_helpers_dp_mst_write_payload_allocation_table( 1386 stream->ctx, 1387 stream, 1388 &proposed_table, 1389 false)) 1390 update_mst_stream_alloc_table( 1391 link, 1392 pipe_ctx->stream_res.stream_enc, 1393 pipe_ctx->stream_res.hpo_dp_stream_enc, 1394 &proposed_table); 1395 else 1396 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1397 pipe_ctx->pipe_idx); 1398 } else { 1399 /* when link is no longer in mst mode (mst hub unplugged), 1400 * remove payload with default dc logic 1401 */ 1402 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1403 pipe_ctx->stream_res.hpo_dp_stream_enc); 1404 } 1405 1406 print_mst_streams(link); 1407 1408 /* update mst stream allocation table hardware state */ 1409 if (link_hwss->ext.update_stream_allocation_table == NULL || 1410 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1411 DC_LOG_DEBUG("Unknown encoding format\n"); 1412 return DC_ERROR_UNEXPECTED; 1413 } 1414 1415 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1416 &link->mst_stream_alloc_table); 1417 1418 if (mst_mode) 1419 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1420 stream->ctx, 1421 stream); 1422 1423 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1424 stream->ctx, 1425 stream); 1426 1427 return DC_OK; 1428 } 1429 1430 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1431 * because stream_encoder is not exposed to dm 1432 */ 1433 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1434 { 1435 struct dc_stream_state *stream = pipe_ctx->stream; 1436 struct dc_link *link = stream->link; 1437 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1438 struct fixed31_32 avg_time_slots_per_mtp; 1439 struct fixed31_32 pbn; 1440 struct fixed31_32 pbn_per_slot; 1441 enum act_return_status ret; 1442 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1443 DC_LOGGER_INIT(link->ctx->logger); 1444 1445 /* enable_link_dp_mst already check link->enabled_stream_count 1446 * and stream is in link->stream[]. This is called during set mode, 1447 * stream_enc is available. 1448 */ 1449 1450 /* get calculate VC payload for stream: stream_alloc */ 1451 if (dm_helpers_dp_mst_write_payload_allocation_table( 1452 stream->ctx, 1453 stream, 1454 &proposed_table, 1455 true)) 1456 update_mst_stream_alloc_table( 1457 link, 1458 pipe_ctx->stream_res.stream_enc, 1459 pipe_ctx->stream_res.hpo_dp_stream_enc, 1460 &proposed_table); 1461 else 1462 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1463 pipe_ctx->pipe_idx); 1464 1465 print_mst_streams(link); 1466 1467 ASSERT(proposed_table.stream_count > 0); 1468 1469 /* program DP source TX for payload */ 1470 if (link_hwss->ext.update_stream_allocation_table == NULL || 1471 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1472 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1473 return DC_ERROR_UNEXPECTED; 1474 } 1475 1476 link_hwss->ext.update_stream_allocation_table(link, 1477 &pipe_ctx->link_res, 1478 &link->mst_stream_alloc_table); 1479 1480 /* send down message */ 1481 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1482 stream->ctx, 1483 stream); 1484 1485 if (ret != ACT_LINK_LOST) 1486 dm_helpers_dp_mst_send_payload_allocation( 1487 stream->ctx, 1488 stream); 1489 1490 /* slot X.Y for only current stream */ 1491 pbn_per_slot = get_pbn_per_slot(stream); 1492 if (pbn_per_slot.value == 0) { 1493 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1494 return DC_UNSUPPORTED_VALUE; 1495 } 1496 pbn = get_pbn_from_timing(pipe_ctx); 1497 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1498 1499 log_vcp_x_y(link, avg_time_slots_per_mtp); 1500 1501 if (link_hwss->ext.set_throttled_vcp_size) 1502 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1503 if (link_hwss->ext.set_hblank_min_symbol_width) 1504 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1505 &link->cur_link_settings, 1506 avg_time_slots_per_mtp); 1507 1508 return DC_OK; 1509 } 1510 1511 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1512 const struct dc_stream_state *stream, 1513 const struct dc_link *link) 1514 { 1515 struct fixed31_32 link_bw_effective = 1516 dc_fixpt_from_int( 1517 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1518 struct fixed31_32 timeslot_bw_effective = 1519 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1520 struct fixed31_32 timing_bw = 1521 dc_fixpt_from_int( 1522 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1523 dc_link_get_highest_encoding_format(link))); 1524 struct fixed31_32 avg_time_slots_per_mtp = 1525 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1526 1527 return avg_time_slots_per_mtp; 1528 } 1529 1530 1531 static bool write_128b_132b_sst_payload_allocation_table( 1532 const struct dc_stream_state *stream, 1533 struct dc_link *link, 1534 struct link_mst_stream_allocation_table *proposed_table, 1535 bool allocate) 1536 { 1537 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1538 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1539 bool result = false; 1540 uint8_t req_slot_count = 0; 1541 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1542 union payload_table_update_status update_status = { 0 }; 1543 const uint32_t max_retries = 30; 1544 uint32_t retries = 0; 1545 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1546 DC_LOGGER_INIT(link->ctx->logger); 1547 1548 if (allocate) { 1549 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1550 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1551 /// Validation should filter out modes that exceed link BW 1552 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1553 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1554 return false; 1555 } else { 1556 /// Leave req_slot_count = 0 if allocate is false. 1557 } 1558 1559 proposed_table->stream_count = 1; /// Always 1 stream for SST 1560 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1561 proposed_table->stream_allocations[0].vcp_id = vc_id; 1562 1563 if (!display_connected || link->aux_access_disabled) 1564 return true; 1565 1566 /// Write DPCD 2C0 = 1 to start updating 1567 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1568 core_link_write_dpcd( 1569 link, 1570 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1571 &update_status.raw, 1572 1); 1573 1574 /// Program the changes in DPCD 1C0 - 1C2 1575 ASSERT(vc_id == 1); 1576 core_link_write_dpcd( 1577 link, 1578 DP_PAYLOAD_ALLOCATE_SET, 1579 &vc_id, 1580 1); 1581 1582 ASSERT(start_time_slot == 0); 1583 core_link_write_dpcd( 1584 link, 1585 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1586 &start_time_slot, 1587 1); 1588 1589 core_link_write_dpcd( 1590 link, 1591 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1592 &req_slot_count, 1593 1); 1594 1595 /// Poll till DPCD 2C0 read 1 1596 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1597 1598 while (retries < max_retries) { 1599 if (core_link_read_dpcd( 1600 link, 1601 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1602 &update_status.raw, 1603 1) == DC_OK) { 1604 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1605 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1606 result = true; 1607 break; 1608 } 1609 } else { 1610 union dpcd_rev dpcdRev = {0}; 1611 1612 if (core_link_read_dpcd( 1613 link, 1614 DP_DPCD_REV, 1615 &dpcdRev.raw, 1616 1) != DC_OK) { 1617 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1618 "of sink while polling payload table " 1619 "updated status bit."); 1620 break; 1621 } 1622 } 1623 retries++; 1624 fsleep(5000); 1625 } 1626 1627 if (!result && retries == max_retries) { 1628 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1629 "continue on. Something is wrong with the branch."); 1630 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1631 } 1632 1633 return result; 1634 } 1635 1636 /* 1637 * Payload allocation/deallocation for SST introduced in DP2.0 1638 */ 1639 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1640 bool allocate) 1641 { 1642 struct dc_stream_state *stream = pipe_ctx->stream; 1643 struct dc_link *link = stream->link; 1644 struct link_mst_stream_allocation_table proposed_table = {0}; 1645 struct fixed31_32 avg_time_slots_per_mtp; 1646 const struct dc_link_settings empty_link_settings = {0}; 1647 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1648 DC_LOGGER_INIT(link->ctx->logger); 1649 1650 /* slot X.Y for SST payload deallocate */ 1651 if (!allocate) { 1652 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1653 1654 log_vcp_x_y(link, avg_time_slots_per_mtp); 1655 1656 if (link_hwss->ext.set_throttled_vcp_size) 1657 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1658 avg_time_slots_per_mtp); 1659 if (link_hwss->ext.set_hblank_min_symbol_width) 1660 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1661 &empty_link_settings, 1662 avg_time_slots_per_mtp); 1663 } 1664 1665 /* calculate VC payload and update branch with new payload allocation table*/ 1666 if (!write_128b_132b_sst_payload_allocation_table( 1667 stream, 1668 link, 1669 &proposed_table, 1670 allocate)) { 1671 DC_LOG_ERROR("SST Update Payload: Failed to update " 1672 "allocation table for " 1673 "pipe idx: %d\n", 1674 pipe_ctx->pipe_idx); 1675 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1676 } 1677 1678 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1679 1680 ASSERT(proposed_table.stream_count == 1); 1681 1682 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1683 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1684 "vcp_id: %d " 1685 "slot_count: %d\n", 1686 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1687 proposed_table.stream_allocations[0].vcp_id, 1688 proposed_table.stream_allocations[0].slot_count); 1689 1690 /* program DP source TX for payload */ 1691 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1692 &proposed_table); 1693 1694 /* poll for ACT handled */ 1695 if (!poll_for_allocation_change_trigger(link)) { 1696 // Failures will result in blackscreen and errors logged 1697 BREAK_TO_DEBUGGER(); 1698 } 1699 1700 /* slot X.Y for SST payload allocate */ 1701 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1702 DP_128b_132b_ENCODING) { 1703 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1704 1705 log_vcp_x_y(link, avg_time_slots_per_mtp); 1706 1707 if (link_hwss->ext.set_throttled_vcp_size) 1708 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1709 avg_time_slots_per_mtp); 1710 if (link_hwss->ext.set_hblank_min_symbol_width) 1711 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1712 &link->cur_link_settings, 1713 avg_time_slots_per_mtp); 1714 } 1715 1716 /* Always return DC_OK. 1717 * If part of sequence fails, log failure(s) and show blackscreen 1718 */ 1719 return DC_OK; 1720 } 1721 1722 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1723 { 1724 struct dc_stream_state *stream = pipe_ctx->stream; 1725 struct dc_link *link = stream->link; 1726 struct fixed31_32 avg_time_slots_per_mtp; 1727 struct fixed31_32 pbn; 1728 struct fixed31_32 pbn_per_slot; 1729 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1730 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1731 DC_LOGGER_INIT(link->ctx->logger); 1732 1733 /* decrease throttled vcp size */ 1734 pbn_per_slot = get_pbn_per_slot(stream); 1735 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1736 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1737 1738 if (link_hwss->ext.set_throttled_vcp_size) 1739 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1740 if (link_hwss->ext.set_hblank_min_symbol_width) 1741 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1742 &link->cur_link_settings, 1743 avg_time_slots_per_mtp); 1744 1745 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1746 dm_helpers_dp_mst_send_payload_allocation( 1747 stream->ctx, 1748 stream); 1749 1750 /* notify immediate branch device table update */ 1751 if (dm_helpers_dp_mst_write_payload_allocation_table( 1752 stream->ctx, 1753 stream, 1754 &proposed_table, 1755 true)) { 1756 /* update mst stream allocation table software state */ 1757 update_mst_stream_alloc_table( 1758 link, 1759 pipe_ctx->stream_res.stream_enc, 1760 pipe_ctx->stream_res.hpo_dp_stream_enc, 1761 &proposed_table); 1762 } else { 1763 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1764 pipe_ctx->pipe_idx); 1765 } 1766 1767 print_mst_streams(link); 1768 1769 ASSERT(proposed_table.stream_count > 0); 1770 1771 /* update mst stream allocation table hardware state */ 1772 if (link_hwss->ext.update_stream_allocation_table == NULL || 1773 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1774 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1775 return DC_ERROR_UNEXPECTED; 1776 } 1777 1778 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1779 &link->mst_stream_alloc_table); 1780 1781 /* poll for immediate branch device ACT handled */ 1782 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1783 stream->ctx, 1784 stream); 1785 1786 return DC_OK; 1787 } 1788 1789 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1790 { 1791 struct dc_stream_state *stream = pipe_ctx->stream; 1792 struct dc_link *link = stream->link; 1793 struct fixed31_32 avg_time_slots_per_mtp; 1794 struct fixed31_32 pbn; 1795 struct fixed31_32 pbn_per_slot; 1796 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1797 enum act_return_status ret; 1798 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1799 DC_LOGGER_INIT(link->ctx->logger); 1800 1801 /* notify immediate branch device table update */ 1802 if (dm_helpers_dp_mst_write_payload_allocation_table( 1803 stream->ctx, 1804 stream, 1805 &proposed_table, 1806 true)) { 1807 /* update mst stream allocation table software state */ 1808 update_mst_stream_alloc_table( 1809 link, 1810 pipe_ctx->stream_res.stream_enc, 1811 pipe_ctx->stream_res.hpo_dp_stream_enc, 1812 &proposed_table); 1813 } 1814 1815 print_mst_streams(link); 1816 1817 ASSERT(proposed_table.stream_count > 0); 1818 1819 /* update mst stream allocation table hardware state */ 1820 if (link_hwss->ext.update_stream_allocation_table == NULL || 1821 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1822 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1823 return DC_ERROR_UNEXPECTED; 1824 } 1825 1826 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1827 &link->mst_stream_alloc_table); 1828 1829 /* poll for immediate branch device ACT handled */ 1830 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1831 stream->ctx, 1832 stream); 1833 1834 if (ret != ACT_LINK_LOST) { 1835 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1836 dm_helpers_dp_mst_send_payload_allocation( 1837 stream->ctx, 1838 stream); 1839 } 1840 1841 /* increase throttled vcp size */ 1842 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1843 pbn_per_slot = get_pbn_per_slot(stream); 1844 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1845 1846 if (link_hwss->ext.set_throttled_vcp_size) 1847 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1848 if (link_hwss->ext.set_hblank_min_symbol_width) 1849 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1850 &link->cur_link_settings, 1851 avg_time_slots_per_mtp); 1852 1853 return DC_OK; 1854 } 1855 1856 static void disable_link_dp(struct dc_link *link, 1857 const struct link_resource *link_res, 1858 enum signal_type signal) 1859 { 1860 struct dc_link_settings link_settings = link->cur_link_settings; 1861 1862 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1863 link->mst_stream_alloc_table.stream_count > 0) 1864 /* disable MST link only when last vc payload is deallocated */ 1865 return; 1866 1867 dp_disable_link_phy(link, link_res, signal); 1868 1869 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1870 if (!link->skip_implict_edp_power_control) 1871 link->dc->hwss.edp_power_control(link, false); 1872 } 1873 1874 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->sink_count == 0) 1875 /* set the sink to SST mode after disabling the link */ 1876 enable_mst_on_sink(link, false); 1877 1878 if (link_dp_get_encoding_format(&link_settings) == 1879 DP_8b_10b_ENCODING) { 1880 dp_set_fec_enable(link, link_res, false); 1881 dp_set_fec_ready(link, link_res, false); 1882 } 1883 } 1884 1885 static void disable_link(struct dc_link *link, 1886 const struct link_resource *link_res, 1887 enum signal_type signal) 1888 { 1889 if (dc_is_dp_signal(signal)) { 1890 disable_link_dp(link, link_res, signal); 1891 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1892 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1893 } else { 1894 link->dc->hwss.disable_link_output(link, link_res, signal); 1895 } 1896 1897 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1898 /* MST disable link only when no stream use the link */ 1899 if (link->mst_stream_alloc_table.stream_count <= 0) 1900 link->link_status.link_active = false; 1901 } else { 1902 link->link_status.link_active = false; 1903 } 1904 } 1905 1906 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1907 { 1908 struct dc_stream_state *stream = pipe_ctx->stream; 1909 struct dc_link *link = stream->link; 1910 enum dc_color_depth display_color_depth; 1911 enum engine_id eng_id; 1912 struct ext_hdmi_settings settings = {0}; 1913 bool is_over_340mhz = false; 1914 bool is_vga_mode = (stream->timing.h_addressable == 640) 1915 && (stream->timing.v_addressable == 480); 1916 struct dc *dc = pipe_ctx->stream->ctx->dc; 1917 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1918 1919 if (stream->phy_pix_clk == 0) 1920 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1921 if (stream->phy_pix_clk > 340000) 1922 is_over_340mhz = true; 1923 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1924 ASSERT(false); 1925 return; 1926 } 1927 1928 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1929 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1930 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1931 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1932 /* DP159, Retimer settings */ 1933 eng_id = pipe_ctx->stream_res.stream_enc->id; 1934 1935 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1936 write_i2c_retimer_setting(pipe_ctx, 1937 is_vga_mode, is_over_340mhz, &settings); 1938 } else { 1939 write_i2c_default_retimer_setting(pipe_ctx, 1940 is_vga_mode, is_over_340mhz); 1941 } 1942 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1943 /* PI3EQX1204, Redriver settings */ 1944 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1945 } 1946 } 1947 1948 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1949 write_scdc_data( 1950 stream->link->ddc, 1951 stream->phy_pix_clk, 1952 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 1953 1954 memset(&stream->link->cur_link_settings, 0, 1955 sizeof(struct dc_link_settings)); 1956 1957 display_color_depth = stream->timing.display_color_depth; 1958 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1959 display_color_depth = COLOR_DEPTH_888; 1960 1961 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 1962 * character clock in case that beyond 340MHz. 1963 */ 1964 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 1965 link_hwss->setup_stream_encoder(pipe_ctx); 1966 1967 dc->hwss.enable_tmds_link_output( 1968 link, 1969 &pipe_ctx->link_res, 1970 pipe_ctx->stream->signal, 1971 pipe_ctx->clock_source->id, 1972 display_color_depth, 1973 stream->phy_pix_clk); 1974 1975 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1976 read_scdc_data(link->ddc); 1977 } 1978 1979 static enum dc_status enable_link_dp(struct dc_state *state, 1980 struct pipe_ctx *pipe_ctx) 1981 { 1982 struct dc_stream_state *stream = pipe_ctx->stream; 1983 enum dc_status status; 1984 bool skip_video_pattern; 1985 struct dc_link *link = stream->link; 1986 const struct dc_link_settings *link_settings = 1987 &pipe_ctx->link_config.dp_link_settings; 1988 bool fec_enable; 1989 int i; 1990 bool apply_seamless_boot_optimization = false; 1991 uint32_t bl_oled_enable_delay = 50; // in ms 1992 uint32_t post_oui_delay = 30; // 30ms 1993 /* Reduce link bandwidth between failed link training attempts. */ 1994 bool do_fallback = false; 1995 int lt_attempts = LINK_TRAINING_ATTEMPTS; 1996 1997 // Increase retry count if attempting DP1.x on FIXED_VS link 1998 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 1999 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2000 lt_attempts = 10; 2001 2002 // check for seamless boot 2003 for (i = 0; i < state->stream_count; i++) { 2004 if (state->streams[i]->apply_seamless_boot_optimization) { 2005 apply_seamless_boot_optimization = true; 2006 break; 2007 } 2008 } 2009 2010 /* Train with fallback when enabling DPIA link. Conventional links are 2011 * trained with fallback during sink detection. 2012 */ 2013 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2014 !link->dc->config.enable_dpia_pre_training) 2015 do_fallback = true; 2016 2017 /* 2018 * Temporary w/a to get DP2.0 link rates to work with SST. 2019 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2020 */ 2021 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2022 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2023 link->dc->debug.set_mst_en_for_sst) { 2024 enable_mst_on_sink(link, true); 2025 } else if (link->dpcd_caps.is_mst_capable && 2026 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2027 /* disable mst on sink */ 2028 enable_mst_on_sink(link, false); 2029 } 2030 2031 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2032 /*in case it is not on*/ 2033 if (!link->dc->config.edp_no_power_sequencing) 2034 link->dc->hwss.edp_power_control(link, true); 2035 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2036 } 2037 2038 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2039 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2040 } else { 2041 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2042 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2043 if (state->clk_mgr && !apply_seamless_boot_optimization) 2044 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2045 state, false); 2046 } 2047 2048 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2049 dpcd_set_source_specific_data(link); 2050 if (link->dpcd_sink_ext_caps.raw != 0) { 2051 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2052 msleep(post_oui_delay); 2053 } 2054 2055 // similarly, mode switch can cause loss of cable ID 2056 dpcd_write_cable_id_to_dprx(link); 2057 2058 skip_video_pattern = true; 2059 2060 if (link_settings->link_rate == LINK_RATE_LOW) 2061 skip_video_pattern = false; 2062 2063 if (stream->sink_patches.oled_optimize_display_on) 2064 set_default_brightness(link); 2065 2066 if (perform_link_training_with_retries(link_settings, 2067 skip_video_pattern, 2068 lt_attempts, 2069 pipe_ctx, 2070 pipe_ctx->stream->signal, 2071 do_fallback)) { 2072 status = DC_OK; 2073 } else { 2074 status = DC_FAIL_DP_LINK_TRAINING; 2075 } 2076 2077 if (link->preferred_training_settings.fec_enable) 2078 fec_enable = *link->preferred_training_settings.fec_enable; 2079 else 2080 fec_enable = true; 2081 2082 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2083 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 2084 2085 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2086 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2087 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2088 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2089 if (!stream->sink_patches.oled_optimize_display_on) { 2090 set_default_brightness(link); 2091 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2092 msleep(bl_oled_enable_delay); 2093 edp_backlight_enable_aux(link, true); 2094 } else { 2095 edp_backlight_enable_aux(link, true); 2096 } 2097 } 2098 2099 return status; 2100 } 2101 2102 static enum dc_status enable_link_edp( 2103 struct dc_state *state, 2104 struct pipe_ctx *pipe_ctx) 2105 { 2106 return enable_link_dp(state, pipe_ctx); 2107 } 2108 2109 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2110 { 2111 struct dc_stream_state *stream = pipe_ctx->stream; 2112 struct dc_link *link = stream->link; 2113 struct dc *dc = stream->ctx->dc; 2114 2115 if (stream->phy_pix_clk == 0) 2116 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2117 2118 memset(&stream->link->cur_link_settings, 0, 2119 sizeof(struct dc_link_settings)); 2120 dc->hwss.enable_lvds_link_output( 2121 link, 2122 &pipe_ctx->link_res, 2123 pipe_ctx->clock_source->id, 2124 stream->phy_pix_clk); 2125 2126 } 2127 2128 static enum dc_status enable_link_dp_mst( 2129 struct dc_state *state, 2130 struct pipe_ctx *pipe_ctx) 2131 { 2132 struct dc_link *link = pipe_ctx->stream->link; 2133 unsigned char mstm_cntl = 0; 2134 2135 /* sink signal type after MST branch is MST. Multiple MST sinks 2136 * share one link. Link DP PHY is enable or training only once. 2137 */ 2138 if (link->link_status.link_active) 2139 return DC_OK; 2140 2141 /* clear payload table */ 2142 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2143 if (mstm_cntl & DP_MST_EN) 2144 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2145 2146 /* to make sure the pending down rep can be processed 2147 * before enabling the link 2148 */ 2149 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2150 2151 /* set the sink to MST mode before enabling the link */ 2152 enable_mst_on_sink(link, true); 2153 2154 return enable_link_dp(state, pipe_ctx); 2155 } 2156 2157 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2158 { 2159 struct dc_link *link = pipe_ctx->stream->link; 2160 2161 link->dc->hwss.enable_dp_link_output(link, 2162 &pipe_ctx->link_res, 2163 SIGNAL_TYPE_DISPLAY_PORT, 2164 pipe_ctx->clock_source->id, 2165 &pipe_ctx->link_config.dp_link_settings); 2166 return DC_OK; 2167 } 2168 2169 static enum dc_status enable_link( 2170 struct dc_state *state, 2171 struct pipe_ctx *pipe_ctx) 2172 { 2173 enum dc_status status = DC_ERROR_UNEXPECTED; 2174 struct dc_stream_state *stream = pipe_ctx->stream; 2175 struct dc_link *link = NULL; 2176 2177 if (stream == NULL) 2178 return DC_ERROR_UNEXPECTED; 2179 link = stream->link; 2180 2181 /* There's some scenarios where driver is unloaded with display 2182 * still enabled. When driver is reloaded, it may cause a display 2183 * to not light up if there is a mismatch between old and new 2184 * link settings. Need to call disable first before enabling at 2185 * new link settings. 2186 */ 2187 if (link->link_status.link_active) 2188 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2189 2190 switch (pipe_ctx->stream->signal) { 2191 case SIGNAL_TYPE_DISPLAY_PORT: 2192 status = enable_link_dp(state, pipe_ctx); 2193 break; 2194 case SIGNAL_TYPE_EDP: 2195 status = enable_link_edp(state, pipe_ctx); 2196 break; 2197 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2198 status = enable_link_dp_mst(state, pipe_ctx); 2199 msleep(200); 2200 break; 2201 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2202 case SIGNAL_TYPE_DVI_DUAL_LINK: 2203 case SIGNAL_TYPE_HDMI_TYPE_A: 2204 enable_link_hdmi(pipe_ctx); 2205 status = DC_OK; 2206 break; 2207 case SIGNAL_TYPE_LVDS: 2208 enable_link_lvds(pipe_ctx); 2209 status = DC_OK; 2210 break; 2211 case SIGNAL_TYPE_RGB: 2212 status = DC_OK; 2213 break; 2214 case SIGNAL_TYPE_VIRTUAL: 2215 status = enable_link_virtual(pipe_ctx); 2216 break; 2217 default: 2218 break; 2219 } 2220 2221 if (status == DC_OK) { 2222 pipe_ctx->stream->link->link_status.link_active = true; 2223 } 2224 2225 return status; 2226 } 2227 2228 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2229 { 2230 struct dc_link *link = stream->sink->link; 2231 int req_bw = bw; 2232 2233 DC_LOGGER_INIT(link->ctx->logger); 2234 2235 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2236 return false; 2237 2238 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2239 int sink_index = 0; 2240 int i = 0; 2241 2242 for (i = 0; i < link->sink_count; i++) { 2243 if (link->remote_sinks[i] == NULL) 2244 continue; 2245 2246 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2247 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2248 else 2249 sink_index = i; 2250 } 2251 2252 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2253 } 2254 2255 link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); 2256 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2257 2258 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2259 2260 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2261 int i = 0; 2262 2263 for (i = 0; i < link->sink_count; i++) { 2264 if (link->remote_sinks[i] == NULL) 2265 continue; 2266 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2267 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2268 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2269 } 2270 } 2271 2272 return true; 2273 } 2274 2275 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2276 { 2277 bool ret; 2278 2279 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2280 dc_link_get_highest_encoding_format(stream->sink->link)); 2281 2282 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2283 2284 return ret; 2285 } 2286 2287 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2288 { 2289 bool ret; 2290 2291 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2292 2293 return ret; 2294 } 2295 2296 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2297 { 2298 struct dc *dc = pipe_ctx->stream->ctx->dc; 2299 struct dc_stream_state *stream = pipe_ctx->stream; 2300 struct dc_link *link = stream->sink->link; 2301 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2302 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2303 2304 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2305 2306 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2307 2308 if (dp_is_128b_132b_signal(pipe_ctx)) 2309 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2310 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2311 return; 2312 2313 if (pipe_ctx->stream->sink) { 2314 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2315 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2316 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2317 pipe_ctx->stream->sink->edid_caps.display_name, 2318 pipe_ctx->stream->signal, link->link_index, link->sink_count); 2319 } 2320 } 2321 2322 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2323 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2324 set_avmute(pipe_ctx, true); 2325 } 2326 2327 dc->hwss.disable_audio_stream(pipe_ctx); 2328 2329 update_psp_stream_config(pipe_ctx, true); 2330 dc->hwss.blank_stream(pipe_ctx); 2331 2332 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2333 deallocate_usb4_bandwidth(pipe_ctx->stream); 2334 2335 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2336 deallocate_mst_payload(pipe_ctx); 2337 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2338 dp_is_128b_132b_signal(pipe_ctx)) 2339 update_sst_payload(pipe_ctx, false); 2340 2341 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2342 struct ext_hdmi_settings settings = {0}; 2343 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2344 2345 unsigned short masked_chip_caps = link->chip_caps & 2346 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2347 //Need to inform that sink is going to use legacy HDMI mode. 2348 write_scdc_data( 2349 link->ddc, 2350 165000,//vbios only handles 165Mhz. 2351 false); 2352 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2353 /* DP159, Retimer settings */ 2354 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2355 write_i2c_retimer_setting(pipe_ctx, 2356 false, false, &settings); 2357 else 2358 write_i2c_default_retimer_setting(pipe_ctx, 2359 false, false); 2360 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2361 /* PI3EQX1204, Redriver settings */ 2362 write_i2c_redriver_setting(pipe_ctx, false); 2363 } 2364 } 2365 2366 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2367 !dp_is_128b_132b_signal(pipe_ctx)) { 2368 2369 /* In DP1.x SST mode, our encoder will go to TPS1 2370 * when link is on but stream is off. 2371 * Disabling link before stream will avoid exposing TPS1 pattern 2372 * during the disable sequence as it will confuse some receivers 2373 * state machine. 2374 * In DP2 or MST mode, our encoder will stay video active 2375 */ 2376 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2377 dc->hwss.disable_stream(pipe_ctx); 2378 } else { 2379 dc->hwss.disable_stream(pipe_ctx); 2380 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2381 } 2382 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2383 2384 if (pipe_ctx->stream->timing.flags.DSC) { 2385 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2386 link_set_dsc_enable(pipe_ctx, false); 2387 } 2388 if (dp_is_128b_132b_signal(pipe_ctx)) { 2389 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2390 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2391 } 2392 2393 if (vpg && vpg->funcs->vpg_powerdown) 2394 vpg->funcs->vpg_powerdown(vpg); 2395 2396 /* for psp not exist case */ 2397 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2398 /* reset internal save state to default since eDP is off */ 2399 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2400 /* since current psp not loaded, we need to reset it to default */ 2401 link->panel_mode = panel_mode; 2402 } 2403 } 2404 2405 void link_set_dpms_on( 2406 struct dc_state *state, 2407 struct pipe_ctx *pipe_ctx) 2408 { 2409 struct dc *dc = pipe_ctx->stream->ctx->dc; 2410 struct dc_stream_state *stream = pipe_ctx->stream; 2411 struct dc_link *link = stream->sink->link; 2412 enum dc_status status; 2413 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 2414 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2415 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2416 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2417 bool apply_edp_fast_boot_optimization = 2418 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2419 2420 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2421 2422 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2423 2424 if (dp_is_128b_132b_signal(pipe_ctx)) 2425 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2426 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2427 return; 2428 2429 if (pipe_ctx->stream->sink) { 2430 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2431 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2432 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2433 pipe_ctx->stream->sink->edid_caps.display_name, 2434 pipe_ctx->stream->signal, 2435 link->link_index, 2436 link->sink_count); 2437 } 2438 } 2439 2440 if (!dc->config.unify_link_enc_assignment) 2441 link_enc = link_enc_cfg_get_link_enc(link); 2442 ASSERT(link_enc); 2443 2444 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2445 && !dp_is_128b_132b_signal(pipe_ctx)) { 2446 if (link_enc) 2447 link_enc->funcs->setup( 2448 link_enc, 2449 pipe_ctx->stream->signal); 2450 } 2451 2452 pipe_ctx->stream->link->link_state_valid = true; 2453 2454 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2455 if (dp_is_128b_132b_signal(pipe_ctx)) 2456 otg_out_dest = OUT_MUX_HPO_DP; 2457 else 2458 otg_out_dest = OUT_MUX_DIO; 2459 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2460 } 2461 2462 link_hwss->setup_stream_attribute(pipe_ctx); 2463 2464 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2465 2466 // Enable VPG before building infoframe 2467 if (vpg && vpg->funcs->vpg_poweron) 2468 vpg->funcs->vpg_poweron(vpg); 2469 2470 resource_build_info_frame(pipe_ctx); 2471 dc->hwss.update_info_frame(pipe_ctx); 2472 2473 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2474 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2475 2476 /* Do not touch link on seamless boot optimization. */ 2477 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2478 pipe_ctx->stream->dpms_off = false; 2479 2480 /* Still enable stream features & audio on seamless boot for DP external displays */ 2481 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2482 enable_stream_features(pipe_ctx); 2483 dc->hwss.enable_audio_stream(pipe_ctx); 2484 } 2485 2486 update_psp_stream_config(pipe_ctx, false); 2487 return; 2488 } 2489 2490 /* eDP lit up by bios already, no need to enable again. */ 2491 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2492 apply_edp_fast_boot_optimization && 2493 !pipe_ctx->stream->timing.flags.DSC && 2494 !pipe_ctx->next_odm_pipe) { 2495 pipe_ctx->stream->dpms_off = false; 2496 update_psp_stream_config(pipe_ctx, false); 2497 2498 if (link->is_dds) { 2499 uint32_t post_oui_delay = 30; // 30ms 2500 2501 dpcd_set_source_specific_data(link); 2502 msleep(post_oui_delay); 2503 } 2504 2505 return; 2506 } 2507 2508 if (pipe_ctx->stream->dpms_off) 2509 return; 2510 2511 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2512 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2513 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2514 */ 2515 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2516 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2517 return; 2518 } 2519 2520 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2521 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2522 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2523 * will be automatically set at a later time when the video is enabled 2524 * (DP_VID_STREAM_EN = 1). 2525 */ 2526 if (pipe_ctx->stream->timing.flags.DSC) { 2527 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2528 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2529 link_set_dsc_enable(pipe_ctx, true); 2530 } 2531 2532 status = enable_link(state, pipe_ctx); 2533 2534 if (status != DC_OK) { 2535 DC_LOG_WARNING("enabling link %u failed: %d\n", 2536 pipe_ctx->stream->link->link_index, 2537 status); 2538 2539 /* Abort stream enable *unless* the failure was due to 2540 * DP link training - some DP monitors will recover and 2541 * show the stream anyway. But MST displays can't proceed 2542 * without link training. 2543 */ 2544 if (status != DC_FAIL_DP_LINK_TRAINING || 2545 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2546 if (false == stream->link->link_status.link_active) 2547 disable_link(stream->link, &pipe_ctx->link_res, 2548 pipe_ctx->stream->signal); 2549 BREAK_TO_DEBUGGER(); 2550 return; 2551 } 2552 } 2553 2554 /* turn off otg test pattern if enable */ 2555 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2556 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2557 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2558 COLOR_DEPTH_UNDEFINED); 2559 2560 /* This second call is needed to reconfigure the DIG 2561 * as a workaround for the incorrect value being applied 2562 * from transmitter control. 2563 */ 2564 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2565 dp_is_128b_132b_signal(pipe_ctx))) { 2566 2567 if (link_enc) 2568 link_enc->funcs->setup( 2569 link_enc, 2570 pipe_ctx->stream->signal); 2571 2572 } 2573 2574 dc->hwss.enable_stream(pipe_ctx); 2575 2576 /* Set DPS PPS SDP (AKA "info frames") */ 2577 if (pipe_ctx->stream->timing.flags.DSC) { 2578 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2579 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2580 dp_set_dsc_on_rx(pipe_ctx, true); 2581 link_set_dsc_pps_packet(pipe_ctx, true, true); 2582 } 2583 } 2584 2585 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2586 dp_set_hblank_reduction_on_rx(pipe_ctx); 2587 2588 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2589 allocate_usb4_bandwidth(pipe_ctx->stream); 2590 2591 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2592 allocate_mst_payload(pipe_ctx); 2593 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2594 dp_is_128b_132b_signal(pipe_ctx)) 2595 update_sst_payload(pipe_ctx, true); 2596 2597 /* Corruption was observed on systems with display mux when stream gets 2598 * enabled after the mux switch. Having a small delay between link 2599 * training and stream unblank resolves the corruption issue. 2600 * This is workaround. 2601 */ 2602 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2603 link->is_display_mux_present) 2604 msleep(20); 2605 2606 dc->hwss.unblank_stream(pipe_ctx, 2607 &pipe_ctx->stream->link->cur_link_settings); 2608 2609 if (stream->sink_patches.delay_ignore_msa > 0) 2610 msleep(stream->sink_patches.delay_ignore_msa); 2611 2612 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2613 enable_stream_features(pipe_ctx); 2614 update_psp_stream_config(pipe_ctx, false); 2615 2616 dc->hwss.enable_audio_stream(pipe_ctx); 2617 2618 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2619 set_avmute(pipe_ctx, false); 2620 } 2621 } 2622