1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #define DC_LOGGER \ 59 dc_logger 60 #define DC_LOGGER_INIT(logger) \ 61 struct dal_logger *dc_logger = logger 62 63 #define LINK_INFO(...) \ 64 DC_LOG_HW_HOTPLUG( \ 65 __VA_ARGS__) 66 67 #define RETIMER_REDRIVER_INFO(...) \ 68 DC_LOG_RETIMER_REDRIVER( \ 69 __VA_ARGS__) 70 #include "dc/dcn30/dcn30_vpg.h" 71 72 #define MAX_MTP_SLOT_COUNT 64 73 #define LINK_TRAINING_ATTEMPTS 4 74 #define PEAK_FACTOR_X1000 1006 75 76 void link_blank_all_dp_displays(struct dc *dc) 77 { 78 unsigned int i; 79 uint8_t dpcd_power_state = '\0'; 80 enum dc_status status = DC_ERROR_UNEXPECTED; 81 82 for (i = 0; i < dc->link_count; i++) { 83 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 84 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 85 continue; 86 87 /* DP 2.0 spec requires that we read LTTPR caps first */ 88 dp_retrieve_lttpr_cap(dc->links[i]); 89 /* if any of the displays are lit up turn them off */ 90 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 91 &dpcd_power_state, sizeof(dpcd_power_state)); 92 93 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 94 link_blank_dp_stream(dc->links[i], true); 95 } 96 97 } 98 99 void link_blank_all_edp_displays(struct dc *dc) 100 { 101 unsigned int i; 102 uint8_t dpcd_power_state = '\0'; 103 enum dc_status status = DC_ERROR_UNEXPECTED; 104 105 for (i = 0; i < dc->link_count; i++) { 106 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 107 (!dc->links[i]->edp_sink_present)) 108 continue; 109 110 /* if any of the displays are lit up turn them off */ 111 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 112 &dpcd_power_state, sizeof(dpcd_power_state)); 113 114 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 115 link_blank_dp_stream(dc->links[i], true); 116 } 117 } 118 119 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 120 { 121 unsigned int j; 122 struct dc *dc = link->ctx->dc; 123 enum signal_type signal = link->connector_signal; 124 125 if ((signal == SIGNAL_TYPE_EDP) || 126 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 127 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 128 link->link_enc->funcs->get_dig_frontend && 129 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 130 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 131 132 if (fe != ENGINE_ID_UNKNOWN) 133 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 134 if (fe == dc->res_pool->stream_enc[j]->id) { 135 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 136 dc->res_pool->stream_enc[j]); 137 break; 138 } 139 } 140 } 141 142 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 143 dpcd_write_rx_power_ctrl(link, false); 144 } 145 } 146 147 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 148 { 149 struct pipe_ctx *pipes[MAX_PIPES]; 150 struct dc_state *state = link->dc->current_state; 151 uint8_t count; 152 int i; 153 struct dc_stream_update stream_update; 154 bool dpms_off = true; 155 struct link_resource link_res = {0}; 156 157 memset(&stream_update, 0, sizeof(stream_update)); 158 stream_update.dpms_off = &dpms_off; 159 160 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 161 162 for (i = 0; i < count; i++) { 163 stream_update.stream = pipes[i]->stream; 164 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 165 pipes[i]->stream, &stream_update, 166 state); 167 } 168 169 /* link can be also enabled by vbios. In this case it is not recorded 170 * in pipe_ctx. Disable link phy here to make sure it is completely off 171 */ 172 dp_disable_link_phy(link, &link_res, link->connector_signal); 173 } 174 175 void link_resume(struct dc_link *link) 176 { 177 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 178 program_hpd_filter(link); 179 } 180 181 /* This function returns true if the pipe is used to feed video signal directly 182 * to the link. 183 */ 184 static bool is_master_pipe_for_link(const struct dc_link *link, 185 const struct pipe_ctx *pipe) 186 { 187 return resource_is_pipe_type(pipe, OTG_MASTER) && 188 pipe->stream->link == link; 189 } 190 191 /* 192 * This function finds all master pipes feeding to a given link with dpms set to 193 * on in given dc state. 194 */ 195 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 196 struct dc_state *state, 197 uint8_t *count, 198 struct pipe_ctx *pipes[MAX_PIPES]) 199 { 200 int i; 201 struct pipe_ctx *pipe = NULL; 202 203 *count = 0; 204 for (i = 0; i < MAX_PIPES; i++) { 205 pipe = &state->res_ctx.pipe_ctx[i]; 206 207 if (is_master_pipe_for_link(link, pipe) && 208 pipe->stream->dpms_off == false) { 209 pipes[(*count)++] = pipe; 210 } 211 } 212 } 213 214 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 215 enum engine_id eng_id, 216 struct ext_hdmi_settings *settings) 217 { 218 bool result = false; 219 int i = 0; 220 struct integrated_info *integrated_info = 221 pipe_ctx->stream->ctx->dc_bios->integrated_info; 222 223 if (integrated_info == NULL) 224 return false; 225 226 /* 227 * Get retimer settings from sbios for passing SI eye test for DCE11 228 * The setting values are varied based on board revision and port id 229 * Therefore the setting values of each ports is passed by sbios. 230 */ 231 232 // Check if current bios contains ext Hdmi settings 233 if (integrated_info->gpu_cap_info & 0x20) { 234 switch (eng_id) { 235 case ENGINE_ID_DIGA: 236 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 237 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 238 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 memmove(settings->reg_settings, 240 integrated_info->dp0_ext_hdmi_reg_settings, 241 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 242 memmove(settings->reg_settings_6g, 243 integrated_info->dp0_ext_hdmi_6g_reg_settings, 244 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 245 result = true; 246 break; 247 case ENGINE_ID_DIGB: 248 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 249 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 250 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 memmove(settings->reg_settings, 252 integrated_info->dp1_ext_hdmi_reg_settings, 253 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 254 memmove(settings->reg_settings_6g, 255 integrated_info->dp1_ext_hdmi_6g_reg_settings, 256 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 257 result = true; 258 break; 259 case ENGINE_ID_DIGC: 260 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 261 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 262 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 memmove(settings->reg_settings, 264 integrated_info->dp2_ext_hdmi_reg_settings, 265 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 266 memmove(settings->reg_settings_6g, 267 integrated_info->dp2_ext_hdmi_6g_reg_settings, 268 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 269 result = true; 270 break; 271 case ENGINE_ID_DIGD: 272 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 273 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 274 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 memmove(settings->reg_settings, 276 integrated_info->dp3_ext_hdmi_reg_settings, 277 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 278 memmove(settings->reg_settings_6g, 279 integrated_info->dp3_ext_hdmi_6g_reg_settings, 280 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 281 result = true; 282 break; 283 default: 284 break; 285 } 286 287 if (result == true) { 288 // Validate settings from bios integrated info table 289 if (settings->slv_addr == 0) 290 return false; 291 if (settings->reg_num > 9) 292 return false; 293 if (settings->reg_num_6g > 3) 294 return false; 295 296 for (i = 0; i < settings->reg_num; i++) { 297 if (settings->reg_settings[i].i2c_reg_index > 0x20) 298 return false; 299 } 300 301 for (i = 0; i < settings->reg_num_6g; i++) { 302 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 303 return false; 304 } 305 } 306 } 307 308 return result; 309 } 310 311 static bool write_i2c(struct pipe_ctx *pipe_ctx, 312 uint8_t address, uint8_t *buffer, uint32_t length) 313 { 314 struct i2c_command cmd = {0}; 315 struct i2c_payload payload = {0}; 316 317 memset(&payload, 0, sizeof(payload)); 318 memset(&cmd, 0, sizeof(cmd)); 319 320 cmd.number_of_payloads = 1; 321 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 322 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 323 324 payload.address = address; 325 payload.data = buffer; 326 payload.length = length; 327 payload.write = true; 328 cmd.payloads = &payload; 329 330 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 331 pipe_ctx->stream->link, &cmd)) 332 return true; 333 334 return false; 335 } 336 337 static void write_i2c_retimer_setting( 338 struct pipe_ctx *pipe_ctx, 339 bool is_vga_mode, 340 bool is_over_340mhz, 341 struct ext_hdmi_settings *settings) 342 { 343 uint8_t slave_address = (settings->slv_addr >> 1); 344 uint8_t buffer[2]; 345 const uint8_t apply_rx_tx_change = 0x4; 346 uint8_t offset = 0xA; 347 uint8_t value = 0; 348 int i = 0; 349 bool i2c_success = false; 350 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 351 352 memset(&buffer, 0, sizeof(buffer)); 353 354 /* Start Ext-Hdmi programming*/ 355 356 for (i = 0; i < settings->reg_num; i++) { 357 /* Apply 3G settings */ 358 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 359 360 buffer[0] = settings->reg_settings[i].i2c_reg_index; 361 buffer[1] = settings->reg_settings[i].i2c_reg_val; 362 i2c_success = write_i2c(pipe_ctx, slave_address, 363 buffer, sizeof(buffer)); 364 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 365 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 366 slave_address, buffer[0], buffer[1], i2c_success?1:0); 367 368 if (!i2c_success) 369 goto i2c_write_fail; 370 371 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 372 * needs to be set to 1 on every 0xA-0xC write. 373 */ 374 if (settings->reg_settings[i].i2c_reg_index == 0xA || 375 settings->reg_settings[i].i2c_reg_index == 0xB || 376 settings->reg_settings[i].i2c_reg_index == 0xC) { 377 378 /* Query current value from offset 0xA */ 379 if (settings->reg_settings[i].i2c_reg_index == 0xA) 380 value = settings->reg_settings[i].i2c_reg_val; 381 else { 382 i2c_success = 383 link_query_ddc_data( 384 pipe_ctx->stream->link->ddc, 385 slave_address, &offset, 1, &value, 1); 386 if (!i2c_success) 387 goto i2c_write_fail; 388 } 389 390 buffer[0] = offset; 391 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 392 buffer[1] = value | apply_rx_tx_change; 393 i2c_success = write_i2c(pipe_ctx, slave_address, 394 buffer, sizeof(buffer)); 395 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 396 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 397 slave_address, buffer[0], buffer[1], i2c_success?1:0); 398 if (!i2c_success) 399 goto i2c_write_fail; 400 } 401 } 402 } 403 404 /* Apply 3G settings */ 405 if (is_over_340mhz) { 406 for (i = 0; i < settings->reg_num_6g; i++) { 407 /* Apply 3G settings */ 408 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 409 410 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 411 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 412 i2c_success = write_i2c(pipe_ctx, slave_address, 413 buffer, sizeof(buffer)); 414 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 415 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 416 slave_address, buffer[0], buffer[1], i2c_success?1:0); 417 418 if (!i2c_success) 419 goto i2c_write_fail; 420 421 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 422 * needs to be set to 1 on every 0xA-0xC write. 423 */ 424 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 425 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 427 428 /* Query current value from offset 0xA */ 429 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 430 value = settings->reg_settings_6g[i].i2c_reg_val; 431 else { 432 i2c_success = 433 link_query_ddc_data( 434 pipe_ctx->stream->link->ddc, 435 slave_address, &offset, 1, &value, 1); 436 if (!i2c_success) 437 goto i2c_write_fail; 438 } 439 440 buffer[0] = offset; 441 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 442 buffer[1] = value | apply_rx_tx_change; 443 i2c_success = write_i2c(pipe_ctx, slave_address, 444 buffer, sizeof(buffer)); 445 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 446 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 447 slave_address, buffer[0], buffer[1], i2c_success?1:0); 448 if (!i2c_success) 449 goto i2c_write_fail; 450 } 451 } 452 } 453 } 454 455 if (is_vga_mode) { 456 /* Program additional settings if using 640x480 resolution */ 457 458 /* Write offset 0xFF to 0x01 */ 459 buffer[0] = 0xff; 460 buffer[1] = 0x01; 461 i2c_success = write_i2c(pipe_ctx, slave_address, 462 buffer, sizeof(buffer)); 463 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 464 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 465 slave_address, buffer[0], buffer[1], i2c_success?1:0); 466 if (!i2c_success) 467 goto i2c_write_fail; 468 469 /* Write offset 0x00 to 0x23 */ 470 buffer[0] = 0x00; 471 buffer[1] = 0x23; 472 i2c_success = write_i2c(pipe_ctx, slave_address, 473 buffer, sizeof(buffer)); 474 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 475 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 476 slave_address, buffer[0], buffer[1], i2c_success?1:0); 477 if (!i2c_success) 478 goto i2c_write_fail; 479 480 /* Write offset 0xff to 0x00 */ 481 buffer[0] = 0xff; 482 buffer[1] = 0x00; 483 i2c_success = write_i2c(pipe_ctx, slave_address, 484 buffer, sizeof(buffer)); 485 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 486 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 487 slave_address, buffer[0], buffer[1], i2c_success?1:0); 488 if (!i2c_success) 489 goto i2c_write_fail; 490 491 } 492 493 return; 494 495 i2c_write_fail: 496 DC_LOG_DEBUG("Set retimer failed"); 497 } 498 499 static void write_i2c_default_retimer_setting( 500 struct pipe_ctx *pipe_ctx, 501 bool is_vga_mode, 502 bool is_over_340mhz) 503 { 504 uint8_t slave_address = (0xBA >> 1); 505 uint8_t buffer[2]; 506 bool i2c_success = false; 507 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 508 509 memset(&buffer, 0, sizeof(buffer)); 510 511 /* Program Slave Address for tuning single integrity */ 512 /* Write offset 0x0A to 0x13 */ 513 buffer[0] = 0x0A; 514 buffer[1] = 0x13; 515 i2c_success = write_i2c(pipe_ctx, slave_address, 516 buffer, sizeof(buffer)); 517 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 518 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 519 slave_address, buffer[0], buffer[1], i2c_success?1:0); 520 if (!i2c_success) 521 goto i2c_write_fail; 522 523 /* Write offset 0x0A to 0x17 */ 524 buffer[0] = 0x0A; 525 buffer[1] = 0x17; 526 i2c_success = write_i2c(pipe_ctx, slave_address, 527 buffer, sizeof(buffer)); 528 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 529 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 530 slave_address, buffer[0], buffer[1], i2c_success?1:0); 531 if (!i2c_success) 532 goto i2c_write_fail; 533 534 /* Write offset 0x0B to 0xDA or 0xD8 */ 535 buffer[0] = 0x0B; 536 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 537 i2c_success = write_i2c(pipe_ctx, slave_address, 538 buffer, sizeof(buffer)); 539 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 540 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 541 slave_address, buffer[0], buffer[1], i2c_success?1:0); 542 if (!i2c_success) 543 goto i2c_write_fail; 544 545 /* Write offset 0x0A to 0x17 */ 546 buffer[0] = 0x0A; 547 buffer[1] = 0x17; 548 i2c_success = write_i2c(pipe_ctx, slave_address, 549 buffer, sizeof(buffer)); 550 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 551 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 552 slave_address, buffer[0], buffer[1], i2c_success?1:0); 553 if (!i2c_success) 554 goto i2c_write_fail; 555 556 /* Write offset 0x0C to 0x1D or 0x91 */ 557 buffer[0] = 0x0C; 558 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 559 i2c_success = write_i2c(pipe_ctx, slave_address, 560 buffer, sizeof(buffer)); 561 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 562 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 563 slave_address, buffer[0], buffer[1], i2c_success?1:0); 564 if (!i2c_success) 565 goto i2c_write_fail; 566 567 /* Write offset 0x0A to 0x17 */ 568 buffer[0] = 0x0A; 569 buffer[1] = 0x17; 570 i2c_success = write_i2c(pipe_ctx, slave_address, 571 buffer, sizeof(buffer)); 572 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 573 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 574 slave_address, buffer[0], buffer[1], i2c_success?1:0); 575 if (!i2c_success) 576 goto i2c_write_fail; 577 578 579 if (is_vga_mode) { 580 /* Program additional settings if using 640x480 resolution */ 581 582 /* Write offset 0xFF to 0x01 */ 583 buffer[0] = 0xff; 584 buffer[1] = 0x01; 585 i2c_success = write_i2c(pipe_ctx, slave_address, 586 buffer, sizeof(buffer)); 587 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 588 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 589 slave_address, buffer[0], buffer[1], i2c_success?1:0); 590 if (!i2c_success) 591 goto i2c_write_fail; 592 593 /* Write offset 0x00 to 0x23 */ 594 buffer[0] = 0x00; 595 buffer[1] = 0x23; 596 i2c_success = write_i2c(pipe_ctx, slave_address, 597 buffer, sizeof(buffer)); 598 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 599 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 600 slave_address, buffer[0], buffer[1], i2c_success?1:0); 601 if (!i2c_success) 602 goto i2c_write_fail; 603 604 /* Write offset 0xff to 0x00 */ 605 buffer[0] = 0xff; 606 buffer[1] = 0x00; 607 i2c_success = write_i2c(pipe_ctx, slave_address, 608 buffer, sizeof(buffer)); 609 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 610 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 611 slave_address, buffer[0], buffer[1], i2c_success?1:0); 612 if (!i2c_success) 613 goto i2c_write_fail; 614 } 615 616 return; 617 618 i2c_write_fail: 619 DC_LOG_DEBUG("Set default retimer failed"); 620 } 621 622 static void write_i2c_redriver_setting( 623 struct pipe_ctx *pipe_ctx, 624 bool is_over_340mhz) 625 { 626 uint8_t slave_address = (0xF0 >> 1); 627 uint8_t buffer[16]; 628 bool i2c_success = false; 629 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 630 631 memset(&buffer, 0, sizeof(buffer)); 632 633 // Program Slave Address for tuning single integrity 634 buffer[3] = 0x4E; 635 buffer[4] = 0x4E; 636 buffer[5] = 0x4E; 637 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 638 639 i2c_success = write_i2c(pipe_ctx, slave_address, 640 buffer, sizeof(buffer)); 641 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 642 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 643 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 644 i2c_success = %d\n", 645 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 646 647 if (!i2c_success) 648 DC_LOG_DEBUG("Set redriver failed"); 649 } 650 651 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 652 { 653 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 654 struct link_encoder *link_enc = NULL; 655 struct cp_psp_stream_config config = {0}; 656 enum dp_panel_mode panel_mode = 657 dp_get_panel_mode(pipe_ctx->stream->link); 658 659 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 660 return; 661 662 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 663 ASSERT(link_enc); 664 if (link_enc == NULL) 665 return; 666 667 /* otg instance */ 668 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 669 670 /* dig front end */ 671 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 672 673 /* stream encoder index */ 674 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 675 if (dp_is_128b_132b_signal(pipe_ctx)) 676 config.stream_enc_idx = 677 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 678 679 /* dig back end */ 680 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 681 682 /* link encoder index */ 683 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 684 if (dp_is_128b_132b_signal(pipe_ctx)) 685 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 686 687 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 688 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 689 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 690 else 691 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 692 693 694 /* phy index */ 695 config.phy_idx = resource_transmitter_to_phy_idx( 696 pipe_ctx->stream->link->dc, link_enc->transmitter); 697 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 698 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 699 config.phy_idx = 0; 700 701 /* stream properties */ 702 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 703 config.mst_enabled = (pipe_ctx->stream->signal == 704 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 705 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 706 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 707 1 : 0; 708 config.dpms_off = dpms_off; 709 710 /* dm stream context */ 711 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 712 713 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 714 } 715 716 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 717 { 718 struct dc *dc = pipe_ctx->stream->ctx->dc; 719 720 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 721 return; 722 723 dc->hwss.set_avmute(pipe_ctx, enable); 724 } 725 726 static void enable_mst_on_sink(struct dc_link *link, bool enable) 727 { 728 unsigned char mstmCntl; 729 730 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 731 if (enable) 732 mstmCntl |= DP_MST_EN; 733 else 734 mstmCntl &= (~DP_MST_EN); 735 736 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 737 } 738 739 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 740 struct dsc_optc_config *config) 741 { 742 uint32_t precision = 1 << 28; 743 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 744 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 745 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 746 DC_LOGGER_INIT(dsc->ctx->logger); 747 748 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 749 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 750 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 751 */ 752 ll_bytes_per_pix_fraq *= 10000000; 753 ll_bytes_per_pix_fraq /= precision; 754 755 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 756 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 757 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 758 DC_LOG_DSC("\tslice_width %d", config->slice_width); 759 } 760 761 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 762 { 763 struct dc *dc = pipe_ctx->stream->ctx->dc; 764 struct dc_stream_state *stream = pipe_ctx->stream; 765 bool result = false; 766 767 if (dc_is_virtual_signal(stream->signal)) 768 result = true; 769 else 770 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 771 return result; 772 } 773 774 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 775 * i.e. after dp_enable_dsc_on_rx() had been called 776 */ 777 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 778 { 779 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 780 struct dc_stream_state *stream = pipe_ctx->stream; 781 struct pipe_ctx *odm_pipe; 782 int opp_cnt = 1; 783 DC_LOGGER_INIT(dsc->ctx->logger); 784 785 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 786 opp_cnt++; 787 788 if (enable) { 789 struct dsc_config dsc_cfg; 790 struct dsc_optc_config dsc_optc_cfg; 791 enum optc_dsc_mode optc_dsc_mode; 792 793 /* Enable DSC hw block */ 794 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 795 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 796 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 797 dsc_cfg.color_depth = stream->timing.display_color_depth; 798 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 799 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 800 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 801 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 802 803 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 804 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 805 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 806 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 807 808 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 809 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 810 } 811 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 812 dsc_cfg.pic_width *= opp_cnt; 813 814 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 815 816 /* Enable DSC in encoder */ 817 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 818 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 819 dsc_optc_config_log(dsc, &dsc_optc_cfg); 820 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 821 optc_dsc_mode, 822 dsc_optc_cfg.bytes_per_pixel, 823 dsc_optc_cfg.slice_width); 824 825 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 826 } 827 828 /* Enable DSC in OPTC */ 829 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 830 dsc_optc_config_log(dsc, &dsc_optc_cfg); 831 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 832 optc_dsc_mode, 833 dsc_optc_cfg.bytes_per_pixel, 834 dsc_optc_cfg.slice_width); 835 } else { 836 /* disable DSC in OPTC */ 837 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 838 pipe_ctx->stream_res.tg, 839 OPTC_DSC_DISABLED, 0, 0); 840 841 /* disable DSC in stream encoder */ 842 if (dc_is_dp_signal(stream->signal)) { 843 if (dp_is_128b_132b_signal(pipe_ctx)) 844 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 845 pipe_ctx->stream_res.hpo_dp_stream_enc, 846 false, 847 NULL, 848 true); 849 else { 850 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 851 pipe_ctx->stream_res.stream_enc, 852 OPTC_DSC_DISABLED, 0, 0); 853 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 854 pipe_ctx->stream_res.stream_enc, false, NULL, true); 855 } 856 } 857 858 /* disable DSC block */ 859 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 860 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 861 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 862 } 863 } 864 865 /* 866 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 867 * hence PPS info packet update need to use frame update instead of immediate update. 868 * Added parameter immediate_update for this purpose. 869 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 870 * which is the only place where a "false" would be passed in for param immediate_update. 871 * 872 * immediate_update is only applicable when DSC is enabled. 873 */ 874 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 875 { 876 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 877 struct dc_stream_state *stream = pipe_ctx->stream; 878 DC_LOGGER_INIT(dsc->ctx->logger); 879 880 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 881 return false; 882 883 if (enable) { 884 struct dsc_config dsc_cfg; 885 uint8_t dsc_packed_pps[128]; 886 887 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 888 memset(dsc_packed_pps, 0, 128); 889 890 /* Enable DSC hw block */ 891 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 892 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 893 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 894 dsc_cfg.color_depth = stream->timing.display_color_depth; 895 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 896 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 897 898 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 899 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 900 if (dc_is_dp_signal(stream->signal)) { 901 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 902 if (dp_is_128b_132b_signal(pipe_ctx)) 903 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 904 pipe_ctx->stream_res.hpo_dp_stream_enc, 905 true, 906 &dsc_packed_pps[0], 907 immediate_update); 908 else 909 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 910 pipe_ctx->stream_res.stream_enc, 911 true, 912 &dsc_packed_pps[0], 913 immediate_update); 914 } 915 } else { 916 /* disable DSC PPS in stream encoder */ 917 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 918 if (dc_is_dp_signal(stream->signal)) { 919 if (dp_is_128b_132b_signal(pipe_ctx)) 920 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 921 pipe_ctx->stream_res.hpo_dp_stream_enc, 922 false, 923 NULL, 924 true); 925 else 926 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 927 pipe_ctx->stream_res.stream_enc, false, NULL, true); 928 } 929 } 930 931 return true; 932 } 933 934 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 935 { 936 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 937 bool result = false; 938 939 if (!pipe_ctx->stream->timing.flags.DSC) 940 goto out; 941 if (!dsc) 942 goto out; 943 944 if (enable) { 945 { 946 link_set_dsc_on_stream(pipe_ctx, true); 947 result = true; 948 } 949 } else { 950 dp_set_dsc_on_rx(pipe_ctx, false); 951 link_set_dsc_on_stream(pipe_ctx, false); 952 result = true; 953 } 954 out: 955 return result; 956 } 957 958 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 959 { 960 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 961 962 if (!pipe_ctx->stream->timing.flags.DSC) 963 return false; 964 if (!dsc) 965 return false; 966 967 link_set_dsc_on_stream(pipe_ctx, true); 968 link_set_dsc_pps_packet(pipe_ctx, true, false); 969 return true; 970 } 971 972 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 973 { 974 struct dc_stream_state *stream = pipe_ctx->stream; 975 976 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 977 struct dc_link *link = stream->link; 978 union down_spread_ctrl old_downspread; 979 union down_spread_ctrl new_downspread; 980 981 memset(&old_downspread, 0, sizeof(old_downspread)); 982 983 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 984 &old_downspread.raw, sizeof(old_downspread)); 985 986 new_downspread.raw = old_downspread.raw; 987 988 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 989 (stream->ignore_msa_timing_param) ? 1 : 0; 990 991 if (new_downspread.raw != old_downspread.raw) { 992 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 993 &new_downspread.raw, sizeof(new_downspread)); 994 } 995 996 } else { 997 dm_helpers_mst_enable_stream_features(stream); 998 } 999 } 1000 1001 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1002 { 1003 const uint32_t VCP_Y_PRECISION = 1000; 1004 uint64_t vcp_x, vcp_y; 1005 DC_LOGGER_INIT(link->ctx->logger); 1006 1007 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1008 avg_time_slots_per_mtp = dc_fixpt_add( 1009 avg_time_slots_per_mtp, 1010 dc_fixpt_from_fraction( 1011 1, 1012 2*VCP_Y_PRECISION)); 1013 1014 vcp_x = dc_fixpt_floor( 1015 avg_time_slots_per_mtp); 1016 vcp_y = dc_fixpt_floor( 1017 dc_fixpt_mul_int( 1018 dc_fixpt_sub_int( 1019 avg_time_slots_per_mtp, 1020 dc_fixpt_floor( 1021 avg_time_slots_per_mtp)), 1022 VCP_Y_PRECISION)); 1023 1024 1025 if (link->type == dc_connection_mst_branch) 1026 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1027 "X: %llu " 1028 "Y: %llu/%d", 1029 vcp_x, 1030 vcp_y, 1031 VCP_Y_PRECISION); 1032 else 1033 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1034 "X: %llu " 1035 "Y: %llu/%d", 1036 vcp_x, 1037 vcp_y, 1038 VCP_Y_PRECISION); 1039 } 1040 1041 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1042 { 1043 struct fixed31_32 mbytes_per_sec; 1044 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1045 &stream->link->cur_link_settings); 1046 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1047 1048 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1049 1050 return dc_fixpt_div_int(mbytes_per_sec, 54); 1051 } 1052 1053 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1054 { 1055 struct fixed31_32 peak_kbps; 1056 uint32_t numerator = 0; 1057 uint32_t denominator = 1; 1058 1059 /* 1060 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 1061 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1062 * common multiplier to render an integer PBN for all link rate/lane 1063 * counts combinations 1064 * calculate 1065 * peak_kbps *= (1006/1000) 1066 * peak_kbps *= (64/54) 1067 * peak_kbps *= 8 convert to bytes 1068 */ 1069 1070 numerator = 64 * PEAK_FACTOR_X1000; 1071 denominator = 54 * 8 * 1000 * 1000; 1072 kbps *= numerator; 1073 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1074 1075 return peak_kbps; 1076 } 1077 1078 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1079 { 1080 uint64_t kbps; 1081 enum dc_link_encoding_format link_encoding; 1082 1083 if (dp_is_128b_132b_signal(pipe_ctx)) 1084 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1085 else 1086 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1087 1088 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1089 return get_pbn_from_bw_in_kbps(kbps); 1090 } 1091 1092 1093 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1094 static void get_lane_status( 1095 struct dc_link *link, 1096 uint32_t lane_count, 1097 union lane_status *status, 1098 union lane_align_status_updated *status_updated) 1099 { 1100 unsigned int lane; 1101 uint8_t dpcd_buf[3] = {0}; 1102 1103 if (status == NULL || status_updated == NULL) { 1104 return; 1105 } 1106 1107 core_link_read_dpcd( 1108 link, 1109 DP_LANE0_1_STATUS, 1110 dpcd_buf, 1111 sizeof(dpcd_buf)); 1112 1113 for (lane = 0; lane < lane_count; lane++) { 1114 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1115 } 1116 1117 status_updated->raw = dpcd_buf[2]; 1118 } 1119 1120 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1121 { 1122 /* 1123 * wait for ACT handled 1124 */ 1125 int i; 1126 const int act_retries = 30; 1127 enum act_return_status result = ACT_FAILED; 1128 union payload_table_update_status update_status = {0}; 1129 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1130 union lane_align_status_updated lane_status_updated; 1131 DC_LOGGER_INIT(link->ctx->logger); 1132 1133 if (link->aux_access_disabled) 1134 return true; 1135 for (i = 0; i < act_retries; i++) { 1136 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1137 1138 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1139 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1140 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1141 !dp_is_interlane_aligned(lane_status_updated)) { 1142 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1143 "polling for ACT handled."); 1144 result = ACT_LINK_LOST; 1145 break; 1146 } 1147 core_link_read_dpcd( 1148 link, 1149 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1150 &update_status.raw, 1151 1); 1152 1153 if (update_status.bits.ACT_HANDLED == 1) { 1154 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1155 result = ACT_SUCCESS; 1156 break; 1157 } 1158 1159 fsleep(5000); 1160 } 1161 1162 if (result == ACT_FAILED) { 1163 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1164 "continue on. Something is wrong with the branch."); 1165 } 1166 1167 return (result == ACT_SUCCESS); 1168 } 1169 1170 static void update_mst_stream_alloc_table( 1171 struct dc_link *link, 1172 struct stream_encoder *stream_enc, 1173 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1174 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1175 { 1176 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1177 struct link_mst_stream_allocation *dc_alloc; 1178 1179 int i; 1180 int j; 1181 1182 /* if DRM proposed_table has more than one new payload */ 1183 ASSERT(proposed_table->stream_count - 1184 link->mst_stream_alloc_table.stream_count < 2); 1185 1186 /* copy proposed_table to link, add stream encoder */ 1187 for (i = 0; i < proposed_table->stream_count; i++) { 1188 1189 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1190 dc_alloc = 1191 &link->mst_stream_alloc_table.stream_allocations[j]; 1192 1193 if (dc_alloc->vcp_id == 1194 proposed_table->stream_allocations[i].vcp_id) { 1195 1196 work_table[i] = *dc_alloc; 1197 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1198 break; /* exit j loop */ 1199 } 1200 } 1201 1202 /* new vcp_id */ 1203 if (j == link->mst_stream_alloc_table.stream_count) { 1204 work_table[i].vcp_id = 1205 proposed_table->stream_allocations[i].vcp_id; 1206 work_table[i].slot_count = 1207 proposed_table->stream_allocations[i].slot_count; 1208 work_table[i].stream_enc = stream_enc; 1209 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1210 } 1211 } 1212 1213 /* update link->mst_stream_alloc_table with work_table */ 1214 link->mst_stream_alloc_table.stream_count = 1215 proposed_table->stream_count; 1216 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1217 link->mst_stream_alloc_table.stream_allocations[i] = 1218 work_table[i]; 1219 } 1220 1221 static void remove_stream_from_alloc_table( 1222 struct dc_link *link, 1223 struct stream_encoder *dio_stream_enc, 1224 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1225 { 1226 int i = 0; 1227 struct link_mst_stream_allocation_table *table = 1228 &link->mst_stream_alloc_table; 1229 1230 if (hpo_dp_stream_enc) { 1231 for (; i < table->stream_count; i++) 1232 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1233 break; 1234 } else { 1235 for (; i < table->stream_count; i++) 1236 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1237 break; 1238 } 1239 1240 if (i < table->stream_count) { 1241 i++; 1242 for (; i < table->stream_count; i++) 1243 table->stream_allocations[i-1] = table->stream_allocations[i]; 1244 memset(&table->stream_allocations[table->stream_count-1], 0, 1245 sizeof(struct link_mst_stream_allocation)); 1246 table->stream_count--; 1247 } 1248 } 1249 1250 static enum dc_status deallocate_mst_payload_with_temp_drm_wa( 1251 struct pipe_ctx *pipe_ctx) 1252 { 1253 struct dc_stream_state *stream = pipe_ctx->stream; 1254 struct dc_link *link = stream->link; 1255 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1256 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1257 int i; 1258 bool mst_mode = (link->type == dc_connection_mst_branch); 1259 /* adjust for drm changes*/ 1260 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1261 const struct dc_link_settings empty_link_settings = {0}; 1262 DC_LOGGER_INIT(link->ctx->logger); 1263 1264 if (link_hwss->ext.set_throttled_vcp_size) 1265 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1266 if (link_hwss->ext.set_hblank_min_symbol_width) 1267 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1268 &empty_link_settings, 1269 avg_time_slots_per_mtp); 1270 1271 if (dm_helpers_dp_mst_write_payload_allocation_table( 1272 stream->ctx, 1273 stream, 1274 &proposed_table, 1275 false)) 1276 update_mst_stream_alloc_table( 1277 link, 1278 pipe_ctx->stream_res.stream_enc, 1279 pipe_ctx->stream_res.hpo_dp_stream_enc, 1280 &proposed_table); 1281 else 1282 DC_LOG_WARNING("Failed to update" 1283 "MST allocation table for" 1284 "pipe idx:%d\n", 1285 pipe_ctx->pipe_idx); 1286 1287 DC_LOG_MST("%s" 1288 "stream_count: %d: ", 1289 __func__, 1290 link->mst_stream_alloc_table.stream_count); 1291 1292 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1293 DC_LOG_MST("stream_enc[%d]: %p " 1294 "stream[%d].hpo_dp_stream_enc: %p " 1295 "stream[%d].vcp_id: %d " 1296 "stream[%d].slot_count: %d\n", 1297 i, 1298 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1299 i, 1300 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1301 i, 1302 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1303 i, 1304 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1305 } 1306 1307 if (link_hwss->ext.update_stream_allocation_table == NULL || 1308 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1309 DC_LOG_DEBUG("Unknown encoding format\n"); 1310 return DC_ERROR_UNEXPECTED; 1311 } 1312 1313 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1314 &link->mst_stream_alloc_table); 1315 1316 if (mst_mode) { 1317 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1318 stream->ctx, 1319 stream); 1320 } 1321 1322 dm_helpers_dp_mst_send_payload_allocation( 1323 stream->ctx, 1324 stream, 1325 false); 1326 1327 return DC_OK; 1328 } 1329 1330 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1331 { 1332 struct dc_stream_state *stream = pipe_ctx->stream; 1333 struct dc_link *link = stream->link; 1334 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1335 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1336 int i; 1337 bool mst_mode = (link->type == dc_connection_mst_branch); 1338 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1339 const struct dc_link_settings empty_link_settings = {0}; 1340 DC_LOGGER_INIT(link->ctx->logger); 1341 1342 if (link->dc->debug.temp_mst_deallocation_sequence) 1343 return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); 1344 1345 /* deallocate_mst_payload is called before disable link. When mode or 1346 * disable/enable monitor, new stream is created which is not in link 1347 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1348 * should not done. For new mode set, map_resources will get engine 1349 * for new stream, so stream_enc->id should be validated until here. 1350 */ 1351 1352 /* slot X.Y */ 1353 if (link_hwss->ext.set_throttled_vcp_size) 1354 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1355 if (link_hwss->ext.set_hblank_min_symbol_width) 1356 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1357 &empty_link_settings, 1358 avg_time_slots_per_mtp); 1359 1360 if (mst_mode) { 1361 /* when link is in mst mode, reply on mst manager to remove 1362 * payload 1363 */ 1364 if (dm_helpers_dp_mst_write_payload_allocation_table( 1365 stream->ctx, 1366 stream, 1367 &proposed_table, 1368 false)) 1369 update_mst_stream_alloc_table( 1370 link, 1371 pipe_ctx->stream_res.stream_enc, 1372 pipe_ctx->stream_res.hpo_dp_stream_enc, 1373 &proposed_table); 1374 else 1375 DC_LOG_WARNING("Failed to update" 1376 "MST allocation table for" 1377 "pipe idx:%d\n", 1378 pipe_ctx->pipe_idx); 1379 } else { 1380 /* when link is no longer in mst mode (mst hub unplugged), 1381 * remove payload with default dc logic 1382 */ 1383 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1384 pipe_ctx->stream_res.hpo_dp_stream_enc); 1385 } 1386 1387 DC_LOG_MST("%s" 1388 "stream_count: %d: ", 1389 __func__, 1390 link->mst_stream_alloc_table.stream_count); 1391 1392 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1393 DC_LOG_MST("stream_enc[%d]: %p " 1394 "stream[%d].hpo_dp_stream_enc: %p " 1395 "stream[%d].vcp_id: %d " 1396 "stream[%d].slot_count: %d\n", 1397 i, 1398 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1399 i, 1400 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1401 i, 1402 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1403 i, 1404 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1405 } 1406 1407 /* update mst stream allocation table hardware state */ 1408 if (link_hwss->ext.update_stream_allocation_table == NULL || 1409 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1410 DC_LOG_DEBUG("Unknown encoding format\n"); 1411 return DC_ERROR_UNEXPECTED; 1412 } 1413 1414 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1415 &link->mst_stream_alloc_table); 1416 1417 if (mst_mode) { 1418 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1419 stream->ctx, 1420 stream); 1421 1422 dm_helpers_dp_mst_send_payload_allocation( 1423 stream->ctx, 1424 stream, 1425 false); 1426 } 1427 1428 return DC_OK; 1429 } 1430 1431 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1432 * because stream_encoder is not exposed to dm 1433 */ 1434 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1435 { 1436 struct dc_stream_state *stream = pipe_ctx->stream; 1437 struct dc_link *link = stream->link; 1438 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1439 struct fixed31_32 avg_time_slots_per_mtp; 1440 struct fixed31_32 pbn; 1441 struct fixed31_32 pbn_per_slot; 1442 int i; 1443 enum act_return_status ret; 1444 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1445 DC_LOGGER_INIT(link->ctx->logger); 1446 1447 /* enable_link_dp_mst already check link->enabled_stream_count 1448 * and stream is in link->stream[]. This is called during set mode, 1449 * stream_enc is available. 1450 */ 1451 1452 /* get calculate VC payload for stream: stream_alloc */ 1453 if (dm_helpers_dp_mst_write_payload_allocation_table( 1454 stream->ctx, 1455 stream, 1456 &proposed_table, 1457 true)) 1458 update_mst_stream_alloc_table( 1459 link, 1460 pipe_ctx->stream_res.stream_enc, 1461 pipe_ctx->stream_res.hpo_dp_stream_enc, 1462 &proposed_table); 1463 else 1464 DC_LOG_WARNING("Failed to update" 1465 "MST allocation table for" 1466 "pipe idx:%d\n", 1467 pipe_ctx->pipe_idx); 1468 1469 DC_LOG_MST("%s " 1470 "stream_count: %d: \n ", 1471 __func__, 1472 link->mst_stream_alloc_table.stream_count); 1473 1474 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1475 DC_LOG_MST("stream_enc[%d]: %p " 1476 "stream[%d].hpo_dp_stream_enc: %p " 1477 "stream[%d].vcp_id: %d " 1478 "stream[%d].slot_count: %d\n", 1479 i, 1480 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1481 i, 1482 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1483 i, 1484 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1485 i, 1486 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1487 } 1488 1489 ASSERT(proposed_table.stream_count > 0); 1490 1491 /* program DP source TX for payload */ 1492 if (link_hwss->ext.update_stream_allocation_table == NULL || 1493 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1494 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1495 return DC_ERROR_UNEXPECTED; 1496 } 1497 1498 link_hwss->ext.update_stream_allocation_table(link, 1499 &pipe_ctx->link_res, 1500 &link->mst_stream_alloc_table); 1501 1502 /* send down message */ 1503 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1504 stream->ctx, 1505 stream); 1506 1507 if (ret != ACT_LINK_LOST) { 1508 dm_helpers_dp_mst_send_payload_allocation( 1509 stream->ctx, 1510 stream, 1511 true); 1512 } 1513 1514 /* slot X.Y for only current stream */ 1515 pbn_per_slot = get_pbn_per_slot(stream); 1516 if (pbn_per_slot.value == 0) { 1517 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1518 return DC_UNSUPPORTED_VALUE; 1519 } 1520 pbn = get_pbn_from_timing(pipe_ctx); 1521 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1522 1523 log_vcp_x_y(link, avg_time_slots_per_mtp); 1524 1525 if (link_hwss->ext.set_throttled_vcp_size) 1526 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1527 if (link_hwss->ext.set_hblank_min_symbol_width) 1528 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1529 &link->cur_link_settings, 1530 avg_time_slots_per_mtp); 1531 1532 return DC_OK; 1533 } 1534 1535 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1536 const struct dc_stream_state *stream, 1537 const struct dc_link *link) 1538 { 1539 struct fixed31_32 link_bw_effective = 1540 dc_fixpt_from_int( 1541 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1542 struct fixed31_32 timeslot_bw_effective = 1543 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1544 struct fixed31_32 timing_bw = 1545 dc_fixpt_from_int( 1546 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1547 dc_link_get_highest_encoding_format(link))); 1548 struct fixed31_32 avg_time_slots_per_mtp = 1549 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1550 1551 return avg_time_slots_per_mtp; 1552 } 1553 1554 1555 static bool write_128b_132b_sst_payload_allocation_table( 1556 const struct dc_stream_state *stream, 1557 struct dc_link *link, 1558 struct link_mst_stream_allocation_table *proposed_table, 1559 bool allocate) 1560 { 1561 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1562 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1563 bool result = false; 1564 uint8_t req_slot_count = 0; 1565 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1566 union payload_table_update_status update_status = { 0 }; 1567 const uint32_t max_retries = 30; 1568 uint32_t retries = 0; 1569 DC_LOGGER_INIT(link->ctx->logger); 1570 1571 if (allocate) { 1572 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1573 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1574 /// Validation should filter out modes that exceed link BW 1575 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1576 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1577 return false; 1578 } else { 1579 /// Leave req_slot_count = 0 if allocate is false. 1580 } 1581 1582 proposed_table->stream_count = 1; /// Always 1 stream for SST 1583 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1584 proposed_table->stream_allocations[0].vcp_id = vc_id; 1585 1586 if (link->aux_access_disabled) 1587 return true; 1588 1589 /// Write DPCD 2C0 = 1 to start updating 1590 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1591 core_link_write_dpcd( 1592 link, 1593 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1594 &update_status.raw, 1595 1); 1596 1597 /// Program the changes in DPCD 1C0 - 1C2 1598 ASSERT(vc_id == 1); 1599 core_link_write_dpcd( 1600 link, 1601 DP_PAYLOAD_ALLOCATE_SET, 1602 &vc_id, 1603 1); 1604 1605 ASSERT(start_time_slot == 0); 1606 core_link_write_dpcd( 1607 link, 1608 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1609 &start_time_slot, 1610 1); 1611 1612 core_link_write_dpcd( 1613 link, 1614 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1615 &req_slot_count, 1616 1); 1617 1618 /// Poll till DPCD 2C0 read 1 1619 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1620 1621 while (retries < max_retries) { 1622 if (core_link_read_dpcd( 1623 link, 1624 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1625 &update_status.raw, 1626 1) == DC_OK) { 1627 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1628 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1629 result = true; 1630 break; 1631 } 1632 } else { 1633 union dpcd_rev dpcdRev; 1634 1635 if (core_link_read_dpcd( 1636 link, 1637 DP_DPCD_REV, 1638 &dpcdRev.raw, 1639 1) != DC_OK) { 1640 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1641 "of sink while polling payload table " 1642 "updated status bit."); 1643 break; 1644 } 1645 } 1646 retries++; 1647 fsleep(5000); 1648 } 1649 1650 if (!result && retries == max_retries) { 1651 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1652 "continue on. Something is wrong with the branch."); 1653 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1654 } 1655 1656 return result; 1657 } 1658 1659 /* 1660 * Payload allocation/deallocation for SST introduced in DP2.0 1661 */ 1662 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1663 bool allocate) 1664 { 1665 struct dc_stream_state *stream = pipe_ctx->stream; 1666 struct dc_link *link = stream->link; 1667 struct link_mst_stream_allocation_table proposed_table = {0}; 1668 struct fixed31_32 avg_time_slots_per_mtp; 1669 const struct dc_link_settings empty_link_settings = {0}; 1670 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1671 DC_LOGGER_INIT(link->ctx->logger); 1672 1673 /* slot X.Y for SST payload deallocate */ 1674 if (!allocate) { 1675 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1676 1677 log_vcp_x_y(link, avg_time_slots_per_mtp); 1678 1679 if (link_hwss->ext.set_throttled_vcp_size) 1680 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1681 avg_time_slots_per_mtp); 1682 if (link_hwss->ext.set_hblank_min_symbol_width) 1683 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1684 &empty_link_settings, 1685 avg_time_slots_per_mtp); 1686 } 1687 1688 /* calculate VC payload and update branch with new payload allocation table*/ 1689 if (!write_128b_132b_sst_payload_allocation_table( 1690 stream, 1691 link, 1692 &proposed_table, 1693 allocate)) { 1694 DC_LOG_ERROR("SST Update Payload: Failed to update " 1695 "allocation table for " 1696 "pipe idx: %d\n", 1697 pipe_ctx->pipe_idx); 1698 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1699 } 1700 1701 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1702 1703 ASSERT(proposed_table.stream_count == 1); 1704 1705 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1706 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1707 "vcp_id: %d " 1708 "slot_count: %d\n", 1709 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1710 proposed_table.stream_allocations[0].vcp_id, 1711 proposed_table.stream_allocations[0].slot_count); 1712 1713 /* program DP source TX for payload */ 1714 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1715 &proposed_table); 1716 1717 /* poll for ACT handled */ 1718 if (!poll_for_allocation_change_trigger(link)) { 1719 // Failures will result in blackscreen and errors logged 1720 BREAK_TO_DEBUGGER(); 1721 } 1722 1723 /* slot X.Y for SST payload allocate */ 1724 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1725 DP_128b_132b_ENCODING) { 1726 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1727 1728 log_vcp_x_y(link, avg_time_slots_per_mtp); 1729 1730 if (link_hwss->ext.set_throttled_vcp_size) 1731 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1732 avg_time_slots_per_mtp); 1733 if (link_hwss->ext.set_hblank_min_symbol_width) 1734 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1735 &link->cur_link_settings, 1736 avg_time_slots_per_mtp); 1737 } 1738 1739 /* Always return DC_OK. 1740 * If part of sequence fails, log failure(s) and show blackscreen 1741 */ 1742 return DC_OK; 1743 } 1744 1745 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1746 { 1747 struct dc_stream_state *stream = pipe_ctx->stream; 1748 struct dc_link *link = stream->link; 1749 struct fixed31_32 avg_time_slots_per_mtp; 1750 struct fixed31_32 pbn; 1751 struct fixed31_32 pbn_per_slot; 1752 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1753 uint8_t i; 1754 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1755 DC_LOGGER_INIT(link->ctx->logger); 1756 1757 /* decrease throttled vcp size */ 1758 pbn_per_slot = get_pbn_per_slot(stream); 1759 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1760 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1761 1762 if (link_hwss->ext.set_throttled_vcp_size) 1763 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1764 if (link_hwss->ext.set_hblank_min_symbol_width) 1765 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1766 &link->cur_link_settings, 1767 avg_time_slots_per_mtp); 1768 1769 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1770 dm_helpers_dp_mst_send_payload_allocation( 1771 stream->ctx, 1772 stream, 1773 true); 1774 1775 /* notify immediate branch device table update */ 1776 if (dm_helpers_dp_mst_write_payload_allocation_table( 1777 stream->ctx, 1778 stream, 1779 &proposed_table, 1780 true)) { 1781 /* update mst stream allocation table software state */ 1782 update_mst_stream_alloc_table( 1783 link, 1784 pipe_ctx->stream_res.stream_enc, 1785 pipe_ctx->stream_res.hpo_dp_stream_enc, 1786 &proposed_table); 1787 } else { 1788 DC_LOG_WARNING("Failed to update" 1789 "MST allocation table for" 1790 "pipe idx:%d\n", 1791 pipe_ctx->pipe_idx); 1792 } 1793 1794 DC_LOG_MST("%s " 1795 "stream_count: %d: \n ", 1796 __func__, 1797 link->mst_stream_alloc_table.stream_count); 1798 1799 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1800 DC_LOG_MST("stream_enc[%d]: %p " 1801 "stream[%d].hpo_dp_stream_enc: %p " 1802 "stream[%d].vcp_id: %d " 1803 "stream[%d].slot_count: %d\n", 1804 i, 1805 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1806 i, 1807 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1808 i, 1809 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1810 i, 1811 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1812 } 1813 1814 ASSERT(proposed_table.stream_count > 0); 1815 1816 /* update mst stream allocation table hardware state */ 1817 if (link_hwss->ext.update_stream_allocation_table == NULL || 1818 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1819 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1820 return DC_ERROR_UNEXPECTED; 1821 } 1822 1823 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1824 &link->mst_stream_alloc_table); 1825 1826 /* poll for immediate branch device ACT handled */ 1827 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1828 stream->ctx, 1829 stream); 1830 1831 return DC_OK; 1832 } 1833 1834 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1835 { 1836 struct dc_stream_state *stream = pipe_ctx->stream; 1837 struct dc_link *link = stream->link; 1838 struct fixed31_32 avg_time_slots_per_mtp; 1839 struct fixed31_32 pbn; 1840 struct fixed31_32 pbn_per_slot; 1841 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1842 uint8_t i; 1843 enum act_return_status ret; 1844 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1845 DC_LOGGER_INIT(link->ctx->logger); 1846 1847 /* notify immediate branch device table update */ 1848 if (dm_helpers_dp_mst_write_payload_allocation_table( 1849 stream->ctx, 1850 stream, 1851 &proposed_table, 1852 true)) { 1853 /* update mst stream allocation table software state */ 1854 update_mst_stream_alloc_table( 1855 link, 1856 pipe_ctx->stream_res.stream_enc, 1857 pipe_ctx->stream_res.hpo_dp_stream_enc, 1858 &proposed_table); 1859 } 1860 1861 DC_LOG_MST("%s " 1862 "stream_count: %d: \n ", 1863 __func__, 1864 link->mst_stream_alloc_table.stream_count); 1865 1866 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1867 DC_LOG_MST("stream_enc[%d]: %p " 1868 "stream[%d].hpo_dp_stream_enc: %p " 1869 "stream[%d].vcp_id: %d " 1870 "stream[%d].slot_count: %d\n", 1871 i, 1872 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1873 i, 1874 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1875 i, 1876 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1877 i, 1878 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1879 } 1880 1881 ASSERT(proposed_table.stream_count > 0); 1882 1883 /* update mst stream allocation table hardware state */ 1884 if (link_hwss->ext.update_stream_allocation_table == NULL || 1885 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1886 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1887 return DC_ERROR_UNEXPECTED; 1888 } 1889 1890 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1891 &link->mst_stream_alloc_table); 1892 1893 /* poll for immediate branch device ACT handled */ 1894 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1895 stream->ctx, 1896 stream); 1897 1898 if (ret != ACT_LINK_LOST) { 1899 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1900 dm_helpers_dp_mst_send_payload_allocation( 1901 stream->ctx, 1902 stream, 1903 true); 1904 } 1905 1906 /* increase throttled vcp size */ 1907 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1908 pbn_per_slot = get_pbn_per_slot(stream); 1909 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1910 1911 if (link_hwss->ext.set_throttled_vcp_size) 1912 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1913 if (link_hwss->ext.set_hblank_min_symbol_width) 1914 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1915 &link->cur_link_settings, 1916 avg_time_slots_per_mtp); 1917 1918 return DC_OK; 1919 } 1920 1921 static void disable_link_dp(struct dc_link *link, 1922 const struct link_resource *link_res, 1923 enum signal_type signal) 1924 { 1925 struct dc_link_settings link_settings = link->cur_link_settings; 1926 1927 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1928 link->mst_stream_alloc_table.stream_count > 0) 1929 /* disable MST link only when last vc payload is deallocated */ 1930 return; 1931 1932 dp_disable_link_phy(link, link_res, signal); 1933 1934 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1935 if (!link->skip_implict_edp_power_control) 1936 link->dc->hwss.edp_power_control(link, false); 1937 } 1938 1939 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1940 /* set the sink to SST mode after disabling the link */ 1941 enable_mst_on_sink(link, false); 1942 1943 if (link_dp_get_encoding_format(&link_settings) == 1944 DP_8b_10b_ENCODING) { 1945 dp_set_fec_enable(link, false); 1946 dp_set_fec_ready(link, link_res, false); 1947 } 1948 } 1949 1950 static void disable_link(struct dc_link *link, 1951 const struct link_resource *link_res, 1952 enum signal_type signal) 1953 { 1954 if (dc_is_dp_signal(signal)) { 1955 disable_link_dp(link, link_res, signal); 1956 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1957 link->dc->hwss.disable_link_output(link, link_res, signal); 1958 } 1959 1960 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1961 /* MST disable link only when no stream use the link */ 1962 if (link->mst_stream_alloc_table.stream_count <= 0) 1963 link->link_status.link_active = false; 1964 } else { 1965 link->link_status.link_active = false; 1966 } 1967 } 1968 1969 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1970 { 1971 struct dc_stream_state *stream = pipe_ctx->stream; 1972 struct dc_link *link = stream->link; 1973 enum dc_color_depth display_color_depth; 1974 enum engine_id eng_id; 1975 struct ext_hdmi_settings settings = {0}; 1976 bool is_over_340mhz = false; 1977 bool is_vga_mode = (stream->timing.h_addressable == 640) 1978 && (stream->timing.v_addressable == 480); 1979 struct dc *dc = pipe_ctx->stream->ctx->dc; 1980 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1981 1982 if (stream->phy_pix_clk == 0) 1983 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1984 if (stream->phy_pix_clk > 340000) 1985 is_over_340mhz = true; 1986 1987 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1988 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1989 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1990 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1991 /* DP159, Retimer settings */ 1992 eng_id = pipe_ctx->stream_res.stream_enc->id; 1993 1994 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1995 write_i2c_retimer_setting(pipe_ctx, 1996 is_vga_mode, is_over_340mhz, &settings); 1997 } else { 1998 write_i2c_default_retimer_setting(pipe_ctx, 1999 is_vga_mode, is_over_340mhz); 2000 } 2001 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2002 /* PI3EQX1204, Redriver settings */ 2003 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 2004 } 2005 } 2006 2007 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2008 write_scdc_data( 2009 stream->link->ddc, 2010 stream->phy_pix_clk, 2011 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2012 2013 memset(&stream->link->cur_link_settings, 0, 2014 sizeof(struct dc_link_settings)); 2015 2016 display_color_depth = stream->timing.display_color_depth; 2017 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2018 display_color_depth = COLOR_DEPTH_888; 2019 2020 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 2021 * character clock in case that beyond 340MHz. 2022 */ 2023 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 2024 link_hwss->setup_stream_encoder(pipe_ctx); 2025 2026 dc->hwss.enable_tmds_link_output( 2027 link, 2028 &pipe_ctx->link_res, 2029 pipe_ctx->stream->signal, 2030 pipe_ctx->clock_source->id, 2031 display_color_depth, 2032 stream->phy_pix_clk); 2033 2034 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2035 read_scdc_data(link->ddc); 2036 } 2037 2038 static enum dc_status enable_link_dp(struct dc_state *state, 2039 struct pipe_ctx *pipe_ctx) 2040 { 2041 struct dc_stream_state *stream = pipe_ctx->stream; 2042 enum dc_status status; 2043 bool skip_video_pattern; 2044 struct dc_link *link = stream->link; 2045 const struct dc_link_settings *link_settings = 2046 &pipe_ctx->link_config.dp_link_settings; 2047 bool fec_enable; 2048 int i; 2049 bool apply_seamless_boot_optimization = false; 2050 uint32_t bl_oled_enable_delay = 50; // in ms 2051 uint32_t post_oui_delay = 30; // 30ms 2052 /* Reduce link bandwidth between failed link training attempts. */ 2053 bool do_fallback = false; 2054 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2055 2056 // Increase retry count if attempting DP1.x on FIXED_VS link 2057 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2058 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2059 lt_attempts = 10; 2060 2061 // check for seamless boot 2062 for (i = 0; i < state->stream_count; i++) { 2063 if (state->streams[i]->apply_seamless_boot_optimization) { 2064 apply_seamless_boot_optimization = true; 2065 break; 2066 } 2067 } 2068 2069 /* 2070 * If the link is DP-over-USB4 do the following: 2071 * - Train with fallback when enabling DPIA link. Conventional links are 2072 * trained with fallback during sink detection. 2073 * - Allocate only what the stream needs for bw in Gbps. Inform the CM 2074 * in case stream needs more or less bw from what has been allocated 2075 * earlier at plug time. 2076 */ 2077 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 2078 do_fallback = true; 2079 } 2080 2081 /* 2082 * Temporary w/a to get DP2.0 link rates to work with SST. 2083 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2084 */ 2085 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2086 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2087 link->dc->debug.set_mst_en_for_sst) { 2088 enable_mst_on_sink(link, true); 2089 } 2090 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2091 /*in case it is not on*/ 2092 if (!link->dc->config.edp_no_power_sequencing) 2093 link->dc->hwss.edp_power_control(link, true); 2094 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2095 } 2096 2097 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2098 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2099 } else { 2100 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2101 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2102 if (state->clk_mgr && !apply_seamless_boot_optimization) 2103 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2104 state, false); 2105 } 2106 2107 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2108 dpcd_set_source_specific_data(link); 2109 if (link->dpcd_sink_ext_caps.raw != 0) { 2110 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2111 msleep(post_oui_delay); 2112 } 2113 2114 // similarly, mode switch can cause loss of cable ID 2115 dpcd_write_cable_id_to_dprx(link); 2116 2117 skip_video_pattern = true; 2118 2119 if (link_settings->link_rate == LINK_RATE_LOW) 2120 skip_video_pattern = false; 2121 2122 if (perform_link_training_with_retries(link_settings, 2123 skip_video_pattern, 2124 lt_attempts, 2125 pipe_ctx, 2126 pipe_ctx->stream->signal, 2127 do_fallback)) { 2128 status = DC_OK; 2129 } else { 2130 status = DC_FAIL_DP_LINK_TRAINING; 2131 } 2132 2133 if (link->preferred_training_settings.fec_enable) 2134 fec_enable = *link->preferred_training_settings.fec_enable; 2135 else 2136 fec_enable = true; 2137 2138 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2139 dp_set_fec_enable(link, fec_enable); 2140 2141 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2142 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2143 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2144 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2145 set_default_brightness_aux(link); 2146 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2147 msleep(bl_oled_enable_delay); 2148 edp_backlight_enable_aux(link, true); 2149 } 2150 2151 return status; 2152 } 2153 2154 static enum dc_status enable_link_edp( 2155 struct dc_state *state, 2156 struct pipe_ctx *pipe_ctx) 2157 { 2158 return enable_link_dp(state, pipe_ctx); 2159 } 2160 2161 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2162 { 2163 struct dc_stream_state *stream = pipe_ctx->stream; 2164 struct dc_link *link = stream->link; 2165 struct dc *dc = stream->ctx->dc; 2166 2167 if (stream->phy_pix_clk == 0) 2168 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2169 2170 memset(&stream->link->cur_link_settings, 0, 2171 sizeof(struct dc_link_settings)); 2172 dc->hwss.enable_lvds_link_output( 2173 link, 2174 &pipe_ctx->link_res, 2175 pipe_ctx->clock_source->id, 2176 stream->phy_pix_clk); 2177 2178 } 2179 2180 static enum dc_status enable_link_dp_mst( 2181 struct dc_state *state, 2182 struct pipe_ctx *pipe_ctx) 2183 { 2184 struct dc_link *link = pipe_ctx->stream->link; 2185 unsigned char mstm_cntl; 2186 2187 /* sink signal type after MST branch is MST. Multiple MST sinks 2188 * share one link. Link DP PHY is enable or training only once. 2189 */ 2190 if (link->link_status.link_active) 2191 return DC_OK; 2192 2193 /* clear payload table */ 2194 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2195 if (mstm_cntl & DP_MST_EN) 2196 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2197 2198 /* to make sure the pending down rep can be processed 2199 * before enabling the link 2200 */ 2201 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2202 2203 /* set the sink to MST mode before enabling the link */ 2204 enable_mst_on_sink(link, true); 2205 2206 return enable_link_dp(state, pipe_ctx); 2207 } 2208 2209 static enum dc_status enable_link( 2210 struct dc_state *state, 2211 struct pipe_ctx *pipe_ctx) 2212 { 2213 enum dc_status status = DC_ERROR_UNEXPECTED; 2214 struct dc_stream_state *stream = pipe_ctx->stream; 2215 struct dc_link *link = stream->link; 2216 2217 /* There's some scenarios where driver is unloaded with display 2218 * still enabled. When driver is reloaded, it may cause a display 2219 * to not light up if there is a mismatch between old and new 2220 * link settings. Need to call disable first before enabling at 2221 * new link settings. 2222 */ 2223 if (link->link_status.link_active) 2224 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2225 2226 switch (pipe_ctx->stream->signal) { 2227 case SIGNAL_TYPE_DISPLAY_PORT: 2228 status = enable_link_dp(state, pipe_ctx); 2229 break; 2230 case SIGNAL_TYPE_EDP: 2231 status = enable_link_edp(state, pipe_ctx); 2232 break; 2233 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2234 status = enable_link_dp_mst(state, pipe_ctx); 2235 msleep(200); 2236 break; 2237 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2238 case SIGNAL_TYPE_DVI_DUAL_LINK: 2239 case SIGNAL_TYPE_HDMI_TYPE_A: 2240 enable_link_hdmi(pipe_ctx); 2241 status = DC_OK; 2242 break; 2243 case SIGNAL_TYPE_LVDS: 2244 enable_link_lvds(pipe_ctx); 2245 status = DC_OK; 2246 break; 2247 case SIGNAL_TYPE_VIRTUAL: 2248 status = DC_OK; 2249 break; 2250 default: 2251 break; 2252 } 2253 2254 if (status == DC_OK) { 2255 pipe_ctx->stream->link->link_status.link_active = true; 2256 } 2257 2258 return status; 2259 } 2260 2261 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2262 { 2263 struct dc *dc = pipe_ctx->stream->ctx->dc; 2264 struct dc_stream_state *stream = pipe_ctx->stream; 2265 struct dc_link *link = stream->sink->link; 2266 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2267 2268 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2269 2270 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2271 2272 if (dp_is_128b_132b_signal(pipe_ctx)) 2273 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2274 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2275 return; 2276 2277 if (pipe_ctx->stream->sink) { 2278 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2279 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2280 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2281 pipe_ctx->stream->sink->edid_caps.display_name, 2282 pipe_ctx->stream->signal); 2283 } 2284 } 2285 2286 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2287 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2288 set_avmute(pipe_ctx, true); 2289 } 2290 2291 dc->hwss.disable_audio_stream(pipe_ctx); 2292 2293 update_psp_stream_config(pipe_ctx, true); 2294 dc->hwss.blank_stream(pipe_ctx); 2295 2296 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2297 deallocate_mst_payload(pipe_ctx); 2298 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2299 dp_is_128b_132b_signal(pipe_ctx)) 2300 update_sst_payload(pipe_ctx, false); 2301 2302 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2303 struct ext_hdmi_settings settings = {0}; 2304 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2305 2306 unsigned short masked_chip_caps = link->chip_caps & 2307 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2308 //Need to inform that sink is going to use legacy HDMI mode. 2309 write_scdc_data( 2310 link->ddc, 2311 165000,//vbios only handles 165Mhz. 2312 false); 2313 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2314 /* DP159, Retimer settings */ 2315 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2316 write_i2c_retimer_setting(pipe_ctx, 2317 false, false, &settings); 2318 else 2319 write_i2c_default_retimer_setting(pipe_ctx, 2320 false, false); 2321 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2322 /* PI3EQX1204, Redriver settings */ 2323 write_i2c_redriver_setting(pipe_ctx, false); 2324 } 2325 } 2326 2327 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2328 !dp_is_128b_132b_signal(pipe_ctx)) { 2329 2330 /* In DP1.x SST mode, our encoder will go to TPS1 2331 * when link is on but stream is off. 2332 * Disabling link before stream will avoid exposing TPS1 pattern 2333 * during the disable sequence as it will confuse some receivers 2334 * state machine. 2335 * In DP2 or MST mode, our encoder will stay video active 2336 */ 2337 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2338 dc->hwss.disable_stream(pipe_ctx); 2339 } else { 2340 dc->hwss.disable_stream(pipe_ctx); 2341 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2342 } 2343 2344 if (pipe_ctx->stream->timing.flags.DSC) { 2345 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2346 link_set_dsc_enable(pipe_ctx, false); 2347 } 2348 if (dp_is_128b_132b_signal(pipe_ctx)) { 2349 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2350 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2351 } 2352 2353 if (vpg && vpg->funcs->vpg_powerdown) 2354 vpg->funcs->vpg_powerdown(vpg); 2355 2356 /* for psp not exist case */ 2357 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2358 /* reset internal save state to default since eDP is off */ 2359 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2360 /* since current psp not loaded, we need to reset it to default*/ 2361 link->panel_mode = panel_mode; 2362 } 2363 } 2364 2365 void link_set_dpms_on( 2366 struct dc_state *state, 2367 struct pipe_ctx *pipe_ctx) 2368 { 2369 struct dc *dc = pipe_ctx->stream->ctx->dc; 2370 struct dc_stream_state *stream = pipe_ctx->stream; 2371 struct dc_link *link = stream->sink->link; 2372 enum dc_status status; 2373 struct link_encoder *link_enc; 2374 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2375 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2376 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2377 bool apply_edp_fast_boot_optimization = 2378 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2379 2380 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2381 2382 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2383 2384 if (dp_is_128b_132b_signal(pipe_ctx)) 2385 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2386 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2387 return; 2388 2389 if (pipe_ctx->stream->sink) { 2390 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2391 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2392 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2393 pipe_ctx->stream->sink->edid_caps.display_name, 2394 pipe_ctx->stream->signal); 2395 } 2396 } 2397 2398 link_enc = link_enc_cfg_get_link_enc(link); 2399 ASSERT(link_enc); 2400 2401 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2402 && !dp_is_128b_132b_signal(pipe_ctx)) { 2403 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2404 2405 if (link_enc) 2406 link_enc->funcs->setup( 2407 link_enc, 2408 pipe_ctx->stream->signal); 2409 2410 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2411 stream_enc->funcs->dig_stream_enable( 2412 stream_enc, 2413 pipe_ctx->stream->signal, 1); 2414 } 2415 2416 pipe_ctx->stream->link->link_state_valid = true; 2417 2418 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2419 if (dp_is_128b_132b_signal(pipe_ctx)) 2420 otg_out_dest = OUT_MUX_HPO_DP; 2421 else 2422 otg_out_dest = OUT_MUX_DIO; 2423 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2424 } 2425 2426 link_hwss->setup_stream_attribute(pipe_ctx); 2427 2428 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2429 2430 // Enable VPG before building infoframe 2431 if (vpg && vpg->funcs->vpg_poweron) 2432 vpg->funcs->vpg_poweron(vpg); 2433 2434 resource_build_info_frame(pipe_ctx); 2435 dc->hwss.update_info_frame(pipe_ctx); 2436 2437 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2438 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2439 2440 /* Do not touch link on seamless boot optimization. */ 2441 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2442 pipe_ctx->stream->dpms_off = false; 2443 2444 /* Still enable stream features & audio on seamless boot for DP external displays */ 2445 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2446 enable_stream_features(pipe_ctx); 2447 dc->hwss.enable_audio_stream(pipe_ctx); 2448 } 2449 2450 update_psp_stream_config(pipe_ctx, false); 2451 return; 2452 } 2453 2454 /* eDP lit up by bios already, no need to enable again. */ 2455 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2456 apply_edp_fast_boot_optimization && 2457 !pipe_ctx->stream->timing.flags.DSC && 2458 !pipe_ctx->next_odm_pipe) { 2459 pipe_ctx->stream->dpms_off = false; 2460 update_psp_stream_config(pipe_ctx, false); 2461 return; 2462 } 2463 2464 if (pipe_ctx->stream->dpms_off) 2465 return; 2466 2467 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2468 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2469 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2470 * will be automatically set at a later time when the video is enabled 2471 * (DP_VID_STREAM_EN = 1). 2472 */ 2473 if (pipe_ctx->stream->timing.flags.DSC) { 2474 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2475 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2476 link_set_dsc_enable(pipe_ctx, true); 2477 } 2478 2479 status = enable_link(state, pipe_ctx); 2480 2481 if (status != DC_OK) { 2482 DC_LOG_WARNING("enabling link %u failed: %d\n", 2483 pipe_ctx->stream->link->link_index, 2484 status); 2485 2486 /* Abort stream enable *unless* the failure was due to 2487 * DP link training - some DP monitors will recover and 2488 * show the stream anyway. But MST displays can't proceed 2489 * without link training. 2490 */ 2491 if (status != DC_FAIL_DP_LINK_TRAINING || 2492 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2493 if (false == stream->link->link_status.link_active) 2494 disable_link(stream->link, &pipe_ctx->link_res, 2495 pipe_ctx->stream->signal); 2496 BREAK_TO_DEBUGGER(); 2497 return; 2498 } 2499 } 2500 2501 /* turn off otg test pattern if enable */ 2502 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2503 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2504 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2505 COLOR_DEPTH_UNDEFINED); 2506 2507 /* This second call is needed to reconfigure the DIG 2508 * as a workaround for the incorrect value being applied 2509 * from transmitter control. 2510 */ 2511 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2512 dp_is_128b_132b_signal(pipe_ctx))) { 2513 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2514 2515 if (link_enc) 2516 link_enc->funcs->setup( 2517 link_enc, 2518 pipe_ctx->stream->signal); 2519 2520 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2521 stream_enc->funcs->dig_stream_enable( 2522 stream_enc, 2523 pipe_ctx->stream->signal, 1); 2524 2525 } 2526 2527 dc->hwss.enable_stream(pipe_ctx); 2528 2529 /* Set DPS PPS SDP (AKA "info frames") */ 2530 if (pipe_ctx->stream->timing.flags.DSC) { 2531 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2532 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2533 dp_set_dsc_on_rx(pipe_ctx, true); 2534 link_set_dsc_pps_packet(pipe_ctx, true, true); 2535 } 2536 } 2537 2538 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2539 allocate_mst_payload(pipe_ctx); 2540 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2541 dp_is_128b_132b_signal(pipe_ctx)) 2542 update_sst_payload(pipe_ctx, true); 2543 2544 dc->hwss.unblank_stream(pipe_ctx, 2545 &pipe_ctx->stream->link->cur_link_settings); 2546 2547 if (stream->sink_patches.delay_ignore_msa > 0) 2548 msleep(stream->sink_patches.delay_ignore_msa); 2549 2550 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2551 enable_stream_features(pipe_ctx); 2552 update_psp_stream_config(pipe_ctx, false); 2553 2554 dc->hwss.enable_audio_stream(pipe_ctx); 2555 2556 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2557 set_avmute(pipe_ctx, false); 2558 } 2559 } 2560