1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #define DC_LOGGER \ 59 dc_logger 60 #define DC_LOGGER_INIT(logger) \ 61 struct dal_logger *dc_logger = logger 62 63 #define LINK_INFO(...) \ 64 DC_LOG_HW_HOTPLUG( \ 65 __VA_ARGS__) 66 67 #define RETIMER_REDRIVER_INFO(...) \ 68 DC_LOG_RETIMER_REDRIVER( \ 69 __VA_ARGS__) 70 #include "dc/dcn30/dcn30_vpg.h" 71 72 #define MAX_MTP_SLOT_COUNT 64 73 #define LINK_TRAINING_ATTEMPTS 4 74 #define PEAK_FACTOR_X1000 1006 75 76 void link_blank_all_dp_displays(struct dc *dc) 77 { 78 unsigned int i; 79 uint8_t dpcd_power_state = '\0'; 80 enum dc_status status = DC_ERROR_UNEXPECTED; 81 82 for (i = 0; i < dc->link_count; i++) { 83 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 84 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 85 continue; 86 87 /* DP 2.0 spec requires that we read LTTPR caps first */ 88 dp_retrieve_lttpr_cap(dc->links[i]); 89 /* if any of the displays are lit up turn them off */ 90 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 91 &dpcd_power_state, sizeof(dpcd_power_state)); 92 93 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 94 link_blank_dp_stream(dc->links[i], true); 95 } 96 97 } 98 99 void link_blank_all_edp_displays(struct dc *dc) 100 { 101 unsigned int i; 102 uint8_t dpcd_power_state = '\0'; 103 enum dc_status status = DC_ERROR_UNEXPECTED; 104 105 for (i = 0; i < dc->link_count; i++) { 106 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 107 (!dc->links[i]->edp_sink_present)) 108 continue; 109 110 /* if any of the displays are lit up turn them off */ 111 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 112 &dpcd_power_state, sizeof(dpcd_power_state)); 113 114 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 115 link_blank_dp_stream(dc->links[i], true); 116 } 117 } 118 119 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 120 { 121 unsigned int j; 122 struct dc *dc = link->ctx->dc; 123 enum signal_type signal = link->connector_signal; 124 125 if ((signal == SIGNAL_TYPE_EDP) || 126 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 127 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 128 link->link_enc->funcs->get_dig_frontend && 129 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 130 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 131 132 if (fe != ENGINE_ID_UNKNOWN) 133 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 134 if (fe == dc->res_pool->stream_enc[j]->id) { 135 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 136 dc->res_pool->stream_enc[j]); 137 break; 138 } 139 } 140 } 141 142 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 143 dpcd_write_rx_power_ctrl(link, false); 144 } 145 } 146 147 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 148 { 149 struct pipe_ctx *pipes[MAX_PIPES]; 150 struct dc_state *state = link->dc->current_state; 151 uint8_t count; 152 int i; 153 struct dc_stream_update stream_update; 154 bool dpms_off = true; 155 struct link_resource link_res = {0}; 156 157 memset(&stream_update, 0, sizeof(stream_update)); 158 stream_update.dpms_off = &dpms_off; 159 160 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 161 162 for (i = 0; i < count; i++) { 163 stream_update.stream = pipes[i]->stream; 164 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 165 pipes[i]->stream, &stream_update, 166 state); 167 } 168 169 /* link can be also enabled by vbios. In this case it is not recorded 170 * in pipe_ctx. Disable link phy here to make sure it is completely off 171 */ 172 dp_disable_link_phy(link, &link_res, link->connector_signal); 173 } 174 175 void link_resume(struct dc_link *link) 176 { 177 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 178 program_hpd_filter(link); 179 } 180 181 /* This function returns true if the pipe is used to feed video signal directly 182 * to the link. 183 */ 184 static bool is_master_pipe_for_link(const struct dc_link *link, 185 const struct pipe_ctx *pipe) 186 { 187 return resource_is_pipe_type(pipe, OTG_MASTER) && 188 pipe->stream->link == link; 189 } 190 191 /* 192 * This function finds all master pipes feeding to a given link with dpms set to 193 * on in given dc state. 194 */ 195 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 196 struct dc_state *state, 197 uint8_t *count, 198 struct pipe_ctx *pipes[MAX_PIPES]) 199 { 200 int i; 201 struct pipe_ctx *pipe = NULL; 202 203 *count = 0; 204 for (i = 0; i < MAX_PIPES; i++) { 205 pipe = &state->res_ctx.pipe_ctx[i]; 206 207 if (is_master_pipe_for_link(link, pipe) && 208 pipe->stream->dpms_off == false) { 209 pipes[(*count)++] = pipe; 210 } 211 } 212 } 213 214 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 215 enum engine_id eng_id, 216 struct ext_hdmi_settings *settings) 217 { 218 bool result = false; 219 int i = 0; 220 struct integrated_info *integrated_info = 221 pipe_ctx->stream->ctx->dc_bios->integrated_info; 222 223 if (integrated_info == NULL) 224 return false; 225 226 /* 227 * Get retimer settings from sbios for passing SI eye test for DCE11 228 * The setting values are varied based on board revision and port id 229 * Therefore the setting values of each ports is passed by sbios. 230 */ 231 232 // Check if current bios contains ext Hdmi settings 233 if (integrated_info->gpu_cap_info & 0x20) { 234 switch (eng_id) { 235 case ENGINE_ID_DIGA: 236 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 237 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 238 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 memmove(settings->reg_settings, 240 integrated_info->dp0_ext_hdmi_reg_settings, 241 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 242 memmove(settings->reg_settings_6g, 243 integrated_info->dp0_ext_hdmi_6g_reg_settings, 244 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 245 result = true; 246 break; 247 case ENGINE_ID_DIGB: 248 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 249 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 250 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 memmove(settings->reg_settings, 252 integrated_info->dp1_ext_hdmi_reg_settings, 253 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 254 memmove(settings->reg_settings_6g, 255 integrated_info->dp1_ext_hdmi_6g_reg_settings, 256 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 257 result = true; 258 break; 259 case ENGINE_ID_DIGC: 260 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 261 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 262 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 memmove(settings->reg_settings, 264 integrated_info->dp2_ext_hdmi_reg_settings, 265 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 266 memmove(settings->reg_settings_6g, 267 integrated_info->dp2_ext_hdmi_6g_reg_settings, 268 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 269 result = true; 270 break; 271 case ENGINE_ID_DIGD: 272 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 273 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 274 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 memmove(settings->reg_settings, 276 integrated_info->dp3_ext_hdmi_reg_settings, 277 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 278 memmove(settings->reg_settings_6g, 279 integrated_info->dp3_ext_hdmi_6g_reg_settings, 280 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 281 result = true; 282 break; 283 default: 284 break; 285 } 286 287 if (result == true) { 288 // Validate settings from bios integrated info table 289 if (settings->slv_addr == 0) 290 return false; 291 if (settings->reg_num > 9) 292 return false; 293 if (settings->reg_num_6g > 3) 294 return false; 295 296 for (i = 0; i < settings->reg_num; i++) { 297 if (settings->reg_settings[i].i2c_reg_index > 0x20) 298 return false; 299 } 300 301 for (i = 0; i < settings->reg_num_6g; i++) { 302 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 303 return false; 304 } 305 } 306 } 307 308 return result; 309 } 310 311 static bool write_i2c(struct pipe_ctx *pipe_ctx, 312 uint8_t address, uint8_t *buffer, uint32_t length) 313 { 314 struct i2c_command cmd = {0}; 315 struct i2c_payload payload = {0}; 316 317 memset(&payload, 0, sizeof(payload)); 318 memset(&cmd, 0, sizeof(cmd)); 319 320 cmd.number_of_payloads = 1; 321 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 322 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 323 324 payload.address = address; 325 payload.data = buffer; 326 payload.length = length; 327 payload.write = true; 328 cmd.payloads = &payload; 329 330 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 331 pipe_ctx->stream->link, &cmd)) 332 return true; 333 334 return false; 335 } 336 337 static void write_i2c_retimer_setting( 338 struct pipe_ctx *pipe_ctx, 339 bool is_vga_mode, 340 bool is_over_340mhz, 341 struct ext_hdmi_settings *settings) 342 { 343 uint8_t slave_address = (settings->slv_addr >> 1); 344 uint8_t buffer[2]; 345 const uint8_t apply_rx_tx_change = 0x4; 346 uint8_t offset = 0xA; 347 uint8_t value = 0; 348 int i = 0; 349 bool i2c_success = false; 350 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 351 352 memset(&buffer, 0, sizeof(buffer)); 353 354 /* Start Ext-Hdmi programming*/ 355 356 for (i = 0; i < settings->reg_num; i++) { 357 /* Apply 3G settings */ 358 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 359 360 buffer[0] = settings->reg_settings[i].i2c_reg_index; 361 buffer[1] = settings->reg_settings[i].i2c_reg_val; 362 i2c_success = write_i2c(pipe_ctx, slave_address, 363 buffer, sizeof(buffer)); 364 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 365 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 366 slave_address, buffer[0], buffer[1], i2c_success?1:0); 367 368 if (!i2c_success) 369 goto i2c_write_fail; 370 371 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 372 * needs to be set to 1 on every 0xA-0xC write. 373 */ 374 if (settings->reg_settings[i].i2c_reg_index == 0xA || 375 settings->reg_settings[i].i2c_reg_index == 0xB || 376 settings->reg_settings[i].i2c_reg_index == 0xC) { 377 378 /* Query current value from offset 0xA */ 379 if (settings->reg_settings[i].i2c_reg_index == 0xA) 380 value = settings->reg_settings[i].i2c_reg_val; 381 else { 382 i2c_success = 383 link_query_ddc_data( 384 pipe_ctx->stream->link->ddc, 385 slave_address, &offset, 1, &value, 1); 386 if (!i2c_success) 387 goto i2c_write_fail; 388 } 389 390 buffer[0] = offset; 391 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 392 buffer[1] = value | apply_rx_tx_change; 393 i2c_success = write_i2c(pipe_ctx, slave_address, 394 buffer, sizeof(buffer)); 395 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 396 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 397 slave_address, buffer[0], buffer[1], i2c_success?1:0); 398 if (!i2c_success) 399 goto i2c_write_fail; 400 } 401 } 402 } 403 404 /* Apply 3G settings */ 405 if (is_over_340mhz) { 406 for (i = 0; i < settings->reg_num_6g; i++) { 407 /* Apply 3G settings */ 408 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 409 410 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 411 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 412 i2c_success = write_i2c(pipe_ctx, slave_address, 413 buffer, sizeof(buffer)); 414 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 415 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 416 slave_address, buffer[0], buffer[1], i2c_success?1:0); 417 418 if (!i2c_success) 419 goto i2c_write_fail; 420 421 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 422 * needs to be set to 1 on every 0xA-0xC write. 423 */ 424 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 425 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 427 428 /* Query current value from offset 0xA */ 429 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 430 value = settings->reg_settings_6g[i].i2c_reg_val; 431 else { 432 i2c_success = 433 link_query_ddc_data( 434 pipe_ctx->stream->link->ddc, 435 slave_address, &offset, 1, &value, 1); 436 if (!i2c_success) 437 goto i2c_write_fail; 438 } 439 440 buffer[0] = offset; 441 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 442 buffer[1] = value | apply_rx_tx_change; 443 i2c_success = write_i2c(pipe_ctx, slave_address, 444 buffer, sizeof(buffer)); 445 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 446 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 447 slave_address, buffer[0], buffer[1], i2c_success?1:0); 448 if (!i2c_success) 449 goto i2c_write_fail; 450 } 451 } 452 } 453 } 454 455 if (is_vga_mode) { 456 /* Program additional settings if using 640x480 resolution */ 457 458 /* Write offset 0xFF to 0x01 */ 459 buffer[0] = 0xff; 460 buffer[1] = 0x01; 461 i2c_success = write_i2c(pipe_ctx, slave_address, 462 buffer, sizeof(buffer)); 463 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 464 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 465 slave_address, buffer[0], buffer[1], i2c_success?1:0); 466 if (!i2c_success) 467 goto i2c_write_fail; 468 469 /* Write offset 0x00 to 0x23 */ 470 buffer[0] = 0x00; 471 buffer[1] = 0x23; 472 i2c_success = write_i2c(pipe_ctx, slave_address, 473 buffer, sizeof(buffer)); 474 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 475 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 476 slave_address, buffer[0], buffer[1], i2c_success?1:0); 477 if (!i2c_success) 478 goto i2c_write_fail; 479 480 /* Write offset 0xff to 0x00 */ 481 buffer[0] = 0xff; 482 buffer[1] = 0x00; 483 i2c_success = write_i2c(pipe_ctx, slave_address, 484 buffer, sizeof(buffer)); 485 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 486 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 487 slave_address, buffer[0], buffer[1], i2c_success?1:0); 488 if (!i2c_success) 489 goto i2c_write_fail; 490 491 } 492 493 return; 494 495 i2c_write_fail: 496 DC_LOG_DEBUG("Set retimer failed"); 497 } 498 499 static void write_i2c_default_retimer_setting( 500 struct pipe_ctx *pipe_ctx, 501 bool is_vga_mode, 502 bool is_over_340mhz) 503 { 504 uint8_t slave_address = (0xBA >> 1); 505 uint8_t buffer[2]; 506 bool i2c_success = false; 507 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 508 509 memset(&buffer, 0, sizeof(buffer)); 510 511 /* Program Slave Address for tuning single integrity */ 512 /* Write offset 0x0A to 0x13 */ 513 buffer[0] = 0x0A; 514 buffer[1] = 0x13; 515 i2c_success = write_i2c(pipe_ctx, slave_address, 516 buffer, sizeof(buffer)); 517 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 518 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 519 slave_address, buffer[0], buffer[1], i2c_success?1:0); 520 if (!i2c_success) 521 goto i2c_write_fail; 522 523 /* Write offset 0x0A to 0x17 */ 524 buffer[0] = 0x0A; 525 buffer[1] = 0x17; 526 i2c_success = write_i2c(pipe_ctx, slave_address, 527 buffer, sizeof(buffer)); 528 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 529 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 530 slave_address, buffer[0], buffer[1], i2c_success?1:0); 531 if (!i2c_success) 532 goto i2c_write_fail; 533 534 /* Write offset 0x0B to 0xDA or 0xD8 */ 535 buffer[0] = 0x0B; 536 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 537 i2c_success = write_i2c(pipe_ctx, slave_address, 538 buffer, sizeof(buffer)); 539 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 540 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 541 slave_address, buffer[0], buffer[1], i2c_success?1:0); 542 if (!i2c_success) 543 goto i2c_write_fail; 544 545 /* Write offset 0x0A to 0x17 */ 546 buffer[0] = 0x0A; 547 buffer[1] = 0x17; 548 i2c_success = write_i2c(pipe_ctx, slave_address, 549 buffer, sizeof(buffer)); 550 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 551 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 552 slave_address, buffer[0], buffer[1], i2c_success?1:0); 553 if (!i2c_success) 554 goto i2c_write_fail; 555 556 /* Write offset 0x0C to 0x1D or 0x91 */ 557 buffer[0] = 0x0C; 558 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 559 i2c_success = write_i2c(pipe_ctx, slave_address, 560 buffer, sizeof(buffer)); 561 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 562 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 563 slave_address, buffer[0], buffer[1], i2c_success?1:0); 564 if (!i2c_success) 565 goto i2c_write_fail; 566 567 /* Write offset 0x0A to 0x17 */ 568 buffer[0] = 0x0A; 569 buffer[1] = 0x17; 570 i2c_success = write_i2c(pipe_ctx, slave_address, 571 buffer, sizeof(buffer)); 572 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 573 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 574 slave_address, buffer[0], buffer[1], i2c_success?1:0); 575 if (!i2c_success) 576 goto i2c_write_fail; 577 578 579 if (is_vga_mode) { 580 /* Program additional settings if using 640x480 resolution */ 581 582 /* Write offset 0xFF to 0x01 */ 583 buffer[0] = 0xff; 584 buffer[1] = 0x01; 585 i2c_success = write_i2c(pipe_ctx, slave_address, 586 buffer, sizeof(buffer)); 587 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 588 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 589 slave_address, buffer[0], buffer[1], i2c_success?1:0); 590 if (!i2c_success) 591 goto i2c_write_fail; 592 593 /* Write offset 0x00 to 0x23 */ 594 buffer[0] = 0x00; 595 buffer[1] = 0x23; 596 i2c_success = write_i2c(pipe_ctx, slave_address, 597 buffer, sizeof(buffer)); 598 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 599 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 600 slave_address, buffer[0], buffer[1], i2c_success?1:0); 601 if (!i2c_success) 602 goto i2c_write_fail; 603 604 /* Write offset 0xff to 0x00 */ 605 buffer[0] = 0xff; 606 buffer[1] = 0x00; 607 i2c_success = write_i2c(pipe_ctx, slave_address, 608 buffer, sizeof(buffer)); 609 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 610 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 611 slave_address, buffer[0], buffer[1], i2c_success?1:0); 612 if (!i2c_success) 613 goto i2c_write_fail; 614 } 615 616 return; 617 618 i2c_write_fail: 619 DC_LOG_DEBUG("Set default retimer failed"); 620 } 621 622 static void write_i2c_redriver_setting( 623 struct pipe_ctx *pipe_ctx, 624 bool is_over_340mhz) 625 { 626 uint8_t slave_address = (0xF0 >> 1); 627 uint8_t buffer[16]; 628 bool i2c_success = false; 629 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 630 631 memset(&buffer, 0, sizeof(buffer)); 632 633 // Program Slave Address for tuning single integrity 634 buffer[3] = 0x4E; 635 buffer[4] = 0x4E; 636 buffer[5] = 0x4E; 637 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 638 639 i2c_success = write_i2c(pipe_ctx, slave_address, 640 buffer, sizeof(buffer)); 641 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 642 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 643 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 644 i2c_success = %d\n", 645 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 646 647 if (!i2c_success) 648 DC_LOG_DEBUG("Set redriver failed"); 649 } 650 651 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 652 { 653 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 654 struct link_encoder *link_enc = NULL; 655 struct cp_psp_stream_config config = {0}; 656 enum dp_panel_mode panel_mode = 657 dp_get_panel_mode(pipe_ctx->stream->link); 658 659 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 660 return; 661 662 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 663 ASSERT(link_enc); 664 if (link_enc == NULL) 665 return; 666 667 /* otg instance */ 668 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 669 670 /* dig front end */ 671 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 672 673 /* stream encoder index */ 674 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 675 if (dp_is_128b_132b_signal(pipe_ctx)) 676 config.stream_enc_idx = 677 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 678 679 /* dig back end */ 680 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 681 682 /* link encoder index */ 683 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 684 if (dp_is_128b_132b_signal(pipe_ctx)) 685 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 686 687 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 688 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 689 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 690 else 691 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 692 693 694 /* phy index */ 695 config.phy_idx = resource_transmitter_to_phy_idx( 696 pipe_ctx->stream->link->dc, link_enc->transmitter); 697 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 698 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 699 config.phy_idx = 0; 700 701 /* stream properties */ 702 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 703 config.mst_enabled = (pipe_ctx->stream->signal == 704 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 705 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 706 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 707 1 : 0; 708 config.dpms_off = dpms_off; 709 710 /* dm stream context */ 711 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 712 713 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 714 } 715 716 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 717 { 718 struct dc *dc = pipe_ctx->stream->ctx->dc; 719 720 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 721 return; 722 723 dc->hwss.set_avmute(pipe_ctx, enable); 724 } 725 726 static void enable_mst_on_sink(struct dc_link *link, bool enable) 727 { 728 unsigned char mstmCntl; 729 730 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 731 if (enable) 732 mstmCntl |= DP_MST_EN; 733 else 734 mstmCntl &= (~DP_MST_EN); 735 736 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 737 } 738 739 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 740 struct dsc_optc_config *config) 741 { 742 uint32_t precision = 1 << 28; 743 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 744 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 745 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 746 DC_LOGGER_INIT(dsc->ctx->logger); 747 748 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 749 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 750 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 751 */ 752 ll_bytes_per_pix_fraq *= 10000000; 753 ll_bytes_per_pix_fraq /= precision; 754 755 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 756 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 757 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 758 DC_LOG_DSC("\tslice_width %d", config->slice_width); 759 } 760 761 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 762 { 763 struct dc *dc = pipe_ctx->stream->ctx->dc; 764 struct dc_stream_state *stream = pipe_ctx->stream; 765 bool result = false; 766 767 if (dc_is_virtual_signal(stream->signal)) 768 result = true; 769 else 770 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 771 return result; 772 } 773 774 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 775 * i.e. after dp_enable_dsc_on_rx() had been called 776 */ 777 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 778 { 779 /* TODO: Move this to HWSS as this is hardware programming sequence not a 780 * link layer sequence 781 */ 782 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 783 struct dc *dc = pipe_ctx->stream->ctx->dc; 784 struct dc_stream_state *stream = pipe_ctx->stream; 785 struct pipe_ctx *odm_pipe; 786 int opp_cnt = 1; 787 struct dccg *dccg = dc->res_pool->dccg; 788 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 789 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 790 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 791 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 792 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 793 * this problem. We are implementing a workaround here to keep using dscclk 794 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 795 * 48Mhz) pixel clock to avoid hitting this problem. 796 */ 797 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 798 stream->timing.pix_clk_100hz > 480000; 799 DC_LOGGER_INIT(dsc->ctx->logger); 800 801 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 802 opp_cnt++; 803 804 if (enable) { 805 struct dsc_config dsc_cfg; 806 struct dsc_optc_config dsc_optc_cfg; 807 enum optc_dsc_mode optc_dsc_mode; 808 809 /* Enable DSC hw block */ 810 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 811 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 812 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 813 dsc_cfg.color_depth = stream->timing.display_color_depth; 814 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 815 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 816 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 817 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 818 819 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 820 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 821 if (should_use_dto_dscclk) 822 dccg->funcs->set_dto_dscclk(dccg, dsc->inst); 823 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 824 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 825 826 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 827 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 828 if (should_use_dto_dscclk) 829 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst); 830 } 831 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 832 dsc_cfg.pic_width *= opp_cnt; 833 834 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 835 836 /* Enable DSC in encoder */ 837 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 838 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 839 dsc_optc_config_log(dsc, &dsc_optc_cfg); 840 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 841 optc_dsc_mode, 842 dsc_optc_cfg.bytes_per_pixel, 843 dsc_optc_cfg.slice_width); 844 845 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 846 } 847 848 /* Enable DSC in OPTC */ 849 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 850 dsc_optc_config_log(dsc, &dsc_optc_cfg); 851 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 852 optc_dsc_mode, 853 dsc_optc_cfg.bytes_per_pixel, 854 dsc_optc_cfg.slice_width); 855 } else { 856 /* disable DSC in OPTC */ 857 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 858 pipe_ctx->stream_res.tg, 859 OPTC_DSC_DISABLED, 0, 0); 860 861 /* disable DSC in stream encoder */ 862 if (dc_is_dp_signal(stream->signal)) { 863 if (dp_is_128b_132b_signal(pipe_ctx)) 864 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 865 pipe_ctx->stream_res.hpo_dp_stream_enc, 866 false, 867 NULL, 868 true); 869 else { 870 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 871 pipe_ctx->stream_res.stream_enc, 872 OPTC_DSC_DISABLED, 0, 0); 873 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 874 pipe_ctx->stream_res.stream_enc, false, NULL, true); 875 } 876 } 877 878 /* disable DSC block */ 879 if (dccg->funcs->set_ref_dscclk) 880 dccg->funcs->set_ref_dscclk(dccg, pipe_ctx->stream_res.dsc->inst); 881 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 882 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 883 if (dccg->funcs->set_ref_dscclk) 884 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 885 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 886 } 887 } 888 } 889 890 /* 891 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 892 * hence PPS info packet update need to use frame update instead of immediate update. 893 * Added parameter immediate_update for this purpose. 894 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 895 * which is the only place where a "false" would be passed in for param immediate_update. 896 * 897 * immediate_update is only applicable when DSC is enabled. 898 */ 899 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 900 { 901 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 902 struct dc_stream_state *stream = pipe_ctx->stream; 903 DC_LOGGER_INIT(dsc->ctx->logger); 904 905 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 906 return false; 907 908 if (enable) { 909 struct dsc_config dsc_cfg; 910 uint8_t dsc_packed_pps[128]; 911 912 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 913 memset(dsc_packed_pps, 0, 128); 914 915 /* Enable DSC hw block */ 916 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 917 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 918 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 919 dsc_cfg.color_depth = stream->timing.display_color_depth; 920 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 921 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 922 923 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 924 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 925 if (dc_is_dp_signal(stream->signal)) { 926 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 927 if (dp_is_128b_132b_signal(pipe_ctx)) 928 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 929 pipe_ctx->stream_res.hpo_dp_stream_enc, 930 true, 931 &dsc_packed_pps[0], 932 immediate_update); 933 else 934 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 935 pipe_ctx->stream_res.stream_enc, 936 true, 937 &dsc_packed_pps[0], 938 immediate_update); 939 } 940 } else { 941 /* disable DSC PPS in stream encoder */ 942 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 943 if (dc_is_dp_signal(stream->signal)) { 944 if (dp_is_128b_132b_signal(pipe_ctx)) 945 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 946 pipe_ctx->stream_res.hpo_dp_stream_enc, 947 false, 948 NULL, 949 true); 950 else 951 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 952 pipe_ctx->stream_res.stream_enc, false, NULL, true); 953 } 954 } 955 956 return true; 957 } 958 959 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 960 { 961 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 962 bool result = false; 963 964 if (!pipe_ctx->stream->timing.flags.DSC) 965 goto out; 966 if (!dsc) 967 goto out; 968 969 if (enable) { 970 { 971 link_set_dsc_on_stream(pipe_ctx, true); 972 result = true; 973 } 974 } else { 975 dp_set_dsc_on_rx(pipe_ctx, false); 976 link_set_dsc_on_stream(pipe_ctx, false); 977 result = true; 978 } 979 out: 980 return result; 981 } 982 983 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 984 { 985 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 986 987 if (!pipe_ctx->stream->timing.flags.DSC) 988 return false; 989 if (!dsc) 990 return false; 991 992 link_set_dsc_on_stream(pipe_ctx, true); 993 link_set_dsc_pps_packet(pipe_ctx, true, false); 994 return true; 995 } 996 997 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 998 { 999 struct dc_stream_state *stream = pipe_ctx->stream; 1000 1001 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1002 struct dc_link *link = stream->link; 1003 union down_spread_ctrl old_downspread; 1004 union down_spread_ctrl new_downspread; 1005 1006 memset(&old_downspread, 0, sizeof(old_downspread)); 1007 1008 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1009 &old_downspread.raw, sizeof(old_downspread)); 1010 1011 new_downspread.raw = old_downspread.raw; 1012 1013 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1014 (stream->ignore_msa_timing_param) ? 1 : 0; 1015 1016 if (new_downspread.raw != old_downspread.raw) { 1017 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1018 &new_downspread.raw, sizeof(new_downspread)); 1019 } 1020 1021 } else { 1022 dm_helpers_mst_enable_stream_features(stream); 1023 } 1024 } 1025 1026 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1027 { 1028 const uint32_t VCP_Y_PRECISION = 1000; 1029 uint64_t vcp_x, vcp_y; 1030 DC_LOGGER_INIT(link->ctx->logger); 1031 1032 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1033 avg_time_slots_per_mtp = dc_fixpt_add( 1034 avg_time_slots_per_mtp, 1035 dc_fixpt_from_fraction( 1036 1, 1037 2*VCP_Y_PRECISION)); 1038 1039 vcp_x = dc_fixpt_floor( 1040 avg_time_slots_per_mtp); 1041 vcp_y = dc_fixpt_floor( 1042 dc_fixpt_mul_int( 1043 dc_fixpt_sub_int( 1044 avg_time_slots_per_mtp, 1045 dc_fixpt_floor( 1046 avg_time_slots_per_mtp)), 1047 VCP_Y_PRECISION)); 1048 1049 1050 if (link->type == dc_connection_mst_branch) 1051 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1052 "X: %llu " 1053 "Y: %llu/%d", 1054 vcp_x, 1055 vcp_y, 1056 VCP_Y_PRECISION); 1057 else 1058 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1059 "X: %llu " 1060 "Y: %llu/%d", 1061 vcp_x, 1062 vcp_y, 1063 VCP_Y_PRECISION); 1064 } 1065 1066 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1067 { 1068 struct fixed31_32 mbytes_per_sec; 1069 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1070 &stream->link->cur_link_settings); 1071 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1072 1073 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1074 1075 return dc_fixpt_div_int(mbytes_per_sec, 54); 1076 } 1077 1078 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1079 { 1080 struct fixed31_32 peak_kbps; 1081 uint32_t numerator = 0; 1082 uint32_t denominator = 1; 1083 1084 /* 1085 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1086 * required when determining PBN/time slot utilization on the link between 1087 * us and the branch, since that overhead is already accounted for in 1088 * the get_pbn_per_slot function. 1089 * 1090 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1091 * common multiplier to render an integer PBN for all link rate/lane 1092 * counts combinations 1093 * calculate 1094 * peak_kbps *= (64/54) 1095 * peak_kbps /= (8 * 1000) convert to bytes 1096 */ 1097 1098 numerator = 64; 1099 denominator = 54 * 8 * 1000; 1100 kbps *= numerator; 1101 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1102 1103 return peak_kbps; 1104 } 1105 1106 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1107 { 1108 uint64_t kbps; 1109 enum dc_link_encoding_format link_encoding; 1110 1111 if (dp_is_128b_132b_signal(pipe_ctx)) 1112 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1113 else 1114 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1115 1116 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1117 return get_pbn_from_bw_in_kbps(kbps); 1118 } 1119 1120 1121 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1122 static void get_lane_status( 1123 struct dc_link *link, 1124 uint32_t lane_count, 1125 union lane_status *status, 1126 union lane_align_status_updated *status_updated) 1127 { 1128 unsigned int lane; 1129 uint8_t dpcd_buf[3] = {0}; 1130 1131 if (status == NULL || status_updated == NULL) { 1132 return; 1133 } 1134 1135 core_link_read_dpcd( 1136 link, 1137 DP_LANE0_1_STATUS, 1138 dpcd_buf, 1139 sizeof(dpcd_buf)); 1140 1141 for (lane = 0; lane < lane_count; lane++) { 1142 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1143 } 1144 1145 status_updated->raw = dpcd_buf[2]; 1146 } 1147 1148 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1149 { 1150 /* 1151 * wait for ACT handled 1152 */ 1153 int i; 1154 const int act_retries = 30; 1155 enum act_return_status result = ACT_FAILED; 1156 union payload_table_update_status update_status = {0}; 1157 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1158 union lane_align_status_updated lane_status_updated; 1159 DC_LOGGER_INIT(link->ctx->logger); 1160 1161 if (link->aux_access_disabled) 1162 return true; 1163 for (i = 0; i < act_retries; i++) { 1164 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1165 1166 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1167 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1168 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1169 !dp_is_interlane_aligned(lane_status_updated)) { 1170 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1171 "polling for ACT handled."); 1172 result = ACT_LINK_LOST; 1173 break; 1174 } 1175 core_link_read_dpcd( 1176 link, 1177 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1178 &update_status.raw, 1179 1); 1180 1181 if (update_status.bits.ACT_HANDLED == 1) { 1182 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1183 result = ACT_SUCCESS; 1184 break; 1185 } 1186 1187 fsleep(5000); 1188 } 1189 1190 if (result == ACT_FAILED) { 1191 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1192 "continue on. Something is wrong with the branch."); 1193 } 1194 1195 return (result == ACT_SUCCESS); 1196 } 1197 1198 static void update_mst_stream_alloc_table( 1199 struct dc_link *link, 1200 struct stream_encoder *stream_enc, 1201 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1202 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1203 { 1204 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1205 struct link_mst_stream_allocation *dc_alloc; 1206 1207 int i; 1208 int j; 1209 1210 /* if DRM proposed_table has more than one new payload */ 1211 ASSERT(proposed_table->stream_count - 1212 link->mst_stream_alloc_table.stream_count < 2); 1213 1214 /* copy proposed_table to link, add stream encoder */ 1215 for (i = 0; i < proposed_table->stream_count; i++) { 1216 1217 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1218 dc_alloc = 1219 &link->mst_stream_alloc_table.stream_allocations[j]; 1220 1221 if (dc_alloc->vcp_id == 1222 proposed_table->stream_allocations[i].vcp_id) { 1223 1224 work_table[i] = *dc_alloc; 1225 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1226 break; /* exit j loop */ 1227 } 1228 } 1229 1230 /* new vcp_id */ 1231 if (j == link->mst_stream_alloc_table.stream_count) { 1232 work_table[i].vcp_id = 1233 proposed_table->stream_allocations[i].vcp_id; 1234 work_table[i].slot_count = 1235 proposed_table->stream_allocations[i].slot_count; 1236 work_table[i].stream_enc = stream_enc; 1237 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1238 } 1239 } 1240 1241 /* update link->mst_stream_alloc_table with work_table */ 1242 link->mst_stream_alloc_table.stream_count = 1243 proposed_table->stream_count; 1244 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1245 link->mst_stream_alloc_table.stream_allocations[i] = 1246 work_table[i]; 1247 } 1248 1249 static void remove_stream_from_alloc_table( 1250 struct dc_link *link, 1251 struct stream_encoder *dio_stream_enc, 1252 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1253 { 1254 int i = 0; 1255 struct link_mst_stream_allocation_table *table = 1256 &link->mst_stream_alloc_table; 1257 1258 if (hpo_dp_stream_enc) { 1259 for (; i < table->stream_count; i++) 1260 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1261 break; 1262 } else { 1263 for (; i < table->stream_count; i++) 1264 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1265 break; 1266 } 1267 1268 if (i < table->stream_count) { 1269 i++; 1270 for (; i < table->stream_count; i++) 1271 table->stream_allocations[i-1] = table->stream_allocations[i]; 1272 memset(&table->stream_allocations[table->stream_count-1], 0, 1273 sizeof(struct link_mst_stream_allocation)); 1274 table->stream_count--; 1275 } 1276 } 1277 1278 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1279 { 1280 struct dc_stream_state *stream = pipe_ctx->stream; 1281 struct dc_link *link = stream->link; 1282 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1283 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1284 int i; 1285 bool mst_mode = (link->type == dc_connection_mst_branch); 1286 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1287 const struct dc_link_settings empty_link_settings = {0}; 1288 DC_LOGGER_INIT(link->ctx->logger); 1289 1290 /* deallocate_mst_payload is called before disable link. When mode or 1291 * disable/enable monitor, new stream is created which is not in link 1292 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1293 * should not done. For new mode set, map_resources will get engine 1294 * for new stream, so stream_enc->id should be validated until here. 1295 */ 1296 1297 /* slot X.Y */ 1298 if (link_hwss->ext.set_throttled_vcp_size) 1299 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1300 if (link_hwss->ext.set_hblank_min_symbol_width) 1301 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1302 &empty_link_settings, 1303 avg_time_slots_per_mtp); 1304 1305 if (mst_mode) { 1306 /* when link is in mst mode, reply on mst manager to remove 1307 * payload 1308 */ 1309 if (dm_helpers_dp_mst_write_payload_allocation_table( 1310 stream->ctx, 1311 stream, 1312 &proposed_table, 1313 false)) 1314 update_mst_stream_alloc_table( 1315 link, 1316 pipe_ctx->stream_res.stream_enc, 1317 pipe_ctx->stream_res.hpo_dp_stream_enc, 1318 &proposed_table); 1319 else 1320 DC_LOG_WARNING("Failed to update" 1321 "MST allocation table for" 1322 "pipe idx:%d\n", 1323 pipe_ctx->pipe_idx); 1324 } else { 1325 /* when link is no longer in mst mode (mst hub unplugged), 1326 * remove payload with default dc logic 1327 */ 1328 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1329 pipe_ctx->stream_res.hpo_dp_stream_enc); 1330 } 1331 1332 DC_LOG_MST("%s" 1333 "stream_count: %d: ", 1334 __func__, 1335 link->mst_stream_alloc_table.stream_count); 1336 1337 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1338 DC_LOG_MST("stream_enc[%d]: %p " 1339 "stream[%d].hpo_dp_stream_enc: %p " 1340 "stream[%d].vcp_id: %d " 1341 "stream[%d].slot_count: %d\n", 1342 i, 1343 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1344 i, 1345 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1346 i, 1347 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1348 i, 1349 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1350 } 1351 1352 /* update mst stream allocation table hardware state */ 1353 if (link_hwss->ext.update_stream_allocation_table == NULL || 1354 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1355 DC_LOG_DEBUG("Unknown encoding format\n"); 1356 return DC_ERROR_UNEXPECTED; 1357 } 1358 1359 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1360 &link->mst_stream_alloc_table); 1361 1362 if (mst_mode) 1363 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1364 stream->ctx, 1365 stream); 1366 1367 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1368 stream->ctx, 1369 stream); 1370 1371 return DC_OK; 1372 } 1373 1374 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1375 * because stream_encoder is not exposed to dm 1376 */ 1377 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1378 { 1379 struct dc_stream_state *stream = pipe_ctx->stream; 1380 struct dc_link *link = stream->link; 1381 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1382 struct fixed31_32 avg_time_slots_per_mtp; 1383 struct fixed31_32 pbn; 1384 struct fixed31_32 pbn_per_slot; 1385 int i; 1386 enum act_return_status ret; 1387 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1388 DC_LOGGER_INIT(link->ctx->logger); 1389 1390 /* enable_link_dp_mst already check link->enabled_stream_count 1391 * and stream is in link->stream[]. This is called during set mode, 1392 * stream_enc is available. 1393 */ 1394 1395 /* get calculate VC payload for stream: stream_alloc */ 1396 if (dm_helpers_dp_mst_write_payload_allocation_table( 1397 stream->ctx, 1398 stream, 1399 &proposed_table, 1400 true)) 1401 update_mst_stream_alloc_table( 1402 link, 1403 pipe_ctx->stream_res.stream_enc, 1404 pipe_ctx->stream_res.hpo_dp_stream_enc, 1405 &proposed_table); 1406 else 1407 DC_LOG_WARNING("Failed to update" 1408 "MST allocation table for" 1409 "pipe idx:%d\n", 1410 pipe_ctx->pipe_idx); 1411 1412 DC_LOG_MST("%s " 1413 "stream_count: %d: \n ", 1414 __func__, 1415 link->mst_stream_alloc_table.stream_count); 1416 1417 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1418 DC_LOG_MST("stream_enc[%d]: %p " 1419 "stream[%d].hpo_dp_stream_enc: %p " 1420 "stream[%d].vcp_id: %d " 1421 "stream[%d].slot_count: %d\n", 1422 i, 1423 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1424 i, 1425 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1426 i, 1427 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1428 i, 1429 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1430 } 1431 1432 ASSERT(proposed_table.stream_count > 0); 1433 1434 /* program DP source TX for payload */ 1435 if (link_hwss->ext.update_stream_allocation_table == NULL || 1436 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1437 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1438 return DC_ERROR_UNEXPECTED; 1439 } 1440 1441 link_hwss->ext.update_stream_allocation_table(link, 1442 &pipe_ctx->link_res, 1443 &link->mst_stream_alloc_table); 1444 1445 /* send down message */ 1446 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1447 stream->ctx, 1448 stream); 1449 1450 if (ret != ACT_LINK_LOST) 1451 dm_helpers_dp_mst_send_payload_allocation( 1452 stream->ctx, 1453 stream); 1454 1455 /* slot X.Y for only current stream */ 1456 pbn_per_slot = get_pbn_per_slot(stream); 1457 if (pbn_per_slot.value == 0) { 1458 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1459 return DC_UNSUPPORTED_VALUE; 1460 } 1461 pbn = get_pbn_from_timing(pipe_ctx); 1462 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1463 1464 log_vcp_x_y(link, avg_time_slots_per_mtp); 1465 1466 if (link_hwss->ext.set_throttled_vcp_size) 1467 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1468 if (link_hwss->ext.set_hblank_min_symbol_width) 1469 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1470 &link->cur_link_settings, 1471 avg_time_slots_per_mtp); 1472 1473 return DC_OK; 1474 } 1475 1476 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1477 const struct dc_stream_state *stream, 1478 const struct dc_link *link) 1479 { 1480 struct fixed31_32 link_bw_effective = 1481 dc_fixpt_from_int( 1482 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1483 struct fixed31_32 timeslot_bw_effective = 1484 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1485 struct fixed31_32 timing_bw = 1486 dc_fixpt_from_int( 1487 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1488 dc_link_get_highest_encoding_format(link))); 1489 struct fixed31_32 avg_time_slots_per_mtp = 1490 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1491 1492 return avg_time_slots_per_mtp; 1493 } 1494 1495 1496 static bool write_128b_132b_sst_payload_allocation_table( 1497 const struct dc_stream_state *stream, 1498 struct dc_link *link, 1499 struct link_mst_stream_allocation_table *proposed_table, 1500 bool allocate) 1501 { 1502 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1503 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1504 bool result = false; 1505 uint8_t req_slot_count = 0; 1506 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1507 union payload_table_update_status update_status = { 0 }; 1508 const uint32_t max_retries = 30; 1509 uint32_t retries = 0; 1510 DC_LOGGER_INIT(link->ctx->logger); 1511 1512 if (allocate) { 1513 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1514 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1515 /// Validation should filter out modes that exceed link BW 1516 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1517 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1518 return false; 1519 } else { 1520 /// Leave req_slot_count = 0 if allocate is false. 1521 } 1522 1523 proposed_table->stream_count = 1; /// Always 1 stream for SST 1524 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1525 proposed_table->stream_allocations[0].vcp_id = vc_id; 1526 1527 if (link->aux_access_disabled) 1528 return true; 1529 1530 /// Write DPCD 2C0 = 1 to start updating 1531 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1532 core_link_write_dpcd( 1533 link, 1534 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1535 &update_status.raw, 1536 1); 1537 1538 /// Program the changes in DPCD 1C0 - 1C2 1539 ASSERT(vc_id == 1); 1540 core_link_write_dpcd( 1541 link, 1542 DP_PAYLOAD_ALLOCATE_SET, 1543 &vc_id, 1544 1); 1545 1546 ASSERT(start_time_slot == 0); 1547 core_link_write_dpcd( 1548 link, 1549 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1550 &start_time_slot, 1551 1); 1552 1553 core_link_write_dpcd( 1554 link, 1555 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1556 &req_slot_count, 1557 1); 1558 1559 /// Poll till DPCD 2C0 read 1 1560 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1561 1562 while (retries < max_retries) { 1563 if (core_link_read_dpcd( 1564 link, 1565 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1566 &update_status.raw, 1567 1) == DC_OK) { 1568 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1569 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1570 result = true; 1571 break; 1572 } 1573 } else { 1574 union dpcd_rev dpcdRev; 1575 1576 if (core_link_read_dpcd( 1577 link, 1578 DP_DPCD_REV, 1579 &dpcdRev.raw, 1580 1) != DC_OK) { 1581 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1582 "of sink while polling payload table " 1583 "updated status bit."); 1584 break; 1585 } 1586 } 1587 retries++; 1588 fsleep(5000); 1589 } 1590 1591 if (!result && retries == max_retries) { 1592 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1593 "continue on. Something is wrong with the branch."); 1594 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1595 } 1596 1597 return result; 1598 } 1599 1600 /* 1601 * Payload allocation/deallocation for SST introduced in DP2.0 1602 */ 1603 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1604 bool allocate) 1605 { 1606 struct dc_stream_state *stream = pipe_ctx->stream; 1607 struct dc_link *link = stream->link; 1608 struct link_mst_stream_allocation_table proposed_table = {0}; 1609 struct fixed31_32 avg_time_slots_per_mtp; 1610 const struct dc_link_settings empty_link_settings = {0}; 1611 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1612 DC_LOGGER_INIT(link->ctx->logger); 1613 1614 /* slot X.Y for SST payload deallocate */ 1615 if (!allocate) { 1616 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1617 1618 log_vcp_x_y(link, avg_time_slots_per_mtp); 1619 1620 if (link_hwss->ext.set_throttled_vcp_size) 1621 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1622 avg_time_slots_per_mtp); 1623 if (link_hwss->ext.set_hblank_min_symbol_width) 1624 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1625 &empty_link_settings, 1626 avg_time_slots_per_mtp); 1627 } 1628 1629 /* calculate VC payload and update branch with new payload allocation table*/ 1630 if (!write_128b_132b_sst_payload_allocation_table( 1631 stream, 1632 link, 1633 &proposed_table, 1634 allocate)) { 1635 DC_LOG_ERROR("SST Update Payload: Failed to update " 1636 "allocation table for " 1637 "pipe idx: %d\n", 1638 pipe_ctx->pipe_idx); 1639 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1640 } 1641 1642 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1643 1644 ASSERT(proposed_table.stream_count == 1); 1645 1646 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1647 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1648 "vcp_id: %d " 1649 "slot_count: %d\n", 1650 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1651 proposed_table.stream_allocations[0].vcp_id, 1652 proposed_table.stream_allocations[0].slot_count); 1653 1654 /* program DP source TX for payload */ 1655 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1656 &proposed_table); 1657 1658 /* poll for ACT handled */ 1659 if (!poll_for_allocation_change_trigger(link)) { 1660 // Failures will result in blackscreen and errors logged 1661 BREAK_TO_DEBUGGER(); 1662 } 1663 1664 /* slot X.Y for SST payload allocate */ 1665 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1666 DP_128b_132b_ENCODING) { 1667 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1668 1669 log_vcp_x_y(link, avg_time_slots_per_mtp); 1670 1671 if (link_hwss->ext.set_throttled_vcp_size) 1672 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1673 avg_time_slots_per_mtp); 1674 if (link_hwss->ext.set_hblank_min_symbol_width) 1675 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1676 &link->cur_link_settings, 1677 avg_time_slots_per_mtp); 1678 } 1679 1680 /* Always return DC_OK. 1681 * If part of sequence fails, log failure(s) and show blackscreen 1682 */ 1683 return DC_OK; 1684 } 1685 1686 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1687 { 1688 struct dc_stream_state *stream = pipe_ctx->stream; 1689 struct dc_link *link = stream->link; 1690 struct fixed31_32 avg_time_slots_per_mtp; 1691 struct fixed31_32 pbn; 1692 struct fixed31_32 pbn_per_slot; 1693 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1694 uint8_t i; 1695 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1696 DC_LOGGER_INIT(link->ctx->logger); 1697 1698 /* decrease throttled vcp size */ 1699 pbn_per_slot = get_pbn_per_slot(stream); 1700 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1701 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1702 1703 if (link_hwss->ext.set_throttled_vcp_size) 1704 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1705 if (link_hwss->ext.set_hblank_min_symbol_width) 1706 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1707 &link->cur_link_settings, 1708 avg_time_slots_per_mtp); 1709 1710 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1711 dm_helpers_dp_mst_send_payload_allocation( 1712 stream->ctx, 1713 stream); 1714 1715 /* notify immediate branch device table update */ 1716 if (dm_helpers_dp_mst_write_payload_allocation_table( 1717 stream->ctx, 1718 stream, 1719 &proposed_table, 1720 true)) { 1721 /* update mst stream allocation table software state */ 1722 update_mst_stream_alloc_table( 1723 link, 1724 pipe_ctx->stream_res.stream_enc, 1725 pipe_ctx->stream_res.hpo_dp_stream_enc, 1726 &proposed_table); 1727 } else { 1728 DC_LOG_WARNING("Failed to update" 1729 "MST allocation table for" 1730 "pipe idx:%d\n", 1731 pipe_ctx->pipe_idx); 1732 } 1733 1734 DC_LOG_MST("%s " 1735 "stream_count: %d: \n ", 1736 __func__, 1737 link->mst_stream_alloc_table.stream_count); 1738 1739 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1740 DC_LOG_MST("stream_enc[%d]: %p " 1741 "stream[%d].hpo_dp_stream_enc: %p " 1742 "stream[%d].vcp_id: %d " 1743 "stream[%d].slot_count: %d\n", 1744 i, 1745 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1746 i, 1747 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1748 i, 1749 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1750 i, 1751 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1752 } 1753 1754 ASSERT(proposed_table.stream_count > 0); 1755 1756 /* update mst stream allocation table hardware state */ 1757 if (link_hwss->ext.update_stream_allocation_table == NULL || 1758 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1759 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1760 return DC_ERROR_UNEXPECTED; 1761 } 1762 1763 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1764 &link->mst_stream_alloc_table); 1765 1766 /* poll for immediate branch device ACT handled */ 1767 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1768 stream->ctx, 1769 stream); 1770 1771 return DC_OK; 1772 } 1773 1774 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1775 { 1776 struct dc_stream_state *stream = pipe_ctx->stream; 1777 struct dc_link *link = stream->link; 1778 struct fixed31_32 avg_time_slots_per_mtp; 1779 struct fixed31_32 pbn; 1780 struct fixed31_32 pbn_per_slot; 1781 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1782 uint8_t i; 1783 enum act_return_status ret; 1784 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1785 DC_LOGGER_INIT(link->ctx->logger); 1786 1787 /* notify immediate branch device table update */ 1788 if (dm_helpers_dp_mst_write_payload_allocation_table( 1789 stream->ctx, 1790 stream, 1791 &proposed_table, 1792 true)) { 1793 /* update mst stream allocation table software state */ 1794 update_mst_stream_alloc_table( 1795 link, 1796 pipe_ctx->stream_res.stream_enc, 1797 pipe_ctx->stream_res.hpo_dp_stream_enc, 1798 &proposed_table); 1799 } 1800 1801 DC_LOG_MST("%s " 1802 "stream_count: %d: \n ", 1803 __func__, 1804 link->mst_stream_alloc_table.stream_count); 1805 1806 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1807 DC_LOG_MST("stream_enc[%d]: %p " 1808 "stream[%d].hpo_dp_stream_enc: %p " 1809 "stream[%d].vcp_id: %d " 1810 "stream[%d].slot_count: %d\n", 1811 i, 1812 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1813 i, 1814 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1815 i, 1816 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1817 i, 1818 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1819 } 1820 1821 ASSERT(proposed_table.stream_count > 0); 1822 1823 /* update mst stream allocation table hardware state */ 1824 if (link_hwss->ext.update_stream_allocation_table == NULL || 1825 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1826 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1827 return DC_ERROR_UNEXPECTED; 1828 } 1829 1830 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1831 &link->mst_stream_alloc_table); 1832 1833 /* poll for immediate branch device ACT handled */ 1834 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1835 stream->ctx, 1836 stream); 1837 1838 if (ret != ACT_LINK_LOST) { 1839 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1840 dm_helpers_dp_mst_send_payload_allocation( 1841 stream->ctx, 1842 stream); 1843 } 1844 1845 /* increase throttled vcp size */ 1846 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1847 pbn_per_slot = get_pbn_per_slot(stream); 1848 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1849 1850 if (link_hwss->ext.set_throttled_vcp_size) 1851 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1852 if (link_hwss->ext.set_hblank_min_symbol_width) 1853 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1854 &link->cur_link_settings, 1855 avg_time_slots_per_mtp); 1856 1857 return DC_OK; 1858 } 1859 1860 static void disable_link_dp(struct dc_link *link, 1861 const struct link_resource *link_res, 1862 enum signal_type signal) 1863 { 1864 struct dc_link_settings link_settings = link->cur_link_settings; 1865 1866 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1867 link->mst_stream_alloc_table.stream_count > 0) 1868 /* disable MST link only when last vc payload is deallocated */ 1869 return; 1870 1871 dp_disable_link_phy(link, link_res, signal); 1872 1873 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1874 if (!link->skip_implict_edp_power_control) 1875 link->dc->hwss.edp_power_control(link, false); 1876 } 1877 1878 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1879 /* set the sink to SST mode after disabling the link */ 1880 enable_mst_on_sink(link, false); 1881 1882 if (link_dp_get_encoding_format(&link_settings) == 1883 DP_8b_10b_ENCODING) { 1884 dp_set_fec_enable(link, false); 1885 dp_set_fec_ready(link, link_res, false); 1886 } 1887 } 1888 1889 static void disable_link(struct dc_link *link, 1890 const struct link_resource *link_res, 1891 enum signal_type signal) 1892 { 1893 if (dc_is_dp_signal(signal)) { 1894 disable_link_dp(link, link_res, signal); 1895 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1896 link->dc->hwss.disable_link_output(link, link_res, signal); 1897 } 1898 1899 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1900 /* MST disable link only when no stream use the link */ 1901 if (link->mst_stream_alloc_table.stream_count <= 0) 1902 link->link_status.link_active = false; 1903 } else { 1904 link->link_status.link_active = false; 1905 } 1906 } 1907 1908 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1909 { 1910 struct dc_stream_state *stream = pipe_ctx->stream; 1911 struct dc_link *link = stream->link; 1912 enum dc_color_depth display_color_depth; 1913 enum engine_id eng_id; 1914 struct ext_hdmi_settings settings = {0}; 1915 bool is_over_340mhz = false; 1916 bool is_vga_mode = (stream->timing.h_addressable == 640) 1917 && (stream->timing.v_addressable == 480); 1918 struct dc *dc = pipe_ctx->stream->ctx->dc; 1919 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1920 1921 if (stream->phy_pix_clk == 0) 1922 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1923 if (stream->phy_pix_clk > 340000) 1924 is_over_340mhz = true; 1925 1926 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1927 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1928 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1929 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1930 /* DP159, Retimer settings */ 1931 eng_id = pipe_ctx->stream_res.stream_enc->id; 1932 1933 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1934 write_i2c_retimer_setting(pipe_ctx, 1935 is_vga_mode, is_over_340mhz, &settings); 1936 } else { 1937 write_i2c_default_retimer_setting(pipe_ctx, 1938 is_vga_mode, is_over_340mhz); 1939 } 1940 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1941 /* PI3EQX1204, Redriver settings */ 1942 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1943 } 1944 } 1945 1946 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1947 write_scdc_data( 1948 stream->link->ddc, 1949 stream->phy_pix_clk, 1950 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 1951 1952 memset(&stream->link->cur_link_settings, 0, 1953 sizeof(struct dc_link_settings)); 1954 1955 display_color_depth = stream->timing.display_color_depth; 1956 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1957 display_color_depth = COLOR_DEPTH_888; 1958 1959 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 1960 * character clock in case that beyond 340MHz. 1961 */ 1962 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 1963 link_hwss->setup_stream_encoder(pipe_ctx); 1964 1965 dc->hwss.enable_tmds_link_output( 1966 link, 1967 &pipe_ctx->link_res, 1968 pipe_ctx->stream->signal, 1969 pipe_ctx->clock_source->id, 1970 display_color_depth, 1971 stream->phy_pix_clk); 1972 1973 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1974 read_scdc_data(link->ddc); 1975 } 1976 1977 static enum dc_status enable_link_dp(struct dc_state *state, 1978 struct pipe_ctx *pipe_ctx) 1979 { 1980 struct dc_stream_state *stream = pipe_ctx->stream; 1981 enum dc_status status; 1982 bool skip_video_pattern; 1983 struct dc_link *link = stream->link; 1984 const struct dc_link_settings *link_settings = 1985 &pipe_ctx->link_config.dp_link_settings; 1986 bool fec_enable; 1987 int i; 1988 bool apply_seamless_boot_optimization = false; 1989 uint32_t bl_oled_enable_delay = 50; // in ms 1990 uint32_t post_oui_delay = 30; // 30ms 1991 /* Reduce link bandwidth between failed link training attempts. */ 1992 bool do_fallback = false; 1993 int lt_attempts = LINK_TRAINING_ATTEMPTS; 1994 1995 // Increase retry count if attempting DP1.x on FIXED_VS link 1996 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 1997 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 1998 lt_attempts = 10; 1999 2000 // check for seamless boot 2001 for (i = 0; i < state->stream_count; i++) { 2002 if (state->streams[i]->apply_seamless_boot_optimization) { 2003 apply_seamless_boot_optimization = true; 2004 break; 2005 } 2006 } 2007 2008 /* 2009 * If the link is DP-over-USB4 do the following: 2010 * - Train with fallback when enabling DPIA link. Conventional links are 2011 * trained with fallback during sink detection. 2012 * - Allocate only what the stream needs for bw in Gbps. Inform the CM 2013 * in case stream needs more or less bw from what has been allocated 2014 * earlier at plug time. 2015 */ 2016 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 2017 do_fallback = true; 2018 } 2019 2020 /* 2021 * Temporary w/a to get DP2.0 link rates to work with SST. 2022 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2023 */ 2024 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2025 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2026 link->dc->debug.set_mst_en_for_sst) { 2027 enable_mst_on_sink(link, true); 2028 } 2029 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2030 /*in case it is not on*/ 2031 if (!link->dc->config.edp_no_power_sequencing) 2032 link->dc->hwss.edp_power_control(link, true); 2033 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2034 } 2035 2036 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2037 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2038 } else { 2039 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2040 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2041 if (state->clk_mgr && !apply_seamless_boot_optimization) 2042 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2043 state, false); 2044 } 2045 2046 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2047 dpcd_set_source_specific_data(link); 2048 if (link->dpcd_sink_ext_caps.raw != 0) { 2049 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2050 msleep(post_oui_delay); 2051 } 2052 2053 // similarly, mode switch can cause loss of cable ID 2054 dpcd_write_cable_id_to_dprx(link); 2055 2056 skip_video_pattern = true; 2057 2058 if (link_settings->link_rate == LINK_RATE_LOW) 2059 skip_video_pattern = false; 2060 2061 if (perform_link_training_with_retries(link_settings, 2062 skip_video_pattern, 2063 lt_attempts, 2064 pipe_ctx, 2065 pipe_ctx->stream->signal, 2066 do_fallback)) { 2067 status = DC_OK; 2068 } else { 2069 status = DC_FAIL_DP_LINK_TRAINING; 2070 } 2071 2072 if (link->preferred_training_settings.fec_enable) 2073 fec_enable = *link->preferred_training_settings.fec_enable; 2074 else 2075 fec_enable = true; 2076 2077 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2078 dp_set_fec_enable(link, fec_enable); 2079 2080 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2081 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2082 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2083 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2084 set_default_brightness_aux(link); 2085 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2086 msleep(bl_oled_enable_delay); 2087 edp_backlight_enable_aux(link, true); 2088 } 2089 2090 return status; 2091 } 2092 2093 static enum dc_status enable_link_edp( 2094 struct dc_state *state, 2095 struct pipe_ctx *pipe_ctx) 2096 { 2097 return enable_link_dp(state, pipe_ctx); 2098 } 2099 2100 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2101 { 2102 struct dc_stream_state *stream = pipe_ctx->stream; 2103 struct dc_link *link = stream->link; 2104 struct dc *dc = stream->ctx->dc; 2105 2106 if (stream->phy_pix_clk == 0) 2107 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2108 2109 memset(&stream->link->cur_link_settings, 0, 2110 sizeof(struct dc_link_settings)); 2111 dc->hwss.enable_lvds_link_output( 2112 link, 2113 &pipe_ctx->link_res, 2114 pipe_ctx->clock_source->id, 2115 stream->phy_pix_clk); 2116 2117 } 2118 2119 static enum dc_status enable_link_dp_mst( 2120 struct dc_state *state, 2121 struct pipe_ctx *pipe_ctx) 2122 { 2123 struct dc_link *link = pipe_ctx->stream->link; 2124 unsigned char mstm_cntl; 2125 2126 /* sink signal type after MST branch is MST. Multiple MST sinks 2127 * share one link. Link DP PHY is enable or training only once. 2128 */ 2129 if (link->link_status.link_active) 2130 return DC_OK; 2131 2132 /* clear payload table */ 2133 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2134 if (mstm_cntl & DP_MST_EN) 2135 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2136 2137 /* to make sure the pending down rep can be processed 2138 * before enabling the link 2139 */ 2140 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2141 2142 /* set the sink to MST mode before enabling the link */ 2143 enable_mst_on_sink(link, true); 2144 2145 return enable_link_dp(state, pipe_ctx); 2146 } 2147 2148 static enum dc_status enable_link( 2149 struct dc_state *state, 2150 struct pipe_ctx *pipe_ctx) 2151 { 2152 enum dc_status status = DC_ERROR_UNEXPECTED; 2153 struct dc_stream_state *stream = pipe_ctx->stream; 2154 struct dc_link *link = stream->link; 2155 2156 /* There's some scenarios where driver is unloaded with display 2157 * still enabled. When driver is reloaded, it may cause a display 2158 * to not light up if there is a mismatch between old and new 2159 * link settings. Need to call disable first before enabling at 2160 * new link settings. 2161 */ 2162 if (link->link_status.link_active) 2163 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2164 2165 switch (pipe_ctx->stream->signal) { 2166 case SIGNAL_TYPE_DISPLAY_PORT: 2167 status = enable_link_dp(state, pipe_ctx); 2168 break; 2169 case SIGNAL_TYPE_EDP: 2170 status = enable_link_edp(state, pipe_ctx); 2171 break; 2172 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2173 status = enable_link_dp_mst(state, pipe_ctx); 2174 msleep(200); 2175 break; 2176 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2177 case SIGNAL_TYPE_DVI_DUAL_LINK: 2178 case SIGNAL_TYPE_HDMI_TYPE_A: 2179 enable_link_hdmi(pipe_ctx); 2180 status = DC_OK; 2181 break; 2182 case SIGNAL_TYPE_LVDS: 2183 enable_link_lvds(pipe_ctx); 2184 status = DC_OK; 2185 break; 2186 case SIGNAL_TYPE_VIRTUAL: 2187 status = DC_OK; 2188 break; 2189 default: 2190 break; 2191 } 2192 2193 if (status == DC_OK) { 2194 pipe_ctx->stream->link->link_status.link_active = true; 2195 } 2196 2197 return status; 2198 } 2199 2200 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2201 { 2202 struct dc *dc = pipe_ctx->stream->ctx->dc; 2203 struct dc_stream_state *stream = pipe_ctx->stream; 2204 struct dc_link *link = stream->sink->link; 2205 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2206 2207 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2208 2209 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2210 2211 if (dp_is_128b_132b_signal(pipe_ctx)) 2212 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2213 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2214 return; 2215 2216 if (pipe_ctx->stream->sink) { 2217 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2218 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2219 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2220 pipe_ctx->stream->sink->edid_caps.display_name, 2221 pipe_ctx->stream->signal); 2222 } 2223 } 2224 2225 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2226 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2227 set_avmute(pipe_ctx, true); 2228 } 2229 2230 dc->hwss.disable_audio_stream(pipe_ctx); 2231 2232 update_psp_stream_config(pipe_ctx, true); 2233 dc->hwss.blank_stream(pipe_ctx); 2234 2235 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2236 deallocate_mst_payload(pipe_ctx); 2237 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2238 dp_is_128b_132b_signal(pipe_ctx)) 2239 update_sst_payload(pipe_ctx, false); 2240 2241 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2242 struct ext_hdmi_settings settings = {0}; 2243 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2244 2245 unsigned short masked_chip_caps = link->chip_caps & 2246 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2247 //Need to inform that sink is going to use legacy HDMI mode. 2248 write_scdc_data( 2249 link->ddc, 2250 165000,//vbios only handles 165Mhz. 2251 false); 2252 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2253 /* DP159, Retimer settings */ 2254 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2255 write_i2c_retimer_setting(pipe_ctx, 2256 false, false, &settings); 2257 else 2258 write_i2c_default_retimer_setting(pipe_ctx, 2259 false, false); 2260 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2261 /* PI3EQX1204, Redriver settings */ 2262 write_i2c_redriver_setting(pipe_ctx, false); 2263 } 2264 } 2265 2266 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2267 !dp_is_128b_132b_signal(pipe_ctx)) { 2268 2269 /* In DP1.x SST mode, our encoder will go to TPS1 2270 * when link is on but stream is off. 2271 * Disabling link before stream will avoid exposing TPS1 pattern 2272 * during the disable sequence as it will confuse some receivers 2273 * state machine. 2274 * In DP2 or MST mode, our encoder will stay video active 2275 */ 2276 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2277 dc->hwss.disable_stream(pipe_ctx); 2278 } else { 2279 dc->hwss.disable_stream(pipe_ctx); 2280 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2281 } 2282 2283 if (pipe_ctx->stream->timing.flags.DSC) { 2284 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2285 link_set_dsc_enable(pipe_ctx, false); 2286 } 2287 if (dp_is_128b_132b_signal(pipe_ctx)) { 2288 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2289 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2290 } 2291 2292 if (vpg && vpg->funcs->vpg_powerdown) 2293 vpg->funcs->vpg_powerdown(vpg); 2294 2295 /* for psp not exist case */ 2296 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2297 /* reset internal save state to default since eDP is off */ 2298 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2299 /* since current psp not loaded, we need to reset it to default*/ 2300 link->panel_mode = panel_mode; 2301 } 2302 } 2303 2304 void link_set_dpms_on( 2305 struct dc_state *state, 2306 struct pipe_ctx *pipe_ctx) 2307 { 2308 struct dc *dc = pipe_ctx->stream->ctx->dc; 2309 struct dc_stream_state *stream = pipe_ctx->stream; 2310 struct dc_link *link = stream->sink->link; 2311 enum dc_status status; 2312 struct link_encoder *link_enc; 2313 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2314 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2315 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2316 bool apply_edp_fast_boot_optimization = 2317 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2318 2319 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2320 2321 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2322 2323 if (dp_is_128b_132b_signal(pipe_ctx)) 2324 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2325 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2326 return; 2327 2328 if (pipe_ctx->stream->sink) { 2329 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2330 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2331 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2332 pipe_ctx->stream->sink->edid_caps.display_name, 2333 pipe_ctx->stream->signal); 2334 } 2335 } 2336 2337 link_enc = link_enc_cfg_get_link_enc(link); 2338 ASSERT(link_enc); 2339 2340 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2341 && !dp_is_128b_132b_signal(pipe_ctx)) { 2342 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2343 2344 if (link_enc) 2345 link_enc->funcs->setup( 2346 link_enc, 2347 pipe_ctx->stream->signal); 2348 2349 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2350 stream_enc->funcs->dig_stream_enable( 2351 stream_enc, 2352 pipe_ctx->stream->signal, 1); 2353 } 2354 2355 pipe_ctx->stream->link->link_state_valid = true; 2356 2357 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2358 if (dp_is_128b_132b_signal(pipe_ctx)) 2359 otg_out_dest = OUT_MUX_HPO_DP; 2360 else 2361 otg_out_dest = OUT_MUX_DIO; 2362 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2363 } 2364 2365 link_hwss->setup_stream_attribute(pipe_ctx); 2366 2367 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2368 2369 // Enable VPG before building infoframe 2370 if (vpg && vpg->funcs->vpg_poweron) 2371 vpg->funcs->vpg_poweron(vpg); 2372 2373 resource_build_info_frame(pipe_ctx); 2374 dc->hwss.update_info_frame(pipe_ctx); 2375 2376 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2377 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2378 2379 /* Do not touch link on seamless boot optimization. */ 2380 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2381 pipe_ctx->stream->dpms_off = false; 2382 2383 /* Still enable stream features & audio on seamless boot for DP external displays */ 2384 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2385 enable_stream_features(pipe_ctx); 2386 dc->hwss.enable_audio_stream(pipe_ctx); 2387 } 2388 2389 update_psp_stream_config(pipe_ctx, false); 2390 return; 2391 } 2392 2393 /* eDP lit up by bios already, no need to enable again. */ 2394 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2395 apply_edp_fast_boot_optimization && 2396 !pipe_ctx->stream->timing.flags.DSC && 2397 !pipe_ctx->next_odm_pipe) { 2398 pipe_ctx->stream->dpms_off = false; 2399 update_psp_stream_config(pipe_ctx, false); 2400 return; 2401 } 2402 2403 if (pipe_ctx->stream->dpms_off) 2404 return; 2405 2406 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2407 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2408 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2409 * will be automatically set at a later time when the video is enabled 2410 * (DP_VID_STREAM_EN = 1). 2411 */ 2412 if (pipe_ctx->stream->timing.flags.DSC) { 2413 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2414 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2415 link_set_dsc_enable(pipe_ctx, true); 2416 } 2417 2418 status = enable_link(state, pipe_ctx); 2419 2420 if (status != DC_OK) { 2421 DC_LOG_WARNING("enabling link %u failed: %d\n", 2422 pipe_ctx->stream->link->link_index, 2423 status); 2424 2425 /* Abort stream enable *unless* the failure was due to 2426 * DP link training - some DP monitors will recover and 2427 * show the stream anyway. But MST displays can't proceed 2428 * without link training. 2429 */ 2430 if (status != DC_FAIL_DP_LINK_TRAINING || 2431 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2432 if (false == stream->link->link_status.link_active) 2433 disable_link(stream->link, &pipe_ctx->link_res, 2434 pipe_ctx->stream->signal); 2435 BREAK_TO_DEBUGGER(); 2436 return; 2437 } 2438 } 2439 2440 /* turn off otg test pattern if enable */ 2441 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2442 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2443 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2444 COLOR_DEPTH_UNDEFINED); 2445 2446 /* This second call is needed to reconfigure the DIG 2447 * as a workaround for the incorrect value being applied 2448 * from transmitter control. 2449 */ 2450 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2451 dp_is_128b_132b_signal(pipe_ctx))) { 2452 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2453 2454 if (link_enc) 2455 link_enc->funcs->setup( 2456 link_enc, 2457 pipe_ctx->stream->signal); 2458 2459 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2460 stream_enc->funcs->dig_stream_enable( 2461 stream_enc, 2462 pipe_ctx->stream->signal, 1); 2463 2464 } 2465 2466 dc->hwss.enable_stream(pipe_ctx); 2467 2468 /* Set DPS PPS SDP (AKA "info frames") */ 2469 if (pipe_ctx->stream->timing.flags.DSC) { 2470 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2471 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2472 dp_set_dsc_on_rx(pipe_ctx, true); 2473 link_set_dsc_pps_packet(pipe_ctx, true, true); 2474 } 2475 } 2476 2477 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2478 allocate_mst_payload(pipe_ctx); 2479 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2480 dp_is_128b_132b_signal(pipe_ctx)) 2481 update_sst_payload(pipe_ctx, true); 2482 2483 dc->hwss.unblank_stream(pipe_ctx, 2484 &pipe_ctx->stream->link->cur_link_settings); 2485 2486 if (stream->sink_patches.delay_ignore_msa > 0) 2487 msleep(stream->sink_patches.delay_ignore_msa); 2488 2489 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2490 enable_stream_features(pipe_ctx); 2491 update_psp_stream_config(pipe_ctx, false); 2492 2493 dc->hwss.enable_audio_stream(pipe_ctx); 2494 2495 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2496 set_avmute(pipe_ctx, false); 2497 } 2498 } 2499