1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_fpga.h" 42 #include "accessories/link_dp_trace.h" 43 #include "protocols/link_dpcd.h" 44 #include "protocols/link_ddc.h" 45 #include "protocols/link_hpd.h" 46 #include "protocols/link_dp_phy.h" 47 #include "protocols/link_dp_capability.h" 48 #include "protocols/link_dp_training.h" 49 #include "protocols/link_edp_panel_control.h" 50 #include "protocols/link_dp_dpia_bw.h" 51 52 #include "dm_helpers.h" 53 #include "link_enc_cfg.h" 54 #include "resource.h" 55 #include "dsc.h" 56 #include "dccg.h" 57 #include "clk_mgr.h" 58 #include "atomfirmware.h" 59 #define DC_LOGGER_INIT(logger) 60 61 #define LINK_INFO(...) \ 62 DC_LOG_HW_HOTPLUG( \ 63 __VA_ARGS__) 64 65 #define RETIMER_REDRIVER_INFO(...) \ 66 DC_LOG_RETIMER_REDRIVER( \ 67 __VA_ARGS__) 68 #include "dc/dcn30/dcn30_vpg.h" 69 70 #define MAX_MTP_SLOT_COUNT 64 71 #define LINK_TRAINING_ATTEMPTS 4 72 #define PEAK_FACTOR_X1000 1006 73 74 void link_blank_all_dp_displays(struct dc *dc) 75 { 76 unsigned int i; 77 uint8_t dpcd_power_state = '\0'; 78 enum dc_status status = DC_ERROR_UNEXPECTED; 79 80 for (i = 0; i < dc->link_count; i++) { 81 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 82 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 83 continue; 84 85 /* DP 2.0 spec requires that we read LTTPR caps first */ 86 dp_retrieve_lttpr_cap(dc->links[i]); 87 /* if any of the displays are lit up turn them off */ 88 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 89 &dpcd_power_state, sizeof(dpcd_power_state)); 90 91 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 92 link_blank_dp_stream(dc->links[i], true); 93 } 94 95 } 96 97 void link_blank_all_edp_displays(struct dc *dc) 98 { 99 unsigned int i; 100 uint8_t dpcd_power_state = '\0'; 101 enum dc_status status = DC_ERROR_UNEXPECTED; 102 103 for (i = 0; i < dc->link_count; i++) { 104 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 105 (!dc->links[i]->edp_sink_present)) 106 continue; 107 108 /* if any of the displays are lit up turn them off */ 109 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 110 &dpcd_power_state, sizeof(dpcd_power_state)); 111 112 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 113 link_blank_dp_stream(dc->links[i], true); 114 } 115 } 116 117 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 118 { 119 unsigned int j; 120 struct dc *dc = link->ctx->dc; 121 enum signal_type signal = link->connector_signal; 122 123 if ((signal == SIGNAL_TYPE_EDP) || 124 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 125 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 126 link->link_enc->funcs->get_dig_frontend && 127 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 128 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 129 130 if (fe != ENGINE_ID_UNKNOWN) 131 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 132 if (fe == dc->res_pool->stream_enc[j]->id) { 133 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 134 dc->res_pool->stream_enc[j]); 135 break; 136 } 137 } 138 } 139 140 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 141 dpcd_write_rx_power_ctrl(link, false); 142 } 143 } 144 145 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 146 { 147 struct pipe_ctx *pipes[MAX_PIPES]; 148 struct dc_state *state = link->dc->current_state; 149 uint8_t count; 150 int i; 151 struct dc_stream_update stream_update; 152 bool dpms_off = true; 153 struct link_resource link_res = {0}; 154 155 memset(&stream_update, 0, sizeof(stream_update)); 156 stream_update.dpms_off = &dpms_off; 157 158 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 159 160 for (i = 0; i < count; i++) { 161 stream_update.stream = pipes[i]->stream; 162 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 163 pipes[i]->stream, &stream_update, 164 state); 165 } 166 167 /* link can be also enabled by vbios. In this case it is not recorded 168 * in pipe_ctx. Disable link phy here to make sure it is completely off 169 */ 170 dp_disable_link_phy(link, &link_res, link->connector_signal); 171 } 172 173 void link_resume(struct dc_link *link) 174 { 175 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 176 program_hpd_filter(link); 177 } 178 179 /* This function returns true if the pipe is used to feed video signal directly 180 * to the link. 181 */ 182 static bool is_master_pipe_for_link(const struct dc_link *link, 183 const struct pipe_ctx *pipe) 184 { 185 return resource_is_pipe_type(pipe, OTG_MASTER) && 186 pipe->stream->link == link; 187 } 188 189 /* 190 * This function finds all master pipes feeding to a given link with dpms set to 191 * on in given dc state. 192 */ 193 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 194 struct dc_state *state, 195 uint8_t *count, 196 struct pipe_ctx *pipes[MAX_PIPES]) 197 { 198 int i; 199 struct pipe_ctx *pipe = NULL; 200 201 *count = 0; 202 for (i = 0; i < MAX_PIPES; i++) { 203 pipe = &state->res_ctx.pipe_ctx[i]; 204 205 if (is_master_pipe_for_link(link, pipe) && 206 pipe->stream->dpms_off == false) { 207 pipes[(*count)++] = pipe; 208 } 209 } 210 } 211 212 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 213 enum engine_id eng_id, 214 struct ext_hdmi_settings *settings) 215 { 216 bool result = false; 217 int i = 0; 218 struct integrated_info *integrated_info = 219 pipe_ctx->stream->ctx->dc_bios->integrated_info; 220 221 if (integrated_info == NULL) 222 return false; 223 224 /* 225 * Get retimer settings from sbios for passing SI eye test for DCE11 226 * The setting values are varied based on board revision and port id 227 * Therefore the setting values of each ports is passed by sbios. 228 */ 229 230 // Check if current bios contains ext Hdmi settings 231 if (integrated_info->gpu_cap_info & 0x20) { 232 switch (eng_id) { 233 case ENGINE_ID_DIGA: 234 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 235 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 236 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 237 memmove(settings->reg_settings, 238 integrated_info->dp0_ext_hdmi_reg_settings, 239 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 240 memmove(settings->reg_settings_6g, 241 integrated_info->dp0_ext_hdmi_6g_reg_settings, 242 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 243 result = true; 244 break; 245 case ENGINE_ID_DIGB: 246 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 247 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 248 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 249 memmove(settings->reg_settings, 250 integrated_info->dp1_ext_hdmi_reg_settings, 251 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 252 memmove(settings->reg_settings_6g, 253 integrated_info->dp1_ext_hdmi_6g_reg_settings, 254 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 255 result = true; 256 break; 257 case ENGINE_ID_DIGC: 258 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 259 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 260 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 261 memmove(settings->reg_settings, 262 integrated_info->dp2_ext_hdmi_reg_settings, 263 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 264 memmove(settings->reg_settings_6g, 265 integrated_info->dp2_ext_hdmi_6g_reg_settings, 266 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 267 result = true; 268 break; 269 case ENGINE_ID_DIGD: 270 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 271 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 272 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 273 memmove(settings->reg_settings, 274 integrated_info->dp3_ext_hdmi_reg_settings, 275 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 276 memmove(settings->reg_settings_6g, 277 integrated_info->dp3_ext_hdmi_6g_reg_settings, 278 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 279 result = true; 280 break; 281 default: 282 break; 283 } 284 285 if (result == true) { 286 // Validate settings from bios integrated info table 287 if (settings->slv_addr == 0) 288 return false; 289 if (settings->reg_num > 9) 290 return false; 291 if (settings->reg_num_6g > 3) 292 return false; 293 294 for (i = 0; i < settings->reg_num; i++) { 295 if (settings->reg_settings[i].i2c_reg_index > 0x20) 296 return false; 297 } 298 299 for (i = 0; i < settings->reg_num_6g; i++) { 300 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 301 return false; 302 } 303 } 304 } 305 306 return result; 307 } 308 309 static bool write_i2c(struct pipe_ctx *pipe_ctx, 310 uint8_t address, uint8_t *buffer, uint32_t length) 311 { 312 struct i2c_command cmd = {0}; 313 struct i2c_payload payload = {0}; 314 315 memset(&payload, 0, sizeof(payload)); 316 memset(&cmd, 0, sizeof(cmd)); 317 318 cmd.number_of_payloads = 1; 319 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 320 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 321 322 payload.address = address; 323 payload.data = buffer; 324 payload.length = length; 325 payload.write = true; 326 cmd.payloads = &payload; 327 328 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 329 pipe_ctx->stream->link, &cmd)) 330 return true; 331 332 return false; 333 } 334 335 static void write_i2c_retimer_setting( 336 struct pipe_ctx *pipe_ctx, 337 bool is_vga_mode, 338 bool is_over_340mhz, 339 struct ext_hdmi_settings *settings) 340 { 341 uint8_t slave_address = (settings->slv_addr >> 1); 342 uint8_t buffer[2]; 343 const uint8_t apply_rx_tx_change = 0x4; 344 uint8_t offset = 0xA; 345 uint8_t value = 0; 346 int i = 0; 347 bool i2c_success = false; 348 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 349 350 memset(&buffer, 0, sizeof(buffer)); 351 352 /* Start Ext-Hdmi programming*/ 353 354 for (i = 0; i < settings->reg_num; i++) { 355 /* Apply 3G settings */ 356 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 357 358 buffer[0] = settings->reg_settings[i].i2c_reg_index; 359 buffer[1] = settings->reg_settings[i].i2c_reg_val; 360 i2c_success = write_i2c(pipe_ctx, slave_address, 361 buffer, sizeof(buffer)); 362 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 363 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 364 slave_address, buffer[0], buffer[1], i2c_success?1:0); 365 366 if (!i2c_success) 367 goto i2c_write_fail; 368 369 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 370 * needs to be set to 1 on every 0xA-0xC write. 371 */ 372 if (settings->reg_settings[i].i2c_reg_index == 0xA || 373 settings->reg_settings[i].i2c_reg_index == 0xB || 374 settings->reg_settings[i].i2c_reg_index == 0xC) { 375 376 /* Query current value from offset 0xA */ 377 if (settings->reg_settings[i].i2c_reg_index == 0xA) 378 value = settings->reg_settings[i].i2c_reg_val; 379 else { 380 i2c_success = 381 link_query_ddc_data( 382 pipe_ctx->stream->link->ddc, 383 slave_address, &offset, 1, &value, 1); 384 if (!i2c_success) 385 goto i2c_write_fail; 386 } 387 388 buffer[0] = offset; 389 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 390 buffer[1] = value | apply_rx_tx_change; 391 i2c_success = write_i2c(pipe_ctx, slave_address, 392 buffer, sizeof(buffer)); 393 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 394 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 395 slave_address, buffer[0], buffer[1], i2c_success?1:0); 396 if (!i2c_success) 397 goto i2c_write_fail; 398 } 399 } 400 } 401 402 /* Apply 3G settings */ 403 if (is_over_340mhz) { 404 for (i = 0; i < settings->reg_num_6g; i++) { 405 /* Apply 3G settings */ 406 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 407 408 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 409 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 410 i2c_success = write_i2c(pipe_ctx, slave_address, 411 buffer, sizeof(buffer)); 412 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 413 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 414 slave_address, buffer[0], buffer[1], i2c_success?1:0); 415 416 if (!i2c_success) 417 goto i2c_write_fail; 418 419 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 420 * needs to be set to 1 on every 0xA-0xC write. 421 */ 422 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 423 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 424 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 425 426 /* Query current value from offset 0xA */ 427 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 428 value = settings->reg_settings_6g[i].i2c_reg_val; 429 else { 430 i2c_success = 431 link_query_ddc_data( 432 pipe_ctx->stream->link->ddc, 433 slave_address, &offset, 1, &value, 1); 434 if (!i2c_success) 435 goto i2c_write_fail; 436 } 437 438 buffer[0] = offset; 439 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 440 buffer[1] = value | apply_rx_tx_change; 441 i2c_success = write_i2c(pipe_ctx, slave_address, 442 buffer, sizeof(buffer)); 443 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 444 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 445 slave_address, buffer[0], buffer[1], i2c_success?1:0); 446 if (!i2c_success) 447 goto i2c_write_fail; 448 } 449 } 450 } 451 } 452 453 if (is_vga_mode) { 454 /* Program additional settings if using 640x480 resolution */ 455 456 /* Write offset 0xFF to 0x01 */ 457 buffer[0] = 0xff; 458 buffer[1] = 0x01; 459 i2c_success = write_i2c(pipe_ctx, slave_address, 460 buffer, sizeof(buffer)); 461 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 462 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 463 slave_address, buffer[0], buffer[1], i2c_success?1:0); 464 if (!i2c_success) 465 goto i2c_write_fail; 466 467 /* Write offset 0x00 to 0x23 */ 468 buffer[0] = 0x00; 469 buffer[1] = 0x23; 470 i2c_success = write_i2c(pipe_ctx, slave_address, 471 buffer, sizeof(buffer)); 472 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 473 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 474 slave_address, buffer[0], buffer[1], i2c_success?1:0); 475 if (!i2c_success) 476 goto i2c_write_fail; 477 478 /* Write offset 0xff to 0x00 */ 479 buffer[0] = 0xff; 480 buffer[1] = 0x00; 481 i2c_success = write_i2c(pipe_ctx, slave_address, 482 buffer, sizeof(buffer)); 483 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 484 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 485 slave_address, buffer[0], buffer[1], i2c_success?1:0); 486 if (!i2c_success) 487 goto i2c_write_fail; 488 489 } 490 491 return; 492 493 i2c_write_fail: 494 DC_LOG_DEBUG("Set retimer failed"); 495 } 496 497 static void write_i2c_default_retimer_setting( 498 struct pipe_ctx *pipe_ctx, 499 bool is_vga_mode, 500 bool is_over_340mhz) 501 { 502 uint8_t slave_address = (0xBA >> 1); 503 uint8_t buffer[2]; 504 bool i2c_success = false; 505 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 506 507 memset(&buffer, 0, sizeof(buffer)); 508 509 /* Program Slave Address for tuning single integrity */ 510 /* Write offset 0x0A to 0x13 */ 511 buffer[0] = 0x0A; 512 buffer[1] = 0x13; 513 i2c_success = write_i2c(pipe_ctx, slave_address, 514 buffer, sizeof(buffer)); 515 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 516 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 517 slave_address, buffer[0], buffer[1], i2c_success?1:0); 518 if (!i2c_success) 519 goto i2c_write_fail; 520 521 /* Write offset 0x0A to 0x17 */ 522 buffer[0] = 0x0A; 523 buffer[1] = 0x17; 524 i2c_success = write_i2c(pipe_ctx, slave_address, 525 buffer, sizeof(buffer)); 526 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 527 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 528 slave_address, buffer[0], buffer[1], i2c_success?1:0); 529 if (!i2c_success) 530 goto i2c_write_fail; 531 532 /* Write offset 0x0B to 0xDA or 0xD8 */ 533 buffer[0] = 0x0B; 534 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 535 i2c_success = write_i2c(pipe_ctx, slave_address, 536 buffer, sizeof(buffer)); 537 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 538 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 539 slave_address, buffer[0], buffer[1], i2c_success?1:0); 540 if (!i2c_success) 541 goto i2c_write_fail; 542 543 /* Write offset 0x0A to 0x17 */ 544 buffer[0] = 0x0A; 545 buffer[1] = 0x17; 546 i2c_success = write_i2c(pipe_ctx, slave_address, 547 buffer, sizeof(buffer)); 548 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 549 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 550 slave_address, buffer[0], buffer[1], i2c_success?1:0); 551 if (!i2c_success) 552 goto i2c_write_fail; 553 554 /* Write offset 0x0C to 0x1D or 0x91 */ 555 buffer[0] = 0x0C; 556 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 557 i2c_success = write_i2c(pipe_ctx, slave_address, 558 buffer, sizeof(buffer)); 559 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 560 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 561 slave_address, buffer[0], buffer[1], i2c_success?1:0); 562 if (!i2c_success) 563 goto i2c_write_fail; 564 565 /* Write offset 0x0A to 0x17 */ 566 buffer[0] = 0x0A; 567 buffer[1] = 0x17; 568 i2c_success = write_i2c(pipe_ctx, slave_address, 569 buffer, sizeof(buffer)); 570 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 571 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 572 slave_address, buffer[0], buffer[1], i2c_success?1:0); 573 if (!i2c_success) 574 goto i2c_write_fail; 575 576 577 if (is_vga_mode) { 578 /* Program additional settings if using 640x480 resolution */ 579 580 /* Write offset 0xFF to 0x01 */ 581 buffer[0] = 0xff; 582 buffer[1] = 0x01; 583 i2c_success = write_i2c(pipe_ctx, slave_address, 584 buffer, sizeof(buffer)); 585 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 586 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 587 slave_address, buffer[0], buffer[1], i2c_success?1:0); 588 if (!i2c_success) 589 goto i2c_write_fail; 590 591 /* Write offset 0x00 to 0x23 */ 592 buffer[0] = 0x00; 593 buffer[1] = 0x23; 594 i2c_success = write_i2c(pipe_ctx, slave_address, 595 buffer, sizeof(buffer)); 596 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 597 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 598 slave_address, buffer[0], buffer[1], i2c_success?1:0); 599 if (!i2c_success) 600 goto i2c_write_fail; 601 602 /* Write offset 0xff to 0x00 */ 603 buffer[0] = 0xff; 604 buffer[1] = 0x00; 605 i2c_success = write_i2c(pipe_ctx, slave_address, 606 buffer, sizeof(buffer)); 607 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 608 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 609 slave_address, buffer[0], buffer[1], i2c_success?1:0); 610 if (!i2c_success) 611 goto i2c_write_fail; 612 } 613 614 return; 615 616 i2c_write_fail: 617 DC_LOG_DEBUG("Set default retimer failed"); 618 } 619 620 static void write_i2c_redriver_setting( 621 struct pipe_ctx *pipe_ctx, 622 bool is_over_340mhz) 623 { 624 uint8_t slave_address = (0xF0 >> 1); 625 uint8_t buffer[16]; 626 bool i2c_success = false; 627 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 628 629 memset(&buffer, 0, sizeof(buffer)); 630 631 // Program Slave Address for tuning single integrity 632 buffer[3] = 0x4E; 633 buffer[4] = 0x4E; 634 buffer[5] = 0x4E; 635 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 636 637 i2c_success = write_i2c(pipe_ctx, slave_address, 638 buffer, sizeof(buffer)); 639 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 640 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 641 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 642 i2c_success = %d\n", 643 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 644 645 if (!i2c_success) 646 DC_LOG_DEBUG("Set redriver failed"); 647 } 648 649 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 650 { 651 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 652 struct link_encoder *link_enc = NULL; 653 struct cp_psp_stream_config config = {0}; 654 enum dp_panel_mode panel_mode = 655 dp_get_panel_mode(pipe_ctx->stream->link); 656 657 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 658 return; 659 660 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 661 ASSERT(link_enc); 662 if (link_enc == NULL) 663 return; 664 665 /* otg instance */ 666 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 667 668 /* dig front end */ 669 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 670 671 /* stream encoder index */ 672 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 673 if (dp_is_128b_132b_signal(pipe_ctx)) 674 config.stream_enc_idx = 675 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 676 677 /* dig back end */ 678 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 679 680 /* link encoder index */ 681 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 682 if (dp_is_128b_132b_signal(pipe_ctx)) 683 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 684 685 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 686 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 687 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 688 else 689 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 690 691 692 /* phy index */ 693 config.phy_idx = resource_transmitter_to_phy_idx( 694 pipe_ctx->stream->link->dc, link_enc->transmitter); 695 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 696 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 697 config.phy_idx = 0; 698 699 /* stream properties */ 700 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 701 config.mst_enabled = (pipe_ctx->stream->signal == 702 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 703 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 704 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 705 1 : 0; 706 config.dpms_off = dpms_off; 707 708 /* dm stream context */ 709 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 710 711 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 712 } 713 714 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 715 { 716 struct dc *dc = pipe_ctx->stream->ctx->dc; 717 718 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 719 return; 720 721 dc->hwss.set_avmute(pipe_ctx, enable); 722 } 723 724 static void enable_mst_on_sink(struct dc_link *link, bool enable) 725 { 726 unsigned char mstmCntl; 727 728 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 729 if (enable) 730 mstmCntl |= DP_MST_EN; 731 else 732 mstmCntl &= (~DP_MST_EN); 733 734 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 735 } 736 737 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 738 struct dsc_optc_config *config) 739 { 740 uint32_t precision = 1 << 28; 741 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 742 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 743 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 744 DC_LOGGER_INIT(dsc->ctx->logger); 745 746 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 747 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 748 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 749 */ 750 ll_bytes_per_pix_fraq *= 10000000; 751 ll_bytes_per_pix_fraq /= precision; 752 753 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 754 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 755 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 756 DC_LOG_DSC("\tslice_width %d", config->slice_width); 757 } 758 759 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 760 { 761 struct dc *dc = pipe_ctx->stream->ctx->dc; 762 struct dc_stream_state *stream = pipe_ctx->stream; 763 bool result = false; 764 765 if (dc_is_virtual_signal(stream->signal)) 766 result = true; 767 else 768 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 769 return result; 770 } 771 772 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 773 * i.e. after dp_enable_dsc_on_rx() had been called 774 */ 775 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 776 { 777 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 778 struct dc_stream_state *stream = pipe_ctx->stream; 779 struct pipe_ctx *odm_pipe; 780 int opp_cnt = 1; 781 DC_LOGGER_INIT(dsc->ctx->logger); 782 783 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 784 opp_cnt++; 785 786 if (enable) { 787 struct dsc_config dsc_cfg; 788 struct dsc_optc_config dsc_optc_cfg; 789 enum optc_dsc_mode optc_dsc_mode; 790 791 /* Enable DSC hw block */ 792 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 793 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 794 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 795 dsc_cfg.color_depth = stream->timing.display_color_depth; 796 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 797 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 798 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 799 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 800 801 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 802 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 803 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 804 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 805 806 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 807 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 808 } 809 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 810 dsc_cfg.pic_width *= opp_cnt; 811 812 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 813 814 /* Enable DSC in encoder */ 815 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 816 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 817 dsc_optc_config_log(dsc, &dsc_optc_cfg); 818 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 819 optc_dsc_mode, 820 dsc_optc_cfg.bytes_per_pixel, 821 dsc_optc_cfg.slice_width); 822 823 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 824 } 825 826 /* Enable DSC in OPTC */ 827 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 828 dsc_optc_config_log(dsc, &dsc_optc_cfg); 829 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 830 optc_dsc_mode, 831 dsc_optc_cfg.bytes_per_pixel, 832 dsc_optc_cfg.slice_width); 833 } else { 834 /* disable DSC in OPTC */ 835 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 836 pipe_ctx->stream_res.tg, 837 OPTC_DSC_DISABLED, 0, 0); 838 839 /* disable DSC in stream encoder */ 840 if (dc_is_dp_signal(stream->signal)) { 841 if (dp_is_128b_132b_signal(pipe_ctx)) 842 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 843 pipe_ctx->stream_res.hpo_dp_stream_enc, 844 false, 845 NULL, 846 true); 847 else { 848 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 849 pipe_ctx->stream_res.stream_enc, 850 OPTC_DSC_DISABLED, 0, 0); 851 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 852 pipe_ctx->stream_res.stream_enc, false, NULL, true); 853 } 854 } 855 856 /* disable DSC block */ 857 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 858 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 859 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 860 } 861 } 862 863 /* 864 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 865 * hence PPS info packet update need to use frame update instead of immediate update. 866 * Added parameter immediate_update for this purpose. 867 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 868 * which is the only place where a "false" would be passed in for param immediate_update. 869 * 870 * immediate_update is only applicable when DSC is enabled. 871 */ 872 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 873 { 874 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 875 struct dc_stream_state *stream = pipe_ctx->stream; 876 DC_LOGGER_INIT(dsc->ctx->logger); 877 878 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 879 return false; 880 881 if (enable) { 882 struct dsc_config dsc_cfg; 883 uint8_t dsc_packed_pps[128]; 884 885 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 886 memset(dsc_packed_pps, 0, 128); 887 888 /* Enable DSC hw block */ 889 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 890 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 891 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 892 dsc_cfg.color_depth = stream->timing.display_color_depth; 893 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 894 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 895 896 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 897 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 898 if (dc_is_dp_signal(stream->signal)) { 899 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 900 if (dp_is_128b_132b_signal(pipe_ctx)) 901 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 902 pipe_ctx->stream_res.hpo_dp_stream_enc, 903 true, 904 &dsc_packed_pps[0], 905 immediate_update); 906 else 907 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 908 pipe_ctx->stream_res.stream_enc, 909 true, 910 &dsc_packed_pps[0], 911 immediate_update); 912 } 913 } else { 914 /* disable DSC PPS in stream encoder */ 915 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 916 if (dc_is_dp_signal(stream->signal)) { 917 if (dp_is_128b_132b_signal(pipe_ctx)) 918 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 919 pipe_ctx->stream_res.hpo_dp_stream_enc, 920 false, 921 NULL, 922 true); 923 else 924 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 925 pipe_ctx->stream_res.stream_enc, false, NULL, true); 926 } 927 } 928 929 return true; 930 } 931 932 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 933 { 934 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 935 bool result = false; 936 937 if (!pipe_ctx->stream->timing.flags.DSC) 938 goto out; 939 if (!dsc) 940 goto out; 941 942 if (enable) { 943 { 944 link_set_dsc_on_stream(pipe_ctx, true); 945 result = true; 946 } 947 } else { 948 dp_set_dsc_on_rx(pipe_ctx, false); 949 link_set_dsc_on_stream(pipe_ctx, false); 950 result = true; 951 } 952 out: 953 return result; 954 } 955 956 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 957 { 958 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 959 960 if (!pipe_ctx->stream->timing.flags.DSC) 961 return false; 962 if (!dsc) 963 return false; 964 965 link_set_dsc_on_stream(pipe_ctx, true); 966 link_set_dsc_pps_packet(pipe_ctx, true, false); 967 return true; 968 } 969 970 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 971 { 972 struct dc_stream_state *stream = pipe_ctx->stream; 973 974 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 975 struct dc_link *link = stream->link; 976 union down_spread_ctrl old_downspread; 977 union down_spread_ctrl new_downspread; 978 979 memset(&old_downspread, 0, sizeof(old_downspread)); 980 981 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 982 &old_downspread.raw, sizeof(old_downspread)); 983 984 new_downspread.raw = old_downspread.raw; 985 986 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 987 (stream->ignore_msa_timing_param) ? 1 : 0; 988 989 if (new_downspread.raw != old_downspread.raw) { 990 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 991 &new_downspread.raw, sizeof(new_downspread)); 992 } 993 994 } else { 995 dm_helpers_mst_enable_stream_features(stream); 996 } 997 } 998 999 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1000 { 1001 const uint32_t VCP_Y_PRECISION = 1000; 1002 uint64_t vcp_x, vcp_y; 1003 DC_LOGGER_INIT(link->ctx->logger); 1004 1005 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1006 avg_time_slots_per_mtp = dc_fixpt_add( 1007 avg_time_slots_per_mtp, 1008 dc_fixpt_from_fraction( 1009 1, 1010 2*VCP_Y_PRECISION)); 1011 1012 vcp_x = dc_fixpt_floor( 1013 avg_time_slots_per_mtp); 1014 vcp_y = dc_fixpt_floor( 1015 dc_fixpt_mul_int( 1016 dc_fixpt_sub_int( 1017 avg_time_slots_per_mtp, 1018 dc_fixpt_floor( 1019 avg_time_slots_per_mtp)), 1020 VCP_Y_PRECISION)); 1021 1022 1023 if (link->type == dc_connection_mst_branch) 1024 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1025 "X: %llu " 1026 "Y: %llu/%d", 1027 vcp_x, 1028 vcp_y, 1029 VCP_Y_PRECISION); 1030 else 1031 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1032 "X: %llu " 1033 "Y: %llu/%d", 1034 vcp_x, 1035 vcp_y, 1036 VCP_Y_PRECISION); 1037 } 1038 1039 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1040 { 1041 struct fixed31_32 mbytes_per_sec; 1042 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1043 &stream->link->cur_link_settings); 1044 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1045 1046 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1047 1048 return dc_fixpt_div_int(mbytes_per_sec, 54); 1049 } 1050 1051 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1052 { 1053 struct fixed31_32 peak_kbps; 1054 uint32_t numerator = 0; 1055 uint32_t denominator = 1; 1056 1057 /* 1058 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 1059 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1060 * common multiplier to render an integer PBN for all link rate/lane 1061 * counts combinations 1062 * calculate 1063 * peak_kbps *= (1006/1000) 1064 * peak_kbps *= (64/54) 1065 * peak_kbps *= 8 convert to bytes 1066 */ 1067 1068 numerator = 64 * PEAK_FACTOR_X1000; 1069 denominator = 54 * 8 * 1000 * 1000; 1070 kbps *= numerator; 1071 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1072 1073 return peak_kbps; 1074 } 1075 1076 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1077 { 1078 uint64_t kbps; 1079 enum dc_link_encoding_format link_encoding; 1080 1081 if (dp_is_128b_132b_signal(pipe_ctx)) 1082 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1083 else 1084 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1085 1086 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1087 return get_pbn_from_bw_in_kbps(kbps); 1088 } 1089 1090 1091 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1092 static void get_lane_status( 1093 struct dc_link *link, 1094 uint32_t lane_count, 1095 union lane_status *status, 1096 union lane_align_status_updated *status_updated) 1097 { 1098 unsigned int lane; 1099 uint8_t dpcd_buf[3] = {0}; 1100 1101 if (status == NULL || status_updated == NULL) { 1102 return; 1103 } 1104 1105 core_link_read_dpcd( 1106 link, 1107 DP_LANE0_1_STATUS, 1108 dpcd_buf, 1109 sizeof(dpcd_buf)); 1110 1111 for (lane = 0; lane < lane_count; lane++) { 1112 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1113 } 1114 1115 status_updated->raw = dpcd_buf[2]; 1116 } 1117 1118 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1119 { 1120 /* 1121 * wait for ACT handled 1122 */ 1123 int i; 1124 const int act_retries = 30; 1125 enum act_return_status result = ACT_FAILED; 1126 union payload_table_update_status update_status = {0}; 1127 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1128 union lane_align_status_updated lane_status_updated; 1129 DC_LOGGER_INIT(link->ctx->logger); 1130 1131 if (link->aux_access_disabled) 1132 return true; 1133 for (i = 0; i < act_retries; i++) { 1134 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1135 1136 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1137 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1138 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1139 !dp_is_interlane_aligned(lane_status_updated)) { 1140 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1141 "polling for ACT handled."); 1142 result = ACT_LINK_LOST; 1143 break; 1144 } 1145 core_link_read_dpcd( 1146 link, 1147 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1148 &update_status.raw, 1149 1); 1150 1151 if (update_status.bits.ACT_HANDLED == 1) { 1152 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1153 result = ACT_SUCCESS; 1154 break; 1155 } 1156 1157 fsleep(5000); 1158 } 1159 1160 if (result == ACT_FAILED) { 1161 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1162 "continue on. Something is wrong with the branch."); 1163 } 1164 1165 return (result == ACT_SUCCESS); 1166 } 1167 1168 static void update_mst_stream_alloc_table( 1169 struct dc_link *link, 1170 struct stream_encoder *stream_enc, 1171 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1172 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1173 { 1174 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1175 struct link_mst_stream_allocation *dc_alloc; 1176 1177 int i; 1178 int j; 1179 1180 /* if DRM proposed_table has more than one new payload */ 1181 ASSERT(proposed_table->stream_count - 1182 link->mst_stream_alloc_table.stream_count < 2); 1183 1184 /* copy proposed_table to link, add stream encoder */ 1185 for (i = 0; i < proposed_table->stream_count; i++) { 1186 1187 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1188 dc_alloc = 1189 &link->mst_stream_alloc_table.stream_allocations[j]; 1190 1191 if (dc_alloc->vcp_id == 1192 proposed_table->stream_allocations[i].vcp_id) { 1193 1194 work_table[i] = *dc_alloc; 1195 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1196 break; /* exit j loop */ 1197 } 1198 } 1199 1200 /* new vcp_id */ 1201 if (j == link->mst_stream_alloc_table.stream_count) { 1202 work_table[i].vcp_id = 1203 proposed_table->stream_allocations[i].vcp_id; 1204 work_table[i].slot_count = 1205 proposed_table->stream_allocations[i].slot_count; 1206 work_table[i].stream_enc = stream_enc; 1207 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1208 } 1209 } 1210 1211 /* update link->mst_stream_alloc_table with work_table */ 1212 link->mst_stream_alloc_table.stream_count = 1213 proposed_table->stream_count; 1214 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1215 link->mst_stream_alloc_table.stream_allocations[i] = 1216 work_table[i]; 1217 } 1218 1219 static void remove_stream_from_alloc_table( 1220 struct dc_link *link, 1221 struct stream_encoder *dio_stream_enc, 1222 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1223 { 1224 int i = 0; 1225 struct link_mst_stream_allocation_table *table = 1226 &link->mst_stream_alloc_table; 1227 1228 if (hpo_dp_stream_enc) { 1229 for (; i < table->stream_count; i++) 1230 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1231 break; 1232 } else { 1233 for (; i < table->stream_count; i++) 1234 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1235 break; 1236 } 1237 1238 if (i < table->stream_count) { 1239 i++; 1240 for (; i < table->stream_count; i++) 1241 table->stream_allocations[i-1] = table->stream_allocations[i]; 1242 memset(&table->stream_allocations[table->stream_count-1], 0, 1243 sizeof(struct link_mst_stream_allocation)); 1244 table->stream_count--; 1245 } 1246 } 1247 1248 static enum dc_status deallocate_mst_payload_with_temp_drm_wa( 1249 struct pipe_ctx *pipe_ctx) 1250 { 1251 struct dc_stream_state *stream = pipe_ctx->stream; 1252 struct dc_link *link = stream->link; 1253 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1254 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1255 int i; 1256 bool mst_mode = (link->type == dc_connection_mst_branch); 1257 /* adjust for drm changes*/ 1258 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1259 const struct dc_link_settings empty_link_settings = {0}; 1260 DC_LOGGER_INIT(link->ctx->logger); 1261 1262 if (link_hwss->ext.set_throttled_vcp_size) 1263 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1264 if (link_hwss->ext.set_hblank_min_symbol_width) 1265 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1266 &empty_link_settings, 1267 avg_time_slots_per_mtp); 1268 1269 if (dm_helpers_dp_mst_write_payload_allocation_table( 1270 stream->ctx, 1271 stream, 1272 &proposed_table, 1273 false)) 1274 update_mst_stream_alloc_table( 1275 link, 1276 pipe_ctx->stream_res.stream_enc, 1277 pipe_ctx->stream_res.hpo_dp_stream_enc, 1278 &proposed_table); 1279 else 1280 DC_LOG_WARNING("Failed to update" 1281 "MST allocation table for" 1282 "pipe idx:%d\n", 1283 pipe_ctx->pipe_idx); 1284 1285 DC_LOG_MST("%s" 1286 "stream_count: %d: ", 1287 __func__, 1288 link->mst_stream_alloc_table.stream_count); 1289 1290 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1291 DC_LOG_MST("stream_enc[%d]: %p " 1292 "stream[%d].hpo_dp_stream_enc: %p " 1293 "stream[%d].vcp_id: %d " 1294 "stream[%d].slot_count: %d\n", 1295 i, 1296 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1297 i, 1298 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1299 i, 1300 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1301 i, 1302 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1303 } 1304 1305 if (link_hwss->ext.update_stream_allocation_table == NULL || 1306 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1307 DC_LOG_DEBUG("Unknown encoding format\n"); 1308 return DC_ERROR_UNEXPECTED; 1309 } 1310 1311 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1312 &link->mst_stream_alloc_table); 1313 1314 if (mst_mode) { 1315 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1316 stream->ctx, 1317 stream); 1318 } 1319 1320 dm_helpers_dp_mst_send_payload_allocation( 1321 stream->ctx, 1322 stream, 1323 false); 1324 1325 return DC_OK; 1326 } 1327 1328 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1329 { 1330 struct dc_stream_state *stream = pipe_ctx->stream; 1331 struct dc_link *link = stream->link; 1332 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1333 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1334 int i; 1335 bool mst_mode = (link->type == dc_connection_mst_branch); 1336 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1337 const struct dc_link_settings empty_link_settings = {0}; 1338 DC_LOGGER_INIT(link->ctx->logger); 1339 1340 if (link->dc->debug.temp_mst_deallocation_sequence) 1341 return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); 1342 1343 /* deallocate_mst_payload is called before disable link. When mode or 1344 * disable/enable monitor, new stream is created which is not in link 1345 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1346 * should not done. For new mode set, map_resources will get engine 1347 * for new stream, so stream_enc->id should be validated until here. 1348 */ 1349 1350 /* slot X.Y */ 1351 if (link_hwss->ext.set_throttled_vcp_size) 1352 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1353 if (link_hwss->ext.set_hblank_min_symbol_width) 1354 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1355 &empty_link_settings, 1356 avg_time_slots_per_mtp); 1357 1358 if (mst_mode) { 1359 /* when link is in mst mode, reply on mst manager to remove 1360 * payload 1361 */ 1362 if (dm_helpers_dp_mst_write_payload_allocation_table( 1363 stream->ctx, 1364 stream, 1365 &proposed_table, 1366 false)) 1367 update_mst_stream_alloc_table( 1368 link, 1369 pipe_ctx->stream_res.stream_enc, 1370 pipe_ctx->stream_res.hpo_dp_stream_enc, 1371 &proposed_table); 1372 else 1373 DC_LOG_WARNING("Failed to update" 1374 "MST allocation table for" 1375 "pipe idx:%d\n", 1376 pipe_ctx->pipe_idx); 1377 } else { 1378 /* when link is no longer in mst mode (mst hub unplugged), 1379 * remove payload with default dc logic 1380 */ 1381 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1382 pipe_ctx->stream_res.hpo_dp_stream_enc); 1383 } 1384 1385 DC_LOG_MST("%s" 1386 "stream_count: %d: ", 1387 __func__, 1388 link->mst_stream_alloc_table.stream_count); 1389 1390 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1391 DC_LOG_MST("stream_enc[%d]: %p " 1392 "stream[%d].hpo_dp_stream_enc: %p " 1393 "stream[%d].vcp_id: %d " 1394 "stream[%d].slot_count: %d\n", 1395 i, 1396 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1397 i, 1398 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1399 i, 1400 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1401 i, 1402 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1403 } 1404 1405 /* update mst stream allocation table hardware state */ 1406 if (link_hwss->ext.update_stream_allocation_table == NULL || 1407 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1408 DC_LOG_DEBUG("Unknown encoding format\n"); 1409 return DC_ERROR_UNEXPECTED; 1410 } 1411 1412 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1413 &link->mst_stream_alloc_table); 1414 1415 if (mst_mode) { 1416 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1417 stream->ctx, 1418 stream); 1419 1420 dm_helpers_dp_mst_send_payload_allocation( 1421 stream->ctx, 1422 stream, 1423 false); 1424 } 1425 1426 return DC_OK; 1427 } 1428 1429 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1430 * because stream_encoder is not exposed to dm 1431 */ 1432 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1433 { 1434 struct dc_stream_state *stream = pipe_ctx->stream; 1435 struct dc_link *link = stream->link; 1436 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1437 struct fixed31_32 avg_time_slots_per_mtp; 1438 struct fixed31_32 pbn; 1439 struct fixed31_32 pbn_per_slot; 1440 int i; 1441 enum act_return_status ret; 1442 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1443 DC_LOGGER_INIT(link->ctx->logger); 1444 1445 /* enable_link_dp_mst already check link->enabled_stream_count 1446 * and stream is in link->stream[]. This is called during set mode, 1447 * stream_enc is available. 1448 */ 1449 1450 /* get calculate VC payload for stream: stream_alloc */ 1451 if (dm_helpers_dp_mst_write_payload_allocation_table( 1452 stream->ctx, 1453 stream, 1454 &proposed_table, 1455 true)) 1456 update_mst_stream_alloc_table( 1457 link, 1458 pipe_ctx->stream_res.stream_enc, 1459 pipe_ctx->stream_res.hpo_dp_stream_enc, 1460 &proposed_table); 1461 else 1462 DC_LOG_WARNING("Failed to update" 1463 "MST allocation table for" 1464 "pipe idx:%d\n", 1465 pipe_ctx->pipe_idx); 1466 1467 DC_LOG_MST("%s " 1468 "stream_count: %d: \n ", 1469 __func__, 1470 link->mst_stream_alloc_table.stream_count); 1471 1472 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1473 DC_LOG_MST("stream_enc[%d]: %p " 1474 "stream[%d].hpo_dp_stream_enc: %p " 1475 "stream[%d].vcp_id: %d " 1476 "stream[%d].slot_count: %d\n", 1477 i, 1478 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1479 i, 1480 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1481 i, 1482 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1483 i, 1484 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1485 } 1486 1487 ASSERT(proposed_table.stream_count > 0); 1488 1489 /* program DP source TX for payload */ 1490 if (link_hwss->ext.update_stream_allocation_table == NULL || 1491 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1492 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1493 return DC_ERROR_UNEXPECTED; 1494 } 1495 1496 link_hwss->ext.update_stream_allocation_table(link, 1497 &pipe_ctx->link_res, 1498 &link->mst_stream_alloc_table); 1499 1500 /* send down message */ 1501 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1502 stream->ctx, 1503 stream); 1504 1505 if (ret != ACT_LINK_LOST) { 1506 dm_helpers_dp_mst_send_payload_allocation( 1507 stream->ctx, 1508 stream, 1509 true); 1510 } 1511 1512 /* slot X.Y for only current stream */ 1513 pbn_per_slot = get_pbn_per_slot(stream); 1514 if (pbn_per_slot.value == 0) { 1515 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1516 return DC_UNSUPPORTED_VALUE; 1517 } 1518 pbn = get_pbn_from_timing(pipe_ctx); 1519 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1520 1521 log_vcp_x_y(link, avg_time_slots_per_mtp); 1522 1523 if (link_hwss->ext.set_throttled_vcp_size) 1524 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1525 if (link_hwss->ext.set_hblank_min_symbol_width) 1526 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1527 &link->cur_link_settings, 1528 avg_time_slots_per_mtp); 1529 1530 return DC_OK; 1531 } 1532 1533 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1534 const struct dc_stream_state *stream, 1535 const struct dc_link *link) 1536 { 1537 struct fixed31_32 link_bw_effective = 1538 dc_fixpt_from_int( 1539 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1540 struct fixed31_32 timeslot_bw_effective = 1541 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1542 struct fixed31_32 timing_bw = 1543 dc_fixpt_from_int( 1544 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1545 dc_link_get_highest_encoding_format(link))); 1546 struct fixed31_32 avg_time_slots_per_mtp = 1547 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1548 1549 return avg_time_slots_per_mtp; 1550 } 1551 1552 1553 static bool write_128b_132b_sst_payload_allocation_table( 1554 const struct dc_stream_state *stream, 1555 struct dc_link *link, 1556 struct link_mst_stream_allocation_table *proposed_table, 1557 bool allocate) 1558 { 1559 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1560 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1561 bool result = false; 1562 uint8_t req_slot_count = 0; 1563 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1564 union payload_table_update_status update_status = { 0 }; 1565 const uint32_t max_retries = 30; 1566 uint32_t retries = 0; 1567 DC_LOGGER_INIT(link->ctx->logger); 1568 1569 if (allocate) { 1570 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1571 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1572 /// Validation should filter out modes that exceed link BW 1573 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1574 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1575 return false; 1576 } else { 1577 /// Leave req_slot_count = 0 if allocate is false. 1578 } 1579 1580 proposed_table->stream_count = 1; /// Always 1 stream for SST 1581 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1582 proposed_table->stream_allocations[0].vcp_id = vc_id; 1583 1584 if (link->aux_access_disabled) 1585 return true; 1586 1587 /// Write DPCD 2C0 = 1 to start updating 1588 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1589 core_link_write_dpcd( 1590 link, 1591 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1592 &update_status.raw, 1593 1); 1594 1595 /// Program the changes in DPCD 1C0 - 1C2 1596 ASSERT(vc_id == 1); 1597 core_link_write_dpcd( 1598 link, 1599 DP_PAYLOAD_ALLOCATE_SET, 1600 &vc_id, 1601 1); 1602 1603 ASSERT(start_time_slot == 0); 1604 core_link_write_dpcd( 1605 link, 1606 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1607 &start_time_slot, 1608 1); 1609 1610 core_link_write_dpcd( 1611 link, 1612 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1613 &req_slot_count, 1614 1); 1615 1616 /// Poll till DPCD 2C0 read 1 1617 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1618 1619 while (retries < max_retries) { 1620 if (core_link_read_dpcd( 1621 link, 1622 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1623 &update_status.raw, 1624 1) == DC_OK) { 1625 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1626 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1627 result = true; 1628 break; 1629 } 1630 } else { 1631 union dpcd_rev dpcdRev; 1632 1633 if (core_link_read_dpcd( 1634 link, 1635 DP_DPCD_REV, 1636 &dpcdRev.raw, 1637 1) != DC_OK) { 1638 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1639 "of sink while polling payload table " 1640 "updated status bit."); 1641 break; 1642 } 1643 } 1644 retries++; 1645 fsleep(5000); 1646 } 1647 1648 if (!result && retries == max_retries) { 1649 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1650 "continue on. Something is wrong with the branch."); 1651 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1652 } 1653 1654 return result; 1655 } 1656 1657 /* 1658 * Payload allocation/deallocation for SST introduced in DP2.0 1659 */ 1660 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1661 bool allocate) 1662 { 1663 struct dc_stream_state *stream = pipe_ctx->stream; 1664 struct dc_link *link = stream->link; 1665 struct link_mst_stream_allocation_table proposed_table = {0}; 1666 struct fixed31_32 avg_time_slots_per_mtp; 1667 const struct dc_link_settings empty_link_settings = {0}; 1668 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1669 DC_LOGGER_INIT(link->ctx->logger); 1670 1671 /* slot X.Y for SST payload deallocate */ 1672 if (!allocate) { 1673 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1674 1675 log_vcp_x_y(link, avg_time_slots_per_mtp); 1676 1677 if (link_hwss->ext.set_throttled_vcp_size) 1678 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1679 avg_time_slots_per_mtp); 1680 if (link_hwss->ext.set_hblank_min_symbol_width) 1681 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1682 &empty_link_settings, 1683 avg_time_slots_per_mtp); 1684 } 1685 1686 /* calculate VC payload and update branch with new payload allocation table*/ 1687 if (!write_128b_132b_sst_payload_allocation_table( 1688 stream, 1689 link, 1690 &proposed_table, 1691 allocate)) { 1692 DC_LOG_ERROR("SST Update Payload: Failed to update " 1693 "allocation table for " 1694 "pipe idx: %d\n", 1695 pipe_ctx->pipe_idx); 1696 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1697 } 1698 1699 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1700 1701 ASSERT(proposed_table.stream_count == 1); 1702 1703 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1704 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1705 "vcp_id: %d " 1706 "slot_count: %d\n", 1707 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1708 proposed_table.stream_allocations[0].vcp_id, 1709 proposed_table.stream_allocations[0].slot_count); 1710 1711 /* program DP source TX for payload */ 1712 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1713 &proposed_table); 1714 1715 /* poll for ACT handled */ 1716 if (!poll_for_allocation_change_trigger(link)) { 1717 // Failures will result in blackscreen and errors logged 1718 BREAK_TO_DEBUGGER(); 1719 } 1720 1721 /* slot X.Y for SST payload allocate */ 1722 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1723 DP_128b_132b_ENCODING) { 1724 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1725 1726 log_vcp_x_y(link, avg_time_slots_per_mtp); 1727 1728 if (link_hwss->ext.set_throttled_vcp_size) 1729 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1730 avg_time_slots_per_mtp); 1731 if (link_hwss->ext.set_hblank_min_symbol_width) 1732 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1733 &link->cur_link_settings, 1734 avg_time_slots_per_mtp); 1735 } 1736 1737 /* Always return DC_OK. 1738 * If part of sequence fails, log failure(s) and show blackscreen 1739 */ 1740 return DC_OK; 1741 } 1742 1743 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1744 { 1745 struct dc_stream_state *stream = pipe_ctx->stream; 1746 struct dc_link *link = stream->link; 1747 struct fixed31_32 avg_time_slots_per_mtp; 1748 struct fixed31_32 pbn; 1749 struct fixed31_32 pbn_per_slot; 1750 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1751 uint8_t i; 1752 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1753 DC_LOGGER_INIT(link->ctx->logger); 1754 1755 /* decrease throttled vcp size */ 1756 pbn_per_slot = get_pbn_per_slot(stream); 1757 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1758 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1759 1760 if (link_hwss->ext.set_throttled_vcp_size) 1761 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1762 if (link_hwss->ext.set_hblank_min_symbol_width) 1763 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1764 &link->cur_link_settings, 1765 avg_time_slots_per_mtp); 1766 1767 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1768 dm_helpers_dp_mst_send_payload_allocation( 1769 stream->ctx, 1770 stream, 1771 true); 1772 1773 /* notify immediate branch device table update */ 1774 if (dm_helpers_dp_mst_write_payload_allocation_table( 1775 stream->ctx, 1776 stream, 1777 &proposed_table, 1778 true)) { 1779 /* update mst stream allocation table software state */ 1780 update_mst_stream_alloc_table( 1781 link, 1782 pipe_ctx->stream_res.stream_enc, 1783 pipe_ctx->stream_res.hpo_dp_stream_enc, 1784 &proposed_table); 1785 } else { 1786 DC_LOG_WARNING("Failed to update" 1787 "MST allocation table for" 1788 "pipe idx:%d\n", 1789 pipe_ctx->pipe_idx); 1790 } 1791 1792 DC_LOG_MST("%s " 1793 "stream_count: %d: \n ", 1794 __func__, 1795 link->mst_stream_alloc_table.stream_count); 1796 1797 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1798 DC_LOG_MST("stream_enc[%d]: %p " 1799 "stream[%d].hpo_dp_stream_enc: %p " 1800 "stream[%d].vcp_id: %d " 1801 "stream[%d].slot_count: %d\n", 1802 i, 1803 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1804 i, 1805 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1806 i, 1807 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1808 i, 1809 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1810 } 1811 1812 ASSERT(proposed_table.stream_count > 0); 1813 1814 /* update mst stream allocation table hardware state */ 1815 if (link_hwss->ext.update_stream_allocation_table == NULL || 1816 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1817 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1818 return DC_ERROR_UNEXPECTED; 1819 } 1820 1821 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1822 &link->mst_stream_alloc_table); 1823 1824 /* poll for immediate branch device ACT handled */ 1825 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1826 stream->ctx, 1827 stream); 1828 1829 return DC_OK; 1830 } 1831 1832 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1833 { 1834 struct dc_stream_state *stream = pipe_ctx->stream; 1835 struct dc_link *link = stream->link; 1836 struct fixed31_32 avg_time_slots_per_mtp; 1837 struct fixed31_32 pbn; 1838 struct fixed31_32 pbn_per_slot; 1839 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1840 uint8_t i; 1841 enum act_return_status ret; 1842 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1843 DC_LOGGER_INIT(link->ctx->logger); 1844 1845 /* notify immediate branch device table update */ 1846 if (dm_helpers_dp_mst_write_payload_allocation_table( 1847 stream->ctx, 1848 stream, 1849 &proposed_table, 1850 true)) { 1851 /* update mst stream allocation table software state */ 1852 update_mst_stream_alloc_table( 1853 link, 1854 pipe_ctx->stream_res.stream_enc, 1855 pipe_ctx->stream_res.hpo_dp_stream_enc, 1856 &proposed_table); 1857 } 1858 1859 DC_LOG_MST("%s " 1860 "stream_count: %d: \n ", 1861 __func__, 1862 link->mst_stream_alloc_table.stream_count); 1863 1864 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1865 DC_LOG_MST("stream_enc[%d]: %p " 1866 "stream[%d].hpo_dp_stream_enc: %p " 1867 "stream[%d].vcp_id: %d " 1868 "stream[%d].slot_count: %d\n", 1869 i, 1870 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1871 i, 1872 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1873 i, 1874 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1875 i, 1876 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1877 } 1878 1879 ASSERT(proposed_table.stream_count > 0); 1880 1881 /* update mst stream allocation table hardware state */ 1882 if (link_hwss->ext.update_stream_allocation_table == NULL || 1883 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1884 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1885 return DC_ERROR_UNEXPECTED; 1886 } 1887 1888 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1889 &link->mst_stream_alloc_table); 1890 1891 /* poll for immediate branch device ACT handled */ 1892 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1893 stream->ctx, 1894 stream); 1895 1896 if (ret != ACT_LINK_LOST) { 1897 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1898 dm_helpers_dp_mst_send_payload_allocation( 1899 stream->ctx, 1900 stream, 1901 true); 1902 } 1903 1904 /* increase throttled vcp size */ 1905 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1906 pbn_per_slot = get_pbn_per_slot(stream); 1907 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1908 1909 if (link_hwss->ext.set_throttled_vcp_size) 1910 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1911 if (link_hwss->ext.set_hblank_min_symbol_width) 1912 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1913 &link->cur_link_settings, 1914 avg_time_slots_per_mtp); 1915 1916 return DC_OK; 1917 } 1918 1919 static void disable_link_dp(struct dc_link *link, 1920 const struct link_resource *link_res, 1921 enum signal_type signal) 1922 { 1923 struct dc_link_settings link_settings = link->cur_link_settings; 1924 1925 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1926 link->mst_stream_alloc_table.stream_count > 0) 1927 /* disable MST link only when last vc payload is deallocated */ 1928 return; 1929 1930 dp_disable_link_phy(link, link_res, signal); 1931 1932 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1933 if (!link->dc->config.edp_no_power_sequencing) 1934 link->dc->hwss.edp_power_control(link, false); 1935 } 1936 1937 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1938 /* set the sink to SST mode after disabling the link */ 1939 enable_mst_on_sink(link, false); 1940 1941 if (link_dp_get_encoding_format(&link_settings) == 1942 DP_8b_10b_ENCODING) { 1943 dp_set_fec_enable(link, false); 1944 dp_set_fec_ready(link, link_res, false); 1945 } 1946 } 1947 1948 static void disable_link(struct dc_link *link, 1949 const struct link_resource *link_res, 1950 enum signal_type signal) 1951 { 1952 if (dc_is_dp_signal(signal)) { 1953 disable_link_dp(link, link_res, signal); 1954 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1955 link->dc->hwss.disable_link_output(link, link_res, signal); 1956 } 1957 1958 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1959 /* MST disable link only when no stream use the link */ 1960 if (link->mst_stream_alloc_table.stream_count <= 0) 1961 link->link_status.link_active = false; 1962 } else { 1963 link->link_status.link_active = false; 1964 } 1965 } 1966 1967 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1968 { 1969 struct dc_stream_state *stream = pipe_ctx->stream; 1970 struct dc_link *link = stream->link; 1971 enum dc_color_depth display_color_depth; 1972 enum engine_id eng_id; 1973 struct ext_hdmi_settings settings = {0}; 1974 bool is_over_340mhz = false; 1975 bool is_vga_mode = (stream->timing.h_addressable == 640) 1976 && (stream->timing.v_addressable == 480); 1977 struct dc *dc = pipe_ctx->stream->ctx->dc; 1978 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1979 1980 if (stream->phy_pix_clk == 0) 1981 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1982 if (stream->phy_pix_clk > 340000) 1983 is_over_340mhz = true; 1984 1985 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1986 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1987 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1988 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1989 /* DP159, Retimer settings */ 1990 eng_id = pipe_ctx->stream_res.stream_enc->id; 1991 1992 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1993 write_i2c_retimer_setting(pipe_ctx, 1994 is_vga_mode, is_over_340mhz, &settings); 1995 } else { 1996 write_i2c_default_retimer_setting(pipe_ctx, 1997 is_vga_mode, is_over_340mhz); 1998 } 1999 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2000 /* PI3EQX1204, Redriver settings */ 2001 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 2002 } 2003 } 2004 2005 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2006 write_scdc_data( 2007 stream->link->ddc, 2008 stream->phy_pix_clk, 2009 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2010 2011 memset(&stream->link->cur_link_settings, 0, 2012 sizeof(struct dc_link_settings)); 2013 2014 display_color_depth = stream->timing.display_color_depth; 2015 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2016 display_color_depth = COLOR_DEPTH_888; 2017 2018 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 2019 * character clock in case that beyond 340MHz. 2020 */ 2021 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 2022 link_hwss->setup_stream_encoder(pipe_ctx); 2023 2024 dc->hwss.enable_tmds_link_output( 2025 link, 2026 &pipe_ctx->link_res, 2027 pipe_ctx->stream->signal, 2028 pipe_ctx->clock_source->id, 2029 display_color_depth, 2030 stream->phy_pix_clk); 2031 2032 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2033 read_scdc_data(link->ddc); 2034 } 2035 2036 static enum dc_status enable_link_dp(struct dc_state *state, 2037 struct pipe_ctx *pipe_ctx) 2038 { 2039 struct dc_stream_state *stream = pipe_ctx->stream; 2040 enum dc_status status; 2041 bool skip_video_pattern; 2042 struct dc_link *link = stream->link; 2043 const struct dc_link_settings *link_settings = 2044 &pipe_ctx->link_config.dp_link_settings; 2045 bool fec_enable; 2046 int i; 2047 bool apply_seamless_boot_optimization = false; 2048 uint32_t bl_oled_enable_delay = 50; // in ms 2049 uint32_t post_oui_delay = 30; // 30ms 2050 /* Reduce link bandwidth between failed link training attempts. */ 2051 bool do_fallback = false; 2052 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2053 2054 // Increase retry count if attempting DP1.x on FIXED_VS link 2055 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2056 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2057 lt_attempts = 10; 2058 2059 // check for seamless boot 2060 for (i = 0; i < state->stream_count; i++) { 2061 if (state->streams[i]->apply_seamless_boot_optimization) { 2062 apply_seamless_boot_optimization = true; 2063 break; 2064 } 2065 } 2066 2067 /* 2068 * If the link is DP-over-USB4 do the following: 2069 * - Train with fallback when enabling DPIA link. Conventional links are 2070 * trained with fallback during sink detection. 2071 * - Allocate only what the stream needs for bw in Gbps. Inform the CM 2072 * in case stream needs more or less bw from what has been allocated 2073 * earlier at plug time. 2074 */ 2075 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 2076 do_fallback = true; 2077 } 2078 2079 /* 2080 * Temporary w/a to get DP2.0 link rates to work with SST. 2081 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2082 */ 2083 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2084 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2085 link->dc->debug.set_mst_en_for_sst) { 2086 enable_mst_on_sink(link, true); 2087 } 2088 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2089 /*in case it is not on*/ 2090 if (!link->dc->config.edp_no_power_sequencing) 2091 link->dc->hwss.edp_power_control(link, true); 2092 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2093 } 2094 2095 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2096 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2097 } else { 2098 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2099 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2100 if (state->clk_mgr && !apply_seamless_boot_optimization) 2101 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2102 state, false); 2103 } 2104 2105 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2106 dpcd_set_source_specific_data(link); 2107 if (link->dpcd_sink_ext_caps.raw != 0) { 2108 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2109 msleep(post_oui_delay); 2110 } 2111 2112 // similarly, mode switch can cause loss of cable ID 2113 dpcd_write_cable_id_to_dprx(link); 2114 2115 skip_video_pattern = true; 2116 2117 if (link_settings->link_rate == LINK_RATE_LOW) 2118 skip_video_pattern = false; 2119 2120 if (perform_link_training_with_retries(link_settings, 2121 skip_video_pattern, 2122 lt_attempts, 2123 pipe_ctx, 2124 pipe_ctx->stream->signal, 2125 do_fallback)) { 2126 status = DC_OK; 2127 } else { 2128 status = DC_FAIL_DP_LINK_TRAINING; 2129 } 2130 2131 if (link->preferred_training_settings.fec_enable) 2132 fec_enable = *link->preferred_training_settings.fec_enable; 2133 else 2134 fec_enable = true; 2135 2136 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2137 dp_set_fec_enable(link, fec_enable); 2138 2139 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2140 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2141 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2142 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2143 set_cached_brightness_aux(link); 2144 2145 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2146 msleep(bl_oled_enable_delay); 2147 edp_backlight_enable_aux(link, true); 2148 } 2149 2150 return status; 2151 } 2152 2153 static enum dc_status enable_link_edp( 2154 struct dc_state *state, 2155 struct pipe_ctx *pipe_ctx) 2156 { 2157 return enable_link_dp(state, pipe_ctx); 2158 } 2159 2160 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2161 { 2162 struct dc_stream_state *stream = pipe_ctx->stream; 2163 struct dc_link *link = stream->link; 2164 struct dc *dc = stream->ctx->dc; 2165 2166 if (stream->phy_pix_clk == 0) 2167 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2168 2169 memset(&stream->link->cur_link_settings, 0, 2170 sizeof(struct dc_link_settings)); 2171 dc->hwss.enable_lvds_link_output( 2172 link, 2173 &pipe_ctx->link_res, 2174 pipe_ctx->clock_source->id, 2175 stream->phy_pix_clk); 2176 2177 } 2178 2179 static enum dc_status enable_link_dp_mst( 2180 struct dc_state *state, 2181 struct pipe_ctx *pipe_ctx) 2182 { 2183 struct dc_link *link = pipe_ctx->stream->link; 2184 unsigned char mstm_cntl; 2185 2186 /* sink signal type after MST branch is MST. Multiple MST sinks 2187 * share one link. Link DP PHY is enable or training only once. 2188 */ 2189 if (link->link_status.link_active) 2190 return DC_OK; 2191 2192 /* clear payload table */ 2193 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2194 if (mstm_cntl & DP_MST_EN) 2195 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2196 2197 /* to make sure the pending down rep can be processed 2198 * before enabling the link 2199 */ 2200 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2201 2202 /* set the sink to MST mode before enabling the link */ 2203 enable_mst_on_sink(link, true); 2204 2205 return enable_link_dp(state, pipe_ctx); 2206 } 2207 2208 static enum dc_status enable_link( 2209 struct dc_state *state, 2210 struct pipe_ctx *pipe_ctx) 2211 { 2212 enum dc_status status = DC_ERROR_UNEXPECTED; 2213 struct dc_stream_state *stream = pipe_ctx->stream; 2214 struct dc_link *link = stream->link; 2215 2216 /* There's some scenarios where driver is unloaded with display 2217 * still enabled. When driver is reloaded, it may cause a display 2218 * to not light up if there is a mismatch between old and new 2219 * link settings. Need to call disable first before enabling at 2220 * new link settings. 2221 */ 2222 if (link->link_status.link_active && !stream->skip_edp_power_down) 2223 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2224 2225 switch (pipe_ctx->stream->signal) { 2226 case SIGNAL_TYPE_DISPLAY_PORT: 2227 status = enable_link_dp(state, pipe_ctx); 2228 break; 2229 case SIGNAL_TYPE_EDP: 2230 status = enable_link_edp(state, pipe_ctx); 2231 break; 2232 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2233 status = enable_link_dp_mst(state, pipe_ctx); 2234 msleep(200); 2235 break; 2236 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2237 case SIGNAL_TYPE_DVI_DUAL_LINK: 2238 case SIGNAL_TYPE_HDMI_TYPE_A: 2239 enable_link_hdmi(pipe_ctx); 2240 status = DC_OK; 2241 break; 2242 case SIGNAL_TYPE_LVDS: 2243 enable_link_lvds(pipe_ctx); 2244 status = DC_OK; 2245 break; 2246 case SIGNAL_TYPE_VIRTUAL: 2247 status = DC_OK; 2248 break; 2249 default: 2250 break; 2251 } 2252 2253 if (status == DC_OK) { 2254 pipe_ctx->stream->link->link_status.link_active = true; 2255 } 2256 2257 return status; 2258 } 2259 2260 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2261 { 2262 struct dc *dc = pipe_ctx->stream->ctx->dc; 2263 struct dc_stream_state *stream = pipe_ctx->stream; 2264 struct dc_link *link = stream->sink->link; 2265 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2266 2267 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2268 2269 if (dp_is_128b_132b_signal(pipe_ctx)) 2270 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2271 2272 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2273 2274 if (pipe_ctx->stream->sink) { 2275 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2276 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2277 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2278 pipe_ctx->stream->sink->edid_caps.display_name, 2279 pipe_ctx->stream->signal); 2280 } 2281 } 2282 2283 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2284 return; 2285 2286 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2287 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2288 set_avmute(pipe_ctx, true); 2289 } 2290 2291 dc->hwss.disable_audio_stream(pipe_ctx); 2292 2293 update_psp_stream_config(pipe_ctx, true); 2294 dc->hwss.blank_stream(pipe_ctx); 2295 2296 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2297 deallocate_mst_payload(pipe_ctx); 2298 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2299 dp_is_128b_132b_signal(pipe_ctx)) 2300 update_sst_payload(pipe_ctx, false); 2301 2302 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2303 struct ext_hdmi_settings settings = {0}; 2304 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2305 2306 unsigned short masked_chip_caps = link->chip_caps & 2307 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2308 //Need to inform that sink is going to use legacy HDMI mode. 2309 write_scdc_data( 2310 link->ddc, 2311 165000,//vbios only handles 165Mhz. 2312 false); 2313 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2314 /* DP159, Retimer settings */ 2315 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2316 write_i2c_retimer_setting(pipe_ctx, 2317 false, false, &settings); 2318 else 2319 write_i2c_default_retimer_setting(pipe_ctx, 2320 false, false); 2321 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2322 /* PI3EQX1204, Redriver settings */ 2323 write_i2c_redriver_setting(pipe_ctx, false); 2324 } 2325 } 2326 2327 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2328 !dp_is_128b_132b_signal(pipe_ctx)) { 2329 2330 /* In DP1.x SST mode, our encoder will go to TPS1 2331 * when link is on but stream is off. 2332 * Disabling link before stream will avoid exposing TPS1 pattern 2333 * during the disable sequence as it will confuse some receivers 2334 * state machine. 2335 * In DP2 or MST mode, our encoder will stay video active 2336 */ 2337 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2338 dc->hwss.disable_stream(pipe_ctx); 2339 } else { 2340 dc->hwss.disable_stream(pipe_ctx); 2341 if (!pipe_ctx->stream->skip_edp_power_down) { 2342 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2343 } 2344 } 2345 2346 if (pipe_ctx->stream->timing.flags.DSC) { 2347 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2348 link_set_dsc_enable(pipe_ctx, false); 2349 } 2350 if (dp_is_128b_132b_signal(pipe_ctx)) { 2351 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2352 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2353 } 2354 2355 if (vpg && vpg->funcs->vpg_powerdown) 2356 vpg->funcs->vpg_powerdown(vpg); 2357 } 2358 2359 void link_set_dpms_on( 2360 struct dc_state *state, 2361 struct pipe_ctx *pipe_ctx) 2362 { 2363 struct dc *dc = pipe_ctx->stream->ctx->dc; 2364 struct dc_stream_state *stream = pipe_ctx->stream; 2365 struct dc_link *link = stream->sink->link; 2366 enum dc_status status; 2367 struct link_encoder *link_enc; 2368 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2369 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2370 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2371 bool apply_edp_fast_boot_optimization = 2372 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2373 2374 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2375 2376 if (dp_is_128b_132b_signal(pipe_ctx)) 2377 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2378 2379 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2380 2381 if (pipe_ctx->stream->sink) { 2382 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2383 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2384 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2385 pipe_ctx->stream->sink->edid_caps.display_name, 2386 pipe_ctx->stream->signal); 2387 } 2388 } 2389 2390 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2391 return; 2392 2393 link_enc = link_enc_cfg_get_link_enc(link); 2394 ASSERT(link_enc); 2395 2396 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2397 && !dp_is_128b_132b_signal(pipe_ctx)) { 2398 if (link_enc) 2399 link_enc->funcs->setup( 2400 link_enc, 2401 pipe_ctx->stream->signal); 2402 } 2403 2404 pipe_ctx->stream->link->link_state_valid = true; 2405 2406 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2407 if (dp_is_128b_132b_signal(pipe_ctx)) 2408 otg_out_dest = OUT_MUX_HPO_DP; 2409 else 2410 otg_out_dest = OUT_MUX_DIO; 2411 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2412 } 2413 2414 link_hwss->setup_stream_attribute(pipe_ctx); 2415 2416 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2417 2418 // Enable VPG before building infoframe 2419 if (vpg && vpg->funcs->vpg_poweron) 2420 vpg->funcs->vpg_poweron(vpg); 2421 2422 resource_build_info_frame(pipe_ctx); 2423 dc->hwss.update_info_frame(pipe_ctx); 2424 2425 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2426 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2427 2428 /* Do not touch link on seamless boot optimization. */ 2429 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2430 pipe_ctx->stream->dpms_off = false; 2431 2432 /* Still enable stream features & audio on seamless boot for DP external displays */ 2433 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2434 enable_stream_features(pipe_ctx); 2435 dc->hwss.enable_audio_stream(pipe_ctx); 2436 } 2437 2438 update_psp_stream_config(pipe_ctx, false); 2439 return; 2440 } 2441 2442 /* eDP lit up by bios already, no need to enable again. */ 2443 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2444 apply_edp_fast_boot_optimization && 2445 !pipe_ctx->stream->timing.flags.DSC && 2446 !pipe_ctx->next_odm_pipe) { 2447 pipe_ctx->stream->dpms_off = false; 2448 update_psp_stream_config(pipe_ctx, false); 2449 return; 2450 } 2451 2452 if (pipe_ctx->stream->dpms_off) 2453 return; 2454 2455 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2456 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2457 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2458 * will be automatically set at a later time when the video is enabled 2459 * (DP_VID_STREAM_EN = 1). 2460 */ 2461 if (pipe_ctx->stream->timing.flags.DSC) { 2462 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2463 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2464 link_set_dsc_enable(pipe_ctx, true); 2465 2466 } 2467 2468 status = enable_link(state, pipe_ctx); 2469 2470 if (status != DC_OK) { 2471 DC_LOG_WARNING("enabling link %u failed: %d\n", 2472 pipe_ctx->stream->link->link_index, 2473 status); 2474 2475 /* Abort stream enable *unless* the failure was due to 2476 * DP link training - some DP monitors will recover and 2477 * show the stream anyway. But MST displays can't proceed 2478 * without link training. 2479 */ 2480 if (status != DC_FAIL_DP_LINK_TRAINING || 2481 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2482 if (false == stream->link->link_status.link_active) 2483 disable_link(stream->link, &pipe_ctx->link_res, 2484 pipe_ctx->stream->signal); 2485 BREAK_TO_DEBUGGER(); 2486 return; 2487 } 2488 } 2489 2490 /* turn off otg test pattern if enable */ 2491 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2492 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2493 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2494 COLOR_DEPTH_UNDEFINED); 2495 2496 /* This second call is needed to reconfigure the DIG 2497 * as a workaround for the incorrect value being applied 2498 * from transmitter control. 2499 */ 2500 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2501 dp_is_128b_132b_signal(pipe_ctx))) { 2502 if (link_enc) 2503 link_enc->funcs->setup( 2504 link_enc, 2505 pipe_ctx->stream->signal); 2506 } 2507 2508 dc->hwss.enable_stream(pipe_ctx); 2509 2510 /* Set DPS PPS SDP (AKA "info frames") */ 2511 if (pipe_ctx->stream->timing.flags.DSC) { 2512 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2513 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2514 dp_set_dsc_on_rx(pipe_ctx, true); 2515 link_set_dsc_pps_packet(pipe_ctx, true, true); 2516 } 2517 } 2518 2519 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2520 allocate_mst_payload(pipe_ctx); 2521 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2522 dp_is_128b_132b_signal(pipe_ctx)) 2523 update_sst_payload(pipe_ctx, true); 2524 2525 dc->hwss.unblank_stream(pipe_ctx, 2526 &pipe_ctx->stream->link->cur_link_settings); 2527 2528 if (stream->sink_patches.delay_ignore_msa > 0) 2529 msleep(stream->sink_patches.delay_ignore_msa); 2530 2531 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2532 enable_stream_features(pipe_ctx); 2533 update_psp_stream_config(pipe_ctx, false); 2534 2535 dc->hwss.enable_audio_stream(pipe_ctx); 2536 2537 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2538 set_avmute(pipe_ctx, false); 2539 } 2540 } 2541