1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 144 dpcd_write_rx_power_ctrl(link, false); 145 } 146 } 147 148 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 149 { 150 struct pipe_ctx *pipes[MAX_PIPES]; 151 struct dc_state *state = link->dc->current_state; 152 uint8_t count; 153 int i; 154 struct dc_stream_update stream_update; 155 bool dpms_off = true; 156 struct link_resource link_res = {0}; 157 158 memset(&stream_update, 0, sizeof(stream_update)); 159 stream_update.dpms_off = &dpms_off; 160 161 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 162 163 for (i = 0; i < count; i++) { 164 stream_update.stream = pipes[i]->stream; 165 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 166 pipes[i]->stream, &stream_update, 167 state); 168 } 169 170 /* link can be also enabled by vbios. In this case it is not recorded 171 * in pipe_ctx. Disable link phy here to make sure it is completely off 172 */ 173 dp_disable_link_phy(link, &link_res, link->connector_signal); 174 } 175 176 void link_resume(struct dc_link *link) 177 { 178 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 179 program_hpd_filter(link); 180 } 181 182 /* This function returns true if the pipe is used to feed video signal directly 183 * to the link. 184 */ 185 static bool is_master_pipe_for_link(const struct dc_link *link, 186 const struct pipe_ctx *pipe) 187 { 188 return resource_is_pipe_type(pipe, OTG_MASTER) && 189 pipe->stream->link == link; 190 } 191 192 /* 193 * This function finds all master pipes feeding to a given link with dpms set to 194 * on in given dc state. 195 */ 196 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 197 struct dc_state *state, 198 uint8_t *count, 199 struct pipe_ctx *pipes[MAX_PIPES]) 200 { 201 int i; 202 struct pipe_ctx *pipe = NULL; 203 204 *count = 0; 205 for (i = 0; i < MAX_PIPES; i++) { 206 pipe = &state->res_ctx.pipe_ctx[i]; 207 208 if (is_master_pipe_for_link(link, pipe) && 209 pipe->stream->dpms_off == false) { 210 pipes[(*count)++] = pipe; 211 } 212 } 213 } 214 215 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 216 enum engine_id eng_id, 217 struct ext_hdmi_settings *settings) 218 { 219 bool result = false; 220 int i = 0; 221 struct integrated_info *integrated_info = 222 pipe_ctx->stream->ctx->dc_bios->integrated_info; 223 224 if (integrated_info == NULL) 225 return false; 226 227 /* 228 * Get retimer settings from sbios for passing SI eye test for DCE11 229 * The setting values are varied based on board revision and port id 230 * Therefore the setting values of each ports is passed by sbios. 231 */ 232 233 // Check if current bios contains ext Hdmi settings 234 if (integrated_info->gpu_cap_info & 0x20) { 235 switch (eng_id) { 236 case ENGINE_ID_DIGA: 237 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 238 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 240 memmove(settings->reg_settings, 241 integrated_info->dp0_ext_hdmi_reg_settings, 242 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 243 memmove(settings->reg_settings_6g, 244 integrated_info->dp0_ext_hdmi_6g_reg_settings, 245 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 246 result = true; 247 break; 248 case ENGINE_ID_DIGB: 249 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 250 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 252 memmove(settings->reg_settings, 253 integrated_info->dp1_ext_hdmi_reg_settings, 254 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 255 memmove(settings->reg_settings_6g, 256 integrated_info->dp1_ext_hdmi_6g_reg_settings, 257 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 258 result = true; 259 break; 260 case ENGINE_ID_DIGC: 261 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 262 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 264 memmove(settings->reg_settings, 265 integrated_info->dp2_ext_hdmi_reg_settings, 266 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 267 memmove(settings->reg_settings_6g, 268 integrated_info->dp2_ext_hdmi_6g_reg_settings, 269 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 270 result = true; 271 break; 272 case ENGINE_ID_DIGD: 273 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 274 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 276 memmove(settings->reg_settings, 277 integrated_info->dp3_ext_hdmi_reg_settings, 278 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 279 memmove(settings->reg_settings_6g, 280 integrated_info->dp3_ext_hdmi_6g_reg_settings, 281 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 282 result = true; 283 break; 284 default: 285 break; 286 } 287 288 if (result == true) { 289 // Validate settings from bios integrated info table 290 if (settings->slv_addr == 0) 291 return false; 292 if (settings->reg_num > 9) 293 return false; 294 if (settings->reg_num_6g > 3) 295 return false; 296 297 for (i = 0; i < settings->reg_num; i++) { 298 if (settings->reg_settings[i].i2c_reg_index > 0x20) 299 return false; 300 } 301 302 for (i = 0; i < settings->reg_num_6g; i++) { 303 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 304 return false; 305 } 306 } 307 } 308 309 return result; 310 } 311 312 static bool write_i2c(struct pipe_ctx *pipe_ctx, 313 uint8_t address, uint8_t *buffer, uint32_t length) 314 { 315 struct i2c_command cmd = {0}; 316 struct i2c_payload payload = {0}; 317 318 memset(&payload, 0, sizeof(payload)); 319 memset(&cmd, 0, sizeof(cmd)); 320 321 cmd.number_of_payloads = 1; 322 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 323 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 324 325 payload.address = address; 326 payload.data = buffer; 327 payload.length = length; 328 payload.write = true; 329 cmd.payloads = &payload; 330 331 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 332 pipe_ctx->stream->link, &cmd)) 333 return true; 334 335 return false; 336 } 337 338 static void write_i2c_retimer_setting( 339 struct pipe_ctx *pipe_ctx, 340 bool is_vga_mode, 341 bool is_over_340mhz, 342 struct ext_hdmi_settings *settings) 343 { 344 uint8_t slave_address = (settings->slv_addr >> 1); 345 uint8_t buffer[2]; 346 const uint8_t apply_rx_tx_change = 0x4; 347 uint8_t offset = 0xA; 348 uint8_t value = 0; 349 int i = 0; 350 bool i2c_success = false; 351 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 352 353 memset(&buffer, 0, sizeof(buffer)); 354 355 /* Start Ext-Hdmi programming*/ 356 357 for (i = 0; i < settings->reg_num; i++) { 358 /* Apply 3G settings */ 359 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 360 361 buffer[0] = settings->reg_settings[i].i2c_reg_index; 362 buffer[1] = settings->reg_settings[i].i2c_reg_val; 363 i2c_success = write_i2c(pipe_ctx, slave_address, 364 buffer, sizeof(buffer)); 365 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 366 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 367 slave_address, buffer[0], buffer[1], i2c_success?1:0); 368 369 if (!i2c_success) 370 goto i2c_write_fail; 371 372 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 373 * needs to be set to 1 on every 0xA-0xC write. 374 */ 375 if (settings->reg_settings[i].i2c_reg_index == 0xA || 376 settings->reg_settings[i].i2c_reg_index == 0xB || 377 settings->reg_settings[i].i2c_reg_index == 0xC) { 378 379 /* Query current value from offset 0xA */ 380 if (settings->reg_settings[i].i2c_reg_index == 0xA) 381 value = settings->reg_settings[i].i2c_reg_val; 382 else { 383 i2c_success = 384 link_query_ddc_data( 385 pipe_ctx->stream->link->ddc, 386 slave_address, &offset, 1, &value, 1); 387 if (!i2c_success) 388 goto i2c_write_fail; 389 } 390 391 buffer[0] = offset; 392 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 393 buffer[1] = value | apply_rx_tx_change; 394 i2c_success = write_i2c(pipe_ctx, slave_address, 395 buffer, sizeof(buffer)); 396 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 397 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 398 slave_address, buffer[0], buffer[1], i2c_success?1:0); 399 if (!i2c_success) 400 goto i2c_write_fail; 401 } 402 } 403 } 404 405 /* Apply 3G settings */ 406 if (is_over_340mhz) { 407 for (i = 0; i < settings->reg_num_6g; i++) { 408 /* Apply 3G settings */ 409 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 410 411 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 412 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 413 i2c_success = write_i2c(pipe_ctx, slave_address, 414 buffer, sizeof(buffer)); 415 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 416 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 417 slave_address, buffer[0], buffer[1], i2c_success?1:0); 418 419 if (!i2c_success) 420 goto i2c_write_fail; 421 422 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 423 * needs to be set to 1 on every 0xA-0xC write. 424 */ 425 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 427 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 428 429 /* Query current value from offset 0xA */ 430 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 431 value = settings->reg_settings_6g[i].i2c_reg_val; 432 else { 433 i2c_success = 434 link_query_ddc_data( 435 pipe_ctx->stream->link->ddc, 436 slave_address, &offset, 1, &value, 1); 437 if (!i2c_success) 438 goto i2c_write_fail; 439 } 440 441 buffer[0] = offset; 442 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 443 buffer[1] = value | apply_rx_tx_change; 444 i2c_success = write_i2c(pipe_ctx, slave_address, 445 buffer, sizeof(buffer)); 446 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 447 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 448 slave_address, buffer[0], buffer[1], i2c_success?1:0); 449 if (!i2c_success) 450 goto i2c_write_fail; 451 } 452 } 453 } 454 } 455 456 if (is_vga_mode) { 457 /* Program additional settings if using 640x480 resolution */ 458 459 /* Write offset 0xFF to 0x01 */ 460 buffer[0] = 0xff; 461 buffer[1] = 0x01; 462 i2c_success = write_i2c(pipe_ctx, slave_address, 463 buffer, sizeof(buffer)); 464 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 465 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 466 slave_address, buffer[0], buffer[1], i2c_success?1:0); 467 if (!i2c_success) 468 goto i2c_write_fail; 469 470 /* Write offset 0x00 to 0x23 */ 471 buffer[0] = 0x00; 472 buffer[1] = 0x23; 473 i2c_success = write_i2c(pipe_ctx, slave_address, 474 buffer, sizeof(buffer)); 475 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 476 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 477 slave_address, buffer[0], buffer[1], i2c_success?1:0); 478 if (!i2c_success) 479 goto i2c_write_fail; 480 481 /* Write offset 0xff to 0x00 */ 482 buffer[0] = 0xff; 483 buffer[1] = 0x00; 484 i2c_success = write_i2c(pipe_ctx, slave_address, 485 buffer, sizeof(buffer)); 486 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 487 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 488 slave_address, buffer[0], buffer[1], i2c_success?1:0); 489 if (!i2c_success) 490 goto i2c_write_fail; 491 492 } 493 494 return; 495 496 i2c_write_fail: 497 DC_LOG_DEBUG("Set retimer failed"); 498 } 499 500 static void write_i2c_default_retimer_setting( 501 struct pipe_ctx *pipe_ctx, 502 bool is_vga_mode, 503 bool is_over_340mhz) 504 { 505 uint8_t slave_address = (0xBA >> 1); 506 uint8_t buffer[2]; 507 bool i2c_success = false; 508 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 509 510 memset(&buffer, 0, sizeof(buffer)); 511 512 /* Program Slave Address for tuning single integrity */ 513 /* Write offset 0x0A to 0x13 */ 514 buffer[0] = 0x0A; 515 buffer[1] = 0x13; 516 i2c_success = write_i2c(pipe_ctx, slave_address, 517 buffer, sizeof(buffer)); 518 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 519 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 520 slave_address, buffer[0], buffer[1], i2c_success?1:0); 521 if (!i2c_success) 522 goto i2c_write_fail; 523 524 /* Write offset 0x0A to 0x17 */ 525 buffer[0] = 0x0A; 526 buffer[1] = 0x17; 527 i2c_success = write_i2c(pipe_ctx, slave_address, 528 buffer, sizeof(buffer)); 529 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 530 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 531 slave_address, buffer[0], buffer[1], i2c_success?1:0); 532 if (!i2c_success) 533 goto i2c_write_fail; 534 535 /* Write offset 0x0B to 0xDA or 0xD8 */ 536 buffer[0] = 0x0B; 537 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 538 i2c_success = write_i2c(pipe_ctx, slave_address, 539 buffer, sizeof(buffer)); 540 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 541 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 542 slave_address, buffer[0], buffer[1], i2c_success?1:0); 543 if (!i2c_success) 544 goto i2c_write_fail; 545 546 /* Write offset 0x0A to 0x17 */ 547 buffer[0] = 0x0A; 548 buffer[1] = 0x17; 549 i2c_success = write_i2c(pipe_ctx, slave_address, 550 buffer, sizeof(buffer)); 551 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 552 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 553 slave_address, buffer[0], buffer[1], i2c_success?1:0); 554 if (!i2c_success) 555 goto i2c_write_fail; 556 557 /* Write offset 0x0C to 0x1D or 0x91 */ 558 buffer[0] = 0x0C; 559 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 560 i2c_success = write_i2c(pipe_ctx, slave_address, 561 buffer, sizeof(buffer)); 562 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 563 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 564 slave_address, buffer[0], buffer[1], i2c_success?1:0); 565 if (!i2c_success) 566 goto i2c_write_fail; 567 568 /* Write offset 0x0A to 0x17 */ 569 buffer[0] = 0x0A; 570 buffer[1] = 0x17; 571 i2c_success = write_i2c(pipe_ctx, slave_address, 572 buffer, sizeof(buffer)); 573 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 574 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 575 slave_address, buffer[0], buffer[1], i2c_success?1:0); 576 if (!i2c_success) 577 goto i2c_write_fail; 578 579 580 if (is_vga_mode) { 581 /* Program additional settings if using 640x480 resolution */ 582 583 /* Write offset 0xFF to 0x01 */ 584 buffer[0] = 0xff; 585 buffer[1] = 0x01; 586 i2c_success = write_i2c(pipe_ctx, slave_address, 587 buffer, sizeof(buffer)); 588 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 589 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 590 slave_address, buffer[0], buffer[1], i2c_success?1:0); 591 if (!i2c_success) 592 goto i2c_write_fail; 593 594 /* Write offset 0x00 to 0x23 */ 595 buffer[0] = 0x00; 596 buffer[1] = 0x23; 597 i2c_success = write_i2c(pipe_ctx, slave_address, 598 buffer, sizeof(buffer)); 599 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 600 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 601 slave_address, buffer[0], buffer[1], i2c_success?1:0); 602 if (!i2c_success) 603 goto i2c_write_fail; 604 605 /* Write offset 0xff to 0x00 */ 606 buffer[0] = 0xff; 607 buffer[1] = 0x00; 608 i2c_success = write_i2c(pipe_ctx, slave_address, 609 buffer, sizeof(buffer)); 610 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 611 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 612 slave_address, buffer[0], buffer[1], i2c_success?1:0); 613 if (!i2c_success) 614 goto i2c_write_fail; 615 } 616 617 return; 618 619 i2c_write_fail: 620 DC_LOG_DEBUG("Set default retimer failed"); 621 } 622 623 static void write_i2c_redriver_setting( 624 struct pipe_ctx *pipe_ctx, 625 bool is_over_340mhz) 626 { 627 uint8_t slave_address = (0xF0 >> 1); 628 uint8_t buffer[16]; 629 bool i2c_success = false; 630 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 631 632 memset(&buffer, 0, sizeof(buffer)); 633 634 // Program Slave Address for tuning single integrity 635 buffer[3] = 0x4E; 636 buffer[4] = 0x4E; 637 buffer[5] = 0x4E; 638 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 639 640 i2c_success = write_i2c(pipe_ctx, slave_address, 641 buffer, sizeof(buffer)); 642 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 643 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 644 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 645 i2c_success = %d\n", 646 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 647 648 if (!i2c_success) 649 DC_LOG_DEBUG("Set redriver failed"); 650 } 651 652 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 653 { 654 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 655 struct link_encoder *link_enc = NULL; 656 struct cp_psp_stream_config config = {0}; 657 enum dp_panel_mode panel_mode = 658 dp_get_panel_mode(pipe_ctx->stream->link); 659 660 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 661 return; 662 663 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 664 ASSERT(link_enc); 665 if (link_enc == NULL) 666 return; 667 668 /* otg instance */ 669 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 670 671 /* dig front end */ 672 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 673 674 /* stream encoder index */ 675 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 676 if (dp_is_128b_132b_signal(pipe_ctx)) 677 config.stream_enc_idx = 678 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 679 680 /* dig back end */ 681 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 682 683 /* link encoder index */ 684 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 685 if (dp_is_128b_132b_signal(pipe_ctx)) 686 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 687 688 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 689 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 690 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 691 else 692 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 693 694 695 /* phy index */ 696 config.phy_idx = resource_transmitter_to_phy_idx( 697 pipe_ctx->stream->link->dc, link_enc->transmitter); 698 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 699 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 700 config.phy_idx = 0; 701 702 /* stream properties */ 703 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 704 config.mst_enabled = (pipe_ctx->stream->signal == 705 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 706 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 707 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 708 1 : 0; 709 config.dpms_off = dpms_off; 710 711 /* dm stream context */ 712 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 713 714 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 715 } 716 717 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 718 { 719 struct dc *dc = pipe_ctx->stream->ctx->dc; 720 721 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 722 return; 723 724 dc->hwss.set_avmute(pipe_ctx, enable); 725 } 726 727 static void enable_mst_on_sink(struct dc_link *link, bool enable) 728 { 729 unsigned char mstmCntl = 0; 730 731 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 732 if (enable) 733 mstmCntl |= DP_MST_EN; 734 else 735 mstmCntl &= (~DP_MST_EN); 736 737 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 738 } 739 740 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 741 struct dsc_optc_config *config) 742 { 743 uint32_t precision = 1 << 28; 744 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 745 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 746 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 747 DC_LOGGER_INIT(dsc->ctx->logger); 748 749 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 750 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 751 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 752 */ 753 ll_bytes_per_pix_fraq *= 10000000; 754 ll_bytes_per_pix_fraq /= precision; 755 756 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 757 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 758 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 759 DC_LOG_DSC("\tslice_width %d", config->slice_width); 760 } 761 762 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 763 { 764 struct dc *dc = pipe_ctx->stream->ctx->dc; 765 struct dc_stream_state *stream = pipe_ctx->stream; 766 bool result = false; 767 768 if (dc_is_virtual_signal(stream->signal)) 769 result = true; 770 else 771 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 772 return result; 773 } 774 775 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 776 * i.e. after dp_enable_dsc_on_rx() had been called 777 */ 778 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 779 { 780 /* TODO: Move this to HWSS as this is hardware programming sequence not a 781 * link layer sequence 782 */ 783 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 784 struct dc *dc = pipe_ctx->stream->ctx->dc; 785 struct dc_stream_state *stream = pipe_ctx->stream; 786 struct pipe_ctx *odm_pipe; 787 int opp_cnt = 1; 788 struct dccg *dccg = dc->res_pool->dccg; 789 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 790 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 791 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 792 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 793 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 794 * this problem. We are implementing a workaround here to keep using dscclk 795 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 796 * 48Mhz) pixel clock to avoid hitting this problem. 797 */ 798 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 799 stream->timing.pix_clk_100hz > 480000; 800 DC_LOGGER_INIT(dsc->ctx->logger); 801 802 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 803 opp_cnt++; 804 805 if (enable) { 806 struct dsc_config dsc_cfg; 807 struct dsc_optc_config dsc_optc_cfg = {0}; 808 enum optc_dsc_mode optc_dsc_mode; 809 810 /* Enable DSC hw block */ 811 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 812 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 813 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 814 dsc_cfg.color_depth = stream->timing.display_color_depth; 815 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 816 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 817 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 818 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 819 820 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 821 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 822 if (should_use_dto_dscclk) 823 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, true); 824 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 825 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 826 827 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 828 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 829 if (should_use_dto_dscclk) 830 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, true); 831 } 832 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 833 dsc_cfg.pic_width *= opp_cnt; 834 835 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 836 837 /* Enable DSC in encoder */ 838 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 839 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 840 dsc_optc_config_log(dsc, &dsc_optc_cfg); 841 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 842 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 843 optc_dsc_mode, 844 dsc_optc_cfg.bytes_per_pixel, 845 dsc_optc_cfg.slice_width); 846 847 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 848 } 849 850 /* Enable DSC in OPTC */ 851 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 852 dsc_optc_config_log(dsc, &dsc_optc_cfg); 853 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 854 optc_dsc_mode, 855 dsc_optc_cfg.bytes_per_pixel, 856 dsc_optc_cfg.slice_width); 857 } else { 858 /* disable DSC in OPTC */ 859 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 860 pipe_ctx->stream_res.tg, 861 OPTC_DSC_DISABLED, 0, 0); 862 863 /* disable DSC in stream encoder */ 864 if (dc_is_dp_signal(stream->signal)) { 865 if (dp_is_128b_132b_signal(pipe_ctx)) 866 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 867 pipe_ctx->stream_res.hpo_dp_stream_enc, 868 false, 869 NULL, 870 true); 871 else { 872 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 873 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 874 pipe_ctx->stream_res.stream_enc, 875 OPTC_DSC_DISABLED, 0, 0); 876 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 877 pipe_ctx->stream_res.stream_enc, false, NULL, true); 878 } 879 } 880 881 /* disable DSC block */ 882 if (dccg->funcs->set_dto_dscclk) 883 dccg->funcs->set_dto_dscclk(dccg, pipe_ctx->stream_res.dsc->inst, false); 884 pipe_ctx->stream_res.dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc); 885 if (dccg->funcs->set_ref_dscclk) 886 dccg->funcs->set_ref_dscclk(dccg, pipe_ctx->stream_res.dsc->inst); 887 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 888 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 889 if (dccg->funcs->set_dto_dscclk) 890 dccg->funcs->set_dto_dscclk(dccg, odm_pipe->stream_res.dsc->inst, false); 891 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 892 if (dccg->funcs->set_ref_dscclk) 893 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 894 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 895 } 896 } 897 } 898 899 /* 900 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 901 * hence PPS info packet update need to use frame update instead of immediate update. 902 * Added parameter immediate_update for this purpose. 903 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 904 * which is the only place where a "false" would be passed in for param immediate_update. 905 * 906 * immediate_update is only applicable when DSC is enabled. 907 */ 908 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 909 { 910 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 911 struct dc_stream_state *stream = pipe_ctx->stream; 912 913 if (!pipe_ctx->stream->timing.flags.DSC) 914 return false; 915 916 if (!dsc) 917 return false; 918 919 DC_LOGGER_INIT(dsc->ctx->logger); 920 921 if (enable) { 922 struct dsc_config dsc_cfg; 923 uint8_t dsc_packed_pps[128]; 924 925 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 926 memset(dsc_packed_pps, 0, 128); 927 928 /* Enable DSC hw block */ 929 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 930 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 931 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 932 dsc_cfg.color_depth = stream->timing.display_color_depth; 933 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 934 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 935 936 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 937 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 938 if (dc_is_dp_signal(stream->signal)) { 939 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 940 if (dp_is_128b_132b_signal(pipe_ctx)) 941 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 942 pipe_ctx->stream_res.hpo_dp_stream_enc, 943 true, 944 &dsc_packed_pps[0], 945 immediate_update); 946 else 947 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 948 pipe_ctx->stream_res.stream_enc, 949 true, 950 &dsc_packed_pps[0], 951 immediate_update); 952 } 953 } else { 954 /* disable DSC PPS in stream encoder */ 955 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 956 if (dc_is_dp_signal(stream->signal)) { 957 if (dp_is_128b_132b_signal(pipe_ctx)) 958 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 959 pipe_ctx->stream_res.hpo_dp_stream_enc, 960 false, 961 NULL, 962 true); 963 else 964 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 965 pipe_ctx->stream_res.stream_enc, false, NULL, true); 966 } 967 } 968 969 return true; 970 } 971 972 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 973 { 974 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 975 bool result = false; 976 977 if (!pipe_ctx->stream->timing.flags.DSC) 978 goto out; 979 if (!dsc) 980 goto out; 981 982 if (enable) { 983 { 984 link_set_dsc_on_stream(pipe_ctx, true); 985 result = true; 986 } 987 } else { 988 dp_set_dsc_on_rx(pipe_ctx, false); 989 link_set_dsc_on_stream(pipe_ctx, false); 990 result = true; 991 } 992 out: 993 return result; 994 } 995 996 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 997 { 998 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 999 1000 if (!pipe_ctx->stream->timing.flags.DSC) 1001 return false; 1002 if (!dsc) 1003 return false; 1004 1005 link_set_dsc_on_stream(pipe_ctx, true); 1006 link_set_dsc_pps_packet(pipe_ctx, true, false); 1007 return true; 1008 } 1009 1010 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1011 { 1012 struct dc_stream_state *stream = pipe_ctx->stream; 1013 1014 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1015 struct dc_link *link = stream->link; 1016 union down_spread_ctrl old_downspread; 1017 union down_spread_ctrl new_downspread; 1018 1019 memset(&old_downspread, 0, sizeof(old_downspread)); 1020 1021 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1022 &old_downspread.raw, sizeof(old_downspread)); 1023 1024 new_downspread.raw = old_downspread.raw; 1025 1026 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1027 (stream->ignore_msa_timing_param) ? 1 : 0; 1028 1029 if (new_downspread.raw != old_downspread.raw) { 1030 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1031 &new_downspread.raw, sizeof(new_downspread)); 1032 } 1033 1034 } else { 1035 dm_helpers_mst_enable_stream_features(stream); 1036 } 1037 } 1038 1039 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1040 { 1041 const uint32_t VCP_Y_PRECISION = 1000; 1042 uint64_t vcp_x, vcp_y; 1043 DC_LOGGER_INIT(link->ctx->logger); 1044 1045 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1046 avg_time_slots_per_mtp = dc_fixpt_add( 1047 avg_time_slots_per_mtp, 1048 dc_fixpt_from_fraction( 1049 1, 1050 2*VCP_Y_PRECISION)); 1051 1052 vcp_x = dc_fixpt_floor( 1053 avg_time_slots_per_mtp); 1054 vcp_y = dc_fixpt_floor( 1055 dc_fixpt_mul_int( 1056 dc_fixpt_sub_int( 1057 avg_time_slots_per_mtp, 1058 dc_fixpt_floor( 1059 avg_time_slots_per_mtp)), 1060 VCP_Y_PRECISION)); 1061 1062 1063 if (link->type == dc_connection_mst_branch) 1064 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1065 "X: %llu " 1066 "Y: %llu/%d", 1067 vcp_x, 1068 vcp_y, 1069 VCP_Y_PRECISION); 1070 else 1071 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1072 "X: %llu " 1073 "Y: %llu/%d", 1074 vcp_x, 1075 vcp_y, 1076 VCP_Y_PRECISION); 1077 } 1078 1079 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1080 { 1081 struct fixed31_32 mbytes_per_sec; 1082 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1083 &stream->link->cur_link_settings); 1084 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1085 1086 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1087 1088 return dc_fixpt_div_int(mbytes_per_sec, 54); 1089 } 1090 1091 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1092 { 1093 struct fixed31_32 peak_kbps; 1094 uint32_t numerator = 0; 1095 uint32_t denominator = 1; 1096 1097 /* 1098 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1099 * required when determining PBN/time slot utilization on the link between 1100 * us and the branch, since that overhead is already accounted for in 1101 * the get_pbn_per_slot function. 1102 * 1103 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1104 * common multiplier to render an integer PBN for all link rate/lane 1105 * counts combinations 1106 * calculate 1107 * peak_kbps *= (64/54) 1108 * peak_kbps /= (8 * 1000) convert to bytes 1109 */ 1110 1111 numerator = 64; 1112 denominator = 54 * 8 * 1000; 1113 kbps *= numerator; 1114 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1115 1116 return peak_kbps; 1117 } 1118 1119 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1120 { 1121 uint64_t kbps; 1122 enum dc_link_encoding_format link_encoding; 1123 1124 if (dp_is_128b_132b_signal(pipe_ctx)) 1125 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1126 else 1127 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1128 1129 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1130 return get_pbn_from_bw_in_kbps(kbps); 1131 } 1132 1133 1134 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1135 static void get_lane_status( 1136 struct dc_link *link, 1137 uint32_t lane_count, 1138 union lane_status *status, 1139 union lane_align_status_updated *status_updated) 1140 { 1141 unsigned int lane; 1142 uint8_t dpcd_buf[3] = {0}; 1143 1144 if (status == NULL || status_updated == NULL) { 1145 return; 1146 } 1147 1148 core_link_read_dpcd( 1149 link, 1150 DP_LANE0_1_STATUS, 1151 dpcd_buf, 1152 sizeof(dpcd_buf)); 1153 1154 for (lane = 0; lane < lane_count; lane++) { 1155 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1156 } 1157 1158 status_updated->raw = dpcd_buf[2]; 1159 } 1160 1161 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1162 { 1163 /* 1164 * wait for ACT handled 1165 */ 1166 int i; 1167 const int act_retries = 30; 1168 enum act_return_status result = ACT_FAILED; 1169 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1170 union payload_table_update_status update_status = {0}; 1171 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1172 union lane_align_status_updated lane_status_updated; 1173 DC_LOGGER_INIT(link->ctx->logger); 1174 1175 if (!display_connected || link->aux_access_disabled) 1176 return true; 1177 for (i = 0; i < act_retries; i++) { 1178 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1179 1180 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1181 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1182 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1183 !dp_is_interlane_aligned(lane_status_updated)) { 1184 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1185 "polling for ACT handled."); 1186 result = ACT_LINK_LOST; 1187 break; 1188 } 1189 core_link_read_dpcd( 1190 link, 1191 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1192 &update_status.raw, 1193 1); 1194 1195 if (update_status.bits.ACT_HANDLED == 1) { 1196 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1197 result = ACT_SUCCESS; 1198 break; 1199 } 1200 1201 fsleep(5000); 1202 } 1203 1204 if (result == ACT_FAILED) { 1205 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1206 "continue on. Something is wrong with the branch."); 1207 } 1208 1209 return (result == ACT_SUCCESS); 1210 } 1211 1212 static void update_mst_stream_alloc_table( 1213 struct dc_link *link, 1214 struct stream_encoder *stream_enc, 1215 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1216 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1217 { 1218 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1219 struct link_mst_stream_allocation *dc_alloc; 1220 1221 int i; 1222 int j; 1223 1224 /* if DRM proposed_table has more than one new payload */ 1225 ASSERT(proposed_table->stream_count - 1226 link->mst_stream_alloc_table.stream_count < 2); 1227 1228 /* copy proposed_table to link, add stream encoder */ 1229 for (i = 0; i < proposed_table->stream_count; i++) { 1230 1231 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1232 dc_alloc = 1233 &link->mst_stream_alloc_table.stream_allocations[j]; 1234 1235 if (dc_alloc->vcp_id == 1236 proposed_table->stream_allocations[i].vcp_id) { 1237 1238 work_table[i] = *dc_alloc; 1239 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1240 break; /* exit j loop */ 1241 } 1242 } 1243 1244 /* new vcp_id */ 1245 if (j == link->mst_stream_alloc_table.stream_count) { 1246 work_table[i].vcp_id = 1247 proposed_table->stream_allocations[i].vcp_id; 1248 work_table[i].slot_count = 1249 proposed_table->stream_allocations[i].slot_count; 1250 work_table[i].stream_enc = stream_enc; 1251 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1252 } 1253 } 1254 1255 /* update link->mst_stream_alloc_table with work_table */ 1256 link->mst_stream_alloc_table.stream_count = 1257 proposed_table->stream_count; 1258 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1259 link->mst_stream_alloc_table.stream_allocations[i] = 1260 work_table[i]; 1261 } 1262 1263 static void remove_stream_from_alloc_table( 1264 struct dc_link *link, 1265 struct stream_encoder *dio_stream_enc, 1266 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1267 { 1268 int i = 0; 1269 struct link_mst_stream_allocation_table *table = 1270 &link->mst_stream_alloc_table; 1271 1272 if (hpo_dp_stream_enc) { 1273 for (; i < table->stream_count; i++) 1274 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1275 break; 1276 } else { 1277 for (; i < table->stream_count; i++) 1278 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1279 break; 1280 } 1281 1282 if (i < table->stream_count) { 1283 i++; 1284 for (; i < table->stream_count; i++) 1285 table->stream_allocations[i-1] = table->stream_allocations[i]; 1286 memset(&table->stream_allocations[table->stream_count-1], 0, 1287 sizeof(struct link_mst_stream_allocation)); 1288 table->stream_count--; 1289 } 1290 } 1291 1292 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1293 { 1294 struct dc_stream_state *stream = pipe_ctx->stream; 1295 struct dc_link *link = stream->link; 1296 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1297 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1298 int i; 1299 bool mst_mode = (link->type == dc_connection_mst_branch); 1300 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1301 const struct dc_link_settings empty_link_settings = {0}; 1302 DC_LOGGER_INIT(link->ctx->logger); 1303 1304 /* deallocate_mst_payload is called before disable link. When mode or 1305 * disable/enable monitor, new stream is created which is not in link 1306 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1307 * should not done. For new mode set, map_resources will get engine 1308 * for new stream, so stream_enc->id should be validated until here. 1309 */ 1310 1311 /* slot X.Y */ 1312 if (link_hwss->ext.set_throttled_vcp_size) 1313 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1314 if (link_hwss->ext.set_hblank_min_symbol_width) 1315 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1316 &empty_link_settings, 1317 avg_time_slots_per_mtp); 1318 1319 if (mst_mode) { 1320 /* when link is in mst mode, reply on mst manager to remove 1321 * payload 1322 */ 1323 if (dm_helpers_dp_mst_write_payload_allocation_table( 1324 stream->ctx, 1325 stream, 1326 &proposed_table, 1327 false)) 1328 update_mst_stream_alloc_table( 1329 link, 1330 pipe_ctx->stream_res.stream_enc, 1331 pipe_ctx->stream_res.hpo_dp_stream_enc, 1332 &proposed_table); 1333 else 1334 DC_LOG_WARNING("Failed to update" 1335 "MST allocation table for" 1336 "pipe idx:%d\n", 1337 pipe_ctx->pipe_idx); 1338 } else { 1339 /* when link is no longer in mst mode (mst hub unplugged), 1340 * remove payload with default dc logic 1341 */ 1342 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1343 pipe_ctx->stream_res.hpo_dp_stream_enc); 1344 } 1345 1346 DC_LOG_MST("%s" 1347 "stream_count: %d: ", 1348 __func__, 1349 link->mst_stream_alloc_table.stream_count); 1350 1351 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1352 DC_LOG_MST("stream_enc[%d]: %p " 1353 "stream[%d].hpo_dp_stream_enc: %p " 1354 "stream[%d].vcp_id: %d " 1355 "stream[%d].slot_count: %d\n", 1356 i, 1357 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1358 i, 1359 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1360 i, 1361 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1362 i, 1363 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1364 } 1365 1366 /* update mst stream allocation table hardware state */ 1367 if (link_hwss->ext.update_stream_allocation_table == NULL || 1368 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1369 DC_LOG_DEBUG("Unknown encoding format\n"); 1370 return DC_ERROR_UNEXPECTED; 1371 } 1372 1373 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1374 &link->mst_stream_alloc_table); 1375 1376 if (mst_mode) 1377 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1378 stream->ctx, 1379 stream); 1380 1381 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1382 stream->ctx, 1383 stream); 1384 1385 return DC_OK; 1386 } 1387 1388 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1389 * because stream_encoder is not exposed to dm 1390 */ 1391 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1392 { 1393 struct dc_stream_state *stream = pipe_ctx->stream; 1394 struct dc_link *link = stream->link; 1395 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1396 struct fixed31_32 avg_time_slots_per_mtp; 1397 struct fixed31_32 pbn; 1398 struct fixed31_32 pbn_per_slot; 1399 int i; 1400 enum act_return_status ret; 1401 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1402 DC_LOGGER_INIT(link->ctx->logger); 1403 1404 /* enable_link_dp_mst already check link->enabled_stream_count 1405 * and stream is in link->stream[]. This is called during set mode, 1406 * stream_enc is available. 1407 */ 1408 1409 /* get calculate VC payload for stream: stream_alloc */ 1410 if (dm_helpers_dp_mst_write_payload_allocation_table( 1411 stream->ctx, 1412 stream, 1413 &proposed_table, 1414 true)) 1415 update_mst_stream_alloc_table( 1416 link, 1417 pipe_ctx->stream_res.stream_enc, 1418 pipe_ctx->stream_res.hpo_dp_stream_enc, 1419 &proposed_table); 1420 else 1421 DC_LOG_WARNING("Failed to update" 1422 "MST allocation table for" 1423 "pipe idx:%d\n", 1424 pipe_ctx->pipe_idx); 1425 1426 DC_LOG_MST("%s " 1427 "stream_count: %d: \n ", 1428 __func__, 1429 link->mst_stream_alloc_table.stream_count); 1430 1431 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1432 DC_LOG_MST("stream_enc[%d]: %p " 1433 "stream[%d].hpo_dp_stream_enc: %p " 1434 "stream[%d].vcp_id: %d " 1435 "stream[%d].slot_count: %d\n", 1436 i, 1437 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1438 i, 1439 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1440 i, 1441 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1442 i, 1443 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1444 } 1445 1446 ASSERT(proposed_table.stream_count > 0); 1447 1448 /* program DP source TX for payload */ 1449 if (link_hwss->ext.update_stream_allocation_table == NULL || 1450 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1451 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1452 return DC_ERROR_UNEXPECTED; 1453 } 1454 1455 link_hwss->ext.update_stream_allocation_table(link, 1456 &pipe_ctx->link_res, 1457 &link->mst_stream_alloc_table); 1458 1459 /* send down message */ 1460 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1461 stream->ctx, 1462 stream); 1463 1464 if (ret != ACT_LINK_LOST) 1465 dm_helpers_dp_mst_send_payload_allocation( 1466 stream->ctx, 1467 stream); 1468 1469 /* slot X.Y for only current stream */ 1470 pbn_per_slot = get_pbn_per_slot(stream); 1471 if (pbn_per_slot.value == 0) { 1472 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1473 return DC_UNSUPPORTED_VALUE; 1474 } 1475 pbn = get_pbn_from_timing(pipe_ctx); 1476 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1477 1478 log_vcp_x_y(link, avg_time_slots_per_mtp); 1479 1480 if (link_hwss->ext.set_throttled_vcp_size) 1481 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1482 if (link_hwss->ext.set_hblank_min_symbol_width) 1483 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1484 &link->cur_link_settings, 1485 avg_time_slots_per_mtp); 1486 1487 return DC_OK; 1488 } 1489 1490 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1491 const struct dc_stream_state *stream, 1492 const struct dc_link *link) 1493 { 1494 struct fixed31_32 link_bw_effective = 1495 dc_fixpt_from_int( 1496 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1497 struct fixed31_32 timeslot_bw_effective = 1498 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1499 struct fixed31_32 timing_bw = 1500 dc_fixpt_from_int( 1501 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1502 dc_link_get_highest_encoding_format(link))); 1503 struct fixed31_32 avg_time_slots_per_mtp = 1504 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1505 1506 return avg_time_slots_per_mtp; 1507 } 1508 1509 1510 static bool write_128b_132b_sst_payload_allocation_table( 1511 const struct dc_stream_state *stream, 1512 struct dc_link *link, 1513 struct link_mst_stream_allocation_table *proposed_table, 1514 bool allocate) 1515 { 1516 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1517 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1518 bool result = false; 1519 uint8_t req_slot_count = 0; 1520 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1521 union payload_table_update_status update_status = { 0 }; 1522 const uint32_t max_retries = 30; 1523 uint32_t retries = 0; 1524 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1525 DC_LOGGER_INIT(link->ctx->logger); 1526 1527 if (allocate) { 1528 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1529 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1530 /// Validation should filter out modes that exceed link BW 1531 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1532 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1533 return false; 1534 } else { 1535 /// Leave req_slot_count = 0 if allocate is false. 1536 } 1537 1538 proposed_table->stream_count = 1; /// Always 1 stream for SST 1539 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1540 proposed_table->stream_allocations[0].vcp_id = vc_id; 1541 1542 if (!display_connected || link->aux_access_disabled) 1543 return true; 1544 1545 /// Write DPCD 2C0 = 1 to start updating 1546 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1547 core_link_write_dpcd( 1548 link, 1549 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1550 &update_status.raw, 1551 1); 1552 1553 /// Program the changes in DPCD 1C0 - 1C2 1554 ASSERT(vc_id == 1); 1555 core_link_write_dpcd( 1556 link, 1557 DP_PAYLOAD_ALLOCATE_SET, 1558 &vc_id, 1559 1); 1560 1561 ASSERT(start_time_slot == 0); 1562 core_link_write_dpcd( 1563 link, 1564 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1565 &start_time_slot, 1566 1); 1567 1568 core_link_write_dpcd( 1569 link, 1570 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1571 &req_slot_count, 1572 1); 1573 1574 /// Poll till DPCD 2C0 read 1 1575 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1576 1577 while (retries < max_retries) { 1578 if (core_link_read_dpcd( 1579 link, 1580 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1581 &update_status.raw, 1582 1) == DC_OK) { 1583 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1584 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1585 result = true; 1586 break; 1587 } 1588 } else { 1589 union dpcd_rev dpcdRev = {0}; 1590 1591 if (core_link_read_dpcd( 1592 link, 1593 DP_DPCD_REV, 1594 &dpcdRev.raw, 1595 1) != DC_OK) { 1596 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1597 "of sink while polling payload table " 1598 "updated status bit."); 1599 break; 1600 } 1601 } 1602 retries++; 1603 fsleep(5000); 1604 } 1605 1606 if (!result && retries == max_retries) { 1607 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1608 "continue on. Something is wrong with the branch."); 1609 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1610 } 1611 1612 return result; 1613 } 1614 1615 /* 1616 * Payload allocation/deallocation for SST introduced in DP2.0 1617 */ 1618 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1619 bool allocate) 1620 { 1621 struct dc_stream_state *stream = pipe_ctx->stream; 1622 struct dc_link *link = stream->link; 1623 struct link_mst_stream_allocation_table proposed_table = {0}; 1624 struct fixed31_32 avg_time_slots_per_mtp; 1625 const struct dc_link_settings empty_link_settings = {0}; 1626 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1627 DC_LOGGER_INIT(link->ctx->logger); 1628 1629 /* slot X.Y for SST payload deallocate */ 1630 if (!allocate) { 1631 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1632 1633 log_vcp_x_y(link, avg_time_slots_per_mtp); 1634 1635 if (link_hwss->ext.set_throttled_vcp_size) 1636 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1637 avg_time_slots_per_mtp); 1638 if (link_hwss->ext.set_hblank_min_symbol_width) 1639 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1640 &empty_link_settings, 1641 avg_time_slots_per_mtp); 1642 } 1643 1644 /* calculate VC payload and update branch with new payload allocation table*/ 1645 if (!write_128b_132b_sst_payload_allocation_table( 1646 stream, 1647 link, 1648 &proposed_table, 1649 allocate)) { 1650 DC_LOG_ERROR("SST Update Payload: Failed to update " 1651 "allocation table for " 1652 "pipe idx: %d\n", 1653 pipe_ctx->pipe_idx); 1654 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1655 } 1656 1657 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1658 1659 ASSERT(proposed_table.stream_count == 1); 1660 1661 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1662 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1663 "vcp_id: %d " 1664 "slot_count: %d\n", 1665 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1666 proposed_table.stream_allocations[0].vcp_id, 1667 proposed_table.stream_allocations[0].slot_count); 1668 1669 /* program DP source TX for payload */ 1670 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1671 &proposed_table); 1672 1673 /* poll for ACT handled */ 1674 if (!poll_for_allocation_change_trigger(link)) { 1675 // Failures will result in blackscreen and errors logged 1676 BREAK_TO_DEBUGGER(); 1677 } 1678 1679 /* slot X.Y for SST payload allocate */ 1680 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1681 DP_128b_132b_ENCODING) { 1682 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1683 1684 log_vcp_x_y(link, avg_time_slots_per_mtp); 1685 1686 if (link_hwss->ext.set_throttled_vcp_size) 1687 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1688 avg_time_slots_per_mtp); 1689 if (link_hwss->ext.set_hblank_min_symbol_width) 1690 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1691 &link->cur_link_settings, 1692 avg_time_slots_per_mtp); 1693 } 1694 1695 /* Always return DC_OK. 1696 * If part of sequence fails, log failure(s) and show blackscreen 1697 */ 1698 return DC_OK; 1699 } 1700 1701 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1702 { 1703 struct dc_stream_state *stream = pipe_ctx->stream; 1704 struct dc_link *link = stream->link; 1705 struct fixed31_32 avg_time_slots_per_mtp; 1706 struct fixed31_32 pbn; 1707 struct fixed31_32 pbn_per_slot; 1708 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1709 uint8_t i; 1710 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1711 DC_LOGGER_INIT(link->ctx->logger); 1712 1713 /* decrease throttled vcp size */ 1714 pbn_per_slot = get_pbn_per_slot(stream); 1715 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1716 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1717 1718 if (link_hwss->ext.set_throttled_vcp_size) 1719 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1720 if (link_hwss->ext.set_hblank_min_symbol_width) 1721 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1722 &link->cur_link_settings, 1723 avg_time_slots_per_mtp); 1724 1725 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1726 dm_helpers_dp_mst_send_payload_allocation( 1727 stream->ctx, 1728 stream); 1729 1730 /* notify immediate branch device table update */ 1731 if (dm_helpers_dp_mst_write_payload_allocation_table( 1732 stream->ctx, 1733 stream, 1734 &proposed_table, 1735 true)) { 1736 /* update mst stream allocation table software state */ 1737 update_mst_stream_alloc_table( 1738 link, 1739 pipe_ctx->stream_res.stream_enc, 1740 pipe_ctx->stream_res.hpo_dp_stream_enc, 1741 &proposed_table); 1742 } else { 1743 DC_LOG_WARNING("Failed to update" 1744 "MST allocation table for" 1745 "pipe idx:%d\n", 1746 pipe_ctx->pipe_idx); 1747 } 1748 1749 DC_LOG_MST("%s " 1750 "stream_count: %d: \n ", 1751 __func__, 1752 link->mst_stream_alloc_table.stream_count); 1753 1754 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1755 DC_LOG_MST("stream_enc[%d]: %p " 1756 "stream[%d].hpo_dp_stream_enc: %p " 1757 "stream[%d].vcp_id: %d " 1758 "stream[%d].slot_count: %d\n", 1759 i, 1760 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1761 i, 1762 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1763 i, 1764 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1765 i, 1766 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1767 } 1768 1769 ASSERT(proposed_table.stream_count > 0); 1770 1771 /* update mst stream allocation table hardware state */ 1772 if (link_hwss->ext.update_stream_allocation_table == NULL || 1773 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1774 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1775 return DC_ERROR_UNEXPECTED; 1776 } 1777 1778 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1779 &link->mst_stream_alloc_table); 1780 1781 /* poll for immediate branch device ACT handled */ 1782 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1783 stream->ctx, 1784 stream); 1785 1786 return DC_OK; 1787 } 1788 1789 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1790 { 1791 struct dc_stream_state *stream = pipe_ctx->stream; 1792 struct dc_link *link = stream->link; 1793 struct fixed31_32 avg_time_slots_per_mtp; 1794 struct fixed31_32 pbn; 1795 struct fixed31_32 pbn_per_slot; 1796 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1797 uint8_t i; 1798 enum act_return_status ret; 1799 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1800 DC_LOGGER_INIT(link->ctx->logger); 1801 1802 /* notify immediate branch device table update */ 1803 if (dm_helpers_dp_mst_write_payload_allocation_table( 1804 stream->ctx, 1805 stream, 1806 &proposed_table, 1807 true)) { 1808 /* update mst stream allocation table software state */ 1809 update_mst_stream_alloc_table( 1810 link, 1811 pipe_ctx->stream_res.stream_enc, 1812 pipe_ctx->stream_res.hpo_dp_stream_enc, 1813 &proposed_table); 1814 } 1815 1816 DC_LOG_MST("%s " 1817 "stream_count: %d: \n ", 1818 __func__, 1819 link->mst_stream_alloc_table.stream_count); 1820 1821 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1822 DC_LOG_MST("stream_enc[%d]: %p " 1823 "stream[%d].hpo_dp_stream_enc: %p " 1824 "stream[%d].vcp_id: %d " 1825 "stream[%d].slot_count: %d\n", 1826 i, 1827 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1828 i, 1829 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1830 i, 1831 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1832 i, 1833 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1834 } 1835 1836 ASSERT(proposed_table.stream_count > 0); 1837 1838 /* update mst stream allocation table hardware state */ 1839 if (link_hwss->ext.update_stream_allocation_table == NULL || 1840 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1841 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1842 return DC_ERROR_UNEXPECTED; 1843 } 1844 1845 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1846 &link->mst_stream_alloc_table); 1847 1848 /* poll for immediate branch device ACT handled */ 1849 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1850 stream->ctx, 1851 stream); 1852 1853 if (ret != ACT_LINK_LOST) { 1854 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1855 dm_helpers_dp_mst_send_payload_allocation( 1856 stream->ctx, 1857 stream); 1858 } 1859 1860 /* increase throttled vcp size */ 1861 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1862 pbn_per_slot = get_pbn_per_slot(stream); 1863 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1864 1865 if (link_hwss->ext.set_throttled_vcp_size) 1866 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1867 if (link_hwss->ext.set_hblank_min_symbol_width) 1868 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1869 &link->cur_link_settings, 1870 avg_time_slots_per_mtp); 1871 1872 return DC_OK; 1873 } 1874 1875 static void disable_link_dp(struct dc_link *link, 1876 const struct link_resource *link_res, 1877 enum signal_type signal) 1878 { 1879 struct dc_link_settings link_settings = link->cur_link_settings; 1880 1881 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1882 link->mst_stream_alloc_table.stream_count > 0) 1883 /* disable MST link only when last vc payload is deallocated */ 1884 return; 1885 1886 dp_disable_link_phy(link, link_res, signal); 1887 1888 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1889 if (!link->skip_implict_edp_power_control) 1890 link->dc->hwss.edp_power_control(link, false); 1891 } 1892 1893 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1894 /* set the sink to SST mode after disabling the link */ 1895 enable_mst_on_sink(link, false); 1896 1897 if (link_dp_get_encoding_format(&link_settings) == 1898 DP_8b_10b_ENCODING) { 1899 dp_set_fec_enable(link, false); 1900 dp_set_fec_ready(link, link_res, false); 1901 } 1902 } 1903 1904 static void disable_link(struct dc_link *link, 1905 const struct link_resource *link_res, 1906 enum signal_type signal) 1907 { 1908 if (dc_is_dp_signal(signal)) { 1909 disable_link_dp(link, link_res, signal); 1910 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1911 link->dc->hwss.disable_link_output(link, link_res, signal); 1912 } 1913 1914 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1915 /* MST disable link only when no stream use the link */ 1916 if (link->mst_stream_alloc_table.stream_count <= 0) 1917 link->link_status.link_active = false; 1918 } else { 1919 link->link_status.link_active = false; 1920 } 1921 } 1922 1923 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1924 { 1925 struct dc_stream_state *stream = pipe_ctx->stream; 1926 struct dc_link *link = stream->link; 1927 enum dc_color_depth display_color_depth; 1928 enum engine_id eng_id; 1929 struct ext_hdmi_settings settings = {0}; 1930 bool is_over_340mhz = false; 1931 bool is_vga_mode = (stream->timing.h_addressable == 640) 1932 && (stream->timing.v_addressable == 480); 1933 struct dc *dc = pipe_ctx->stream->ctx->dc; 1934 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1935 1936 if (stream->phy_pix_clk == 0) 1937 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1938 if (stream->phy_pix_clk > 340000) 1939 is_over_340mhz = true; 1940 1941 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1942 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1943 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1944 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1945 /* DP159, Retimer settings */ 1946 eng_id = pipe_ctx->stream_res.stream_enc->id; 1947 1948 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1949 write_i2c_retimer_setting(pipe_ctx, 1950 is_vga_mode, is_over_340mhz, &settings); 1951 } else { 1952 write_i2c_default_retimer_setting(pipe_ctx, 1953 is_vga_mode, is_over_340mhz); 1954 } 1955 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1956 /* PI3EQX1204, Redriver settings */ 1957 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1958 } 1959 } 1960 1961 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1962 write_scdc_data( 1963 stream->link->ddc, 1964 stream->phy_pix_clk, 1965 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 1966 1967 memset(&stream->link->cur_link_settings, 0, 1968 sizeof(struct dc_link_settings)); 1969 1970 display_color_depth = stream->timing.display_color_depth; 1971 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1972 display_color_depth = COLOR_DEPTH_888; 1973 1974 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 1975 * character clock in case that beyond 340MHz. 1976 */ 1977 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 1978 link_hwss->setup_stream_encoder(pipe_ctx); 1979 1980 dc->hwss.enable_tmds_link_output( 1981 link, 1982 &pipe_ctx->link_res, 1983 pipe_ctx->stream->signal, 1984 pipe_ctx->clock_source->id, 1985 display_color_depth, 1986 stream->phy_pix_clk); 1987 1988 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1989 read_scdc_data(link->ddc); 1990 } 1991 1992 static enum dc_status enable_link_dp(struct dc_state *state, 1993 struct pipe_ctx *pipe_ctx) 1994 { 1995 struct dc_stream_state *stream = pipe_ctx->stream; 1996 enum dc_status status; 1997 bool skip_video_pattern; 1998 struct dc_link *link = stream->link; 1999 const struct dc_link_settings *link_settings = 2000 &pipe_ctx->link_config.dp_link_settings; 2001 bool fec_enable; 2002 int i; 2003 bool apply_seamless_boot_optimization = false; 2004 uint32_t bl_oled_enable_delay = 50; // in ms 2005 uint32_t post_oui_delay = 30; // 30ms 2006 /* Reduce link bandwidth between failed link training attempts. */ 2007 bool do_fallback = false; 2008 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2009 2010 // Increase retry count if attempting DP1.x on FIXED_VS link 2011 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2012 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2013 lt_attempts = 10; 2014 2015 // check for seamless boot 2016 for (i = 0; i < state->stream_count; i++) { 2017 if (state->streams[i]->apply_seamless_boot_optimization) { 2018 apply_seamless_boot_optimization = true; 2019 break; 2020 } 2021 } 2022 2023 /* Train with fallback when enabling DPIA link. Conventional links are 2024 * trained with fallback during sink detection. 2025 */ 2026 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2027 do_fallback = true; 2028 2029 /* 2030 * Temporary w/a to get DP2.0 link rates to work with SST. 2031 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2032 */ 2033 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2034 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2035 link->dc->debug.set_mst_en_for_sst) { 2036 enable_mst_on_sink(link, true); 2037 } 2038 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2039 /*in case it is not on*/ 2040 if (!link->dc->config.edp_no_power_sequencing) 2041 link->dc->hwss.edp_power_control(link, true); 2042 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2043 } 2044 2045 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2046 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2047 } else { 2048 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2049 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2050 if (state->clk_mgr && !apply_seamless_boot_optimization) 2051 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2052 state, false); 2053 } 2054 2055 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2056 dpcd_set_source_specific_data(link); 2057 if (link->dpcd_sink_ext_caps.raw != 0) { 2058 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2059 msleep(post_oui_delay); 2060 } 2061 2062 // similarly, mode switch can cause loss of cable ID 2063 dpcd_write_cable_id_to_dprx(link); 2064 2065 skip_video_pattern = true; 2066 2067 if (link_settings->link_rate == LINK_RATE_LOW) 2068 skip_video_pattern = false; 2069 2070 if (perform_link_training_with_retries(link_settings, 2071 skip_video_pattern, 2072 lt_attempts, 2073 pipe_ctx, 2074 pipe_ctx->stream->signal, 2075 do_fallback)) { 2076 status = DC_OK; 2077 } else { 2078 status = DC_FAIL_DP_LINK_TRAINING; 2079 } 2080 2081 if (link->preferred_training_settings.fec_enable) 2082 fec_enable = *link->preferred_training_settings.fec_enable; 2083 else 2084 fec_enable = true; 2085 2086 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2087 dp_set_fec_enable(link, fec_enable); 2088 2089 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2090 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2091 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2092 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2093 set_default_brightness_aux(link); 2094 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2095 msleep(bl_oled_enable_delay); 2096 edp_backlight_enable_aux(link, true); 2097 } 2098 2099 return status; 2100 } 2101 2102 static enum dc_status enable_link_edp( 2103 struct dc_state *state, 2104 struct pipe_ctx *pipe_ctx) 2105 { 2106 return enable_link_dp(state, pipe_ctx); 2107 } 2108 2109 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2110 { 2111 struct dc_stream_state *stream = pipe_ctx->stream; 2112 struct dc_link *link = stream->link; 2113 struct dc *dc = stream->ctx->dc; 2114 2115 if (stream->phy_pix_clk == 0) 2116 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2117 2118 memset(&stream->link->cur_link_settings, 0, 2119 sizeof(struct dc_link_settings)); 2120 dc->hwss.enable_lvds_link_output( 2121 link, 2122 &pipe_ctx->link_res, 2123 pipe_ctx->clock_source->id, 2124 stream->phy_pix_clk); 2125 2126 } 2127 2128 static enum dc_status enable_link_dp_mst( 2129 struct dc_state *state, 2130 struct pipe_ctx *pipe_ctx) 2131 { 2132 struct dc_link *link = pipe_ctx->stream->link; 2133 unsigned char mstm_cntl = 0; 2134 2135 /* sink signal type after MST branch is MST. Multiple MST sinks 2136 * share one link. Link DP PHY is enable or training only once. 2137 */ 2138 if (link->link_status.link_active) 2139 return DC_OK; 2140 2141 /* clear payload table */ 2142 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2143 if (mstm_cntl & DP_MST_EN) 2144 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2145 2146 /* to make sure the pending down rep can be processed 2147 * before enabling the link 2148 */ 2149 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2150 2151 /* set the sink to MST mode before enabling the link */ 2152 enable_mst_on_sink(link, true); 2153 2154 return enable_link_dp(state, pipe_ctx); 2155 } 2156 2157 static enum dc_status enable_link( 2158 struct dc_state *state, 2159 struct pipe_ctx *pipe_ctx) 2160 { 2161 enum dc_status status = DC_ERROR_UNEXPECTED; 2162 struct dc_stream_state *stream = pipe_ctx->stream; 2163 struct dc_link *link = stream->link; 2164 2165 /* There's some scenarios where driver is unloaded with display 2166 * still enabled. When driver is reloaded, it may cause a display 2167 * to not light up if there is a mismatch between old and new 2168 * link settings. Need to call disable first before enabling at 2169 * new link settings. 2170 */ 2171 if (link->link_status.link_active) 2172 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2173 2174 switch (pipe_ctx->stream->signal) { 2175 case SIGNAL_TYPE_DISPLAY_PORT: 2176 status = enable_link_dp(state, pipe_ctx); 2177 break; 2178 case SIGNAL_TYPE_EDP: 2179 status = enable_link_edp(state, pipe_ctx); 2180 break; 2181 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2182 status = enable_link_dp_mst(state, pipe_ctx); 2183 msleep(200); 2184 break; 2185 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2186 case SIGNAL_TYPE_DVI_DUAL_LINK: 2187 case SIGNAL_TYPE_HDMI_TYPE_A: 2188 enable_link_hdmi(pipe_ctx); 2189 status = DC_OK; 2190 break; 2191 case SIGNAL_TYPE_LVDS: 2192 enable_link_lvds(pipe_ctx); 2193 status = DC_OK; 2194 break; 2195 case SIGNAL_TYPE_VIRTUAL: 2196 status = DC_OK; 2197 break; 2198 default: 2199 break; 2200 } 2201 2202 if (status == DC_OK) { 2203 pipe_ctx->stream->link->link_status.link_active = true; 2204 } 2205 2206 return status; 2207 } 2208 2209 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2210 { 2211 struct dc_link *link = stream->sink->link; 2212 int req_bw = bw; 2213 2214 DC_LOGGER_INIT(link->ctx->logger); 2215 2216 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2217 return false; 2218 2219 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2220 int sink_index = 0; 2221 int i = 0; 2222 2223 for (i = 0; i < link->sink_count; i++) { 2224 if (link->remote_sinks[i] == NULL) 2225 continue; 2226 2227 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2228 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2229 else 2230 sink_index = i; 2231 } 2232 2233 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2234 } 2235 2236 /* get dp overhead for dp tunneling */ 2237 link->dpia_bw_alloc_config.dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(link); 2238 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2239 2240 if (link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw)) { 2241 if (req_bw <= link->dpia_bw_alloc_config.allocated_bw) { 2242 DC_LOG_DEBUG("%s, Success in allocate bw for link(%d), allocated_bw(%d), dp_overhead(%d)\n", 2243 __func__, link->link_index, link->dpia_bw_alloc_config.allocated_bw, 2244 link->dpia_bw_alloc_config.dp_overhead); 2245 } else { 2246 // Cannot get the required bandwidth. 2247 DC_LOG_ERROR("%s, Failed to allocate bw for link(%d), allocated_bw(%d), dp_overhead(%d)\n", 2248 __func__, link->link_index, link->dpia_bw_alloc_config.allocated_bw, 2249 link->dpia_bw_alloc_config.dp_overhead); 2250 return false; 2251 } 2252 } else { 2253 DC_LOG_DEBUG("%s, usb4 request bw timeout\n", __func__); 2254 return false; 2255 } 2256 2257 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2258 int i = 0; 2259 2260 for (i = 0; i < link->sink_count; i++) { 2261 if (link->remote_sinks[i] == NULL) 2262 continue; 2263 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2264 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2265 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2266 } 2267 } 2268 2269 return true; 2270 } 2271 2272 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2273 { 2274 bool ret; 2275 2276 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2277 dc_link_get_highest_encoding_format(stream->sink->link)); 2278 2279 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2280 2281 return ret; 2282 } 2283 2284 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2285 { 2286 bool ret; 2287 2288 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2289 2290 return ret; 2291 } 2292 2293 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2294 { 2295 struct dc *dc = pipe_ctx->stream->ctx->dc; 2296 struct dc_stream_state *stream = pipe_ctx->stream; 2297 struct dc_link *link = stream->sink->link; 2298 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2299 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2300 2301 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2302 2303 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2304 2305 if (dp_is_128b_132b_signal(pipe_ctx)) 2306 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2307 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2308 return; 2309 2310 if (pipe_ctx->stream->sink) { 2311 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2312 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2313 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2314 pipe_ctx->stream->sink->edid_caps.display_name, 2315 pipe_ctx->stream->signal); 2316 } 2317 } 2318 2319 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2320 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2321 set_avmute(pipe_ctx, true); 2322 } 2323 2324 dc->hwss.disable_audio_stream(pipe_ctx); 2325 2326 update_psp_stream_config(pipe_ctx, true); 2327 dc->hwss.blank_stream(pipe_ctx); 2328 2329 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2330 deallocate_usb4_bandwidth(pipe_ctx->stream); 2331 2332 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2333 deallocate_mst_payload(pipe_ctx); 2334 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2335 dp_is_128b_132b_signal(pipe_ctx)) 2336 update_sst_payload(pipe_ctx, false); 2337 2338 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2339 struct ext_hdmi_settings settings = {0}; 2340 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2341 2342 unsigned short masked_chip_caps = link->chip_caps & 2343 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2344 //Need to inform that sink is going to use legacy HDMI mode. 2345 write_scdc_data( 2346 link->ddc, 2347 165000,//vbios only handles 165Mhz. 2348 false); 2349 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2350 /* DP159, Retimer settings */ 2351 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2352 write_i2c_retimer_setting(pipe_ctx, 2353 false, false, &settings); 2354 else 2355 write_i2c_default_retimer_setting(pipe_ctx, 2356 false, false); 2357 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2358 /* PI3EQX1204, Redriver settings */ 2359 write_i2c_redriver_setting(pipe_ctx, false); 2360 } 2361 } 2362 2363 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2364 !dp_is_128b_132b_signal(pipe_ctx)) { 2365 2366 /* In DP1.x SST mode, our encoder will go to TPS1 2367 * when link is on but stream is off. 2368 * Disabling link before stream will avoid exposing TPS1 pattern 2369 * during the disable sequence as it will confuse some receivers 2370 * state machine. 2371 * In DP2 or MST mode, our encoder will stay video active 2372 */ 2373 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2374 dc->hwss.disable_stream(pipe_ctx); 2375 } else { 2376 dc->hwss.disable_stream(pipe_ctx); 2377 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2378 } 2379 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2380 2381 if (pipe_ctx->stream->timing.flags.DSC) { 2382 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2383 link_set_dsc_enable(pipe_ctx, false); 2384 } 2385 if (dp_is_128b_132b_signal(pipe_ctx)) { 2386 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2387 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2388 } 2389 2390 if (vpg && vpg->funcs->vpg_powerdown) 2391 vpg->funcs->vpg_powerdown(vpg); 2392 2393 /* for psp not exist case */ 2394 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2395 /* reset internal save state to default since eDP is off */ 2396 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2397 /* since current psp not loaded, we need to reset it to default*/ 2398 link->panel_mode = panel_mode; 2399 } 2400 } 2401 2402 void link_set_dpms_on( 2403 struct dc_state *state, 2404 struct pipe_ctx *pipe_ctx) 2405 { 2406 struct dc *dc = pipe_ctx->stream->ctx->dc; 2407 struct dc_stream_state *stream = pipe_ctx->stream; 2408 struct dc_link *link = stream->sink->link; 2409 enum dc_status status; 2410 struct link_encoder *link_enc; 2411 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2412 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2413 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2414 bool apply_edp_fast_boot_optimization = 2415 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2416 2417 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2418 2419 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2420 2421 if (dp_is_128b_132b_signal(pipe_ctx)) 2422 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2423 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2424 return; 2425 2426 if (pipe_ctx->stream->sink) { 2427 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2428 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2429 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2430 pipe_ctx->stream->sink->edid_caps.display_name, 2431 pipe_ctx->stream->signal); 2432 } 2433 } 2434 2435 link_enc = link_enc_cfg_get_link_enc(link); 2436 ASSERT(link_enc); 2437 2438 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2439 && !dp_is_128b_132b_signal(pipe_ctx)) { 2440 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2441 2442 if (link_enc) 2443 link_enc->funcs->setup( 2444 link_enc, 2445 pipe_ctx->stream->signal); 2446 2447 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2448 stream_enc->funcs->dig_stream_enable( 2449 stream_enc, 2450 pipe_ctx->stream->signal, 1); 2451 } 2452 2453 pipe_ctx->stream->link->link_state_valid = true; 2454 2455 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2456 if (dp_is_128b_132b_signal(pipe_ctx)) 2457 otg_out_dest = OUT_MUX_HPO_DP; 2458 else 2459 otg_out_dest = OUT_MUX_DIO; 2460 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2461 } 2462 2463 link_hwss->setup_stream_attribute(pipe_ctx); 2464 2465 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2466 2467 // Enable VPG before building infoframe 2468 if (vpg && vpg->funcs->vpg_poweron) 2469 vpg->funcs->vpg_poweron(vpg); 2470 2471 resource_build_info_frame(pipe_ctx); 2472 dc->hwss.update_info_frame(pipe_ctx); 2473 2474 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2475 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2476 2477 /* Do not touch link on seamless boot optimization. */ 2478 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2479 pipe_ctx->stream->dpms_off = false; 2480 2481 /* Still enable stream features & audio on seamless boot for DP external displays */ 2482 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2483 enable_stream_features(pipe_ctx); 2484 dc->hwss.enable_audio_stream(pipe_ctx); 2485 } 2486 2487 update_psp_stream_config(pipe_ctx, false); 2488 return; 2489 } 2490 2491 /* eDP lit up by bios already, no need to enable again. */ 2492 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2493 apply_edp_fast_boot_optimization && 2494 !pipe_ctx->stream->timing.flags.DSC && 2495 !pipe_ctx->next_odm_pipe) { 2496 pipe_ctx->stream->dpms_off = false; 2497 update_psp_stream_config(pipe_ctx, false); 2498 return; 2499 } 2500 2501 if (pipe_ctx->stream->dpms_off) 2502 return; 2503 2504 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2505 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2506 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2507 * will be automatically set at a later time when the video is enabled 2508 * (DP_VID_STREAM_EN = 1). 2509 */ 2510 if (pipe_ctx->stream->timing.flags.DSC) { 2511 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2512 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2513 link_set_dsc_enable(pipe_ctx, true); 2514 } 2515 2516 status = enable_link(state, pipe_ctx); 2517 2518 if (status != DC_OK) { 2519 DC_LOG_WARNING("enabling link %u failed: %d\n", 2520 pipe_ctx->stream->link->link_index, 2521 status); 2522 2523 /* Abort stream enable *unless* the failure was due to 2524 * DP link training - some DP monitors will recover and 2525 * show the stream anyway. But MST displays can't proceed 2526 * without link training. 2527 */ 2528 if (status != DC_FAIL_DP_LINK_TRAINING || 2529 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2530 if (false == stream->link->link_status.link_active) 2531 disable_link(stream->link, &pipe_ctx->link_res, 2532 pipe_ctx->stream->signal); 2533 BREAK_TO_DEBUGGER(); 2534 return; 2535 } 2536 } 2537 2538 /* turn off otg test pattern if enable */ 2539 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2540 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2541 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2542 COLOR_DEPTH_UNDEFINED); 2543 2544 /* This second call is needed to reconfigure the DIG 2545 * as a workaround for the incorrect value being applied 2546 * from transmitter control. 2547 */ 2548 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2549 dp_is_128b_132b_signal(pipe_ctx))) { 2550 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2551 2552 if (link_enc) 2553 link_enc->funcs->setup( 2554 link_enc, 2555 pipe_ctx->stream->signal); 2556 2557 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2558 stream_enc->funcs->dig_stream_enable( 2559 stream_enc, 2560 pipe_ctx->stream->signal, 1); 2561 2562 } 2563 2564 dc->hwss.enable_stream(pipe_ctx); 2565 2566 /* Set DPS PPS SDP (AKA "info frames") */ 2567 if (pipe_ctx->stream->timing.flags.DSC) { 2568 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2569 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2570 dp_set_dsc_on_rx(pipe_ctx, true); 2571 link_set_dsc_pps_packet(pipe_ctx, true, true); 2572 } 2573 } 2574 2575 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2576 allocate_usb4_bandwidth(pipe_ctx->stream); 2577 2578 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2579 allocate_mst_payload(pipe_ctx); 2580 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2581 dp_is_128b_132b_signal(pipe_ctx)) 2582 update_sst_payload(pipe_ctx, true); 2583 2584 dc->hwss.unblank_stream(pipe_ctx, 2585 &pipe_ctx->stream->link->cur_link_settings); 2586 2587 if (stream->sink_patches.delay_ignore_msa > 0) 2588 msleep(stream->sink_patches.delay_ignore_msa); 2589 2590 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2591 enable_stream_features(pipe_ctx); 2592 update_psp_stream_config(pipe_ctx, false); 2593 2594 dc->hwss.enable_audio_stream(pipe_ctx); 2595 2596 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2597 set_avmute(pipe_ctx, false); 2598 } 2599 } 2600