1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 144 dpcd_write_rx_power_ctrl(link, false); 145 } 146 } 147 148 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 149 { 150 struct pipe_ctx *pipes[MAX_PIPES]; 151 struct dc_stream_state *streams[MAX_PIPES]; 152 struct dc_state *state = link->dc->current_state; 153 uint8_t count; 154 int i; 155 struct dc_stream_update stream_update; 156 bool dpms_off = true; 157 struct link_resource link_res = {0}; 158 159 memset(&stream_update, 0, sizeof(stream_update)); 160 stream_update.dpms_off = &dpms_off; 161 162 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 163 164 /* The subsequent call to dc_commit_updates_for_stream for a full update 165 * will release the current state and swap to a new state. Releasing the 166 * current state results in the stream pointers in the pipe_ctx structs 167 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream. 168 */ 169 for (i = 0; i < count; i++) 170 streams[i] = pipes[i]->stream; 171 172 for (i = 0; i < count; i++) { 173 stream_update.stream = streams[i]; 174 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 175 streams[i], &stream_update, 176 state); 177 } 178 179 /* link can be also enabled by vbios. In this case it is not recorded 180 * in pipe_ctx. Disable link phy here to make sure it is completely off 181 */ 182 dp_disable_link_phy(link, &link_res, link->connector_signal); 183 } 184 185 void link_resume(struct dc_link *link) 186 { 187 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 188 program_hpd_filter(link); 189 } 190 191 /* This function returns true if the pipe is used to feed video signal directly 192 * to the link. 193 */ 194 static bool is_master_pipe_for_link(const struct dc_link *link, 195 const struct pipe_ctx *pipe) 196 { 197 return resource_is_pipe_type(pipe, OTG_MASTER) && 198 pipe->stream->link == link; 199 } 200 201 /* 202 * This function finds all master pipes feeding to a given link with dpms set to 203 * on in given dc state. 204 */ 205 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 206 struct dc_state *state, 207 uint8_t *count, 208 struct pipe_ctx *pipes[MAX_PIPES]) 209 { 210 int i; 211 struct pipe_ctx *pipe = NULL; 212 213 *count = 0; 214 for (i = 0; i < MAX_PIPES; i++) { 215 pipe = &state->res_ctx.pipe_ctx[i]; 216 217 if (is_master_pipe_for_link(link, pipe) && 218 pipe->stream->dpms_off == false) { 219 pipes[(*count)++] = pipe; 220 } 221 } 222 } 223 224 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 225 enum engine_id eng_id, 226 struct ext_hdmi_settings *settings) 227 { 228 bool result = false; 229 int i = 0; 230 struct integrated_info *integrated_info = 231 pipe_ctx->stream->ctx->dc_bios->integrated_info; 232 233 if (integrated_info == NULL) 234 return false; 235 236 /* 237 * Get retimer settings from sbios for passing SI eye test for DCE11 238 * The setting values are varied based on board revision and port id 239 * Therefore the setting values of each ports is passed by sbios. 240 */ 241 242 // Check if current bios contains ext Hdmi settings 243 if (integrated_info->gpu_cap_info & 0x20) { 244 switch (eng_id) { 245 case ENGINE_ID_DIGA: 246 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 247 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 248 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 249 memmove(settings->reg_settings, 250 integrated_info->dp0_ext_hdmi_reg_settings, 251 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 252 memmove(settings->reg_settings_6g, 253 integrated_info->dp0_ext_hdmi_6g_reg_settings, 254 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 255 result = true; 256 break; 257 case ENGINE_ID_DIGB: 258 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 259 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 260 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 261 memmove(settings->reg_settings, 262 integrated_info->dp1_ext_hdmi_reg_settings, 263 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 264 memmove(settings->reg_settings_6g, 265 integrated_info->dp1_ext_hdmi_6g_reg_settings, 266 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 267 result = true; 268 break; 269 case ENGINE_ID_DIGC: 270 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 271 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 272 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 273 memmove(settings->reg_settings, 274 integrated_info->dp2_ext_hdmi_reg_settings, 275 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 276 memmove(settings->reg_settings_6g, 277 integrated_info->dp2_ext_hdmi_6g_reg_settings, 278 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 279 result = true; 280 break; 281 case ENGINE_ID_DIGD: 282 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 283 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 284 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 285 memmove(settings->reg_settings, 286 integrated_info->dp3_ext_hdmi_reg_settings, 287 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 288 memmove(settings->reg_settings_6g, 289 integrated_info->dp3_ext_hdmi_6g_reg_settings, 290 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 291 result = true; 292 break; 293 default: 294 break; 295 } 296 297 if (result == true) { 298 // Validate settings from bios integrated info table 299 if (settings->slv_addr == 0) 300 return false; 301 if (settings->reg_num > 9) 302 return false; 303 if (settings->reg_num_6g > 3) 304 return false; 305 306 for (i = 0; i < settings->reg_num; i++) { 307 if (settings->reg_settings[i].i2c_reg_index > 0x20) 308 return false; 309 } 310 311 for (i = 0; i < settings->reg_num_6g; i++) { 312 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 313 return false; 314 } 315 } 316 } 317 318 return result; 319 } 320 321 static bool write_i2c(struct pipe_ctx *pipe_ctx, 322 uint8_t address, uint8_t *buffer, uint32_t length) 323 { 324 struct i2c_command cmd = {0}; 325 struct i2c_payload payload = {0}; 326 327 memset(&payload, 0, sizeof(payload)); 328 memset(&cmd, 0, sizeof(cmd)); 329 330 cmd.number_of_payloads = 1; 331 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 332 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 333 334 payload.address = address; 335 payload.data = buffer; 336 payload.length = length; 337 payload.write = true; 338 cmd.payloads = &payload; 339 340 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 341 pipe_ctx->stream->link, &cmd)) 342 return true; 343 344 return false; 345 } 346 347 static void write_i2c_retimer_setting( 348 struct pipe_ctx *pipe_ctx, 349 bool is_vga_mode, 350 bool is_over_340mhz, 351 struct ext_hdmi_settings *settings) 352 { 353 uint8_t slave_address = (settings->slv_addr >> 1); 354 uint8_t buffer[2]; 355 const uint8_t apply_rx_tx_change = 0x4; 356 uint8_t offset = 0xA; 357 uint8_t value = 0; 358 int i = 0; 359 bool i2c_success = false; 360 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 361 362 memset(&buffer, 0, sizeof(buffer)); 363 364 /* Start Ext-Hdmi programming*/ 365 366 for (i = 0; i < settings->reg_num; i++) { 367 /* Apply 3G settings */ 368 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 369 370 buffer[0] = settings->reg_settings[i].i2c_reg_index; 371 buffer[1] = settings->reg_settings[i].i2c_reg_val; 372 i2c_success = write_i2c(pipe_ctx, slave_address, 373 buffer, sizeof(buffer)); 374 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 375 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 376 slave_address, buffer[0], buffer[1], i2c_success?1:0); 377 378 if (!i2c_success) 379 goto i2c_write_fail; 380 381 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 382 * needs to be set to 1 on every 0xA-0xC write. 383 */ 384 if (settings->reg_settings[i].i2c_reg_index == 0xA || 385 settings->reg_settings[i].i2c_reg_index == 0xB || 386 settings->reg_settings[i].i2c_reg_index == 0xC) { 387 388 /* Query current value from offset 0xA */ 389 if (settings->reg_settings[i].i2c_reg_index == 0xA) 390 value = settings->reg_settings[i].i2c_reg_val; 391 else { 392 i2c_success = 393 link_query_ddc_data( 394 pipe_ctx->stream->link->ddc, 395 slave_address, &offset, 1, &value, 1); 396 if (!i2c_success) 397 goto i2c_write_fail; 398 } 399 400 buffer[0] = offset; 401 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 402 buffer[1] = value | apply_rx_tx_change; 403 i2c_success = write_i2c(pipe_ctx, slave_address, 404 buffer, sizeof(buffer)); 405 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 406 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 407 slave_address, buffer[0], buffer[1], i2c_success?1:0); 408 if (!i2c_success) 409 goto i2c_write_fail; 410 } 411 } 412 } 413 414 /* Apply 3G settings */ 415 if (is_over_340mhz) { 416 for (i = 0; i < settings->reg_num_6g; i++) { 417 /* Apply 3G settings */ 418 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 419 420 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 421 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 422 i2c_success = write_i2c(pipe_ctx, slave_address, 423 buffer, sizeof(buffer)); 424 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 425 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 426 slave_address, buffer[0], buffer[1], i2c_success?1:0); 427 428 if (!i2c_success) 429 goto i2c_write_fail; 430 431 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 432 * needs to be set to 1 on every 0xA-0xC write. 433 */ 434 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 435 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 436 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 437 438 /* Query current value from offset 0xA */ 439 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 440 value = settings->reg_settings_6g[i].i2c_reg_val; 441 else { 442 i2c_success = 443 link_query_ddc_data( 444 pipe_ctx->stream->link->ddc, 445 slave_address, &offset, 1, &value, 1); 446 if (!i2c_success) 447 goto i2c_write_fail; 448 } 449 450 buffer[0] = offset; 451 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 452 buffer[1] = value | apply_rx_tx_change; 453 i2c_success = write_i2c(pipe_ctx, slave_address, 454 buffer, sizeof(buffer)); 455 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 456 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 457 slave_address, buffer[0], buffer[1], i2c_success?1:0); 458 if (!i2c_success) 459 goto i2c_write_fail; 460 } 461 } 462 } 463 } 464 465 if (is_vga_mode) { 466 /* Program additional settings if using 640x480 resolution */ 467 468 /* Write offset 0xFF to 0x01 */ 469 buffer[0] = 0xff; 470 buffer[1] = 0x01; 471 i2c_success = write_i2c(pipe_ctx, slave_address, 472 buffer, sizeof(buffer)); 473 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 474 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 475 slave_address, buffer[0], buffer[1], i2c_success?1:0); 476 if (!i2c_success) 477 goto i2c_write_fail; 478 479 /* Write offset 0x00 to 0x23 */ 480 buffer[0] = 0x00; 481 buffer[1] = 0x23; 482 i2c_success = write_i2c(pipe_ctx, slave_address, 483 buffer, sizeof(buffer)); 484 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 485 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 486 slave_address, buffer[0], buffer[1], i2c_success?1:0); 487 if (!i2c_success) 488 goto i2c_write_fail; 489 490 /* Write offset 0xff to 0x00 */ 491 buffer[0] = 0xff; 492 buffer[1] = 0x00; 493 i2c_success = write_i2c(pipe_ctx, slave_address, 494 buffer, sizeof(buffer)); 495 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 496 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 497 slave_address, buffer[0], buffer[1], i2c_success?1:0); 498 if (!i2c_success) 499 goto i2c_write_fail; 500 501 } 502 503 return; 504 505 i2c_write_fail: 506 DC_LOG_DEBUG("Set retimer failed"); 507 } 508 509 static void write_i2c_default_retimer_setting( 510 struct pipe_ctx *pipe_ctx, 511 bool is_vga_mode, 512 bool is_over_340mhz) 513 { 514 uint8_t slave_address = (0xBA >> 1); 515 uint8_t buffer[2]; 516 bool i2c_success = false; 517 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 518 519 memset(&buffer, 0, sizeof(buffer)); 520 521 /* Program Slave Address for tuning single integrity */ 522 /* Write offset 0x0A to 0x13 */ 523 buffer[0] = 0x0A; 524 buffer[1] = 0x13; 525 i2c_success = write_i2c(pipe_ctx, slave_address, 526 buffer, sizeof(buffer)); 527 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 528 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 529 slave_address, buffer[0], buffer[1], i2c_success?1:0); 530 if (!i2c_success) 531 goto i2c_write_fail; 532 533 /* Write offset 0x0A to 0x17 */ 534 buffer[0] = 0x0A; 535 buffer[1] = 0x17; 536 i2c_success = write_i2c(pipe_ctx, slave_address, 537 buffer, sizeof(buffer)); 538 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 539 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 540 slave_address, buffer[0], buffer[1], i2c_success?1:0); 541 if (!i2c_success) 542 goto i2c_write_fail; 543 544 /* Write offset 0x0B to 0xDA or 0xD8 */ 545 buffer[0] = 0x0B; 546 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 547 i2c_success = write_i2c(pipe_ctx, slave_address, 548 buffer, sizeof(buffer)); 549 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 550 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 551 slave_address, buffer[0], buffer[1], i2c_success?1:0); 552 if (!i2c_success) 553 goto i2c_write_fail; 554 555 /* Write offset 0x0A to 0x17 */ 556 buffer[0] = 0x0A; 557 buffer[1] = 0x17; 558 i2c_success = write_i2c(pipe_ctx, slave_address, 559 buffer, sizeof(buffer)); 560 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 561 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 562 slave_address, buffer[0], buffer[1], i2c_success?1:0); 563 if (!i2c_success) 564 goto i2c_write_fail; 565 566 /* Write offset 0x0C to 0x1D or 0x91 */ 567 buffer[0] = 0x0C; 568 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 569 i2c_success = write_i2c(pipe_ctx, slave_address, 570 buffer, sizeof(buffer)); 571 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 572 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 573 slave_address, buffer[0], buffer[1], i2c_success?1:0); 574 if (!i2c_success) 575 goto i2c_write_fail; 576 577 /* Write offset 0x0A to 0x17 */ 578 buffer[0] = 0x0A; 579 buffer[1] = 0x17; 580 i2c_success = write_i2c(pipe_ctx, slave_address, 581 buffer, sizeof(buffer)); 582 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 583 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 584 slave_address, buffer[0], buffer[1], i2c_success?1:0); 585 if (!i2c_success) 586 goto i2c_write_fail; 587 588 589 if (is_vga_mode) { 590 /* Program additional settings if using 640x480 resolution */ 591 592 /* Write offset 0xFF to 0x01 */ 593 buffer[0] = 0xff; 594 buffer[1] = 0x01; 595 i2c_success = write_i2c(pipe_ctx, slave_address, 596 buffer, sizeof(buffer)); 597 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 598 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 599 slave_address, buffer[0], buffer[1], i2c_success?1:0); 600 if (!i2c_success) 601 goto i2c_write_fail; 602 603 /* Write offset 0x00 to 0x23 */ 604 buffer[0] = 0x00; 605 buffer[1] = 0x23; 606 i2c_success = write_i2c(pipe_ctx, slave_address, 607 buffer, sizeof(buffer)); 608 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 609 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 610 slave_address, buffer[0], buffer[1], i2c_success?1:0); 611 if (!i2c_success) 612 goto i2c_write_fail; 613 614 /* Write offset 0xff to 0x00 */ 615 buffer[0] = 0xff; 616 buffer[1] = 0x00; 617 i2c_success = write_i2c(pipe_ctx, slave_address, 618 buffer, sizeof(buffer)); 619 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 620 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 621 slave_address, buffer[0], buffer[1], i2c_success?1:0); 622 if (!i2c_success) 623 goto i2c_write_fail; 624 } 625 626 return; 627 628 i2c_write_fail: 629 DC_LOG_DEBUG("Set default retimer failed"); 630 } 631 632 static void write_i2c_redriver_setting( 633 struct pipe_ctx *pipe_ctx, 634 bool is_over_340mhz) 635 { 636 uint8_t slave_address = (0xF0 >> 1); 637 uint8_t buffer[16]; 638 bool i2c_success = false; 639 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 640 641 memset(&buffer, 0, sizeof(buffer)); 642 643 // Program Slave Address for tuning single integrity 644 buffer[3] = 0x4E; 645 buffer[4] = 0x4E; 646 buffer[5] = 0x4E; 647 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 648 649 i2c_success = write_i2c(pipe_ctx, slave_address, 650 buffer, sizeof(buffer)); 651 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 652 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 653 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 654 i2c_success = %d\n", 655 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 656 657 if (!i2c_success) 658 DC_LOG_DEBUG("Set redriver failed"); 659 } 660 661 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 662 { 663 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 664 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 665 struct cp_psp_stream_config config = {0}; 666 enum dp_panel_mode panel_mode = 667 dp_get_panel_mode(pipe_ctx->stream->link); 668 669 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 670 return; 671 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 672 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 673 ASSERT(link_enc); 674 if (link_enc == NULL) 675 return; 676 677 /* otg instance */ 678 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 679 680 /* dig front end */ 681 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 682 683 /* stream encoder index */ 684 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 685 if (dp_is_128b_132b_signal(pipe_ctx)) 686 config.stream_enc_idx = 687 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 688 689 /* dig back end */ 690 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 691 692 /* link encoder index */ 693 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 694 if (dp_is_128b_132b_signal(pipe_ctx)) 695 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 696 697 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 698 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 699 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 700 else 701 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 702 703 704 /* phy index */ 705 config.phy_idx = resource_transmitter_to_phy_idx( 706 pipe_ctx->stream->link->dc, link_enc->transmitter); 707 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 708 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 709 config.phy_idx = 0; 710 711 /* stream properties */ 712 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 713 config.mst_enabled = (pipe_ctx->stream->signal == 714 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 715 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 716 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 717 1 : 0; 718 config.dpms_off = dpms_off; 719 720 /* dm stream context */ 721 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 722 723 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 724 } 725 726 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 727 { 728 struct dc *dc = pipe_ctx->stream->ctx->dc; 729 730 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 731 return; 732 733 dc->hwss.set_avmute(pipe_ctx, enable); 734 } 735 736 static void enable_mst_on_sink(struct dc_link *link, bool enable) 737 { 738 unsigned char mstmCntl = 0; 739 740 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 741 if (enable) 742 mstmCntl |= DP_MST_EN; 743 else 744 mstmCntl &= (~DP_MST_EN); 745 746 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 747 } 748 749 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 750 struct dsc_optc_config *config) 751 { 752 uint32_t precision = 1 << 28; 753 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 754 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 755 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 756 DC_LOGGER_INIT(dsc->ctx->logger); 757 758 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 759 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 760 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 761 */ 762 ll_bytes_per_pix_fraq *= 10000000; 763 ll_bytes_per_pix_fraq /= precision; 764 765 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 766 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 767 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 768 DC_LOG_DSC("\tslice_width %d", config->slice_width); 769 } 770 771 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 772 { 773 struct dc *dc = pipe_ctx->stream->ctx->dc; 774 struct dc_stream_state *stream = pipe_ctx->stream; 775 bool result = false; 776 777 if (dc_is_virtual_signal(stream->signal)) 778 result = true; 779 else 780 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 781 return result; 782 } 783 784 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 785 { 786 struct dc *dc = pipe_ctx->stream->ctx->dc; 787 struct dc_stream_state *stream = pipe_ctx->stream; 788 bool result = false; 789 790 if (dc_is_virtual_signal(stream->signal)) 791 result = true; 792 else 793 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 794 return result; 795 } 796 797 798 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 799 * i.e. after dp_enable_dsc_on_rx() had been called 800 */ 801 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 802 { 803 /* TODO: Move this to HWSS as this is hardware programming sequence not a 804 * link layer sequence 805 */ 806 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 807 struct dc *dc = pipe_ctx->stream->ctx->dc; 808 struct dc_stream_state *stream = pipe_ctx->stream; 809 struct pipe_ctx *odm_pipe; 810 int opp_cnt = 1; 811 struct dccg *dccg = dc->res_pool->dccg; 812 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 813 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 814 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 815 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 816 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 817 * this problem. We are implementing a workaround here to keep using dscclk 818 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 819 * 48Mhz) pixel clock to avoid hitting this problem. 820 */ 821 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 822 stream->timing.pix_clk_100hz > 480000; 823 DC_LOGGER_INIT(dsc->ctx->logger); 824 825 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 826 opp_cnt++; 827 828 if (enable) { 829 struct dsc_config dsc_cfg; 830 struct dsc_optc_config dsc_optc_cfg = {0}; 831 enum optc_dsc_mode optc_dsc_mode; 832 833 /* Enable DSC hw block */ 834 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow + 835 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 836 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 837 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 838 dsc_cfg.color_depth = stream->timing.display_color_depth; 839 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 840 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 841 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 842 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 843 844 if (should_use_dto_dscclk) 845 dccg->funcs->set_dto_dscclk(dccg, dsc->inst); 846 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 847 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 848 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 849 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 850 851 if (should_use_dto_dscclk) 852 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst); 853 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 854 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 855 } 856 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 857 dsc_cfg.pic_width *= opp_cnt; 858 859 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 860 861 /* Enable DSC in encoder */ 862 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 863 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 864 dsc_optc_config_log(dsc, &dsc_optc_cfg); 865 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 866 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 867 optc_dsc_mode, 868 dsc_optc_cfg.bytes_per_pixel, 869 dsc_optc_cfg.slice_width); 870 871 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 872 } 873 874 /* Enable DSC in OPTC */ 875 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 876 dsc_optc_config_log(dsc, &dsc_optc_cfg); 877 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 878 optc_dsc_mode, 879 dsc_optc_cfg.bytes_per_pixel, 880 dsc_optc_cfg.slice_width); 881 } else { 882 /* disable DSC in OPTC */ 883 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 884 pipe_ctx->stream_res.tg, 885 OPTC_DSC_DISABLED, 0, 0); 886 887 /* disable DSC in stream encoder */ 888 if (dc_is_dp_signal(stream->signal)) { 889 if (dp_is_128b_132b_signal(pipe_ctx)) 890 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 891 pipe_ctx->stream_res.hpo_dp_stream_enc, 892 false, 893 NULL, 894 true); 895 else { 896 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 897 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 898 pipe_ctx->stream_res.stream_enc, 899 OPTC_DSC_DISABLED, 0, 0); 900 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 901 pipe_ctx->stream_res.stream_enc, false, NULL, true); 902 } 903 } 904 905 /* disable DSC block */ 906 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 907 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 908 /* 909 * TODO - dsc_disconnect is a double buffered register. 910 * by the time we call dsc_disable, dsc may still remain 911 * connected to OPP. In this case OPTC will no longer 912 * get correct pixel data because DSCC is off. However 913 * we also can't wait for the disconnect pending 914 * complete, because this function can be called 915 * with/without OTG master lock acquired. When the lock 916 * is acquired we will never get pending complete until 917 * we release the lock later. So there is no easy way to 918 * solve this problem especially when the lock is 919 * acquired. DSC is a front end hw block it should be 920 * programmed as part of front end sequence, where the 921 * commit sequence without lock and update sequence 922 * with lock are completely separated. However because 923 * we are programming dsc as part of back end link 924 * programming sequence, we don't know if front end OPTC 925 * master lock is acquired. The back end should be 926 * agnostic to front end lock. DSC programming shouldn't 927 * belong to this sequence. 928 */ 929 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 930 if (dccg->funcs->set_ref_dscclk) 931 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 932 } 933 } 934 } 935 936 /* 937 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 938 * hence PPS info packet update need to use frame update instead of immediate update. 939 * Added parameter immediate_update for this purpose. 940 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 941 * which is the only place where a "false" would be passed in for param immediate_update. 942 * 943 * immediate_update is only applicable when DSC is enabled. 944 */ 945 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 946 { 947 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 948 struct dc_stream_state *stream = pipe_ctx->stream; 949 950 if (!pipe_ctx->stream->timing.flags.DSC) 951 return false; 952 953 if (!dsc) 954 return false; 955 956 DC_LOGGER_INIT(dsc->ctx->logger); 957 958 if (enable) { 959 struct dsc_config dsc_cfg; 960 uint8_t dsc_packed_pps[128]; 961 962 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 963 memset(dsc_packed_pps, 0, 128); 964 965 /* Enable DSC hw block */ 966 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 967 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 968 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 969 dsc_cfg.color_depth = stream->timing.display_color_depth; 970 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 971 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 972 973 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 974 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 975 if (dc_is_dp_signal(stream->signal)) { 976 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 977 if (dp_is_128b_132b_signal(pipe_ctx)) 978 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 979 pipe_ctx->stream_res.hpo_dp_stream_enc, 980 true, 981 &dsc_packed_pps[0], 982 immediate_update); 983 else 984 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 985 pipe_ctx->stream_res.stream_enc, 986 true, 987 &dsc_packed_pps[0], 988 immediate_update); 989 } 990 } else { 991 /* disable DSC PPS in stream encoder */ 992 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 993 if (dc_is_dp_signal(stream->signal)) { 994 if (dp_is_128b_132b_signal(pipe_ctx)) 995 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 996 pipe_ctx->stream_res.hpo_dp_stream_enc, 997 false, 998 NULL, 999 true); 1000 else 1001 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 1002 pipe_ctx->stream_res.stream_enc, false, NULL, true); 1003 } 1004 } 1005 1006 return true; 1007 } 1008 1009 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 1010 { 1011 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1012 bool result = false; 1013 1014 if (!pipe_ctx->stream->timing.flags.DSC) 1015 goto out; 1016 if (!dsc) 1017 goto out; 1018 1019 if (enable) { 1020 { 1021 link_set_dsc_on_stream(pipe_ctx, true); 1022 result = true; 1023 } 1024 } else { 1025 dp_set_dsc_on_rx(pipe_ctx, false); 1026 link_set_dsc_on_stream(pipe_ctx, false); 1027 result = true; 1028 } 1029 out: 1030 return result; 1031 } 1032 1033 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 1034 { 1035 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1036 1037 if (!pipe_ctx->stream->timing.flags.DSC) 1038 return false; 1039 if (!dsc) 1040 return false; 1041 1042 link_set_dsc_on_stream(pipe_ctx, true); 1043 link_set_dsc_pps_packet(pipe_ctx, true, false); 1044 return true; 1045 } 1046 1047 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1048 { 1049 struct dc_stream_state *stream = pipe_ctx->stream; 1050 1051 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1052 struct dc_link *link = stream->link; 1053 union down_spread_ctrl old_downspread; 1054 union down_spread_ctrl new_downspread; 1055 1056 memset(&old_downspread, 0, sizeof(old_downspread)); 1057 1058 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1059 &old_downspread.raw, sizeof(old_downspread)); 1060 1061 new_downspread.raw = old_downspread.raw; 1062 1063 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1064 (stream->ignore_msa_timing_param) ? 1 : 0; 1065 1066 if (new_downspread.raw != old_downspread.raw) { 1067 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1068 &new_downspread.raw, sizeof(new_downspread)); 1069 } 1070 1071 } else { 1072 dm_helpers_mst_enable_stream_features(stream); 1073 } 1074 } 1075 1076 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1077 { 1078 const uint32_t VCP_Y_PRECISION = 1000; 1079 uint64_t vcp_x, vcp_y; 1080 DC_LOGGER_INIT(link->ctx->logger); 1081 1082 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1083 avg_time_slots_per_mtp = dc_fixpt_add( 1084 avg_time_slots_per_mtp, 1085 dc_fixpt_from_fraction( 1086 1, 1087 2*VCP_Y_PRECISION)); 1088 1089 vcp_x = dc_fixpt_floor( 1090 avg_time_slots_per_mtp); 1091 vcp_y = dc_fixpt_floor( 1092 dc_fixpt_mul_int( 1093 dc_fixpt_sub_int( 1094 avg_time_slots_per_mtp, 1095 dc_fixpt_floor( 1096 avg_time_slots_per_mtp)), 1097 VCP_Y_PRECISION)); 1098 1099 1100 if (link->type == dc_connection_mst_branch) 1101 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1102 "X: %llu " 1103 "Y: %llu/%d", 1104 vcp_x, 1105 vcp_y, 1106 VCP_Y_PRECISION); 1107 else 1108 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1109 "X: %llu " 1110 "Y: %llu/%d", 1111 vcp_x, 1112 vcp_y, 1113 VCP_Y_PRECISION); 1114 } 1115 1116 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1117 { 1118 struct fixed31_32 mbytes_per_sec; 1119 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1120 &stream->link->cur_link_settings); 1121 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1122 1123 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1124 1125 return dc_fixpt_div_int(mbytes_per_sec, 54); 1126 } 1127 1128 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1129 { 1130 struct fixed31_32 peak_kbps; 1131 uint32_t numerator = 0; 1132 uint32_t denominator = 1; 1133 1134 /* 1135 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1136 * required when determining PBN/time slot utilization on the link between 1137 * us and the branch, since that overhead is already accounted for in 1138 * the get_pbn_per_slot function. 1139 * 1140 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1141 * common multiplier to render an integer PBN for all link rate/lane 1142 * counts combinations 1143 * calculate 1144 * peak_kbps *= (64/54) 1145 * peak_kbps /= (8 * 1000) convert to bytes 1146 */ 1147 1148 numerator = 64; 1149 denominator = 54 * 8 * 1000; 1150 kbps *= numerator; 1151 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1152 1153 return peak_kbps; 1154 } 1155 1156 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1157 { 1158 uint64_t kbps; 1159 enum dc_link_encoding_format link_encoding; 1160 1161 if (dp_is_128b_132b_signal(pipe_ctx)) 1162 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1163 else 1164 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1165 1166 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1167 return get_pbn_from_bw_in_kbps(kbps); 1168 } 1169 1170 1171 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1172 static void get_lane_status( 1173 struct dc_link *link, 1174 uint32_t lane_count, 1175 union lane_status *status, 1176 union lane_align_status_updated *status_updated) 1177 { 1178 unsigned int lane; 1179 uint8_t dpcd_buf[3] = {0}; 1180 1181 if (status == NULL || status_updated == NULL) { 1182 return; 1183 } 1184 1185 core_link_read_dpcd( 1186 link, 1187 DP_LANE0_1_STATUS, 1188 dpcd_buf, 1189 sizeof(dpcd_buf)); 1190 1191 for (lane = 0; lane < lane_count; lane++) { 1192 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1193 } 1194 1195 status_updated->raw = dpcd_buf[2]; 1196 } 1197 1198 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1199 { 1200 /* 1201 * wait for ACT handled 1202 */ 1203 int i; 1204 const int act_retries = 30; 1205 enum act_return_status result = ACT_FAILED; 1206 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1207 union payload_table_update_status update_status = {0}; 1208 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1209 union lane_align_status_updated lane_status_updated; 1210 DC_LOGGER_INIT(link->ctx->logger); 1211 1212 if (!display_connected || link->aux_access_disabled) 1213 return true; 1214 for (i = 0; i < act_retries; i++) { 1215 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1216 1217 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1218 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1219 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1220 !dp_is_interlane_aligned(lane_status_updated)) { 1221 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1222 "polling for ACT handled."); 1223 result = ACT_LINK_LOST; 1224 break; 1225 } 1226 core_link_read_dpcd( 1227 link, 1228 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1229 &update_status.raw, 1230 1); 1231 1232 if (update_status.bits.ACT_HANDLED == 1) { 1233 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1234 result = ACT_SUCCESS; 1235 break; 1236 } 1237 1238 fsleep(5000); 1239 } 1240 1241 if (result == ACT_FAILED) { 1242 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1243 "continue on. Something is wrong with the branch."); 1244 } 1245 1246 return (result == ACT_SUCCESS); 1247 } 1248 1249 static void update_mst_stream_alloc_table( 1250 struct dc_link *link, 1251 struct stream_encoder *stream_enc, 1252 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1253 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1254 { 1255 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1256 struct link_mst_stream_allocation *dc_alloc; 1257 1258 int i; 1259 int j; 1260 1261 /* if DRM proposed_table has more than one new payload */ 1262 ASSERT(proposed_table->stream_count - 1263 link->mst_stream_alloc_table.stream_count < 2); 1264 1265 /* copy proposed_table to link, add stream encoder */ 1266 for (i = 0; i < proposed_table->stream_count; i++) { 1267 1268 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1269 dc_alloc = 1270 &link->mst_stream_alloc_table.stream_allocations[j]; 1271 1272 if (dc_alloc->vcp_id == 1273 proposed_table->stream_allocations[i].vcp_id) { 1274 1275 work_table[i] = *dc_alloc; 1276 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1277 break; /* exit j loop */ 1278 } 1279 } 1280 1281 /* new vcp_id */ 1282 if (j == link->mst_stream_alloc_table.stream_count) { 1283 work_table[i].vcp_id = 1284 proposed_table->stream_allocations[i].vcp_id; 1285 work_table[i].slot_count = 1286 proposed_table->stream_allocations[i].slot_count; 1287 work_table[i].stream_enc = stream_enc; 1288 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1289 } 1290 } 1291 1292 /* update link->mst_stream_alloc_table with work_table */ 1293 link->mst_stream_alloc_table.stream_count = 1294 proposed_table->stream_count; 1295 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1296 link->mst_stream_alloc_table.stream_allocations[i] = 1297 work_table[i]; 1298 } 1299 1300 static void remove_stream_from_alloc_table( 1301 struct dc_link *link, 1302 struct stream_encoder *dio_stream_enc, 1303 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1304 { 1305 int i = 0; 1306 struct link_mst_stream_allocation_table *table = 1307 &link->mst_stream_alloc_table; 1308 1309 if (hpo_dp_stream_enc) { 1310 for (; i < table->stream_count; i++) 1311 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1312 break; 1313 } else { 1314 for (; i < table->stream_count; i++) 1315 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1316 break; 1317 } 1318 1319 if (i < table->stream_count) { 1320 i++; 1321 for (; i < table->stream_count; i++) 1322 table->stream_allocations[i-1] = table->stream_allocations[i]; 1323 memset(&table->stream_allocations[table->stream_count-1], 0, 1324 sizeof(struct link_mst_stream_allocation)); 1325 table->stream_count--; 1326 } 1327 } 1328 1329 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1330 { 1331 struct dc_stream_state *stream = pipe_ctx->stream; 1332 struct dc_link *link = stream->link; 1333 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1334 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1335 int i; 1336 bool mst_mode = (link->type == dc_connection_mst_branch); 1337 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1338 const struct dc_link_settings empty_link_settings = {0}; 1339 DC_LOGGER_INIT(link->ctx->logger); 1340 1341 /* deallocate_mst_payload is called before disable link. When mode or 1342 * disable/enable monitor, new stream is created which is not in link 1343 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1344 * should not done. For new mode set, map_resources will get engine 1345 * for new stream, so stream_enc->id should be validated until here. 1346 */ 1347 1348 /* slot X.Y */ 1349 if (link_hwss->ext.set_throttled_vcp_size) 1350 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1351 if (link_hwss->ext.set_hblank_min_symbol_width) 1352 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1353 &empty_link_settings, 1354 avg_time_slots_per_mtp); 1355 1356 if (mst_mode) { 1357 /* when link is in mst mode, reply on mst manager to remove 1358 * payload 1359 */ 1360 if (dm_helpers_dp_mst_write_payload_allocation_table( 1361 stream->ctx, 1362 stream, 1363 &proposed_table, 1364 false)) 1365 update_mst_stream_alloc_table( 1366 link, 1367 pipe_ctx->stream_res.stream_enc, 1368 pipe_ctx->stream_res.hpo_dp_stream_enc, 1369 &proposed_table); 1370 else 1371 DC_LOG_WARNING("Failed to update" 1372 "MST allocation table for" 1373 "pipe idx:%d\n", 1374 pipe_ctx->pipe_idx); 1375 } else { 1376 /* when link is no longer in mst mode (mst hub unplugged), 1377 * remove payload with default dc logic 1378 */ 1379 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1380 pipe_ctx->stream_res.hpo_dp_stream_enc); 1381 } 1382 1383 DC_LOG_MST("%s" 1384 "stream_count: %d: ", 1385 __func__, 1386 link->mst_stream_alloc_table.stream_count); 1387 1388 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1389 DC_LOG_MST("stream_enc[%d]: %p " 1390 "stream[%d].hpo_dp_stream_enc: %p " 1391 "stream[%d].vcp_id: %d " 1392 "stream[%d].slot_count: %d\n", 1393 i, 1394 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1395 i, 1396 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1397 i, 1398 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1399 i, 1400 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1401 } 1402 1403 /* update mst stream allocation table hardware state */ 1404 if (link_hwss->ext.update_stream_allocation_table == NULL || 1405 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1406 DC_LOG_DEBUG("Unknown encoding format\n"); 1407 return DC_ERROR_UNEXPECTED; 1408 } 1409 1410 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1411 &link->mst_stream_alloc_table); 1412 1413 if (mst_mode) 1414 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1415 stream->ctx, 1416 stream); 1417 1418 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1419 stream->ctx, 1420 stream); 1421 1422 return DC_OK; 1423 } 1424 1425 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1426 * because stream_encoder is not exposed to dm 1427 */ 1428 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1429 { 1430 struct dc_stream_state *stream = pipe_ctx->stream; 1431 struct dc_link *link = stream->link; 1432 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1433 struct fixed31_32 avg_time_slots_per_mtp; 1434 struct fixed31_32 pbn; 1435 struct fixed31_32 pbn_per_slot; 1436 int i; 1437 enum act_return_status ret; 1438 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1439 DC_LOGGER_INIT(link->ctx->logger); 1440 1441 /* enable_link_dp_mst already check link->enabled_stream_count 1442 * and stream is in link->stream[]. This is called during set mode, 1443 * stream_enc is available. 1444 */ 1445 1446 /* get calculate VC payload for stream: stream_alloc */ 1447 if (dm_helpers_dp_mst_write_payload_allocation_table( 1448 stream->ctx, 1449 stream, 1450 &proposed_table, 1451 true)) 1452 update_mst_stream_alloc_table( 1453 link, 1454 pipe_ctx->stream_res.stream_enc, 1455 pipe_ctx->stream_res.hpo_dp_stream_enc, 1456 &proposed_table); 1457 else 1458 DC_LOG_WARNING("Failed to update" 1459 "MST allocation table for" 1460 "pipe idx:%d\n", 1461 pipe_ctx->pipe_idx); 1462 1463 DC_LOG_MST("%s " 1464 "stream_count: %d: \n ", 1465 __func__, 1466 link->mst_stream_alloc_table.stream_count); 1467 1468 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1469 DC_LOG_MST("stream_enc[%d]: %p " 1470 "stream[%d].hpo_dp_stream_enc: %p " 1471 "stream[%d].vcp_id: %d " 1472 "stream[%d].slot_count: %d\n", 1473 i, 1474 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1475 i, 1476 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1477 i, 1478 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1479 i, 1480 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1481 } 1482 1483 ASSERT(proposed_table.stream_count > 0); 1484 1485 /* program DP source TX for payload */ 1486 if (link_hwss->ext.update_stream_allocation_table == NULL || 1487 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1488 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1489 return DC_ERROR_UNEXPECTED; 1490 } 1491 1492 link_hwss->ext.update_stream_allocation_table(link, 1493 &pipe_ctx->link_res, 1494 &link->mst_stream_alloc_table); 1495 1496 /* send down message */ 1497 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1498 stream->ctx, 1499 stream); 1500 1501 if (ret != ACT_LINK_LOST) 1502 dm_helpers_dp_mst_send_payload_allocation( 1503 stream->ctx, 1504 stream); 1505 1506 /* slot X.Y for only current stream */ 1507 pbn_per_slot = get_pbn_per_slot(stream); 1508 if (pbn_per_slot.value == 0) { 1509 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1510 return DC_UNSUPPORTED_VALUE; 1511 } 1512 pbn = get_pbn_from_timing(pipe_ctx); 1513 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1514 1515 log_vcp_x_y(link, avg_time_slots_per_mtp); 1516 1517 if (link_hwss->ext.set_throttled_vcp_size) 1518 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1519 if (link_hwss->ext.set_hblank_min_symbol_width) 1520 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1521 &link->cur_link_settings, 1522 avg_time_slots_per_mtp); 1523 1524 return DC_OK; 1525 } 1526 1527 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1528 const struct dc_stream_state *stream, 1529 const struct dc_link *link) 1530 { 1531 struct fixed31_32 link_bw_effective = 1532 dc_fixpt_from_int( 1533 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1534 struct fixed31_32 timeslot_bw_effective = 1535 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1536 struct fixed31_32 timing_bw = 1537 dc_fixpt_from_int( 1538 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1539 dc_link_get_highest_encoding_format(link))); 1540 struct fixed31_32 avg_time_slots_per_mtp = 1541 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1542 1543 return avg_time_slots_per_mtp; 1544 } 1545 1546 1547 static bool write_128b_132b_sst_payload_allocation_table( 1548 const struct dc_stream_state *stream, 1549 struct dc_link *link, 1550 struct link_mst_stream_allocation_table *proposed_table, 1551 bool allocate) 1552 { 1553 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1554 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1555 bool result = false; 1556 uint8_t req_slot_count = 0; 1557 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1558 union payload_table_update_status update_status = { 0 }; 1559 const uint32_t max_retries = 30; 1560 uint32_t retries = 0; 1561 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1562 DC_LOGGER_INIT(link->ctx->logger); 1563 1564 if (allocate) { 1565 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1566 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1567 /// Validation should filter out modes that exceed link BW 1568 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1569 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1570 return false; 1571 } else { 1572 /// Leave req_slot_count = 0 if allocate is false. 1573 } 1574 1575 proposed_table->stream_count = 1; /// Always 1 stream for SST 1576 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1577 proposed_table->stream_allocations[0].vcp_id = vc_id; 1578 1579 if (!display_connected || link->aux_access_disabled) 1580 return true; 1581 1582 /// Write DPCD 2C0 = 1 to start updating 1583 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1584 core_link_write_dpcd( 1585 link, 1586 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1587 &update_status.raw, 1588 1); 1589 1590 /// Program the changes in DPCD 1C0 - 1C2 1591 ASSERT(vc_id == 1); 1592 core_link_write_dpcd( 1593 link, 1594 DP_PAYLOAD_ALLOCATE_SET, 1595 &vc_id, 1596 1); 1597 1598 ASSERT(start_time_slot == 0); 1599 core_link_write_dpcd( 1600 link, 1601 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1602 &start_time_slot, 1603 1); 1604 1605 core_link_write_dpcd( 1606 link, 1607 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1608 &req_slot_count, 1609 1); 1610 1611 /// Poll till DPCD 2C0 read 1 1612 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1613 1614 while (retries < max_retries) { 1615 if (core_link_read_dpcd( 1616 link, 1617 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1618 &update_status.raw, 1619 1) == DC_OK) { 1620 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1621 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1622 result = true; 1623 break; 1624 } 1625 } else { 1626 union dpcd_rev dpcdRev = {0}; 1627 1628 if (core_link_read_dpcd( 1629 link, 1630 DP_DPCD_REV, 1631 &dpcdRev.raw, 1632 1) != DC_OK) { 1633 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1634 "of sink while polling payload table " 1635 "updated status bit."); 1636 break; 1637 } 1638 } 1639 retries++; 1640 fsleep(5000); 1641 } 1642 1643 if (!result && retries == max_retries) { 1644 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1645 "continue on. Something is wrong with the branch."); 1646 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1647 } 1648 1649 return result; 1650 } 1651 1652 /* 1653 * Payload allocation/deallocation for SST introduced in DP2.0 1654 */ 1655 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1656 bool allocate) 1657 { 1658 struct dc_stream_state *stream = pipe_ctx->stream; 1659 struct dc_link *link = stream->link; 1660 struct link_mst_stream_allocation_table proposed_table = {0}; 1661 struct fixed31_32 avg_time_slots_per_mtp; 1662 const struct dc_link_settings empty_link_settings = {0}; 1663 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1664 DC_LOGGER_INIT(link->ctx->logger); 1665 1666 /* slot X.Y for SST payload deallocate */ 1667 if (!allocate) { 1668 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1669 1670 log_vcp_x_y(link, avg_time_slots_per_mtp); 1671 1672 if (link_hwss->ext.set_throttled_vcp_size) 1673 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1674 avg_time_slots_per_mtp); 1675 if (link_hwss->ext.set_hblank_min_symbol_width) 1676 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1677 &empty_link_settings, 1678 avg_time_slots_per_mtp); 1679 } 1680 1681 /* calculate VC payload and update branch with new payload allocation table*/ 1682 if (!write_128b_132b_sst_payload_allocation_table( 1683 stream, 1684 link, 1685 &proposed_table, 1686 allocate)) { 1687 DC_LOG_ERROR("SST Update Payload: Failed to update " 1688 "allocation table for " 1689 "pipe idx: %d\n", 1690 pipe_ctx->pipe_idx); 1691 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1692 } 1693 1694 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1695 1696 ASSERT(proposed_table.stream_count == 1); 1697 1698 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1699 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1700 "vcp_id: %d " 1701 "slot_count: %d\n", 1702 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1703 proposed_table.stream_allocations[0].vcp_id, 1704 proposed_table.stream_allocations[0].slot_count); 1705 1706 /* program DP source TX for payload */ 1707 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1708 &proposed_table); 1709 1710 /* poll for ACT handled */ 1711 if (!poll_for_allocation_change_trigger(link)) { 1712 // Failures will result in blackscreen and errors logged 1713 BREAK_TO_DEBUGGER(); 1714 } 1715 1716 /* slot X.Y for SST payload allocate */ 1717 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1718 DP_128b_132b_ENCODING) { 1719 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1720 1721 log_vcp_x_y(link, avg_time_slots_per_mtp); 1722 1723 if (link_hwss->ext.set_throttled_vcp_size) 1724 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1725 avg_time_slots_per_mtp); 1726 if (link_hwss->ext.set_hblank_min_symbol_width) 1727 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1728 &link->cur_link_settings, 1729 avg_time_slots_per_mtp); 1730 } 1731 1732 /* Always return DC_OK. 1733 * If part of sequence fails, log failure(s) and show blackscreen 1734 */ 1735 return DC_OK; 1736 } 1737 1738 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1739 { 1740 struct dc_stream_state *stream = pipe_ctx->stream; 1741 struct dc_link *link = stream->link; 1742 struct fixed31_32 avg_time_slots_per_mtp; 1743 struct fixed31_32 pbn; 1744 struct fixed31_32 pbn_per_slot; 1745 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1746 uint8_t i; 1747 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1748 DC_LOGGER_INIT(link->ctx->logger); 1749 1750 /* decrease throttled vcp size */ 1751 pbn_per_slot = get_pbn_per_slot(stream); 1752 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1753 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1754 1755 if (link_hwss->ext.set_throttled_vcp_size) 1756 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1757 if (link_hwss->ext.set_hblank_min_symbol_width) 1758 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1759 &link->cur_link_settings, 1760 avg_time_slots_per_mtp); 1761 1762 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1763 dm_helpers_dp_mst_send_payload_allocation( 1764 stream->ctx, 1765 stream); 1766 1767 /* notify immediate branch device table update */ 1768 if (dm_helpers_dp_mst_write_payload_allocation_table( 1769 stream->ctx, 1770 stream, 1771 &proposed_table, 1772 true)) { 1773 /* update mst stream allocation table software state */ 1774 update_mst_stream_alloc_table( 1775 link, 1776 pipe_ctx->stream_res.stream_enc, 1777 pipe_ctx->stream_res.hpo_dp_stream_enc, 1778 &proposed_table); 1779 } else { 1780 DC_LOG_WARNING("Failed to update" 1781 "MST allocation table for" 1782 "pipe idx:%d\n", 1783 pipe_ctx->pipe_idx); 1784 } 1785 1786 DC_LOG_MST("%s " 1787 "stream_count: %d: \n ", 1788 __func__, 1789 link->mst_stream_alloc_table.stream_count); 1790 1791 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1792 DC_LOG_MST("stream_enc[%d]: %p " 1793 "stream[%d].hpo_dp_stream_enc: %p " 1794 "stream[%d].vcp_id: %d " 1795 "stream[%d].slot_count: %d\n", 1796 i, 1797 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1798 i, 1799 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1800 i, 1801 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1802 i, 1803 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1804 } 1805 1806 ASSERT(proposed_table.stream_count > 0); 1807 1808 /* update mst stream allocation table hardware state */ 1809 if (link_hwss->ext.update_stream_allocation_table == NULL || 1810 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1811 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1812 return DC_ERROR_UNEXPECTED; 1813 } 1814 1815 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1816 &link->mst_stream_alloc_table); 1817 1818 /* poll for immediate branch device ACT handled */ 1819 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1820 stream->ctx, 1821 stream); 1822 1823 return DC_OK; 1824 } 1825 1826 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1827 { 1828 struct dc_stream_state *stream = pipe_ctx->stream; 1829 struct dc_link *link = stream->link; 1830 struct fixed31_32 avg_time_slots_per_mtp; 1831 struct fixed31_32 pbn; 1832 struct fixed31_32 pbn_per_slot; 1833 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1834 uint8_t i; 1835 enum act_return_status ret; 1836 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1837 DC_LOGGER_INIT(link->ctx->logger); 1838 1839 /* notify immediate branch device table update */ 1840 if (dm_helpers_dp_mst_write_payload_allocation_table( 1841 stream->ctx, 1842 stream, 1843 &proposed_table, 1844 true)) { 1845 /* update mst stream allocation table software state */ 1846 update_mst_stream_alloc_table( 1847 link, 1848 pipe_ctx->stream_res.stream_enc, 1849 pipe_ctx->stream_res.hpo_dp_stream_enc, 1850 &proposed_table); 1851 } 1852 1853 DC_LOG_MST("%s " 1854 "stream_count: %d: \n ", 1855 __func__, 1856 link->mst_stream_alloc_table.stream_count); 1857 1858 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1859 DC_LOG_MST("stream_enc[%d]: %p " 1860 "stream[%d].hpo_dp_stream_enc: %p " 1861 "stream[%d].vcp_id: %d " 1862 "stream[%d].slot_count: %d\n", 1863 i, 1864 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1865 i, 1866 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1867 i, 1868 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1869 i, 1870 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1871 } 1872 1873 ASSERT(proposed_table.stream_count > 0); 1874 1875 /* update mst stream allocation table hardware state */ 1876 if (link_hwss->ext.update_stream_allocation_table == NULL || 1877 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1878 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1879 return DC_ERROR_UNEXPECTED; 1880 } 1881 1882 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1883 &link->mst_stream_alloc_table); 1884 1885 /* poll for immediate branch device ACT handled */ 1886 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1887 stream->ctx, 1888 stream); 1889 1890 if (ret != ACT_LINK_LOST) { 1891 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1892 dm_helpers_dp_mst_send_payload_allocation( 1893 stream->ctx, 1894 stream); 1895 } 1896 1897 /* increase throttled vcp size */ 1898 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1899 pbn_per_slot = get_pbn_per_slot(stream); 1900 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1901 1902 if (link_hwss->ext.set_throttled_vcp_size) 1903 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1904 if (link_hwss->ext.set_hblank_min_symbol_width) 1905 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1906 &link->cur_link_settings, 1907 avg_time_slots_per_mtp); 1908 1909 return DC_OK; 1910 } 1911 1912 static void disable_link_dp(struct dc_link *link, 1913 const struct link_resource *link_res, 1914 enum signal_type signal) 1915 { 1916 struct dc_link_settings link_settings = link->cur_link_settings; 1917 1918 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1919 link->mst_stream_alloc_table.stream_count > 0) 1920 /* disable MST link only when last vc payload is deallocated */ 1921 return; 1922 1923 dp_disable_link_phy(link, link_res, signal); 1924 1925 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1926 if (!link->skip_implict_edp_power_control) 1927 link->dc->hwss.edp_power_control(link, false); 1928 } 1929 1930 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1931 /* set the sink to SST mode after disabling the link */ 1932 enable_mst_on_sink(link, false); 1933 1934 if (link_dp_get_encoding_format(&link_settings) == 1935 DP_8b_10b_ENCODING) { 1936 dp_set_fec_enable(link, link_res, false); 1937 dp_set_fec_ready(link, link_res, false); 1938 } 1939 } 1940 1941 static void disable_link(struct dc_link *link, 1942 const struct link_resource *link_res, 1943 enum signal_type signal) 1944 { 1945 if (dc_is_dp_signal(signal)) { 1946 disable_link_dp(link, link_res, signal); 1947 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1948 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1949 } else { 1950 link->dc->hwss.disable_link_output(link, link_res, signal); 1951 } 1952 1953 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1954 /* MST disable link only when no stream use the link */ 1955 if (link->mst_stream_alloc_table.stream_count <= 0) 1956 link->link_status.link_active = false; 1957 } else { 1958 link->link_status.link_active = false; 1959 } 1960 } 1961 1962 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1963 { 1964 struct dc_stream_state *stream = pipe_ctx->stream; 1965 struct dc_link *link = stream->link; 1966 enum dc_color_depth display_color_depth; 1967 enum engine_id eng_id; 1968 struct ext_hdmi_settings settings = {0}; 1969 bool is_over_340mhz = false; 1970 bool is_vga_mode = (stream->timing.h_addressable == 640) 1971 && (stream->timing.v_addressable == 480); 1972 struct dc *dc = pipe_ctx->stream->ctx->dc; 1973 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1974 1975 if (stream->phy_pix_clk == 0) 1976 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1977 if (stream->phy_pix_clk > 340000) 1978 is_over_340mhz = true; 1979 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1980 ASSERT(false); 1981 return; 1982 } 1983 1984 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1985 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1986 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1987 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1988 /* DP159, Retimer settings */ 1989 eng_id = pipe_ctx->stream_res.stream_enc->id; 1990 1991 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1992 write_i2c_retimer_setting(pipe_ctx, 1993 is_vga_mode, is_over_340mhz, &settings); 1994 } else { 1995 write_i2c_default_retimer_setting(pipe_ctx, 1996 is_vga_mode, is_over_340mhz); 1997 } 1998 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1999 /* PI3EQX1204, Redriver settings */ 2000 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 2001 } 2002 } 2003 2004 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2005 write_scdc_data( 2006 stream->link->ddc, 2007 stream->phy_pix_clk, 2008 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2009 2010 memset(&stream->link->cur_link_settings, 0, 2011 sizeof(struct dc_link_settings)); 2012 2013 display_color_depth = stream->timing.display_color_depth; 2014 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2015 display_color_depth = COLOR_DEPTH_888; 2016 2017 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 2018 * character clock in case that beyond 340MHz. 2019 */ 2020 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 2021 link_hwss->setup_stream_encoder(pipe_ctx); 2022 2023 dc->hwss.enable_tmds_link_output( 2024 link, 2025 &pipe_ctx->link_res, 2026 pipe_ctx->stream->signal, 2027 pipe_ctx->clock_source->id, 2028 display_color_depth, 2029 stream->phy_pix_clk); 2030 2031 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2032 read_scdc_data(link->ddc); 2033 } 2034 2035 static enum dc_status enable_link_dp(struct dc_state *state, 2036 struct pipe_ctx *pipe_ctx) 2037 { 2038 struct dc_stream_state *stream = pipe_ctx->stream; 2039 enum dc_status status; 2040 bool skip_video_pattern; 2041 struct dc_link *link = stream->link; 2042 const struct dc_link_settings *link_settings = 2043 &pipe_ctx->link_config.dp_link_settings; 2044 bool fec_enable; 2045 int i; 2046 bool apply_seamless_boot_optimization = false; 2047 uint32_t bl_oled_enable_delay = 50; // in ms 2048 uint32_t post_oui_delay = 30; // 30ms 2049 /* Reduce link bandwidth between failed link training attempts. */ 2050 bool do_fallback = false; 2051 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2052 2053 // Increase retry count if attempting DP1.x on FIXED_VS link 2054 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2055 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2056 lt_attempts = 10; 2057 2058 // check for seamless boot 2059 for (i = 0; i < state->stream_count; i++) { 2060 if (state->streams[i]->apply_seamless_boot_optimization) { 2061 apply_seamless_boot_optimization = true; 2062 break; 2063 } 2064 } 2065 2066 /* Train with fallback when enabling DPIA link. Conventional links are 2067 * trained with fallback during sink detection. 2068 */ 2069 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2070 !link->dc->config.enable_dpia_pre_training) 2071 do_fallback = true; 2072 2073 /* 2074 * Temporary w/a to get DP2.0 link rates to work with SST. 2075 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2076 */ 2077 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2078 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2079 link->dc->debug.set_mst_en_for_sst) { 2080 enable_mst_on_sink(link, true); 2081 } 2082 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2083 /*in case it is not on*/ 2084 if (!link->dc->config.edp_no_power_sequencing) 2085 link->dc->hwss.edp_power_control(link, true); 2086 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2087 } 2088 2089 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2090 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2091 } else { 2092 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2093 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2094 if (state->clk_mgr && !apply_seamless_boot_optimization) 2095 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2096 state, false); 2097 } 2098 2099 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2100 dpcd_set_source_specific_data(link); 2101 if (link->dpcd_sink_ext_caps.raw != 0) { 2102 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2103 msleep(post_oui_delay); 2104 } 2105 2106 // similarly, mode switch can cause loss of cable ID 2107 dpcd_write_cable_id_to_dprx(link); 2108 2109 skip_video_pattern = true; 2110 2111 if (link_settings->link_rate == LINK_RATE_LOW) 2112 skip_video_pattern = false; 2113 2114 if (stream->sink_patches.oled_optimize_display_on) 2115 set_default_brightness_aux(link); 2116 2117 if (perform_link_training_with_retries(link_settings, 2118 skip_video_pattern, 2119 lt_attempts, 2120 pipe_ctx, 2121 pipe_ctx->stream->signal, 2122 do_fallback)) { 2123 status = DC_OK; 2124 } else { 2125 status = DC_FAIL_DP_LINK_TRAINING; 2126 } 2127 2128 if (link->preferred_training_settings.fec_enable) 2129 fec_enable = *link->preferred_training_settings.fec_enable; 2130 else 2131 fec_enable = true; 2132 2133 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2134 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 2135 2136 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2137 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2138 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2139 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2140 if (!stream->sink_patches.oled_optimize_display_on) { 2141 set_default_brightness_aux(link); 2142 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2143 msleep(bl_oled_enable_delay); 2144 edp_backlight_enable_aux(link, true); 2145 } else { 2146 edp_backlight_enable_aux(link, true); 2147 } 2148 } 2149 2150 return status; 2151 } 2152 2153 static enum dc_status enable_link_edp( 2154 struct dc_state *state, 2155 struct pipe_ctx *pipe_ctx) 2156 { 2157 return enable_link_dp(state, pipe_ctx); 2158 } 2159 2160 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2161 { 2162 struct dc_stream_state *stream = pipe_ctx->stream; 2163 struct dc_link *link = stream->link; 2164 struct dc *dc = stream->ctx->dc; 2165 2166 if (stream->phy_pix_clk == 0) 2167 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2168 2169 memset(&stream->link->cur_link_settings, 0, 2170 sizeof(struct dc_link_settings)); 2171 dc->hwss.enable_lvds_link_output( 2172 link, 2173 &pipe_ctx->link_res, 2174 pipe_ctx->clock_source->id, 2175 stream->phy_pix_clk); 2176 2177 } 2178 2179 static enum dc_status enable_link_dp_mst( 2180 struct dc_state *state, 2181 struct pipe_ctx *pipe_ctx) 2182 { 2183 struct dc_link *link = pipe_ctx->stream->link; 2184 unsigned char mstm_cntl = 0; 2185 2186 /* sink signal type after MST branch is MST. Multiple MST sinks 2187 * share one link. Link DP PHY is enable or training only once. 2188 */ 2189 if (link->link_status.link_active) 2190 return DC_OK; 2191 2192 /* clear payload table */ 2193 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2194 if (mstm_cntl & DP_MST_EN) 2195 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2196 2197 /* to make sure the pending down rep can be processed 2198 * before enabling the link 2199 */ 2200 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2201 2202 /* set the sink to MST mode before enabling the link */ 2203 enable_mst_on_sink(link, true); 2204 2205 return enable_link_dp(state, pipe_ctx); 2206 } 2207 2208 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2209 { 2210 struct dc_link *link = pipe_ctx->stream->link; 2211 2212 link->dc->hwss.enable_dp_link_output(link, 2213 &pipe_ctx->link_res, 2214 SIGNAL_TYPE_DISPLAY_PORT, 2215 pipe_ctx->clock_source->id, 2216 &pipe_ctx->link_config.dp_link_settings); 2217 return DC_OK; 2218 } 2219 2220 static enum dc_status enable_link( 2221 struct dc_state *state, 2222 struct pipe_ctx *pipe_ctx) 2223 { 2224 enum dc_status status = DC_ERROR_UNEXPECTED; 2225 struct dc_stream_state *stream = pipe_ctx->stream; 2226 struct dc_link *link = stream->link; 2227 2228 /* There's some scenarios where driver is unloaded with display 2229 * still enabled. When driver is reloaded, it may cause a display 2230 * to not light up if there is a mismatch between old and new 2231 * link settings. Need to call disable first before enabling at 2232 * new link settings. 2233 */ 2234 if (link->link_status.link_active) 2235 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2236 2237 switch (pipe_ctx->stream->signal) { 2238 case SIGNAL_TYPE_DISPLAY_PORT: 2239 status = enable_link_dp(state, pipe_ctx); 2240 break; 2241 case SIGNAL_TYPE_EDP: 2242 status = enable_link_edp(state, pipe_ctx); 2243 break; 2244 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2245 status = enable_link_dp_mst(state, pipe_ctx); 2246 msleep(200); 2247 break; 2248 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2249 case SIGNAL_TYPE_DVI_DUAL_LINK: 2250 case SIGNAL_TYPE_HDMI_TYPE_A: 2251 enable_link_hdmi(pipe_ctx); 2252 status = DC_OK; 2253 break; 2254 case SIGNAL_TYPE_LVDS: 2255 enable_link_lvds(pipe_ctx); 2256 status = DC_OK; 2257 break; 2258 case SIGNAL_TYPE_VIRTUAL: 2259 status = enable_link_virtual(pipe_ctx); 2260 break; 2261 default: 2262 break; 2263 } 2264 2265 if (status == DC_OK) { 2266 pipe_ctx->stream->link->link_status.link_active = true; 2267 } 2268 2269 return status; 2270 } 2271 2272 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2273 { 2274 struct dc_link *link = stream->sink->link; 2275 int req_bw = bw; 2276 2277 DC_LOGGER_INIT(link->ctx->logger); 2278 2279 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2280 return false; 2281 2282 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2283 int sink_index = 0; 2284 int i = 0; 2285 2286 for (i = 0; i < link->sink_count; i++) { 2287 if (link->remote_sinks[i] == NULL) 2288 continue; 2289 2290 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2291 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2292 else 2293 sink_index = i; 2294 } 2295 2296 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2297 } 2298 2299 /* get dp overhead for dp tunneling */ 2300 link->dpia_bw_alloc_config.dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(link); 2301 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2302 2303 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2304 2305 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2306 int i = 0; 2307 2308 for (i = 0; i < link->sink_count; i++) { 2309 if (link->remote_sinks[i] == NULL) 2310 continue; 2311 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2312 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2313 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2314 } 2315 } 2316 2317 return true; 2318 } 2319 2320 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2321 { 2322 bool ret; 2323 2324 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2325 dc_link_get_highest_encoding_format(stream->sink->link)); 2326 2327 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2328 2329 return ret; 2330 } 2331 2332 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2333 { 2334 bool ret; 2335 2336 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2337 2338 return ret; 2339 } 2340 2341 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2342 { 2343 struct dc *dc = pipe_ctx->stream->ctx->dc; 2344 struct dc_stream_state *stream = pipe_ctx->stream; 2345 struct dc_link *link = stream->sink->link; 2346 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2347 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2348 2349 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2350 2351 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2352 2353 if (dp_is_128b_132b_signal(pipe_ctx)) 2354 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2355 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2356 return; 2357 2358 if (pipe_ctx->stream->sink) { 2359 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2360 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2361 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2362 pipe_ctx->stream->sink->edid_caps.display_name, 2363 pipe_ctx->stream->signal); 2364 } 2365 } 2366 2367 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2368 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2369 set_avmute(pipe_ctx, true); 2370 } 2371 2372 dc->hwss.disable_audio_stream(pipe_ctx); 2373 2374 update_psp_stream_config(pipe_ctx, true); 2375 dc->hwss.blank_stream(pipe_ctx); 2376 2377 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2378 deallocate_usb4_bandwidth(pipe_ctx->stream); 2379 2380 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2381 deallocate_mst_payload(pipe_ctx); 2382 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2383 dp_is_128b_132b_signal(pipe_ctx)) 2384 update_sst_payload(pipe_ctx, false); 2385 2386 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2387 struct ext_hdmi_settings settings = {0}; 2388 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2389 2390 unsigned short masked_chip_caps = link->chip_caps & 2391 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2392 //Need to inform that sink is going to use legacy HDMI mode. 2393 write_scdc_data( 2394 link->ddc, 2395 165000,//vbios only handles 165Mhz. 2396 false); 2397 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2398 /* DP159, Retimer settings */ 2399 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2400 write_i2c_retimer_setting(pipe_ctx, 2401 false, false, &settings); 2402 else 2403 write_i2c_default_retimer_setting(pipe_ctx, 2404 false, false); 2405 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2406 /* PI3EQX1204, Redriver settings */ 2407 write_i2c_redriver_setting(pipe_ctx, false); 2408 } 2409 } 2410 2411 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2412 !dp_is_128b_132b_signal(pipe_ctx)) { 2413 2414 /* In DP1.x SST mode, our encoder will go to TPS1 2415 * when link is on but stream is off. 2416 * Disabling link before stream will avoid exposing TPS1 pattern 2417 * during the disable sequence as it will confuse some receivers 2418 * state machine. 2419 * In DP2 or MST mode, our encoder will stay video active 2420 */ 2421 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2422 dc->hwss.disable_stream(pipe_ctx); 2423 } else { 2424 dc->hwss.disable_stream(pipe_ctx); 2425 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2426 } 2427 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2428 2429 if (pipe_ctx->stream->timing.flags.DSC) { 2430 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2431 link_set_dsc_enable(pipe_ctx, false); 2432 } 2433 if (dp_is_128b_132b_signal(pipe_ctx)) { 2434 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2435 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2436 } 2437 2438 if (vpg && vpg->funcs->vpg_powerdown) 2439 vpg->funcs->vpg_powerdown(vpg); 2440 2441 /* for psp not exist case */ 2442 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2443 /* reset internal save state to default since eDP is off */ 2444 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2445 /* since current psp not loaded, we need to reset it to default */ 2446 link->panel_mode = panel_mode; 2447 } 2448 } 2449 2450 void link_set_dpms_on( 2451 struct dc_state *state, 2452 struct pipe_ctx *pipe_ctx) 2453 { 2454 struct dc *dc = pipe_ctx->stream->ctx->dc; 2455 struct dc_stream_state *stream = pipe_ctx->stream; 2456 struct dc_link *link = stream->sink->link; 2457 enum dc_status status; 2458 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 2459 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2460 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2461 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2462 bool apply_edp_fast_boot_optimization = 2463 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2464 2465 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2466 2467 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2468 2469 if (dp_is_128b_132b_signal(pipe_ctx)) 2470 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2471 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2472 return; 2473 2474 if (pipe_ctx->stream->sink) { 2475 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2476 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2477 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2478 pipe_ctx->stream->sink->edid_caps.display_name, 2479 pipe_ctx->stream->signal); 2480 } 2481 } 2482 2483 if (!dc->config.unify_link_enc_assignment) 2484 link_enc = link_enc_cfg_get_link_enc(link); 2485 ASSERT(link_enc); 2486 2487 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2488 && !dp_is_128b_132b_signal(pipe_ctx)) { 2489 if (link_enc) 2490 link_enc->funcs->setup( 2491 link_enc, 2492 pipe_ctx->stream->signal); 2493 } 2494 2495 pipe_ctx->stream->link->link_state_valid = true; 2496 2497 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2498 if (dp_is_128b_132b_signal(pipe_ctx)) 2499 otg_out_dest = OUT_MUX_HPO_DP; 2500 else 2501 otg_out_dest = OUT_MUX_DIO; 2502 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2503 } 2504 2505 link_hwss->setup_stream_attribute(pipe_ctx); 2506 2507 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2508 2509 // Enable VPG before building infoframe 2510 if (vpg && vpg->funcs->vpg_poweron) 2511 vpg->funcs->vpg_poweron(vpg); 2512 2513 resource_build_info_frame(pipe_ctx); 2514 dc->hwss.update_info_frame(pipe_ctx); 2515 2516 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2517 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2518 2519 /* Do not touch link on seamless boot optimization. */ 2520 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2521 pipe_ctx->stream->dpms_off = false; 2522 2523 /* Still enable stream features & audio on seamless boot for DP external displays */ 2524 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2525 enable_stream_features(pipe_ctx); 2526 dc->hwss.enable_audio_stream(pipe_ctx); 2527 } 2528 2529 update_psp_stream_config(pipe_ctx, false); 2530 return; 2531 } 2532 2533 /* eDP lit up by bios already, no need to enable again. */ 2534 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2535 apply_edp_fast_boot_optimization && 2536 !pipe_ctx->stream->timing.flags.DSC && 2537 !pipe_ctx->next_odm_pipe) { 2538 pipe_ctx->stream->dpms_off = false; 2539 update_psp_stream_config(pipe_ctx, false); 2540 return; 2541 } 2542 2543 if (pipe_ctx->stream->dpms_off) 2544 return; 2545 2546 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2547 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2548 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2549 */ 2550 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2551 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2552 return; 2553 } 2554 2555 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2556 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2557 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2558 * will be automatically set at a later time when the video is enabled 2559 * (DP_VID_STREAM_EN = 1). 2560 */ 2561 if (pipe_ctx->stream->timing.flags.DSC) { 2562 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2563 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2564 link_set_dsc_enable(pipe_ctx, true); 2565 } 2566 2567 status = enable_link(state, pipe_ctx); 2568 2569 if (status != DC_OK) { 2570 DC_LOG_WARNING("enabling link %u failed: %d\n", 2571 pipe_ctx->stream->link->link_index, 2572 status); 2573 2574 /* Abort stream enable *unless* the failure was due to 2575 * DP link training - some DP monitors will recover and 2576 * show the stream anyway. But MST displays can't proceed 2577 * without link training. 2578 */ 2579 if (status != DC_FAIL_DP_LINK_TRAINING || 2580 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2581 if (false == stream->link->link_status.link_active) 2582 disable_link(stream->link, &pipe_ctx->link_res, 2583 pipe_ctx->stream->signal); 2584 BREAK_TO_DEBUGGER(); 2585 return; 2586 } 2587 } 2588 2589 /* turn off otg test pattern if enable */ 2590 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2591 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2592 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2593 COLOR_DEPTH_UNDEFINED); 2594 2595 /* This second call is needed to reconfigure the DIG 2596 * as a workaround for the incorrect value being applied 2597 * from transmitter control. 2598 */ 2599 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2600 dp_is_128b_132b_signal(pipe_ctx))) { 2601 2602 if (link_enc) 2603 link_enc->funcs->setup( 2604 link_enc, 2605 pipe_ctx->stream->signal); 2606 2607 } 2608 2609 dc->hwss.enable_stream(pipe_ctx); 2610 2611 /* Set DPS PPS SDP (AKA "info frames") */ 2612 if (pipe_ctx->stream->timing.flags.DSC) { 2613 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2614 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2615 dp_set_dsc_on_rx(pipe_ctx, true); 2616 link_set_dsc_pps_packet(pipe_ctx, true, true); 2617 } 2618 } 2619 2620 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2621 dp_set_hblank_reduction_on_rx(pipe_ctx); 2622 2623 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2624 allocate_usb4_bandwidth(pipe_ctx->stream); 2625 2626 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2627 allocate_mst_payload(pipe_ctx); 2628 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2629 dp_is_128b_132b_signal(pipe_ctx)) 2630 update_sst_payload(pipe_ctx, true); 2631 2632 dc->hwss.unblank_stream(pipe_ctx, 2633 &pipe_ctx->stream->link->cur_link_settings); 2634 2635 if (stream->sink_patches.delay_ignore_msa > 0) 2636 msleep(stream->sink_patches.delay_ignore_msa); 2637 2638 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2639 enable_stream_features(pipe_ctx); 2640 update_psp_stream_config(pipe_ctx, false); 2641 2642 dc->hwss.enable_audio_stream(pipe_ctx); 2643 2644 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2645 set_avmute(pipe_ctx, false); 2646 } 2647 } 2648