1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) && 144 (link->type != dc_connection_none)) 145 dpcd_write_rx_power_ctrl(link, false); 146 } 147 } 148 149 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 150 { 151 struct pipe_ctx *pipes[MAX_PIPES]; 152 struct dc_stream_state *streams[MAX_PIPES]; 153 struct dc_state *state = link->dc->current_state; 154 uint8_t count; 155 int i; 156 struct dc_stream_update stream_update; 157 bool dpms_off = true; 158 struct link_resource link_res = {0}; 159 160 memset(&stream_update, 0, sizeof(stream_update)); 161 stream_update.dpms_off = &dpms_off; 162 163 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 164 165 /* The subsequent call to dc_commit_updates_for_stream for a full update 166 * will release the current state and swap to a new state. Releasing the 167 * current state results in the stream pointers in the pipe_ctx structs 168 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream. 169 */ 170 for (i = 0; i < count; i++) 171 streams[i] = pipes[i]->stream; 172 173 for (i = 0; i < count; i++) { 174 stream_update.stream = streams[i]; 175 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 176 streams[i], &stream_update, 177 state); 178 } 179 180 /* link can be also enabled by vbios. In this case it is not recorded 181 * in pipe_ctx. Disable link phy here to make sure it is completely off 182 */ 183 dp_disable_link_phy(link, &link_res, link->connector_signal); 184 } 185 186 void link_resume(struct dc_link *link) 187 { 188 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 189 program_hpd_filter(link); 190 } 191 192 /* This function returns true if the pipe is used to feed video signal directly 193 * to the link. 194 */ 195 static bool is_master_pipe_for_link(const struct dc_link *link, 196 const struct pipe_ctx *pipe) 197 { 198 return resource_is_pipe_type(pipe, OTG_MASTER) && 199 pipe->stream->link == link; 200 } 201 202 /* 203 * This function finds all master pipes feeding to a given link with dpms set to 204 * on in given dc state. 205 */ 206 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 207 struct dc_state *state, 208 uint8_t *count, 209 struct pipe_ctx *pipes[MAX_PIPES]) 210 { 211 int i; 212 struct pipe_ctx *pipe = NULL; 213 214 *count = 0; 215 for (i = 0; i < MAX_PIPES; i++) { 216 pipe = &state->res_ctx.pipe_ctx[i]; 217 218 if (is_master_pipe_for_link(link, pipe) && 219 pipe->stream->dpms_off == false) { 220 pipes[(*count)++] = pipe; 221 } 222 } 223 } 224 225 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 226 enum engine_id eng_id, 227 struct ext_hdmi_settings *settings) 228 { 229 bool result = false; 230 int i = 0; 231 struct integrated_info *integrated_info = 232 pipe_ctx->stream->ctx->dc_bios->integrated_info; 233 234 if (integrated_info == NULL) 235 return false; 236 237 /* 238 * Get retimer settings from sbios for passing SI eye test for DCE11 239 * The setting values are varied based on board revision and port id 240 * Therefore the setting values of each ports is passed by sbios. 241 */ 242 243 // Check if current bios contains ext Hdmi settings 244 if (integrated_info->gpu_cap_info & 0x20) { 245 switch (eng_id) { 246 case ENGINE_ID_DIGA: 247 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 248 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 249 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 250 memmove(settings->reg_settings, 251 integrated_info->dp0_ext_hdmi_reg_settings, 252 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 253 memmove(settings->reg_settings_6g, 254 integrated_info->dp0_ext_hdmi_6g_reg_settings, 255 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 256 result = true; 257 break; 258 case ENGINE_ID_DIGB: 259 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 260 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 261 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 262 memmove(settings->reg_settings, 263 integrated_info->dp1_ext_hdmi_reg_settings, 264 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 265 memmove(settings->reg_settings_6g, 266 integrated_info->dp1_ext_hdmi_6g_reg_settings, 267 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 268 result = true; 269 break; 270 case ENGINE_ID_DIGC: 271 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 272 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 273 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 274 memmove(settings->reg_settings, 275 integrated_info->dp2_ext_hdmi_reg_settings, 276 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 277 memmove(settings->reg_settings_6g, 278 integrated_info->dp2_ext_hdmi_6g_reg_settings, 279 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 280 result = true; 281 break; 282 case ENGINE_ID_DIGD: 283 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 284 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 285 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 286 memmove(settings->reg_settings, 287 integrated_info->dp3_ext_hdmi_reg_settings, 288 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 289 memmove(settings->reg_settings_6g, 290 integrated_info->dp3_ext_hdmi_6g_reg_settings, 291 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 292 result = true; 293 break; 294 default: 295 break; 296 } 297 298 if (result == true) { 299 // Validate settings from bios integrated info table 300 if (settings->slv_addr == 0) 301 return false; 302 if (settings->reg_num > 9) 303 return false; 304 if (settings->reg_num_6g > 3) 305 return false; 306 307 for (i = 0; i < settings->reg_num; i++) { 308 if (settings->reg_settings[i].i2c_reg_index > 0x20) 309 return false; 310 } 311 312 for (i = 0; i < settings->reg_num_6g; i++) { 313 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 314 return false; 315 } 316 } 317 } 318 319 return result; 320 } 321 322 static bool write_i2c(struct pipe_ctx *pipe_ctx, 323 uint8_t address, uint8_t *buffer, uint32_t length) 324 { 325 struct i2c_command cmd = {0}; 326 struct i2c_payload payload = {0}; 327 328 memset(&payload, 0, sizeof(payload)); 329 memset(&cmd, 0, sizeof(cmd)); 330 331 cmd.number_of_payloads = 1; 332 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 333 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 334 335 payload.address = address; 336 payload.data = buffer; 337 payload.length = length; 338 payload.write = true; 339 cmd.payloads = &payload; 340 341 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 342 pipe_ctx->stream->link, &cmd)) 343 return true; 344 345 return false; 346 } 347 348 static void write_i2c_retimer_setting( 349 struct pipe_ctx *pipe_ctx, 350 bool is_vga_mode, 351 bool is_over_340mhz, 352 struct ext_hdmi_settings *settings) 353 { 354 uint8_t slave_address = (settings->slv_addr >> 1); 355 uint8_t buffer[2]; 356 const uint8_t apply_rx_tx_change = 0x4; 357 uint8_t offset = 0xA; 358 uint8_t value = 0; 359 int i = 0; 360 bool i2c_success = false; 361 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 362 363 memset(&buffer, 0, sizeof(buffer)); 364 365 /* Start Ext-Hdmi programming*/ 366 367 for (i = 0; i < settings->reg_num; i++) { 368 /* Apply 3G settings */ 369 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 370 371 buffer[0] = settings->reg_settings[i].i2c_reg_index; 372 buffer[1] = settings->reg_settings[i].i2c_reg_val; 373 i2c_success = write_i2c(pipe_ctx, slave_address, 374 buffer, sizeof(buffer)); 375 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 376 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 377 slave_address, buffer[0], buffer[1], i2c_success?1:0); 378 379 if (!i2c_success) 380 goto i2c_write_fail; 381 382 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 383 * needs to be set to 1 on every 0xA-0xC write. 384 */ 385 if (settings->reg_settings[i].i2c_reg_index == 0xA || 386 settings->reg_settings[i].i2c_reg_index == 0xB || 387 settings->reg_settings[i].i2c_reg_index == 0xC) { 388 389 /* Query current value from offset 0xA */ 390 if (settings->reg_settings[i].i2c_reg_index == 0xA) 391 value = settings->reg_settings[i].i2c_reg_val; 392 else { 393 i2c_success = 394 link_query_ddc_data( 395 pipe_ctx->stream->link->ddc, 396 slave_address, &offset, 1, &value, 1); 397 if (!i2c_success) 398 goto i2c_write_fail; 399 } 400 401 buffer[0] = offset; 402 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 403 buffer[1] = value | apply_rx_tx_change; 404 i2c_success = write_i2c(pipe_ctx, slave_address, 405 buffer, sizeof(buffer)); 406 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 407 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 408 slave_address, buffer[0], buffer[1], i2c_success?1:0); 409 if (!i2c_success) 410 goto i2c_write_fail; 411 } 412 } 413 } 414 415 /* Apply 3G settings */ 416 if (is_over_340mhz) { 417 for (i = 0; i < settings->reg_num_6g; i++) { 418 /* Apply 3G settings */ 419 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 420 421 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 422 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 423 i2c_success = write_i2c(pipe_ctx, slave_address, 424 buffer, sizeof(buffer)); 425 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 426 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 427 slave_address, buffer[0], buffer[1], i2c_success?1:0); 428 429 if (!i2c_success) 430 goto i2c_write_fail; 431 432 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 433 * needs to be set to 1 on every 0xA-0xC write. 434 */ 435 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 436 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 437 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 438 439 /* Query current value from offset 0xA */ 440 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 441 value = settings->reg_settings_6g[i].i2c_reg_val; 442 else { 443 i2c_success = 444 link_query_ddc_data( 445 pipe_ctx->stream->link->ddc, 446 slave_address, &offset, 1, &value, 1); 447 if (!i2c_success) 448 goto i2c_write_fail; 449 } 450 451 buffer[0] = offset; 452 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 453 buffer[1] = value | apply_rx_tx_change; 454 i2c_success = write_i2c(pipe_ctx, slave_address, 455 buffer, sizeof(buffer)); 456 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 457 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 458 slave_address, buffer[0], buffer[1], i2c_success?1:0); 459 if (!i2c_success) 460 goto i2c_write_fail; 461 } 462 } 463 } 464 } 465 466 if (is_vga_mode) { 467 /* Program additional settings if using 640x480 resolution */ 468 469 /* Write offset 0xFF to 0x01 */ 470 buffer[0] = 0xff; 471 buffer[1] = 0x01; 472 i2c_success = write_i2c(pipe_ctx, slave_address, 473 buffer, sizeof(buffer)); 474 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 475 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 476 slave_address, buffer[0], buffer[1], i2c_success?1:0); 477 if (!i2c_success) 478 goto i2c_write_fail; 479 480 /* Write offset 0x00 to 0x23 */ 481 buffer[0] = 0x00; 482 buffer[1] = 0x23; 483 i2c_success = write_i2c(pipe_ctx, slave_address, 484 buffer, sizeof(buffer)); 485 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 486 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 487 slave_address, buffer[0], buffer[1], i2c_success?1:0); 488 if (!i2c_success) 489 goto i2c_write_fail; 490 491 /* Write offset 0xff to 0x00 */ 492 buffer[0] = 0xff; 493 buffer[1] = 0x00; 494 i2c_success = write_i2c(pipe_ctx, slave_address, 495 buffer, sizeof(buffer)); 496 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 497 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 498 slave_address, buffer[0], buffer[1], i2c_success?1:0); 499 if (!i2c_success) 500 goto i2c_write_fail; 501 502 } 503 504 return; 505 506 i2c_write_fail: 507 DC_LOG_DEBUG("Set retimer failed"); 508 } 509 510 static void write_i2c_default_retimer_setting( 511 struct pipe_ctx *pipe_ctx, 512 bool is_vga_mode, 513 bool is_over_340mhz) 514 { 515 uint8_t slave_address = (0xBA >> 1); 516 uint8_t buffer[2]; 517 bool i2c_success = false; 518 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 519 520 memset(&buffer, 0, sizeof(buffer)); 521 522 /* Program Slave Address for tuning single integrity */ 523 /* Write offset 0x0A to 0x13 */ 524 buffer[0] = 0x0A; 525 buffer[1] = 0x13; 526 i2c_success = write_i2c(pipe_ctx, slave_address, 527 buffer, sizeof(buffer)); 528 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 529 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 530 slave_address, buffer[0], buffer[1], i2c_success?1:0); 531 if (!i2c_success) 532 goto i2c_write_fail; 533 534 /* Write offset 0x0A to 0x17 */ 535 buffer[0] = 0x0A; 536 buffer[1] = 0x17; 537 i2c_success = write_i2c(pipe_ctx, slave_address, 538 buffer, sizeof(buffer)); 539 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 540 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 541 slave_address, buffer[0], buffer[1], i2c_success?1:0); 542 if (!i2c_success) 543 goto i2c_write_fail; 544 545 /* Write offset 0x0B to 0xDA or 0xD8 */ 546 buffer[0] = 0x0B; 547 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 548 i2c_success = write_i2c(pipe_ctx, slave_address, 549 buffer, sizeof(buffer)); 550 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 551 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 552 slave_address, buffer[0], buffer[1], i2c_success?1:0); 553 if (!i2c_success) 554 goto i2c_write_fail; 555 556 /* Write offset 0x0A to 0x17 */ 557 buffer[0] = 0x0A; 558 buffer[1] = 0x17; 559 i2c_success = write_i2c(pipe_ctx, slave_address, 560 buffer, sizeof(buffer)); 561 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 562 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 563 slave_address, buffer[0], buffer[1], i2c_success?1:0); 564 if (!i2c_success) 565 goto i2c_write_fail; 566 567 /* Write offset 0x0C to 0x1D or 0x91 */ 568 buffer[0] = 0x0C; 569 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 570 i2c_success = write_i2c(pipe_ctx, slave_address, 571 buffer, sizeof(buffer)); 572 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 573 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 574 slave_address, buffer[0], buffer[1], i2c_success?1:0); 575 if (!i2c_success) 576 goto i2c_write_fail; 577 578 /* Write offset 0x0A to 0x17 */ 579 buffer[0] = 0x0A; 580 buffer[1] = 0x17; 581 i2c_success = write_i2c(pipe_ctx, slave_address, 582 buffer, sizeof(buffer)); 583 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 584 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 585 slave_address, buffer[0], buffer[1], i2c_success?1:0); 586 if (!i2c_success) 587 goto i2c_write_fail; 588 589 590 if (is_vga_mode) { 591 /* Program additional settings if using 640x480 resolution */ 592 593 /* Write offset 0xFF to 0x01 */ 594 buffer[0] = 0xff; 595 buffer[1] = 0x01; 596 i2c_success = write_i2c(pipe_ctx, slave_address, 597 buffer, sizeof(buffer)); 598 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 599 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 600 slave_address, buffer[0], buffer[1], i2c_success?1:0); 601 if (!i2c_success) 602 goto i2c_write_fail; 603 604 /* Write offset 0x00 to 0x23 */ 605 buffer[0] = 0x00; 606 buffer[1] = 0x23; 607 i2c_success = write_i2c(pipe_ctx, slave_address, 608 buffer, sizeof(buffer)); 609 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 610 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 611 slave_address, buffer[0], buffer[1], i2c_success?1:0); 612 if (!i2c_success) 613 goto i2c_write_fail; 614 615 /* Write offset 0xff to 0x00 */ 616 buffer[0] = 0xff; 617 buffer[1] = 0x00; 618 i2c_success = write_i2c(pipe_ctx, slave_address, 619 buffer, sizeof(buffer)); 620 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 621 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 622 slave_address, buffer[0], buffer[1], i2c_success?1:0); 623 if (!i2c_success) 624 goto i2c_write_fail; 625 } 626 627 return; 628 629 i2c_write_fail: 630 DC_LOG_DEBUG("Set default retimer failed"); 631 } 632 633 static void write_i2c_redriver_setting( 634 struct pipe_ctx *pipe_ctx, 635 bool is_over_340mhz) 636 { 637 uint8_t slave_address = (0xF0 >> 1); 638 uint8_t buffer[16]; 639 bool i2c_success = false; 640 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 641 642 memset(&buffer, 0, sizeof(buffer)); 643 644 // Program Slave Address for tuning single integrity 645 buffer[3] = 0x4E; 646 buffer[4] = 0x4E; 647 buffer[5] = 0x4E; 648 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 649 650 i2c_success = write_i2c(pipe_ctx, slave_address, 651 buffer, sizeof(buffer)); 652 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 653 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 654 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 655 i2c_success = %d\n", 656 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 657 658 if (!i2c_success) 659 DC_LOG_DEBUG("Set redriver failed"); 660 } 661 662 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 663 { 664 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 665 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 666 struct cp_psp_stream_config config = {0}; 667 enum dp_panel_mode panel_mode = 668 dp_get_panel_mode(pipe_ctx->stream->link); 669 670 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 671 return; 672 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 673 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 674 ASSERT(link_enc); 675 if (link_enc == NULL) 676 return; 677 678 /* otg instance */ 679 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 680 681 /* dig front end */ 682 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 683 684 /* stream encoder index */ 685 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 686 if (dp_is_128b_132b_signal(pipe_ctx)) 687 config.stream_enc_idx = 688 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 689 690 /* dig back end */ 691 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 692 693 /* link encoder index */ 694 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 695 if (dp_is_128b_132b_signal(pipe_ctx)) 696 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 697 698 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 699 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 700 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 701 else 702 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 703 704 705 /* phy index */ 706 config.phy_idx = resource_transmitter_to_phy_idx( 707 pipe_ctx->stream->link->dc, link_enc->transmitter); 708 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 709 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 710 config.phy_idx = 0; 711 712 /* stream properties */ 713 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 714 config.mst_enabled = (pipe_ctx->stream->signal == 715 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 716 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 717 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 718 1 : 0; 719 config.dpms_off = dpms_off; 720 721 /* dm stream context */ 722 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 723 724 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 725 } 726 727 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 728 { 729 struct dc *dc = pipe_ctx->stream->ctx->dc; 730 731 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 732 return; 733 734 dc->hwss.set_avmute(pipe_ctx, enable); 735 } 736 737 static void enable_mst_on_sink(struct dc_link *link, bool enable) 738 { 739 unsigned char mstmCntl = 0; 740 741 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 742 if (enable) 743 mstmCntl |= DP_MST_EN; 744 else 745 mstmCntl &= (~DP_MST_EN); 746 747 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 748 } 749 750 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 751 struct dsc_optc_config *config) 752 { 753 uint32_t precision = 1 << 28; 754 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 755 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 756 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 757 DC_LOGGER_INIT(dsc->ctx->logger); 758 759 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 760 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 761 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 762 */ 763 ll_bytes_per_pix_fraq *= 10000000; 764 ll_bytes_per_pix_fraq /= precision; 765 766 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 767 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 768 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 769 DC_LOG_DSC("\tslice_width %d", config->slice_width); 770 } 771 772 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 773 { 774 struct dc *dc = pipe_ctx->stream->ctx->dc; 775 struct dc_stream_state *stream = pipe_ctx->stream; 776 bool result = false; 777 778 if (dc_is_virtual_signal(stream->signal)) 779 result = true; 780 else 781 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 782 return result; 783 } 784 785 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 786 { 787 struct dc *dc = pipe_ctx->stream->ctx->dc; 788 struct dc_stream_state *stream = pipe_ctx->stream; 789 bool result = false; 790 791 if (dc_is_virtual_signal(stream->signal)) 792 result = true; 793 else 794 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 795 return result; 796 } 797 798 799 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 800 * i.e. after dp_enable_dsc_on_rx() had been called 801 */ 802 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 803 { 804 /* TODO: Move this to HWSS as this is hardware programming sequence not a 805 * link layer sequence 806 */ 807 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 808 struct dc *dc = pipe_ctx->stream->ctx->dc; 809 struct dc_stream_state *stream = pipe_ctx->stream; 810 struct pipe_ctx *odm_pipe; 811 int opp_cnt = 1; 812 struct dccg *dccg = dc->res_pool->dccg; 813 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 814 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 815 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 816 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 817 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 818 * this problem. We are implementing a workaround here to keep using dscclk 819 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 820 * 48Mhz) pixel clock to avoid hitting this problem. 821 */ 822 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 823 stream->timing.pix_clk_100hz > 480000; 824 DC_LOGGER_INIT(dsc->ctx->logger); 825 826 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 827 opp_cnt++; 828 829 if (enable) { 830 struct dsc_config dsc_cfg; 831 struct dsc_optc_config dsc_optc_cfg = {0}; 832 enum optc_dsc_mode optc_dsc_mode; 833 834 /* Enable DSC hw block */ 835 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow + 836 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 837 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 838 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 839 dsc_cfg.color_depth = stream->timing.display_color_depth; 840 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 841 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 842 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 843 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 844 845 if (should_use_dto_dscclk) 846 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 847 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 848 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 849 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 850 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 851 852 if (should_use_dto_dscclk) 853 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 854 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 855 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 856 } 857 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 858 dsc_cfg.pic_width *= opp_cnt; 859 860 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 861 862 /* Enable DSC in encoder */ 863 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 864 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 865 dsc_optc_config_log(dsc, &dsc_optc_cfg); 866 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 867 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 868 optc_dsc_mode, 869 dsc_optc_cfg.bytes_per_pixel, 870 dsc_optc_cfg.slice_width); 871 872 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 873 } 874 875 /* Enable DSC in OPTC */ 876 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 877 dsc_optc_config_log(dsc, &dsc_optc_cfg); 878 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 879 optc_dsc_mode, 880 dsc_optc_cfg.bytes_per_pixel, 881 dsc_optc_cfg.slice_width); 882 } else { 883 /* disable DSC in OPTC */ 884 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 885 pipe_ctx->stream_res.tg, 886 OPTC_DSC_DISABLED, 0, 0); 887 888 /* disable DSC in stream encoder */ 889 if (dc_is_dp_signal(stream->signal)) { 890 if (dp_is_128b_132b_signal(pipe_ctx)) 891 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 892 pipe_ctx->stream_res.hpo_dp_stream_enc, 893 false, 894 NULL, 895 true); 896 else { 897 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 898 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 899 pipe_ctx->stream_res.stream_enc, 900 OPTC_DSC_DISABLED, 0, 0); 901 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 902 pipe_ctx->stream_res.stream_enc, false, NULL, true); 903 } 904 } 905 906 /* disable DSC block */ 907 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 908 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 909 /* 910 * TODO - dsc_disconnect is a double buffered register. 911 * by the time we call dsc_disable, dsc may still remain 912 * connected to OPP. In this case OPTC will no longer 913 * get correct pixel data because DSCC is off. However 914 * we also can't wait for the disconnect pending 915 * complete, because this function can be called 916 * with/without OTG master lock acquired. When the lock 917 * is acquired we will never get pending complete until 918 * we release the lock later. So there is no easy way to 919 * solve this problem especially when the lock is 920 * acquired. DSC is a front end hw block it should be 921 * programmed as part of front end sequence, where the 922 * commit sequence without lock and update sequence 923 * with lock are completely separated. However because 924 * we are programming dsc as part of back end link 925 * programming sequence, we don't know if front end OPTC 926 * master lock is acquired. The back end should be 927 * agnostic to front end lock. DSC programming shouldn't 928 * belong to this sequence. 929 */ 930 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 931 if (dccg->funcs->set_ref_dscclk) 932 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 933 } 934 } 935 } 936 937 /* 938 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 939 * hence PPS info packet update need to use frame update instead of immediate update. 940 * Added parameter immediate_update for this purpose. 941 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 942 * which is the only place where a "false" would be passed in for param immediate_update. 943 * 944 * immediate_update is only applicable when DSC is enabled. 945 */ 946 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 947 { 948 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 949 struct dc_stream_state *stream = pipe_ctx->stream; 950 951 if (!pipe_ctx->stream->timing.flags.DSC) 952 return false; 953 954 if (!dsc) 955 return false; 956 957 DC_LOGGER_INIT(dsc->ctx->logger); 958 959 if (enable) { 960 struct dsc_config dsc_cfg; 961 uint8_t dsc_packed_pps[128]; 962 963 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 964 memset(dsc_packed_pps, 0, 128); 965 966 /* Enable DSC hw block */ 967 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 968 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 969 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 970 dsc_cfg.color_depth = stream->timing.display_color_depth; 971 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 972 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 973 974 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 975 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 976 if (dc_is_dp_signal(stream->signal)) { 977 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 978 if (dp_is_128b_132b_signal(pipe_ctx)) 979 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 980 pipe_ctx->stream_res.hpo_dp_stream_enc, 981 true, 982 &dsc_packed_pps[0], 983 immediate_update); 984 else 985 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 986 pipe_ctx->stream_res.stream_enc, 987 true, 988 &dsc_packed_pps[0], 989 immediate_update); 990 } 991 } else { 992 /* disable DSC PPS in stream encoder */ 993 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 994 if (dc_is_dp_signal(stream->signal)) { 995 if (dp_is_128b_132b_signal(pipe_ctx)) 996 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 997 pipe_ctx->stream_res.hpo_dp_stream_enc, 998 false, 999 NULL, 1000 true); 1001 else 1002 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 1003 pipe_ctx->stream_res.stream_enc, false, NULL, true); 1004 } 1005 } 1006 1007 return true; 1008 } 1009 1010 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 1011 { 1012 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1013 bool result = false; 1014 1015 if (!pipe_ctx->stream->timing.flags.DSC) 1016 goto out; 1017 if (!dsc) 1018 goto out; 1019 1020 if (enable) { 1021 { 1022 link_set_dsc_on_stream(pipe_ctx, true); 1023 result = true; 1024 } 1025 } else { 1026 dp_set_dsc_on_rx(pipe_ctx, false); 1027 link_set_dsc_on_stream(pipe_ctx, false); 1028 result = true; 1029 } 1030 out: 1031 return result; 1032 } 1033 1034 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 1035 { 1036 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1037 1038 if (!pipe_ctx->stream->timing.flags.DSC) 1039 return false; 1040 if (!dsc) 1041 return false; 1042 1043 link_set_dsc_on_stream(pipe_ctx, true); 1044 link_set_dsc_pps_packet(pipe_ctx, true, false); 1045 return true; 1046 } 1047 1048 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1049 { 1050 struct dc_stream_state *stream = pipe_ctx->stream; 1051 1052 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1053 struct dc_link *link = stream->link; 1054 union down_spread_ctrl old_downspread; 1055 union down_spread_ctrl new_downspread; 1056 1057 memset(&old_downspread, 0, sizeof(old_downspread)); 1058 1059 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1060 &old_downspread.raw, sizeof(old_downspread)); 1061 1062 new_downspread.raw = old_downspread.raw; 1063 1064 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1065 (stream->ignore_msa_timing_param) ? 1 : 0; 1066 1067 if (new_downspread.raw != old_downspread.raw) { 1068 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1069 &new_downspread.raw, sizeof(new_downspread)); 1070 } 1071 1072 } else { 1073 dm_helpers_mst_enable_stream_features(stream); 1074 } 1075 } 1076 1077 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1078 { 1079 const uint32_t VCP_Y_PRECISION = 1000; 1080 uint64_t vcp_x, vcp_y; 1081 DC_LOGGER_INIT(link->ctx->logger); 1082 1083 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1084 avg_time_slots_per_mtp = dc_fixpt_add( 1085 avg_time_slots_per_mtp, 1086 dc_fixpt_from_fraction( 1087 1, 1088 2*VCP_Y_PRECISION)); 1089 1090 vcp_x = dc_fixpt_floor( 1091 avg_time_slots_per_mtp); 1092 vcp_y = dc_fixpt_floor( 1093 dc_fixpt_mul_int( 1094 dc_fixpt_sub_int( 1095 avg_time_slots_per_mtp, 1096 dc_fixpt_floor( 1097 avg_time_slots_per_mtp)), 1098 VCP_Y_PRECISION)); 1099 1100 1101 if (link->type == dc_connection_mst_branch) 1102 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1103 "X: %llu " 1104 "Y: %llu/%d", 1105 vcp_x, 1106 vcp_y, 1107 VCP_Y_PRECISION); 1108 else 1109 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1110 "X: %llu " 1111 "Y: %llu/%d", 1112 vcp_x, 1113 vcp_y, 1114 VCP_Y_PRECISION); 1115 } 1116 1117 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1118 { 1119 struct fixed31_32 mbytes_per_sec; 1120 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1121 &stream->link->cur_link_settings); 1122 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1123 1124 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1125 1126 return dc_fixpt_div_int(mbytes_per_sec, 54); 1127 } 1128 1129 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1130 { 1131 struct fixed31_32 peak_kbps; 1132 uint32_t numerator = 0; 1133 uint32_t denominator = 1; 1134 1135 /* 1136 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1137 * required when determining PBN/time slot utilization on the link between 1138 * us and the branch, since that overhead is already accounted for in 1139 * the get_pbn_per_slot function. 1140 * 1141 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1142 * common multiplier to render an integer PBN for all link rate/lane 1143 * counts combinations 1144 * calculate 1145 * peak_kbps *= (64/54) 1146 * peak_kbps /= (8 * 1000) convert to bytes 1147 */ 1148 1149 numerator = 64; 1150 denominator = 54 * 8 * 1000; 1151 kbps *= numerator; 1152 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1153 1154 return peak_kbps; 1155 } 1156 1157 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1158 { 1159 uint64_t kbps; 1160 enum dc_link_encoding_format link_encoding; 1161 1162 if (dp_is_128b_132b_signal(pipe_ctx)) 1163 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1164 else 1165 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1166 1167 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1168 return get_pbn_from_bw_in_kbps(kbps); 1169 } 1170 1171 1172 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1173 static void get_lane_status( 1174 struct dc_link *link, 1175 uint32_t lane_count, 1176 union lane_status *status, 1177 union lane_align_status_updated *status_updated) 1178 { 1179 unsigned int lane; 1180 uint8_t dpcd_buf[3] = {0}; 1181 1182 if (status == NULL || status_updated == NULL) { 1183 return; 1184 } 1185 1186 core_link_read_dpcd( 1187 link, 1188 DP_LANE0_1_STATUS, 1189 dpcd_buf, 1190 sizeof(dpcd_buf)); 1191 1192 for (lane = 0; lane < lane_count; lane++) { 1193 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1194 } 1195 1196 status_updated->raw = dpcd_buf[2]; 1197 } 1198 1199 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1200 { 1201 /* 1202 * wait for ACT handled 1203 */ 1204 int i; 1205 const int act_retries = 30; 1206 enum act_return_status result = ACT_FAILED; 1207 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1208 union payload_table_update_status update_status = {0}; 1209 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1210 union lane_align_status_updated lane_status_updated; 1211 DC_LOGGER_INIT(link->ctx->logger); 1212 1213 if (!display_connected || link->aux_access_disabled) 1214 return true; 1215 for (i = 0; i < act_retries; i++) { 1216 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1217 1218 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1219 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1220 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1221 !dp_is_interlane_aligned(lane_status_updated)) { 1222 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1223 "polling for ACT handled."); 1224 result = ACT_LINK_LOST; 1225 break; 1226 } 1227 core_link_read_dpcd( 1228 link, 1229 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1230 &update_status.raw, 1231 1); 1232 1233 if (update_status.bits.ACT_HANDLED == 1) { 1234 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1235 result = ACT_SUCCESS; 1236 break; 1237 } 1238 1239 fsleep(5000); 1240 } 1241 1242 if (result == ACT_FAILED) { 1243 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1244 "continue on. Something is wrong with the branch."); 1245 } 1246 1247 return (result == ACT_SUCCESS); 1248 } 1249 1250 static void update_mst_stream_alloc_table( 1251 struct dc_link *link, 1252 struct stream_encoder *stream_enc, 1253 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1254 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1255 { 1256 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1257 struct link_mst_stream_allocation *dc_alloc; 1258 1259 int i; 1260 int j; 1261 1262 /* if DRM proposed_table has more than one new payload */ 1263 ASSERT(proposed_table->stream_count - 1264 link->mst_stream_alloc_table.stream_count < 2); 1265 1266 /* copy proposed_table to link, add stream encoder */ 1267 for (i = 0; i < proposed_table->stream_count; i++) { 1268 1269 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1270 dc_alloc = 1271 &link->mst_stream_alloc_table.stream_allocations[j]; 1272 1273 if (dc_alloc->vcp_id == 1274 proposed_table->stream_allocations[i].vcp_id) { 1275 1276 work_table[i] = *dc_alloc; 1277 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1278 break; /* exit j loop */ 1279 } 1280 } 1281 1282 /* new vcp_id */ 1283 if (j == link->mst_stream_alloc_table.stream_count) { 1284 work_table[i].vcp_id = 1285 proposed_table->stream_allocations[i].vcp_id; 1286 work_table[i].slot_count = 1287 proposed_table->stream_allocations[i].slot_count; 1288 work_table[i].stream_enc = stream_enc; 1289 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1290 } 1291 } 1292 1293 /* update link->mst_stream_alloc_table with work_table */ 1294 link->mst_stream_alloc_table.stream_count = 1295 proposed_table->stream_count; 1296 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1297 link->mst_stream_alloc_table.stream_allocations[i] = 1298 work_table[i]; 1299 } 1300 1301 static void remove_stream_from_alloc_table( 1302 struct dc_link *link, 1303 struct stream_encoder *dio_stream_enc, 1304 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1305 { 1306 int i = 0; 1307 struct link_mst_stream_allocation_table *table = 1308 &link->mst_stream_alloc_table; 1309 1310 if (hpo_dp_stream_enc) { 1311 for (; i < table->stream_count; i++) 1312 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1313 break; 1314 } else { 1315 for (; i < table->stream_count; i++) 1316 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1317 break; 1318 } 1319 1320 if (i < table->stream_count) { 1321 i++; 1322 for (; i < table->stream_count; i++) 1323 table->stream_allocations[i-1] = table->stream_allocations[i]; 1324 memset(&table->stream_allocations[table->stream_count-1], 0, 1325 sizeof(struct link_mst_stream_allocation)); 1326 table->stream_count--; 1327 } 1328 } 1329 1330 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1331 { 1332 struct dc_stream_state *stream = pipe_ctx->stream; 1333 struct dc_link *link = stream->link; 1334 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1335 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1336 int i; 1337 bool mst_mode = (link->type == dc_connection_mst_branch); 1338 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1339 const struct dc_link_settings empty_link_settings = {0}; 1340 DC_LOGGER_INIT(link->ctx->logger); 1341 1342 /* deallocate_mst_payload is called before disable link. When mode or 1343 * disable/enable monitor, new stream is created which is not in link 1344 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1345 * should not done. For new mode set, map_resources will get engine 1346 * for new stream, so stream_enc->id should be validated until here. 1347 */ 1348 1349 /* slot X.Y */ 1350 if (link_hwss->ext.set_throttled_vcp_size) 1351 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1352 if (link_hwss->ext.set_hblank_min_symbol_width) 1353 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1354 &empty_link_settings, 1355 avg_time_slots_per_mtp); 1356 1357 if (mst_mode) { 1358 /* when link is in mst mode, reply on mst manager to remove 1359 * payload 1360 */ 1361 if (dm_helpers_dp_mst_write_payload_allocation_table( 1362 stream->ctx, 1363 stream, 1364 &proposed_table, 1365 false)) 1366 update_mst_stream_alloc_table( 1367 link, 1368 pipe_ctx->stream_res.stream_enc, 1369 pipe_ctx->stream_res.hpo_dp_stream_enc, 1370 &proposed_table); 1371 else 1372 DC_LOG_WARNING("Failed to update" 1373 "MST allocation table for" 1374 "pipe idx:%d\n", 1375 pipe_ctx->pipe_idx); 1376 } else { 1377 /* when link is no longer in mst mode (mst hub unplugged), 1378 * remove payload with default dc logic 1379 */ 1380 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1381 pipe_ctx->stream_res.hpo_dp_stream_enc); 1382 } 1383 1384 DC_LOG_MST("%s" 1385 "stream_count: %d: ", 1386 __func__, 1387 link->mst_stream_alloc_table.stream_count); 1388 1389 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1390 DC_LOG_MST("stream_enc[%d]: %p " 1391 "stream[%d].hpo_dp_stream_enc: %p " 1392 "stream[%d].vcp_id: %d " 1393 "stream[%d].slot_count: %d\n", 1394 i, 1395 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1396 i, 1397 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1398 i, 1399 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1400 i, 1401 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1402 } 1403 1404 /* update mst stream allocation table hardware state */ 1405 if (link_hwss->ext.update_stream_allocation_table == NULL || 1406 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1407 DC_LOG_DEBUG("Unknown encoding format\n"); 1408 return DC_ERROR_UNEXPECTED; 1409 } 1410 1411 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1412 &link->mst_stream_alloc_table); 1413 1414 if (mst_mode) 1415 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1416 stream->ctx, 1417 stream); 1418 1419 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1420 stream->ctx, 1421 stream); 1422 1423 return DC_OK; 1424 } 1425 1426 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1427 * because stream_encoder is not exposed to dm 1428 */ 1429 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1430 { 1431 struct dc_stream_state *stream = pipe_ctx->stream; 1432 struct dc_link *link = stream->link; 1433 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1434 struct fixed31_32 avg_time_slots_per_mtp; 1435 struct fixed31_32 pbn; 1436 struct fixed31_32 pbn_per_slot; 1437 int i; 1438 enum act_return_status ret; 1439 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1440 DC_LOGGER_INIT(link->ctx->logger); 1441 1442 /* enable_link_dp_mst already check link->enabled_stream_count 1443 * and stream is in link->stream[]. This is called during set mode, 1444 * stream_enc is available. 1445 */ 1446 1447 /* get calculate VC payload for stream: stream_alloc */ 1448 if (dm_helpers_dp_mst_write_payload_allocation_table( 1449 stream->ctx, 1450 stream, 1451 &proposed_table, 1452 true)) 1453 update_mst_stream_alloc_table( 1454 link, 1455 pipe_ctx->stream_res.stream_enc, 1456 pipe_ctx->stream_res.hpo_dp_stream_enc, 1457 &proposed_table); 1458 else 1459 DC_LOG_WARNING("Failed to update" 1460 "MST allocation table for" 1461 "pipe idx:%d\n", 1462 pipe_ctx->pipe_idx); 1463 1464 DC_LOG_MST("%s " 1465 "stream_count: %d: \n ", 1466 __func__, 1467 link->mst_stream_alloc_table.stream_count); 1468 1469 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1470 DC_LOG_MST("stream_enc[%d]: %p " 1471 "stream[%d].hpo_dp_stream_enc: %p " 1472 "stream[%d].vcp_id: %d " 1473 "stream[%d].slot_count: %d\n", 1474 i, 1475 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1476 i, 1477 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1478 i, 1479 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1480 i, 1481 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1482 } 1483 1484 ASSERT(proposed_table.stream_count > 0); 1485 1486 /* program DP source TX for payload */ 1487 if (link_hwss->ext.update_stream_allocation_table == NULL || 1488 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1489 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1490 return DC_ERROR_UNEXPECTED; 1491 } 1492 1493 link_hwss->ext.update_stream_allocation_table(link, 1494 &pipe_ctx->link_res, 1495 &link->mst_stream_alloc_table); 1496 1497 /* send down message */ 1498 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1499 stream->ctx, 1500 stream); 1501 1502 if (ret != ACT_LINK_LOST) 1503 dm_helpers_dp_mst_send_payload_allocation( 1504 stream->ctx, 1505 stream); 1506 1507 /* slot X.Y for only current stream */ 1508 pbn_per_slot = get_pbn_per_slot(stream); 1509 if (pbn_per_slot.value == 0) { 1510 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1511 return DC_UNSUPPORTED_VALUE; 1512 } 1513 pbn = get_pbn_from_timing(pipe_ctx); 1514 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1515 1516 log_vcp_x_y(link, avg_time_slots_per_mtp); 1517 1518 if (link_hwss->ext.set_throttled_vcp_size) 1519 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1520 if (link_hwss->ext.set_hblank_min_symbol_width) 1521 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1522 &link->cur_link_settings, 1523 avg_time_slots_per_mtp); 1524 1525 return DC_OK; 1526 } 1527 1528 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1529 const struct dc_stream_state *stream, 1530 const struct dc_link *link) 1531 { 1532 struct fixed31_32 link_bw_effective = 1533 dc_fixpt_from_int( 1534 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1535 struct fixed31_32 timeslot_bw_effective = 1536 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1537 struct fixed31_32 timing_bw = 1538 dc_fixpt_from_int( 1539 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1540 dc_link_get_highest_encoding_format(link))); 1541 struct fixed31_32 avg_time_slots_per_mtp = 1542 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1543 1544 return avg_time_slots_per_mtp; 1545 } 1546 1547 1548 static bool write_128b_132b_sst_payload_allocation_table( 1549 const struct dc_stream_state *stream, 1550 struct dc_link *link, 1551 struct link_mst_stream_allocation_table *proposed_table, 1552 bool allocate) 1553 { 1554 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1555 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1556 bool result = false; 1557 uint8_t req_slot_count = 0; 1558 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1559 union payload_table_update_status update_status = { 0 }; 1560 const uint32_t max_retries = 30; 1561 uint32_t retries = 0; 1562 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1563 DC_LOGGER_INIT(link->ctx->logger); 1564 1565 if (allocate) { 1566 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1567 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1568 /// Validation should filter out modes that exceed link BW 1569 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1570 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1571 return false; 1572 } else { 1573 /// Leave req_slot_count = 0 if allocate is false. 1574 } 1575 1576 proposed_table->stream_count = 1; /// Always 1 stream for SST 1577 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1578 proposed_table->stream_allocations[0].vcp_id = vc_id; 1579 1580 if (!display_connected || link->aux_access_disabled) 1581 return true; 1582 1583 /// Write DPCD 2C0 = 1 to start updating 1584 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1585 core_link_write_dpcd( 1586 link, 1587 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1588 &update_status.raw, 1589 1); 1590 1591 /// Program the changes in DPCD 1C0 - 1C2 1592 ASSERT(vc_id == 1); 1593 core_link_write_dpcd( 1594 link, 1595 DP_PAYLOAD_ALLOCATE_SET, 1596 &vc_id, 1597 1); 1598 1599 ASSERT(start_time_slot == 0); 1600 core_link_write_dpcd( 1601 link, 1602 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1603 &start_time_slot, 1604 1); 1605 1606 core_link_write_dpcd( 1607 link, 1608 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1609 &req_slot_count, 1610 1); 1611 1612 /// Poll till DPCD 2C0 read 1 1613 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1614 1615 while (retries < max_retries) { 1616 if (core_link_read_dpcd( 1617 link, 1618 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1619 &update_status.raw, 1620 1) == DC_OK) { 1621 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1622 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1623 result = true; 1624 break; 1625 } 1626 } else { 1627 union dpcd_rev dpcdRev = {0}; 1628 1629 if (core_link_read_dpcd( 1630 link, 1631 DP_DPCD_REV, 1632 &dpcdRev.raw, 1633 1) != DC_OK) { 1634 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1635 "of sink while polling payload table " 1636 "updated status bit."); 1637 break; 1638 } 1639 } 1640 retries++; 1641 fsleep(5000); 1642 } 1643 1644 if (!result && retries == max_retries) { 1645 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1646 "continue on. Something is wrong with the branch."); 1647 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1648 } 1649 1650 return result; 1651 } 1652 1653 /* 1654 * Payload allocation/deallocation for SST introduced in DP2.0 1655 */ 1656 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1657 bool allocate) 1658 { 1659 struct dc_stream_state *stream = pipe_ctx->stream; 1660 struct dc_link *link = stream->link; 1661 struct link_mst_stream_allocation_table proposed_table = {0}; 1662 struct fixed31_32 avg_time_slots_per_mtp; 1663 const struct dc_link_settings empty_link_settings = {0}; 1664 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1665 DC_LOGGER_INIT(link->ctx->logger); 1666 1667 /* slot X.Y for SST payload deallocate */ 1668 if (!allocate) { 1669 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1670 1671 log_vcp_x_y(link, avg_time_slots_per_mtp); 1672 1673 if (link_hwss->ext.set_throttled_vcp_size) 1674 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1675 avg_time_slots_per_mtp); 1676 if (link_hwss->ext.set_hblank_min_symbol_width) 1677 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1678 &empty_link_settings, 1679 avg_time_slots_per_mtp); 1680 } 1681 1682 /* calculate VC payload and update branch with new payload allocation table*/ 1683 if (!write_128b_132b_sst_payload_allocation_table( 1684 stream, 1685 link, 1686 &proposed_table, 1687 allocate)) { 1688 DC_LOG_ERROR("SST Update Payload: Failed to update " 1689 "allocation table for " 1690 "pipe idx: %d\n", 1691 pipe_ctx->pipe_idx); 1692 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1693 } 1694 1695 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1696 1697 ASSERT(proposed_table.stream_count == 1); 1698 1699 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1700 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1701 "vcp_id: %d " 1702 "slot_count: %d\n", 1703 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1704 proposed_table.stream_allocations[0].vcp_id, 1705 proposed_table.stream_allocations[0].slot_count); 1706 1707 /* program DP source TX for payload */ 1708 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1709 &proposed_table); 1710 1711 /* poll for ACT handled */ 1712 if (!poll_for_allocation_change_trigger(link)) { 1713 // Failures will result in blackscreen and errors logged 1714 BREAK_TO_DEBUGGER(); 1715 } 1716 1717 /* slot X.Y for SST payload allocate */ 1718 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1719 DP_128b_132b_ENCODING) { 1720 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1721 1722 log_vcp_x_y(link, avg_time_slots_per_mtp); 1723 1724 if (link_hwss->ext.set_throttled_vcp_size) 1725 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1726 avg_time_slots_per_mtp); 1727 if (link_hwss->ext.set_hblank_min_symbol_width) 1728 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1729 &link->cur_link_settings, 1730 avg_time_slots_per_mtp); 1731 } 1732 1733 /* Always return DC_OK. 1734 * If part of sequence fails, log failure(s) and show blackscreen 1735 */ 1736 return DC_OK; 1737 } 1738 1739 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1740 { 1741 struct dc_stream_state *stream = pipe_ctx->stream; 1742 struct dc_link *link = stream->link; 1743 struct fixed31_32 avg_time_slots_per_mtp; 1744 struct fixed31_32 pbn; 1745 struct fixed31_32 pbn_per_slot; 1746 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1747 uint8_t i; 1748 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1749 DC_LOGGER_INIT(link->ctx->logger); 1750 1751 /* decrease throttled vcp size */ 1752 pbn_per_slot = get_pbn_per_slot(stream); 1753 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1754 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1755 1756 if (link_hwss->ext.set_throttled_vcp_size) 1757 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1758 if (link_hwss->ext.set_hblank_min_symbol_width) 1759 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1760 &link->cur_link_settings, 1761 avg_time_slots_per_mtp); 1762 1763 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1764 dm_helpers_dp_mst_send_payload_allocation( 1765 stream->ctx, 1766 stream); 1767 1768 /* notify immediate branch device table update */ 1769 if (dm_helpers_dp_mst_write_payload_allocation_table( 1770 stream->ctx, 1771 stream, 1772 &proposed_table, 1773 true)) { 1774 /* update mst stream allocation table software state */ 1775 update_mst_stream_alloc_table( 1776 link, 1777 pipe_ctx->stream_res.stream_enc, 1778 pipe_ctx->stream_res.hpo_dp_stream_enc, 1779 &proposed_table); 1780 } else { 1781 DC_LOG_WARNING("Failed to update" 1782 "MST allocation table for" 1783 "pipe idx:%d\n", 1784 pipe_ctx->pipe_idx); 1785 } 1786 1787 DC_LOG_MST("%s " 1788 "stream_count: %d: \n ", 1789 __func__, 1790 link->mst_stream_alloc_table.stream_count); 1791 1792 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1793 DC_LOG_MST("stream_enc[%d]: %p " 1794 "stream[%d].hpo_dp_stream_enc: %p " 1795 "stream[%d].vcp_id: %d " 1796 "stream[%d].slot_count: %d\n", 1797 i, 1798 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1799 i, 1800 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1801 i, 1802 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1803 i, 1804 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1805 } 1806 1807 ASSERT(proposed_table.stream_count > 0); 1808 1809 /* update mst stream allocation table hardware state */ 1810 if (link_hwss->ext.update_stream_allocation_table == NULL || 1811 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1812 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1813 return DC_ERROR_UNEXPECTED; 1814 } 1815 1816 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1817 &link->mst_stream_alloc_table); 1818 1819 /* poll for immediate branch device ACT handled */ 1820 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1821 stream->ctx, 1822 stream); 1823 1824 return DC_OK; 1825 } 1826 1827 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1828 { 1829 struct dc_stream_state *stream = pipe_ctx->stream; 1830 struct dc_link *link = stream->link; 1831 struct fixed31_32 avg_time_slots_per_mtp; 1832 struct fixed31_32 pbn; 1833 struct fixed31_32 pbn_per_slot; 1834 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1835 uint8_t i; 1836 enum act_return_status ret; 1837 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1838 DC_LOGGER_INIT(link->ctx->logger); 1839 1840 /* notify immediate branch device table update */ 1841 if (dm_helpers_dp_mst_write_payload_allocation_table( 1842 stream->ctx, 1843 stream, 1844 &proposed_table, 1845 true)) { 1846 /* update mst stream allocation table software state */ 1847 update_mst_stream_alloc_table( 1848 link, 1849 pipe_ctx->stream_res.stream_enc, 1850 pipe_ctx->stream_res.hpo_dp_stream_enc, 1851 &proposed_table); 1852 } 1853 1854 DC_LOG_MST("%s " 1855 "stream_count: %d: \n ", 1856 __func__, 1857 link->mst_stream_alloc_table.stream_count); 1858 1859 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1860 DC_LOG_MST("stream_enc[%d]: %p " 1861 "stream[%d].hpo_dp_stream_enc: %p " 1862 "stream[%d].vcp_id: %d " 1863 "stream[%d].slot_count: %d\n", 1864 i, 1865 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1866 i, 1867 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1868 i, 1869 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1870 i, 1871 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1872 } 1873 1874 ASSERT(proposed_table.stream_count > 0); 1875 1876 /* update mst stream allocation table hardware state */ 1877 if (link_hwss->ext.update_stream_allocation_table == NULL || 1878 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1879 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1880 return DC_ERROR_UNEXPECTED; 1881 } 1882 1883 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1884 &link->mst_stream_alloc_table); 1885 1886 /* poll for immediate branch device ACT handled */ 1887 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1888 stream->ctx, 1889 stream); 1890 1891 if (ret != ACT_LINK_LOST) { 1892 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1893 dm_helpers_dp_mst_send_payload_allocation( 1894 stream->ctx, 1895 stream); 1896 } 1897 1898 /* increase throttled vcp size */ 1899 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1900 pbn_per_slot = get_pbn_per_slot(stream); 1901 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1902 1903 if (link_hwss->ext.set_throttled_vcp_size) 1904 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1905 if (link_hwss->ext.set_hblank_min_symbol_width) 1906 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1907 &link->cur_link_settings, 1908 avg_time_slots_per_mtp); 1909 1910 return DC_OK; 1911 } 1912 1913 static void disable_link_dp(struct dc_link *link, 1914 const struct link_resource *link_res, 1915 enum signal_type signal) 1916 { 1917 struct dc_link_settings link_settings = link->cur_link_settings; 1918 1919 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1920 link->mst_stream_alloc_table.stream_count > 0) 1921 /* disable MST link only when last vc payload is deallocated */ 1922 return; 1923 1924 dp_disable_link_phy(link, link_res, signal); 1925 1926 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1927 if (!link->skip_implict_edp_power_control) 1928 link->dc->hwss.edp_power_control(link, false); 1929 } 1930 1931 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1932 /* set the sink to SST mode after disabling the link */ 1933 enable_mst_on_sink(link, false); 1934 1935 if (link_dp_get_encoding_format(&link_settings) == 1936 DP_8b_10b_ENCODING) { 1937 dp_set_fec_enable(link, link_res, false); 1938 dp_set_fec_ready(link, link_res, false); 1939 } 1940 } 1941 1942 static void disable_link(struct dc_link *link, 1943 const struct link_resource *link_res, 1944 enum signal_type signal) 1945 { 1946 if (dc_is_dp_signal(signal)) { 1947 disable_link_dp(link, link_res, signal); 1948 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1949 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1950 } else { 1951 link->dc->hwss.disable_link_output(link, link_res, signal); 1952 } 1953 1954 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1955 /* MST disable link only when no stream use the link */ 1956 if (link->mst_stream_alloc_table.stream_count <= 0) 1957 link->link_status.link_active = false; 1958 } else { 1959 link->link_status.link_active = false; 1960 } 1961 } 1962 1963 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1964 { 1965 struct dc_stream_state *stream = pipe_ctx->stream; 1966 struct dc_link *link = stream->link; 1967 enum dc_color_depth display_color_depth; 1968 enum engine_id eng_id; 1969 struct ext_hdmi_settings settings = {0}; 1970 bool is_over_340mhz = false; 1971 bool is_vga_mode = (stream->timing.h_addressable == 640) 1972 && (stream->timing.v_addressable == 480); 1973 struct dc *dc = pipe_ctx->stream->ctx->dc; 1974 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1975 1976 if (stream->phy_pix_clk == 0) 1977 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1978 if (stream->phy_pix_clk > 340000) 1979 is_over_340mhz = true; 1980 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1981 ASSERT(false); 1982 return; 1983 } 1984 1985 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1986 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1987 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1988 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1989 /* DP159, Retimer settings */ 1990 eng_id = pipe_ctx->stream_res.stream_enc->id; 1991 1992 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1993 write_i2c_retimer_setting(pipe_ctx, 1994 is_vga_mode, is_over_340mhz, &settings); 1995 } else { 1996 write_i2c_default_retimer_setting(pipe_ctx, 1997 is_vga_mode, is_over_340mhz); 1998 } 1999 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2000 /* PI3EQX1204, Redriver settings */ 2001 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 2002 } 2003 } 2004 2005 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2006 write_scdc_data( 2007 stream->link->ddc, 2008 stream->phy_pix_clk, 2009 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2010 2011 memset(&stream->link->cur_link_settings, 0, 2012 sizeof(struct dc_link_settings)); 2013 2014 display_color_depth = stream->timing.display_color_depth; 2015 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2016 display_color_depth = COLOR_DEPTH_888; 2017 2018 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 2019 * character clock in case that beyond 340MHz. 2020 */ 2021 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 2022 link_hwss->setup_stream_encoder(pipe_ctx); 2023 2024 dc->hwss.enable_tmds_link_output( 2025 link, 2026 &pipe_ctx->link_res, 2027 pipe_ctx->stream->signal, 2028 pipe_ctx->clock_source->id, 2029 display_color_depth, 2030 stream->phy_pix_clk); 2031 2032 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2033 read_scdc_data(link->ddc); 2034 } 2035 2036 static enum dc_status enable_link_dp(struct dc_state *state, 2037 struct pipe_ctx *pipe_ctx) 2038 { 2039 struct dc_stream_state *stream = pipe_ctx->stream; 2040 enum dc_status status; 2041 bool skip_video_pattern; 2042 struct dc_link *link = stream->link; 2043 const struct dc_link_settings *link_settings = 2044 &pipe_ctx->link_config.dp_link_settings; 2045 bool fec_enable; 2046 int i; 2047 bool apply_seamless_boot_optimization = false; 2048 uint32_t bl_oled_enable_delay = 50; // in ms 2049 uint32_t post_oui_delay = 30; // 30ms 2050 /* Reduce link bandwidth between failed link training attempts. */ 2051 bool do_fallback = false; 2052 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2053 2054 // Increase retry count if attempting DP1.x on FIXED_VS link 2055 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2056 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2057 lt_attempts = 10; 2058 2059 // check for seamless boot 2060 for (i = 0; i < state->stream_count; i++) { 2061 if (state->streams[i]->apply_seamless_boot_optimization) { 2062 apply_seamless_boot_optimization = true; 2063 break; 2064 } 2065 } 2066 2067 /* Train with fallback when enabling DPIA link. Conventional links are 2068 * trained with fallback during sink detection. 2069 */ 2070 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2071 !link->dc->config.enable_dpia_pre_training) 2072 do_fallback = true; 2073 2074 /* 2075 * Temporary w/a to get DP2.0 link rates to work with SST. 2076 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2077 */ 2078 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2079 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2080 link->dc->debug.set_mst_en_for_sst) { 2081 enable_mst_on_sink(link, true); 2082 } 2083 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2084 /*in case it is not on*/ 2085 if (!link->dc->config.edp_no_power_sequencing) 2086 link->dc->hwss.edp_power_control(link, true); 2087 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2088 } 2089 2090 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2091 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2092 } else { 2093 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2094 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2095 if (state->clk_mgr && !apply_seamless_boot_optimization) 2096 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2097 state, false); 2098 } 2099 2100 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2101 dpcd_set_source_specific_data(link); 2102 if (link->dpcd_sink_ext_caps.raw != 0) { 2103 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2104 msleep(post_oui_delay); 2105 } 2106 2107 // similarly, mode switch can cause loss of cable ID 2108 dpcd_write_cable_id_to_dprx(link); 2109 2110 skip_video_pattern = true; 2111 2112 if (link_settings->link_rate == LINK_RATE_LOW) 2113 skip_video_pattern = false; 2114 2115 if (stream->sink_patches.oled_optimize_display_on) 2116 set_default_brightness_aux(link); 2117 2118 if (perform_link_training_with_retries(link_settings, 2119 skip_video_pattern, 2120 lt_attempts, 2121 pipe_ctx, 2122 pipe_ctx->stream->signal, 2123 do_fallback)) { 2124 status = DC_OK; 2125 } else { 2126 status = DC_FAIL_DP_LINK_TRAINING; 2127 } 2128 2129 if (link->preferred_training_settings.fec_enable) 2130 fec_enable = *link->preferred_training_settings.fec_enable; 2131 else 2132 fec_enable = true; 2133 2134 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2135 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 2136 2137 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2138 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2139 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2140 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2141 if (!stream->sink_patches.oled_optimize_display_on) { 2142 set_default_brightness_aux(link); 2143 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2144 msleep(bl_oled_enable_delay); 2145 edp_backlight_enable_aux(link, true); 2146 } else { 2147 edp_backlight_enable_aux(link, true); 2148 } 2149 } 2150 2151 return status; 2152 } 2153 2154 static enum dc_status enable_link_edp( 2155 struct dc_state *state, 2156 struct pipe_ctx *pipe_ctx) 2157 { 2158 return enable_link_dp(state, pipe_ctx); 2159 } 2160 2161 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2162 { 2163 struct dc_stream_state *stream = pipe_ctx->stream; 2164 struct dc_link *link = stream->link; 2165 struct dc *dc = stream->ctx->dc; 2166 2167 if (stream->phy_pix_clk == 0) 2168 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2169 2170 memset(&stream->link->cur_link_settings, 0, 2171 sizeof(struct dc_link_settings)); 2172 dc->hwss.enable_lvds_link_output( 2173 link, 2174 &pipe_ctx->link_res, 2175 pipe_ctx->clock_source->id, 2176 stream->phy_pix_clk); 2177 2178 } 2179 2180 static enum dc_status enable_link_dp_mst( 2181 struct dc_state *state, 2182 struct pipe_ctx *pipe_ctx) 2183 { 2184 struct dc_link *link = pipe_ctx->stream->link; 2185 unsigned char mstm_cntl = 0; 2186 2187 /* sink signal type after MST branch is MST. Multiple MST sinks 2188 * share one link. Link DP PHY is enable or training only once. 2189 */ 2190 if (link->link_status.link_active) 2191 return DC_OK; 2192 2193 /* clear payload table */ 2194 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2195 if (mstm_cntl & DP_MST_EN) 2196 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2197 2198 /* to make sure the pending down rep can be processed 2199 * before enabling the link 2200 */ 2201 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2202 2203 /* set the sink to MST mode before enabling the link */ 2204 enable_mst_on_sink(link, true); 2205 2206 return enable_link_dp(state, pipe_ctx); 2207 } 2208 2209 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2210 { 2211 struct dc_link *link = pipe_ctx->stream->link; 2212 2213 link->dc->hwss.enable_dp_link_output(link, 2214 &pipe_ctx->link_res, 2215 SIGNAL_TYPE_DISPLAY_PORT, 2216 pipe_ctx->clock_source->id, 2217 &pipe_ctx->link_config.dp_link_settings); 2218 return DC_OK; 2219 } 2220 2221 static enum dc_status enable_link( 2222 struct dc_state *state, 2223 struct pipe_ctx *pipe_ctx) 2224 { 2225 enum dc_status status = DC_ERROR_UNEXPECTED; 2226 struct dc_stream_state *stream = pipe_ctx->stream; 2227 struct dc_link *link = stream->link; 2228 2229 /* There's some scenarios where driver is unloaded with display 2230 * still enabled. When driver is reloaded, it may cause a display 2231 * to not light up if there is a mismatch between old and new 2232 * link settings. Need to call disable first before enabling at 2233 * new link settings. 2234 */ 2235 if (link->link_status.link_active) 2236 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2237 2238 switch (pipe_ctx->stream->signal) { 2239 case SIGNAL_TYPE_DISPLAY_PORT: 2240 status = enable_link_dp(state, pipe_ctx); 2241 break; 2242 case SIGNAL_TYPE_EDP: 2243 status = enable_link_edp(state, pipe_ctx); 2244 break; 2245 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2246 status = enable_link_dp_mst(state, pipe_ctx); 2247 msleep(200); 2248 break; 2249 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2250 case SIGNAL_TYPE_DVI_DUAL_LINK: 2251 case SIGNAL_TYPE_HDMI_TYPE_A: 2252 enable_link_hdmi(pipe_ctx); 2253 status = DC_OK; 2254 break; 2255 case SIGNAL_TYPE_LVDS: 2256 enable_link_lvds(pipe_ctx); 2257 status = DC_OK; 2258 break; 2259 case SIGNAL_TYPE_VIRTUAL: 2260 status = enable_link_virtual(pipe_ctx); 2261 break; 2262 default: 2263 break; 2264 } 2265 2266 if (status == DC_OK) { 2267 pipe_ctx->stream->link->link_status.link_active = true; 2268 } 2269 2270 return status; 2271 } 2272 2273 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2274 { 2275 struct dc_link *link = stream->sink->link; 2276 int req_bw = bw; 2277 2278 DC_LOGGER_INIT(link->ctx->logger); 2279 2280 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2281 return false; 2282 2283 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2284 int sink_index = 0; 2285 int i = 0; 2286 2287 for (i = 0; i < link->sink_count; i++) { 2288 if (link->remote_sinks[i] == NULL) 2289 continue; 2290 2291 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2292 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2293 else 2294 sink_index = i; 2295 } 2296 2297 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2298 } 2299 2300 link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); 2301 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2302 2303 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2304 2305 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2306 int i = 0; 2307 2308 for (i = 0; i < link->sink_count; i++) { 2309 if (link->remote_sinks[i] == NULL) 2310 continue; 2311 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2312 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2313 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2314 } 2315 } 2316 2317 return true; 2318 } 2319 2320 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2321 { 2322 bool ret; 2323 2324 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2325 dc_link_get_highest_encoding_format(stream->sink->link)); 2326 2327 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2328 2329 return ret; 2330 } 2331 2332 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2333 { 2334 bool ret; 2335 2336 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2337 2338 return ret; 2339 } 2340 2341 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2342 { 2343 struct dc *dc = pipe_ctx->stream->ctx->dc; 2344 struct dc_stream_state *stream = pipe_ctx->stream; 2345 struct dc_link *link = stream->sink->link; 2346 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2347 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2348 2349 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2350 2351 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2352 2353 if (dp_is_128b_132b_signal(pipe_ctx)) 2354 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2355 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2356 return; 2357 2358 if (pipe_ctx->stream->sink) { 2359 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2360 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2361 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2362 pipe_ctx->stream->sink->edid_caps.display_name, 2363 pipe_ctx->stream->signal); 2364 } 2365 } 2366 2367 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2368 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2369 set_avmute(pipe_ctx, true); 2370 } 2371 2372 dc->hwss.disable_audio_stream(pipe_ctx); 2373 2374 update_psp_stream_config(pipe_ctx, true); 2375 dc->hwss.blank_stream(pipe_ctx); 2376 2377 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2378 deallocate_usb4_bandwidth(pipe_ctx->stream); 2379 2380 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2381 deallocate_mst_payload(pipe_ctx); 2382 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2383 dp_is_128b_132b_signal(pipe_ctx)) 2384 update_sst_payload(pipe_ctx, false); 2385 2386 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2387 struct ext_hdmi_settings settings = {0}; 2388 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2389 2390 unsigned short masked_chip_caps = link->chip_caps & 2391 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2392 //Need to inform that sink is going to use legacy HDMI mode. 2393 write_scdc_data( 2394 link->ddc, 2395 165000,//vbios only handles 165Mhz. 2396 false); 2397 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2398 /* DP159, Retimer settings */ 2399 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2400 write_i2c_retimer_setting(pipe_ctx, 2401 false, false, &settings); 2402 else 2403 write_i2c_default_retimer_setting(pipe_ctx, 2404 false, false); 2405 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2406 /* PI3EQX1204, Redriver settings */ 2407 write_i2c_redriver_setting(pipe_ctx, false); 2408 } 2409 } 2410 2411 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2412 !dp_is_128b_132b_signal(pipe_ctx)) { 2413 2414 /* In DP1.x SST mode, our encoder will go to TPS1 2415 * when link is on but stream is off. 2416 * Disabling link before stream will avoid exposing TPS1 pattern 2417 * during the disable sequence as it will confuse some receivers 2418 * state machine. 2419 * In DP2 or MST mode, our encoder will stay video active 2420 */ 2421 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2422 dc->hwss.disable_stream(pipe_ctx); 2423 } else { 2424 dc->hwss.disable_stream(pipe_ctx); 2425 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2426 } 2427 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2428 2429 if (pipe_ctx->stream->timing.flags.DSC) { 2430 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2431 link_set_dsc_enable(pipe_ctx, false); 2432 } 2433 if (dp_is_128b_132b_signal(pipe_ctx)) { 2434 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2435 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2436 } 2437 2438 if (vpg && vpg->funcs->vpg_powerdown) 2439 vpg->funcs->vpg_powerdown(vpg); 2440 2441 /* for psp not exist case */ 2442 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2443 /* reset internal save state to default since eDP is off */ 2444 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2445 /* since current psp not loaded, we need to reset it to default */ 2446 link->panel_mode = panel_mode; 2447 } 2448 } 2449 2450 void link_set_dpms_on( 2451 struct dc_state *state, 2452 struct pipe_ctx *pipe_ctx) 2453 { 2454 struct dc *dc = pipe_ctx->stream->ctx->dc; 2455 struct dc_stream_state *stream = pipe_ctx->stream; 2456 struct dc_link *link = stream->sink->link; 2457 enum dc_status status; 2458 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 2459 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2460 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2461 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2462 bool apply_edp_fast_boot_optimization = 2463 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2464 2465 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2466 2467 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2468 2469 if (dp_is_128b_132b_signal(pipe_ctx)) 2470 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2471 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2472 return; 2473 2474 if (pipe_ctx->stream->sink) { 2475 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2476 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2477 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2478 pipe_ctx->stream->sink->edid_caps.display_name, 2479 pipe_ctx->stream->signal); 2480 } 2481 } 2482 2483 if (!dc->config.unify_link_enc_assignment) 2484 link_enc = link_enc_cfg_get_link_enc(link); 2485 ASSERT(link_enc); 2486 2487 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2488 && !dp_is_128b_132b_signal(pipe_ctx)) { 2489 if (link_enc) 2490 link_enc->funcs->setup( 2491 link_enc, 2492 pipe_ctx->stream->signal); 2493 } 2494 2495 pipe_ctx->stream->link->link_state_valid = true; 2496 2497 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2498 if (dp_is_128b_132b_signal(pipe_ctx)) 2499 otg_out_dest = OUT_MUX_HPO_DP; 2500 else 2501 otg_out_dest = OUT_MUX_DIO; 2502 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2503 } 2504 2505 link_hwss->setup_stream_attribute(pipe_ctx); 2506 2507 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2508 2509 // Enable VPG before building infoframe 2510 if (vpg && vpg->funcs->vpg_poweron) 2511 vpg->funcs->vpg_poweron(vpg); 2512 2513 resource_build_info_frame(pipe_ctx); 2514 dc->hwss.update_info_frame(pipe_ctx); 2515 2516 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2517 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2518 2519 /* Do not touch link on seamless boot optimization. */ 2520 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2521 pipe_ctx->stream->dpms_off = false; 2522 2523 /* Still enable stream features & audio on seamless boot for DP external displays */ 2524 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2525 enable_stream_features(pipe_ctx); 2526 dc->hwss.enable_audio_stream(pipe_ctx); 2527 } 2528 2529 update_psp_stream_config(pipe_ctx, false); 2530 return; 2531 } 2532 2533 /* eDP lit up by bios already, no need to enable again. */ 2534 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2535 apply_edp_fast_boot_optimization && 2536 !pipe_ctx->stream->timing.flags.DSC && 2537 !pipe_ctx->next_odm_pipe) { 2538 pipe_ctx->stream->dpms_off = false; 2539 update_psp_stream_config(pipe_ctx, false); 2540 2541 if (link->is_dds) { 2542 uint32_t post_oui_delay = 30; // 30ms 2543 2544 dpcd_set_source_specific_data(link); 2545 msleep(post_oui_delay); 2546 } 2547 2548 return; 2549 } 2550 2551 if (pipe_ctx->stream->dpms_off) 2552 return; 2553 2554 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2555 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2556 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2557 */ 2558 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2559 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2560 return; 2561 } 2562 2563 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2564 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2565 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2566 * will be automatically set at a later time when the video is enabled 2567 * (DP_VID_STREAM_EN = 1). 2568 */ 2569 if (pipe_ctx->stream->timing.flags.DSC) { 2570 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2571 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2572 link_set_dsc_enable(pipe_ctx, true); 2573 } 2574 2575 status = enable_link(state, pipe_ctx); 2576 2577 if (status != DC_OK) { 2578 DC_LOG_WARNING("enabling link %u failed: %d\n", 2579 pipe_ctx->stream->link->link_index, 2580 status); 2581 2582 /* Abort stream enable *unless* the failure was due to 2583 * DP link training - some DP monitors will recover and 2584 * show the stream anyway. But MST displays can't proceed 2585 * without link training. 2586 */ 2587 if (status != DC_FAIL_DP_LINK_TRAINING || 2588 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2589 if (false == stream->link->link_status.link_active) 2590 disable_link(stream->link, &pipe_ctx->link_res, 2591 pipe_ctx->stream->signal); 2592 BREAK_TO_DEBUGGER(); 2593 return; 2594 } 2595 } 2596 2597 /* turn off otg test pattern if enable */ 2598 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2599 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2600 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2601 COLOR_DEPTH_UNDEFINED); 2602 2603 /* This second call is needed to reconfigure the DIG 2604 * as a workaround for the incorrect value being applied 2605 * from transmitter control. 2606 */ 2607 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2608 dp_is_128b_132b_signal(pipe_ctx))) { 2609 2610 if (link_enc) 2611 link_enc->funcs->setup( 2612 link_enc, 2613 pipe_ctx->stream->signal); 2614 2615 } 2616 2617 dc->hwss.enable_stream(pipe_ctx); 2618 2619 /* Set DPS PPS SDP (AKA "info frames") */ 2620 if (pipe_ctx->stream->timing.flags.DSC) { 2621 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2622 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2623 dp_set_dsc_on_rx(pipe_ctx, true); 2624 link_set_dsc_pps_packet(pipe_ctx, true, true); 2625 } 2626 } 2627 2628 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2629 dp_set_hblank_reduction_on_rx(pipe_ctx); 2630 2631 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2632 allocate_usb4_bandwidth(pipe_ctx->stream); 2633 2634 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2635 allocate_mst_payload(pipe_ctx); 2636 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2637 dp_is_128b_132b_signal(pipe_ctx)) 2638 update_sst_payload(pipe_ctx, true); 2639 2640 /* Corruption was observed on systems with display mux when stream gets 2641 * enabled after the mux switch. Having a small delay between link 2642 * training and stream unblank resolves the corruption issue. 2643 * This is workaround. 2644 */ 2645 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2646 link->is_display_mux_present) 2647 msleep(20); 2648 2649 dc->hwss.unblank_stream(pipe_ctx, 2650 &pipe_ctx->stream->link->cur_link_settings); 2651 2652 if (stream->sink_patches.delay_ignore_msa > 0) 2653 msleep(stream->sink_patches.delay_ignore_msa); 2654 2655 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2656 enable_stream_features(pipe_ctx); 2657 update_psp_stream_config(pipe_ctx, false); 2658 2659 dc->hwss.enable_audio_stream(pipe_ctx); 2660 2661 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2662 set_avmute(pipe_ctx, false); 2663 } 2664 } 2665