1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 144 dpcd_write_rx_power_ctrl(link, false); 145 } 146 } 147 148 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 149 { 150 struct pipe_ctx *pipes[MAX_PIPES]; 151 struct dc_state *state = link->dc->current_state; 152 uint8_t count; 153 int i; 154 struct dc_stream_update stream_update; 155 bool dpms_off = true; 156 struct link_resource link_res = {0}; 157 158 memset(&stream_update, 0, sizeof(stream_update)); 159 stream_update.dpms_off = &dpms_off; 160 161 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 162 163 for (i = 0; i < count; i++) { 164 stream_update.stream = pipes[i]->stream; 165 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 166 pipes[i]->stream, &stream_update, 167 state); 168 } 169 170 /* link can be also enabled by vbios. In this case it is not recorded 171 * in pipe_ctx. Disable link phy here to make sure it is completely off 172 */ 173 dp_disable_link_phy(link, &link_res, link->connector_signal); 174 } 175 176 void link_resume(struct dc_link *link) 177 { 178 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 179 program_hpd_filter(link); 180 } 181 182 /* This function returns true if the pipe is used to feed video signal directly 183 * to the link. 184 */ 185 static bool is_master_pipe_for_link(const struct dc_link *link, 186 const struct pipe_ctx *pipe) 187 { 188 return resource_is_pipe_type(pipe, OTG_MASTER) && 189 pipe->stream->link == link; 190 } 191 192 /* 193 * This function finds all master pipes feeding to a given link with dpms set to 194 * on in given dc state. 195 */ 196 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 197 struct dc_state *state, 198 uint8_t *count, 199 struct pipe_ctx *pipes[MAX_PIPES]) 200 { 201 int i; 202 struct pipe_ctx *pipe = NULL; 203 204 *count = 0; 205 for (i = 0; i < MAX_PIPES; i++) { 206 pipe = &state->res_ctx.pipe_ctx[i]; 207 208 if (is_master_pipe_for_link(link, pipe) && 209 pipe->stream->dpms_off == false) { 210 pipes[(*count)++] = pipe; 211 } 212 } 213 } 214 215 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 216 enum engine_id eng_id, 217 struct ext_hdmi_settings *settings) 218 { 219 bool result = false; 220 int i = 0; 221 struct integrated_info *integrated_info = 222 pipe_ctx->stream->ctx->dc_bios->integrated_info; 223 224 if (integrated_info == NULL) 225 return false; 226 227 /* 228 * Get retimer settings from sbios for passing SI eye test for DCE11 229 * The setting values are varied based on board revision and port id 230 * Therefore the setting values of each ports is passed by sbios. 231 */ 232 233 // Check if current bios contains ext Hdmi settings 234 if (integrated_info->gpu_cap_info & 0x20) { 235 switch (eng_id) { 236 case ENGINE_ID_DIGA: 237 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 238 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 240 memmove(settings->reg_settings, 241 integrated_info->dp0_ext_hdmi_reg_settings, 242 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 243 memmove(settings->reg_settings_6g, 244 integrated_info->dp0_ext_hdmi_6g_reg_settings, 245 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 246 result = true; 247 break; 248 case ENGINE_ID_DIGB: 249 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 250 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 252 memmove(settings->reg_settings, 253 integrated_info->dp1_ext_hdmi_reg_settings, 254 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 255 memmove(settings->reg_settings_6g, 256 integrated_info->dp1_ext_hdmi_6g_reg_settings, 257 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 258 result = true; 259 break; 260 case ENGINE_ID_DIGC: 261 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 262 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 264 memmove(settings->reg_settings, 265 integrated_info->dp2_ext_hdmi_reg_settings, 266 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 267 memmove(settings->reg_settings_6g, 268 integrated_info->dp2_ext_hdmi_6g_reg_settings, 269 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 270 result = true; 271 break; 272 case ENGINE_ID_DIGD: 273 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 274 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 276 memmove(settings->reg_settings, 277 integrated_info->dp3_ext_hdmi_reg_settings, 278 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 279 memmove(settings->reg_settings_6g, 280 integrated_info->dp3_ext_hdmi_6g_reg_settings, 281 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 282 result = true; 283 break; 284 default: 285 break; 286 } 287 288 if (result == true) { 289 // Validate settings from bios integrated info table 290 if (settings->slv_addr == 0) 291 return false; 292 if (settings->reg_num > 9) 293 return false; 294 if (settings->reg_num_6g > 3) 295 return false; 296 297 for (i = 0; i < settings->reg_num; i++) { 298 if (settings->reg_settings[i].i2c_reg_index > 0x20) 299 return false; 300 } 301 302 for (i = 0; i < settings->reg_num_6g; i++) { 303 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 304 return false; 305 } 306 } 307 } 308 309 return result; 310 } 311 312 static bool write_i2c(struct pipe_ctx *pipe_ctx, 313 uint8_t address, uint8_t *buffer, uint32_t length) 314 { 315 struct i2c_command cmd = {0}; 316 struct i2c_payload payload = {0}; 317 318 memset(&payload, 0, sizeof(payload)); 319 memset(&cmd, 0, sizeof(cmd)); 320 321 cmd.number_of_payloads = 1; 322 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 323 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 324 325 payload.address = address; 326 payload.data = buffer; 327 payload.length = length; 328 payload.write = true; 329 cmd.payloads = &payload; 330 331 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 332 pipe_ctx->stream->link, &cmd)) 333 return true; 334 335 return false; 336 } 337 338 static void write_i2c_retimer_setting( 339 struct pipe_ctx *pipe_ctx, 340 bool is_vga_mode, 341 bool is_over_340mhz, 342 struct ext_hdmi_settings *settings) 343 { 344 uint8_t slave_address = (settings->slv_addr >> 1); 345 uint8_t buffer[2]; 346 const uint8_t apply_rx_tx_change = 0x4; 347 uint8_t offset = 0xA; 348 uint8_t value = 0; 349 int i = 0; 350 bool i2c_success = false; 351 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 352 353 memset(&buffer, 0, sizeof(buffer)); 354 355 /* Start Ext-Hdmi programming*/ 356 357 for (i = 0; i < settings->reg_num; i++) { 358 /* Apply 3G settings */ 359 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 360 361 buffer[0] = settings->reg_settings[i].i2c_reg_index; 362 buffer[1] = settings->reg_settings[i].i2c_reg_val; 363 i2c_success = write_i2c(pipe_ctx, slave_address, 364 buffer, sizeof(buffer)); 365 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 366 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 367 slave_address, buffer[0], buffer[1], i2c_success?1:0); 368 369 if (!i2c_success) 370 goto i2c_write_fail; 371 372 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 373 * needs to be set to 1 on every 0xA-0xC write. 374 */ 375 if (settings->reg_settings[i].i2c_reg_index == 0xA || 376 settings->reg_settings[i].i2c_reg_index == 0xB || 377 settings->reg_settings[i].i2c_reg_index == 0xC) { 378 379 /* Query current value from offset 0xA */ 380 if (settings->reg_settings[i].i2c_reg_index == 0xA) 381 value = settings->reg_settings[i].i2c_reg_val; 382 else { 383 i2c_success = 384 link_query_ddc_data( 385 pipe_ctx->stream->link->ddc, 386 slave_address, &offset, 1, &value, 1); 387 if (!i2c_success) 388 goto i2c_write_fail; 389 } 390 391 buffer[0] = offset; 392 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 393 buffer[1] = value | apply_rx_tx_change; 394 i2c_success = write_i2c(pipe_ctx, slave_address, 395 buffer, sizeof(buffer)); 396 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 397 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 398 slave_address, buffer[0], buffer[1], i2c_success?1:0); 399 if (!i2c_success) 400 goto i2c_write_fail; 401 } 402 } 403 } 404 405 /* Apply 3G settings */ 406 if (is_over_340mhz) { 407 for (i = 0; i < settings->reg_num_6g; i++) { 408 /* Apply 3G settings */ 409 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 410 411 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 412 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 413 i2c_success = write_i2c(pipe_ctx, slave_address, 414 buffer, sizeof(buffer)); 415 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 416 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 417 slave_address, buffer[0], buffer[1], i2c_success?1:0); 418 419 if (!i2c_success) 420 goto i2c_write_fail; 421 422 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 423 * needs to be set to 1 on every 0xA-0xC write. 424 */ 425 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 427 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 428 429 /* Query current value from offset 0xA */ 430 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 431 value = settings->reg_settings_6g[i].i2c_reg_val; 432 else { 433 i2c_success = 434 link_query_ddc_data( 435 pipe_ctx->stream->link->ddc, 436 slave_address, &offset, 1, &value, 1); 437 if (!i2c_success) 438 goto i2c_write_fail; 439 } 440 441 buffer[0] = offset; 442 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 443 buffer[1] = value | apply_rx_tx_change; 444 i2c_success = write_i2c(pipe_ctx, slave_address, 445 buffer, sizeof(buffer)); 446 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 447 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 448 slave_address, buffer[0], buffer[1], i2c_success?1:0); 449 if (!i2c_success) 450 goto i2c_write_fail; 451 } 452 } 453 } 454 } 455 456 if (is_vga_mode) { 457 /* Program additional settings if using 640x480 resolution */ 458 459 /* Write offset 0xFF to 0x01 */ 460 buffer[0] = 0xff; 461 buffer[1] = 0x01; 462 i2c_success = write_i2c(pipe_ctx, slave_address, 463 buffer, sizeof(buffer)); 464 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 465 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 466 slave_address, buffer[0], buffer[1], i2c_success?1:0); 467 if (!i2c_success) 468 goto i2c_write_fail; 469 470 /* Write offset 0x00 to 0x23 */ 471 buffer[0] = 0x00; 472 buffer[1] = 0x23; 473 i2c_success = write_i2c(pipe_ctx, slave_address, 474 buffer, sizeof(buffer)); 475 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 476 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 477 slave_address, buffer[0], buffer[1], i2c_success?1:0); 478 if (!i2c_success) 479 goto i2c_write_fail; 480 481 /* Write offset 0xff to 0x00 */ 482 buffer[0] = 0xff; 483 buffer[1] = 0x00; 484 i2c_success = write_i2c(pipe_ctx, slave_address, 485 buffer, sizeof(buffer)); 486 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 487 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 488 slave_address, buffer[0], buffer[1], i2c_success?1:0); 489 if (!i2c_success) 490 goto i2c_write_fail; 491 492 } 493 494 return; 495 496 i2c_write_fail: 497 DC_LOG_DEBUG("Set retimer failed"); 498 } 499 500 static void write_i2c_default_retimer_setting( 501 struct pipe_ctx *pipe_ctx, 502 bool is_vga_mode, 503 bool is_over_340mhz) 504 { 505 uint8_t slave_address = (0xBA >> 1); 506 uint8_t buffer[2]; 507 bool i2c_success = false; 508 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 509 510 memset(&buffer, 0, sizeof(buffer)); 511 512 /* Program Slave Address for tuning single integrity */ 513 /* Write offset 0x0A to 0x13 */ 514 buffer[0] = 0x0A; 515 buffer[1] = 0x13; 516 i2c_success = write_i2c(pipe_ctx, slave_address, 517 buffer, sizeof(buffer)); 518 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 519 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 520 slave_address, buffer[0], buffer[1], i2c_success?1:0); 521 if (!i2c_success) 522 goto i2c_write_fail; 523 524 /* Write offset 0x0A to 0x17 */ 525 buffer[0] = 0x0A; 526 buffer[1] = 0x17; 527 i2c_success = write_i2c(pipe_ctx, slave_address, 528 buffer, sizeof(buffer)); 529 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 530 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 531 slave_address, buffer[0], buffer[1], i2c_success?1:0); 532 if (!i2c_success) 533 goto i2c_write_fail; 534 535 /* Write offset 0x0B to 0xDA or 0xD8 */ 536 buffer[0] = 0x0B; 537 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 538 i2c_success = write_i2c(pipe_ctx, slave_address, 539 buffer, sizeof(buffer)); 540 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 541 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 542 slave_address, buffer[0], buffer[1], i2c_success?1:0); 543 if (!i2c_success) 544 goto i2c_write_fail; 545 546 /* Write offset 0x0A to 0x17 */ 547 buffer[0] = 0x0A; 548 buffer[1] = 0x17; 549 i2c_success = write_i2c(pipe_ctx, slave_address, 550 buffer, sizeof(buffer)); 551 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 552 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 553 slave_address, buffer[0], buffer[1], i2c_success?1:0); 554 if (!i2c_success) 555 goto i2c_write_fail; 556 557 /* Write offset 0x0C to 0x1D or 0x91 */ 558 buffer[0] = 0x0C; 559 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 560 i2c_success = write_i2c(pipe_ctx, slave_address, 561 buffer, sizeof(buffer)); 562 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 563 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 564 slave_address, buffer[0], buffer[1], i2c_success?1:0); 565 if (!i2c_success) 566 goto i2c_write_fail; 567 568 /* Write offset 0x0A to 0x17 */ 569 buffer[0] = 0x0A; 570 buffer[1] = 0x17; 571 i2c_success = write_i2c(pipe_ctx, slave_address, 572 buffer, sizeof(buffer)); 573 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 574 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 575 slave_address, buffer[0], buffer[1], i2c_success?1:0); 576 if (!i2c_success) 577 goto i2c_write_fail; 578 579 580 if (is_vga_mode) { 581 /* Program additional settings if using 640x480 resolution */ 582 583 /* Write offset 0xFF to 0x01 */ 584 buffer[0] = 0xff; 585 buffer[1] = 0x01; 586 i2c_success = write_i2c(pipe_ctx, slave_address, 587 buffer, sizeof(buffer)); 588 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 589 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 590 slave_address, buffer[0], buffer[1], i2c_success?1:0); 591 if (!i2c_success) 592 goto i2c_write_fail; 593 594 /* Write offset 0x00 to 0x23 */ 595 buffer[0] = 0x00; 596 buffer[1] = 0x23; 597 i2c_success = write_i2c(pipe_ctx, slave_address, 598 buffer, sizeof(buffer)); 599 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 600 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 601 slave_address, buffer[0], buffer[1], i2c_success?1:0); 602 if (!i2c_success) 603 goto i2c_write_fail; 604 605 /* Write offset 0xff to 0x00 */ 606 buffer[0] = 0xff; 607 buffer[1] = 0x00; 608 i2c_success = write_i2c(pipe_ctx, slave_address, 609 buffer, sizeof(buffer)); 610 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 611 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 612 slave_address, buffer[0], buffer[1], i2c_success?1:0); 613 if (!i2c_success) 614 goto i2c_write_fail; 615 } 616 617 return; 618 619 i2c_write_fail: 620 DC_LOG_DEBUG("Set default retimer failed"); 621 } 622 623 static void write_i2c_redriver_setting( 624 struct pipe_ctx *pipe_ctx, 625 bool is_over_340mhz) 626 { 627 uint8_t slave_address = (0xF0 >> 1); 628 uint8_t buffer[16]; 629 bool i2c_success = false; 630 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 631 632 memset(&buffer, 0, sizeof(buffer)); 633 634 // Program Slave Address for tuning single integrity 635 buffer[3] = 0x4E; 636 buffer[4] = 0x4E; 637 buffer[5] = 0x4E; 638 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 639 640 i2c_success = write_i2c(pipe_ctx, slave_address, 641 buffer, sizeof(buffer)); 642 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 643 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 644 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 645 i2c_success = %d\n", 646 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 647 648 if (!i2c_success) 649 DC_LOG_DEBUG("Set redriver failed"); 650 } 651 652 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 653 { 654 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 655 struct link_encoder *link_enc = NULL; 656 struct cp_psp_stream_config config = {0}; 657 enum dp_panel_mode panel_mode = 658 dp_get_panel_mode(pipe_ctx->stream->link); 659 660 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 661 return; 662 663 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 664 ASSERT(link_enc); 665 if (link_enc == NULL) 666 return; 667 668 /* otg instance */ 669 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 670 671 /* dig front end */ 672 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 673 674 /* stream encoder index */ 675 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 676 if (dp_is_128b_132b_signal(pipe_ctx)) 677 config.stream_enc_idx = 678 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 679 680 /* dig back end */ 681 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 682 683 /* link encoder index */ 684 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 685 if (dp_is_128b_132b_signal(pipe_ctx)) 686 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 687 688 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 689 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 690 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 691 else 692 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 693 694 695 /* phy index */ 696 config.phy_idx = resource_transmitter_to_phy_idx( 697 pipe_ctx->stream->link->dc, link_enc->transmitter); 698 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 699 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 700 config.phy_idx = 0; 701 702 /* stream properties */ 703 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 704 config.mst_enabled = (pipe_ctx->stream->signal == 705 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 706 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 707 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 708 1 : 0; 709 config.dpms_off = dpms_off; 710 711 /* dm stream context */ 712 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 713 714 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 715 } 716 717 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 718 { 719 struct dc *dc = pipe_ctx->stream->ctx->dc; 720 721 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 722 return; 723 724 dc->hwss.set_avmute(pipe_ctx, enable); 725 } 726 727 static void enable_mst_on_sink(struct dc_link *link, bool enable) 728 { 729 unsigned char mstmCntl = 0; 730 731 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 732 if (enable) 733 mstmCntl |= DP_MST_EN; 734 else 735 mstmCntl &= (~DP_MST_EN); 736 737 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 738 } 739 740 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 741 struct dsc_optc_config *config) 742 { 743 uint32_t precision = 1 << 28; 744 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 745 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 746 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 747 DC_LOGGER_INIT(dsc->ctx->logger); 748 749 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 750 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 751 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 752 */ 753 ll_bytes_per_pix_fraq *= 10000000; 754 ll_bytes_per_pix_fraq /= precision; 755 756 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 757 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 758 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 759 DC_LOG_DSC("\tslice_width %d", config->slice_width); 760 } 761 762 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 763 { 764 struct dc *dc = pipe_ctx->stream->ctx->dc; 765 struct dc_stream_state *stream = pipe_ctx->stream; 766 bool result = false; 767 768 if (dc_is_virtual_signal(stream->signal)) 769 result = true; 770 else 771 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 772 return result; 773 } 774 775 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 776 * i.e. after dp_enable_dsc_on_rx() had been called 777 */ 778 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 779 { 780 /* TODO: Move this to HWSS as this is hardware programming sequence not a 781 * link layer sequence 782 */ 783 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 784 struct dc *dc = pipe_ctx->stream->ctx->dc; 785 struct dc_stream_state *stream = pipe_ctx->stream; 786 struct pipe_ctx *odm_pipe; 787 int opp_cnt = 1; 788 struct dccg *dccg = dc->res_pool->dccg; 789 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 790 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 791 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 792 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 793 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 794 * this problem. We are implementing a workaround here to keep using dscclk 795 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 796 * 48Mhz) pixel clock to avoid hitting this problem. 797 */ 798 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 799 stream->timing.pix_clk_100hz > 480000; 800 DC_LOGGER_INIT(dsc->ctx->logger); 801 802 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 803 opp_cnt++; 804 805 if (enable) { 806 struct dsc_config dsc_cfg; 807 struct dsc_optc_config dsc_optc_cfg = {0}; 808 enum optc_dsc_mode optc_dsc_mode; 809 810 /* Enable DSC hw block */ 811 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 812 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 813 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 814 dsc_cfg.color_depth = stream->timing.display_color_depth; 815 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 816 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 817 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 818 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 819 820 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 821 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 822 if (should_use_dto_dscclk) 823 dccg->funcs->set_dto_dscclk(dccg, dsc->inst); 824 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 825 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 826 827 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 828 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 829 if (should_use_dto_dscclk) 830 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst); 831 } 832 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 833 dsc_cfg.pic_width *= opp_cnt; 834 835 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 836 837 /* Enable DSC in encoder */ 838 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 839 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 840 dsc_optc_config_log(dsc, &dsc_optc_cfg); 841 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 842 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 843 optc_dsc_mode, 844 dsc_optc_cfg.bytes_per_pixel, 845 dsc_optc_cfg.slice_width); 846 847 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 848 } 849 850 /* Enable DSC in OPTC */ 851 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 852 dsc_optc_config_log(dsc, &dsc_optc_cfg); 853 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 854 optc_dsc_mode, 855 dsc_optc_cfg.bytes_per_pixel, 856 dsc_optc_cfg.slice_width); 857 } else { 858 /* disable DSC in OPTC */ 859 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 860 pipe_ctx->stream_res.tg, 861 OPTC_DSC_DISABLED, 0, 0); 862 863 /* disable DSC in stream encoder */ 864 if (dc_is_dp_signal(stream->signal)) { 865 if (dp_is_128b_132b_signal(pipe_ctx)) 866 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 867 pipe_ctx->stream_res.hpo_dp_stream_enc, 868 false, 869 NULL, 870 true); 871 else { 872 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 873 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 874 pipe_ctx->stream_res.stream_enc, 875 OPTC_DSC_DISABLED, 0, 0); 876 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 877 pipe_ctx->stream_res.stream_enc, false, NULL, true); 878 } 879 } 880 881 /* disable DSC block */ 882 if (dccg->funcs->set_ref_dscclk) 883 dccg->funcs->set_ref_dscclk(dccg, pipe_ctx->stream_res.dsc->inst); 884 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 885 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 886 if (dccg->funcs->set_ref_dscclk) 887 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 888 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 889 } 890 } 891 } 892 893 /* 894 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 895 * hence PPS info packet update need to use frame update instead of immediate update. 896 * Added parameter immediate_update for this purpose. 897 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 898 * which is the only place where a "false" would be passed in for param immediate_update. 899 * 900 * immediate_update is only applicable when DSC is enabled. 901 */ 902 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 903 { 904 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 905 struct dc_stream_state *stream = pipe_ctx->stream; 906 907 if (!pipe_ctx->stream->timing.flags.DSC) 908 return false; 909 910 if (!dsc) 911 return false; 912 913 DC_LOGGER_INIT(dsc->ctx->logger); 914 915 if (enable) { 916 struct dsc_config dsc_cfg; 917 uint8_t dsc_packed_pps[128]; 918 919 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 920 memset(dsc_packed_pps, 0, 128); 921 922 /* Enable DSC hw block */ 923 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 924 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 925 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 926 dsc_cfg.color_depth = stream->timing.display_color_depth; 927 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 928 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 929 930 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 931 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 932 if (dc_is_dp_signal(stream->signal)) { 933 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 934 if (dp_is_128b_132b_signal(pipe_ctx)) 935 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 936 pipe_ctx->stream_res.hpo_dp_stream_enc, 937 true, 938 &dsc_packed_pps[0], 939 immediate_update); 940 else 941 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 942 pipe_ctx->stream_res.stream_enc, 943 true, 944 &dsc_packed_pps[0], 945 immediate_update); 946 } 947 } else { 948 /* disable DSC PPS in stream encoder */ 949 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 950 if (dc_is_dp_signal(stream->signal)) { 951 if (dp_is_128b_132b_signal(pipe_ctx)) 952 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 953 pipe_ctx->stream_res.hpo_dp_stream_enc, 954 false, 955 NULL, 956 true); 957 else 958 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 959 pipe_ctx->stream_res.stream_enc, false, NULL, true); 960 } 961 } 962 963 return true; 964 } 965 966 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 967 { 968 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 969 bool result = false; 970 971 if (!pipe_ctx->stream->timing.flags.DSC) 972 goto out; 973 if (!dsc) 974 goto out; 975 976 if (enable) { 977 { 978 link_set_dsc_on_stream(pipe_ctx, true); 979 result = true; 980 } 981 } else { 982 dp_set_dsc_on_rx(pipe_ctx, false); 983 link_set_dsc_on_stream(pipe_ctx, false); 984 result = true; 985 } 986 out: 987 return result; 988 } 989 990 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 991 { 992 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 993 994 if (!pipe_ctx->stream->timing.flags.DSC) 995 return false; 996 if (!dsc) 997 return false; 998 999 link_set_dsc_on_stream(pipe_ctx, true); 1000 link_set_dsc_pps_packet(pipe_ctx, true, false); 1001 return true; 1002 } 1003 1004 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1005 { 1006 struct dc_stream_state *stream = pipe_ctx->stream; 1007 1008 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1009 struct dc_link *link = stream->link; 1010 union down_spread_ctrl old_downspread; 1011 union down_spread_ctrl new_downspread; 1012 1013 memset(&old_downspread, 0, sizeof(old_downspread)); 1014 1015 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1016 &old_downspread.raw, sizeof(old_downspread)); 1017 1018 new_downspread.raw = old_downspread.raw; 1019 1020 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1021 (stream->ignore_msa_timing_param) ? 1 : 0; 1022 1023 if (new_downspread.raw != old_downspread.raw) { 1024 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1025 &new_downspread.raw, sizeof(new_downspread)); 1026 } 1027 1028 } else { 1029 dm_helpers_mst_enable_stream_features(stream); 1030 } 1031 } 1032 1033 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1034 { 1035 const uint32_t VCP_Y_PRECISION = 1000; 1036 uint64_t vcp_x, vcp_y; 1037 DC_LOGGER_INIT(link->ctx->logger); 1038 1039 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1040 avg_time_slots_per_mtp = dc_fixpt_add( 1041 avg_time_slots_per_mtp, 1042 dc_fixpt_from_fraction( 1043 1, 1044 2*VCP_Y_PRECISION)); 1045 1046 vcp_x = dc_fixpt_floor( 1047 avg_time_slots_per_mtp); 1048 vcp_y = dc_fixpt_floor( 1049 dc_fixpt_mul_int( 1050 dc_fixpt_sub_int( 1051 avg_time_slots_per_mtp, 1052 dc_fixpt_floor( 1053 avg_time_slots_per_mtp)), 1054 VCP_Y_PRECISION)); 1055 1056 1057 if (link->type == dc_connection_mst_branch) 1058 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1059 "X: %llu " 1060 "Y: %llu/%d", 1061 vcp_x, 1062 vcp_y, 1063 VCP_Y_PRECISION); 1064 else 1065 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1066 "X: %llu " 1067 "Y: %llu/%d", 1068 vcp_x, 1069 vcp_y, 1070 VCP_Y_PRECISION); 1071 } 1072 1073 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1074 { 1075 struct fixed31_32 mbytes_per_sec; 1076 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1077 &stream->link->cur_link_settings); 1078 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1079 1080 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1081 1082 return dc_fixpt_div_int(mbytes_per_sec, 54); 1083 } 1084 1085 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1086 { 1087 struct fixed31_32 peak_kbps; 1088 uint32_t numerator = 0; 1089 uint32_t denominator = 1; 1090 1091 /* 1092 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1093 * required when determining PBN/time slot utilization on the link between 1094 * us and the branch, since that overhead is already accounted for in 1095 * the get_pbn_per_slot function. 1096 * 1097 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1098 * common multiplier to render an integer PBN for all link rate/lane 1099 * counts combinations 1100 * calculate 1101 * peak_kbps *= (64/54) 1102 * peak_kbps /= (8 * 1000) convert to bytes 1103 */ 1104 1105 numerator = 64; 1106 denominator = 54 * 8 * 1000; 1107 kbps *= numerator; 1108 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1109 1110 return peak_kbps; 1111 } 1112 1113 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1114 { 1115 uint64_t kbps; 1116 enum dc_link_encoding_format link_encoding; 1117 1118 if (dp_is_128b_132b_signal(pipe_ctx)) 1119 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1120 else 1121 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1122 1123 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1124 return get_pbn_from_bw_in_kbps(kbps); 1125 } 1126 1127 1128 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1129 static void get_lane_status( 1130 struct dc_link *link, 1131 uint32_t lane_count, 1132 union lane_status *status, 1133 union lane_align_status_updated *status_updated) 1134 { 1135 unsigned int lane; 1136 uint8_t dpcd_buf[3] = {0}; 1137 1138 if (status == NULL || status_updated == NULL) { 1139 return; 1140 } 1141 1142 core_link_read_dpcd( 1143 link, 1144 DP_LANE0_1_STATUS, 1145 dpcd_buf, 1146 sizeof(dpcd_buf)); 1147 1148 for (lane = 0; lane < lane_count; lane++) { 1149 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1150 } 1151 1152 status_updated->raw = dpcd_buf[2]; 1153 } 1154 1155 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1156 { 1157 /* 1158 * wait for ACT handled 1159 */ 1160 int i; 1161 const int act_retries = 30; 1162 enum act_return_status result = ACT_FAILED; 1163 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1164 union payload_table_update_status update_status = {0}; 1165 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1166 union lane_align_status_updated lane_status_updated; 1167 DC_LOGGER_INIT(link->ctx->logger); 1168 1169 if (!display_connected || link->aux_access_disabled) 1170 return true; 1171 for (i = 0; i < act_retries; i++) { 1172 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1173 1174 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1175 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1176 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1177 !dp_is_interlane_aligned(lane_status_updated)) { 1178 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1179 "polling for ACT handled."); 1180 result = ACT_LINK_LOST; 1181 break; 1182 } 1183 core_link_read_dpcd( 1184 link, 1185 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1186 &update_status.raw, 1187 1); 1188 1189 if (update_status.bits.ACT_HANDLED == 1) { 1190 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1191 result = ACT_SUCCESS; 1192 break; 1193 } 1194 1195 fsleep(5000); 1196 } 1197 1198 if (result == ACT_FAILED) { 1199 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1200 "continue on. Something is wrong with the branch."); 1201 } 1202 1203 return (result == ACT_SUCCESS); 1204 } 1205 1206 static void update_mst_stream_alloc_table( 1207 struct dc_link *link, 1208 struct stream_encoder *stream_enc, 1209 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1210 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1211 { 1212 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1213 struct link_mst_stream_allocation *dc_alloc; 1214 1215 int i; 1216 int j; 1217 1218 /* if DRM proposed_table has more than one new payload */ 1219 ASSERT(proposed_table->stream_count - 1220 link->mst_stream_alloc_table.stream_count < 2); 1221 1222 /* copy proposed_table to link, add stream encoder */ 1223 for (i = 0; i < proposed_table->stream_count; i++) { 1224 1225 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1226 dc_alloc = 1227 &link->mst_stream_alloc_table.stream_allocations[j]; 1228 1229 if (dc_alloc->vcp_id == 1230 proposed_table->stream_allocations[i].vcp_id) { 1231 1232 work_table[i] = *dc_alloc; 1233 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1234 break; /* exit j loop */ 1235 } 1236 } 1237 1238 /* new vcp_id */ 1239 if (j == link->mst_stream_alloc_table.stream_count) { 1240 work_table[i].vcp_id = 1241 proposed_table->stream_allocations[i].vcp_id; 1242 work_table[i].slot_count = 1243 proposed_table->stream_allocations[i].slot_count; 1244 work_table[i].stream_enc = stream_enc; 1245 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1246 } 1247 } 1248 1249 /* update link->mst_stream_alloc_table with work_table */ 1250 link->mst_stream_alloc_table.stream_count = 1251 proposed_table->stream_count; 1252 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1253 link->mst_stream_alloc_table.stream_allocations[i] = 1254 work_table[i]; 1255 } 1256 1257 static void remove_stream_from_alloc_table( 1258 struct dc_link *link, 1259 struct stream_encoder *dio_stream_enc, 1260 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1261 { 1262 int i = 0; 1263 struct link_mst_stream_allocation_table *table = 1264 &link->mst_stream_alloc_table; 1265 1266 if (hpo_dp_stream_enc) { 1267 for (; i < table->stream_count; i++) 1268 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1269 break; 1270 } else { 1271 for (; i < table->stream_count; i++) 1272 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1273 break; 1274 } 1275 1276 if (i < table->stream_count) { 1277 i++; 1278 for (; i < table->stream_count; i++) 1279 table->stream_allocations[i-1] = table->stream_allocations[i]; 1280 memset(&table->stream_allocations[table->stream_count-1], 0, 1281 sizeof(struct link_mst_stream_allocation)); 1282 table->stream_count--; 1283 } 1284 } 1285 1286 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1287 { 1288 struct dc_stream_state *stream = pipe_ctx->stream; 1289 struct dc_link *link = stream->link; 1290 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1291 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1292 int i; 1293 bool mst_mode = (link->type == dc_connection_mst_branch); 1294 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1295 const struct dc_link_settings empty_link_settings = {0}; 1296 DC_LOGGER_INIT(link->ctx->logger); 1297 1298 /* deallocate_mst_payload is called before disable link. When mode or 1299 * disable/enable monitor, new stream is created which is not in link 1300 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1301 * should not done. For new mode set, map_resources will get engine 1302 * for new stream, so stream_enc->id should be validated until here. 1303 */ 1304 1305 /* slot X.Y */ 1306 if (link_hwss->ext.set_throttled_vcp_size) 1307 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1308 if (link_hwss->ext.set_hblank_min_symbol_width) 1309 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1310 &empty_link_settings, 1311 avg_time_slots_per_mtp); 1312 1313 if (mst_mode) { 1314 /* when link is in mst mode, reply on mst manager to remove 1315 * payload 1316 */ 1317 if (dm_helpers_dp_mst_write_payload_allocation_table( 1318 stream->ctx, 1319 stream, 1320 &proposed_table, 1321 false)) 1322 update_mst_stream_alloc_table( 1323 link, 1324 pipe_ctx->stream_res.stream_enc, 1325 pipe_ctx->stream_res.hpo_dp_stream_enc, 1326 &proposed_table); 1327 else 1328 DC_LOG_WARNING("Failed to update" 1329 "MST allocation table for" 1330 "pipe idx:%d\n", 1331 pipe_ctx->pipe_idx); 1332 } else { 1333 /* when link is no longer in mst mode (mst hub unplugged), 1334 * remove payload with default dc logic 1335 */ 1336 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1337 pipe_ctx->stream_res.hpo_dp_stream_enc); 1338 } 1339 1340 DC_LOG_MST("%s" 1341 "stream_count: %d: ", 1342 __func__, 1343 link->mst_stream_alloc_table.stream_count); 1344 1345 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1346 DC_LOG_MST("stream_enc[%d]: %p " 1347 "stream[%d].hpo_dp_stream_enc: %p " 1348 "stream[%d].vcp_id: %d " 1349 "stream[%d].slot_count: %d\n", 1350 i, 1351 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1352 i, 1353 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1354 i, 1355 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1356 i, 1357 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1358 } 1359 1360 /* update mst stream allocation table hardware state */ 1361 if (link_hwss->ext.update_stream_allocation_table == NULL || 1362 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1363 DC_LOG_DEBUG("Unknown encoding format\n"); 1364 return DC_ERROR_UNEXPECTED; 1365 } 1366 1367 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1368 &link->mst_stream_alloc_table); 1369 1370 if (mst_mode) 1371 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1372 stream->ctx, 1373 stream); 1374 1375 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1376 stream->ctx, 1377 stream); 1378 1379 return DC_OK; 1380 } 1381 1382 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1383 * because stream_encoder is not exposed to dm 1384 */ 1385 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1386 { 1387 struct dc_stream_state *stream = pipe_ctx->stream; 1388 struct dc_link *link = stream->link; 1389 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1390 struct fixed31_32 avg_time_slots_per_mtp; 1391 struct fixed31_32 pbn; 1392 struct fixed31_32 pbn_per_slot; 1393 int i; 1394 enum act_return_status ret; 1395 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1396 DC_LOGGER_INIT(link->ctx->logger); 1397 1398 /* enable_link_dp_mst already check link->enabled_stream_count 1399 * and stream is in link->stream[]. This is called during set mode, 1400 * stream_enc is available. 1401 */ 1402 1403 /* get calculate VC payload for stream: stream_alloc */ 1404 if (dm_helpers_dp_mst_write_payload_allocation_table( 1405 stream->ctx, 1406 stream, 1407 &proposed_table, 1408 true)) 1409 update_mst_stream_alloc_table( 1410 link, 1411 pipe_ctx->stream_res.stream_enc, 1412 pipe_ctx->stream_res.hpo_dp_stream_enc, 1413 &proposed_table); 1414 else 1415 DC_LOG_WARNING("Failed to update" 1416 "MST allocation table for" 1417 "pipe idx:%d\n", 1418 pipe_ctx->pipe_idx); 1419 1420 DC_LOG_MST("%s " 1421 "stream_count: %d: \n ", 1422 __func__, 1423 link->mst_stream_alloc_table.stream_count); 1424 1425 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1426 DC_LOG_MST("stream_enc[%d]: %p " 1427 "stream[%d].hpo_dp_stream_enc: %p " 1428 "stream[%d].vcp_id: %d " 1429 "stream[%d].slot_count: %d\n", 1430 i, 1431 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1432 i, 1433 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1434 i, 1435 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1436 i, 1437 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1438 } 1439 1440 ASSERT(proposed_table.stream_count > 0); 1441 1442 /* program DP source TX for payload */ 1443 if (link_hwss->ext.update_stream_allocation_table == NULL || 1444 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1445 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1446 return DC_ERROR_UNEXPECTED; 1447 } 1448 1449 link_hwss->ext.update_stream_allocation_table(link, 1450 &pipe_ctx->link_res, 1451 &link->mst_stream_alloc_table); 1452 1453 /* send down message */ 1454 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1455 stream->ctx, 1456 stream); 1457 1458 if (ret != ACT_LINK_LOST) 1459 dm_helpers_dp_mst_send_payload_allocation( 1460 stream->ctx, 1461 stream); 1462 1463 /* slot X.Y for only current stream */ 1464 pbn_per_slot = get_pbn_per_slot(stream); 1465 if (pbn_per_slot.value == 0) { 1466 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1467 return DC_UNSUPPORTED_VALUE; 1468 } 1469 pbn = get_pbn_from_timing(pipe_ctx); 1470 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1471 1472 log_vcp_x_y(link, avg_time_slots_per_mtp); 1473 1474 if (link_hwss->ext.set_throttled_vcp_size) 1475 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1476 if (link_hwss->ext.set_hblank_min_symbol_width) 1477 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1478 &link->cur_link_settings, 1479 avg_time_slots_per_mtp); 1480 1481 return DC_OK; 1482 } 1483 1484 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1485 const struct dc_stream_state *stream, 1486 const struct dc_link *link) 1487 { 1488 struct fixed31_32 link_bw_effective = 1489 dc_fixpt_from_int( 1490 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1491 struct fixed31_32 timeslot_bw_effective = 1492 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1493 struct fixed31_32 timing_bw = 1494 dc_fixpt_from_int( 1495 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1496 dc_link_get_highest_encoding_format(link))); 1497 struct fixed31_32 avg_time_slots_per_mtp = 1498 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1499 1500 return avg_time_slots_per_mtp; 1501 } 1502 1503 1504 static bool write_128b_132b_sst_payload_allocation_table( 1505 const struct dc_stream_state *stream, 1506 struct dc_link *link, 1507 struct link_mst_stream_allocation_table *proposed_table, 1508 bool allocate) 1509 { 1510 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1511 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1512 bool result = false; 1513 uint8_t req_slot_count = 0; 1514 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1515 union payload_table_update_status update_status = { 0 }; 1516 const uint32_t max_retries = 30; 1517 uint32_t retries = 0; 1518 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1519 DC_LOGGER_INIT(link->ctx->logger); 1520 1521 if (allocate) { 1522 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1523 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1524 /// Validation should filter out modes that exceed link BW 1525 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1526 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1527 return false; 1528 } else { 1529 /// Leave req_slot_count = 0 if allocate is false. 1530 } 1531 1532 proposed_table->stream_count = 1; /// Always 1 stream for SST 1533 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1534 proposed_table->stream_allocations[0].vcp_id = vc_id; 1535 1536 if (!display_connected || link->aux_access_disabled) 1537 return true; 1538 1539 /// Write DPCD 2C0 = 1 to start updating 1540 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1541 core_link_write_dpcd( 1542 link, 1543 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1544 &update_status.raw, 1545 1); 1546 1547 /// Program the changes in DPCD 1C0 - 1C2 1548 ASSERT(vc_id == 1); 1549 core_link_write_dpcd( 1550 link, 1551 DP_PAYLOAD_ALLOCATE_SET, 1552 &vc_id, 1553 1); 1554 1555 ASSERT(start_time_slot == 0); 1556 core_link_write_dpcd( 1557 link, 1558 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1559 &start_time_slot, 1560 1); 1561 1562 core_link_write_dpcd( 1563 link, 1564 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1565 &req_slot_count, 1566 1); 1567 1568 /// Poll till DPCD 2C0 read 1 1569 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1570 1571 while (retries < max_retries) { 1572 if (core_link_read_dpcd( 1573 link, 1574 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1575 &update_status.raw, 1576 1) == DC_OK) { 1577 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1578 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1579 result = true; 1580 break; 1581 } 1582 } else { 1583 union dpcd_rev dpcdRev = {0}; 1584 1585 if (core_link_read_dpcd( 1586 link, 1587 DP_DPCD_REV, 1588 &dpcdRev.raw, 1589 1) != DC_OK) { 1590 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1591 "of sink while polling payload table " 1592 "updated status bit."); 1593 break; 1594 } 1595 } 1596 retries++; 1597 fsleep(5000); 1598 } 1599 1600 if (!result && retries == max_retries) { 1601 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1602 "continue on. Something is wrong with the branch."); 1603 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1604 } 1605 1606 return result; 1607 } 1608 1609 /* 1610 * Payload allocation/deallocation for SST introduced in DP2.0 1611 */ 1612 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1613 bool allocate) 1614 { 1615 struct dc_stream_state *stream = pipe_ctx->stream; 1616 struct dc_link *link = stream->link; 1617 struct link_mst_stream_allocation_table proposed_table = {0}; 1618 struct fixed31_32 avg_time_slots_per_mtp; 1619 const struct dc_link_settings empty_link_settings = {0}; 1620 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1621 DC_LOGGER_INIT(link->ctx->logger); 1622 1623 /* slot X.Y for SST payload deallocate */ 1624 if (!allocate) { 1625 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1626 1627 log_vcp_x_y(link, avg_time_slots_per_mtp); 1628 1629 if (link_hwss->ext.set_throttled_vcp_size) 1630 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1631 avg_time_slots_per_mtp); 1632 if (link_hwss->ext.set_hblank_min_symbol_width) 1633 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1634 &empty_link_settings, 1635 avg_time_slots_per_mtp); 1636 } 1637 1638 /* calculate VC payload and update branch with new payload allocation table*/ 1639 if (!write_128b_132b_sst_payload_allocation_table( 1640 stream, 1641 link, 1642 &proposed_table, 1643 allocate)) { 1644 DC_LOG_ERROR("SST Update Payload: Failed to update " 1645 "allocation table for " 1646 "pipe idx: %d\n", 1647 pipe_ctx->pipe_idx); 1648 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1649 } 1650 1651 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1652 1653 ASSERT(proposed_table.stream_count == 1); 1654 1655 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1656 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1657 "vcp_id: %d " 1658 "slot_count: %d\n", 1659 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1660 proposed_table.stream_allocations[0].vcp_id, 1661 proposed_table.stream_allocations[0].slot_count); 1662 1663 /* program DP source TX for payload */ 1664 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1665 &proposed_table); 1666 1667 /* poll for ACT handled */ 1668 if (!poll_for_allocation_change_trigger(link)) { 1669 // Failures will result in blackscreen and errors logged 1670 BREAK_TO_DEBUGGER(); 1671 } 1672 1673 /* slot X.Y for SST payload allocate */ 1674 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1675 DP_128b_132b_ENCODING) { 1676 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1677 1678 log_vcp_x_y(link, avg_time_slots_per_mtp); 1679 1680 if (link_hwss->ext.set_throttled_vcp_size) 1681 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1682 avg_time_slots_per_mtp); 1683 if (link_hwss->ext.set_hblank_min_symbol_width) 1684 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1685 &link->cur_link_settings, 1686 avg_time_slots_per_mtp); 1687 } 1688 1689 /* Always return DC_OK. 1690 * If part of sequence fails, log failure(s) and show blackscreen 1691 */ 1692 return DC_OK; 1693 } 1694 1695 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1696 { 1697 struct dc_stream_state *stream = pipe_ctx->stream; 1698 struct dc_link *link = stream->link; 1699 struct fixed31_32 avg_time_slots_per_mtp; 1700 struct fixed31_32 pbn; 1701 struct fixed31_32 pbn_per_slot; 1702 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1703 uint8_t i; 1704 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1705 DC_LOGGER_INIT(link->ctx->logger); 1706 1707 /* decrease throttled vcp size */ 1708 pbn_per_slot = get_pbn_per_slot(stream); 1709 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1710 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1711 1712 if (link_hwss->ext.set_throttled_vcp_size) 1713 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1714 if (link_hwss->ext.set_hblank_min_symbol_width) 1715 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1716 &link->cur_link_settings, 1717 avg_time_slots_per_mtp); 1718 1719 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1720 dm_helpers_dp_mst_send_payload_allocation( 1721 stream->ctx, 1722 stream); 1723 1724 /* notify immediate branch device table update */ 1725 if (dm_helpers_dp_mst_write_payload_allocation_table( 1726 stream->ctx, 1727 stream, 1728 &proposed_table, 1729 true)) { 1730 /* update mst stream allocation table software state */ 1731 update_mst_stream_alloc_table( 1732 link, 1733 pipe_ctx->stream_res.stream_enc, 1734 pipe_ctx->stream_res.hpo_dp_stream_enc, 1735 &proposed_table); 1736 } else { 1737 DC_LOG_WARNING("Failed to update" 1738 "MST allocation table for" 1739 "pipe idx:%d\n", 1740 pipe_ctx->pipe_idx); 1741 } 1742 1743 DC_LOG_MST("%s " 1744 "stream_count: %d: \n ", 1745 __func__, 1746 link->mst_stream_alloc_table.stream_count); 1747 1748 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1749 DC_LOG_MST("stream_enc[%d]: %p " 1750 "stream[%d].hpo_dp_stream_enc: %p " 1751 "stream[%d].vcp_id: %d " 1752 "stream[%d].slot_count: %d\n", 1753 i, 1754 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1755 i, 1756 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1757 i, 1758 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1759 i, 1760 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1761 } 1762 1763 ASSERT(proposed_table.stream_count > 0); 1764 1765 /* update mst stream allocation table hardware state */ 1766 if (link_hwss->ext.update_stream_allocation_table == NULL || 1767 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1768 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1769 return DC_ERROR_UNEXPECTED; 1770 } 1771 1772 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1773 &link->mst_stream_alloc_table); 1774 1775 /* poll for immediate branch device ACT handled */ 1776 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1777 stream->ctx, 1778 stream); 1779 1780 return DC_OK; 1781 } 1782 1783 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1784 { 1785 struct dc_stream_state *stream = pipe_ctx->stream; 1786 struct dc_link *link = stream->link; 1787 struct fixed31_32 avg_time_slots_per_mtp; 1788 struct fixed31_32 pbn; 1789 struct fixed31_32 pbn_per_slot; 1790 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1791 uint8_t i; 1792 enum act_return_status ret; 1793 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1794 DC_LOGGER_INIT(link->ctx->logger); 1795 1796 /* notify immediate branch device table update */ 1797 if (dm_helpers_dp_mst_write_payload_allocation_table( 1798 stream->ctx, 1799 stream, 1800 &proposed_table, 1801 true)) { 1802 /* update mst stream allocation table software state */ 1803 update_mst_stream_alloc_table( 1804 link, 1805 pipe_ctx->stream_res.stream_enc, 1806 pipe_ctx->stream_res.hpo_dp_stream_enc, 1807 &proposed_table); 1808 } 1809 1810 DC_LOG_MST("%s " 1811 "stream_count: %d: \n ", 1812 __func__, 1813 link->mst_stream_alloc_table.stream_count); 1814 1815 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1816 DC_LOG_MST("stream_enc[%d]: %p " 1817 "stream[%d].hpo_dp_stream_enc: %p " 1818 "stream[%d].vcp_id: %d " 1819 "stream[%d].slot_count: %d\n", 1820 i, 1821 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1822 i, 1823 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1824 i, 1825 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1826 i, 1827 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1828 } 1829 1830 ASSERT(proposed_table.stream_count > 0); 1831 1832 /* update mst stream allocation table hardware state */ 1833 if (link_hwss->ext.update_stream_allocation_table == NULL || 1834 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1835 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1836 return DC_ERROR_UNEXPECTED; 1837 } 1838 1839 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1840 &link->mst_stream_alloc_table); 1841 1842 /* poll for immediate branch device ACT handled */ 1843 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1844 stream->ctx, 1845 stream); 1846 1847 if (ret != ACT_LINK_LOST) { 1848 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1849 dm_helpers_dp_mst_send_payload_allocation( 1850 stream->ctx, 1851 stream); 1852 } 1853 1854 /* increase throttled vcp size */ 1855 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1856 pbn_per_slot = get_pbn_per_slot(stream); 1857 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1858 1859 if (link_hwss->ext.set_throttled_vcp_size) 1860 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1861 if (link_hwss->ext.set_hblank_min_symbol_width) 1862 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1863 &link->cur_link_settings, 1864 avg_time_slots_per_mtp); 1865 1866 return DC_OK; 1867 } 1868 1869 static void disable_link_dp(struct dc_link *link, 1870 const struct link_resource *link_res, 1871 enum signal_type signal) 1872 { 1873 struct dc_link_settings link_settings = link->cur_link_settings; 1874 1875 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1876 link->mst_stream_alloc_table.stream_count > 0) 1877 /* disable MST link only when last vc payload is deallocated */ 1878 return; 1879 1880 dp_disable_link_phy(link, link_res, signal); 1881 1882 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1883 if (!link->skip_implict_edp_power_control) 1884 link->dc->hwss.edp_power_control(link, false); 1885 } 1886 1887 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1888 /* set the sink to SST mode after disabling the link */ 1889 enable_mst_on_sink(link, false); 1890 1891 if (link_dp_get_encoding_format(&link_settings) == 1892 DP_8b_10b_ENCODING) { 1893 dp_set_fec_enable(link, false); 1894 dp_set_fec_ready(link, link_res, false); 1895 } 1896 } 1897 1898 static void disable_link(struct dc_link *link, 1899 const struct link_resource *link_res, 1900 enum signal_type signal) 1901 { 1902 if (dc_is_dp_signal(signal)) { 1903 disable_link_dp(link, link_res, signal); 1904 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1905 link->dc->hwss.disable_link_output(link, link_res, signal); 1906 } 1907 1908 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1909 /* MST disable link only when no stream use the link */ 1910 if (link->mst_stream_alloc_table.stream_count <= 0) 1911 link->link_status.link_active = false; 1912 } else { 1913 link->link_status.link_active = false; 1914 } 1915 } 1916 1917 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1918 { 1919 struct dc_stream_state *stream = pipe_ctx->stream; 1920 struct dc_link *link = stream->link; 1921 enum dc_color_depth display_color_depth; 1922 enum engine_id eng_id; 1923 struct ext_hdmi_settings settings = {0}; 1924 bool is_over_340mhz = false; 1925 bool is_vga_mode = (stream->timing.h_addressable == 640) 1926 && (stream->timing.v_addressable == 480); 1927 struct dc *dc = pipe_ctx->stream->ctx->dc; 1928 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1929 1930 if (stream->phy_pix_clk == 0) 1931 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1932 if (stream->phy_pix_clk > 340000) 1933 is_over_340mhz = true; 1934 1935 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1936 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1937 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1938 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1939 /* DP159, Retimer settings */ 1940 eng_id = pipe_ctx->stream_res.stream_enc->id; 1941 1942 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1943 write_i2c_retimer_setting(pipe_ctx, 1944 is_vga_mode, is_over_340mhz, &settings); 1945 } else { 1946 write_i2c_default_retimer_setting(pipe_ctx, 1947 is_vga_mode, is_over_340mhz); 1948 } 1949 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1950 /* PI3EQX1204, Redriver settings */ 1951 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1952 } 1953 } 1954 1955 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1956 write_scdc_data( 1957 stream->link->ddc, 1958 stream->phy_pix_clk, 1959 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 1960 1961 memset(&stream->link->cur_link_settings, 0, 1962 sizeof(struct dc_link_settings)); 1963 1964 display_color_depth = stream->timing.display_color_depth; 1965 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1966 display_color_depth = COLOR_DEPTH_888; 1967 1968 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 1969 * character clock in case that beyond 340MHz. 1970 */ 1971 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 1972 link_hwss->setup_stream_encoder(pipe_ctx); 1973 1974 dc->hwss.enable_tmds_link_output( 1975 link, 1976 &pipe_ctx->link_res, 1977 pipe_ctx->stream->signal, 1978 pipe_ctx->clock_source->id, 1979 display_color_depth, 1980 stream->phy_pix_clk); 1981 1982 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1983 read_scdc_data(link->ddc); 1984 } 1985 1986 static enum dc_status enable_link_dp(struct dc_state *state, 1987 struct pipe_ctx *pipe_ctx) 1988 { 1989 struct dc_stream_state *stream = pipe_ctx->stream; 1990 enum dc_status status; 1991 bool skip_video_pattern; 1992 struct dc_link *link = stream->link; 1993 const struct dc_link_settings *link_settings = 1994 &pipe_ctx->link_config.dp_link_settings; 1995 bool fec_enable; 1996 int i; 1997 bool apply_seamless_boot_optimization = false; 1998 uint32_t bl_oled_enable_delay = 50; // in ms 1999 uint32_t post_oui_delay = 30; // 30ms 2000 /* Reduce link bandwidth between failed link training attempts. */ 2001 bool do_fallback = false; 2002 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2003 2004 // Increase retry count if attempting DP1.x on FIXED_VS link 2005 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2006 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2007 lt_attempts = 10; 2008 2009 // check for seamless boot 2010 for (i = 0; i < state->stream_count; i++) { 2011 if (state->streams[i]->apply_seamless_boot_optimization) { 2012 apply_seamless_boot_optimization = true; 2013 break; 2014 } 2015 } 2016 2017 /* Train with fallback when enabling DPIA link. Conventional links are 2018 * trained with fallback during sink detection. 2019 */ 2020 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2021 do_fallback = true; 2022 2023 /* 2024 * Temporary w/a to get DP2.0 link rates to work with SST. 2025 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2026 */ 2027 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2028 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2029 link->dc->debug.set_mst_en_for_sst) { 2030 enable_mst_on_sink(link, true); 2031 } 2032 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2033 /*in case it is not on*/ 2034 if (!link->dc->config.edp_no_power_sequencing) 2035 link->dc->hwss.edp_power_control(link, true); 2036 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2037 } 2038 2039 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2040 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2041 } else { 2042 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2043 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2044 if (state->clk_mgr && !apply_seamless_boot_optimization) 2045 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2046 state, false); 2047 } 2048 2049 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2050 dpcd_set_source_specific_data(link); 2051 if (link->dpcd_sink_ext_caps.raw != 0) { 2052 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2053 msleep(post_oui_delay); 2054 } 2055 2056 // similarly, mode switch can cause loss of cable ID 2057 dpcd_write_cable_id_to_dprx(link); 2058 2059 skip_video_pattern = true; 2060 2061 if (link_settings->link_rate == LINK_RATE_LOW) 2062 skip_video_pattern = false; 2063 2064 if (perform_link_training_with_retries(link_settings, 2065 skip_video_pattern, 2066 lt_attempts, 2067 pipe_ctx, 2068 pipe_ctx->stream->signal, 2069 do_fallback)) { 2070 status = DC_OK; 2071 } else { 2072 status = DC_FAIL_DP_LINK_TRAINING; 2073 } 2074 2075 if (link->preferred_training_settings.fec_enable) 2076 fec_enable = *link->preferred_training_settings.fec_enable; 2077 else 2078 fec_enable = true; 2079 2080 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2081 dp_set_fec_enable(link, fec_enable); 2082 2083 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2084 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2085 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2086 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2087 set_default_brightness_aux(link); 2088 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2089 msleep(bl_oled_enable_delay); 2090 edp_backlight_enable_aux(link, true); 2091 } 2092 2093 return status; 2094 } 2095 2096 static enum dc_status enable_link_edp( 2097 struct dc_state *state, 2098 struct pipe_ctx *pipe_ctx) 2099 { 2100 return enable_link_dp(state, pipe_ctx); 2101 } 2102 2103 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2104 { 2105 struct dc_stream_state *stream = pipe_ctx->stream; 2106 struct dc_link *link = stream->link; 2107 struct dc *dc = stream->ctx->dc; 2108 2109 if (stream->phy_pix_clk == 0) 2110 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2111 2112 memset(&stream->link->cur_link_settings, 0, 2113 sizeof(struct dc_link_settings)); 2114 dc->hwss.enable_lvds_link_output( 2115 link, 2116 &pipe_ctx->link_res, 2117 pipe_ctx->clock_source->id, 2118 stream->phy_pix_clk); 2119 2120 } 2121 2122 static enum dc_status enable_link_dp_mst( 2123 struct dc_state *state, 2124 struct pipe_ctx *pipe_ctx) 2125 { 2126 struct dc_link *link = pipe_ctx->stream->link; 2127 unsigned char mstm_cntl = 0; 2128 2129 /* sink signal type after MST branch is MST. Multiple MST sinks 2130 * share one link. Link DP PHY is enable or training only once. 2131 */ 2132 if (link->link_status.link_active) 2133 return DC_OK; 2134 2135 /* clear payload table */ 2136 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2137 if (mstm_cntl & DP_MST_EN) 2138 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2139 2140 /* to make sure the pending down rep can be processed 2141 * before enabling the link 2142 */ 2143 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2144 2145 /* set the sink to MST mode before enabling the link */ 2146 enable_mst_on_sink(link, true); 2147 2148 return enable_link_dp(state, pipe_ctx); 2149 } 2150 2151 static enum dc_status enable_link( 2152 struct dc_state *state, 2153 struct pipe_ctx *pipe_ctx) 2154 { 2155 enum dc_status status = DC_ERROR_UNEXPECTED; 2156 struct dc_stream_state *stream = pipe_ctx->stream; 2157 struct dc_link *link = stream->link; 2158 2159 /* There's some scenarios where driver is unloaded with display 2160 * still enabled. When driver is reloaded, it may cause a display 2161 * to not light up if there is a mismatch between old and new 2162 * link settings. Need to call disable first before enabling at 2163 * new link settings. 2164 */ 2165 if (link->link_status.link_active) 2166 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2167 2168 switch (pipe_ctx->stream->signal) { 2169 case SIGNAL_TYPE_DISPLAY_PORT: 2170 status = enable_link_dp(state, pipe_ctx); 2171 break; 2172 case SIGNAL_TYPE_EDP: 2173 status = enable_link_edp(state, pipe_ctx); 2174 break; 2175 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2176 status = enable_link_dp_mst(state, pipe_ctx); 2177 msleep(200); 2178 break; 2179 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2180 case SIGNAL_TYPE_DVI_DUAL_LINK: 2181 case SIGNAL_TYPE_HDMI_TYPE_A: 2182 enable_link_hdmi(pipe_ctx); 2183 status = DC_OK; 2184 break; 2185 case SIGNAL_TYPE_LVDS: 2186 enable_link_lvds(pipe_ctx); 2187 status = DC_OK; 2188 break; 2189 case SIGNAL_TYPE_VIRTUAL: 2190 status = DC_OK; 2191 break; 2192 default: 2193 break; 2194 } 2195 2196 if (status == DC_OK) { 2197 pipe_ctx->stream->link->link_status.link_active = true; 2198 } 2199 2200 return status; 2201 } 2202 2203 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2204 { 2205 struct dc_link *link = stream->sink->link; 2206 int req_bw = bw; 2207 2208 DC_LOGGER_INIT(link->ctx->logger); 2209 2210 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2211 return false; 2212 2213 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2214 int sink_index = 0; 2215 int i = 0; 2216 2217 for (i = 0; i < link->sink_count; i++) { 2218 if (link->remote_sinks[i] == NULL) 2219 continue; 2220 2221 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2222 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2223 else 2224 sink_index = i; 2225 } 2226 2227 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2228 } 2229 2230 /* get dp overhead for dp tunneling */ 2231 link->dpia_bw_alloc_config.dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(link); 2232 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2233 2234 if (link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw)) { 2235 if (req_bw <= link->dpia_bw_alloc_config.allocated_bw) { 2236 DC_LOG_DEBUG("%s, Success in allocate bw for link(%d), allocated_bw(%d), dp_overhead(%d)\n", 2237 __func__, link->link_index, link->dpia_bw_alloc_config.allocated_bw, 2238 link->dpia_bw_alloc_config.dp_overhead); 2239 } else { 2240 // Cannot get the required bandwidth. 2241 DC_LOG_ERROR("%s, Failed to allocate bw for link(%d), allocated_bw(%d), dp_overhead(%d)\n", 2242 __func__, link->link_index, link->dpia_bw_alloc_config.allocated_bw, 2243 link->dpia_bw_alloc_config.dp_overhead); 2244 return false; 2245 } 2246 } else { 2247 DC_LOG_DEBUG("%s, usb4 request bw timeout\n", __func__); 2248 return false; 2249 } 2250 2251 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2252 int i = 0; 2253 2254 for (i = 0; i < link->sink_count; i++) { 2255 if (link->remote_sinks[i] == NULL) 2256 continue; 2257 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2258 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2259 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2260 } 2261 } 2262 2263 return true; 2264 } 2265 2266 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2267 { 2268 bool ret; 2269 2270 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2271 dc_link_get_highest_encoding_format(stream->sink->link)); 2272 2273 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2274 2275 return ret; 2276 } 2277 2278 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2279 { 2280 bool ret; 2281 2282 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2283 2284 return ret; 2285 } 2286 2287 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2288 { 2289 struct dc *dc = pipe_ctx->stream->ctx->dc; 2290 struct dc_stream_state *stream = pipe_ctx->stream; 2291 struct dc_link *link = stream->sink->link; 2292 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2293 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2294 2295 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2296 2297 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2298 2299 if (dp_is_128b_132b_signal(pipe_ctx)) 2300 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2301 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2302 return; 2303 2304 if (pipe_ctx->stream->sink) { 2305 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2306 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2307 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2308 pipe_ctx->stream->sink->edid_caps.display_name, 2309 pipe_ctx->stream->signal); 2310 } 2311 } 2312 2313 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2314 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2315 set_avmute(pipe_ctx, true); 2316 } 2317 2318 dc->hwss.disable_audio_stream(pipe_ctx); 2319 2320 update_psp_stream_config(pipe_ctx, true); 2321 dc->hwss.blank_stream(pipe_ctx); 2322 2323 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2324 deallocate_usb4_bandwidth(pipe_ctx->stream); 2325 2326 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2327 deallocate_mst_payload(pipe_ctx); 2328 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2329 dp_is_128b_132b_signal(pipe_ctx)) 2330 update_sst_payload(pipe_ctx, false); 2331 2332 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2333 struct ext_hdmi_settings settings = {0}; 2334 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2335 2336 unsigned short masked_chip_caps = link->chip_caps & 2337 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2338 //Need to inform that sink is going to use legacy HDMI mode. 2339 write_scdc_data( 2340 link->ddc, 2341 165000,//vbios only handles 165Mhz. 2342 false); 2343 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2344 /* DP159, Retimer settings */ 2345 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2346 write_i2c_retimer_setting(pipe_ctx, 2347 false, false, &settings); 2348 else 2349 write_i2c_default_retimer_setting(pipe_ctx, 2350 false, false); 2351 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2352 /* PI3EQX1204, Redriver settings */ 2353 write_i2c_redriver_setting(pipe_ctx, false); 2354 } 2355 } 2356 2357 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2358 !dp_is_128b_132b_signal(pipe_ctx)) { 2359 2360 /* In DP1.x SST mode, our encoder will go to TPS1 2361 * when link is on but stream is off. 2362 * Disabling link before stream will avoid exposing TPS1 pattern 2363 * during the disable sequence as it will confuse some receivers 2364 * state machine. 2365 * In DP2 or MST mode, our encoder will stay video active 2366 */ 2367 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2368 dc->hwss.disable_stream(pipe_ctx); 2369 } else { 2370 dc->hwss.disable_stream(pipe_ctx); 2371 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2372 } 2373 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2374 2375 if (pipe_ctx->stream->timing.flags.DSC) { 2376 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2377 link_set_dsc_enable(pipe_ctx, false); 2378 } 2379 if (dp_is_128b_132b_signal(pipe_ctx)) { 2380 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2381 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2382 } 2383 2384 if (vpg && vpg->funcs->vpg_powerdown) 2385 vpg->funcs->vpg_powerdown(vpg); 2386 2387 /* for psp not exist case */ 2388 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2389 /* reset internal save state to default since eDP is off */ 2390 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2391 /* since current psp not loaded, we need to reset it to default*/ 2392 link->panel_mode = panel_mode; 2393 } 2394 } 2395 2396 void link_set_dpms_on( 2397 struct dc_state *state, 2398 struct pipe_ctx *pipe_ctx) 2399 { 2400 struct dc *dc = pipe_ctx->stream->ctx->dc; 2401 struct dc_stream_state *stream = pipe_ctx->stream; 2402 struct dc_link *link = stream->sink->link; 2403 enum dc_status status; 2404 struct link_encoder *link_enc; 2405 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2406 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2407 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2408 bool apply_edp_fast_boot_optimization = 2409 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2410 2411 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2412 2413 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2414 2415 if (dp_is_128b_132b_signal(pipe_ctx)) 2416 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2417 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2418 return; 2419 2420 if (pipe_ctx->stream->sink) { 2421 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2422 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2423 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2424 pipe_ctx->stream->sink->edid_caps.display_name, 2425 pipe_ctx->stream->signal); 2426 } 2427 } 2428 2429 link_enc = link_enc_cfg_get_link_enc(link); 2430 ASSERT(link_enc); 2431 2432 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2433 && !dp_is_128b_132b_signal(pipe_ctx)) { 2434 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2435 2436 if (link_enc) 2437 link_enc->funcs->setup( 2438 link_enc, 2439 pipe_ctx->stream->signal); 2440 2441 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2442 stream_enc->funcs->dig_stream_enable( 2443 stream_enc, 2444 pipe_ctx->stream->signal, 1); 2445 } 2446 2447 pipe_ctx->stream->link->link_state_valid = true; 2448 2449 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2450 if (dp_is_128b_132b_signal(pipe_ctx)) 2451 otg_out_dest = OUT_MUX_HPO_DP; 2452 else 2453 otg_out_dest = OUT_MUX_DIO; 2454 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2455 } 2456 2457 link_hwss->setup_stream_attribute(pipe_ctx); 2458 2459 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2460 2461 // Enable VPG before building infoframe 2462 if (vpg && vpg->funcs->vpg_poweron) 2463 vpg->funcs->vpg_poweron(vpg); 2464 2465 resource_build_info_frame(pipe_ctx); 2466 dc->hwss.update_info_frame(pipe_ctx); 2467 2468 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2469 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2470 2471 /* Do not touch link on seamless boot optimization. */ 2472 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2473 pipe_ctx->stream->dpms_off = false; 2474 2475 /* Still enable stream features & audio on seamless boot for DP external displays */ 2476 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2477 enable_stream_features(pipe_ctx); 2478 dc->hwss.enable_audio_stream(pipe_ctx); 2479 } 2480 2481 update_psp_stream_config(pipe_ctx, false); 2482 return; 2483 } 2484 2485 /* eDP lit up by bios already, no need to enable again. */ 2486 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2487 apply_edp_fast_boot_optimization && 2488 !pipe_ctx->stream->timing.flags.DSC && 2489 !pipe_ctx->next_odm_pipe) { 2490 pipe_ctx->stream->dpms_off = false; 2491 update_psp_stream_config(pipe_ctx, false); 2492 return; 2493 } 2494 2495 if (pipe_ctx->stream->dpms_off) 2496 return; 2497 2498 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2499 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2500 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2501 * will be automatically set at a later time when the video is enabled 2502 * (DP_VID_STREAM_EN = 1). 2503 */ 2504 if (pipe_ctx->stream->timing.flags.DSC) { 2505 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2506 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2507 link_set_dsc_enable(pipe_ctx, true); 2508 } 2509 2510 status = enable_link(state, pipe_ctx); 2511 2512 if (status != DC_OK) { 2513 DC_LOG_WARNING("enabling link %u failed: %d\n", 2514 pipe_ctx->stream->link->link_index, 2515 status); 2516 2517 /* Abort stream enable *unless* the failure was due to 2518 * DP link training - some DP monitors will recover and 2519 * show the stream anyway. But MST displays can't proceed 2520 * without link training. 2521 */ 2522 if (status != DC_FAIL_DP_LINK_TRAINING || 2523 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2524 if (false == stream->link->link_status.link_active) 2525 disable_link(stream->link, &pipe_ctx->link_res, 2526 pipe_ctx->stream->signal); 2527 BREAK_TO_DEBUGGER(); 2528 return; 2529 } 2530 } 2531 2532 /* turn off otg test pattern if enable */ 2533 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2534 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2535 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2536 COLOR_DEPTH_UNDEFINED); 2537 2538 /* This second call is needed to reconfigure the DIG 2539 * as a workaround for the incorrect value being applied 2540 * from transmitter control. 2541 */ 2542 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2543 dp_is_128b_132b_signal(pipe_ctx))) { 2544 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2545 2546 if (link_enc) 2547 link_enc->funcs->setup( 2548 link_enc, 2549 pipe_ctx->stream->signal); 2550 2551 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2552 stream_enc->funcs->dig_stream_enable( 2553 stream_enc, 2554 pipe_ctx->stream->signal, 1); 2555 2556 } 2557 2558 dc->hwss.enable_stream(pipe_ctx); 2559 2560 /* Set DPS PPS SDP (AKA "info frames") */ 2561 if (pipe_ctx->stream->timing.flags.DSC) { 2562 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2563 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2564 dp_set_dsc_on_rx(pipe_ctx, true); 2565 link_set_dsc_pps_packet(pipe_ctx, true, true); 2566 } 2567 } 2568 2569 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2570 allocate_usb4_bandwidth(pipe_ctx->stream); 2571 2572 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2573 allocate_mst_payload(pipe_ctx); 2574 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2575 dp_is_128b_132b_signal(pipe_ctx)) 2576 update_sst_payload(pipe_ctx, true); 2577 2578 dc->hwss.unblank_stream(pipe_ctx, 2579 &pipe_ctx->stream->link->cur_link_settings); 2580 2581 if (stream->sink_patches.delay_ignore_msa > 0) 2582 msleep(stream->sink_patches.delay_ignore_msa); 2583 2584 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2585 enable_stream_features(pipe_ctx); 2586 update_psp_stream_config(pipe_ctx, false); 2587 2588 dc->hwss.enable_audio_stream(pipe_ctx); 2589 2590 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2591 set_avmute(pipe_ctx, false); 2592 } 2593 } 2594