1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_fpga.h" 42 #include "accessories/link_dp_trace.h" 43 #include "protocols/link_dpcd.h" 44 #include "protocols/link_ddc.h" 45 #include "protocols/link_hpd.h" 46 #include "protocols/link_dp_phy.h" 47 #include "protocols/link_dp_capability.h" 48 #include "protocols/link_dp_training.h" 49 #include "protocols/link_edp_panel_control.h" 50 #include "protocols/link_dp_dpia_bw.h" 51 52 #include "dm_helpers.h" 53 #include "link_enc_cfg.h" 54 #include "resource.h" 55 #include "dsc.h" 56 #include "dccg.h" 57 #include "clk_mgr.h" 58 #include "atomfirmware.h" 59 #define DC_LOGGER_INIT(logger) 60 61 #define LINK_INFO(...) \ 62 DC_LOG_HW_HOTPLUG( \ 63 __VA_ARGS__) 64 65 #define RETIMER_REDRIVER_INFO(...) \ 66 DC_LOG_RETIMER_REDRIVER( \ 67 __VA_ARGS__) 68 #include "dc/dcn30/dcn30_vpg.h" 69 70 #define MAX_MTP_SLOT_COUNT 64 71 #define LINK_TRAINING_ATTEMPTS 4 72 #define PEAK_FACTOR_X1000 1006 73 74 void link_blank_all_dp_displays(struct dc *dc) 75 { 76 unsigned int i; 77 uint8_t dpcd_power_state = '\0'; 78 enum dc_status status = DC_ERROR_UNEXPECTED; 79 80 for (i = 0; i < dc->link_count; i++) { 81 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 82 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 83 continue; 84 85 /* DP 2.0 spec requires that we read LTTPR caps first */ 86 dp_retrieve_lttpr_cap(dc->links[i]); 87 /* if any of the displays are lit up turn them off */ 88 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 89 &dpcd_power_state, sizeof(dpcd_power_state)); 90 91 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 92 link_blank_dp_stream(dc->links[i], true); 93 } 94 95 } 96 97 void link_blank_all_edp_displays(struct dc *dc) 98 { 99 unsigned int i; 100 uint8_t dpcd_power_state = '\0'; 101 enum dc_status status = DC_ERROR_UNEXPECTED; 102 103 for (i = 0; i < dc->link_count; i++) { 104 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 105 (!dc->links[i]->edp_sink_present)) 106 continue; 107 108 /* if any of the displays are lit up turn them off */ 109 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 110 &dpcd_power_state, sizeof(dpcd_power_state)); 111 112 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 113 link_blank_dp_stream(dc->links[i], true); 114 } 115 } 116 117 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 118 { 119 unsigned int j; 120 struct dc *dc = link->ctx->dc; 121 enum signal_type signal = link->connector_signal; 122 123 if ((signal == SIGNAL_TYPE_EDP) || 124 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 125 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 126 link->link_enc->funcs->get_dig_frontend && 127 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 128 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 129 130 if (fe != ENGINE_ID_UNKNOWN) 131 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 132 if (fe == dc->res_pool->stream_enc[j]->id) { 133 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 134 dc->res_pool->stream_enc[j]); 135 break; 136 } 137 } 138 } 139 140 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 141 dpcd_write_rx_power_ctrl(link, false); 142 } 143 } 144 145 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 146 { 147 struct pipe_ctx *pipes[MAX_PIPES]; 148 struct dc_state *state = link->dc->current_state; 149 uint8_t count; 150 int i; 151 struct dc_stream_update stream_update; 152 bool dpms_off = true; 153 struct link_resource link_res = {0}; 154 155 memset(&stream_update, 0, sizeof(stream_update)); 156 stream_update.dpms_off = &dpms_off; 157 158 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 159 160 for (i = 0; i < count; i++) { 161 stream_update.stream = pipes[i]->stream; 162 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 163 pipes[i]->stream, &stream_update, 164 state); 165 } 166 167 /* link can be also enabled by vbios. In this case it is not recorded 168 * in pipe_ctx. Disable link phy here to make sure it is completely off 169 */ 170 dp_disable_link_phy(link, &link_res, link->connector_signal); 171 } 172 173 void link_resume(struct dc_link *link) 174 { 175 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 176 program_hpd_filter(link); 177 } 178 179 /* This function returns true if the pipe is used to feed video signal directly 180 * to the link. 181 */ 182 static bool is_master_pipe_for_link(const struct dc_link *link, 183 const struct pipe_ctx *pipe) 184 { 185 return (pipe->stream && 186 pipe->stream->link && 187 pipe->stream->link == link && 188 pipe->top_pipe == NULL && 189 pipe->prev_odm_pipe == NULL); 190 } 191 192 /* 193 * This function finds all master pipes feeding to a given link with dpms set to 194 * on in given dc state. 195 */ 196 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 197 struct dc_state *state, 198 uint8_t *count, 199 struct pipe_ctx *pipes[MAX_PIPES]) 200 { 201 int i; 202 struct pipe_ctx *pipe = NULL; 203 204 *count = 0; 205 for (i = 0; i < MAX_PIPES; i++) { 206 pipe = &state->res_ctx.pipe_ctx[i]; 207 208 if (is_master_pipe_for_link(link, pipe) && 209 pipe->stream->dpms_off == false) { 210 pipes[(*count)++] = pipe; 211 } 212 } 213 } 214 215 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 216 enum engine_id eng_id, 217 struct ext_hdmi_settings *settings) 218 { 219 bool result = false; 220 int i = 0; 221 struct integrated_info *integrated_info = 222 pipe_ctx->stream->ctx->dc_bios->integrated_info; 223 224 if (integrated_info == NULL) 225 return false; 226 227 /* 228 * Get retimer settings from sbios for passing SI eye test for DCE11 229 * The setting values are varied based on board revision and port id 230 * Therefore the setting values of each ports is passed by sbios. 231 */ 232 233 // Check if current bios contains ext Hdmi settings 234 if (integrated_info->gpu_cap_info & 0x20) { 235 switch (eng_id) { 236 case ENGINE_ID_DIGA: 237 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 238 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 240 memmove(settings->reg_settings, 241 integrated_info->dp0_ext_hdmi_reg_settings, 242 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 243 memmove(settings->reg_settings_6g, 244 integrated_info->dp0_ext_hdmi_6g_reg_settings, 245 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 246 result = true; 247 break; 248 case ENGINE_ID_DIGB: 249 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 250 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 252 memmove(settings->reg_settings, 253 integrated_info->dp1_ext_hdmi_reg_settings, 254 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 255 memmove(settings->reg_settings_6g, 256 integrated_info->dp1_ext_hdmi_6g_reg_settings, 257 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 258 result = true; 259 break; 260 case ENGINE_ID_DIGC: 261 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 262 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 264 memmove(settings->reg_settings, 265 integrated_info->dp2_ext_hdmi_reg_settings, 266 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 267 memmove(settings->reg_settings_6g, 268 integrated_info->dp2_ext_hdmi_6g_reg_settings, 269 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 270 result = true; 271 break; 272 case ENGINE_ID_DIGD: 273 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 274 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 276 memmove(settings->reg_settings, 277 integrated_info->dp3_ext_hdmi_reg_settings, 278 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 279 memmove(settings->reg_settings_6g, 280 integrated_info->dp3_ext_hdmi_6g_reg_settings, 281 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 282 result = true; 283 break; 284 default: 285 break; 286 } 287 288 if (result == true) { 289 // Validate settings from bios integrated info table 290 if (settings->slv_addr == 0) 291 return false; 292 if (settings->reg_num > 9) 293 return false; 294 if (settings->reg_num_6g > 3) 295 return false; 296 297 for (i = 0; i < settings->reg_num; i++) { 298 if (settings->reg_settings[i].i2c_reg_index > 0x20) 299 return false; 300 } 301 302 for (i = 0; i < settings->reg_num_6g; i++) { 303 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 304 return false; 305 } 306 } 307 } 308 309 return result; 310 } 311 312 static bool write_i2c(struct pipe_ctx *pipe_ctx, 313 uint8_t address, uint8_t *buffer, uint32_t length) 314 { 315 struct i2c_command cmd = {0}; 316 struct i2c_payload payload = {0}; 317 318 memset(&payload, 0, sizeof(payload)); 319 memset(&cmd, 0, sizeof(cmd)); 320 321 cmd.number_of_payloads = 1; 322 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 323 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 324 325 payload.address = address; 326 payload.data = buffer; 327 payload.length = length; 328 payload.write = true; 329 cmd.payloads = &payload; 330 331 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 332 pipe_ctx->stream->link, &cmd)) 333 return true; 334 335 return false; 336 } 337 338 static void write_i2c_retimer_setting( 339 struct pipe_ctx *pipe_ctx, 340 bool is_vga_mode, 341 bool is_over_340mhz, 342 struct ext_hdmi_settings *settings) 343 { 344 uint8_t slave_address = (settings->slv_addr >> 1); 345 uint8_t buffer[2]; 346 const uint8_t apply_rx_tx_change = 0x4; 347 uint8_t offset = 0xA; 348 uint8_t value = 0; 349 int i = 0; 350 bool i2c_success = false; 351 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 352 353 memset(&buffer, 0, sizeof(buffer)); 354 355 /* Start Ext-Hdmi programming*/ 356 357 for (i = 0; i < settings->reg_num; i++) { 358 /* Apply 3G settings */ 359 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 360 361 buffer[0] = settings->reg_settings[i].i2c_reg_index; 362 buffer[1] = settings->reg_settings[i].i2c_reg_val; 363 i2c_success = write_i2c(pipe_ctx, slave_address, 364 buffer, sizeof(buffer)); 365 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 366 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 367 slave_address, buffer[0], buffer[1], i2c_success?1:0); 368 369 if (!i2c_success) 370 goto i2c_write_fail; 371 372 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 373 * needs to be set to 1 on every 0xA-0xC write. 374 */ 375 if (settings->reg_settings[i].i2c_reg_index == 0xA || 376 settings->reg_settings[i].i2c_reg_index == 0xB || 377 settings->reg_settings[i].i2c_reg_index == 0xC) { 378 379 /* Query current value from offset 0xA */ 380 if (settings->reg_settings[i].i2c_reg_index == 0xA) 381 value = settings->reg_settings[i].i2c_reg_val; 382 else { 383 i2c_success = 384 link_query_ddc_data( 385 pipe_ctx->stream->link->ddc, 386 slave_address, &offset, 1, &value, 1); 387 if (!i2c_success) 388 goto i2c_write_fail; 389 } 390 391 buffer[0] = offset; 392 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 393 buffer[1] = value | apply_rx_tx_change; 394 i2c_success = write_i2c(pipe_ctx, slave_address, 395 buffer, sizeof(buffer)); 396 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 397 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 398 slave_address, buffer[0], buffer[1], i2c_success?1:0); 399 if (!i2c_success) 400 goto i2c_write_fail; 401 } 402 } 403 } 404 405 /* Apply 3G settings */ 406 if (is_over_340mhz) { 407 for (i = 0; i < settings->reg_num_6g; i++) { 408 /* Apply 3G settings */ 409 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 410 411 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 412 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 413 i2c_success = write_i2c(pipe_ctx, slave_address, 414 buffer, sizeof(buffer)); 415 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 416 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 417 slave_address, buffer[0], buffer[1], i2c_success?1:0); 418 419 if (!i2c_success) 420 goto i2c_write_fail; 421 422 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 423 * needs to be set to 1 on every 0xA-0xC write. 424 */ 425 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 427 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 428 429 /* Query current value from offset 0xA */ 430 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 431 value = settings->reg_settings_6g[i].i2c_reg_val; 432 else { 433 i2c_success = 434 link_query_ddc_data( 435 pipe_ctx->stream->link->ddc, 436 slave_address, &offset, 1, &value, 1); 437 if (!i2c_success) 438 goto i2c_write_fail; 439 } 440 441 buffer[0] = offset; 442 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 443 buffer[1] = value | apply_rx_tx_change; 444 i2c_success = write_i2c(pipe_ctx, slave_address, 445 buffer, sizeof(buffer)); 446 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 447 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 448 slave_address, buffer[0], buffer[1], i2c_success?1:0); 449 if (!i2c_success) 450 goto i2c_write_fail; 451 } 452 } 453 } 454 } 455 456 if (is_vga_mode) { 457 /* Program additional settings if using 640x480 resolution */ 458 459 /* Write offset 0xFF to 0x01 */ 460 buffer[0] = 0xff; 461 buffer[1] = 0x01; 462 i2c_success = write_i2c(pipe_ctx, slave_address, 463 buffer, sizeof(buffer)); 464 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 465 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 466 slave_address, buffer[0], buffer[1], i2c_success?1:0); 467 if (!i2c_success) 468 goto i2c_write_fail; 469 470 /* Write offset 0x00 to 0x23 */ 471 buffer[0] = 0x00; 472 buffer[1] = 0x23; 473 i2c_success = write_i2c(pipe_ctx, slave_address, 474 buffer, sizeof(buffer)); 475 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 476 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 477 slave_address, buffer[0], buffer[1], i2c_success?1:0); 478 if (!i2c_success) 479 goto i2c_write_fail; 480 481 /* Write offset 0xff to 0x00 */ 482 buffer[0] = 0xff; 483 buffer[1] = 0x00; 484 i2c_success = write_i2c(pipe_ctx, slave_address, 485 buffer, sizeof(buffer)); 486 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 487 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 488 slave_address, buffer[0], buffer[1], i2c_success?1:0); 489 if (!i2c_success) 490 goto i2c_write_fail; 491 492 } 493 494 return; 495 496 i2c_write_fail: 497 DC_LOG_DEBUG("Set retimer failed"); 498 } 499 500 static void write_i2c_default_retimer_setting( 501 struct pipe_ctx *pipe_ctx, 502 bool is_vga_mode, 503 bool is_over_340mhz) 504 { 505 uint8_t slave_address = (0xBA >> 1); 506 uint8_t buffer[2]; 507 bool i2c_success = false; 508 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 509 510 memset(&buffer, 0, sizeof(buffer)); 511 512 /* Program Slave Address for tuning single integrity */ 513 /* Write offset 0x0A to 0x13 */ 514 buffer[0] = 0x0A; 515 buffer[1] = 0x13; 516 i2c_success = write_i2c(pipe_ctx, slave_address, 517 buffer, sizeof(buffer)); 518 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 519 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 520 slave_address, buffer[0], buffer[1], i2c_success?1:0); 521 if (!i2c_success) 522 goto i2c_write_fail; 523 524 /* Write offset 0x0A to 0x17 */ 525 buffer[0] = 0x0A; 526 buffer[1] = 0x17; 527 i2c_success = write_i2c(pipe_ctx, slave_address, 528 buffer, sizeof(buffer)); 529 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 530 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 531 slave_address, buffer[0], buffer[1], i2c_success?1:0); 532 if (!i2c_success) 533 goto i2c_write_fail; 534 535 /* Write offset 0x0B to 0xDA or 0xD8 */ 536 buffer[0] = 0x0B; 537 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 538 i2c_success = write_i2c(pipe_ctx, slave_address, 539 buffer, sizeof(buffer)); 540 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 541 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 542 slave_address, buffer[0], buffer[1], i2c_success?1:0); 543 if (!i2c_success) 544 goto i2c_write_fail; 545 546 /* Write offset 0x0A to 0x17 */ 547 buffer[0] = 0x0A; 548 buffer[1] = 0x17; 549 i2c_success = write_i2c(pipe_ctx, slave_address, 550 buffer, sizeof(buffer)); 551 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 552 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 553 slave_address, buffer[0], buffer[1], i2c_success?1:0); 554 if (!i2c_success) 555 goto i2c_write_fail; 556 557 /* Write offset 0x0C to 0x1D or 0x91 */ 558 buffer[0] = 0x0C; 559 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 560 i2c_success = write_i2c(pipe_ctx, slave_address, 561 buffer, sizeof(buffer)); 562 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 563 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 564 slave_address, buffer[0], buffer[1], i2c_success?1:0); 565 if (!i2c_success) 566 goto i2c_write_fail; 567 568 /* Write offset 0x0A to 0x17 */ 569 buffer[0] = 0x0A; 570 buffer[1] = 0x17; 571 i2c_success = write_i2c(pipe_ctx, slave_address, 572 buffer, sizeof(buffer)); 573 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 574 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 575 slave_address, buffer[0], buffer[1], i2c_success?1:0); 576 if (!i2c_success) 577 goto i2c_write_fail; 578 579 580 if (is_vga_mode) { 581 /* Program additional settings if using 640x480 resolution */ 582 583 /* Write offset 0xFF to 0x01 */ 584 buffer[0] = 0xff; 585 buffer[1] = 0x01; 586 i2c_success = write_i2c(pipe_ctx, slave_address, 587 buffer, sizeof(buffer)); 588 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 589 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 590 slave_address, buffer[0], buffer[1], i2c_success?1:0); 591 if (!i2c_success) 592 goto i2c_write_fail; 593 594 /* Write offset 0x00 to 0x23 */ 595 buffer[0] = 0x00; 596 buffer[1] = 0x23; 597 i2c_success = write_i2c(pipe_ctx, slave_address, 598 buffer, sizeof(buffer)); 599 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 600 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 601 slave_address, buffer[0], buffer[1], i2c_success?1:0); 602 if (!i2c_success) 603 goto i2c_write_fail; 604 605 /* Write offset 0xff to 0x00 */ 606 buffer[0] = 0xff; 607 buffer[1] = 0x00; 608 i2c_success = write_i2c(pipe_ctx, slave_address, 609 buffer, sizeof(buffer)); 610 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 611 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 612 slave_address, buffer[0], buffer[1], i2c_success?1:0); 613 if (!i2c_success) 614 goto i2c_write_fail; 615 } 616 617 return; 618 619 i2c_write_fail: 620 DC_LOG_DEBUG("Set default retimer failed"); 621 } 622 623 static void write_i2c_redriver_setting( 624 struct pipe_ctx *pipe_ctx, 625 bool is_over_340mhz) 626 { 627 uint8_t slave_address = (0xF0 >> 1); 628 uint8_t buffer[16]; 629 bool i2c_success = false; 630 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 631 632 memset(&buffer, 0, sizeof(buffer)); 633 634 // Program Slave Address for tuning single integrity 635 buffer[3] = 0x4E; 636 buffer[4] = 0x4E; 637 buffer[5] = 0x4E; 638 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 639 640 i2c_success = write_i2c(pipe_ctx, slave_address, 641 buffer, sizeof(buffer)); 642 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 643 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 644 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 645 i2c_success = %d\n", 646 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 647 648 if (!i2c_success) 649 DC_LOG_DEBUG("Set redriver failed"); 650 } 651 652 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 653 { 654 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 655 struct link_encoder *link_enc = NULL; 656 struct cp_psp_stream_config config = {0}; 657 enum dp_panel_mode panel_mode = 658 dp_get_panel_mode(pipe_ctx->stream->link); 659 660 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 661 return; 662 663 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 664 ASSERT(link_enc); 665 if (link_enc == NULL) 666 return; 667 668 /* otg instance */ 669 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 670 671 /* dig front end */ 672 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 673 674 /* stream encoder index */ 675 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 676 if (dp_is_128b_132b_signal(pipe_ctx)) 677 config.stream_enc_idx = 678 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 679 680 /* dig back end */ 681 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 682 683 /* link encoder index */ 684 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 685 if (dp_is_128b_132b_signal(pipe_ctx)) 686 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 687 688 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 689 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 690 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 691 else 692 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 693 694 695 /* phy index */ 696 config.phy_idx = resource_transmitter_to_phy_idx( 697 pipe_ctx->stream->link->dc, link_enc->transmitter); 698 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 699 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 700 config.phy_idx = 0; 701 702 /* stream properties */ 703 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 704 config.mst_enabled = (pipe_ctx->stream->signal == 705 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 706 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 707 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 708 1 : 0; 709 config.dpms_off = dpms_off; 710 711 /* dm stream context */ 712 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 713 714 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 715 } 716 717 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 718 { 719 struct dc *dc = pipe_ctx->stream->ctx->dc; 720 721 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 722 return; 723 724 dc->hwss.set_avmute(pipe_ctx, enable); 725 } 726 727 static void enable_mst_on_sink(struct dc_link *link, bool enable) 728 { 729 unsigned char mstmCntl; 730 731 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 732 if (enable) 733 mstmCntl |= DP_MST_EN; 734 else 735 mstmCntl &= (~DP_MST_EN); 736 737 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 738 } 739 740 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 741 struct dsc_optc_config *config) 742 { 743 uint32_t precision = 1 << 28; 744 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 745 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 746 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 747 DC_LOGGER_INIT(dsc->ctx->logger); 748 749 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 750 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 751 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 752 */ 753 ll_bytes_per_pix_fraq *= 10000000; 754 ll_bytes_per_pix_fraq /= precision; 755 756 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 757 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 758 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 759 DC_LOG_DSC("\tslice_width %d", config->slice_width); 760 } 761 762 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 763 { 764 struct dc *dc = pipe_ctx->stream->ctx->dc; 765 struct dc_stream_state *stream = pipe_ctx->stream; 766 bool result = false; 767 768 if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 769 result = true; 770 else 771 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 772 return result; 773 } 774 775 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 776 * i.e. after dp_enable_dsc_on_rx() had been called 777 */ 778 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 779 { 780 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 781 struct dc *dc = pipe_ctx->stream->ctx->dc; 782 struct dc_stream_state *stream = pipe_ctx->stream; 783 struct pipe_ctx *odm_pipe; 784 int opp_cnt = 1; 785 DC_LOGGER_INIT(dsc->ctx->logger); 786 787 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 788 opp_cnt++; 789 790 if (enable) { 791 struct dsc_config dsc_cfg; 792 struct dsc_optc_config dsc_optc_cfg; 793 enum optc_dsc_mode optc_dsc_mode; 794 795 /* Enable DSC hw block */ 796 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 797 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 798 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 799 dsc_cfg.color_depth = stream->timing.display_color_depth; 800 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 801 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 802 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 803 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 804 805 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 806 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 807 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 808 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 809 810 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 811 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 812 } 813 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 814 dsc_cfg.pic_width *= opp_cnt; 815 816 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 817 818 /* Enable DSC in encoder */ 819 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) 820 && !dp_is_128b_132b_signal(pipe_ctx)) { 821 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 822 dsc_optc_config_log(dsc, &dsc_optc_cfg); 823 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 824 optc_dsc_mode, 825 dsc_optc_cfg.bytes_per_pixel, 826 dsc_optc_cfg.slice_width); 827 828 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 829 } 830 831 /* Enable DSC in OPTC */ 832 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 833 dsc_optc_config_log(dsc, &dsc_optc_cfg); 834 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 835 optc_dsc_mode, 836 dsc_optc_cfg.bytes_per_pixel, 837 dsc_optc_cfg.slice_width); 838 } else { 839 /* disable DSC in OPTC */ 840 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 841 pipe_ctx->stream_res.tg, 842 OPTC_DSC_DISABLED, 0, 0); 843 844 /* disable DSC in stream encoder */ 845 if (dc_is_dp_signal(stream->signal)) { 846 if (dp_is_128b_132b_signal(pipe_ctx)) 847 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 848 pipe_ctx->stream_res.hpo_dp_stream_enc, 849 false, 850 NULL, 851 true); 852 else if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 853 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 854 pipe_ctx->stream_res.stream_enc, 855 OPTC_DSC_DISABLED, 0, 0); 856 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 857 pipe_ctx->stream_res.stream_enc, false, NULL, true); 858 } 859 } 860 861 /* disable DSC block */ 862 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 863 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 864 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 865 } 866 } 867 868 /* 869 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 870 * hence PPS info packet update need to use frame update instead of immediate update. 871 * Added parameter immediate_update for this purpose. 872 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 873 * which is the only place where a "false" would be passed in for param immediate_update. 874 * 875 * immediate_update is only applicable when DSC is enabled. 876 */ 877 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 878 { 879 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 880 struct dc_stream_state *stream = pipe_ctx->stream; 881 DC_LOGGER_INIT(dsc->ctx->logger); 882 883 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 884 return false; 885 886 if (enable) { 887 struct dsc_config dsc_cfg; 888 uint8_t dsc_packed_pps[128]; 889 890 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 891 memset(dsc_packed_pps, 0, 128); 892 893 /* Enable DSC hw block */ 894 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 895 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 896 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 897 dsc_cfg.color_depth = stream->timing.display_color_depth; 898 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 899 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 900 901 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 902 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 903 if (dc_is_dp_signal(stream->signal)) { 904 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 905 if (dp_is_128b_132b_signal(pipe_ctx)) 906 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 907 pipe_ctx->stream_res.hpo_dp_stream_enc, 908 true, 909 &dsc_packed_pps[0], 910 immediate_update); 911 else 912 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 913 pipe_ctx->stream_res.stream_enc, 914 true, 915 &dsc_packed_pps[0], 916 immediate_update); 917 } 918 } else { 919 /* disable DSC PPS in stream encoder */ 920 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 921 if (dc_is_dp_signal(stream->signal)) { 922 if (dp_is_128b_132b_signal(pipe_ctx)) 923 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 924 pipe_ctx->stream_res.hpo_dp_stream_enc, 925 false, 926 NULL, 927 true); 928 else 929 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 930 pipe_ctx->stream_res.stream_enc, false, NULL, true); 931 } 932 } 933 934 return true; 935 } 936 937 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 938 { 939 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 940 bool result = false; 941 942 if (!pipe_ctx->stream->timing.flags.DSC) 943 goto out; 944 if (!dsc) 945 goto out; 946 947 if (enable) { 948 { 949 link_set_dsc_on_stream(pipe_ctx, true); 950 result = true; 951 } 952 } else { 953 dp_set_dsc_on_rx(pipe_ctx, false); 954 link_set_dsc_on_stream(pipe_ctx, false); 955 result = true; 956 } 957 out: 958 return result; 959 } 960 961 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 962 { 963 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 964 965 if (!pipe_ctx->stream->timing.flags.DSC) 966 return false; 967 if (!dsc) 968 return false; 969 970 link_set_dsc_on_stream(pipe_ctx, true); 971 link_set_dsc_pps_packet(pipe_ctx, true, false); 972 return true; 973 } 974 975 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 976 { 977 struct dc_stream_state *stream = pipe_ctx->stream; 978 979 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 980 struct dc_link *link = stream->link; 981 union down_spread_ctrl old_downspread; 982 union down_spread_ctrl new_downspread; 983 984 memset(&old_downspread, 0, sizeof(old_downspread)); 985 986 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 987 &old_downspread.raw, sizeof(old_downspread)); 988 989 new_downspread.raw = old_downspread.raw; 990 991 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 992 (stream->ignore_msa_timing_param) ? 1 : 0; 993 994 if (new_downspread.raw != old_downspread.raw) { 995 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 996 &new_downspread.raw, sizeof(new_downspread)); 997 } 998 999 } else { 1000 dm_helpers_mst_enable_stream_features(stream); 1001 } 1002 } 1003 1004 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1005 { 1006 const uint32_t VCP_Y_PRECISION = 1000; 1007 uint64_t vcp_x, vcp_y; 1008 DC_LOGGER_INIT(link->ctx->logger); 1009 1010 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1011 avg_time_slots_per_mtp = dc_fixpt_add( 1012 avg_time_slots_per_mtp, 1013 dc_fixpt_from_fraction( 1014 1, 1015 2*VCP_Y_PRECISION)); 1016 1017 vcp_x = dc_fixpt_floor( 1018 avg_time_slots_per_mtp); 1019 vcp_y = dc_fixpt_floor( 1020 dc_fixpt_mul_int( 1021 dc_fixpt_sub_int( 1022 avg_time_slots_per_mtp, 1023 dc_fixpt_floor( 1024 avg_time_slots_per_mtp)), 1025 VCP_Y_PRECISION)); 1026 1027 1028 if (link->type == dc_connection_mst_branch) 1029 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1030 "X: %llu " 1031 "Y: %llu/%d", 1032 vcp_x, 1033 vcp_y, 1034 VCP_Y_PRECISION); 1035 else 1036 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1037 "X: %llu " 1038 "Y: %llu/%d", 1039 vcp_x, 1040 vcp_y, 1041 VCP_Y_PRECISION); 1042 } 1043 1044 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1045 { 1046 struct fixed31_32 mbytes_per_sec; 1047 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1048 &stream->link->cur_link_settings); 1049 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1050 1051 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1052 1053 return dc_fixpt_div_int(mbytes_per_sec, 54); 1054 } 1055 1056 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1057 { 1058 struct fixed31_32 peak_kbps; 1059 uint32_t numerator = 0; 1060 uint32_t denominator = 1; 1061 1062 /* 1063 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 1064 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1065 * common multiplier to render an integer PBN for all link rate/lane 1066 * counts combinations 1067 * calculate 1068 * peak_kbps *= (1006/1000) 1069 * peak_kbps *= (64/54) 1070 * peak_kbps *= 8 convert to bytes 1071 */ 1072 1073 numerator = 64 * PEAK_FACTOR_X1000; 1074 denominator = 54 * 8 * 1000 * 1000; 1075 kbps *= numerator; 1076 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1077 1078 return peak_kbps; 1079 } 1080 1081 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1082 { 1083 uint64_t kbps; 1084 1085 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); 1086 return get_pbn_from_bw_in_kbps(kbps); 1087 } 1088 1089 1090 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1091 static void get_lane_status( 1092 struct dc_link *link, 1093 uint32_t lane_count, 1094 union lane_status *status, 1095 union lane_align_status_updated *status_updated) 1096 { 1097 unsigned int lane; 1098 uint8_t dpcd_buf[3] = {0}; 1099 1100 if (status == NULL || status_updated == NULL) { 1101 return; 1102 } 1103 1104 core_link_read_dpcd( 1105 link, 1106 DP_LANE0_1_STATUS, 1107 dpcd_buf, 1108 sizeof(dpcd_buf)); 1109 1110 for (lane = 0; lane < lane_count; lane++) { 1111 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1112 } 1113 1114 status_updated->raw = dpcd_buf[2]; 1115 } 1116 1117 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1118 { 1119 /* 1120 * wait for ACT handled 1121 */ 1122 int i; 1123 const int act_retries = 30; 1124 enum act_return_status result = ACT_FAILED; 1125 union payload_table_update_status update_status = {0}; 1126 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1127 union lane_align_status_updated lane_status_updated; 1128 DC_LOGGER_INIT(link->ctx->logger); 1129 1130 if (link->aux_access_disabled) 1131 return true; 1132 for (i = 0; i < act_retries; i++) { 1133 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1134 1135 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1136 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1137 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1138 !dp_is_interlane_aligned(lane_status_updated)) { 1139 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1140 "polling for ACT handled."); 1141 result = ACT_LINK_LOST; 1142 break; 1143 } 1144 core_link_read_dpcd( 1145 link, 1146 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1147 &update_status.raw, 1148 1); 1149 1150 if (update_status.bits.ACT_HANDLED == 1) { 1151 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1152 result = ACT_SUCCESS; 1153 break; 1154 } 1155 1156 fsleep(5000); 1157 } 1158 1159 if (result == ACT_FAILED) { 1160 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1161 "continue on. Something is wrong with the branch."); 1162 } 1163 1164 return (result == ACT_SUCCESS); 1165 } 1166 1167 static void update_mst_stream_alloc_table( 1168 struct dc_link *link, 1169 struct stream_encoder *stream_enc, 1170 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1171 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1172 { 1173 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1174 struct link_mst_stream_allocation *dc_alloc; 1175 1176 int i; 1177 int j; 1178 1179 /* if DRM proposed_table has more than one new payload */ 1180 ASSERT(proposed_table->stream_count - 1181 link->mst_stream_alloc_table.stream_count < 2); 1182 1183 /* copy proposed_table to link, add stream encoder */ 1184 for (i = 0; i < proposed_table->stream_count; i++) { 1185 1186 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1187 dc_alloc = 1188 &link->mst_stream_alloc_table.stream_allocations[j]; 1189 1190 if (dc_alloc->vcp_id == 1191 proposed_table->stream_allocations[i].vcp_id) { 1192 1193 work_table[i] = *dc_alloc; 1194 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1195 break; /* exit j loop */ 1196 } 1197 } 1198 1199 /* new vcp_id */ 1200 if (j == link->mst_stream_alloc_table.stream_count) { 1201 work_table[i].vcp_id = 1202 proposed_table->stream_allocations[i].vcp_id; 1203 work_table[i].slot_count = 1204 proposed_table->stream_allocations[i].slot_count; 1205 work_table[i].stream_enc = stream_enc; 1206 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1207 } 1208 } 1209 1210 /* update link->mst_stream_alloc_table with work_table */ 1211 link->mst_stream_alloc_table.stream_count = 1212 proposed_table->stream_count; 1213 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1214 link->mst_stream_alloc_table.stream_allocations[i] = 1215 work_table[i]; 1216 } 1217 1218 static void remove_stream_from_alloc_table( 1219 struct dc_link *link, 1220 struct stream_encoder *dio_stream_enc, 1221 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1222 { 1223 int i = 0; 1224 struct link_mst_stream_allocation_table *table = 1225 &link->mst_stream_alloc_table; 1226 1227 if (hpo_dp_stream_enc) { 1228 for (; i < table->stream_count; i++) 1229 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1230 break; 1231 } else { 1232 for (; i < table->stream_count; i++) 1233 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1234 break; 1235 } 1236 1237 if (i < table->stream_count) { 1238 i++; 1239 for (; i < table->stream_count; i++) 1240 table->stream_allocations[i-1] = table->stream_allocations[i]; 1241 memset(&table->stream_allocations[table->stream_count-1], 0, 1242 sizeof(struct link_mst_stream_allocation)); 1243 table->stream_count--; 1244 } 1245 } 1246 1247 static enum dc_status deallocate_mst_payload_with_temp_drm_wa( 1248 struct pipe_ctx *pipe_ctx) 1249 { 1250 struct dc_stream_state *stream = pipe_ctx->stream; 1251 struct dc_link *link = stream->link; 1252 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1253 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1254 int i; 1255 bool mst_mode = (link->type == dc_connection_mst_branch); 1256 /* adjust for drm changes*/ 1257 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1258 const struct dc_link_settings empty_link_settings = {0}; 1259 DC_LOGGER_INIT(link->ctx->logger); 1260 1261 if (link_hwss->ext.set_throttled_vcp_size) 1262 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1263 if (link_hwss->ext.set_hblank_min_symbol_width) 1264 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1265 &empty_link_settings, 1266 avg_time_slots_per_mtp); 1267 1268 if (dm_helpers_dp_mst_write_payload_allocation_table( 1269 stream->ctx, 1270 stream, 1271 &proposed_table, 1272 false)) 1273 update_mst_stream_alloc_table( 1274 link, 1275 pipe_ctx->stream_res.stream_enc, 1276 pipe_ctx->stream_res.hpo_dp_stream_enc, 1277 &proposed_table); 1278 else 1279 DC_LOG_WARNING("Failed to update" 1280 "MST allocation table for" 1281 "pipe idx:%d\n", 1282 pipe_ctx->pipe_idx); 1283 1284 DC_LOG_MST("%s" 1285 "stream_count: %d: ", 1286 __func__, 1287 link->mst_stream_alloc_table.stream_count); 1288 1289 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1290 DC_LOG_MST("stream_enc[%d]: %p " 1291 "stream[%d].hpo_dp_stream_enc: %p " 1292 "stream[%d].vcp_id: %d " 1293 "stream[%d].slot_count: %d\n", 1294 i, 1295 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1296 i, 1297 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1298 i, 1299 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1300 i, 1301 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1302 } 1303 1304 if (link_hwss->ext.update_stream_allocation_table == NULL || 1305 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1306 DC_LOG_DEBUG("Unknown encoding format\n"); 1307 return DC_ERROR_UNEXPECTED; 1308 } 1309 1310 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1311 &link->mst_stream_alloc_table); 1312 1313 if (mst_mode) { 1314 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1315 stream->ctx, 1316 stream); 1317 } 1318 1319 dm_helpers_dp_mst_send_payload_allocation( 1320 stream->ctx, 1321 stream, 1322 false); 1323 1324 return DC_OK; 1325 } 1326 1327 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1328 { 1329 struct dc_stream_state *stream = pipe_ctx->stream; 1330 struct dc_link *link = stream->link; 1331 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1332 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1333 int i; 1334 bool mst_mode = (link->type == dc_connection_mst_branch); 1335 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1336 const struct dc_link_settings empty_link_settings = {0}; 1337 DC_LOGGER_INIT(link->ctx->logger); 1338 1339 if (link->dc->debug.temp_mst_deallocation_sequence) 1340 return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); 1341 1342 /* deallocate_mst_payload is called before disable link. When mode or 1343 * disable/enable monitor, new stream is created which is not in link 1344 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1345 * should not done. For new mode set, map_resources will get engine 1346 * for new stream, so stream_enc->id should be validated until here. 1347 */ 1348 1349 /* slot X.Y */ 1350 if (link_hwss->ext.set_throttled_vcp_size) 1351 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1352 if (link_hwss->ext.set_hblank_min_symbol_width) 1353 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1354 &empty_link_settings, 1355 avg_time_slots_per_mtp); 1356 1357 if (mst_mode) { 1358 /* when link is in mst mode, reply on mst manager to remove 1359 * payload 1360 */ 1361 if (dm_helpers_dp_mst_write_payload_allocation_table( 1362 stream->ctx, 1363 stream, 1364 &proposed_table, 1365 false)) 1366 update_mst_stream_alloc_table( 1367 link, 1368 pipe_ctx->stream_res.stream_enc, 1369 pipe_ctx->stream_res.hpo_dp_stream_enc, 1370 &proposed_table); 1371 else 1372 DC_LOG_WARNING("Failed to update" 1373 "MST allocation table for" 1374 "pipe idx:%d\n", 1375 pipe_ctx->pipe_idx); 1376 } else { 1377 /* when link is no longer in mst mode (mst hub unplugged), 1378 * remove payload with default dc logic 1379 */ 1380 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1381 pipe_ctx->stream_res.hpo_dp_stream_enc); 1382 } 1383 1384 DC_LOG_MST("%s" 1385 "stream_count: %d: ", 1386 __func__, 1387 link->mst_stream_alloc_table.stream_count); 1388 1389 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1390 DC_LOG_MST("stream_enc[%d]: %p " 1391 "stream[%d].hpo_dp_stream_enc: %p " 1392 "stream[%d].vcp_id: %d " 1393 "stream[%d].slot_count: %d\n", 1394 i, 1395 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1396 i, 1397 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1398 i, 1399 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1400 i, 1401 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1402 } 1403 1404 /* update mst stream allocation table hardware state */ 1405 if (link_hwss->ext.update_stream_allocation_table == NULL || 1406 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1407 DC_LOG_DEBUG("Unknown encoding format\n"); 1408 return DC_ERROR_UNEXPECTED; 1409 } 1410 1411 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1412 &link->mst_stream_alloc_table); 1413 1414 if (mst_mode) { 1415 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1416 stream->ctx, 1417 stream); 1418 1419 dm_helpers_dp_mst_send_payload_allocation( 1420 stream->ctx, 1421 stream, 1422 false); 1423 } 1424 1425 return DC_OK; 1426 } 1427 1428 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1429 * because stream_encoder is not exposed to dm 1430 */ 1431 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1432 { 1433 struct dc_stream_state *stream = pipe_ctx->stream; 1434 struct dc_link *link = stream->link; 1435 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1436 struct fixed31_32 avg_time_slots_per_mtp; 1437 struct fixed31_32 pbn; 1438 struct fixed31_32 pbn_per_slot; 1439 int i; 1440 enum act_return_status ret; 1441 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1442 DC_LOGGER_INIT(link->ctx->logger); 1443 1444 /* enable_link_dp_mst already check link->enabled_stream_count 1445 * and stream is in link->stream[]. This is called during set mode, 1446 * stream_enc is available. 1447 */ 1448 1449 /* get calculate VC payload for stream: stream_alloc */ 1450 if (dm_helpers_dp_mst_write_payload_allocation_table( 1451 stream->ctx, 1452 stream, 1453 &proposed_table, 1454 true)) 1455 update_mst_stream_alloc_table( 1456 link, 1457 pipe_ctx->stream_res.stream_enc, 1458 pipe_ctx->stream_res.hpo_dp_stream_enc, 1459 &proposed_table); 1460 else 1461 DC_LOG_WARNING("Failed to update" 1462 "MST allocation table for" 1463 "pipe idx:%d\n", 1464 pipe_ctx->pipe_idx); 1465 1466 DC_LOG_MST("%s " 1467 "stream_count: %d: \n ", 1468 __func__, 1469 link->mst_stream_alloc_table.stream_count); 1470 1471 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1472 DC_LOG_MST("stream_enc[%d]: %p " 1473 "stream[%d].hpo_dp_stream_enc: %p " 1474 "stream[%d].vcp_id: %d " 1475 "stream[%d].slot_count: %d\n", 1476 i, 1477 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1478 i, 1479 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1480 i, 1481 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1482 i, 1483 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1484 } 1485 1486 ASSERT(proposed_table.stream_count > 0); 1487 1488 /* program DP source TX for payload */ 1489 if (link_hwss->ext.update_stream_allocation_table == NULL || 1490 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1491 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1492 return DC_ERROR_UNEXPECTED; 1493 } 1494 1495 link_hwss->ext.update_stream_allocation_table(link, 1496 &pipe_ctx->link_res, 1497 &link->mst_stream_alloc_table); 1498 1499 /* send down message */ 1500 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1501 stream->ctx, 1502 stream); 1503 1504 if (ret != ACT_LINK_LOST) { 1505 dm_helpers_dp_mst_send_payload_allocation( 1506 stream->ctx, 1507 stream, 1508 true); 1509 } 1510 1511 /* slot X.Y for only current stream */ 1512 pbn_per_slot = get_pbn_per_slot(stream); 1513 if (pbn_per_slot.value == 0) { 1514 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1515 return DC_UNSUPPORTED_VALUE; 1516 } 1517 pbn = get_pbn_from_timing(pipe_ctx); 1518 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1519 1520 log_vcp_x_y(link, avg_time_slots_per_mtp); 1521 1522 if (link_hwss->ext.set_throttled_vcp_size) 1523 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1524 if (link_hwss->ext.set_hblank_min_symbol_width) 1525 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1526 &link->cur_link_settings, 1527 avg_time_slots_per_mtp); 1528 1529 return DC_OK; 1530 } 1531 1532 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1533 const struct dc_stream_state *stream, 1534 const struct dc_link *link) 1535 { 1536 struct fixed31_32 link_bw_effective = 1537 dc_fixpt_from_int( 1538 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1539 struct fixed31_32 timeslot_bw_effective = 1540 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1541 struct fixed31_32 timing_bw = 1542 dc_fixpt_from_int( 1543 dc_bandwidth_in_kbps_from_timing(&stream->timing)); 1544 struct fixed31_32 avg_time_slots_per_mtp = 1545 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1546 1547 return avg_time_slots_per_mtp; 1548 } 1549 1550 1551 static bool write_128b_132b_sst_payload_allocation_table( 1552 const struct dc_stream_state *stream, 1553 struct dc_link *link, 1554 struct link_mst_stream_allocation_table *proposed_table, 1555 bool allocate) 1556 { 1557 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1558 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1559 bool result = false; 1560 uint8_t req_slot_count = 0; 1561 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1562 union payload_table_update_status update_status = { 0 }; 1563 const uint32_t max_retries = 30; 1564 uint32_t retries = 0; 1565 DC_LOGGER_INIT(link->ctx->logger); 1566 1567 if (allocate) { 1568 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1569 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1570 /// Validation should filter out modes that exceed link BW 1571 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1572 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1573 return false; 1574 } else { 1575 /// Leave req_slot_count = 0 if allocate is false. 1576 } 1577 1578 proposed_table->stream_count = 1; /// Always 1 stream for SST 1579 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1580 proposed_table->stream_allocations[0].vcp_id = vc_id; 1581 1582 if (link->aux_access_disabled) 1583 return true; 1584 1585 /// Write DPCD 2C0 = 1 to start updating 1586 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1587 core_link_write_dpcd( 1588 link, 1589 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1590 &update_status.raw, 1591 1); 1592 1593 /// Program the changes in DPCD 1C0 - 1C2 1594 ASSERT(vc_id == 1); 1595 core_link_write_dpcd( 1596 link, 1597 DP_PAYLOAD_ALLOCATE_SET, 1598 &vc_id, 1599 1); 1600 1601 ASSERT(start_time_slot == 0); 1602 core_link_write_dpcd( 1603 link, 1604 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1605 &start_time_slot, 1606 1); 1607 1608 core_link_write_dpcd( 1609 link, 1610 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1611 &req_slot_count, 1612 1); 1613 1614 /// Poll till DPCD 2C0 read 1 1615 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1616 1617 while (retries < max_retries) { 1618 if (core_link_read_dpcd( 1619 link, 1620 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1621 &update_status.raw, 1622 1) == DC_OK) { 1623 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1624 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1625 result = true; 1626 break; 1627 } 1628 } else { 1629 union dpcd_rev dpcdRev; 1630 1631 if (core_link_read_dpcd( 1632 link, 1633 DP_DPCD_REV, 1634 &dpcdRev.raw, 1635 1) != DC_OK) { 1636 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1637 "of sink while polling payload table " 1638 "updated status bit."); 1639 break; 1640 } 1641 } 1642 retries++; 1643 fsleep(5000); 1644 } 1645 1646 if (!result && retries == max_retries) { 1647 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1648 "continue on. Something is wrong with the branch."); 1649 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1650 } 1651 1652 return result; 1653 } 1654 1655 /* 1656 * Payload allocation/deallocation for SST introduced in DP2.0 1657 */ 1658 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1659 bool allocate) 1660 { 1661 struct dc_stream_state *stream = pipe_ctx->stream; 1662 struct dc_link *link = stream->link; 1663 struct link_mst_stream_allocation_table proposed_table = {0}; 1664 struct fixed31_32 avg_time_slots_per_mtp; 1665 const struct dc_link_settings empty_link_settings = {0}; 1666 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1667 DC_LOGGER_INIT(link->ctx->logger); 1668 1669 /* slot X.Y for SST payload deallocate */ 1670 if (!allocate) { 1671 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1672 1673 log_vcp_x_y(link, avg_time_slots_per_mtp); 1674 1675 if (link_hwss->ext.set_throttled_vcp_size) 1676 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1677 avg_time_slots_per_mtp); 1678 if (link_hwss->ext.set_hblank_min_symbol_width) 1679 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1680 &empty_link_settings, 1681 avg_time_slots_per_mtp); 1682 } 1683 1684 /* calculate VC payload and update branch with new payload allocation table*/ 1685 if (!write_128b_132b_sst_payload_allocation_table( 1686 stream, 1687 link, 1688 &proposed_table, 1689 allocate)) { 1690 DC_LOG_ERROR("SST Update Payload: Failed to update " 1691 "allocation table for " 1692 "pipe idx: %d\n", 1693 pipe_ctx->pipe_idx); 1694 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1695 } 1696 1697 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1698 1699 ASSERT(proposed_table.stream_count == 1); 1700 1701 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1702 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1703 "vcp_id: %d " 1704 "slot_count: %d\n", 1705 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1706 proposed_table.stream_allocations[0].vcp_id, 1707 proposed_table.stream_allocations[0].slot_count); 1708 1709 /* program DP source TX for payload */ 1710 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1711 &proposed_table); 1712 1713 /* poll for ACT handled */ 1714 if (!poll_for_allocation_change_trigger(link)) { 1715 // Failures will result in blackscreen and errors logged 1716 BREAK_TO_DEBUGGER(); 1717 } 1718 1719 /* slot X.Y for SST payload allocate */ 1720 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1721 DP_128b_132b_ENCODING) { 1722 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1723 1724 log_vcp_x_y(link, avg_time_slots_per_mtp); 1725 1726 if (link_hwss->ext.set_throttled_vcp_size) 1727 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1728 avg_time_slots_per_mtp); 1729 if (link_hwss->ext.set_hblank_min_symbol_width) 1730 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1731 &link->cur_link_settings, 1732 avg_time_slots_per_mtp); 1733 } 1734 1735 /* Always return DC_OK. 1736 * If part of sequence fails, log failure(s) and show blackscreen 1737 */ 1738 return DC_OK; 1739 } 1740 1741 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1742 { 1743 struct dc_stream_state *stream = pipe_ctx->stream; 1744 struct dc_link *link = stream->link; 1745 struct fixed31_32 avg_time_slots_per_mtp; 1746 struct fixed31_32 pbn; 1747 struct fixed31_32 pbn_per_slot; 1748 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1749 uint8_t i; 1750 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1751 DC_LOGGER_INIT(link->ctx->logger); 1752 1753 /* decrease throttled vcp size */ 1754 pbn_per_slot = get_pbn_per_slot(stream); 1755 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1756 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1757 1758 if (link_hwss->ext.set_throttled_vcp_size) 1759 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1760 if (link_hwss->ext.set_hblank_min_symbol_width) 1761 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1762 &link->cur_link_settings, 1763 avg_time_slots_per_mtp); 1764 1765 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1766 dm_helpers_dp_mst_send_payload_allocation( 1767 stream->ctx, 1768 stream, 1769 true); 1770 1771 /* notify immediate branch device table update */ 1772 if (dm_helpers_dp_mst_write_payload_allocation_table( 1773 stream->ctx, 1774 stream, 1775 &proposed_table, 1776 true)) { 1777 /* update mst stream allocation table software state */ 1778 update_mst_stream_alloc_table( 1779 link, 1780 pipe_ctx->stream_res.stream_enc, 1781 pipe_ctx->stream_res.hpo_dp_stream_enc, 1782 &proposed_table); 1783 } else { 1784 DC_LOG_WARNING("Failed to update" 1785 "MST allocation table for" 1786 "pipe idx:%d\n", 1787 pipe_ctx->pipe_idx); 1788 } 1789 1790 DC_LOG_MST("%s " 1791 "stream_count: %d: \n ", 1792 __func__, 1793 link->mst_stream_alloc_table.stream_count); 1794 1795 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1796 DC_LOG_MST("stream_enc[%d]: %p " 1797 "stream[%d].hpo_dp_stream_enc: %p " 1798 "stream[%d].vcp_id: %d " 1799 "stream[%d].slot_count: %d\n", 1800 i, 1801 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1802 i, 1803 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1804 i, 1805 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1806 i, 1807 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1808 } 1809 1810 ASSERT(proposed_table.stream_count > 0); 1811 1812 /* update mst stream allocation table hardware state */ 1813 if (link_hwss->ext.update_stream_allocation_table == NULL || 1814 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1815 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1816 return DC_ERROR_UNEXPECTED; 1817 } 1818 1819 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1820 &link->mst_stream_alloc_table); 1821 1822 /* poll for immediate branch device ACT handled */ 1823 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1824 stream->ctx, 1825 stream); 1826 1827 return DC_OK; 1828 } 1829 1830 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1831 { 1832 struct dc_stream_state *stream = pipe_ctx->stream; 1833 struct dc_link *link = stream->link; 1834 struct fixed31_32 avg_time_slots_per_mtp; 1835 struct fixed31_32 pbn; 1836 struct fixed31_32 pbn_per_slot; 1837 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1838 uint8_t i; 1839 enum act_return_status ret; 1840 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1841 DC_LOGGER_INIT(link->ctx->logger); 1842 1843 /* notify immediate branch device table update */ 1844 if (dm_helpers_dp_mst_write_payload_allocation_table( 1845 stream->ctx, 1846 stream, 1847 &proposed_table, 1848 true)) { 1849 /* update mst stream allocation table software state */ 1850 update_mst_stream_alloc_table( 1851 link, 1852 pipe_ctx->stream_res.stream_enc, 1853 pipe_ctx->stream_res.hpo_dp_stream_enc, 1854 &proposed_table); 1855 } 1856 1857 DC_LOG_MST("%s " 1858 "stream_count: %d: \n ", 1859 __func__, 1860 link->mst_stream_alloc_table.stream_count); 1861 1862 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1863 DC_LOG_MST("stream_enc[%d]: %p " 1864 "stream[%d].hpo_dp_stream_enc: %p " 1865 "stream[%d].vcp_id: %d " 1866 "stream[%d].slot_count: %d\n", 1867 i, 1868 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1869 i, 1870 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1871 i, 1872 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1873 i, 1874 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1875 } 1876 1877 ASSERT(proposed_table.stream_count > 0); 1878 1879 /* update mst stream allocation table hardware state */ 1880 if (link_hwss->ext.update_stream_allocation_table == NULL || 1881 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1882 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1883 return DC_ERROR_UNEXPECTED; 1884 } 1885 1886 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1887 &link->mst_stream_alloc_table); 1888 1889 /* poll for immediate branch device ACT handled */ 1890 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1891 stream->ctx, 1892 stream); 1893 1894 if (ret != ACT_LINK_LOST) { 1895 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1896 dm_helpers_dp_mst_send_payload_allocation( 1897 stream->ctx, 1898 stream, 1899 true); 1900 } 1901 1902 /* increase throttled vcp size */ 1903 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1904 pbn_per_slot = get_pbn_per_slot(stream); 1905 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1906 1907 if (link_hwss->ext.set_throttled_vcp_size) 1908 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1909 if (link_hwss->ext.set_hblank_min_symbol_width) 1910 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1911 &link->cur_link_settings, 1912 avg_time_slots_per_mtp); 1913 1914 return DC_OK; 1915 } 1916 1917 static void disable_link_dp(struct dc_link *link, 1918 const struct link_resource *link_res, 1919 enum signal_type signal) 1920 { 1921 struct dc_link_settings link_settings = link->cur_link_settings; 1922 1923 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1924 link->mst_stream_alloc_table.stream_count > 0) 1925 /* disable MST link only when last vc payload is deallocated */ 1926 return; 1927 1928 dp_disable_link_phy(link, link_res, signal); 1929 1930 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1931 if (!link->dc->config.edp_no_power_sequencing) 1932 link->dc->hwss.edp_power_control(link, false); 1933 } 1934 1935 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1936 /* set the sink to SST mode after disabling the link */ 1937 enable_mst_on_sink(link, false); 1938 1939 if (link_dp_get_encoding_format(&link_settings) == 1940 DP_8b_10b_ENCODING) { 1941 dp_set_fec_enable(link, false); 1942 dp_set_fec_ready(link, link_res, false); 1943 } 1944 } 1945 1946 static void disable_link(struct dc_link *link, 1947 const struct link_resource *link_res, 1948 enum signal_type signal) 1949 { 1950 if (dc_is_dp_signal(signal)) { 1951 disable_link_dp(link, link_res, signal); 1952 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1953 link->dc->hwss.disable_link_output(link, link_res, signal); 1954 } 1955 1956 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1957 /* MST disable link only when no stream use the link */ 1958 if (link->mst_stream_alloc_table.stream_count <= 0) 1959 link->link_status.link_active = false; 1960 } else { 1961 link->link_status.link_active = false; 1962 } 1963 } 1964 1965 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1966 { 1967 struct dc_stream_state *stream = pipe_ctx->stream; 1968 struct dc_link *link = stream->link; 1969 enum dc_color_depth display_color_depth; 1970 enum engine_id eng_id; 1971 struct ext_hdmi_settings settings = {0}; 1972 bool is_over_340mhz = false; 1973 bool is_vga_mode = (stream->timing.h_addressable == 640) 1974 && (stream->timing.v_addressable == 480); 1975 struct dc *dc = pipe_ctx->stream->ctx->dc; 1976 1977 if (stream->phy_pix_clk == 0) 1978 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1979 if (stream->phy_pix_clk > 340000) 1980 is_over_340mhz = true; 1981 1982 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1983 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1984 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1985 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1986 /* DP159, Retimer settings */ 1987 eng_id = pipe_ctx->stream_res.stream_enc->id; 1988 1989 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1990 write_i2c_retimer_setting(pipe_ctx, 1991 is_vga_mode, is_over_340mhz, &settings); 1992 } else { 1993 write_i2c_default_retimer_setting(pipe_ctx, 1994 is_vga_mode, is_over_340mhz); 1995 } 1996 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1997 /* PI3EQX1204, Redriver settings */ 1998 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1999 } 2000 } 2001 2002 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2003 write_scdc_data( 2004 stream->link->ddc, 2005 stream->phy_pix_clk, 2006 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2007 2008 memset(&stream->link->cur_link_settings, 0, 2009 sizeof(struct dc_link_settings)); 2010 2011 display_color_depth = stream->timing.display_color_depth; 2012 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2013 display_color_depth = COLOR_DEPTH_888; 2014 2015 dc->hwss.enable_tmds_link_output( 2016 link, 2017 &pipe_ctx->link_res, 2018 pipe_ctx->stream->signal, 2019 pipe_ctx->clock_source->id, 2020 display_color_depth, 2021 stream->phy_pix_clk); 2022 2023 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2024 read_scdc_data(link->ddc); 2025 } 2026 2027 static enum dc_status enable_link_dp(struct dc_state *state, 2028 struct pipe_ctx *pipe_ctx) 2029 { 2030 struct dc_stream_state *stream = pipe_ctx->stream; 2031 enum dc_status status; 2032 bool skip_video_pattern; 2033 struct dc_link *link = stream->link; 2034 const struct dc_link_settings *link_settings = 2035 &pipe_ctx->link_config.dp_link_settings; 2036 bool fec_enable; 2037 int i; 2038 bool apply_seamless_boot_optimization = false; 2039 uint32_t bl_oled_enable_delay = 50; // in ms 2040 uint32_t post_oui_delay = 30; // 30ms 2041 /* Reduce link bandwidth between failed link training attempts. */ 2042 bool do_fallback = false; 2043 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2044 2045 // Increase retry count if attempting DP1.x on FIXED_VS link 2046 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2047 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2048 lt_attempts = 10; 2049 2050 // check for seamless boot 2051 for (i = 0; i < state->stream_count; i++) { 2052 if (state->streams[i]->apply_seamless_boot_optimization) { 2053 apply_seamless_boot_optimization = true; 2054 break; 2055 } 2056 } 2057 2058 /* 2059 * If the link is DP-over-USB4 do the following: 2060 * - Train with fallback when enabling DPIA link. Conventional links are 2061 * trained with fallback during sink detection. 2062 * - Allocate only what the stream needs for bw in Gbps. Inform the CM 2063 * in case stream needs more or less bw from what has been allocated 2064 * earlier at plug time. 2065 */ 2066 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 2067 do_fallback = true; 2068 } 2069 2070 /* 2071 * Temporary w/a to get DP2.0 link rates to work with SST. 2072 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2073 */ 2074 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2075 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2076 link->dc->debug.set_mst_en_for_sst) { 2077 enable_mst_on_sink(link, true); 2078 } 2079 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2080 /*in case it is not on*/ 2081 if (!link->dc->config.edp_no_power_sequencing) 2082 link->dc->hwss.edp_power_control(link, true); 2083 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2084 } 2085 2086 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2087 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2088 } else { 2089 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2090 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2091 if (state->clk_mgr && !apply_seamless_boot_optimization) 2092 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2093 state, false); 2094 } 2095 2096 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2097 dpcd_set_source_specific_data(link); 2098 if (link->dpcd_sink_ext_caps.raw != 0) { 2099 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2100 msleep(post_oui_delay); 2101 } 2102 2103 // similarly, mode switch can cause loss of cable ID 2104 dpcd_write_cable_id_to_dprx(link); 2105 2106 skip_video_pattern = true; 2107 2108 if (link_settings->link_rate == LINK_RATE_LOW) 2109 skip_video_pattern = false; 2110 2111 if (perform_link_training_with_retries(link_settings, 2112 skip_video_pattern, 2113 lt_attempts, 2114 pipe_ctx, 2115 pipe_ctx->stream->signal, 2116 do_fallback)) { 2117 status = DC_OK; 2118 } else { 2119 status = DC_FAIL_DP_LINK_TRAINING; 2120 } 2121 2122 if (link->preferred_training_settings.fec_enable) 2123 fec_enable = *link->preferred_training_settings.fec_enable; 2124 else 2125 fec_enable = true; 2126 2127 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2128 dp_set_fec_enable(link, fec_enable); 2129 2130 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2131 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2132 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2133 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2134 set_default_brightness_aux(link); // TODO: use cached if known 2135 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2136 msleep(bl_oled_enable_delay); 2137 edp_backlight_enable_aux(link, true); 2138 } 2139 2140 return status; 2141 } 2142 2143 static enum dc_status enable_link_edp( 2144 struct dc_state *state, 2145 struct pipe_ctx *pipe_ctx) 2146 { 2147 return enable_link_dp(state, pipe_ctx); 2148 } 2149 2150 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2151 { 2152 struct dc_stream_state *stream = pipe_ctx->stream; 2153 struct dc_link *link = stream->link; 2154 struct dc *dc = stream->ctx->dc; 2155 2156 if (stream->phy_pix_clk == 0) 2157 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2158 2159 memset(&stream->link->cur_link_settings, 0, 2160 sizeof(struct dc_link_settings)); 2161 dc->hwss.enable_lvds_link_output( 2162 link, 2163 &pipe_ctx->link_res, 2164 pipe_ctx->clock_source->id, 2165 stream->phy_pix_clk); 2166 2167 } 2168 2169 static enum dc_status enable_link_dp_mst( 2170 struct dc_state *state, 2171 struct pipe_ctx *pipe_ctx) 2172 { 2173 struct dc_link *link = pipe_ctx->stream->link; 2174 unsigned char mstm_cntl; 2175 2176 /* sink signal type after MST branch is MST. Multiple MST sinks 2177 * share one link. Link DP PHY is enable or training only once. 2178 */ 2179 if (link->link_status.link_active) 2180 return DC_OK; 2181 2182 /* clear payload table */ 2183 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2184 if (mstm_cntl & DP_MST_EN) 2185 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2186 2187 /* to make sure the pending down rep can be processed 2188 * before enabling the link 2189 */ 2190 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2191 2192 /* set the sink to MST mode before enabling the link */ 2193 enable_mst_on_sink(link, true); 2194 2195 return enable_link_dp(state, pipe_ctx); 2196 } 2197 2198 static enum dc_status enable_link( 2199 struct dc_state *state, 2200 struct pipe_ctx *pipe_ctx) 2201 { 2202 enum dc_status status = DC_ERROR_UNEXPECTED; 2203 struct dc_stream_state *stream = pipe_ctx->stream; 2204 struct dc_link *link = stream->link; 2205 2206 /* There's some scenarios where driver is unloaded with display 2207 * still enabled. When driver is reloaded, it may cause a display 2208 * to not light up if there is a mismatch between old and new 2209 * link settings. Need to call disable first before enabling at 2210 * new link settings. 2211 */ 2212 if (link->link_status.link_active) { 2213 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2214 } 2215 2216 switch (pipe_ctx->stream->signal) { 2217 case SIGNAL_TYPE_DISPLAY_PORT: 2218 status = enable_link_dp(state, pipe_ctx); 2219 break; 2220 case SIGNAL_TYPE_EDP: 2221 status = enable_link_edp(state, pipe_ctx); 2222 break; 2223 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2224 status = enable_link_dp_mst(state, pipe_ctx); 2225 msleep(200); 2226 break; 2227 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2228 case SIGNAL_TYPE_DVI_DUAL_LINK: 2229 case SIGNAL_TYPE_HDMI_TYPE_A: 2230 enable_link_hdmi(pipe_ctx); 2231 status = DC_OK; 2232 break; 2233 case SIGNAL_TYPE_LVDS: 2234 enable_link_lvds(pipe_ctx); 2235 status = DC_OK; 2236 break; 2237 case SIGNAL_TYPE_VIRTUAL: 2238 status = DC_OK; 2239 break; 2240 default: 2241 break; 2242 } 2243 2244 if (status == DC_OK) { 2245 pipe_ctx->stream->link->link_status.link_active = true; 2246 } 2247 2248 return status; 2249 } 2250 2251 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2252 { 2253 struct dc *dc = pipe_ctx->stream->ctx->dc; 2254 struct dc_stream_state *stream = pipe_ctx->stream; 2255 struct dc_link *link = stream->sink->link; 2256 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2257 2258 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2259 2260 if (dp_is_128b_132b_signal(pipe_ctx)) 2261 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2262 2263 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2264 2265 if (pipe_ctx->stream->sink) { 2266 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2267 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2268 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2269 pipe_ctx->stream->sink->edid_caps.display_name, 2270 pipe_ctx->stream->signal); 2271 } 2272 } 2273 2274 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2275 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2276 return; 2277 2278 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2279 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2280 set_avmute(pipe_ctx, true); 2281 } 2282 2283 dc->hwss.disable_audio_stream(pipe_ctx); 2284 2285 update_psp_stream_config(pipe_ctx, true); 2286 dc->hwss.blank_stream(pipe_ctx); 2287 2288 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2289 deallocate_mst_payload(pipe_ctx); 2290 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2291 dp_is_128b_132b_signal(pipe_ctx)) 2292 update_sst_payload(pipe_ctx, false); 2293 2294 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2295 struct ext_hdmi_settings settings = {0}; 2296 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2297 2298 unsigned short masked_chip_caps = link->chip_caps & 2299 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2300 //Need to inform that sink is going to use legacy HDMI mode. 2301 write_scdc_data( 2302 link->ddc, 2303 165000,//vbios only handles 165Mhz. 2304 false); 2305 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2306 /* DP159, Retimer settings */ 2307 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2308 write_i2c_retimer_setting(pipe_ctx, 2309 false, false, &settings); 2310 else 2311 write_i2c_default_retimer_setting(pipe_ctx, 2312 false, false); 2313 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2314 /* PI3EQX1204, Redriver settings */ 2315 write_i2c_redriver_setting(pipe_ctx, false); 2316 } 2317 } 2318 2319 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2320 !dp_is_128b_132b_signal(pipe_ctx)) { 2321 2322 /* In DP1.x SST mode, our encoder will go to TPS1 2323 * when link is on but stream is off. 2324 * Disabling link before stream will avoid exposing TPS1 pattern 2325 * during the disable sequence as it will confuse some receivers 2326 * state machine. 2327 * In DP2 or MST mode, our encoder will stay video active 2328 */ 2329 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2330 dc->hwss.disable_stream(pipe_ctx); 2331 } else { 2332 dc->hwss.disable_stream(pipe_ctx); 2333 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2334 } 2335 2336 if (pipe_ctx->stream->timing.flags.DSC) { 2337 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2338 link_set_dsc_enable(pipe_ctx, false); 2339 } 2340 if (dp_is_128b_132b_signal(pipe_ctx)) { 2341 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2342 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2343 } 2344 2345 if (vpg && vpg->funcs->vpg_powerdown) 2346 vpg->funcs->vpg_powerdown(vpg); 2347 } 2348 2349 void link_set_dpms_on( 2350 struct dc_state *state, 2351 struct pipe_ctx *pipe_ctx) 2352 { 2353 struct dc *dc = pipe_ctx->stream->ctx->dc; 2354 struct dc_stream_state *stream = pipe_ctx->stream; 2355 struct dc_link *link = stream->sink->link; 2356 enum dc_status status; 2357 struct link_encoder *link_enc; 2358 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2359 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2360 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2361 2362 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2363 2364 if (dp_is_128b_132b_signal(pipe_ctx)) 2365 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2366 2367 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2368 2369 if (pipe_ctx->stream->sink) { 2370 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2371 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2372 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2373 pipe_ctx->stream->sink->edid_caps.display_name, 2374 pipe_ctx->stream->signal); 2375 } 2376 } 2377 2378 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2379 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2380 return; 2381 2382 link_enc = link_enc_cfg_get_link_enc(link); 2383 ASSERT(link_enc); 2384 2385 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2386 && !dp_is_128b_132b_signal(pipe_ctx)) { 2387 if (link_enc) 2388 link_enc->funcs->setup( 2389 link_enc, 2390 pipe_ctx->stream->signal); 2391 } 2392 2393 pipe_ctx->stream->link->link_state_valid = true; 2394 2395 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2396 if (dp_is_128b_132b_signal(pipe_ctx)) 2397 otg_out_dest = OUT_MUX_HPO_DP; 2398 else 2399 otg_out_dest = OUT_MUX_DIO; 2400 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2401 } 2402 2403 link_hwss->setup_stream_attribute(pipe_ctx); 2404 2405 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2406 bool apply_edp_fast_boot_optimization = 2407 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2408 2409 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2410 2411 // Enable VPG before building infoframe 2412 if (vpg && vpg->funcs->vpg_poweron) 2413 vpg->funcs->vpg_poweron(vpg); 2414 2415 resource_build_info_frame(pipe_ctx); 2416 dc->hwss.update_info_frame(pipe_ctx); 2417 2418 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2419 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2420 2421 /* Do not touch link on seamless boot optimization. */ 2422 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2423 pipe_ctx->stream->dpms_off = false; 2424 2425 /* Still enable stream features & audio on seamless boot for DP external displays */ 2426 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2427 enable_stream_features(pipe_ctx); 2428 dc->hwss.enable_audio_stream(pipe_ctx); 2429 } 2430 2431 update_psp_stream_config(pipe_ctx, false); 2432 return; 2433 } 2434 2435 /* eDP lit up by bios already, no need to enable again. */ 2436 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2437 apply_edp_fast_boot_optimization && 2438 !pipe_ctx->stream->timing.flags.DSC && 2439 !pipe_ctx->next_odm_pipe) { 2440 pipe_ctx->stream->dpms_off = false; 2441 update_psp_stream_config(pipe_ctx, false); 2442 return; 2443 } 2444 2445 if (pipe_ctx->stream->dpms_off) 2446 return; 2447 2448 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2449 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2450 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2451 * will be automatically set at a later time when the video is enabled 2452 * (DP_VID_STREAM_EN = 1). 2453 */ 2454 if (pipe_ctx->stream->timing.flags.DSC) { 2455 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2456 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2457 link_set_dsc_enable(pipe_ctx, true); 2458 2459 } 2460 2461 status = enable_link(state, pipe_ctx); 2462 2463 if (status != DC_OK) { 2464 DC_LOG_WARNING("enabling link %u failed: %d\n", 2465 pipe_ctx->stream->link->link_index, 2466 status); 2467 2468 /* Abort stream enable *unless* the failure was due to 2469 * DP link training - some DP monitors will recover and 2470 * show the stream anyway. But MST displays can't proceed 2471 * without link training. 2472 */ 2473 if (status != DC_FAIL_DP_LINK_TRAINING || 2474 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2475 if (false == stream->link->link_status.link_active) 2476 disable_link(stream->link, &pipe_ctx->link_res, 2477 pipe_ctx->stream->signal); 2478 BREAK_TO_DEBUGGER(); 2479 return; 2480 } 2481 } 2482 2483 /* turn off otg test pattern if enable */ 2484 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2485 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2486 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2487 COLOR_DEPTH_UNDEFINED); 2488 2489 /* This second call is needed to reconfigure the DIG 2490 * as a workaround for the incorrect value being applied 2491 * from transmitter control. 2492 */ 2493 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2494 dp_is_128b_132b_signal(pipe_ctx))) { 2495 if (link_enc) 2496 link_enc->funcs->setup( 2497 link_enc, 2498 pipe_ctx->stream->signal); 2499 } 2500 2501 dc->hwss.enable_stream(pipe_ctx); 2502 2503 /* Set DPS PPS SDP (AKA "info frames") */ 2504 if (pipe_ctx->stream->timing.flags.DSC) { 2505 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2506 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2507 dp_set_dsc_on_rx(pipe_ctx, true); 2508 link_set_dsc_pps_packet(pipe_ctx, true, true); 2509 } 2510 } 2511 2512 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2513 allocate_mst_payload(pipe_ctx); 2514 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2515 dp_is_128b_132b_signal(pipe_ctx)) 2516 update_sst_payload(pipe_ctx, true); 2517 2518 dc->hwss.unblank_stream(pipe_ctx, 2519 &pipe_ctx->stream->link->cur_link_settings); 2520 2521 if (stream->sink_patches.delay_ignore_msa > 0) 2522 msleep(stream->sink_patches.delay_ignore_msa); 2523 2524 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2525 enable_stream_features(pipe_ctx); 2526 update_psp_stream_config(pipe_ctx, false); 2527 2528 dc->hwss.enable_audio_stream(pipe_ctx); 2529 2530 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2531 if (dp_is_128b_132b_signal(pipe_ctx)) 2532 dp_fpga_hpo_enable_link_and_stream(state, pipe_ctx); 2533 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2534 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2535 link_set_dsc_enable(pipe_ctx, true); 2536 } 2537 2538 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2539 set_avmute(pipe_ctx, false); 2540 } 2541 } 2542