1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 144 dpcd_write_rx_power_ctrl(link, false); 145 } 146 } 147 148 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 149 { 150 struct pipe_ctx *pipes[MAX_PIPES]; 151 struct dc_state *state = link->dc->current_state; 152 uint8_t count; 153 int i; 154 struct dc_stream_update stream_update; 155 bool dpms_off = true; 156 struct link_resource link_res = {0}; 157 158 memset(&stream_update, 0, sizeof(stream_update)); 159 stream_update.dpms_off = &dpms_off; 160 161 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 162 163 for (i = 0; i < count; i++) { 164 stream_update.stream = pipes[i]->stream; 165 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 166 pipes[i]->stream, &stream_update, 167 state); 168 } 169 170 /* link can be also enabled by vbios. In this case it is not recorded 171 * in pipe_ctx. Disable link phy here to make sure it is completely off 172 */ 173 dp_disable_link_phy(link, &link_res, link->connector_signal); 174 } 175 176 void link_resume(struct dc_link *link) 177 { 178 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 179 program_hpd_filter(link); 180 } 181 182 /* This function returns true if the pipe is used to feed video signal directly 183 * to the link. 184 */ 185 static bool is_master_pipe_for_link(const struct dc_link *link, 186 const struct pipe_ctx *pipe) 187 { 188 return resource_is_pipe_type(pipe, OTG_MASTER) && 189 pipe->stream->link == link; 190 } 191 192 /* 193 * This function finds all master pipes feeding to a given link with dpms set to 194 * on in given dc state. 195 */ 196 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 197 struct dc_state *state, 198 uint8_t *count, 199 struct pipe_ctx *pipes[MAX_PIPES]) 200 { 201 int i; 202 struct pipe_ctx *pipe = NULL; 203 204 *count = 0; 205 for (i = 0; i < MAX_PIPES; i++) { 206 pipe = &state->res_ctx.pipe_ctx[i]; 207 208 if (is_master_pipe_for_link(link, pipe) && 209 pipe->stream->dpms_off == false) { 210 pipes[(*count)++] = pipe; 211 } 212 } 213 } 214 215 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 216 enum engine_id eng_id, 217 struct ext_hdmi_settings *settings) 218 { 219 bool result = false; 220 int i = 0; 221 struct integrated_info *integrated_info = 222 pipe_ctx->stream->ctx->dc_bios->integrated_info; 223 224 if (integrated_info == NULL) 225 return false; 226 227 /* 228 * Get retimer settings from sbios for passing SI eye test for DCE11 229 * The setting values are varied based on board revision and port id 230 * Therefore the setting values of each ports is passed by sbios. 231 */ 232 233 // Check if current bios contains ext Hdmi settings 234 if (integrated_info->gpu_cap_info & 0x20) { 235 switch (eng_id) { 236 case ENGINE_ID_DIGA: 237 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 238 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 240 memmove(settings->reg_settings, 241 integrated_info->dp0_ext_hdmi_reg_settings, 242 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 243 memmove(settings->reg_settings_6g, 244 integrated_info->dp0_ext_hdmi_6g_reg_settings, 245 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 246 result = true; 247 break; 248 case ENGINE_ID_DIGB: 249 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 250 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 252 memmove(settings->reg_settings, 253 integrated_info->dp1_ext_hdmi_reg_settings, 254 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 255 memmove(settings->reg_settings_6g, 256 integrated_info->dp1_ext_hdmi_6g_reg_settings, 257 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 258 result = true; 259 break; 260 case ENGINE_ID_DIGC: 261 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 262 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 264 memmove(settings->reg_settings, 265 integrated_info->dp2_ext_hdmi_reg_settings, 266 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 267 memmove(settings->reg_settings_6g, 268 integrated_info->dp2_ext_hdmi_6g_reg_settings, 269 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 270 result = true; 271 break; 272 case ENGINE_ID_DIGD: 273 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 274 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 276 memmove(settings->reg_settings, 277 integrated_info->dp3_ext_hdmi_reg_settings, 278 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 279 memmove(settings->reg_settings_6g, 280 integrated_info->dp3_ext_hdmi_6g_reg_settings, 281 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 282 result = true; 283 break; 284 default: 285 break; 286 } 287 288 if (result == true) { 289 // Validate settings from bios integrated info table 290 if (settings->slv_addr == 0) 291 return false; 292 if (settings->reg_num > 9) 293 return false; 294 if (settings->reg_num_6g > 3) 295 return false; 296 297 for (i = 0; i < settings->reg_num; i++) { 298 if (settings->reg_settings[i].i2c_reg_index > 0x20) 299 return false; 300 } 301 302 for (i = 0; i < settings->reg_num_6g; i++) { 303 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 304 return false; 305 } 306 } 307 } 308 309 return result; 310 } 311 312 static bool write_i2c(struct pipe_ctx *pipe_ctx, 313 uint8_t address, uint8_t *buffer, uint32_t length) 314 { 315 struct i2c_command cmd = {0}; 316 struct i2c_payload payload = {0}; 317 318 memset(&payload, 0, sizeof(payload)); 319 memset(&cmd, 0, sizeof(cmd)); 320 321 cmd.number_of_payloads = 1; 322 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 323 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 324 325 payload.address = address; 326 payload.data = buffer; 327 payload.length = length; 328 payload.write = true; 329 cmd.payloads = &payload; 330 331 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 332 pipe_ctx->stream->link, &cmd)) 333 return true; 334 335 return false; 336 } 337 338 static void write_i2c_retimer_setting( 339 struct pipe_ctx *pipe_ctx, 340 bool is_vga_mode, 341 bool is_over_340mhz, 342 struct ext_hdmi_settings *settings) 343 { 344 uint8_t slave_address = (settings->slv_addr >> 1); 345 uint8_t buffer[2]; 346 const uint8_t apply_rx_tx_change = 0x4; 347 uint8_t offset = 0xA; 348 uint8_t value = 0; 349 int i = 0; 350 bool i2c_success = false; 351 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 352 353 memset(&buffer, 0, sizeof(buffer)); 354 355 /* Start Ext-Hdmi programming*/ 356 357 for (i = 0; i < settings->reg_num; i++) { 358 /* Apply 3G settings */ 359 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 360 361 buffer[0] = settings->reg_settings[i].i2c_reg_index; 362 buffer[1] = settings->reg_settings[i].i2c_reg_val; 363 i2c_success = write_i2c(pipe_ctx, slave_address, 364 buffer, sizeof(buffer)); 365 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 366 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 367 slave_address, buffer[0], buffer[1], i2c_success?1:0); 368 369 if (!i2c_success) 370 goto i2c_write_fail; 371 372 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 373 * needs to be set to 1 on every 0xA-0xC write. 374 */ 375 if (settings->reg_settings[i].i2c_reg_index == 0xA || 376 settings->reg_settings[i].i2c_reg_index == 0xB || 377 settings->reg_settings[i].i2c_reg_index == 0xC) { 378 379 /* Query current value from offset 0xA */ 380 if (settings->reg_settings[i].i2c_reg_index == 0xA) 381 value = settings->reg_settings[i].i2c_reg_val; 382 else { 383 i2c_success = 384 link_query_ddc_data( 385 pipe_ctx->stream->link->ddc, 386 slave_address, &offset, 1, &value, 1); 387 if (!i2c_success) 388 goto i2c_write_fail; 389 } 390 391 buffer[0] = offset; 392 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 393 buffer[1] = value | apply_rx_tx_change; 394 i2c_success = write_i2c(pipe_ctx, slave_address, 395 buffer, sizeof(buffer)); 396 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 397 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 398 slave_address, buffer[0], buffer[1], i2c_success?1:0); 399 if (!i2c_success) 400 goto i2c_write_fail; 401 } 402 } 403 } 404 405 /* Apply 3G settings */ 406 if (is_over_340mhz) { 407 for (i = 0; i < settings->reg_num_6g; i++) { 408 /* Apply 3G settings */ 409 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 410 411 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 412 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 413 i2c_success = write_i2c(pipe_ctx, slave_address, 414 buffer, sizeof(buffer)); 415 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 416 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 417 slave_address, buffer[0], buffer[1], i2c_success?1:0); 418 419 if (!i2c_success) 420 goto i2c_write_fail; 421 422 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 423 * needs to be set to 1 on every 0xA-0xC write. 424 */ 425 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 427 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 428 429 /* Query current value from offset 0xA */ 430 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 431 value = settings->reg_settings_6g[i].i2c_reg_val; 432 else { 433 i2c_success = 434 link_query_ddc_data( 435 pipe_ctx->stream->link->ddc, 436 slave_address, &offset, 1, &value, 1); 437 if (!i2c_success) 438 goto i2c_write_fail; 439 } 440 441 buffer[0] = offset; 442 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 443 buffer[1] = value | apply_rx_tx_change; 444 i2c_success = write_i2c(pipe_ctx, slave_address, 445 buffer, sizeof(buffer)); 446 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 447 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 448 slave_address, buffer[0], buffer[1], i2c_success?1:0); 449 if (!i2c_success) 450 goto i2c_write_fail; 451 } 452 } 453 } 454 } 455 456 if (is_vga_mode) { 457 /* Program additional settings if using 640x480 resolution */ 458 459 /* Write offset 0xFF to 0x01 */ 460 buffer[0] = 0xff; 461 buffer[1] = 0x01; 462 i2c_success = write_i2c(pipe_ctx, slave_address, 463 buffer, sizeof(buffer)); 464 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 465 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 466 slave_address, buffer[0], buffer[1], i2c_success?1:0); 467 if (!i2c_success) 468 goto i2c_write_fail; 469 470 /* Write offset 0x00 to 0x23 */ 471 buffer[0] = 0x00; 472 buffer[1] = 0x23; 473 i2c_success = write_i2c(pipe_ctx, slave_address, 474 buffer, sizeof(buffer)); 475 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 476 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 477 slave_address, buffer[0], buffer[1], i2c_success?1:0); 478 if (!i2c_success) 479 goto i2c_write_fail; 480 481 /* Write offset 0xff to 0x00 */ 482 buffer[0] = 0xff; 483 buffer[1] = 0x00; 484 i2c_success = write_i2c(pipe_ctx, slave_address, 485 buffer, sizeof(buffer)); 486 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 487 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 488 slave_address, buffer[0], buffer[1], i2c_success?1:0); 489 if (!i2c_success) 490 goto i2c_write_fail; 491 492 } 493 494 return; 495 496 i2c_write_fail: 497 DC_LOG_DEBUG("Set retimer failed"); 498 } 499 500 static void write_i2c_default_retimer_setting( 501 struct pipe_ctx *pipe_ctx, 502 bool is_vga_mode, 503 bool is_over_340mhz) 504 { 505 uint8_t slave_address = (0xBA >> 1); 506 uint8_t buffer[2]; 507 bool i2c_success = false; 508 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 509 510 memset(&buffer, 0, sizeof(buffer)); 511 512 /* Program Slave Address for tuning single integrity */ 513 /* Write offset 0x0A to 0x13 */ 514 buffer[0] = 0x0A; 515 buffer[1] = 0x13; 516 i2c_success = write_i2c(pipe_ctx, slave_address, 517 buffer, sizeof(buffer)); 518 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 519 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 520 slave_address, buffer[0], buffer[1], i2c_success?1:0); 521 if (!i2c_success) 522 goto i2c_write_fail; 523 524 /* Write offset 0x0A to 0x17 */ 525 buffer[0] = 0x0A; 526 buffer[1] = 0x17; 527 i2c_success = write_i2c(pipe_ctx, slave_address, 528 buffer, sizeof(buffer)); 529 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 530 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 531 slave_address, buffer[0], buffer[1], i2c_success?1:0); 532 if (!i2c_success) 533 goto i2c_write_fail; 534 535 /* Write offset 0x0B to 0xDA or 0xD8 */ 536 buffer[0] = 0x0B; 537 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 538 i2c_success = write_i2c(pipe_ctx, slave_address, 539 buffer, sizeof(buffer)); 540 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 541 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 542 slave_address, buffer[0], buffer[1], i2c_success?1:0); 543 if (!i2c_success) 544 goto i2c_write_fail; 545 546 /* Write offset 0x0A to 0x17 */ 547 buffer[0] = 0x0A; 548 buffer[1] = 0x17; 549 i2c_success = write_i2c(pipe_ctx, slave_address, 550 buffer, sizeof(buffer)); 551 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 552 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 553 slave_address, buffer[0], buffer[1], i2c_success?1:0); 554 if (!i2c_success) 555 goto i2c_write_fail; 556 557 /* Write offset 0x0C to 0x1D or 0x91 */ 558 buffer[0] = 0x0C; 559 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 560 i2c_success = write_i2c(pipe_ctx, slave_address, 561 buffer, sizeof(buffer)); 562 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 563 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 564 slave_address, buffer[0], buffer[1], i2c_success?1:0); 565 if (!i2c_success) 566 goto i2c_write_fail; 567 568 /* Write offset 0x0A to 0x17 */ 569 buffer[0] = 0x0A; 570 buffer[1] = 0x17; 571 i2c_success = write_i2c(pipe_ctx, slave_address, 572 buffer, sizeof(buffer)); 573 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 574 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 575 slave_address, buffer[0], buffer[1], i2c_success?1:0); 576 if (!i2c_success) 577 goto i2c_write_fail; 578 579 580 if (is_vga_mode) { 581 /* Program additional settings if using 640x480 resolution */ 582 583 /* Write offset 0xFF to 0x01 */ 584 buffer[0] = 0xff; 585 buffer[1] = 0x01; 586 i2c_success = write_i2c(pipe_ctx, slave_address, 587 buffer, sizeof(buffer)); 588 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 589 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 590 slave_address, buffer[0], buffer[1], i2c_success?1:0); 591 if (!i2c_success) 592 goto i2c_write_fail; 593 594 /* Write offset 0x00 to 0x23 */ 595 buffer[0] = 0x00; 596 buffer[1] = 0x23; 597 i2c_success = write_i2c(pipe_ctx, slave_address, 598 buffer, sizeof(buffer)); 599 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 600 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 601 slave_address, buffer[0], buffer[1], i2c_success?1:0); 602 if (!i2c_success) 603 goto i2c_write_fail; 604 605 /* Write offset 0xff to 0x00 */ 606 buffer[0] = 0xff; 607 buffer[1] = 0x00; 608 i2c_success = write_i2c(pipe_ctx, slave_address, 609 buffer, sizeof(buffer)); 610 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 611 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 612 slave_address, buffer[0], buffer[1], i2c_success?1:0); 613 if (!i2c_success) 614 goto i2c_write_fail; 615 } 616 617 return; 618 619 i2c_write_fail: 620 DC_LOG_DEBUG("Set default retimer failed"); 621 } 622 623 static void write_i2c_redriver_setting( 624 struct pipe_ctx *pipe_ctx, 625 bool is_over_340mhz) 626 { 627 uint8_t slave_address = (0xF0 >> 1); 628 uint8_t buffer[16]; 629 bool i2c_success = false; 630 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 631 632 memset(&buffer, 0, sizeof(buffer)); 633 634 // Program Slave Address for tuning single integrity 635 buffer[3] = 0x4E; 636 buffer[4] = 0x4E; 637 buffer[5] = 0x4E; 638 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 639 640 i2c_success = write_i2c(pipe_ctx, slave_address, 641 buffer, sizeof(buffer)); 642 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 643 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 644 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 645 i2c_success = %d\n", 646 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 647 648 if (!i2c_success) 649 DC_LOG_DEBUG("Set redriver failed"); 650 } 651 652 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 653 { 654 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 655 struct link_encoder *link_enc = NULL; 656 struct cp_psp_stream_config config = {0}; 657 enum dp_panel_mode panel_mode = 658 dp_get_panel_mode(pipe_ctx->stream->link); 659 660 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 661 return; 662 663 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 664 ASSERT(link_enc); 665 if (link_enc == NULL) 666 return; 667 668 /* otg instance */ 669 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 670 671 /* dig front end */ 672 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 673 674 /* stream encoder index */ 675 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 676 if (dp_is_128b_132b_signal(pipe_ctx)) 677 config.stream_enc_idx = 678 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 679 680 /* dig back end */ 681 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 682 683 /* link encoder index */ 684 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 685 if (dp_is_128b_132b_signal(pipe_ctx)) 686 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 687 688 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 689 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 690 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 691 else 692 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 693 694 695 /* phy index */ 696 config.phy_idx = resource_transmitter_to_phy_idx( 697 pipe_ctx->stream->link->dc, link_enc->transmitter); 698 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 699 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 700 config.phy_idx = 0; 701 702 /* stream properties */ 703 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 704 config.mst_enabled = (pipe_ctx->stream->signal == 705 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 706 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 707 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 708 1 : 0; 709 config.dpms_off = dpms_off; 710 711 /* dm stream context */ 712 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 713 714 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 715 } 716 717 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 718 { 719 struct dc *dc = pipe_ctx->stream->ctx->dc; 720 721 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 722 return; 723 724 dc->hwss.set_avmute(pipe_ctx, enable); 725 } 726 727 static void enable_mst_on_sink(struct dc_link *link, bool enable) 728 { 729 unsigned char mstmCntl = 0; 730 731 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 732 if (enable) 733 mstmCntl |= DP_MST_EN; 734 else 735 mstmCntl &= (~DP_MST_EN); 736 737 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 738 } 739 740 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 741 struct dsc_optc_config *config) 742 { 743 uint32_t precision = 1 << 28; 744 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 745 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 746 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 747 DC_LOGGER_INIT(dsc->ctx->logger); 748 749 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 750 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 751 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 752 */ 753 ll_bytes_per_pix_fraq *= 10000000; 754 ll_bytes_per_pix_fraq /= precision; 755 756 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 757 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 758 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 759 DC_LOG_DSC("\tslice_width %d", config->slice_width); 760 } 761 762 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 763 { 764 struct dc *dc = pipe_ctx->stream->ctx->dc; 765 struct dc_stream_state *stream = pipe_ctx->stream; 766 bool result = false; 767 768 if (dc_is_virtual_signal(stream->signal)) 769 result = true; 770 else 771 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 772 return result; 773 } 774 775 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 776 * i.e. after dp_enable_dsc_on_rx() had been called 777 */ 778 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 779 { 780 /* TODO: Move this to HWSS as this is hardware programming sequence not a 781 * link layer sequence 782 */ 783 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 784 struct dc *dc = pipe_ctx->stream->ctx->dc; 785 struct dc_stream_state *stream = pipe_ctx->stream; 786 struct pipe_ctx *odm_pipe; 787 int opp_cnt = 1; 788 struct dccg *dccg = dc->res_pool->dccg; 789 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 790 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 791 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 792 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 793 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 794 * this problem. We are implementing a workaround here to keep using dscclk 795 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 796 * 48Mhz) pixel clock to avoid hitting this problem. 797 */ 798 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 799 stream->timing.pix_clk_100hz > 480000; 800 DC_LOGGER_INIT(dsc->ctx->logger); 801 802 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 803 opp_cnt++; 804 805 if (enable) { 806 struct dsc_config dsc_cfg; 807 struct dsc_optc_config dsc_optc_cfg = {0}; 808 enum optc_dsc_mode optc_dsc_mode; 809 810 /* Enable DSC hw block */ 811 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 812 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 813 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 814 dsc_cfg.color_depth = stream->timing.display_color_depth; 815 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 816 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 817 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 818 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 819 820 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 821 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 822 if (should_use_dto_dscclk) 823 dccg->funcs->set_dto_dscclk(dccg, dsc->inst); 824 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 825 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 826 827 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 828 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 829 if (should_use_dto_dscclk) 830 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst); 831 } 832 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 833 dsc_cfg.pic_width *= opp_cnt; 834 835 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 836 837 /* Enable DSC in encoder */ 838 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 839 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 840 dsc_optc_config_log(dsc, &dsc_optc_cfg); 841 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 842 optc_dsc_mode, 843 dsc_optc_cfg.bytes_per_pixel, 844 dsc_optc_cfg.slice_width); 845 846 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 847 } 848 849 /* Enable DSC in OPTC */ 850 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 851 dsc_optc_config_log(dsc, &dsc_optc_cfg); 852 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 853 optc_dsc_mode, 854 dsc_optc_cfg.bytes_per_pixel, 855 dsc_optc_cfg.slice_width); 856 } else { 857 /* disable DSC in OPTC */ 858 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 859 pipe_ctx->stream_res.tg, 860 OPTC_DSC_DISABLED, 0, 0); 861 862 /* disable DSC in stream encoder */ 863 if (dc_is_dp_signal(stream->signal)) { 864 if (dp_is_128b_132b_signal(pipe_ctx)) 865 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 866 pipe_ctx->stream_res.hpo_dp_stream_enc, 867 false, 868 NULL, 869 true); 870 else { 871 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 872 pipe_ctx->stream_res.stream_enc, 873 OPTC_DSC_DISABLED, 0, 0); 874 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 875 pipe_ctx->stream_res.stream_enc, false, NULL, true); 876 } 877 } 878 879 /* disable DSC block */ 880 if (dccg->funcs->set_ref_dscclk) 881 dccg->funcs->set_ref_dscclk(dccg, pipe_ctx->stream_res.dsc->inst); 882 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 883 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 884 if (dccg->funcs->set_ref_dscclk) 885 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 886 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 887 } 888 } 889 } 890 891 /* 892 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 893 * hence PPS info packet update need to use frame update instead of immediate update. 894 * Added parameter immediate_update for this purpose. 895 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 896 * which is the only place where a "false" would be passed in for param immediate_update. 897 * 898 * immediate_update is only applicable when DSC is enabled. 899 */ 900 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 901 { 902 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 903 struct dc_stream_state *stream = pipe_ctx->stream; 904 905 if (!pipe_ctx->stream->timing.flags.DSC) 906 return false; 907 908 if (!dsc) 909 return false; 910 911 DC_LOGGER_INIT(dsc->ctx->logger); 912 913 if (enable) { 914 struct dsc_config dsc_cfg; 915 uint8_t dsc_packed_pps[128]; 916 917 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 918 memset(dsc_packed_pps, 0, 128); 919 920 /* Enable DSC hw block */ 921 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 922 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 923 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 924 dsc_cfg.color_depth = stream->timing.display_color_depth; 925 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 926 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 927 928 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 929 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 930 if (dc_is_dp_signal(stream->signal)) { 931 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 932 if (dp_is_128b_132b_signal(pipe_ctx)) 933 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 934 pipe_ctx->stream_res.hpo_dp_stream_enc, 935 true, 936 &dsc_packed_pps[0], 937 immediate_update); 938 else 939 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 940 pipe_ctx->stream_res.stream_enc, 941 true, 942 &dsc_packed_pps[0], 943 immediate_update); 944 } 945 } else { 946 /* disable DSC PPS in stream encoder */ 947 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 948 if (dc_is_dp_signal(stream->signal)) { 949 if (dp_is_128b_132b_signal(pipe_ctx)) 950 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 951 pipe_ctx->stream_res.hpo_dp_stream_enc, 952 false, 953 NULL, 954 true); 955 else 956 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 957 pipe_ctx->stream_res.stream_enc, false, NULL, true); 958 } 959 } 960 961 return true; 962 } 963 964 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 965 { 966 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 967 bool result = false; 968 969 if (!pipe_ctx->stream->timing.flags.DSC) 970 goto out; 971 if (!dsc) 972 goto out; 973 974 if (enable) { 975 { 976 link_set_dsc_on_stream(pipe_ctx, true); 977 result = true; 978 } 979 } else { 980 dp_set_dsc_on_rx(pipe_ctx, false); 981 link_set_dsc_on_stream(pipe_ctx, false); 982 result = true; 983 } 984 out: 985 return result; 986 } 987 988 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 989 { 990 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 991 992 if (!pipe_ctx->stream->timing.flags.DSC) 993 return false; 994 if (!dsc) 995 return false; 996 997 link_set_dsc_on_stream(pipe_ctx, true); 998 link_set_dsc_pps_packet(pipe_ctx, true, false); 999 return true; 1000 } 1001 1002 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1003 { 1004 struct dc_stream_state *stream = pipe_ctx->stream; 1005 1006 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1007 struct dc_link *link = stream->link; 1008 union down_spread_ctrl old_downspread; 1009 union down_spread_ctrl new_downspread; 1010 1011 memset(&old_downspread, 0, sizeof(old_downspread)); 1012 1013 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1014 &old_downspread.raw, sizeof(old_downspread)); 1015 1016 new_downspread.raw = old_downspread.raw; 1017 1018 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1019 (stream->ignore_msa_timing_param) ? 1 : 0; 1020 1021 if (new_downspread.raw != old_downspread.raw) { 1022 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1023 &new_downspread.raw, sizeof(new_downspread)); 1024 } 1025 1026 } else { 1027 dm_helpers_mst_enable_stream_features(stream); 1028 } 1029 } 1030 1031 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1032 { 1033 const uint32_t VCP_Y_PRECISION = 1000; 1034 uint64_t vcp_x, vcp_y; 1035 DC_LOGGER_INIT(link->ctx->logger); 1036 1037 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1038 avg_time_slots_per_mtp = dc_fixpt_add( 1039 avg_time_slots_per_mtp, 1040 dc_fixpt_from_fraction( 1041 1, 1042 2*VCP_Y_PRECISION)); 1043 1044 vcp_x = dc_fixpt_floor( 1045 avg_time_slots_per_mtp); 1046 vcp_y = dc_fixpt_floor( 1047 dc_fixpt_mul_int( 1048 dc_fixpt_sub_int( 1049 avg_time_slots_per_mtp, 1050 dc_fixpt_floor( 1051 avg_time_slots_per_mtp)), 1052 VCP_Y_PRECISION)); 1053 1054 1055 if (link->type == dc_connection_mst_branch) 1056 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1057 "X: %llu " 1058 "Y: %llu/%d", 1059 vcp_x, 1060 vcp_y, 1061 VCP_Y_PRECISION); 1062 else 1063 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1064 "X: %llu " 1065 "Y: %llu/%d", 1066 vcp_x, 1067 vcp_y, 1068 VCP_Y_PRECISION); 1069 } 1070 1071 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1072 { 1073 struct fixed31_32 mbytes_per_sec; 1074 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1075 &stream->link->cur_link_settings); 1076 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1077 1078 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1079 1080 return dc_fixpt_div_int(mbytes_per_sec, 54); 1081 } 1082 1083 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1084 { 1085 struct fixed31_32 peak_kbps; 1086 uint32_t numerator = 0; 1087 uint32_t denominator = 1; 1088 1089 /* 1090 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1091 * required when determining PBN/time slot utilization on the link between 1092 * us and the branch, since that overhead is already accounted for in 1093 * the get_pbn_per_slot function. 1094 * 1095 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1096 * common multiplier to render an integer PBN for all link rate/lane 1097 * counts combinations 1098 * calculate 1099 * peak_kbps *= (64/54) 1100 * peak_kbps /= (8 * 1000) convert to bytes 1101 */ 1102 1103 numerator = 64; 1104 denominator = 54 * 8 * 1000; 1105 kbps *= numerator; 1106 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1107 1108 return peak_kbps; 1109 } 1110 1111 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1112 { 1113 uint64_t kbps; 1114 enum dc_link_encoding_format link_encoding; 1115 1116 if (dp_is_128b_132b_signal(pipe_ctx)) 1117 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1118 else 1119 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1120 1121 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1122 return get_pbn_from_bw_in_kbps(kbps); 1123 } 1124 1125 1126 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1127 static void get_lane_status( 1128 struct dc_link *link, 1129 uint32_t lane_count, 1130 union lane_status *status, 1131 union lane_align_status_updated *status_updated) 1132 { 1133 unsigned int lane; 1134 uint8_t dpcd_buf[3] = {0}; 1135 1136 if (status == NULL || status_updated == NULL) { 1137 return; 1138 } 1139 1140 core_link_read_dpcd( 1141 link, 1142 DP_LANE0_1_STATUS, 1143 dpcd_buf, 1144 sizeof(dpcd_buf)); 1145 1146 for (lane = 0; lane < lane_count; lane++) { 1147 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1148 } 1149 1150 status_updated->raw = dpcd_buf[2]; 1151 } 1152 1153 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1154 { 1155 /* 1156 * wait for ACT handled 1157 */ 1158 int i; 1159 const int act_retries = 30; 1160 enum act_return_status result = ACT_FAILED; 1161 union payload_table_update_status update_status = {0}; 1162 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1163 union lane_align_status_updated lane_status_updated; 1164 DC_LOGGER_INIT(link->ctx->logger); 1165 1166 if (link->aux_access_disabled) 1167 return true; 1168 for (i = 0; i < act_retries; i++) { 1169 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1170 1171 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1172 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1173 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1174 !dp_is_interlane_aligned(lane_status_updated)) { 1175 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1176 "polling for ACT handled."); 1177 result = ACT_LINK_LOST; 1178 break; 1179 } 1180 core_link_read_dpcd( 1181 link, 1182 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1183 &update_status.raw, 1184 1); 1185 1186 if (update_status.bits.ACT_HANDLED == 1) { 1187 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1188 result = ACT_SUCCESS; 1189 break; 1190 } 1191 1192 fsleep(5000); 1193 } 1194 1195 if (result == ACT_FAILED) { 1196 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1197 "continue on. Something is wrong with the branch."); 1198 } 1199 1200 return (result == ACT_SUCCESS); 1201 } 1202 1203 static void update_mst_stream_alloc_table( 1204 struct dc_link *link, 1205 struct stream_encoder *stream_enc, 1206 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1207 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1208 { 1209 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1210 struct link_mst_stream_allocation *dc_alloc; 1211 1212 int i; 1213 int j; 1214 1215 /* if DRM proposed_table has more than one new payload */ 1216 ASSERT(proposed_table->stream_count - 1217 link->mst_stream_alloc_table.stream_count < 2); 1218 1219 /* copy proposed_table to link, add stream encoder */ 1220 for (i = 0; i < proposed_table->stream_count; i++) { 1221 1222 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1223 dc_alloc = 1224 &link->mst_stream_alloc_table.stream_allocations[j]; 1225 1226 if (dc_alloc->vcp_id == 1227 proposed_table->stream_allocations[i].vcp_id) { 1228 1229 work_table[i] = *dc_alloc; 1230 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1231 break; /* exit j loop */ 1232 } 1233 } 1234 1235 /* new vcp_id */ 1236 if (j == link->mst_stream_alloc_table.stream_count) { 1237 work_table[i].vcp_id = 1238 proposed_table->stream_allocations[i].vcp_id; 1239 work_table[i].slot_count = 1240 proposed_table->stream_allocations[i].slot_count; 1241 work_table[i].stream_enc = stream_enc; 1242 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1243 } 1244 } 1245 1246 /* update link->mst_stream_alloc_table with work_table */ 1247 link->mst_stream_alloc_table.stream_count = 1248 proposed_table->stream_count; 1249 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1250 link->mst_stream_alloc_table.stream_allocations[i] = 1251 work_table[i]; 1252 } 1253 1254 static void remove_stream_from_alloc_table( 1255 struct dc_link *link, 1256 struct stream_encoder *dio_stream_enc, 1257 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1258 { 1259 int i = 0; 1260 struct link_mst_stream_allocation_table *table = 1261 &link->mst_stream_alloc_table; 1262 1263 if (hpo_dp_stream_enc) { 1264 for (; i < table->stream_count; i++) 1265 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1266 break; 1267 } else { 1268 for (; i < table->stream_count; i++) 1269 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1270 break; 1271 } 1272 1273 if (i < table->stream_count) { 1274 i++; 1275 for (; i < table->stream_count; i++) 1276 table->stream_allocations[i-1] = table->stream_allocations[i]; 1277 memset(&table->stream_allocations[table->stream_count-1], 0, 1278 sizeof(struct link_mst_stream_allocation)); 1279 table->stream_count--; 1280 } 1281 } 1282 1283 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1284 { 1285 struct dc_stream_state *stream = pipe_ctx->stream; 1286 struct dc_link *link = stream->link; 1287 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1288 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1289 int i; 1290 bool mst_mode = (link->type == dc_connection_mst_branch); 1291 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1292 const struct dc_link_settings empty_link_settings = {0}; 1293 DC_LOGGER_INIT(link->ctx->logger); 1294 1295 /* deallocate_mst_payload is called before disable link. When mode or 1296 * disable/enable monitor, new stream is created which is not in link 1297 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1298 * should not done. For new mode set, map_resources will get engine 1299 * for new stream, so stream_enc->id should be validated until here. 1300 */ 1301 1302 /* slot X.Y */ 1303 if (link_hwss->ext.set_throttled_vcp_size) 1304 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1305 if (link_hwss->ext.set_hblank_min_symbol_width) 1306 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1307 &empty_link_settings, 1308 avg_time_slots_per_mtp); 1309 1310 if (mst_mode) { 1311 /* when link is in mst mode, reply on mst manager to remove 1312 * payload 1313 */ 1314 if (dm_helpers_dp_mst_write_payload_allocation_table( 1315 stream->ctx, 1316 stream, 1317 &proposed_table, 1318 false)) 1319 update_mst_stream_alloc_table( 1320 link, 1321 pipe_ctx->stream_res.stream_enc, 1322 pipe_ctx->stream_res.hpo_dp_stream_enc, 1323 &proposed_table); 1324 else 1325 DC_LOG_WARNING("Failed to update" 1326 "MST allocation table for" 1327 "pipe idx:%d\n", 1328 pipe_ctx->pipe_idx); 1329 } else { 1330 /* when link is no longer in mst mode (mst hub unplugged), 1331 * remove payload with default dc logic 1332 */ 1333 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1334 pipe_ctx->stream_res.hpo_dp_stream_enc); 1335 } 1336 1337 DC_LOG_MST("%s" 1338 "stream_count: %d: ", 1339 __func__, 1340 link->mst_stream_alloc_table.stream_count); 1341 1342 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1343 DC_LOG_MST("stream_enc[%d]: %p " 1344 "stream[%d].hpo_dp_stream_enc: %p " 1345 "stream[%d].vcp_id: %d " 1346 "stream[%d].slot_count: %d\n", 1347 i, 1348 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1349 i, 1350 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1351 i, 1352 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1353 i, 1354 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1355 } 1356 1357 /* update mst stream allocation table hardware state */ 1358 if (link_hwss->ext.update_stream_allocation_table == NULL || 1359 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1360 DC_LOG_DEBUG("Unknown encoding format\n"); 1361 return DC_ERROR_UNEXPECTED; 1362 } 1363 1364 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1365 &link->mst_stream_alloc_table); 1366 1367 if (mst_mode) 1368 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1369 stream->ctx, 1370 stream); 1371 1372 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1373 stream->ctx, 1374 stream); 1375 1376 return DC_OK; 1377 } 1378 1379 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1380 * because stream_encoder is not exposed to dm 1381 */ 1382 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1383 { 1384 struct dc_stream_state *stream = pipe_ctx->stream; 1385 struct dc_link *link = stream->link; 1386 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1387 struct fixed31_32 avg_time_slots_per_mtp; 1388 struct fixed31_32 pbn; 1389 struct fixed31_32 pbn_per_slot; 1390 int i; 1391 enum act_return_status ret; 1392 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1393 DC_LOGGER_INIT(link->ctx->logger); 1394 1395 /* enable_link_dp_mst already check link->enabled_stream_count 1396 * and stream is in link->stream[]. This is called during set mode, 1397 * stream_enc is available. 1398 */ 1399 1400 /* get calculate VC payload for stream: stream_alloc */ 1401 if (dm_helpers_dp_mst_write_payload_allocation_table( 1402 stream->ctx, 1403 stream, 1404 &proposed_table, 1405 true)) 1406 update_mst_stream_alloc_table( 1407 link, 1408 pipe_ctx->stream_res.stream_enc, 1409 pipe_ctx->stream_res.hpo_dp_stream_enc, 1410 &proposed_table); 1411 else 1412 DC_LOG_WARNING("Failed to update" 1413 "MST allocation table for" 1414 "pipe idx:%d\n", 1415 pipe_ctx->pipe_idx); 1416 1417 DC_LOG_MST("%s " 1418 "stream_count: %d: \n ", 1419 __func__, 1420 link->mst_stream_alloc_table.stream_count); 1421 1422 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1423 DC_LOG_MST("stream_enc[%d]: %p " 1424 "stream[%d].hpo_dp_stream_enc: %p " 1425 "stream[%d].vcp_id: %d " 1426 "stream[%d].slot_count: %d\n", 1427 i, 1428 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1429 i, 1430 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1431 i, 1432 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1433 i, 1434 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1435 } 1436 1437 ASSERT(proposed_table.stream_count > 0); 1438 1439 /* program DP source TX for payload */ 1440 if (link_hwss->ext.update_stream_allocation_table == NULL || 1441 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1442 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1443 return DC_ERROR_UNEXPECTED; 1444 } 1445 1446 link_hwss->ext.update_stream_allocation_table(link, 1447 &pipe_ctx->link_res, 1448 &link->mst_stream_alloc_table); 1449 1450 /* send down message */ 1451 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1452 stream->ctx, 1453 stream); 1454 1455 if (ret != ACT_LINK_LOST) 1456 dm_helpers_dp_mst_send_payload_allocation( 1457 stream->ctx, 1458 stream); 1459 1460 /* slot X.Y for only current stream */ 1461 pbn_per_slot = get_pbn_per_slot(stream); 1462 if (pbn_per_slot.value == 0) { 1463 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1464 return DC_UNSUPPORTED_VALUE; 1465 } 1466 pbn = get_pbn_from_timing(pipe_ctx); 1467 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1468 1469 log_vcp_x_y(link, avg_time_slots_per_mtp); 1470 1471 if (link_hwss->ext.set_throttled_vcp_size) 1472 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1473 if (link_hwss->ext.set_hblank_min_symbol_width) 1474 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1475 &link->cur_link_settings, 1476 avg_time_slots_per_mtp); 1477 1478 return DC_OK; 1479 } 1480 1481 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1482 const struct dc_stream_state *stream, 1483 const struct dc_link *link) 1484 { 1485 struct fixed31_32 link_bw_effective = 1486 dc_fixpt_from_int( 1487 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1488 struct fixed31_32 timeslot_bw_effective = 1489 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1490 struct fixed31_32 timing_bw = 1491 dc_fixpt_from_int( 1492 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1493 dc_link_get_highest_encoding_format(link))); 1494 struct fixed31_32 avg_time_slots_per_mtp = 1495 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1496 1497 return avg_time_slots_per_mtp; 1498 } 1499 1500 1501 static bool write_128b_132b_sst_payload_allocation_table( 1502 const struct dc_stream_state *stream, 1503 struct dc_link *link, 1504 struct link_mst_stream_allocation_table *proposed_table, 1505 bool allocate) 1506 { 1507 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1508 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1509 bool result = false; 1510 uint8_t req_slot_count = 0; 1511 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1512 union payload_table_update_status update_status = { 0 }; 1513 const uint32_t max_retries = 30; 1514 uint32_t retries = 0; 1515 DC_LOGGER_INIT(link->ctx->logger); 1516 1517 if (allocate) { 1518 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1519 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1520 /// Validation should filter out modes that exceed link BW 1521 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1522 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1523 return false; 1524 } else { 1525 /// Leave req_slot_count = 0 if allocate is false. 1526 } 1527 1528 proposed_table->stream_count = 1; /// Always 1 stream for SST 1529 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1530 proposed_table->stream_allocations[0].vcp_id = vc_id; 1531 1532 if (link->aux_access_disabled) 1533 return true; 1534 1535 /// Write DPCD 2C0 = 1 to start updating 1536 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1537 core_link_write_dpcd( 1538 link, 1539 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1540 &update_status.raw, 1541 1); 1542 1543 /// Program the changes in DPCD 1C0 - 1C2 1544 ASSERT(vc_id == 1); 1545 core_link_write_dpcd( 1546 link, 1547 DP_PAYLOAD_ALLOCATE_SET, 1548 &vc_id, 1549 1); 1550 1551 ASSERT(start_time_slot == 0); 1552 core_link_write_dpcd( 1553 link, 1554 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1555 &start_time_slot, 1556 1); 1557 1558 core_link_write_dpcd( 1559 link, 1560 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1561 &req_slot_count, 1562 1); 1563 1564 /// Poll till DPCD 2C0 read 1 1565 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1566 1567 while (retries < max_retries) { 1568 if (core_link_read_dpcd( 1569 link, 1570 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1571 &update_status.raw, 1572 1) == DC_OK) { 1573 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1574 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1575 result = true; 1576 break; 1577 } 1578 } else { 1579 union dpcd_rev dpcdRev = {0}; 1580 1581 if (core_link_read_dpcd( 1582 link, 1583 DP_DPCD_REV, 1584 &dpcdRev.raw, 1585 1) != DC_OK) { 1586 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1587 "of sink while polling payload table " 1588 "updated status bit."); 1589 break; 1590 } 1591 } 1592 retries++; 1593 fsleep(5000); 1594 } 1595 1596 if (!result && retries == max_retries) { 1597 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1598 "continue on. Something is wrong with the branch."); 1599 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1600 } 1601 1602 return result; 1603 } 1604 1605 /* 1606 * Payload allocation/deallocation for SST introduced in DP2.0 1607 */ 1608 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1609 bool allocate) 1610 { 1611 struct dc_stream_state *stream = pipe_ctx->stream; 1612 struct dc_link *link = stream->link; 1613 struct link_mst_stream_allocation_table proposed_table = {0}; 1614 struct fixed31_32 avg_time_slots_per_mtp; 1615 const struct dc_link_settings empty_link_settings = {0}; 1616 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1617 DC_LOGGER_INIT(link->ctx->logger); 1618 1619 /* slot X.Y for SST payload deallocate */ 1620 if (!allocate) { 1621 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1622 1623 log_vcp_x_y(link, avg_time_slots_per_mtp); 1624 1625 if (link_hwss->ext.set_throttled_vcp_size) 1626 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1627 avg_time_slots_per_mtp); 1628 if (link_hwss->ext.set_hblank_min_symbol_width) 1629 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1630 &empty_link_settings, 1631 avg_time_slots_per_mtp); 1632 } 1633 1634 /* calculate VC payload and update branch with new payload allocation table*/ 1635 if (!write_128b_132b_sst_payload_allocation_table( 1636 stream, 1637 link, 1638 &proposed_table, 1639 allocate)) { 1640 DC_LOG_ERROR("SST Update Payload: Failed to update " 1641 "allocation table for " 1642 "pipe idx: %d\n", 1643 pipe_ctx->pipe_idx); 1644 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1645 } 1646 1647 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1648 1649 ASSERT(proposed_table.stream_count == 1); 1650 1651 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1652 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1653 "vcp_id: %d " 1654 "slot_count: %d\n", 1655 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1656 proposed_table.stream_allocations[0].vcp_id, 1657 proposed_table.stream_allocations[0].slot_count); 1658 1659 /* program DP source TX for payload */ 1660 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1661 &proposed_table); 1662 1663 /* poll for ACT handled */ 1664 if (!poll_for_allocation_change_trigger(link)) { 1665 // Failures will result in blackscreen and errors logged 1666 BREAK_TO_DEBUGGER(); 1667 } 1668 1669 /* slot X.Y for SST payload allocate */ 1670 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1671 DP_128b_132b_ENCODING) { 1672 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1673 1674 log_vcp_x_y(link, avg_time_slots_per_mtp); 1675 1676 if (link_hwss->ext.set_throttled_vcp_size) 1677 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1678 avg_time_slots_per_mtp); 1679 if (link_hwss->ext.set_hblank_min_symbol_width) 1680 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1681 &link->cur_link_settings, 1682 avg_time_slots_per_mtp); 1683 } 1684 1685 /* Always return DC_OK. 1686 * If part of sequence fails, log failure(s) and show blackscreen 1687 */ 1688 return DC_OK; 1689 } 1690 1691 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1692 { 1693 struct dc_stream_state *stream = pipe_ctx->stream; 1694 struct dc_link *link = stream->link; 1695 struct fixed31_32 avg_time_slots_per_mtp; 1696 struct fixed31_32 pbn; 1697 struct fixed31_32 pbn_per_slot; 1698 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1699 uint8_t i; 1700 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1701 DC_LOGGER_INIT(link->ctx->logger); 1702 1703 /* decrease throttled vcp size */ 1704 pbn_per_slot = get_pbn_per_slot(stream); 1705 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1706 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1707 1708 if (link_hwss->ext.set_throttled_vcp_size) 1709 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1710 if (link_hwss->ext.set_hblank_min_symbol_width) 1711 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1712 &link->cur_link_settings, 1713 avg_time_slots_per_mtp); 1714 1715 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1716 dm_helpers_dp_mst_send_payload_allocation( 1717 stream->ctx, 1718 stream); 1719 1720 /* notify immediate branch device table update */ 1721 if (dm_helpers_dp_mst_write_payload_allocation_table( 1722 stream->ctx, 1723 stream, 1724 &proposed_table, 1725 true)) { 1726 /* update mst stream allocation table software state */ 1727 update_mst_stream_alloc_table( 1728 link, 1729 pipe_ctx->stream_res.stream_enc, 1730 pipe_ctx->stream_res.hpo_dp_stream_enc, 1731 &proposed_table); 1732 } else { 1733 DC_LOG_WARNING("Failed to update" 1734 "MST allocation table for" 1735 "pipe idx:%d\n", 1736 pipe_ctx->pipe_idx); 1737 } 1738 1739 DC_LOG_MST("%s " 1740 "stream_count: %d: \n ", 1741 __func__, 1742 link->mst_stream_alloc_table.stream_count); 1743 1744 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1745 DC_LOG_MST("stream_enc[%d]: %p " 1746 "stream[%d].hpo_dp_stream_enc: %p " 1747 "stream[%d].vcp_id: %d " 1748 "stream[%d].slot_count: %d\n", 1749 i, 1750 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1751 i, 1752 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1753 i, 1754 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1755 i, 1756 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1757 } 1758 1759 ASSERT(proposed_table.stream_count > 0); 1760 1761 /* update mst stream allocation table hardware state */ 1762 if (link_hwss->ext.update_stream_allocation_table == NULL || 1763 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1764 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1765 return DC_ERROR_UNEXPECTED; 1766 } 1767 1768 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1769 &link->mst_stream_alloc_table); 1770 1771 /* poll for immediate branch device ACT handled */ 1772 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1773 stream->ctx, 1774 stream); 1775 1776 return DC_OK; 1777 } 1778 1779 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1780 { 1781 struct dc_stream_state *stream = pipe_ctx->stream; 1782 struct dc_link *link = stream->link; 1783 struct fixed31_32 avg_time_slots_per_mtp; 1784 struct fixed31_32 pbn; 1785 struct fixed31_32 pbn_per_slot; 1786 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1787 uint8_t i; 1788 enum act_return_status ret; 1789 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1790 DC_LOGGER_INIT(link->ctx->logger); 1791 1792 /* notify immediate branch device table update */ 1793 if (dm_helpers_dp_mst_write_payload_allocation_table( 1794 stream->ctx, 1795 stream, 1796 &proposed_table, 1797 true)) { 1798 /* update mst stream allocation table software state */ 1799 update_mst_stream_alloc_table( 1800 link, 1801 pipe_ctx->stream_res.stream_enc, 1802 pipe_ctx->stream_res.hpo_dp_stream_enc, 1803 &proposed_table); 1804 } 1805 1806 DC_LOG_MST("%s " 1807 "stream_count: %d: \n ", 1808 __func__, 1809 link->mst_stream_alloc_table.stream_count); 1810 1811 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1812 DC_LOG_MST("stream_enc[%d]: %p " 1813 "stream[%d].hpo_dp_stream_enc: %p " 1814 "stream[%d].vcp_id: %d " 1815 "stream[%d].slot_count: %d\n", 1816 i, 1817 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1818 i, 1819 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1820 i, 1821 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1822 i, 1823 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1824 } 1825 1826 ASSERT(proposed_table.stream_count > 0); 1827 1828 /* update mst stream allocation table hardware state */ 1829 if (link_hwss->ext.update_stream_allocation_table == NULL || 1830 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1831 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1832 return DC_ERROR_UNEXPECTED; 1833 } 1834 1835 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1836 &link->mst_stream_alloc_table); 1837 1838 /* poll for immediate branch device ACT handled */ 1839 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1840 stream->ctx, 1841 stream); 1842 1843 if (ret != ACT_LINK_LOST) { 1844 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1845 dm_helpers_dp_mst_send_payload_allocation( 1846 stream->ctx, 1847 stream); 1848 } 1849 1850 /* increase throttled vcp size */ 1851 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1852 pbn_per_slot = get_pbn_per_slot(stream); 1853 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1854 1855 if (link_hwss->ext.set_throttled_vcp_size) 1856 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1857 if (link_hwss->ext.set_hblank_min_symbol_width) 1858 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1859 &link->cur_link_settings, 1860 avg_time_slots_per_mtp); 1861 1862 return DC_OK; 1863 } 1864 1865 static void disable_link_dp(struct dc_link *link, 1866 const struct link_resource *link_res, 1867 enum signal_type signal) 1868 { 1869 struct dc_link_settings link_settings = link->cur_link_settings; 1870 1871 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1872 link->mst_stream_alloc_table.stream_count > 0) 1873 /* disable MST link only when last vc payload is deallocated */ 1874 return; 1875 1876 dp_disable_link_phy(link, link_res, signal); 1877 1878 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1879 if (!link->skip_implict_edp_power_control) 1880 link->dc->hwss.edp_power_control(link, false); 1881 } 1882 1883 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1884 /* set the sink to SST mode after disabling the link */ 1885 enable_mst_on_sink(link, false); 1886 1887 if (link_dp_get_encoding_format(&link_settings) == 1888 DP_8b_10b_ENCODING) { 1889 dp_set_fec_enable(link, false); 1890 dp_set_fec_ready(link, link_res, false); 1891 } 1892 } 1893 1894 static void disable_link(struct dc_link *link, 1895 const struct link_resource *link_res, 1896 enum signal_type signal) 1897 { 1898 if (dc_is_dp_signal(signal)) { 1899 disable_link_dp(link, link_res, signal); 1900 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1901 link->dc->hwss.disable_link_output(link, link_res, signal); 1902 } 1903 1904 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1905 /* MST disable link only when no stream use the link */ 1906 if (link->mst_stream_alloc_table.stream_count <= 0) 1907 link->link_status.link_active = false; 1908 } else { 1909 link->link_status.link_active = false; 1910 } 1911 } 1912 1913 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1914 { 1915 struct dc_stream_state *stream = pipe_ctx->stream; 1916 struct dc_link *link = stream->link; 1917 enum dc_color_depth display_color_depth; 1918 enum engine_id eng_id; 1919 struct ext_hdmi_settings settings = {0}; 1920 bool is_over_340mhz = false; 1921 bool is_vga_mode = (stream->timing.h_addressable == 640) 1922 && (stream->timing.v_addressable == 480); 1923 struct dc *dc = pipe_ctx->stream->ctx->dc; 1924 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1925 1926 if (stream->phy_pix_clk == 0) 1927 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1928 if (stream->phy_pix_clk > 340000) 1929 is_over_340mhz = true; 1930 1931 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1932 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1933 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1934 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1935 /* DP159, Retimer settings */ 1936 eng_id = pipe_ctx->stream_res.stream_enc->id; 1937 1938 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1939 write_i2c_retimer_setting(pipe_ctx, 1940 is_vga_mode, is_over_340mhz, &settings); 1941 } else { 1942 write_i2c_default_retimer_setting(pipe_ctx, 1943 is_vga_mode, is_over_340mhz); 1944 } 1945 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1946 /* PI3EQX1204, Redriver settings */ 1947 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1948 } 1949 } 1950 1951 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1952 write_scdc_data( 1953 stream->link->ddc, 1954 stream->phy_pix_clk, 1955 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 1956 1957 memset(&stream->link->cur_link_settings, 0, 1958 sizeof(struct dc_link_settings)); 1959 1960 display_color_depth = stream->timing.display_color_depth; 1961 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1962 display_color_depth = COLOR_DEPTH_888; 1963 1964 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 1965 * character clock in case that beyond 340MHz. 1966 */ 1967 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 1968 link_hwss->setup_stream_encoder(pipe_ctx); 1969 1970 dc->hwss.enable_tmds_link_output( 1971 link, 1972 &pipe_ctx->link_res, 1973 pipe_ctx->stream->signal, 1974 pipe_ctx->clock_source->id, 1975 display_color_depth, 1976 stream->phy_pix_clk); 1977 1978 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1979 read_scdc_data(link->ddc); 1980 } 1981 1982 static enum dc_status enable_link_dp(struct dc_state *state, 1983 struct pipe_ctx *pipe_ctx) 1984 { 1985 struct dc_stream_state *stream = pipe_ctx->stream; 1986 enum dc_status status; 1987 bool skip_video_pattern; 1988 struct dc_link *link = stream->link; 1989 const struct dc_link_settings *link_settings = 1990 &pipe_ctx->link_config.dp_link_settings; 1991 bool fec_enable; 1992 int i; 1993 bool apply_seamless_boot_optimization = false; 1994 uint32_t bl_oled_enable_delay = 50; // in ms 1995 uint32_t post_oui_delay = 30; // 30ms 1996 /* Reduce link bandwidth between failed link training attempts. */ 1997 bool do_fallback = false; 1998 int lt_attempts = LINK_TRAINING_ATTEMPTS; 1999 2000 // Increase retry count if attempting DP1.x on FIXED_VS link 2001 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2002 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2003 lt_attempts = 10; 2004 2005 // check for seamless boot 2006 for (i = 0; i < state->stream_count; i++) { 2007 if (state->streams[i]->apply_seamless_boot_optimization) { 2008 apply_seamless_boot_optimization = true; 2009 break; 2010 } 2011 } 2012 2013 /* Train with fallback when enabling DPIA link. Conventional links are 2014 * trained with fallback during sink detection. 2015 */ 2016 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2017 do_fallback = true; 2018 2019 /* 2020 * Temporary w/a to get DP2.0 link rates to work with SST. 2021 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2022 */ 2023 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2024 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2025 link->dc->debug.set_mst_en_for_sst) { 2026 enable_mst_on_sink(link, true); 2027 } 2028 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2029 /*in case it is not on*/ 2030 if (!link->dc->config.edp_no_power_sequencing) 2031 link->dc->hwss.edp_power_control(link, true); 2032 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2033 } 2034 2035 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2036 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2037 } else { 2038 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2039 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2040 if (state->clk_mgr && !apply_seamless_boot_optimization) 2041 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2042 state, false); 2043 } 2044 2045 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2046 dpcd_set_source_specific_data(link); 2047 if (link->dpcd_sink_ext_caps.raw != 0) { 2048 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2049 msleep(post_oui_delay); 2050 } 2051 2052 // similarly, mode switch can cause loss of cable ID 2053 dpcd_write_cable_id_to_dprx(link); 2054 2055 skip_video_pattern = true; 2056 2057 if (link_settings->link_rate == LINK_RATE_LOW) 2058 skip_video_pattern = false; 2059 2060 if (perform_link_training_with_retries(link_settings, 2061 skip_video_pattern, 2062 lt_attempts, 2063 pipe_ctx, 2064 pipe_ctx->stream->signal, 2065 do_fallback)) { 2066 status = DC_OK; 2067 } else { 2068 status = DC_FAIL_DP_LINK_TRAINING; 2069 } 2070 2071 if (link->preferred_training_settings.fec_enable) 2072 fec_enable = *link->preferred_training_settings.fec_enable; 2073 else 2074 fec_enable = true; 2075 2076 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2077 dp_set_fec_enable(link, fec_enable); 2078 2079 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2080 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2081 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2082 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2083 set_default_brightness_aux(link); 2084 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2085 msleep(bl_oled_enable_delay); 2086 edp_backlight_enable_aux(link, true); 2087 } 2088 2089 return status; 2090 } 2091 2092 static enum dc_status enable_link_edp( 2093 struct dc_state *state, 2094 struct pipe_ctx *pipe_ctx) 2095 { 2096 return enable_link_dp(state, pipe_ctx); 2097 } 2098 2099 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2100 { 2101 struct dc_stream_state *stream = pipe_ctx->stream; 2102 struct dc_link *link = stream->link; 2103 struct dc *dc = stream->ctx->dc; 2104 2105 if (stream->phy_pix_clk == 0) 2106 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2107 2108 memset(&stream->link->cur_link_settings, 0, 2109 sizeof(struct dc_link_settings)); 2110 dc->hwss.enable_lvds_link_output( 2111 link, 2112 &pipe_ctx->link_res, 2113 pipe_ctx->clock_source->id, 2114 stream->phy_pix_clk); 2115 2116 } 2117 2118 static enum dc_status enable_link_dp_mst( 2119 struct dc_state *state, 2120 struct pipe_ctx *pipe_ctx) 2121 { 2122 struct dc_link *link = pipe_ctx->stream->link; 2123 unsigned char mstm_cntl = 0; 2124 2125 /* sink signal type after MST branch is MST. Multiple MST sinks 2126 * share one link. Link DP PHY is enable or training only once. 2127 */ 2128 if (link->link_status.link_active) 2129 return DC_OK; 2130 2131 /* clear payload table */ 2132 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2133 if (mstm_cntl & DP_MST_EN) 2134 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2135 2136 /* to make sure the pending down rep can be processed 2137 * before enabling the link 2138 */ 2139 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2140 2141 /* set the sink to MST mode before enabling the link */ 2142 enable_mst_on_sink(link, true); 2143 2144 return enable_link_dp(state, pipe_ctx); 2145 } 2146 2147 static enum dc_status enable_link( 2148 struct dc_state *state, 2149 struct pipe_ctx *pipe_ctx) 2150 { 2151 enum dc_status status = DC_ERROR_UNEXPECTED; 2152 struct dc_stream_state *stream = pipe_ctx->stream; 2153 struct dc_link *link = stream->link; 2154 2155 /* There's some scenarios where driver is unloaded with display 2156 * still enabled. When driver is reloaded, it may cause a display 2157 * to not light up if there is a mismatch between old and new 2158 * link settings. Need to call disable first before enabling at 2159 * new link settings. 2160 */ 2161 if (link->link_status.link_active) 2162 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2163 2164 switch (pipe_ctx->stream->signal) { 2165 case SIGNAL_TYPE_DISPLAY_PORT: 2166 status = enable_link_dp(state, pipe_ctx); 2167 break; 2168 case SIGNAL_TYPE_EDP: 2169 status = enable_link_edp(state, pipe_ctx); 2170 break; 2171 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2172 status = enable_link_dp_mst(state, pipe_ctx); 2173 msleep(200); 2174 break; 2175 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2176 case SIGNAL_TYPE_DVI_DUAL_LINK: 2177 case SIGNAL_TYPE_HDMI_TYPE_A: 2178 enable_link_hdmi(pipe_ctx); 2179 status = DC_OK; 2180 break; 2181 case SIGNAL_TYPE_LVDS: 2182 enable_link_lvds(pipe_ctx); 2183 status = DC_OK; 2184 break; 2185 case SIGNAL_TYPE_VIRTUAL: 2186 status = DC_OK; 2187 break; 2188 default: 2189 break; 2190 } 2191 2192 if (status == DC_OK) { 2193 pipe_ctx->stream->link->link_status.link_active = true; 2194 } 2195 2196 return status; 2197 } 2198 2199 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2200 { 2201 struct dc_link *link = stream->sink->link; 2202 int req_bw = bw; 2203 2204 DC_LOGGER_INIT(link->ctx->logger); 2205 2206 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2207 return false; 2208 2209 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2210 int sink_index = 0; 2211 int i = 0; 2212 2213 for (i = 0; i < link->sink_count; i++) { 2214 if (link->remote_sinks[i] == NULL) 2215 continue; 2216 2217 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2218 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2219 else 2220 sink_index = i; 2221 } 2222 2223 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2224 } 2225 2226 /* get dp overhead for dp tunneling */ 2227 link->dpia_bw_alloc_config.dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(link); 2228 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2229 2230 if (link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw)) { 2231 if (req_bw <= link->dpia_bw_alloc_config.allocated_bw) { 2232 DC_LOG_DEBUG("%s, Success in allocate bw for link(%d), allocated_bw(%d), dp_overhead(%d)\n", 2233 __func__, link->link_index, link->dpia_bw_alloc_config.allocated_bw, 2234 link->dpia_bw_alloc_config.dp_overhead); 2235 } else { 2236 // Cannot get the required bandwidth. 2237 DC_LOG_ERROR("%s, Failed to allocate bw for link(%d), allocated_bw(%d), dp_overhead(%d)\n", 2238 __func__, link->link_index, link->dpia_bw_alloc_config.allocated_bw, 2239 link->dpia_bw_alloc_config.dp_overhead); 2240 return false; 2241 } 2242 } else { 2243 DC_LOG_DEBUG("%s, usb4 request bw timeout\n", __func__); 2244 return false; 2245 } 2246 2247 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2248 int i = 0; 2249 2250 for (i = 0; i < link->sink_count; i++) { 2251 if (link->remote_sinks[i] == NULL) 2252 continue; 2253 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2254 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2255 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2256 } 2257 } 2258 2259 return true; 2260 } 2261 2262 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2263 { 2264 bool ret; 2265 2266 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2267 dc_link_get_highest_encoding_format(stream->sink->link)); 2268 2269 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2270 2271 return ret; 2272 } 2273 2274 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2275 { 2276 bool ret; 2277 2278 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2279 2280 return ret; 2281 } 2282 2283 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2284 { 2285 struct dc *dc = pipe_ctx->stream->ctx->dc; 2286 struct dc_stream_state *stream = pipe_ctx->stream; 2287 struct dc_link *link = stream->sink->link; 2288 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2289 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2290 2291 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2292 2293 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2294 2295 if (dp_is_128b_132b_signal(pipe_ctx)) 2296 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2297 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2298 return; 2299 2300 if (pipe_ctx->stream->sink) { 2301 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2302 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2303 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2304 pipe_ctx->stream->sink->edid_caps.display_name, 2305 pipe_ctx->stream->signal); 2306 } 2307 } 2308 2309 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2310 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2311 set_avmute(pipe_ctx, true); 2312 } 2313 2314 dc->hwss.disable_audio_stream(pipe_ctx); 2315 2316 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2317 2318 update_psp_stream_config(pipe_ctx, true); 2319 dc->hwss.blank_stream(pipe_ctx); 2320 2321 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2322 deallocate_usb4_bandwidth(pipe_ctx->stream); 2323 2324 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2325 deallocate_mst_payload(pipe_ctx); 2326 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2327 dp_is_128b_132b_signal(pipe_ctx)) 2328 update_sst_payload(pipe_ctx, false); 2329 2330 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2331 struct ext_hdmi_settings settings = {0}; 2332 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2333 2334 unsigned short masked_chip_caps = link->chip_caps & 2335 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2336 //Need to inform that sink is going to use legacy HDMI mode. 2337 write_scdc_data( 2338 link->ddc, 2339 165000,//vbios only handles 165Mhz. 2340 false); 2341 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2342 /* DP159, Retimer settings */ 2343 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2344 write_i2c_retimer_setting(pipe_ctx, 2345 false, false, &settings); 2346 else 2347 write_i2c_default_retimer_setting(pipe_ctx, 2348 false, false); 2349 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2350 /* PI3EQX1204, Redriver settings */ 2351 write_i2c_redriver_setting(pipe_ctx, false); 2352 } 2353 } 2354 2355 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2356 !dp_is_128b_132b_signal(pipe_ctx)) { 2357 2358 /* In DP1.x SST mode, our encoder will go to TPS1 2359 * when link is on but stream is off. 2360 * Disabling link before stream will avoid exposing TPS1 pattern 2361 * during the disable sequence as it will confuse some receivers 2362 * state machine. 2363 * In DP2 or MST mode, our encoder will stay video active 2364 */ 2365 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2366 dc->hwss.disable_stream(pipe_ctx); 2367 } else { 2368 dc->hwss.disable_stream(pipe_ctx); 2369 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2370 } 2371 2372 if (pipe_ctx->stream->timing.flags.DSC) { 2373 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2374 link_set_dsc_enable(pipe_ctx, false); 2375 } 2376 if (dp_is_128b_132b_signal(pipe_ctx)) { 2377 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2378 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2379 } 2380 2381 if (vpg && vpg->funcs->vpg_powerdown) 2382 vpg->funcs->vpg_powerdown(vpg); 2383 2384 /* for psp not exist case */ 2385 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2386 /* reset internal save state to default since eDP is off */ 2387 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2388 /* since current psp not loaded, we need to reset it to default*/ 2389 link->panel_mode = panel_mode; 2390 } 2391 } 2392 2393 void link_set_dpms_on( 2394 struct dc_state *state, 2395 struct pipe_ctx *pipe_ctx) 2396 { 2397 struct dc *dc = pipe_ctx->stream->ctx->dc; 2398 struct dc_stream_state *stream = pipe_ctx->stream; 2399 struct dc_link *link = stream->sink->link; 2400 enum dc_status status; 2401 struct link_encoder *link_enc; 2402 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2403 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2404 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2405 bool apply_edp_fast_boot_optimization = 2406 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2407 2408 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2409 2410 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2411 2412 if (dp_is_128b_132b_signal(pipe_ctx)) 2413 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2414 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2415 return; 2416 2417 if (pipe_ctx->stream->sink) { 2418 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2419 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2420 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2421 pipe_ctx->stream->sink->edid_caps.display_name, 2422 pipe_ctx->stream->signal); 2423 } 2424 } 2425 2426 link_enc = link_enc_cfg_get_link_enc(link); 2427 ASSERT(link_enc); 2428 2429 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2430 && !dp_is_128b_132b_signal(pipe_ctx)) { 2431 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2432 2433 if (link_enc) 2434 link_enc->funcs->setup( 2435 link_enc, 2436 pipe_ctx->stream->signal); 2437 2438 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2439 stream_enc->funcs->dig_stream_enable( 2440 stream_enc, 2441 pipe_ctx->stream->signal, 1); 2442 } 2443 2444 pipe_ctx->stream->link->link_state_valid = true; 2445 2446 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2447 if (dp_is_128b_132b_signal(pipe_ctx)) 2448 otg_out_dest = OUT_MUX_HPO_DP; 2449 else 2450 otg_out_dest = OUT_MUX_DIO; 2451 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2452 } 2453 2454 link_hwss->setup_stream_attribute(pipe_ctx); 2455 2456 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2457 2458 // Enable VPG before building infoframe 2459 if (vpg && vpg->funcs->vpg_poweron) 2460 vpg->funcs->vpg_poweron(vpg); 2461 2462 resource_build_info_frame(pipe_ctx); 2463 dc->hwss.update_info_frame(pipe_ctx); 2464 2465 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2466 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2467 2468 /* Do not touch link on seamless boot optimization. */ 2469 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2470 pipe_ctx->stream->dpms_off = false; 2471 2472 /* Still enable stream features & audio on seamless boot for DP external displays */ 2473 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2474 enable_stream_features(pipe_ctx); 2475 dc->hwss.enable_audio_stream(pipe_ctx); 2476 } 2477 2478 update_psp_stream_config(pipe_ctx, false); 2479 return; 2480 } 2481 2482 /* eDP lit up by bios already, no need to enable again. */ 2483 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2484 apply_edp_fast_boot_optimization && 2485 !pipe_ctx->stream->timing.flags.DSC && 2486 !pipe_ctx->next_odm_pipe) { 2487 pipe_ctx->stream->dpms_off = false; 2488 update_psp_stream_config(pipe_ctx, false); 2489 return; 2490 } 2491 2492 if (pipe_ctx->stream->dpms_off) 2493 return; 2494 2495 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2496 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2497 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2498 * will be automatically set at a later time when the video is enabled 2499 * (DP_VID_STREAM_EN = 1). 2500 */ 2501 if (pipe_ctx->stream->timing.flags.DSC) { 2502 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2503 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2504 link_set_dsc_enable(pipe_ctx, true); 2505 } 2506 2507 status = enable_link(state, pipe_ctx); 2508 2509 if (status != DC_OK) { 2510 DC_LOG_WARNING("enabling link %u failed: %d\n", 2511 pipe_ctx->stream->link->link_index, 2512 status); 2513 2514 /* Abort stream enable *unless* the failure was due to 2515 * DP link training - some DP monitors will recover and 2516 * show the stream anyway. But MST displays can't proceed 2517 * without link training. 2518 */ 2519 if (status != DC_FAIL_DP_LINK_TRAINING || 2520 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2521 if (false == stream->link->link_status.link_active) 2522 disable_link(stream->link, &pipe_ctx->link_res, 2523 pipe_ctx->stream->signal); 2524 BREAK_TO_DEBUGGER(); 2525 return; 2526 } 2527 } 2528 2529 /* turn off otg test pattern if enable */ 2530 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2531 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2532 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2533 COLOR_DEPTH_UNDEFINED); 2534 2535 /* This second call is needed to reconfigure the DIG 2536 * as a workaround for the incorrect value being applied 2537 * from transmitter control. 2538 */ 2539 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2540 dp_is_128b_132b_signal(pipe_ctx))) { 2541 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2542 2543 if (link_enc) 2544 link_enc->funcs->setup( 2545 link_enc, 2546 pipe_ctx->stream->signal); 2547 2548 if (stream_enc && stream_enc->funcs->dig_stream_enable) 2549 stream_enc->funcs->dig_stream_enable( 2550 stream_enc, 2551 pipe_ctx->stream->signal, 1); 2552 2553 } 2554 2555 dc->hwss.enable_stream(pipe_ctx); 2556 2557 /* Set DPS PPS SDP (AKA "info frames") */ 2558 if (pipe_ctx->stream->timing.flags.DSC) { 2559 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2560 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2561 dp_set_dsc_on_rx(pipe_ctx, true); 2562 link_set_dsc_pps_packet(pipe_ctx, true, true); 2563 } 2564 } 2565 2566 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2567 allocate_usb4_bandwidth(pipe_ctx->stream); 2568 2569 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2570 allocate_mst_payload(pipe_ctx); 2571 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2572 dp_is_128b_132b_signal(pipe_ctx)) 2573 update_sst_payload(pipe_ctx, true); 2574 2575 dc->hwss.unblank_stream(pipe_ctx, 2576 &pipe_ctx->stream->link->cur_link_settings); 2577 2578 if (stream->sink_patches.delay_ignore_msa > 0) 2579 msleep(stream->sink_patches.delay_ignore_msa); 2580 2581 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2582 enable_stream_features(pipe_ctx); 2583 update_psp_stream_config(pipe_ctx, false); 2584 2585 dc->hwss.enable_audio_stream(pipe_ctx); 2586 2587 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2588 set_avmute(pipe_ctx, false); 2589 } 2590 } 2591