1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file manages link detection states and receiver states by using various 28 * link protocols. It also provides helper functions to interpret certain 29 * capabilities or status based on the states it manages or retrieve them 30 * directly from connected receivers. 31 */ 32 33 #include "link_dpms.h" 34 #include "link_detection.h" 35 #include "link_hwss.h" 36 #include "protocols/link_edp_panel_control.h" 37 #include "protocols/link_ddc.h" 38 #include "protocols/link_hpd.h" 39 #include "protocols/link_dpcd.h" 40 #include "protocols/link_dp_capability.h" 41 #include "protocols/link_dp_dpia.h" 42 #include "protocols/link_dp_phy.h" 43 #include "protocols/link_dp_training.h" 44 #include "accessories/link_dp_trace.h" 45 46 #include "link_enc_cfg.h" 47 #include "dm_helpers.h" 48 #include "clk_mgr.h" 49 50 #define DC_LOGGER_INIT(logger) 51 52 #define LINK_INFO(...) \ 53 DC_LOG_HW_HOTPLUG( \ 54 __VA_ARGS__) 55 /* 56 * Some receivers fail to train on first try and are good 57 * on subsequent tries. 2 retries should be plenty. If we 58 * don't have a successful training then we don't expect to 59 * ever get one. 60 */ 61 #define LINK_TRAINING_MAX_VERIFY_RETRY 2 62 63 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal) 64 { 65 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE; 66 67 switch (sink_signal) { 68 case SIGNAL_TYPE_DVI_SINGLE_LINK: 69 case SIGNAL_TYPE_DVI_DUAL_LINK: 70 case SIGNAL_TYPE_HDMI_TYPE_A: 71 case SIGNAL_TYPE_LVDS: 72 case SIGNAL_TYPE_RGB: 73 transaction_type = DDC_TRANSACTION_TYPE_I2C; 74 break; 75 76 case SIGNAL_TYPE_DISPLAY_PORT: 77 case SIGNAL_TYPE_EDP: 78 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 79 break; 80 81 case SIGNAL_TYPE_DISPLAY_PORT_MST: 82 /* MST does not use I2COverAux, but there is the 83 * SPECIAL use case for "immediate dwnstrm device 84 * access" (EPR#370830). 85 */ 86 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 87 break; 88 89 default: 90 break; 91 } 92 93 return transaction_type; 94 } 95 96 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder, 97 struct graphics_object_id downstream) 98 { 99 if (downstream.type == OBJECT_TYPE_CONNECTOR) { 100 switch (downstream.id) { 101 case CONNECTOR_ID_SINGLE_LINK_DVII: 102 switch (encoder.id) { 103 case ENCODER_ID_INTERNAL_DAC1: 104 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 105 case ENCODER_ID_INTERNAL_DAC2: 106 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 107 return SIGNAL_TYPE_RGB; 108 default: 109 return SIGNAL_TYPE_DVI_SINGLE_LINK; 110 } 111 break; 112 case CONNECTOR_ID_DUAL_LINK_DVII: 113 { 114 switch (encoder.id) { 115 case ENCODER_ID_INTERNAL_DAC1: 116 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 117 case ENCODER_ID_INTERNAL_DAC2: 118 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 119 return SIGNAL_TYPE_RGB; 120 default: 121 return SIGNAL_TYPE_DVI_DUAL_LINK; 122 } 123 } 124 break; 125 case CONNECTOR_ID_SINGLE_LINK_DVID: 126 return SIGNAL_TYPE_DVI_SINGLE_LINK; 127 case CONNECTOR_ID_DUAL_LINK_DVID: 128 return SIGNAL_TYPE_DVI_DUAL_LINK; 129 case CONNECTOR_ID_VGA: 130 return SIGNAL_TYPE_RGB; 131 case CONNECTOR_ID_HDMI_TYPE_A: 132 return SIGNAL_TYPE_HDMI_TYPE_A; 133 case CONNECTOR_ID_LVDS: 134 return SIGNAL_TYPE_LVDS; 135 case CONNECTOR_ID_DISPLAY_PORT: 136 case CONNECTOR_ID_USBC: 137 return SIGNAL_TYPE_DISPLAY_PORT; 138 case CONNECTOR_ID_EDP: 139 return SIGNAL_TYPE_EDP; 140 default: 141 return SIGNAL_TYPE_NONE; 142 } 143 } else if (downstream.type == OBJECT_TYPE_ENCODER) { 144 switch (downstream.id) { 145 case ENCODER_ID_EXTERNAL_NUTMEG: 146 case ENCODER_ID_EXTERNAL_TRAVIS: 147 return SIGNAL_TYPE_DISPLAY_PORT; 148 default: 149 return SIGNAL_TYPE_NONE; 150 } 151 } 152 153 return SIGNAL_TYPE_NONE; 154 } 155 156 /* 157 * @brief 158 * Detect output sink type 159 */ 160 static enum signal_type link_detect_sink_signal_type(struct dc_link *link, 161 enum dc_detect_reason reason) 162 { 163 enum signal_type result; 164 struct graphics_object_id enc_id; 165 166 if (link->is_dig_mapping_flexible) 167 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN}; 168 else 169 enc_id = link->link_enc->id; 170 result = get_basic_signal_type(enc_id, link->link_id); 171 172 /* Use basic signal type for link without physical connector. */ 173 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 174 return result; 175 176 /* Internal digital encoder will detect only dongles 177 * that require digital signal 178 */ 179 180 /* Detection mechanism is different 181 * for different native connectors. 182 * LVDS connector supports only LVDS signal; 183 * PCIE is a bus slot, the actual connector needs to be detected first; 184 * eDP connector supports only eDP signal; 185 * HDMI should check straps for audio 186 */ 187 188 /* PCIE detects the actual connector on add-on board */ 189 if (link->link_id.id == CONNECTOR_ID_PCIE) { 190 /* ZAZTODO implement PCIE add-on card detection */ 191 } 192 193 switch (link->link_id.id) { 194 case CONNECTOR_ID_HDMI_TYPE_A: { 195 /* check audio support: 196 * if native HDMI is not supported, switch to DVI 197 */ 198 struct audio_support *aud_support = 199 &link->dc->res_pool->audio_support; 200 201 if (!aud_support->hdmi_audio_native) 202 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A) 203 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 204 } 205 break; 206 case CONNECTOR_ID_DISPLAY_PORT: 207 case CONNECTOR_ID_USBC: { 208 /* DP HPD short pulse. Passive DP dongle will not 209 * have short pulse 210 */ 211 if (reason != DETECT_REASON_HPDRX) { 212 /* Check whether DP signal detected: if not - 213 * we assume signal is DVI; it could be corrected 214 * to HDMI after dongle detection 215 */ 216 if (!dm_helpers_is_dp_sink_present(link)) 217 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 218 } 219 } 220 break; 221 default: 222 break; 223 } 224 225 return result; 226 } 227 228 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type, 229 struct audio_support *audio_support) 230 { 231 enum signal_type signal = SIGNAL_TYPE_NONE; 232 233 switch (dongle_type) { 234 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 235 if (audio_support->hdmi_audio_on_dongle) 236 signal = SIGNAL_TYPE_HDMI_TYPE_A; 237 else 238 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 239 break; 240 case DISPLAY_DONGLE_DP_DVI_DONGLE: 241 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 242 break; 243 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 244 if (audio_support->hdmi_audio_native) 245 signal = SIGNAL_TYPE_HDMI_TYPE_A; 246 else 247 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 248 break; 249 default: 250 signal = SIGNAL_TYPE_NONE; 251 break; 252 } 253 254 return signal; 255 } 256 257 static void read_scdc_caps(struct ddc_service *ddc_service, 258 struct dc_sink *sink) 259 { 260 uint8_t slave_address = HDMI_SCDC_ADDRESS; 261 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI; 262 263 link_query_ddc_data(ddc_service, slave_address, &offset, 264 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte, 265 sizeof(sink->scdc_caps.manufacturer_OUI.byte)); 266 267 offset = HDMI_SCDC_DEVICE_ID; 268 269 link_query_ddc_data(ddc_service, slave_address, &offset, 270 sizeof(offset), &(sink->scdc_caps.device_id.byte), 271 sizeof(sink->scdc_caps.device_id.byte)); 272 } 273 274 static bool i2c_read( 275 struct ddc_service *ddc, 276 uint32_t address, 277 uint8_t *buffer, 278 uint32_t len) 279 { 280 uint8_t offs_data = 0; 281 struct i2c_payload payloads[2] = { 282 { 283 .write = true, 284 .address = address, 285 .length = 1, 286 .data = &offs_data }, 287 { 288 .write = false, 289 .address = address, 290 .length = len, 291 .data = buffer } }; 292 293 struct i2c_command command = { 294 .payloads = payloads, 295 .number_of_payloads = 2, 296 .engine = DDC_I2C_COMMAND_ENGINE, 297 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz }; 298 299 return dm_helpers_submit_i2c( 300 ddc->ctx, 301 ddc->link, 302 &command); 303 } 304 305 enum { 306 DP_SINK_CAP_SIZE = 307 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1 308 }; 309 310 static void query_dp_dual_mode_adaptor( 311 struct ddc_service *ddc, 312 struct display_sink_capability *sink_cap) 313 { 314 uint8_t i; 315 bool is_valid_hdmi_signature; 316 enum display_dongle_type *dongle = &sink_cap->dongle_type; 317 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE]; 318 bool is_type2_dongle = false; 319 int retry_count = 2; 320 struct dp_hdmi_dongle_signature_data *dongle_signature; 321 322 /* Assume we have no valid DP passive dongle connected */ 323 *dongle = DISPLAY_DONGLE_NONE; 324 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK; 325 326 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/ 327 if (!i2c_read( 328 ddc, 329 DP_HDMI_DONGLE_ADDRESS, 330 type2_dongle_buf, 331 sizeof(type2_dongle_buf))) { 332 /* Passive HDMI dongles can sometimes fail here without retrying*/ 333 while (retry_count > 0) { 334 if (i2c_read(ddc, 335 DP_HDMI_DONGLE_ADDRESS, 336 type2_dongle_buf, 337 sizeof(type2_dongle_buf))) 338 break; 339 retry_count--; 340 } 341 if (retry_count == 0) { 342 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 343 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; 344 345 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf), 346 "DP-DVI passive dongle %dMhz: ", 347 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 348 return; 349 } 350 } 351 352 /* Check if Type 2 dongle.*/ 353 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID) 354 is_type2_dongle = true; 355 356 dongle_signature = 357 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf; 358 359 is_valid_hdmi_signature = true; 360 361 /* Check EOT */ 362 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) { 363 is_valid_hdmi_signature = false; 364 } 365 366 /* Check signature */ 367 for (i = 0; i < sizeof(dongle_signature->id); ++i) { 368 /* If its not the right signature, 369 * skip mismatch in subversion byte.*/ 370 if (dongle_signature->id[i] != 371 dp_hdmi_dongle_signature_str[i] && i != 3) { 372 373 if (is_type2_dongle) { 374 is_valid_hdmi_signature = false; 375 break; 376 } 377 378 } 379 } 380 381 if (is_type2_dongle) { 382 uint32_t max_tmds_clk = 383 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK]; 384 385 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2; 386 387 if (0 == max_tmds_clk || 388 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK || 389 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) { 390 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 391 392 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 393 sizeof(type2_dongle_buf), 394 "DP-DVI passive dongle %dMhz: ", 395 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 396 } else { 397 if (is_valid_hdmi_signature == true) { 398 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 399 400 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 401 sizeof(type2_dongle_buf), 402 "Type 2 DP-HDMI passive dongle %dMhz: ", 403 max_tmds_clk); 404 } else { 405 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 406 407 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 408 sizeof(type2_dongle_buf), 409 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ", 410 max_tmds_clk); 411 412 } 413 414 /* Multiply by 1000 to convert to kHz. */ 415 sink_cap->max_hdmi_pixel_clock = 416 max_tmds_clk * 1000; 417 } 418 sink_cap->is_dongle_type_one = false; 419 420 } else { 421 if (is_valid_hdmi_signature == true) { 422 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 423 424 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 425 sizeof(type2_dongle_buf), 426 "Type 1 DP-HDMI passive dongle %dMhz: ", 427 sink_cap->max_hdmi_pixel_clock / 1000); 428 } else { 429 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 430 431 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 432 sizeof(type2_dongle_buf), 433 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ", 434 sink_cap->max_hdmi_pixel_clock / 1000); 435 } 436 sink_cap->is_dongle_type_one = true; 437 } 438 439 return; 440 } 441 442 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc, 443 struct display_sink_capability *sink_cap, 444 struct audio_support *audio_support) 445 { 446 query_dp_dual_mode_adaptor(ddc, sink_cap); 447 448 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type, 449 audio_support); 450 } 451 452 static void link_disconnect_sink(struct dc_link *link) 453 { 454 if (link->local_sink) { 455 dc_sink_release(link->local_sink); 456 link->local_sink = NULL; 457 } 458 459 link->dpcd_sink_count = 0; 460 //link->dpcd_caps.dpcd_rev.raw = 0; 461 } 462 463 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link) 464 { 465 dc_sink_release(link->local_sink); 466 link->local_sink = prev_sink; 467 } 468 469 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link) 470 { 471 struct hdcp_protection_message msg22; 472 struct hdcp_protection_message msg14; 473 474 memset(&msg22, 0, sizeof(struct hdcp_protection_message)); 475 memset(&msg14, 0, sizeof(struct hdcp_protection_message)); 476 memset(link->hdcp_caps.rx_caps.raw, 0, 477 sizeof(link->hdcp_caps.rx_caps.raw)); 478 479 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 480 link->ddc->transaction_type == 481 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) || 482 link->connector_signal == SIGNAL_TYPE_EDP) { 483 msg22.data = link->hdcp_caps.rx_caps.raw; 484 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw); 485 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS; 486 } else { 487 msg22.data = &link->hdcp_caps.rx_caps.fields.version; 488 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version); 489 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION; 490 } 491 msg22.version = HDCP_VERSION_22; 492 msg22.link = HDCP_LINK_PRIMARY; 493 msg22.max_retries = 5; 494 dc_process_hdcp_msg(signal, link, &msg22); 495 496 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 497 enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED; 498 499 msg14.data = &link->hdcp_caps.bcaps.raw; 500 msg14.length = sizeof(link->hdcp_caps.bcaps.raw); 501 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS; 502 msg14.version = HDCP_VERSION_14; 503 msg14.link = HDCP_LINK_PRIMARY; 504 msg14.max_retries = 5; 505 506 status = dc_process_hdcp_msg(signal, link, &msg14); 507 } 508 509 } 510 static void read_current_link_settings_on_detect(struct dc_link *link) 511 { 512 union lane_count_set lane_count_set = {0}; 513 uint8_t link_bw_set; 514 uint8_t link_rate_set; 515 uint32_t read_dpcd_retry_cnt = 10; 516 enum dc_status status = DC_ERROR_UNEXPECTED; 517 int i; 518 union max_down_spread max_down_spread = {0}; 519 520 // Read DPCD 00101h to find out the number of lanes currently set 521 for (i = 0; i < read_dpcd_retry_cnt; i++) { 522 status = core_link_read_dpcd(link, 523 DP_LANE_COUNT_SET, 524 &lane_count_set.raw, 525 sizeof(lane_count_set)); 526 /* First DPCD read after VDD ON can fail if the particular board 527 * does not have HPD pin wired correctly. So if DPCD read fails, 528 * which it should never happen, retry a few times. Target worst 529 * case scenario of 80 ms. 530 */ 531 if (status == DC_OK) { 532 link->cur_link_settings.lane_count = 533 lane_count_set.bits.LANE_COUNT_SET; 534 break; 535 } 536 537 msleep(8); 538 } 539 540 // Read DPCD 00100h to find if standard link rates are set 541 core_link_read_dpcd(link, DP_LINK_BW_SET, 542 &link_bw_set, sizeof(link_bw_set)); 543 544 if (link_bw_set == 0) { 545 if (link->connector_signal == SIGNAL_TYPE_EDP) { 546 /* If standard link rates are not being used, 547 * Read DPCD 00115h to find the edp link rate set used 548 */ 549 core_link_read_dpcd(link, DP_LINK_RATE_SET, 550 &link_rate_set, sizeof(link_rate_set)); 551 552 // edp_supported_link_rates_count = 0 for DP 553 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 554 link->cur_link_settings.link_rate = 555 link->dpcd_caps.edp_supported_link_rates[link_rate_set]; 556 link->cur_link_settings.link_rate_set = link_rate_set; 557 link->cur_link_settings.use_link_rate_set = true; 558 } 559 } else { 560 // Link Rate not found. Seamless boot may not work. 561 ASSERT(false); 562 } 563 } else { 564 link->cur_link_settings.link_rate = link_bw_set; 565 link->cur_link_settings.use_link_rate_set = false; 566 } 567 // Read DPCD 00003h to find the max down spread. 568 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD, 569 &max_down_spread.raw, sizeof(max_down_spread)); 570 link->cur_link_settings.link_spread = 571 max_down_spread.bits.MAX_DOWN_SPREAD ? 572 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 573 } 574 575 static bool detect_dp(struct dc_link *link, 576 struct display_sink_capability *sink_caps, 577 enum dc_detect_reason reason) 578 { 579 struct audio_support *audio_support = &link->dc->res_pool->audio_support; 580 581 sink_caps->signal = link_detect_sink_signal_type(link, reason); 582 sink_caps->transaction_type = 583 get_ddc_transaction_type(sink_caps->signal); 584 585 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 586 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; 587 if (!detect_dp_sink_caps(link)) 588 return false; 589 590 if (is_dp_branch_device(link)) 591 /* DP SST branch */ 592 link->type = dc_connection_sst_branch; 593 } else { 594 /* DP passive dongles */ 595 sink_caps->signal = dp_passive_dongle_detection(link->ddc, 596 sink_caps, 597 audio_support); 598 link->dpcd_caps.dongle_type = sink_caps->dongle_type; 599 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one; 600 link->dpcd_caps.dpcd_rev.raw = 0; 601 } 602 603 return true; 604 } 605 606 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid) 607 { 608 if (old_edid->length != new_edid->length) 609 return false; 610 611 if (new_edid->length == 0) 612 return false; 613 614 return (memcmp(old_edid->raw_edid, 615 new_edid->raw_edid, new_edid->length) == 0); 616 } 617 618 static bool wait_for_entering_dp_alt_mode(struct dc_link *link) 619 { 620 621 /** 622 * something is terribly wrong if time out is > 200ms. (5Hz) 623 * 500 microseconds * 400 tries us 200 ms 624 **/ 625 unsigned int sleep_time_in_microseconds = 500; 626 unsigned int tries_allowed = 400; 627 bool is_in_alt_mode; 628 unsigned long long enter_timestamp; 629 unsigned long long finish_timestamp; 630 unsigned long long time_taken_in_ns; 631 int tries_taken; 632 633 DC_LOGGER_INIT(link->ctx->logger); 634 635 /** 636 * this function will only exist if we are on dcn21 (is_in_alt_mode is a 637 * function pointer, so checking to see if it is equal to 0 is the same 638 * as checking to see if it is null 639 **/ 640 if (!link->link_enc->funcs->is_in_alt_mode) 641 return true; 642 643 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc); 644 DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode); 645 646 if (is_in_alt_mode) 647 return true; 648 649 enter_timestamp = dm_get_timestamp(link->ctx); 650 651 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) { 652 udelay(sleep_time_in_microseconds); 653 /* ask the link if alt mode is enabled, if so return ok */ 654 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) { 655 finish_timestamp = dm_get_timestamp(link->ctx); 656 time_taken_in_ns = 657 dm_get_elapse_time_in_ns(link->ctx, 658 finish_timestamp, 659 enter_timestamp); 660 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n", 661 div_u64(time_taken_in_ns, 1000000)); 662 return true; 663 } 664 } 665 finish_timestamp = dm_get_timestamp(link->ctx); 666 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, 667 enter_timestamp); 668 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n", 669 div_u64(time_taken_in_ns, 1000000)); 670 return false; 671 } 672 673 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link) 674 { 675 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock 676 * reports DSC support. 677 */ 678 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 679 link->type == dc_connection_mst_branch && 680 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 681 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 && 682 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 683 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) 684 link->wa_flags.dpia_mst_dsc_always_on = true; 685 } 686 687 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link) 688 { 689 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */ 690 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 691 link->wa_flags.dpia_mst_dsc_always_on = false; 692 } 693 694 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason) 695 { 696 DC_LOGGER_INIT(link->ctx->logger); 697 698 LINK_INFO("link=%d, mst branch is now Connected\n", 699 link->link_index); 700 701 link->type = dc_connection_mst_branch; 702 apply_dpia_mst_dsc_always_on_wa(link); 703 704 dm_helpers_dp_update_branch_info(link->ctx, link); 705 if (dm_helpers_dp_mst_start_top_mgr(link->ctx, 706 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) { 707 link_disconnect_sink(link); 708 } else { 709 link->type = dc_connection_sst_branch; 710 } 711 712 return link->type == dc_connection_mst_branch; 713 } 714 715 bool link_reset_cur_dp_mst_topology(struct dc_link *link) 716 { 717 DC_LOGGER_INIT(link->ctx->logger); 718 719 LINK_INFO("link=%d, mst branch is now Disconnected\n", 720 link->link_index); 721 722 revert_dpia_mst_dsc_always_on_wa(link); 723 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); 724 } 725 726 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc, 727 enum dc_detect_reason reason) 728 { 729 int i; 730 bool can_apply_seamless_boot = false; 731 732 for (i = 0; i < dc->current_state->stream_count; i++) { 733 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) { 734 can_apply_seamless_boot = true; 735 break; 736 } 737 } 738 739 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT; 740 } 741 742 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc) 743 { 744 dc_z10_restore(dc); 745 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 746 } 747 748 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc) 749 { 750 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 751 } 752 753 static void verify_link_capability_destructive(struct dc_link *link, 754 struct dc_sink *sink, 755 enum dc_detect_reason reason) 756 { 757 bool should_prepare_phy_clocks = 758 should_prepare_phy_clocks_for_link_verification(link->dc, reason); 759 760 if (should_prepare_phy_clocks) 761 prepare_phy_clocks_for_destructive_link_verification(link->dc); 762 763 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 764 struct dc_link_settings known_limit_link_setting = 765 dp_get_max_link_cap(link); 766 link_set_all_streams_dpms_off_for_link(link); 767 dp_verify_link_cap_with_retries( 768 link, &known_limit_link_setting, 769 LINK_TRAINING_MAX_VERIFY_RETRY); 770 } else { 771 ASSERT(0); 772 } 773 774 if (should_prepare_phy_clocks) 775 restore_phy_clocks_for_destructive_link_verification(link->dc); 776 } 777 778 static void verify_link_capability_non_destructive(struct dc_link *link) 779 { 780 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 781 if (dc_is_embedded_signal(link->local_sink->sink_signal) || 782 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 783 /* TODO - should we check link encoder's max link caps here? 784 * How do we know which link encoder to check from? 785 */ 786 link->verified_link_cap = link->reported_link_cap; 787 else 788 link->verified_link_cap = dp_get_max_link_cap(link); 789 } 790 } 791 792 static bool should_verify_link_capability_destructively(struct dc_link *link, 793 enum dc_detect_reason reason) 794 { 795 bool destrictive = false; 796 struct dc_link_settings max_link_cap; 797 bool is_link_enc_unavailable = link->link_enc && 798 link->dc->res_pool->funcs->link_encs_assign && 799 !link_enc_cfg_is_link_enc_avail( 800 link->ctx->dc, 801 link->link_enc->preferred_engine, 802 link); 803 804 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 805 max_link_cap = dp_get_max_link_cap(link); 806 destrictive = true; 807 808 if (link->dc->debug.skip_detection_link_training || 809 dc_is_embedded_signal(link->local_sink->sink_signal) || 810 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 811 destrictive = false; 812 } else if (link_dp_get_encoding_format(&max_link_cap) == 813 DP_8b_10b_ENCODING) { 814 if (link->dpcd_caps.is_mst_capable || 815 is_link_enc_unavailable) { 816 destrictive = false; 817 } 818 } 819 } 820 821 return destrictive; 822 } 823 824 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, 825 enum dc_detect_reason reason) 826 { 827 if (should_verify_link_capability_destructively(link, reason)) 828 verify_link_capability_destructive(link, sink, reason); 829 else 830 verify_link_capability_non_destructive(link); 831 } 832 833 /** 834 * detect_link_and_local_sink() - Detect if a sink is attached to a given link 835 * 836 * link->local_sink is created or destroyed as needed. 837 * 838 * This does not create remote sinks. 839 */ 840 static bool detect_link_and_local_sink(struct dc_link *link, 841 enum dc_detect_reason reason) 842 { 843 struct dc_sink_init_data sink_init_data = { 0 }; 844 struct display_sink_capability sink_caps = { 0 }; 845 uint32_t i; 846 bool converter_disable_audio = false; 847 struct audio_support *aud_support = &link->dc->res_pool->audio_support; 848 bool same_edid = false; 849 enum dc_edid_status edid_status; 850 struct dc_context *dc_ctx = link->ctx; 851 struct dc *dc = dc_ctx->dc; 852 struct dc_sink *sink = NULL; 853 struct dc_sink *prev_sink = NULL; 854 struct dpcd_caps prev_dpcd_caps; 855 enum dc_connection_type new_connection_type = dc_connection_none; 856 enum dc_connection_type pre_connection_type = link->type; 857 const uint32_t post_oui_delay = 30; // 30ms 858 859 DC_LOGGER_INIT(link->ctx->logger); 860 861 if (dc_is_virtual_signal(link->connector_signal)) 862 return false; 863 864 if (((link->connector_signal == SIGNAL_TYPE_LVDS || 865 link->connector_signal == SIGNAL_TYPE_EDP) && 866 (!link->dc->config.allow_edp_hotplug_detection)) && 867 link->local_sink) { 868 // need to re-write OUI and brightness in resume case 869 if (link->connector_signal == SIGNAL_TYPE_EDP && 870 (link->dpcd_sink_ext_caps.bits.oled == 1)) { 871 dpcd_set_source_specific_data(link); 872 msleep(post_oui_delay); 873 set_default_brightness_aux(link); 874 //TODO: use cached 875 } 876 877 return true; 878 } 879 880 if (!link_detect_connection_type(link, &new_connection_type)) { 881 BREAK_TO_DEBUGGER(); 882 return false; 883 } 884 885 prev_sink = link->local_sink; 886 if (prev_sink) { 887 dc_sink_retain(prev_sink); 888 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps)); 889 } 890 891 link_disconnect_sink(link); 892 if (new_connection_type != dc_connection_none) { 893 link->type = new_connection_type; 894 link->link_state_valid = false; 895 896 /* From Disconnected-to-Connected. */ 897 switch (link->connector_signal) { 898 case SIGNAL_TYPE_HDMI_TYPE_A: { 899 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 900 if (aud_support->hdmi_audio_native) 901 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 902 else 903 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 904 break; 905 } 906 907 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 908 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 909 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 910 break; 911 } 912 913 case SIGNAL_TYPE_DVI_DUAL_LINK: { 914 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 915 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 916 break; 917 } 918 919 case SIGNAL_TYPE_LVDS: { 920 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 921 sink_caps.signal = SIGNAL_TYPE_LVDS; 922 break; 923 } 924 925 case SIGNAL_TYPE_EDP: { 926 detect_edp_sink_caps(link); 927 read_current_link_settings_on_detect(link); 928 929 /* Disable power sequence on MIPI panel + converter 930 */ 931 if (dc->config.enable_mipi_converter_optimization && 932 dc_ctx->dce_version == DCN_VERSION_3_01 && 933 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 && 934 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580, 935 sizeof(link->dpcd_caps.branch_dev_name)) == 0) { 936 dc->config.edp_no_power_sequencing = true; 937 938 if (!link->dpcd_caps.set_power_state_capable_edp) 939 link->wa_flags.dp_keep_receiver_powered = true; 940 } 941 942 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 943 sink_caps.signal = SIGNAL_TYPE_EDP; 944 break; 945 } 946 947 case SIGNAL_TYPE_DISPLAY_PORT: { 948 949 /* wa HPD high coming too early*/ 950 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 951 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { 952 953 /* if alt mode times out, return false */ 954 if (!wait_for_entering_dp_alt_mode(link)) 955 return false; 956 } 957 958 if (!detect_dp(link, &sink_caps, reason)) { 959 link->type = pre_connection_type; 960 961 if (prev_sink) 962 dc_sink_release(prev_sink); 963 return false; 964 } 965 966 /* Active SST downstream branch device unplug*/ 967 if (link->type == dc_connection_sst_branch && 968 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) { 969 if (prev_sink) 970 /* Downstream unplug */ 971 dc_sink_release(prev_sink); 972 return true; 973 } 974 975 /* disable audio for non DP to HDMI active sst converter */ 976 if (link->type == dc_connection_sst_branch && 977 is_dp_active_dongle(link) && 978 (link->dpcd_caps.dongle_type != 979 DISPLAY_DONGLE_DP_HDMI_CONVERTER)) 980 converter_disable_audio = true; 981 break; 982 } 983 984 default: 985 DC_ERROR("Invalid connector type! signal:%d\n", 986 link->connector_signal); 987 if (prev_sink) 988 dc_sink_release(prev_sink); 989 return false; 990 } /* switch() */ 991 992 if (link->dpcd_caps.sink_count.bits.SINK_COUNT) 993 link->dpcd_sink_count = 994 link->dpcd_caps.sink_count.bits.SINK_COUNT; 995 else 996 link->dpcd_sink_count = 1; 997 998 set_ddc_transaction_type(link->ddc, 999 sink_caps.transaction_type); 1000 1001 link->aux_mode = 1002 link_is_in_aux_transaction_mode(link->ddc); 1003 1004 sink_init_data.link = link; 1005 sink_init_data.sink_signal = sink_caps.signal; 1006 1007 sink = dc_sink_create(&sink_init_data); 1008 if (!sink) { 1009 DC_ERROR("Failed to create sink!\n"); 1010 if (prev_sink) 1011 dc_sink_release(prev_sink); 1012 return false; 1013 } 1014 1015 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; 1016 sink->converter_disable_audio = converter_disable_audio; 1017 1018 /* dc_sink_create returns a new reference */ 1019 link->local_sink = sink; 1020 1021 edid_status = dm_helpers_read_local_edid(link->ctx, 1022 link, sink); 1023 1024 switch (edid_status) { 1025 case EDID_BAD_CHECKSUM: 1026 DC_LOG_ERROR("EDID checksum invalid.\n"); 1027 break; 1028 case EDID_PARTIAL_VALID: 1029 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n"); 1030 break; 1031 case EDID_NO_RESPONSE: 1032 DC_LOG_ERROR("No EDID read.\n"); 1033 /* 1034 * Abort detection for non-DP connectors if we have 1035 * no EDID 1036 * 1037 * DP needs to report as connected if HDP is high 1038 * even if we have no EDID in order to go to 1039 * fail-safe mode 1040 */ 1041 if (dc_is_hdmi_signal(link->connector_signal) || 1042 dc_is_dvi_signal(link->connector_signal)) { 1043 if (prev_sink) 1044 dc_sink_release(prev_sink); 1045 1046 return false; 1047 } 1048 1049 if (link->type == dc_connection_sst_branch && 1050 link->dpcd_caps.dongle_type == 1051 DISPLAY_DONGLE_DP_VGA_CONVERTER && 1052 reason == DETECT_REASON_HPDRX) { 1053 /* Abort detection for DP-VGA adapters when EDID 1054 * can't be read and detection reason is VGA-side 1055 * hotplug 1056 */ 1057 if (prev_sink) 1058 dc_sink_release(prev_sink); 1059 link_disconnect_sink(link); 1060 1061 return true; 1062 } 1063 1064 break; 1065 default: 1066 break; 1067 } 1068 1069 // Check if edid is the same 1070 if ((prev_sink) && 1071 (edid_status == EDID_THE_SAME || edid_status == EDID_OK)) 1072 same_edid = is_same_edid(&prev_sink->dc_edid, 1073 &sink->dc_edid); 1074 1075 if (sink->edid_caps.panel_patch.skip_scdc_overwrite) 1076 link->ctx->dc->debug.hdmi20_disable = true; 1077 1078 if (dc_is_hdmi_signal(link->connector_signal)) 1079 read_scdc_caps(link->ddc, link->local_sink); 1080 1081 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 1082 sink_caps.transaction_type == 1083 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 1084 /* 1085 * TODO debug why certain monitors don't like 1086 * two link trainings 1087 */ 1088 query_hdcp_capability(sink->sink_signal, link); 1089 } else { 1090 // If edid is the same, then discard new sink and revert back to original sink 1091 if (same_edid) { 1092 link_disconnect_remap(prev_sink, link); 1093 sink = prev_sink; 1094 prev_sink = NULL; 1095 } 1096 query_hdcp_capability(sink->sink_signal, link); 1097 } 1098 1099 /* HDMI-DVI Dongle */ 1100 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && 1101 !sink->edid_caps.edid_hdmi) 1102 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1103 1104 if (link->local_sink && dc_is_dp_signal(sink_caps.signal)) 1105 dp_trace_init(link); 1106 1107 /* Connectivity log: detection */ 1108 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) { 1109 CONN_DATA_DETECT(link, 1110 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE], 1111 DC_EDID_BLOCK_SIZE, 1112 "%s: [Block %d] ", sink->edid_caps.display_name, i); 1113 } 1114 1115 DC_LOG_DETECTION_EDID_PARSER("%s: " 1116 "manufacturer_id = %X, " 1117 "product_id = %X, " 1118 "serial_number = %X, " 1119 "manufacture_week = %d, " 1120 "manufacture_year = %d, " 1121 "display_name = %s, " 1122 "speaker_flag = %d, " 1123 "audio_mode_count = %d\n", 1124 __func__, 1125 sink->edid_caps.manufacturer_id, 1126 sink->edid_caps.product_id, 1127 sink->edid_caps.serial_number, 1128 sink->edid_caps.manufacture_week, 1129 sink->edid_caps.manufacture_year, 1130 sink->edid_caps.display_name, 1131 sink->edid_caps.speaker_flags, 1132 sink->edid_caps.audio_mode_count); 1133 1134 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) { 1135 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, " 1136 "format_code = %d, " 1137 "channel_count = %d, " 1138 "sample_rate = %d, " 1139 "sample_size = %d\n", 1140 __func__, 1141 i, 1142 sink->edid_caps.audio_modes[i].format_code, 1143 sink->edid_caps.audio_modes[i].channel_count, 1144 sink->edid_caps.audio_modes[i].sample_rate, 1145 sink->edid_caps.audio_modes[i].sample_size); 1146 } 1147 1148 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1149 // Init dc_panel_config by HW config 1150 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) 1151 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); 1152 // Pickup base DM settings 1153 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink); 1154 // Override dc_panel_config if system has specific settings 1155 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config); 1156 } 1157 1158 } else { 1159 /* From Connected-to-Disconnected. */ 1160 link->type = dc_connection_none; 1161 sink_caps.signal = SIGNAL_TYPE_NONE; 1162 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps)); 1163 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk 1164 * is not cleared. If we emulate a DP signal on this connection, it thinks 1165 * the dongle is still there and limits the number of modes we can emulate. 1166 * Clear dongle_max_pix_clk on disconnect to fix this 1167 */ 1168 link->dongle_max_pix_clk = 0; 1169 1170 dc_link_clear_dprx_states(link); 1171 dp_trace_reset(link); 1172 } 1173 1174 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n", 1175 link->link_index, sink, 1176 (sink_caps.signal == 1177 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"), 1178 prev_sink, same_edid); 1179 1180 if (prev_sink) 1181 dc_sink_release(prev_sink); 1182 1183 return true; 1184 } 1185 1186 /** 1187 * link_detect_connection_type() - Determine if there is a sink connected 1188 * 1189 * @type: Returned connection type 1190 * Does not detect downstream devices, such as MST sinks 1191 * or display connected through active dongles 1192 */ 1193 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type) 1194 { 1195 uint32_t is_hpd_high = 0; 1196 1197 if (link->connector_signal == SIGNAL_TYPE_LVDS) { 1198 *type = dc_connection_single; 1199 return true; 1200 } 1201 1202 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1203 /*in case it is not on*/ 1204 if (!link->dc->config.edp_no_power_sequencing) 1205 link->dc->hwss.edp_power_control(link, true); 1206 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 1207 } 1208 1209 /* Link may not have physical HPD pin. */ 1210 if (link->ep_type != DISPLAY_ENDPOINT_PHY) { 1211 if (link->is_hpd_pending || !dpia_query_hpd_status(link)) 1212 *type = dc_connection_none; 1213 else 1214 *type = dc_connection_single; 1215 1216 return true; 1217 } 1218 1219 1220 if (!query_hpd_status(link, &is_hpd_high)) 1221 goto hpd_gpio_failure; 1222 1223 if (is_hpd_high) { 1224 *type = dc_connection_single; 1225 /* TODO: need to do the actual detection */ 1226 } else { 1227 *type = dc_connection_none; 1228 } 1229 1230 return true; 1231 1232 hpd_gpio_failure: 1233 return false; 1234 } 1235 1236 bool link_detect(struct dc_link *link, enum dc_detect_reason reason) 1237 { 1238 bool is_local_sink_detect_success; 1239 bool is_delegated_to_mst_top_mgr = false; 1240 enum dc_connection_type pre_link_type = link->type; 1241 1242 DC_LOGGER_INIT(link->ctx->logger); 1243 1244 is_local_sink_detect_success = detect_link_and_local_sink(link, reason); 1245 1246 if (is_local_sink_detect_success && link->local_sink) 1247 verify_link_capability(link, link->local_sink, reason); 1248 1249 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__, 1250 link->link_index, is_local_sink_detect_success, pre_link_type, link->type); 1251 1252 if (is_local_sink_detect_success && link->local_sink && 1253 dc_is_dp_signal(link->local_sink->sink_signal) && 1254 link->dpcd_caps.is_mst_capable) 1255 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason); 1256 1257 if (is_local_sink_detect_success && 1258 pre_link_type == dc_connection_mst_branch && 1259 link->type != dc_connection_mst_branch) 1260 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link); 1261 1262 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr; 1263 } 1264 1265 void link_clear_dprx_states(struct dc_link *link) 1266 { 1267 memset(&link->dprx_states, 0, sizeof(link->dprx_states)); 1268 } 1269 1270 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal) 1271 { 1272 bool ret = false; 1273 1274 switch (signal) { 1275 case SIGNAL_TYPE_DISPLAY_PORT: 1276 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1277 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE; 1278 break; 1279 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1280 case SIGNAL_TYPE_DVI_DUAL_LINK: 1281 case SIGNAL_TYPE_HDMI_TYPE_A: 1282 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable, 1283 * we can poll for bksv but some displays have an issue with this. Since its so rare 1284 * for a display to not be 1.4 capable, this assumtion is ok 1285 */ 1286 ret = true; 1287 break; 1288 default: 1289 break; 1290 } 1291 return ret; 1292 } 1293 1294 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal) 1295 { 1296 bool ret = false; 1297 1298 switch (signal) { 1299 case SIGNAL_TYPE_DISPLAY_PORT: 1300 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1301 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE && 1302 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable && 1303 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0; 1304 break; 1305 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1306 case SIGNAL_TYPE_DVI_DUAL_LINK: 1307 case SIGNAL_TYPE_HDMI_TYPE_A: 1308 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0; 1309 break; 1310 default: 1311 break; 1312 } 1313 1314 return ret; 1315 } 1316 1317 const struct dc_link_status *link_get_status(const struct dc_link *link) 1318 { 1319 return &link->link_status; 1320 } 1321 1322 1323 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) 1324 { 1325 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { 1326 BREAK_TO_DEBUGGER(); 1327 return false; 1328 } 1329 1330 dc_sink_retain(sink); 1331 1332 dc_link->remote_sinks[dc_link->sink_count] = sink; 1333 dc_link->sink_count++; 1334 1335 return true; 1336 } 1337 1338 struct dc_sink *link_add_remote_sink( 1339 struct dc_link *link, 1340 const uint8_t *edid, 1341 int len, 1342 struct dc_sink_init_data *init_data) 1343 { 1344 struct dc_sink *dc_sink; 1345 enum dc_edid_status edid_status; 1346 1347 if (len > DC_MAX_EDID_BUFFER_SIZE) { 1348 dm_error("Max EDID buffer size breached!\n"); 1349 return NULL; 1350 } 1351 1352 if (!init_data) { 1353 BREAK_TO_DEBUGGER(); 1354 return NULL; 1355 } 1356 1357 if (!init_data->link) { 1358 BREAK_TO_DEBUGGER(); 1359 return NULL; 1360 } 1361 1362 dc_sink = dc_sink_create(init_data); 1363 1364 if (!dc_sink) 1365 return NULL; 1366 1367 memmove(dc_sink->dc_edid.raw_edid, edid, len); 1368 dc_sink->dc_edid.length = len; 1369 1370 if (!link_add_remote_sink_helper( 1371 link, 1372 dc_sink)) 1373 goto fail_add_sink; 1374 1375 edid_status = dm_helpers_parse_edid_caps( 1376 link, 1377 &dc_sink->dc_edid, 1378 &dc_sink->edid_caps); 1379 1380 /* 1381 * Treat device as no EDID device if EDID 1382 * parsing fails 1383 */ 1384 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) { 1385 dc_sink->dc_edid.length = 0; 1386 dm_error("Bad EDID, status%d!\n", edid_status); 1387 } 1388 1389 return dc_sink; 1390 1391 fail_add_sink: 1392 dc_sink_release(dc_sink); 1393 return NULL; 1394 } 1395 1396 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) 1397 { 1398 int i; 1399 1400 if (!link->sink_count) { 1401 BREAK_TO_DEBUGGER(); 1402 return; 1403 } 1404 1405 for (i = 0; i < link->sink_count; i++) { 1406 if (link->remote_sinks[i] == sink) { 1407 dc_sink_release(sink); 1408 link->remote_sinks[i] = NULL; 1409 1410 /* shrink array to remove empty place */ 1411 while (i < link->sink_count - 1) { 1412 link->remote_sinks[i] = link->remote_sinks[i+1]; 1413 i++; 1414 } 1415 link->remote_sinks[i] = NULL; 1416 link->sink_count--; 1417 return; 1418 } 1419 } 1420 } 1421