1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file manages link detection states and receiver states by using various 28 * link protocols. It also provides helper functions to interpret certain 29 * capabilities or status based on the states it manages or retrieve them 30 * directly from connected receivers. 31 */ 32 33 #include "link_dpms.h" 34 #include "link_detection.h" 35 #include "link_hwss.h" 36 #include "protocols/link_edp_panel_control.h" 37 #include "protocols/link_ddc.h" 38 #include "protocols/link_hpd.h" 39 #include "protocols/link_dpcd.h" 40 #include "protocols/link_dp_capability.h" 41 #include "protocols/link_dp_dpia.h" 42 #include "protocols/link_dp_phy.h" 43 #include "protocols/link_dp_training.h" 44 #include "protocols/link_dp_dpia_bw.h" 45 #include "accessories/link_dp_trace.h" 46 47 #include "link_enc_cfg.h" 48 #include "dm_helpers.h" 49 #include "clk_mgr.h" 50 51 // Offset DPCD 050Eh == 0x5A 52 #define MST_HUB_ID_0x5A 0x5A 53 54 #define DC_LOGGER \ 55 link->ctx->logger 56 #define DC_LOGGER_INIT(logger) 57 58 #define LINK_INFO(...) \ 59 DC_LOG_HW_HOTPLUG( \ 60 __VA_ARGS__) 61 /* 62 * Some receivers fail to train on first try and are good 63 * on subsequent tries. 2 retries should be plenty. If we 64 * don't have a successful training then we don't expect to 65 * ever get one. 66 */ 67 #define LINK_TRAINING_MAX_VERIFY_RETRY 2 68 69 static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u"; 70 71 static const u8 dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR"; 72 73 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal) 74 { 75 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE; 76 77 switch (sink_signal) { 78 case SIGNAL_TYPE_DVI_SINGLE_LINK: 79 case SIGNAL_TYPE_DVI_DUAL_LINK: 80 case SIGNAL_TYPE_HDMI_TYPE_A: 81 case SIGNAL_TYPE_LVDS: 82 case SIGNAL_TYPE_RGB: 83 transaction_type = DDC_TRANSACTION_TYPE_I2C; 84 break; 85 86 case SIGNAL_TYPE_DISPLAY_PORT: 87 case SIGNAL_TYPE_EDP: 88 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 89 break; 90 91 case SIGNAL_TYPE_DISPLAY_PORT_MST: 92 /* MST does not use I2COverAux, but there is the 93 * SPECIAL use case for "immediate dwnstrm device 94 * access" (EPR#370830). 95 */ 96 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 97 break; 98 99 default: 100 break; 101 } 102 103 return transaction_type; 104 } 105 106 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder, 107 struct graphics_object_id downstream) 108 { 109 if (downstream.type == OBJECT_TYPE_CONNECTOR) { 110 switch (downstream.id) { 111 case CONNECTOR_ID_SINGLE_LINK_DVII: 112 switch (encoder.id) { 113 case ENCODER_ID_INTERNAL_DAC1: 114 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 115 case ENCODER_ID_INTERNAL_DAC2: 116 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 117 return SIGNAL_TYPE_RGB; 118 default: 119 return SIGNAL_TYPE_DVI_SINGLE_LINK; 120 } 121 break; 122 case CONNECTOR_ID_DUAL_LINK_DVII: 123 { 124 switch (encoder.id) { 125 case ENCODER_ID_INTERNAL_DAC1: 126 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 127 case ENCODER_ID_INTERNAL_DAC2: 128 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 129 return SIGNAL_TYPE_RGB; 130 default: 131 return SIGNAL_TYPE_DVI_DUAL_LINK; 132 } 133 } 134 break; 135 case CONNECTOR_ID_SINGLE_LINK_DVID: 136 return SIGNAL_TYPE_DVI_SINGLE_LINK; 137 case CONNECTOR_ID_DUAL_LINK_DVID: 138 return SIGNAL_TYPE_DVI_DUAL_LINK; 139 case CONNECTOR_ID_VGA: 140 return SIGNAL_TYPE_RGB; 141 case CONNECTOR_ID_HDMI_TYPE_A: 142 return SIGNAL_TYPE_HDMI_TYPE_A; 143 case CONNECTOR_ID_LVDS: 144 return SIGNAL_TYPE_LVDS; 145 case CONNECTOR_ID_DISPLAY_PORT: 146 case CONNECTOR_ID_USBC: 147 return SIGNAL_TYPE_DISPLAY_PORT; 148 case CONNECTOR_ID_EDP: 149 return SIGNAL_TYPE_EDP; 150 default: 151 return SIGNAL_TYPE_NONE; 152 } 153 } else if (downstream.type == OBJECT_TYPE_ENCODER) { 154 switch (downstream.id) { 155 case ENCODER_ID_EXTERNAL_NUTMEG: 156 case ENCODER_ID_EXTERNAL_TRAVIS: 157 return SIGNAL_TYPE_DISPLAY_PORT; 158 default: 159 return SIGNAL_TYPE_NONE; 160 } 161 } 162 163 return SIGNAL_TYPE_NONE; 164 } 165 166 /* 167 * @brief 168 * Detect output sink type 169 */ 170 static enum signal_type link_detect_sink_signal_type(struct dc_link *link, 171 enum dc_detect_reason reason) 172 { 173 enum signal_type result; 174 struct graphics_object_id enc_id; 175 176 if (link->is_dig_mapping_flexible) 177 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN}; 178 else 179 enc_id = link->link_enc->id; 180 result = get_basic_signal_type(enc_id, link->link_id); 181 182 /* Use basic signal type for link without physical connector. */ 183 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 184 return result; 185 186 /* Internal digital encoder will detect only dongles 187 * that require digital signal 188 */ 189 190 /* Detection mechanism is different 191 * for different native connectors. 192 * LVDS connector supports only LVDS signal; 193 * PCIE is a bus slot, the actual connector needs to be detected first; 194 * eDP connector supports only eDP signal; 195 * HDMI should check straps for audio 196 */ 197 198 /* PCIE detects the actual connector on add-on board */ 199 if (link->link_id.id == CONNECTOR_ID_PCIE) { 200 /* ZAZTODO implement PCIE add-on card detection */ 201 } 202 203 switch (link->link_id.id) { 204 case CONNECTOR_ID_HDMI_TYPE_A: { 205 /* check audio support: 206 * if native HDMI is not supported, switch to DVI 207 */ 208 struct audio_support *aud_support = 209 &link->dc->res_pool->audio_support; 210 211 if (!aud_support->hdmi_audio_native) 212 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A) 213 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 214 } 215 break; 216 case CONNECTOR_ID_DISPLAY_PORT: 217 case CONNECTOR_ID_USBC: { 218 /* DP HPD short pulse. Passive DP dongle will not 219 * have short pulse 220 */ 221 if (reason != DETECT_REASON_HPDRX) { 222 /* Check whether DP signal detected: if not - 223 * we assume signal is DVI; it could be corrected 224 * to HDMI after dongle detection 225 */ 226 if (!dm_helpers_is_dp_sink_present(link)) 227 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 228 } 229 } 230 break; 231 default: 232 break; 233 } 234 235 return result; 236 } 237 238 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type, 239 struct audio_support *audio_support) 240 { 241 enum signal_type signal = SIGNAL_TYPE_NONE; 242 243 switch (dongle_type) { 244 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 245 if (audio_support->hdmi_audio_on_dongle) 246 signal = SIGNAL_TYPE_HDMI_TYPE_A; 247 else 248 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 249 break; 250 case DISPLAY_DONGLE_DP_DVI_DONGLE: 251 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 252 break; 253 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 254 if (audio_support->hdmi_audio_native) 255 signal = SIGNAL_TYPE_HDMI_TYPE_A; 256 else 257 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 258 break; 259 default: 260 signal = SIGNAL_TYPE_NONE; 261 break; 262 } 263 264 return signal; 265 } 266 267 static void read_scdc_caps(struct ddc_service *ddc_service, 268 struct dc_sink *sink) 269 { 270 uint8_t slave_address = HDMI_SCDC_ADDRESS; 271 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI; 272 273 link_query_ddc_data(ddc_service, slave_address, &offset, 274 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte, 275 sizeof(sink->scdc_caps.manufacturer_OUI.byte)); 276 277 offset = HDMI_SCDC_DEVICE_ID; 278 279 link_query_ddc_data(ddc_service, slave_address, &offset, 280 sizeof(offset), &(sink->scdc_caps.device_id.byte), 281 sizeof(sink->scdc_caps.device_id.byte)); 282 } 283 284 static bool i2c_read( 285 struct ddc_service *ddc, 286 uint32_t address, 287 uint8_t *buffer, 288 uint32_t len) 289 { 290 uint8_t offs_data = 0; 291 struct i2c_payload payloads[2] = { 292 { 293 .write = true, 294 .address = address, 295 .length = 1, 296 .data = &offs_data }, 297 { 298 .write = false, 299 .address = address, 300 .length = len, 301 .data = buffer } }; 302 303 struct i2c_command command = { 304 .payloads = payloads, 305 .number_of_payloads = 2, 306 .engine = DDC_I2C_COMMAND_ENGINE, 307 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz }; 308 309 return dm_helpers_submit_i2c( 310 ddc->ctx, 311 ddc->link, 312 &command); 313 } 314 315 enum { 316 DP_SINK_CAP_SIZE = 317 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1 318 }; 319 320 static void query_dp_dual_mode_adaptor( 321 struct ddc_service *ddc, 322 struct display_sink_capability *sink_cap) 323 { 324 uint8_t i; 325 bool is_valid_hdmi_signature; 326 enum display_dongle_type *dongle = &sink_cap->dongle_type; 327 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE]; 328 bool is_type2_dongle = false; 329 int retry_count = 2; 330 struct dp_hdmi_dongle_signature_data *dongle_signature; 331 struct dc_link *link = ddc->link; 332 333 /* Assume we have no valid DP passive dongle connected */ 334 *dongle = DISPLAY_DONGLE_NONE; 335 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK; 336 337 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/ 338 if (!i2c_read( 339 ddc, 340 DP_HDMI_DONGLE_ADDRESS, 341 type2_dongle_buf, 342 sizeof(type2_dongle_buf))) { 343 /* Passive HDMI dongles can sometimes fail here without retrying*/ 344 while (retry_count > 0) { 345 if (i2c_read(ddc, 346 DP_HDMI_DONGLE_ADDRESS, 347 type2_dongle_buf, 348 sizeof(type2_dongle_buf))) 349 break; 350 retry_count--; 351 } 352 if (retry_count == 0) { 353 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 354 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; 355 356 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf), 357 "DP-DVI passive dongle %dMhz: ", 358 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 359 return; 360 } 361 } 362 363 /* Check if Type 2 dongle.*/ 364 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID) 365 is_type2_dongle = true; 366 367 dongle_signature = 368 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf; 369 370 is_valid_hdmi_signature = true; 371 372 /* Check EOT */ 373 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) { 374 is_valid_hdmi_signature = false; 375 } 376 377 /* Check signature */ 378 for (i = 0; i < sizeof(dongle_signature->id); ++i) { 379 /* If its not the right signature, 380 * skip mismatch in subversion byte.*/ 381 if (dongle_signature->id[i] != 382 dp_hdmi_dongle_signature_str[i] && i != 3) { 383 384 if (is_type2_dongle) { 385 is_valid_hdmi_signature = false; 386 break; 387 } 388 389 } 390 } 391 392 if (is_type2_dongle) { 393 uint32_t max_tmds_clk = 394 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK]; 395 396 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2; 397 398 if (0 == max_tmds_clk || 399 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK || 400 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) { 401 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 402 403 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 404 sizeof(type2_dongle_buf), 405 "DP-DVI passive dongle %dMhz: ", 406 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 407 } else { 408 if (is_valid_hdmi_signature == true) { 409 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 410 411 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 412 sizeof(type2_dongle_buf), 413 "Type 2 DP-HDMI passive dongle %dMhz: ", 414 max_tmds_clk); 415 } else { 416 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 417 418 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 419 sizeof(type2_dongle_buf), 420 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ", 421 max_tmds_clk); 422 423 } 424 425 /* Multiply by 1000 to convert to kHz. */ 426 sink_cap->max_hdmi_pixel_clock = 427 max_tmds_clk * 1000; 428 } 429 sink_cap->is_dongle_type_one = false; 430 431 } else { 432 if (is_valid_hdmi_signature == true) { 433 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 434 435 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 436 sizeof(type2_dongle_buf), 437 "Type 1 DP-HDMI passive dongle %dMhz: ", 438 sink_cap->max_hdmi_pixel_clock / 1000); 439 } else { 440 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 441 442 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 443 sizeof(type2_dongle_buf), 444 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ", 445 sink_cap->max_hdmi_pixel_clock / 1000); 446 } 447 sink_cap->is_dongle_type_one = true; 448 } 449 450 return; 451 } 452 453 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc, 454 struct display_sink_capability *sink_cap, 455 struct audio_support *audio_support) 456 { 457 query_dp_dual_mode_adaptor(ddc, sink_cap); 458 459 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type, 460 audio_support); 461 } 462 463 static void link_disconnect_sink(struct dc_link *link) 464 { 465 if (link->local_sink) { 466 dc_sink_release(link->local_sink); 467 link->local_sink = NULL; 468 } 469 470 link->dpcd_sink_count = 0; 471 //link->dpcd_caps.dpcd_rev.raw = 0; 472 } 473 474 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link) 475 { 476 dc_sink_release(link->local_sink); 477 link->local_sink = prev_sink; 478 } 479 480 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link) 481 { 482 struct hdcp_protection_message msg22; 483 struct hdcp_protection_message msg14; 484 485 memset(&msg22, 0, sizeof(struct hdcp_protection_message)); 486 memset(&msg14, 0, sizeof(struct hdcp_protection_message)); 487 memset(link->hdcp_caps.rx_caps.raw, 0, 488 sizeof(link->hdcp_caps.rx_caps.raw)); 489 490 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 491 link->ddc->transaction_type == 492 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) || 493 link->connector_signal == SIGNAL_TYPE_EDP) { 494 msg22.data = link->hdcp_caps.rx_caps.raw; 495 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw); 496 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS; 497 } else { 498 msg22.data = &link->hdcp_caps.rx_caps.fields.version; 499 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version); 500 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION; 501 } 502 msg22.version = HDCP_VERSION_22; 503 msg22.link = HDCP_LINK_PRIMARY; 504 msg22.max_retries = 5; 505 dc_process_hdcp_msg(signal, link, &msg22); 506 507 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 508 msg14.data = &link->hdcp_caps.bcaps.raw; 509 msg14.length = sizeof(link->hdcp_caps.bcaps.raw); 510 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS; 511 msg14.version = HDCP_VERSION_14; 512 msg14.link = HDCP_LINK_PRIMARY; 513 msg14.max_retries = 5; 514 515 dc_process_hdcp_msg(signal, link, &msg14); 516 } 517 518 } 519 static void read_current_link_settings_on_detect(struct dc_link *link) 520 { 521 union lane_count_set lane_count_set = {0}; 522 uint8_t link_bw_set = 0; 523 uint8_t link_rate_set = 0; 524 uint32_t read_dpcd_retry_cnt = 10; 525 enum dc_status status = DC_ERROR_UNEXPECTED; 526 int i; 527 union max_down_spread max_down_spread = {0}; 528 529 // Read DPCD 00101h to find out the number of lanes currently set 530 for (i = 0; i < read_dpcd_retry_cnt; i++) { 531 status = core_link_read_dpcd(link, 532 DP_LANE_COUNT_SET, 533 &lane_count_set.raw, 534 sizeof(lane_count_set)); 535 /* First DPCD read after VDD ON can fail if the particular board 536 * does not have HPD pin wired correctly. So if DPCD read fails, 537 * which it should never happen, retry a few times. Target worst 538 * case scenario of 80 ms. 539 */ 540 if (status == DC_OK) { 541 link->cur_link_settings.lane_count = 542 lane_count_set.bits.LANE_COUNT_SET; 543 break; 544 } 545 546 msleep(8); 547 } 548 549 // Read DPCD 00100h to find if standard link rates are set 550 core_link_read_dpcd(link, DP_LINK_BW_SET, 551 &link_bw_set, sizeof(link_bw_set)); 552 553 if (link_bw_set == 0) { 554 if (link->connector_signal == SIGNAL_TYPE_EDP) { 555 /* If standard link rates are not being used, 556 * Read DPCD 00115h to find the edp link rate set used 557 */ 558 core_link_read_dpcd(link, DP_LINK_RATE_SET, 559 &link_rate_set, sizeof(link_rate_set)); 560 561 // edp_supported_link_rates_count = 0 for DP 562 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 563 link->cur_link_settings.link_rate = 564 link->dpcd_caps.edp_supported_link_rates[link_rate_set]; 565 link->cur_link_settings.link_rate_set = link_rate_set; 566 link->cur_link_settings.use_link_rate_set = true; 567 } 568 } else { 569 // Link Rate not found. Seamless boot may not work. 570 ASSERT(false); 571 } 572 } else { 573 link->cur_link_settings.link_rate = link_bw_set; 574 link->cur_link_settings.use_link_rate_set = false; 575 } 576 // Read DPCD 00003h to find the max down spread. 577 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD, 578 &max_down_spread.raw, sizeof(max_down_spread)); 579 link->cur_link_settings.link_spread = 580 max_down_spread.bits.MAX_DOWN_SPREAD ? 581 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 582 } 583 584 static bool detect_dp(struct dc_link *link, 585 struct display_sink_capability *sink_caps, 586 enum dc_detect_reason reason) 587 { 588 struct audio_support *audio_support = &link->dc->res_pool->audio_support; 589 590 sink_caps->signal = link_detect_sink_signal_type(link, reason); 591 sink_caps->transaction_type = 592 get_ddc_transaction_type(sink_caps->signal); 593 594 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 595 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; 596 if (!detect_dp_sink_caps(link)) { 597 return false; 598 } 599 600 if (is_dp_branch_device(link)) 601 /* DP SST branch */ 602 link->type = dc_connection_sst_branch; 603 } else { 604 if (link->dc->debug.disable_dp_plus_plus_wa && 605 link->link_enc->features.flags.bits.IS_UHBR20_CAPABLE) 606 return false; 607 608 /* DP passive dongles */ 609 sink_caps->signal = dp_passive_dongle_detection(link->ddc, 610 sink_caps, 611 audio_support); 612 link->dpcd_caps.dongle_type = sink_caps->dongle_type; 613 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one; 614 link->dpcd_caps.dpcd_rev.raw = 0; 615 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0; 616 } 617 618 return true; 619 } 620 621 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid) 622 { 623 if (old_edid->length != new_edid->length) 624 return false; 625 626 if (new_edid->length == 0) 627 return false; 628 629 return (memcmp(old_edid->raw_edid, 630 new_edid->raw_edid, new_edid->length) == 0); 631 } 632 633 static bool wait_for_entering_dp_alt_mode(struct dc_link *link) 634 { 635 636 /** 637 * something is terribly wrong if time out is > 200ms. (5Hz) 638 * 500 microseconds * 400 tries us 200 ms 639 **/ 640 unsigned int sleep_time_in_microseconds = 500; 641 unsigned int tries_allowed = 400; 642 bool is_in_alt_mode; 643 unsigned long long enter_timestamp; 644 unsigned long long finish_timestamp; 645 unsigned long long time_taken_in_ns; 646 int tries_taken; 647 648 DC_LOGGER_INIT(link->ctx->logger); 649 650 /** 651 * this function will only exist if we are on dcn21 (is_in_alt_mode is a 652 * function pointer, so checking to see if it is equal to 0 is the same 653 * as checking to see if it is null 654 **/ 655 if (!link->link_enc->funcs->is_in_alt_mode) 656 return true; 657 658 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc); 659 DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode); 660 661 if (is_in_alt_mode) 662 return true; 663 664 enter_timestamp = dm_get_timestamp(link->ctx); 665 666 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) { 667 udelay(sleep_time_in_microseconds); 668 /* ask the link if alt mode is enabled, if so return ok */ 669 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) { 670 finish_timestamp = dm_get_timestamp(link->ctx); 671 time_taken_in_ns = 672 dm_get_elapse_time_in_ns(link->ctx, 673 finish_timestamp, 674 enter_timestamp); 675 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n", 676 div_u64(time_taken_in_ns, 1000000)); 677 return true; 678 } 679 } 680 finish_timestamp = dm_get_timestamp(link->ctx); 681 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, 682 enter_timestamp); 683 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n", 684 div_u64(time_taken_in_ns, 1000000)); 685 return false; 686 } 687 688 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link) 689 { 690 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock 691 * reports DSC support. 692 */ 693 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 694 link->type == dc_connection_mst_branch && 695 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 696 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 && 697 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 698 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) 699 link->wa_flags.dpia_mst_dsc_always_on = true; 700 701 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 702 link->type == dc_connection_mst_branch && 703 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 704 link->dpcd_caps.branch_vendor_specific_data[2] == MST_HUB_ID_0x5A && 705 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 706 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) { 707 link->wa_flags.dpia_mst_dsc_always_on = true; 708 } 709 } 710 711 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link) 712 { 713 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */ 714 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 715 link->wa_flags.dpia_mst_dsc_always_on = false; 716 } 717 718 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason) 719 { 720 DC_LOGGER_INIT(link->ctx->logger); 721 722 LINK_INFO("link=%d, mst branch is now Connected\n", 723 link->link_index); 724 725 link->type = dc_connection_mst_branch; 726 apply_dpia_mst_dsc_always_on_wa(link); 727 728 dm_helpers_dp_update_branch_info(link->ctx, link); 729 if (dm_helpers_dp_mst_start_top_mgr(link->ctx, 730 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) { 731 link_disconnect_sink(link); 732 } else { 733 link->type = dc_connection_sst_branch; 734 } 735 736 return link->type == dc_connection_mst_branch; 737 } 738 739 bool link_reset_cur_dp_mst_topology(struct dc_link *link) 740 { 741 DC_LOGGER_INIT(link->ctx->logger); 742 743 LINK_INFO("link=%d, mst branch is now Disconnected\n", 744 link->link_index); 745 746 revert_dpia_mst_dsc_always_on_wa(link); 747 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); 748 } 749 750 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc, 751 enum dc_detect_reason reason) 752 { 753 int i; 754 bool can_apply_seamless_boot = false; 755 756 for (i = 0; i < dc->current_state->stream_count; i++) { 757 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) { 758 can_apply_seamless_boot = true; 759 break; 760 } 761 } 762 763 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT; 764 } 765 766 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc) 767 { 768 dc_z10_restore(dc); 769 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 770 } 771 772 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc) 773 { 774 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 775 } 776 777 static void verify_link_capability_destructive(struct dc_link *link, 778 struct dc_sink *sink, 779 enum dc_detect_reason reason) 780 { 781 bool should_prepare_phy_clocks = 782 should_prepare_phy_clocks_for_link_verification(link->dc, reason); 783 784 if (should_prepare_phy_clocks) 785 prepare_phy_clocks_for_destructive_link_verification(link->dc); 786 787 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 788 struct dc_link_settings known_limit_link_setting = 789 dp_get_max_link_cap(link); 790 link_set_all_streams_dpms_off_for_link(link); 791 dp_verify_link_cap_with_retries( 792 link, &known_limit_link_setting, 793 LINK_TRAINING_MAX_VERIFY_RETRY); 794 } else { 795 ASSERT(0); 796 } 797 798 if (should_prepare_phy_clocks) 799 restore_phy_clocks_for_destructive_link_verification(link->dc); 800 } 801 802 static void verify_link_capability_non_destructive(struct dc_link *link) 803 { 804 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 805 if (dc_is_embedded_signal(link->local_sink->sink_signal) || 806 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 807 /* TODO - should we check link encoder's max link caps here? 808 * How do we know which link encoder to check from? 809 */ 810 link->verified_link_cap = link->reported_link_cap; 811 else 812 link->verified_link_cap = dp_get_max_link_cap(link); 813 } 814 } 815 816 static bool should_verify_link_capability_destructively(struct dc_link *link, 817 enum dc_detect_reason reason) 818 { 819 bool destrictive = false; 820 struct dc_link_settings max_link_cap; 821 bool is_link_enc_unavailable = false; 822 823 if (!link->dc->config.unify_link_enc_assignment) 824 is_link_enc_unavailable = link->link_enc && 825 link->dc->res_pool->funcs->link_encs_assign && 826 !link_enc_cfg_is_link_enc_avail( 827 link->ctx->dc, 828 link->link_enc->preferred_engine, 829 link); 830 831 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 832 max_link_cap = dp_get_max_link_cap(link); 833 destrictive = true; 834 835 if (link->dc->debug.skip_detection_link_training || 836 dc_is_embedded_signal(link->local_sink->sink_signal) || 837 (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 838 !link->dc->config.enable_dpia_pre_training)) { 839 destrictive = false; 840 } else if (link_dp_get_encoding_format(&max_link_cap) == 841 DP_8b_10b_ENCODING) { 842 if (link->dpcd_caps.is_mst_capable || 843 is_link_enc_unavailable) { 844 destrictive = false; 845 } 846 } 847 } 848 849 return destrictive; 850 } 851 852 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, 853 enum dc_detect_reason reason) 854 { 855 if (should_verify_link_capability_destructively(link, reason)) 856 verify_link_capability_destructive(link, sink, reason); 857 else 858 verify_link_capability_non_destructive(link); 859 } 860 861 /* 862 * detect_link_and_local_sink() - Detect if a sink is attached to a given link 863 * 864 * link->local_sink is created or destroyed as needed. 865 * 866 * This does not create remote sinks. 867 */ 868 static bool detect_link_and_local_sink(struct dc_link *link, 869 enum dc_detect_reason reason) 870 { 871 struct dc_sink_init_data sink_init_data = { 0 }; 872 struct display_sink_capability sink_caps = { 0 }; 873 uint32_t i; 874 bool converter_disable_audio = false; 875 struct audio_support *aud_support = &link->dc->res_pool->audio_support; 876 bool same_edid = false; 877 enum dc_edid_status edid_status; 878 struct dc_context *dc_ctx = link->ctx; 879 struct dc *dc = dc_ctx->dc; 880 struct dc_sink *sink = NULL; 881 struct dc_sink *prev_sink = NULL; 882 struct dpcd_caps prev_dpcd_caps; 883 enum dc_connection_type new_connection_type = dc_connection_none; 884 const uint32_t post_oui_delay = 30; // 30ms 885 886 DC_LOGGER_INIT(link->ctx->logger); 887 888 if (dc_is_virtual_signal(link->connector_signal)) 889 return false; 890 891 if (((link->connector_signal == SIGNAL_TYPE_LVDS || 892 link->connector_signal == SIGNAL_TYPE_EDP) && 893 (!link->dc->config.allow_edp_hotplug_detection)) && 894 link->local_sink) { 895 // need to re-write OUI and brightness in resume case 896 if (link->connector_signal == SIGNAL_TYPE_EDP && 897 (link->dpcd_sink_ext_caps.bits.oled == 1)) { 898 dpcd_set_source_specific_data(link); 899 msleep(post_oui_delay); 900 set_default_brightness_aux(link); 901 } 902 903 return true; 904 } 905 906 if (!link_detect_connection_type(link, &new_connection_type)) { 907 BREAK_TO_DEBUGGER(); 908 return false; 909 } 910 911 prev_sink = link->local_sink; 912 if (prev_sink) { 913 dc_sink_retain(prev_sink); 914 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps)); 915 } 916 917 link_disconnect_sink(link); 918 if (new_connection_type != dc_connection_none) { 919 link->type = new_connection_type; 920 link->link_state_valid = false; 921 922 /* From Disconnected-to-Connected. */ 923 switch (link->connector_signal) { 924 case SIGNAL_TYPE_HDMI_TYPE_A: { 925 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 926 if (aud_support->hdmi_audio_native) 927 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 928 else 929 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 930 break; 931 } 932 933 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 934 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 935 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 936 break; 937 } 938 939 case SIGNAL_TYPE_DVI_DUAL_LINK: { 940 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 941 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 942 break; 943 } 944 945 case SIGNAL_TYPE_LVDS: { 946 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 947 sink_caps.signal = SIGNAL_TYPE_LVDS; 948 break; 949 } 950 951 case SIGNAL_TYPE_EDP: { 952 detect_edp_sink_caps(link); 953 read_current_link_settings_on_detect(link); 954 955 /* Disable power sequence on MIPI panel + converter 956 */ 957 if (dc->config.enable_mipi_converter_optimization && 958 dc_ctx->dce_version == DCN_VERSION_3_01 && 959 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 && 960 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580, 961 sizeof(link->dpcd_caps.branch_dev_name)) == 0) { 962 dc->config.edp_no_power_sequencing = true; 963 964 if (!link->dpcd_caps.set_power_state_capable_edp) 965 link->wa_flags.dp_keep_receiver_powered = true; 966 } 967 968 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 969 sink_caps.signal = SIGNAL_TYPE_EDP; 970 break; 971 } 972 973 case SIGNAL_TYPE_DISPLAY_PORT: { 974 975 /* wa HPD high coming too early*/ 976 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 977 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { 978 979 /* if alt mode times out, return false */ 980 if (!wait_for_entering_dp_alt_mode(link)) 981 return false; 982 } 983 984 if (!detect_dp(link, &sink_caps, reason)) { 985 986 if (prev_sink) 987 dc_sink_release(prev_sink); 988 return false; 989 } 990 991 /* Active SST downstream branch device unplug*/ 992 if (link->type == dc_connection_sst_branch && 993 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) { 994 if (prev_sink) 995 /* Downstream unplug */ 996 dc_sink_release(prev_sink); 997 return true; 998 } 999 1000 /* disable audio for non DP to HDMI active sst converter */ 1001 if (link->type == dc_connection_sst_branch && 1002 is_dp_active_dongle(link) && 1003 (link->dpcd_caps.dongle_type != 1004 DISPLAY_DONGLE_DP_HDMI_CONVERTER)) 1005 converter_disable_audio = true; 1006 1007 /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */ 1008 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 1009 link->reported_link_cap.link_rate > LINK_RATE_HIGH3) 1010 link->reported_link_cap.link_rate = LINK_RATE_HIGH3; 1011 1012 if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling 1013 && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc 1014 && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) { 1015 if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false) 1016 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false; 1017 } 1018 break; 1019 } 1020 1021 default: 1022 DC_ERROR("Invalid connector type! signal:%d\n", 1023 link->connector_signal); 1024 if (prev_sink) 1025 dc_sink_release(prev_sink); 1026 return false; 1027 } /* switch() */ 1028 1029 if (link->dpcd_caps.sink_count.bits.SINK_COUNT) 1030 link->dpcd_sink_count = 1031 link->dpcd_caps.sink_count.bits.SINK_COUNT; 1032 else 1033 link->dpcd_sink_count = 1; 1034 1035 set_ddc_transaction_type(link->ddc, 1036 sink_caps.transaction_type); 1037 1038 link->aux_mode = 1039 link_is_in_aux_transaction_mode(link->ddc); 1040 1041 sink_init_data.link = link; 1042 sink_init_data.sink_signal = sink_caps.signal; 1043 1044 sink = dc_sink_create(&sink_init_data); 1045 if (!sink) { 1046 DC_ERROR("Failed to create sink!\n"); 1047 if (prev_sink) 1048 dc_sink_release(prev_sink); 1049 return false; 1050 } 1051 1052 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; 1053 sink->converter_disable_audio = converter_disable_audio; 1054 1055 /* dc_sink_create returns a new reference */ 1056 link->local_sink = sink; 1057 1058 edid_status = dm_helpers_read_local_edid(link->ctx, 1059 link, sink); 1060 1061 switch (edid_status) { 1062 case EDID_BAD_CHECKSUM: 1063 DC_LOG_ERROR("EDID checksum invalid.\n"); 1064 break; 1065 case EDID_PARTIAL_VALID: 1066 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n"); 1067 break; 1068 case EDID_NO_RESPONSE: 1069 DC_LOG_ERROR("No EDID read.\n"); 1070 /* 1071 * Abort detection for non-DP connectors if we have 1072 * no EDID 1073 * 1074 * DP needs to report as connected if HDP is high 1075 * even if we have no EDID in order to go to 1076 * fail-safe mode 1077 */ 1078 if (dc_is_hdmi_signal(link->connector_signal) || 1079 dc_is_dvi_signal(link->connector_signal)) { 1080 if (prev_sink) 1081 dc_sink_release(prev_sink); 1082 1083 return false; 1084 } 1085 1086 if (link->type == dc_connection_sst_branch && 1087 link->dpcd_caps.dongle_type == 1088 DISPLAY_DONGLE_DP_VGA_CONVERTER && 1089 reason == DETECT_REASON_HPDRX) { 1090 /* Abort detection for DP-VGA adapters when EDID 1091 * can't be read and detection reason is VGA-side 1092 * hotplug 1093 */ 1094 if (prev_sink) 1095 dc_sink_release(prev_sink); 1096 link_disconnect_sink(link); 1097 1098 return true; 1099 } 1100 1101 break; 1102 default: 1103 break; 1104 } 1105 1106 // Check if edid is the same 1107 if ((prev_sink) && 1108 (edid_status == EDID_THE_SAME || edid_status == EDID_OK)) 1109 same_edid = is_same_edid(&prev_sink->dc_edid, 1110 &sink->dc_edid); 1111 1112 if (sink->edid_caps.panel_patch.skip_scdc_overwrite) 1113 link->ctx->dc->debug.hdmi20_disable = true; 1114 1115 if (sink->edid_caps.panel_patch.remove_sink_ext_caps) 1116 link->dpcd_sink_ext_caps.raw = 0; 1117 1118 if (dc_is_hdmi_signal(link->connector_signal)) 1119 read_scdc_caps(link->ddc, link->local_sink); 1120 1121 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 1122 sink_caps.transaction_type == 1123 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 1124 /* 1125 * TODO debug why certain monitors don't like 1126 * two link trainings 1127 */ 1128 query_hdcp_capability(sink->sink_signal, link); 1129 } else { 1130 // If edid is the same, then discard new sink and revert back to original sink 1131 if (same_edid) { 1132 link_disconnect_remap(prev_sink, link); 1133 sink = prev_sink; 1134 prev_sink = NULL; 1135 } 1136 query_hdcp_capability(sink->sink_signal, link); 1137 } 1138 1139 /* HDMI-DVI Dongle */ 1140 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && 1141 !sink->edid_caps.edid_hdmi) 1142 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1143 1144 if (link->local_sink && dc_is_dp_signal(sink_caps.signal)) 1145 dp_trace_init(link); 1146 1147 /* Connectivity log: detection */ 1148 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) { 1149 CONN_DATA_DETECT(link, 1150 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE], 1151 DC_EDID_BLOCK_SIZE, 1152 "%s: [Block %d] ", sink->edid_caps.display_name, i); 1153 } 1154 1155 DC_LOG_DETECTION_EDID_PARSER("%s: " 1156 "manufacturer_id = %X, " 1157 "product_id = %X, " 1158 "serial_number = %X, " 1159 "manufacture_week = %d, " 1160 "manufacture_year = %d, " 1161 "display_name = %s, " 1162 "speaker_flag = %d, " 1163 "audio_mode_count = %d\n", 1164 __func__, 1165 sink->edid_caps.manufacturer_id, 1166 sink->edid_caps.product_id, 1167 sink->edid_caps.serial_number, 1168 sink->edid_caps.manufacture_week, 1169 sink->edid_caps.manufacture_year, 1170 sink->edid_caps.display_name, 1171 sink->edid_caps.speaker_flags, 1172 sink->edid_caps.audio_mode_count); 1173 1174 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) { 1175 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, " 1176 "format_code = %d, " 1177 "channel_count = %d, " 1178 "sample_rate = %d, " 1179 "sample_size = %d\n", 1180 __func__, 1181 i, 1182 sink->edid_caps.audio_modes[i].format_code, 1183 sink->edid_caps.audio_modes[i].channel_count, 1184 sink->edid_caps.audio_modes[i].sample_rate, 1185 sink->edid_caps.audio_modes[i].sample_size); 1186 } 1187 1188 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1189 // Init dc_panel_config by HW config 1190 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) 1191 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); 1192 // Pickup base DM settings 1193 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink); 1194 // Override dc_panel_config if system has specific settings 1195 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config); 1196 1197 //sink only can use supported link rate table, we are foreced to enable it 1198 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN) 1199 link->panel_config.ilr.optimize_edp_link_rate = true; 1200 link->reported_link_cap.link_rate = get_max_edp_link_rate(link); 1201 } 1202 1203 } else { 1204 /* From Connected-to-Disconnected. */ 1205 link->type = dc_connection_none; 1206 sink_caps.signal = SIGNAL_TYPE_NONE; 1207 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps)); 1208 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk 1209 * is not cleared. If we emulate a DP signal on this connection, it thinks 1210 * the dongle is still there and limits the number of modes we can emulate. 1211 * Clear dongle_max_pix_clk on disconnect to fix this 1212 */ 1213 link->dongle_max_pix_clk = 0; 1214 1215 dc_link_clear_dprx_states(link); 1216 dp_trace_reset(link); 1217 } 1218 1219 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n", 1220 link->link_index, sink, 1221 (sink_caps.signal == 1222 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"), 1223 prev_sink, same_edid); 1224 1225 if (prev_sink) 1226 dc_sink_release(prev_sink); 1227 1228 return true; 1229 } 1230 1231 /* 1232 * link_detect_connection_type() - Determine if there is a sink connected 1233 * 1234 * @type: Returned connection type 1235 * Does not detect downstream devices, such as MST sinks 1236 * or display connected through active dongles 1237 */ 1238 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type) 1239 { 1240 uint32_t is_hpd_high = 0; 1241 1242 if (link->connector_signal == SIGNAL_TYPE_LVDS) { 1243 *type = dc_connection_single; 1244 return true; 1245 } 1246 1247 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1248 /*in case it is not on*/ 1249 if (!link->dc->config.edp_no_power_sequencing) 1250 link->dc->hwss.edp_power_control(link, true); 1251 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 1252 } 1253 1254 /* Link may not have physical HPD pin. */ 1255 if (link->ep_type != DISPLAY_ENDPOINT_PHY) { 1256 if (link->is_hpd_pending || !dpia_query_hpd_status(link)) 1257 *type = dc_connection_none; 1258 else 1259 *type = dc_connection_single; 1260 1261 return true; 1262 } 1263 1264 1265 if (!query_hpd_status(link, &is_hpd_high)) 1266 goto hpd_gpio_failure; 1267 1268 if (is_hpd_high) { 1269 *type = dc_connection_single; 1270 /* TODO: need to do the actual detection */ 1271 } else { 1272 *type = dc_connection_none; 1273 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1274 /* eDP is not connected, power down it */ 1275 if (!link->dc->config.edp_no_power_sequencing) 1276 link->dc->hwss.edp_power_control(link, false); 1277 } 1278 } 1279 1280 return true; 1281 1282 hpd_gpio_failure: 1283 return false; 1284 } 1285 1286 bool link_detect(struct dc_link *link, enum dc_detect_reason reason) 1287 { 1288 bool is_local_sink_detect_success; 1289 bool is_delegated_to_mst_top_mgr = false; 1290 enum dc_connection_type pre_link_type = link->type; 1291 1292 DC_LOGGER_INIT(link->ctx->logger); 1293 1294 is_local_sink_detect_success = detect_link_and_local_sink(link, reason); 1295 1296 if (is_local_sink_detect_success && link->local_sink) 1297 verify_link_capability(link, link->local_sink, reason); 1298 1299 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__, 1300 link->link_index, is_local_sink_detect_success, pre_link_type, link->type); 1301 1302 if (is_local_sink_detect_success && link->local_sink && 1303 dc_is_dp_signal(link->local_sink->sink_signal) && 1304 link->dpcd_caps.is_mst_capable) 1305 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason); 1306 1307 if (pre_link_type == dc_connection_mst_branch && 1308 link->type != dc_connection_mst_branch) 1309 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link); 1310 1311 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr; 1312 } 1313 1314 void link_clear_dprx_states(struct dc_link *link) 1315 { 1316 memset(&link->dprx_states, 0, sizeof(link->dprx_states)); 1317 } 1318 1319 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal) 1320 { 1321 bool ret = false; 1322 1323 switch (signal) { 1324 case SIGNAL_TYPE_DISPLAY_PORT: 1325 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1326 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE; 1327 break; 1328 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1329 case SIGNAL_TYPE_DVI_DUAL_LINK: 1330 case SIGNAL_TYPE_HDMI_TYPE_A: 1331 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable, 1332 * we can poll for bksv but some displays have an issue with this. Since its so rare 1333 * for a display to not be 1.4 capable, this assumtion is ok 1334 */ 1335 ret = true; 1336 break; 1337 default: 1338 break; 1339 } 1340 return ret; 1341 } 1342 1343 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal) 1344 { 1345 bool ret = false; 1346 1347 switch (signal) { 1348 case SIGNAL_TYPE_DISPLAY_PORT: 1349 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1350 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE && 1351 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable && 1352 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0; 1353 break; 1354 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1355 case SIGNAL_TYPE_DVI_DUAL_LINK: 1356 case SIGNAL_TYPE_HDMI_TYPE_A: 1357 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0; 1358 break; 1359 default: 1360 break; 1361 } 1362 1363 return ret; 1364 } 1365 1366 const struct dc_link_status *link_get_status(const struct dc_link *link) 1367 { 1368 return &link->link_status; 1369 } 1370 1371 1372 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) 1373 { 1374 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { 1375 BREAK_TO_DEBUGGER(); 1376 return false; 1377 } 1378 1379 dc_sink_retain(sink); 1380 1381 dc_link->remote_sinks[dc_link->sink_count] = sink; 1382 dc_link->sink_count++; 1383 1384 return true; 1385 } 1386 1387 struct dc_sink *link_add_remote_sink( 1388 struct dc_link *link, 1389 const uint8_t *edid, 1390 int len, 1391 struct dc_sink_init_data *init_data) 1392 { 1393 struct dc_sink *dc_sink; 1394 enum dc_edid_status edid_status; 1395 1396 if (len > DC_MAX_EDID_BUFFER_SIZE) { 1397 dm_error("Max EDID buffer size breached!\n"); 1398 return NULL; 1399 } 1400 1401 if (!init_data) { 1402 BREAK_TO_DEBUGGER(); 1403 return NULL; 1404 } 1405 1406 if (!init_data->link) { 1407 BREAK_TO_DEBUGGER(); 1408 return NULL; 1409 } 1410 1411 dc_sink = dc_sink_create(init_data); 1412 1413 if (!dc_sink) 1414 return NULL; 1415 1416 memmove(dc_sink->dc_edid.raw_edid, edid, len); 1417 dc_sink->dc_edid.length = len; 1418 1419 if (!link_add_remote_sink_helper( 1420 link, 1421 dc_sink)) 1422 goto fail_add_sink; 1423 1424 edid_status = dm_helpers_parse_edid_caps( 1425 link, 1426 &dc_sink->dc_edid, 1427 &dc_sink->edid_caps); 1428 1429 /* 1430 * Treat device as no EDID device if EDID 1431 * parsing fails 1432 */ 1433 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) { 1434 dc_sink->dc_edid.length = 0; 1435 dm_error("Bad EDID, status%d!\n", edid_status); 1436 } 1437 1438 return dc_sink; 1439 1440 fail_add_sink: 1441 dc_sink_release(dc_sink); 1442 return NULL; 1443 } 1444 1445 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) 1446 { 1447 int i; 1448 1449 if (!link->sink_count) { 1450 BREAK_TO_DEBUGGER(); 1451 return; 1452 } 1453 1454 for (i = 0; i < link->sink_count; i++) { 1455 if (link->remote_sinks[i] == sink) { 1456 dc_sink_release(sink); 1457 link->remote_sinks[i] = NULL; 1458 1459 /* shrink array to remove empty place */ 1460 while (i < link->sink_count - 1) { 1461 link->remote_sinks[i] = link->remote_sinks[i+1]; 1462 i++; 1463 } 1464 link->remote_sinks[i] = NULL; 1465 link->sink_count--; 1466 return; 1467 } 1468 } 1469 } 1470