xref: /linux/drivers/gpu/drm/amd/display/dc/irq/irq_service.c (revision fcab107abe1ab5be9dbe874baa722372da8f4f73)
1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "include/irq_service_interface.h"
29 #include "include/logger_interface.h"
30 
31 #include "dce110/irq_service_dce110.h"
32 
33 #if defined(CONFIG_DRM_AMD_DC_SI)
34 #include "dce60/irq_service_dce60.h"
35 #endif
36 
37 #include "dce80/irq_service_dce80.h"
38 #include "dce120/irq_service_dce120.h"
39 #include "dcn10/irq_service_dcn10.h"
40 
41 #include "reg_helper.h"
42 #include "irq_service.h"
43 
44 //HPD0_DC_HPD_INT_STATUS
45 #define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK		0x00000010L
46 #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK		0x00000100L
47 #define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT		0x4
48 #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT     0x8
49 //HPD1_DC_HPD_INT_STATUS
50 #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK			0x10
51 #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT		0x4
52 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK			0x100
53 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT		0x8
54 
55 
56 #define CTX \
57 		irq_service->ctx
58 #define DC_LOGGER \
59 	irq_service->ctx->logger
60 
61 void dal_irq_service_construct(
62 	struct irq_service *irq_service,
63 	struct irq_service_init_data *init_data)
64 {
65 	if (!init_data || !init_data->ctx) {
66 		BREAK_TO_DEBUGGER();
67 		return;
68 	}
69 
70 	irq_service->ctx = init_data->ctx;
71 }
72 
73 void dal_irq_service_destroy(struct irq_service **irq_service)
74 {
75 	if (!irq_service || !*irq_service) {
76 		BREAK_TO_DEBUGGER();
77 		return;
78 	}
79 
80 	kfree(*irq_service);
81 
82 	*irq_service = NULL;
83 }
84 
85 static const struct irq_source_info *find_irq_source_info(
86 	struct irq_service *irq_service,
87 	enum dc_irq_source source)
88 {
89 	if (source >= DAL_IRQ_SOURCES_NUMBER)
90 		return NULL;
91 
92 	return &irq_service->info[source];
93 }
94 
95 void dal_irq_service_set_generic(
96 	struct irq_service *irq_service,
97 	const struct irq_source_info *info,
98 	bool enable)
99 {
100 	uint32_t addr = info->enable_reg;
101 	uint32_t value = dm_read_reg(irq_service->ctx, addr);
102 
103 	value = (value & ~info->enable_mask) |
104 		(info->enable_value[enable ? 0 : 1] & info->enable_mask);
105 	dm_write_reg(irq_service->ctx, addr, value);
106 }
107 
108 bool dal_irq_service_set(
109 	struct irq_service *irq_service,
110 	enum dc_irq_source source,
111 	bool enable)
112 {
113 	const struct irq_source_info *info =
114 		find_irq_source_info(irq_service, source);
115 
116 	if (!info) {
117 		DC_LOG_ERROR("%s: cannot find irq info table entry for %d\n",
118 			__func__,
119 			source);
120 		return false;
121 	}
122 
123 	dal_irq_service_ack(irq_service, source);
124 
125 	if (info->funcs && info->funcs->set) {
126 		if (info->funcs->set == dal_irq_service_dummy_set) {
127 			DC_LOG_WARNING("%s: src: %d, st: %d\n", __func__,
128 				       source, enable);
129 			ASSERT(0);
130 		}
131 
132 		return info->funcs->set(irq_service, info, enable);
133 	}
134 
135 	dal_irq_service_set_generic(irq_service, info, enable);
136 
137 	return true;
138 }
139 
140 void dal_irq_service_ack_generic(
141 	struct irq_service *irq_service,
142 	const struct irq_source_info *info)
143 {
144 	uint32_t addr = info->ack_reg;
145 	uint32_t value = dm_read_reg(irq_service->ctx, addr);
146 
147 	value = (value & ~info->ack_mask) |
148 		(info->ack_value & info->ack_mask);
149 	dm_write_reg(irq_service->ctx, addr, value);
150 }
151 
152 bool dal_irq_service_ack(
153 	struct irq_service *irq_service,
154 	enum dc_irq_source source)
155 {
156 	const struct irq_source_info *info =
157 		find_irq_source_info(irq_service, source);
158 
159 	if (!info) {
160 		DC_LOG_ERROR("%s: cannot find irq info table entry for %d\n",
161 			__func__,
162 			source);
163 		return false;
164 	}
165 
166 	if (info->funcs && info->funcs->ack) {
167 		if (info->funcs->ack == dal_irq_service_dummy_ack) {
168 			DC_LOG_WARNING("%s: src: %d\n", __func__, source);
169 			ASSERT(0);
170 		}
171 
172 		return info->funcs->ack(irq_service, info);
173 	}
174 
175 	dal_irq_service_ack_generic(irq_service, info);
176 
177 	return true;
178 }
179 
180 enum dc_irq_source dal_irq_service_to_irq_source(
181 		struct irq_service *irq_service,
182 		uint32_t src_id,
183 		uint32_t ext_id)
184 {
185 	return irq_service->funcs->to_dal_irq_source(
186 		irq_service,
187 		src_id,
188 		ext_id);
189 }
190 
191 bool hpd0_ack(
192 	struct irq_service *irq_service,
193 	const struct irq_source_info *info)
194 {
195 	uint32_t addr = info->status_reg;
196 	uint32_t value = dm_read_reg(irq_service->ctx, addr);
197 	uint32_t current_status =
198 		get_reg_field_value(
199 			value,
200 			HPD0_DC_HPD_INT_STATUS,
201 			DC_HPD_SENSE_DELAYED);
202 
203 	dal_irq_service_ack_generic(irq_service, info);
204 
205 	value = dm_read_reg(irq_service->ctx, info->enable_reg);
206 
207 	set_reg_field_value(
208 		value,
209 		current_status ? 0 : 1,
210 		HPD0_DC_HPD_INT_CONTROL,
211 		DC_HPD_INT_POLARITY);
212 
213 	dm_write_reg(irq_service->ctx, info->enable_reg, value);
214 
215 	return true;
216 }
217 
218 bool hpd1_ack(
219 	struct irq_service *irq_service,
220 	const struct irq_source_info *info)
221 {
222 	uint32_t addr = info->status_reg;
223 	uint32_t value = dm_read_reg(irq_service->ctx, addr);
224 	uint32_t current_status =
225 		get_reg_field_value(
226 			value,
227 			DC_HPD1_INT_STATUS,
228 			DC_HPD1_SENSE_DELAYED);
229 
230 	dal_irq_service_ack_generic(irq_service, info);
231 
232 	value = dm_read_reg(irq_service->ctx, info->enable_reg);
233 
234 	set_reg_field_value(
235 		value,
236 		current_status ? 0 : 1,
237 		DC_HPD1_INT_CONTROL,
238 		DC_HPD1_INT_POLARITY);
239 
240 	dm_write_reg(irq_service->ctx, info->enable_reg, value);
241 
242 	return true;
243 }
244