1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 */ 24 25 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 26 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 27 28 #include "core_types.h" 29 #include "core_status.h" 30 #include "dal_asic_id.h" 31 #include "dm_pp_smu.h" 32 33 #define MEMORY_TYPE_MULTIPLIER_CZ 4 34 #define MEMORY_TYPE_HBM 2 35 36 37 #define IS_PIPE_SYNCD_VALID(pipe) ((((pipe)->pipe_idx_syncd) & 0x80)?1:0) 38 #define GET_PIPE_SYNCD_FROM_PIPE(pipe) ((pipe)->pipe_idx_syncd & 0x7F) 39 #define SET_PIPE_SYNCD_TO_PIPE(pipe, pipe_syncd) ((pipe)->pipe_idx_syncd = (0x80 | pipe_syncd)) 40 41 enum dce_version resource_parse_asic_id( 42 struct hw_asic_id asic_id); 43 44 struct resource_caps { 45 int num_timing_generator; 46 int num_opp; 47 int num_video_plane; 48 int num_audio; 49 int num_stream_encoder; 50 int num_pll; 51 int num_dwb; 52 int num_ddc; 53 int num_vmid; 54 int num_dsc; 55 unsigned int num_dig_link_enc; // Total number of DIGs (digital encoders) in DIO (Display Input/Output). 56 unsigned int num_usb4_dpia; // Total number of USB4 DPIA (DisplayPort Input Adapters). 57 int num_hpo_dp_stream_encoder; 58 int num_hpo_dp_link_encoder; 59 int num_mpc_3dlut; 60 }; 61 62 struct resource_straps { 63 uint32_t hdmi_disable; 64 uint32_t dc_pinstraps_audio; 65 uint32_t audio_stream_number; 66 }; 67 68 struct resource_create_funcs { 69 void (*read_dce_straps)( 70 struct dc_context *ctx, struct resource_straps *straps); 71 72 struct audio *(*create_audio)( 73 struct dc_context *ctx, unsigned int inst); 74 75 struct stream_encoder *(*create_stream_encoder)( 76 enum engine_id eng_id, struct dc_context *ctx); 77 78 struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)( 79 enum engine_id eng_id, struct dc_context *ctx); 80 81 struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)( 82 uint8_t inst, 83 struct dc_context *ctx); 84 85 struct dce_hwseq *(*create_hwseq)( 86 struct dc_context *ctx); 87 }; 88 89 bool resource_construct( 90 unsigned int num_virtual_links, 91 struct dc *dc, 92 struct resource_pool *pool, 93 const struct resource_create_funcs *create_funcs); 94 95 struct resource_pool *dc_create_resource_pool(struct dc *dc, 96 const struct dc_init_data *init_data, 97 enum dce_version dc_version); 98 99 void dc_destroy_resource_pool(struct dc *dc); 100 101 enum dc_status resource_map_pool_resources( 102 const struct dc *dc, 103 struct dc_state *context, 104 struct dc_stream_state *stream); 105 106 void resource_build_test_pattern_params( 107 struct resource_context *res_ctx, 108 struct pipe_ctx *pipe_ctx); 109 110 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); 111 112 enum dc_status resource_build_scaling_params_for_context( 113 const struct dc *dc, 114 struct dc_state *context); 115 116 void resource_build_info_frame(struct pipe_ctx *pipe_ctx); 117 118 void resource_unreference_clock_source( 119 struct resource_context *res_ctx, 120 const struct resource_pool *pool, 121 struct clock_source *clock_source); 122 123 void resource_reference_clock_source( 124 struct resource_context *res_ctx, 125 const struct resource_pool *pool, 126 struct clock_source *clock_source); 127 128 int resource_get_clock_source_reference( 129 struct resource_context *res_ctx, 130 const struct resource_pool *pool, 131 struct clock_source *clock_source); 132 133 bool resource_are_streams_timing_synchronizable( 134 struct dc_stream_state *stream1, 135 struct dc_stream_state *stream2); 136 137 bool resource_are_vblanks_synchronizable( 138 struct dc_stream_state *stream1, 139 struct dc_stream_state *stream2); 140 141 struct clock_source *resource_find_used_clk_src_for_sharing( 142 struct resource_context *res_ctx, 143 struct pipe_ctx *pipe_ctx); 144 145 struct clock_source *dc_resource_find_first_free_pll( 146 struct resource_context *res_ctx, 147 const struct resource_pool *pool); 148 149 bool resource_attach_surfaces_to_context( 150 struct dc_plane_state *const *plane_state, 151 int surface_count, 152 struct dc_stream_state *dc_stream, 153 struct dc_state *context, 154 const struct resource_pool *pool); 155 156 #define FREE_PIPE_INDEX_NOT_FOUND -1 157 158 /* 159 * pipe types are identified based on MUXes in DCN front end that are capable 160 * of taking input from one DCN pipeline to another DCN pipeline. The name is 161 * in a form of XXXX_YYYY, where XXXX is the DCN front end hardware block the 162 * pipeline ends with and YYYY is the rendering role that the pipe is in. 163 * 164 * For instance OTG_MASTER is a pipe ending with OTG hardware block in its 165 * pipeline and it is in a role of a master pipe for timing generation. 166 * 167 * For quick reference a diagram of each pipe type's areas of responsibility 168 * for outputting timings on the screen is shown below: 169 * 170 * Timing Active for Stream 0 171 * __________________________________________________ 172 * |OTG master 0 (OPP head 0)|OPP head 2 (DPP pipe 2) | 173 * | (DPP pipe 0)| | 174 * | Top Plane 0 | | 175 * | ______________|____ | 176 * | |DPP pipe 1 |DPP | | 177 * | | |pipe| | 178 * | | Bottom |3 | | 179 * | | Plane 1 | | | 180 * | | | | | 181 * | |______________|____| | 182 * | | | 183 * | | | 184 * | ODM slice 0 | ODM slice 1 | 185 * |_________________________|________________________| 186 * 187 * Timing Active for Stream 1 188 * __________________________________________________ 189 * |OTG master 4 (OPP head 4) | 190 * | | 191 * | | 192 * | | 193 * | | 194 * | | 195 * | Blank Pixel Data | 196 * | (generated by DPG4) | 197 * | | 198 * | | 199 * | | 200 * | | 201 * | | 202 * |__________________________________________________| 203 * 204 * Inter-pipe Relation 205 * __________________________________________________ 206 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER | 207 * | | plane 0 | slice 0 | | 208 * | 0 | -------------MPC---------ODM----------- | 209 * | | plane 1 | | | | | 210 * | 1 | ------------- | | | | 211 * | | plane 0 | slice 1 | | | 212 * | 2 | -------------MPC--------- | | 213 * | | plane 1 | | | | 214 * | 3 | ------------- | | | 215 * | | | blank | | 216 * | 4 | | ----------------------- | 217 * | | | | | 218 * | 5 | (FREE) | | | 219 * |________|_______________|___________|_____________| 220 * 221 * The following is a quick reference of the class relation: 222 * 223 * DC state ---1--------0..N--- streams 224 * 225 * stream ---1-----------1--- OTG Master pipe 226 * 227 * OTG Master pipe ---1--------1..N--- OPP Head pipes 228 * 229 * OPP Head pipe ---1--------0..N--- DPP pipes 230 * 231 * stream ---1--------0..N--- Planes 232 * 233 * Plane ---1--------1..N--- DPP pipes 234 * 235 */ 236 enum pipe_type { 237 /* free pipe - free pipe is an uninitialized pipe without a stream 238 * associated with it. It is a free DCN pipe resource. It can be 239 * acquired as any type of pipe. 240 */ 241 FREE_PIPE, 242 243 /* OTG master pipe - the master pipe of its OPP head pipes with a 244 * functional OTG. It merges all its OPP head pipes pixel data in ODM 245 * block and output to back end DIG. OTG master pipe is responsible for 246 * generating entire CRTC timing to back end DIG. An OTG master pipe may 247 * or may not have a plane. If it has a plane it blends it as the left 248 * most MPC slice of the top most layer. If it doesn't have a plane it 249 * can output pixel data from its OPP head pipes' test pattern 250 * generators (DPG) such as solid black pixel data to blank the screen. 251 */ 252 OTG_MASTER, 253 254 /* OPP head pipe - the head pipe of an MPC blending tree with a 255 * functional OPP outputting to an OTG. OPP head pipe is responsible for 256 * processing output pixels in its own ODM slice. It may or may not have 257 * a plane. If it has a plane it blends it as the top most layer within 258 * its own ODM slice. If it doesn't have a plane it can output pixel 259 * data from its DPG such as solid black pixel data to blank the pixel 260 * data in its own ODM slice. OTG master pipe is also an OPP head pipe 261 * but with more responsibility. 262 */ 263 OPP_HEAD, 264 265 /* DPP pipe - the pipe with a functional DPP outputting to an OPP head 266 * pipe's MPC. DPP pipe is responsible for processing pixel data from 267 * its own MPC slice of a plane. It must be connected to an OPP head 268 * pipe and it must have a plane associated with it. 269 */ 270 DPP_PIPE, 271 }; 272 273 /* 274 * Determine if the input pipe_ctx is of a pipe type. 275 * return - true if pipe_ctx is of the input type. 276 */ 277 bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type); 278 279 /* 280 * Acquire a pipe as OTG master pipe and allocate pipe resources required to 281 * enable stream output. 282 */ 283 enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx, 284 const struct resource_pool *pool, 285 struct dc_stream_state *stream); 286 287 /* 288 * Release pipe resources and the OTG master pipe associated with the stream 289 * The stream must have all planes removed and ODM/MPC slice counts are reset 290 * to 1 before invoking this interface. 291 */ 292 void resource_remove_otg_master_for_stream_output(struct dc_state *new_ctx, 293 const struct resource_pool *pool, 294 struct dc_stream_state *stream); 295 296 /* 297 * Add plane to the bottom most layer in plane composition and allocate DPP pipe 298 * resources as needed. 299 * return - true if plane is added in plane composition, false otherwise. 300 */ 301 bool resource_append_dpp_pipes_for_plane_composition( 302 struct dc_state *new_ctx, 303 struct dc_state *cur_ctx, 304 struct resource_pool *pool, 305 struct pipe_ctx *otg_master_pipe, 306 struct dc_plane_state *plane_state); 307 308 /* 309 * Add plane to the bottom most layer in plane composition and allocate DPP pipe 310 * resources as needed. 311 * return - true if plane is added in plane composition, false otherwise. 312 */ 313 void resource_remove_dpp_pipes_for_plane_composition( 314 struct dc_state *context, 315 const struct resource_pool *pool, 316 const struct dc_plane_state *plane_state); 317 318 /* 319 * Update ODM slice count by acquiring or releasing pipes. If new slices need 320 * to be added, it is going to add them to the last ODM index. If existing 321 * slices need to be removed, it is going to remove them from the last ODM 322 * index. 323 * 324 * return - true if ODM slices are updated and required pipes are acquired. All 325 * affected pipe parameters are updated. 326 * 327 * false if resource fails to complete this update. The function is not designed 328 * to recover the creation of invalid topologies. Returning false is typically 329 * an indication of insufficient validation in caller's stack. new_ctx will be 330 * invalid. Caller may attempt to restore new_ctx by calling this function 331 * again with original slice count. 332 */ 333 bool resource_update_pipes_for_stream_with_slice_count( 334 struct dc_state *new_ctx, 335 const struct dc_state *cur_ctx, 336 const struct resource_pool *pool, 337 const struct dc_stream_state *stream, 338 int new_slice_count); 339 340 /* 341 * Update MPC slice count by acquiring or releasing DPP pipes. If new slices 342 * need to be added it is going to add to the last MPC index. If existing 343 * slices need to be removed, it is going to remove them from the last MPC 344 * index. 345 * 346 * @dpp_pipe - top most dpp pipe for MPCC combine. 347 * 348 * return - true if MPC slices are updated and required pipes are acquired. All 349 * affected pipe parameters are updated. 350 * 351 * false if resource fails to complete this update. The function is not designed 352 * to recover the creation of invalid topologies. Returning false is typically 353 * an indication of insufficient validation in caller's stack. new_ctx will be 354 * invalid. Caller may attempt to restore new_ctx by calling this function 355 * again with original slice count. 356 */ 357 bool resource_update_pipes_for_plane_with_slice_count( 358 struct dc_state *new_ctx, 359 const struct dc_state *cur_ctx, 360 const struct resource_pool *pool, 361 const struct dc_plane_state *plane, 362 int slice_count); 363 364 /* 365 * Get the OTG master pipe in resource context associated with the stream. 366 * return - NULL if not found. Otherwise the OTG master pipe associated with the 367 * stream. 368 */ 369 struct pipe_ctx *resource_get_otg_master_for_stream( 370 struct resource_context *res_ctx, 371 const struct dc_stream_state *stream); 372 373 /* 374 * Get an array of OPP heads in opp_heads ordered with index low to high for OTG 375 * master pipe in res_ctx. 376 * return - number of OPP heads in the array. If otg_master passed in is not 377 * an OTG master, the function returns 0. 378 */ 379 int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master, 380 struct resource_context *res_ctx, 381 struct pipe_ctx *opp_heads[MAX_PIPES]); 382 383 /* 384 * Get an array of DPP pipes in dpp_pipes ordered with index low to high for OPP 385 * head pipe in res_ctx. 386 * return - number of DPP pipes in the array. If opp_head passed in is not 387 * an OPP pipe, the function returns 0. 388 */ 389 int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head, 390 struct resource_context *res_ctx, 391 struct pipe_ctx *dpp_pipes[MAX_PIPES]); 392 393 /* 394 * Get an array of DPP pipes in dpp_pipes ordered with index low to high for 395 * plane in res_ctx. 396 * return - number of DPP pipes in the array. 397 */ 398 int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane, 399 struct resource_context *res_ctx, 400 struct pipe_ctx *dpp_pipes[MAX_PIPES]); 401 402 /* 403 * Get the OTG master pipe for the input pipe context. 404 * return - the OTG master pipe for the input pipe 405 * context. 406 */ 407 struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx); 408 409 /* 410 * Get the OPP head pipe for the input pipe context. 411 * return - the OPP head pipe for the input pipe 412 * context. 413 */ 414 struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx); 415 416 /* 417 * Get the DPP pipe allocated for MPC slice 0 and ODM slice 0 of the plane 418 * associated with dpp_pipe. 419 */ 420 struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe); 421 422 /* 423 * Get the MPC slice index counting from 0 from left most slice 424 * For example, if a DPP pipe is used as a secondary pipe in MPCC combine, MPC 425 * split index is greater than 0. 426 */ 427 int resource_get_mpc_slice_index(const struct pipe_ctx *dpp_pipe); 428 429 /* 430 * Get number of MPC "cuts" of the plane associated with the pipe. MPC slice 431 * count is equal to MPC splits + 1. For example if a plane is cut 3 times, it 432 * will have 4 pieces of slice. 433 * return - 0 if pipe is not used for a plane with MPCC combine. otherwise 434 * the number of MPC "cuts" for the plane. 435 */ 436 int resource_get_mpc_slice_count(const struct pipe_ctx *opp_head); 437 438 /* 439 * Get number of ODM "cuts" of the timing associated with the pipe. ODM slice 440 * count is equal to ODM splits + 1. For example if a timing is cut 3 times, it 441 * will have 4 pieces of slice. 442 * return - 0 if pipe is not used for ODM combine. otherwise 443 * the number of ODM "cuts" for the timing. 444 */ 445 int resource_get_odm_slice_count(const struct pipe_ctx *otg_master); 446 447 /* Get the ODM slice index counting from 0 from left most slice */ 448 int resource_get_odm_slice_index(const struct pipe_ctx *opp_head); 449 450 /* determine if pipe topology is changed between state a and state b */ 451 bool resource_is_pipe_topology_changed(const struct dc_state *state_a, 452 const struct dc_state *state_b); 453 454 /* 455 * determine if the two OTG master pipes have the same ODM topology 456 * return 457 * false - if pipes passed in are not OTG masters or ODM topology is 458 * changed. 459 * true - otherwise 460 */ 461 bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a, 462 const struct pipe_ctx *otg_master_b); 463 464 /* log the pipe topology update in state */ 465 void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state); 466 467 /* 468 * Look for a free pipe in new resource context that is used as a secondary OPP 469 * head by cur_otg_master. 470 * 471 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise 472 * pipe idx of the free pipe 473 */ 474 int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master( 475 const struct resource_context *cur_res_ctx, 476 struct resource_context *new_res_ctx, 477 const struct pipe_ctx *cur_otg_master); 478 479 /* 480 * Look for a free pipe in new resource context that is used as a secondary DPP 481 * pipe in MPC blending tree associated with input OPP head pipe. 482 * 483 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise 484 * pipe idx of the free pipe 485 */ 486 int resource_find_free_pipe_used_in_cur_mpc_blending_tree( 487 const struct resource_context *cur_res_ctx, 488 struct resource_context *new_res_ctx, 489 const struct pipe_ctx *cur_opp_head); 490 491 /* 492 * Look for a free pipe in new resource context that is not used in current 493 * resource context. 494 * 495 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise 496 * pipe idx of the free pipe 497 */ 498 int recource_find_free_pipe_not_used_in_cur_res_ctx( 499 const struct resource_context *cur_res_ctx, 500 struct resource_context *new_res_ctx, 501 const struct resource_pool *pool); 502 503 /* 504 * Look for a free pipe in new resource context that is used as a secondary DPP 505 * pipe in any MPCC combine in current resource context. 506 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise 507 * pipe idx of the free pipe 508 */ 509 int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine( 510 const struct resource_context *cur_res_ctx, 511 struct resource_context *new_res_ctx, 512 const struct resource_pool *pool); 513 514 /* 515 * Look for any free pipe in new resource context. 516 * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise 517 * pipe idx of the free pipe 518 */ 519 int resource_find_any_free_pipe(struct resource_context *new_res_ctx, 520 const struct resource_pool *pool); 521 522 /* 523 * Legacy find free secondary pipe logic deprecated for newer DCNs as it doesn't 524 * find the most optimal free pipe to prevent from time consuming hardware state 525 * transitions. 526 */ 527 struct pipe_ctx *resource_find_free_secondary_pipe_legacy( 528 struct resource_context *res_ctx, 529 const struct resource_pool *pool, 530 const struct pipe_ctx *primary_pipe); 531 532 bool resource_validate_attach_surfaces( 533 const struct dc_validation_set set[], 534 int set_count, 535 const struct dc_state *old_context, 536 struct dc_state *context, 537 const struct resource_pool *pool); 538 539 enum dc_status resource_map_clock_resources( 540 const struct dc *dc, 541 struct dc_state *context, 542 struct dc_stream_state *stream); 543 544 enum dc_status resource_map_phy_clock_resources( 545 const struct dc *dc, 546 struct dc_state *context, 547 struct dc_stream_state *stream); 548 549 bool pipe_need_reprogram( 550 struct pipe_ctx *pipe_ctx_old, 551 struct pipe_ctx *pipe_ctx); 552 553 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 554 struct bit_depth_reduction_params *fmt_bit_depth); 555 556 void update_audio_usage( 557 struct resource_context *res_ctx, 558 const struct resource_pool *pool, 559 struct audio *audio, 560 bool acquired); 561 562 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format); 563 564 void get_audio_check(struct audio_info *aud_modes, 565 struct audio_check *aud_chk); 566 567 bool get_temp_dp_link_res(struct dc_link *link, 568 struct link_resource *link_res, 569 struct dc_link_settings *link_settings); 570 571 #if defined(CONFIG_DRM_AMD_DC_FP) 572 struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt( 573 const struct resource_context *res_ctx, 574 const struct resource_pool *pool, 575 const struct dc_link *link); 576 #endif 577 578 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, 579 struct dc_state *context); 580 581 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, 582 struct dc_state *context, 583 uint8_t disabled_master_pipe_idx); 584 585 void reset_sync_context_for_pipe(const struct dc *dc, 586 struct dc_state *context, 587 uint8_t pipe_idx); 588 589 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter); 590 591 const struct link_hwss *get_link_hwss(const struct dc_link *link, 592 const struct link_resource *link_res); 593 594 bool is_h_timing_divisible_by_2(struct dc_stream_state *stream); 595 596 bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy( 597 const struct dc *dc, 598 struct dc_state *state, 599 struct pipe_ctx *pri_pipe, 600 struct pipe_ctx *sec_pipe, 601 bool odm); 602 603 /* A test harness interface that modifies dp encoder resources in the given dc 604 * state and bypasses the need to revalidate. The interface assumes that the 605 * test harness interface is called with pre-validated link config stored in the 606 * pipe_ctx and updates dp encoder resources according to the link config. 607 */ 608 enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc, 609 struct dc_state *context, 610 struct pipe_ctx *pipe_ctx); 611 612 bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream); 613 614 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ 615