1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_HUBP_H__ 27 #define __DAL_HUBP_H__ 28 29 /** 30 * DOC: overview 31 * 32 * Display Controller Hub (DCHUB) is the gateway between the Scalable Data Port 33 * (SDP) and DCN. This component has multiple features, such as memory 34 * arbitration, rotation, and cursor manipulation. 35 * 36 * There is one HUBP allocated per pipe, which fetches data and converts 37 * different pixel formats (i.e. ARGB8888, NV12, etc) into linear, interleaved 38 * and fixed-depth streams of pixel data. 39 */ 40 41 #include "mem_input.h" 42 #include "cursor_reg_cache.h" 43 44 #include "dml2/dml21/inc/dml_top_dchub_registers.h" 45 #include "dml2/dml21/inc/dml_top_types.h" 46 47 #define OPP_ID_INVALID 0xf 48 #define MAX_TTU 0xffffff 49 50 enum cursor_pitch { 51 CURSOR_PITCH_64_PIXELS = 0, 52 CURSOR_PITCH_128_PIXELS, 53 CURSOR_PITCH_256_PIXELS 54 }; 55 56 enum cursor_lines_per_chunk { 57 CURSOR_LINE_PER_CHUNK_1 = 0, /* new for DCN2 */ 58 CURSOR_LINE_PER_CHUNK_2 = 1, 59 CURSOR_LINE_PER_CHUNK_4, 60 CURSOR_LINE_PER_CHUNK_8, 61 CURSOR_LINE_PER_CHUNK_16 62 }; 63 64 enum hubp_ind_block_size { 65 hubp_ind_block_unconstrained = 0, 66 hubp_ind_block_64b, 67 hubp_ind_block_128b, 68 hubp_ind_block_64b_no_128bcl, 69 }; 70 71 enum hubp_3dlut_fl_mode { 72 hubp_3dlut_fl_mode_disable = 0, 73 hubp_3dlut_fl_mode_native_1 = 1, 74 hubp_3dlut_fl_mode_native_2 = 2, 75 hubp_3dlut_fl_mode_transform = 3 76 }; 77 78 enum hubp_3dlut_fl_format { 79 hubp_3dlut_fl_format_unorm_12msb_bitslice = 0, 80 hubp_3dlut_fl_format_unorm_12lsb_bitslice = 1, 81 hubp_3dlut_fl_format_float_fp1_5_10 = 2 82 }; 83 84 enum hubp_3dlut_fl_addressing_mode { 85 hubp_3dlut_fl_addressing_mode_sw_linear = 0, 86 hubp_3dlut_fl_addressing_mode_simple_linear = 1 87 }; 88 89 enum hubp_3dlut_fl_width { 90 hubp_3dlut_fl_width_17 = 17, 91 hubp_3dlut_fl_width_33 = 33, 92 hubp_3dlut_fl_width_transformed = 4916, //mpc default 93 }; 94 95 enum hubp_3dlut_fl_crossbar_bit_slice { 96 hubp_3dlut_fl_crossbar_bit_slice_0_15 = 0, 97 hubp_3dlut_fl_crossbar_bit_slice_16_31 = 1, 98 hubp_3dlut_fl_crossbar_bit_slice_32_47 = 2, 99 hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3 100 }; 101 102 struct hubp_fl_3dlut_config { 103 bool enabled; 104 enum hubp_3dlut_fl_width width; 105 enum hubp_3dlut_fl_mode mode; 106 enum hubp_3dlut_fl_format format; 107 uint16_t bias; 108 uint16_t scale; 109 struct dc_plane_address address; 110 enum hubp_3dlut_fl_addressing_mode addr_mode; 111 enum dc_cm2_gpu_mem_layout layout; 112 uint8_t protection_bits; 113 enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g; 114 enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b; 115 enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r; 116 }; 117 118 struct hubp { 119 const struct hubp_funcs *funcs; 120 struct dc_context *ctx; 121 struct dc_plane_address request_address; 122 int inst; 123 124 /* run time states */ 125 int opp_id; 126 int mpcc_id; 127 struct dc_cursor_attributes curs_attr; 128 struct dc_cursor_position curs_pos; 129 bool power_gated; 130 131 struct cursor_position_cache_hubp pos; 132 struct cursor_attribute_cache_hubp att; 133 struct cursor_rect cur_rect; 134 }; 135 136 struct surface_flip_registers { 137 uint32_t DCSURF_SURFACE_CONTROL; 138 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; 139 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; 140 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 141 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 142 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; 143 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; 144 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 145 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 146 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; 147 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; 148 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; 149 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; 150 bool tmz_surface; 151 bool immediate; 152 uint8_t vmid; 153 bool grph_stereo; 154 }; 155 156 struct hubp_funcs { 157 void (*hubp_setup)( 158 struct hubp *hubp, 159 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 160 struct _vcs_dpi_display_ttu_regs_st *ttu_regs, 161 struct _vcs_dpi_display_rq_regs_st *rq_regs, 162 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); 163 164 void (*hubp_setup2)( 165 struct hubp *hubp, 166 struct dml2_dchub_per_pipe_register_set *pipe_regs, 167 union dml2_global_sync_programming *pipe_global_sync, 168 struct dc_crtc_timing *timing); 169 170 void (*hubp_setup_interdependent)( 171 struct hubp *hubp, 172 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 173 struct _vcs_dpi_display_ttu_regs_st *ttu_regs); 174 175 void (*hubp_setup_interdependent2)( 176 struct hubp *hubp, 177 struct dml2_dchub_per_pipe_register_set *pipe_regs); 178 179 void (*dcc_control)(struct hubp *hubp, bool enable, 180 enum hubp_ind_block_size blk_size); 181 182 void (*hubp_reset)(struct hubp *hubp); 183 184 void (*mem_program_viewport)( 185 struct hubp *hubp, 186 const struct rect *viewport, 187 const struct rect *viewport_c); 188 189 bool (*hubp_program_surface_flip_and_addr)( 190 struct hubp *hubp, 191 const struct dc_plane_address *address, 192 bool flip_immediate); 193 194 void (*hubp_program_pte_vm)( 195 struct hubp *hubp, 196 enum surface_pixel_format format, 197 struct dc_tiling_info *tiling_info, 198 enum dc_rotation_angle rotation); 199 200 void (*hubp_set_vm_system_aperture_settings)( 201 struct hubp *hubp, 202 struct vm_system_aperture_param *apt); 203 204 void (*hubp_set_vm_context0_settings)( 205 struct hubp *hubp, 206 const struct vm_context0_param *vm0); 207 208 void (*hubp_program_surface_config)( 209 struct hubp *hubp, 210 enum surface_pixel_format format, 211 struct dc_tiling_info *tiling_info, 212 struct plane_size *plane_size, 213 enum dc_rotation_angle rotation, 214 struct dc_plane_dcc_param *dcc, 215 bool horizontal_mirror, 216 unsigned int compa_level); 217 218 bool (*hubp_is_flip_pending)(struct hubp *hubp); 219 220 void (*set_blank)(struct hubp *hubp, bool blank); 221 void (*set_blank_regs)(struct hubp *hubp, bool blank); 222 void (*phantom_hubp_post_enable)(struct hubp *hubp); 223 void (*set_hubp_blank_en)(struct hubp *hubp, bool blank); 224 225 void (*set_cursor_attributes)( 226 struct hubp *hubp, 227 const struct dc_cursor_attributes *attr); 228 229 void (*set_cursor_position)( 230 struct hubp *hubp, 231 const struct dc_cursor_position *pos, 232 const struct dc_cursor_mi_param *param); 233 234 void (*hubp_disconnect)(struct hubp *hubp); 235 236 void (*hubp_clk_cntl)(struct hubp *hubp, bool enable); 237 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst); 238 void (*hubp_read_state)(struct hubp *hubp); 239 void (*hubp_clear_underflow)(struct hubp *hubp); 240 void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp); 241 unsigned int (*hubp_get_underflow_status)(struct hubp *hubp); 242 void (*hubp_init)(struct hubp *hubp); 243 244 void (*dmdata_set_attributes)( 245 struct hubp *hubp, 246 const struct dc_dmdata_attributes *attr); 247 248 void (*dmdata_load)( 249 struct hubp *hubp, 250 uint32_t dmdata_sw_size, 251 const uint32_t *dmdata_sw_data); 252 bool (*dmdata_status_done)(struct hubp *hubp); 253 void (*hubp_enable_tripleBuffer)( 254 struct hubp *hubp, 255 bool enable); 256 257 bool (*hubp_is_triplebuffer_enabled)( 258 struct hubp *hubp); 259 260 void (*hubp_set_flip_control_surface_gsl)( 261 struct hubp *hubp, 262 bool enable); 263 264 void (*validate_dml_output)( 265 struct hubp *hubp, 266 struct dc_context *ctx, 267 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 268 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 269 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr); 270 void (*set_unbounded_requesting)( 271 struct hubp *hubp, 272 bool enable); 273 bool (*hubp_in_blank)(struct hubp *hubp); 274 void (*hubp_soft_reset)(struct hubp *hubp, bool reset); 275 276 void (*hubp_set_flip_int)(struct hubp *hubp); 277 278 void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow); 279 void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow); 280 void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor); 281 void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable); 282 void (*hubp_surface_update_lock)(struct hubp *hubp, 283 bool lock); 284 285 void (*program_extended_blank)(struct hubp *hubp, 286 unsigned int min_dst_y_next_start_optimized); 287 288 void (*hubp_wait_pipe_read_start)(struct hubp *hubp); 289 void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); 290 void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale); 291 void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp, 292 enum hubp_3dlut_fl_mode mode); 293 void (*hubp_program_3dlut_fl_format)(struct hubp *hubp, 294 enum hubp_3dlut_fl_format format); 295 void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp, 296 const struct dc_plane_address address); 297 void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group); 298 void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable); 299 void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); 300 void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width); 301 void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits); 302 void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp, 303 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, 304 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, 305 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); 306 int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); 307 void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); 308 void (*hubp_clear_tiling)(struct hubp *hubp); 309 uint32_t (*hubp_get_current_read_line)(struct hubp *hubp); 310 uint32_t (*hubp_get_det_config_error)(struct hubp *hubp); 311 }; 312 313 #endif 314