1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_DCHUBBUB_H__ 27 #define __DAL_DCHUBBUB_H__ 28 29 /** 30 * DOC: overview 31 * 32 * There is only one common DCHUBBUB. It contains the common request and return 33 * blocks for the Data Fabric Interface that are not clock/power gated. 34 */ 35 36 #include "dc/dc_hw_types.h" 37 38 enum dcc_control { 39 dcc_control__256_256_xxx, 40 dcc_control__128_128_xxx, 41 dcc_control__256_64_64, 42 dcc_control__256_128_128, 43 }; 44 45 enum segment_order { 46 segment_order__na, 47 segment_order__contiguous, 48 segment_order__non_contiguous, 49 }; 50 51 struct dcn_hubbub_wm_set { 52 uint32_t wm_set; 53 uint32_t data_urgent; 54 uint32_t pte_meta_urgent; 55 uint32_t sr_enter; 56 uint32_t sr_exit; 57 uint32_t dram_clk_change; 58 uint32_t usr_retrain; 59 uint32_t fclk_pstate_change; 60 uint32_t sr_enter_exit_Z8; 61 uint32_t sr_enter_Z8; 62 }; 63 64 struct dcn_hubbub_wm { 65 struct dcn_hubbub_wm_set sets[4]; 66 }; 67 68 enum dcn_hubbub_page_table_depth { 69 DCN_PAGE_TABLE_DEPTH_1_LEVEL, 70 DCN_PAGE_TABLE_DEPTH_2_LEVEL, 71 DCN_PAGE_TABLE_DEPTH_3_LEVEL, 72 DCN_PAGE_TABLE_DEPTH_4_LEVEL 73 }; 74 75 enum dcn_hubbub_page_table_block_size { 76 DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0, 77 DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4, 78 DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3 79 }; 80 81 struct dcn_hubbub_phys_addr_config { 82 struct { 83 uint64_t fb_top; 84 uint64_t fb_offset; 85 uint64_t fb_base; 86 uint64_t agp_top; 87 uint64_t agp_bot; 88 uint64_t agp_base; 89 } system_aperture; 90 91 struct { 92 uint64_t page_table_start_addr; 93 uint64_t page_table_end_addr; 94 uint64_t page_table_base_addr; 95 } gart_config; 96 97 uint64_t page_table_default_page_addr; 98 }; 99 100 struct dcn_hubbub_virt_addr_config { 101 uint64_t page_table_start_addr; 102 uint64_t page_table_end_addr; 103 enum dcn_hubbub_page_table_block_size page_table_block_size; 104 enum dcn_hubbub_page_table_depth page_table_depth; 105 uint64_t page_table_base_addr; 106 }; 107 108 struct hubbub_addr_config { 109 struct dcn_hubbub_phys_addr_config pa_config; 110 struct dcn_hubbub_virt_addr_config va_config; 111 struct { 112 uint64_t aperture_check_fault; 113 uint64_t generic_fault; 114 } default_addrs; 115 }; 116 117 struct dcn_hubbub_state { 118 uint32_t vm_fault_addr_msb; 119 uint32_t vm_fault_addr_lsb; 120 uint32_t vm_error_status; 121 uint32_t vm_error_vmid; 122 uint32_t vm_error_pipe; 123 uint32_t vm_error_mode; 124 uint32_t test_debug_data; 125 uint32_t watermark_change_cntl; 126 uint32_t dram_state_cntl; 127 }; 128 129 struct hubbub_funcs { 130 void (*update_dchub)( 131 struct hubbub *hubbub, 132 struct dchub_init_data *dh_data); 133 134 int (*init_dchub_sys_ctx)( 135 struct hubbub *hubbub, 136 struct dcn_hubbub_phys_addr_config *pa_config); 137 void (*init_vm_ctx)( 138 struct hubbub *hubbub, 139 struct dcn_hubbub_virt_addr_config *va_config, 140 int vmid); 141 142 bool (*get_dcc_compression_cap)(struct hubbub *hubbub, 143 const struct dc_dcc_surface_param *input, 144 struct dc_surface_dcc_cap *output); 145 146 bool (*dcc_support_swizzle)( 147 enum swizzle_mode_values swizzle, 148 unsigned int bytes_per_element, 149 enum segment_order *segment_order_horz, 150 enum segment_order *segment_order_vert); 151 152 bool (*dcc_support_swizzle_addr3)( 153 enum swizzle_mode_addr3_values swizzle, 154 unsigned int plane_pitch, 155 unsigned int bytes_per_element, 156 enum segment_order *segment_order_horz, 157 enum segment_order *segment_order_vert); 158 159 bool (*dcc_support_pixel_format_plane0_plane1)( 160 enum surface_pixel_format format, 161 unsigned int *plane0_bpe, 162 unsigned int *plane1_bpe); 163 bool (*dcc_support_pixel_format)( 164 enum surface_pixel_format format, 165 unsigned int *bytes_per_element); 166 167 void (*wm_read_state)(struct hubbub *hubbub, 168 struct dcn_hubbub_wm *wm); 169 170 void (*get_dchub_ref_freq)(struct hubbub *hubbub, 171 unsigned int dccg_ref_freq_inKhz, 172 unsigned int *dchub_ref_freq_inKhz); 173 174 bool (*program_watermarks)( 175 struct hubbub *hubbub, 176 union dcn_watermark_set *watermarks, 177 unsigned int refclk_mhz, 178 bool safe_to_lower); 179 180 bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub); 181 void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow); 182 183 bool (*verify_allow_pstate_change_high)(struct hubbub *hubbub); 184 185 void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub); 186 187 void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub); 188 189 void (*hubbub_read_state)(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state); 190 191 void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow); 192 193 void (*init_watermarks)(struct hubbub *hubbub); 194 195 /** 196 * @program_det_size: 197 * 198 * DE-Tile buffers (DET) is a memory that is used to convert the tiled 199 * data into linear, which the rest of the display can use to generate 200 * the graphics output. One of the main features of this component is 201 * that each pipe has a configurable DET buffer which means that when a 202 * pipe is not enabled, the device can assign the memory to other 203 * enabled pipes to try to be more efficient. 204 * 205 * DET logic is handled by dchubbub. Some ASICs provide a feature named 206 * Configurable Return Buffer (CRB) segments which can be allocated to 207 * compressed or detiled buffers. 208 */ 209 void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte); 210 void (*wait_for_det_apply)(struct hubbub *hubbub, int hubp_inst); 211 void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase); 212 void (*init_crb)(struct hubbub *hubbub); 213 void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow); 214 void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel); 215 void (*dchubbub_init)(struct hubbub *hubbub); 216 void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use); 217 void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); 218 void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); 219 }; 220 221 struct hubbub { 222 const struct hubbub_funcs *funcs; 223 struct dc_context *ctx; 224 bool riommu_active; 225 }; 226 227 #endif 228