1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_DCHUBBUB_H__ 27 #define __DAL_DCHUBBUB_H__ 28 29 /** 30 * DOC: overview 31 * 32 * There is only one common DCHUBBUB. It contains the common request and return 33 * blocks for the Data Fabric Interface that are not clock/power gated. 34 */ 35 36 #include "dc/dc_hw_types.h" 37 38 enum dcc_control { 39 dcc_control__256_256_xxx, 40 dcc_control__128_128_xxx, 41 dcc_control__256_64_64, 42 dcc_control__256_128_128, 43 }; 44 45 enum segment_order { 46 segment_order__na, 47 segment_order__contiguous, 48 segment_order__non_contiguous, 49 }; 50 51 struct dcn_hubbub_wm_set { 52 uint32_t wm_set; 53 uint32_t data_urgent; 54 uint32_t pte_meta_urgent; 55 uint32_t sr_enter; 56 uint32_t sr_exit; 57 uint32_t dram_clk_change; 58 uint32_t usr_retrain; 59 uint32_t fclk_pstate_change; 60 uint32_t sr_enter_exit_Z8; 61 uint32_t sr_enter_Z8; 62 }; 63 64 struct dcn_hubbub_wm { 65 struct dcn_hubbub_wm_set sets[4]; 66 }; 67 68 enum dcn_hubbub_page_table_depth { 69 DCN_PAGE_TABLE_DEPTH_1_LEVEL, 70 DCN_PAGE_TABLE_DEPTH_2_LEVEL, 71 DCN_PAGE_TABLE_DEPTH_3_LEVEL, 72 DCN_PAGE_TABLE_DEPTH_4_LEVEL 73 }; 74 75 enum dcn_hubbub_page_table_block_size { 76 DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0, 77 DCN_PAGE_TABLE_BLOCK_SIZE_8KB = 1, 78 DCN_PAGE_TABLE_BLOCK_SIZE_16KB = 2, 79 DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3, 80 DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4, 81 DCN_PAGE_TABLE_BLOCK_SIZE_128KB = 5, 82 DCN_PAGE_TABLE_BLOCK_SIZE_256KB = 6, 83 DCN_PAGE_TABLE_BLOCK_SIZE_512KB = 7, 84 DCN_PAGE_TABLE_BLOCK_SIZE_1024KB = 8, 85 DCN_PAGE_TABLE_BLOCK_SIZE_2048KB = 9 86 }; 87 88 struct dcn_hubbub_phys_addr_config { 89 struct { 90 uint64_t fb_top; 91 uint64_t fb_offset; 92 uint64_t fb_base; 93 uint64_t agp_top; 94 uint64_t agp_bot; 95 uint64_t agp_base; 96 } system_aperture; 97 98 struct { 99 uint64_t page_table_start_addr; 100 uint64_t page_table_end_addr; 101 uint64_t page_table_base_addr; 102 } gart_config; 103 104 uint64_t page_table_default_page_addr; 105 }; 106 107 struct dcn_hubbub_virt_addr_config { 108 uint64_t page_table_start_addr; 109 uint64_t page_table_end_addr; 110 enum dcn_hubbub_page_table_block_size page_table_block_size; 111 enum dcn_hubbub_page_table_depth page_table_depth; 112 uint64_t page_table_base_addr; 113 }; 114 115 struct hubbub_addr_config { 116 struct dcn_hubbub_phys_addr_config pa_config; 117 struct dcn_hubbub_virt_addr_config va_config; 118 struct { 119 uint64_t aperture_check_fault; 120 uint64_t generic_fault; 121 } default_addrs; 122 }; 123 124 struct dcn_hubbub_state { 125 uint32_t vm_fault_addr_msb; 126 uint32_t vm_fault_addr_lsb; 127 uint32_t vm_error_status; 128 uint32_t vm_error_vmid; 129 uint32_t vm_error_pipe; 130 uint32_t vm_error_mode; 131 uint32_t test_debug_data; 132 uint32_t watermark_change_cntl; 133 uint32_t dram_state_cntl; 134 }; 135 136 struct hubbub_funcs { 137 void (*update_dchub)( 138 struct hubbub *hubbub, 139 struct dchub_init_data *dh_data); 140 141 int (*init_dchub_sys_ctx)( 142 struct hubbub *hubbub, 143 struct dcn_hubbub_phys_addr_config *pa_config); 144 void (*init_vm_ctx)( 145 struct hubbub *hubbub, 146 struct dcn_hubbub_virt_addr_config *va_config, 147 int vmid); 148 149 bool (*get_dcc_compression_cap)(struct hubbub *hubbub, 150 const struct dc_dcc_surface_param *input, 151 struct dc_surface_dcc_cap *output); 152 153 bool (*dcc_support_swizzle)( 154 enum swizzle_mode_values swizzle, 155 unsigned int bytes_per_element, 156 enum segment_order *segment_order_horz, 157 enum segment_order *segment_order_vert); 158 159 bool (*dcc_support_swizzle_addr3)( 160 enum swizzle_mode_addr3_values swizzle, 161 unsigned int plane_pitch, 162 unsigned int bytes_per_element, 163 enum segment_order *segment_order_horz, 164 enum segment_order *segment_order_vert); 165 166 bool (*dcc_support_pixel_format_plane0_plane1)( 167 enum surface_pixel_format format, 168 unsigned int *plane0_bpe, 169 unsigned int *plane1_bpe); 170 bool (*dcc_support_pixel_format)( 171 enum surface_pixel_format format, 172 unsigned int *bytes_per_element); 173 174 void (*wm_read_state)(struct hubbub *hubbub, 175 struct dcn_hubbub_wm *wm); 176 177 void (*get_dchub_ref_freq)(struct hubbub *hubbub, 178 unsigned int dccg_ref_freq_inKhz, 179 unsigned int *dchub_ref_freq_inKhz); 180 181 bool (*program_watermarks)( 182 struct hubbub *hubbub, 183 union dcn_watermark_set *watermarks, 184 unsigned int refclk_mhz, 185 bool safe_to_lower); 186 187 bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub); 188 void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow); 189 190 bool (*verify_allow_pstate_change_high)(struct hubbub *hubbub); 191 192 void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub); 193 194 void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub); 195 196 void (*hubbub_read_state)(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state); 197 198 void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow); 199 200 void (*init_watermarks)(struct hubbub *hubbub); 201 202 /** 203 * @program_det_size: 204 * 205 * DE-Tile buffers (DET) is a memory that is used to convert the tiled 206 * data into linear, which the rest of the display can use to generate 207 * the graphics output. One of the main features of this component is 208 * that each pipe has a configurable DET buffer which means that when a 209 * pipe is not enabled, the device can assign the memory to other 210 * enabled pipes to try to be more efficient. 211 * 212 * DET logic is handled by dchubbub. Some ASICs provide a feature named 213 * Configurable Return Buffer (CRB) segments which can be allocated to 214 * compressed or detiled buffers. 215 */ 216 void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte); 217 void (*wait_for_det_apply)(struct hubbub *hubbub, int hubp_inst); 218 void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase); 219 void (*init_crb)(struct hubbub *hubbub); 220 void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow); 221 void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel); 222 void (*dchubbub_init)(struct hubbub *hubbub); 223 void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use); 224 void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); 225 void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); 226 }; 227 228 struct hubbub { 229 const struct hubbub_funcs *funcs; 230 struct dc_context *ctx; 231 bool riommu_active; 232 }; 233 234 #endif 235