1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_DCHUBBUB_H__ 27 #define __DAL_DCHUBBUB_H__ 28 29 /** 30 * DOC: overview 31 * 32 * There is only one common DCHUBBUB. It contains the common request and return 33 * blocks for the Data Fabric Interface that are not clock/power gated. 34 */ 35 36 #include "dc/dc_hw_types.h" 37 38 enum dcc_control { 39 dcc_control__256_256_xxx, 40 dcc_control__128_128_xxx, 41 dcc_control__256_64_64, 42 dcc_control__256_128_128, 43 dcc_control__256_256, 44 dcc_control__256_128, 45 dcc_control__256_64, 46 47 }; 48 49 enum segment_order { 50 segment_order__na, 51 segment_order__contiguous, 52 segment_order__non_contiguous, 53 }; 54 55 struct dcn_hubbub_wm_set { 56 uint32_t wm_set; 57 uint32_t data_urgent; 58 uint32_t pte_meta_urgent; 59 uint32_t sr_enter; 60 uint32_t sr_exit; 61 uint32_t dram_clk_change; 62 uint32_t usr_retrain; 63 uint32_t fclk_pstate_change; 64 uint32_t sr_enter_exit_Z8; 65 uint32_t sr_enter_Z8; 66 }; 67 68 struct dcn_hubbub_wm { 69 struct dcn_hubbub_wm_set sets[4]; 70 }; 71 72 enum dcn_hubbub_page_table_depth { 73 DCN_PAGE_TABLE_DEPTH_1_LEVEL, 74 DCN_PAGE_TABLE_DEPTH_2_LEVEL, 75 DCN_PAGE_TABLE_DEPTH_3_LEVEL, 76 DCN_PAGE_TABLE_DEPTH_4_LEVEL 77 }; 78 79 enum dcn_hubbub_page_table_block_size { 80 DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0, 81 DCN_PAGE_TABLE_BLOCK_SIZE_8KB = 1, 82 DCN_PAGE_TABLE_BLOCK_SIZE_16KB = 2, 83 DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3, 84 DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4, 85 DCN_PAGE_TABLE_BLOCK_SIZE_128KB = 5, 86 DCN_PAGE_TABLE_BLOCK_SIZE_256KB = 6, 87 DCN_PAGE_TABLE_BLOCK_SIZE_512KB = 7, 88 DCN_PAGE_TABLE_BLOCK_SIZE_1024KB = 8, 89 DCN_PAGE_TABLE_BLOCK_SIZE_2048KB = 9 90 }; 91 92 struct dcn_hubbub_phys_addr_config { 93 struct { 94 uint64_t fb_top; 95 uint64_t fb_offset; 96 uint64_t fb_base; 97 uint64_t agp_top; 98 uint64_t agp_bot; 99 uint64_t agp_base; 100 } system_aperture; 101 102 struct { 103 uint64_t page_table_start_addr; 104 uint64_t page_table_end_addr; 105 uint64_t page_table_base_addr; 106 } gart_config; 107 108 uint64_t page_table_default_page_addr; 109 }; 110 111 struct dcn_hubbub_virt_addr_config { 112 uint64_t page_table_start_addr; 113 uint64_t page_table_end_addr; 114 enum dcn_hubbub_page_table_block_size page_table_block_size; 115 enum dcn_hubbub_page_table_depth page_table_depth; 116 uint64_t page_table_base_addr; 117 }; 118 119 struct hubbub_addr_config { 120 struct dcn_hubbub_phys_addr_config pa_config; 121 struct dcn_hubbub_virt_addr_config va_config; 122 struct { 123 uint64_t aperture_check_fault; 124 uint64_t generic_fault; 125 } default_addrs; 126 }; 127 128 struct dcn_hubbub_state { 129 uint32_t vm_fault_addr_msb; 130 uint32_t vm_fault_addr_lsb; 131 uint32_t vm_error_status; 132 uint32_t vm_error_vmid; 133 uint32_t vm_error_pipe; 134 uint32_t vm_error_mode; 135 uint32_t test_debug_data; 136 uint32_t watermark_change_cntl; 137 uint32_t dram_state_cntl; 138 }; 139 140 struct hubbub_system_latencies { 141 uint32_t max_latency_ns; 142 uint32_t avg_latency_ns; 143 uint32_t min_latency_ns; 144 }; 145 146 struct hubbub_urgent_latency_params { 147 uint32_t refclk_mhz; 148 uint32_t t_win_ns; 149 uint32_t bandwidth_mbps; 150 uint32_t bw_factor_x1000; 151 }; 152 153 struct hubbub_funcs { 154 void (*update_dchub)( 155 struct hubbub *hubbub, 156 struct dchub_init_data *dh_data); 157 158 int (*init_dchub_sys_ctx)( 159 struct hubbub *hubbub, 160 struct dcn_hubbub_phys_addr_config *pa_config); 161 void (*init_vm_ctx)( 162 struct hubbub *hubbub, 163 struct dcn_hubbub_virt_addr_config *va_config, 164 int vmid); 165 166 bool (*get_dcc_compression_cap)(struct hubbub *hubbub, 167 const struct dc_dcc_surface_param *input, 168 struct dc_surface_dcc_cap *output); 169 170 bool (*dcc_support_swizzle)( 171 enum swizzle_mode_values swizzle, 172 unsigned int bytes_per_element, 173 enum segment_order *segment_order_horz, 174 enum segment_order *segment_order_vert); 175 176 bool (*dcc_support_swizzle_addr3)( 177 enum swizzle_mode_addr3_values swizzle, 178 unsigned int plane_pitch, 179 unsigned int bytes_per_element, 180 enum segment_order *segment_order_horz, 181 enum segment_order *segment_order_vert); 182 183 bool (*dcc_support_pixel_format_plane0_plane1)( 184 enum surface_pixel_format format, 185 unsigned int *plane0_bpe, 186 unsigned int *plane1_bpe); 187 bool (*dcc_support_pixel_format)( 188 enum surface_pixel_format format, 189 unsigned int *bytes_per_element); 190 191 void (*wm_read_state)(struct hubbub *hubbub, 192 struct dcn_hubbub_wm *wm); 193 194 void (*get_dchub_ref_freq)(struct hubbub *hubbub, 195 unsigned int dccg_ref_freq_inKhz, 196 unsigned int *dchub_ref_freq_inKhz); 197 198 bool (*program_watermarks)( 199 struct hubbub *hubbub, 200 union dcn_watermark_set *watermarks, 201 unsigned int refclk_mhz, 202 bool safe_to_lower); 203 204 bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub); 205 void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow); 206 207 bool (*verify_allow_pstate_change_high)(struct hubbub *hubbub); 208 209 void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub); 210 211 void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub); 212 213 void (*hubbub_read_state)(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state); 214 215 void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow); 216 217 void (*init_watermarks)(struct hubbub *hubbub); 218 219 /** 220 * @program_det_size: 221 * 222 * DE-Tile buffers (DET) is a memory that is used to convert the tiled 223 * data into linear, which the rest of the display can use to generate 224 * the graphics output. One of the main features of this component is 225 * that each pipe has a configurable DET buffer which means that when a 226 * pipe is not enabled, the device can assign the memory to other 227 * enabled pipes to try to be more efficient. 228 * 229 * DET logic is handled by dchubbub. Some ASICs provide a feature named 230 * Configurable Return Buffer (CRB) segments which can be allocated to 231 * compressed or detiled buffers. 232 */ 233 void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte); 234 void (*wait_for_det_apply)(struct hubbub *hubbub, int hubp_inst); 235 void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase); 236 void (*init_crb)(struct hubbub *hubbub); 237 void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow); 238 void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel); 239 void (*dchubbub_init)(struct hubbub *hubbub); 240 void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use); 241 void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); 242 void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); 243 void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); 244 bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); 245 void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes); 246 uint32_t (*compbuf_config_error)(struct hubbub *hubbub); 247 struct hubbub_perfmon_funcs{ 248 void (*start_system_latency_measurement)(struct hubbub *hubbub); 249 void (*get_system_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, struct hubbub_system_latencies *latencies); 250 void (*start_in_order_bandwidth_measurement)(struct hubbub *hubbub); 251 void (*get_in_order_bandwidth_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *bandwidth_mbps); 252 void (*start_urgent_ramp_latency_measurement)(struct hubbub *hubbub, const struct hubbub_urgent_latency_params *params); 253 void (*get_urgent_ramp_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *latency_ns); 254 void (*reset)(struct hubbub *hubbub); 255 } perfmon; 256 }; 257 258 struct hubbub { 259 const struct hubbub_funcs *funcs; 260 struct dc_context *ctx; 261 bool riommu_active; 262 }; 263 264 #endif 265