1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /** 27 * Bandwidth and Watermark calculations interface. 28 * (Refer to "DCEx_mode_support.xlsm" from Perforce.) 29 */ 30 #ifndef __DCN_CALCS_H__ 31 #define __DCN_CALCS_H__ 32 33 #include "bw_fixed.h" 34 #include "display_clock.h" 35 #include "../dml/display_mode_lib.h" 36 37 struct core_dc; 38 struct validate_context; 39 40 /******************************************************************************* 41 * DCN data structures. 42 ******************************************************************************/ 43 44 #define number_of_planes 6 45 #define number_of_planes_minus_one 5 46 #define number_of_states 4 47 #define number_of_states_plus_one 5 48 49 #define ddr4_dram_width 64 50 #define ddr4_dram_factor_single_Channel 16 51 enum dcn_bw_defs { 52 dcn_bw_v_min0p65, 53 dcn_bw_v_mid0p72, 54 dcn_bw_v_nom0p8, 55 dcn_bw_v_max0p9, 56 dcn_bw_v_max0p91, 57 dcn_bw_no_support = 5, 58 dcn_bw_yes, 59 dcn_bw_hor, 60 dcn_bw_vert, 61 dcn_bw_override, 62 dcn_bw_rgb_sub_64, 63 dcn_bw_rgb_sub_32, 64 dcn_bw_rgb_sub_16, 65 dcn_bw_no, 66 dcn_bw_sw_linear, 67 dcn_bw_sw_4_kb_d, 68 dcn_bw_sw_4_kb_d_x, 69 dcn_bw_sw_64_kb_d, 70 dcn_bw_sw_64_kb_d_t, 71 dcn_bw_sw_64_kb_d_x, 72 dcn_bw_sw_var_d, 73 dcn_bw_sw_var_d_x, 74 dcn_bw_yuv420_sub_8, 75 dcn_bw_sw_4_kb_s, 76 dcn_bw_sw_4_kb_s_x, 77 dcn_bw_sw_64_kb_s, 78 dcn_bw_sw_64_kb_s_t, 79 dcn_bw_sw_64_kb_s_x, 80 dcn_bw_writeback, 81 dcn_bw_444, 82 dcn_bw_dp, 83 dcn_bw_420, 84 dcn_bw_hdmi, 85 dcn_bw_sw_var_s, 86 dcn_bw_sw_var_s_x, 87 dcn_bw_yuv420_sub_10, 88 dcn_bw_supported_in_v_active, 89 dcn_bw_supported_in_v_blank, 90 dcn_bw_not_supported, 91 dcn_bw_na, 92 }; 93 94 /*bounding box parameters*/ 95 /*mode parameters*/ 96 /*system configuration*/ 97 /* display configuration*/ 98 struct dcn_bw_internal_vars { 99 float voltage[number_of_states_plus_one + 1]; 100 float max_dispclk[number_of_states_plus_one + 1]; 101 float max_dppclk[number_of_states_plus_one + 1]; 102 float dcfclk_per_state[number_of_states_plus_one + 1]; 103 float phyclk_per_state[number_of_states_plus_one + 1]; 104 float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1]; 105 float sr_exit_time; 106 float sr_enter_plus_exit_time; 107 float dram_clock_change_latency; 108 float urgent_latency; 109 float write_back_latency; 110 float percent_of_ideal_drambw_received_after_urg_latency; 111 float dcfclkv_max0p9; 112 float dcfclkv_nom0p8; 113 float dcfclkv_mid0p72; 114 float dcfclkv_min0p65; 115 float max_dispclk_vmax0p9; 116 float max_dppclk_vmax0p9; 117 float max_dispclk_vnom0p8; 118 float max_dppclk_vnom0p8; 119 float max_dispclk_vmid0p72; 120 float max_dppclk_vmid0p72; 121 float max_dispclk_vmin0p65; 122 float max_dppclk_vmin0p65; 123 float socclk; 124 float fabric_and_dram_bandwidth_vmax0p9; 125 float fabric_and_dram_bandwidth_vnom0p8; 126 float fabric_and_dram_bandwidth_vmid0p72; 127 float fabric_and_dram_bandwidth_vmin0p65; 128 float round_trip_ping_latency_cycles; 129 float urgent_out_of_order_return_per_channel; 130 float number_of_channels; 131 float vmm_page_size; 132 float return_bus_width; 133 float rob_buffer_size_in_kbyte; 134 float det_buffer_size_in_kbyte; 135 float dpp_output_buffer_pixels; 136 float opp_output_buffer_lines; 137 float pixel_chunk_size_in_kbyte; 138 float pte_chunk_size; 139 float meta_chunk_size; 140 float writeback_chunk_size; 141 enum dcn_bw_defs odm_capability; 142 enum dcn_bw_defs dsc_capability; 143 float line_buffer_size; 144 enum dcn_bw_defs is_line_buffer_bpp_fixed; 145 float line_buffer_fixed_bpp; 146 float max_line_buffer_lines; 147 float writeback_luma_buffer_size; 148 float writeback_chroma_buffer_size; 149 float max_num_dpp; 150 float max_num_writeback; 151 float max_dchub_topscl_throughput; 152 float max_pscl_tolb_throughput; 153 float max_lb_tovscl_throughput; 154 float max_vscl_tohscl_throughput; 155 float max_hscl_ratio; 156 float max_vscl_ratio; 157 float max_hscl_taps; 158 float max_vscl_taps; 159 float under_scan_factor; 160 float phyclkv_max0p9; 161 float phyclkv_nom0p8; 162 float phyclkv_mid0p72; 163 float phyclkv_min0p65; 164 float pte_buffer_size_in_requests; 165 float dispclk_ramping_margin; 166 float downspreading; 167 float max_inter_dcn_tile_repeaters; 168 enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 169 enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed; 170 int mode; 171 float viewport_width[number_of_planes_minus_one + 1]; 172 float htotal[number_of_planes_minus_one + 1]; 173 float vtotal[number_of_planes_minus_one + 1]; 174 float v_sync_plus_back_porch[number_of_planes_minus_one + 1]; 175 float vactive[number_of_planes_minus_one + 1]; 176 float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/ 177 float viewport_height[number_of_planes_minus_one + 1]; 178 enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1]; 179 float dcc_rate[number_of_planes_minus_one + 1]; 180 enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1]; 181 float lb_bit_per_pixel[number_of_planes_minus_one + 1]; 182 enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1]; 183 enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1]; 184 enum dcn_bw_defs output_format[number_of_planes_minus_one + 1]; 185 enum dcn_bw_defs output[number_of_planes_minus_one + 1]; 186 float scaler_rec_out_width[number_of_planes_minus_one + 1]; 187 float scaler_recout_height[number_of_planes_minus_one + 1]; 188 float underscan_output[number_of_planes_minus_one + 1]; 189 float interlace_output[number_of_planes_minus_one + 1]; 190 float override_hta_ps[number_of_planes_minus_one + 1]; 191 float override_vta_ps[number_of_planes_minus_one + 1]; 192 float override_hta_pschroma[number_of_planes_minus_one + 1]; 193 float override_vta_pschroma[number_of_planes_minus_one + 1]; 194 float urgent_latency_support_us[number_of_planes_minus_one + 1]; 195 float h_ratio[number_of_planes_minus_one + 1]; 196 float v_ratio[number_of_planes_minus_one + 1]; 197 float htaps[number_of_planes_minus_one + 1]; 198 float vtaps[number_of_planes_minus_one + 1]; 199 float hta_pschroma[number_of_planes_minus_one + 1]; 200 float vta_pschroma[number_of_planes_minus_one + 1]; 201 enum dcn_bw_defs pte_enable; 202 enum dcn_bw_defs synchronized_vblank; 203 enum dcn_bw_defs ta_pscalculation; 204 int voltage_override_level; 205 int number_of_active_planes; 206 int voltage_level; 207 enum dcn_bw_defs immediate_flip_supported; 208 float dcfclk; 209 float max_phyclk; 210 float fabric_and_dram_bandwidth; 211 float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1]; 212 enum dcn_bw_defs dispclk_dppclk_support_per_ratio[1 + 1]; 213 float required_dispclk_per_ratio[1 + 1]; 214 enum dcn_bw_defs error_message[1 + 1]; 215 int dispclk_dppclk_ratio; 216 float dpp_per_plane[number_of_planes_minus_one + 1]; 217 float det_buffer_size_y[number_of_planes_minus_one + 1]; 218 float det_buffer_size_c[number_of_planes_minus_one + 1]; 219 float swath_height_y[number_of_planes_minus_one + 1]; 220 float swath_height_c[number_of_planes_minus_one + 1]; 221 enum dcn_bw_defs final_error_message; 222 float frequency; 223 float header_line; 224 float header; 225 enum dcn_bw_defs voltage_override; 226 enum dcn_bw_defs allow_different_hratio_vratio; 227 float acceptable_quality_hta_ps; 228 float acceptable_quality_vta_ps; 229 float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 230 float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 231 float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 232 float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 233 float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 234 float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 235 float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 236 float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 237 float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 238 float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 239 float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 240 enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 241 enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 242 enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 243 enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 244 float required_dispclk[number_of_states_plus_one + 1][1 + 1]; 245 enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1]; 246 enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1]; 247 float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1]; 248 float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1]; 249 enum dcn_bw_defs urgent_latency_support[number_of_states_plus_one + 1][1 + 1]; 250 enum dcn_bw_defs mode_support_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 251 enum dcn_bw_defs mode_support_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 252 float return_bw_per_state[number_of_states_plus_one + 1]; 253 enum dcn_bw_defs dio_support[number_of_states_plus_one + 1]; 254 float urgent_round_trip_and_out_of_order_latency_per_state[number_of_states_plus_one + 1]; 255 enum dcn_bw_defs rob_support[number_of_states_plus_one + 1]; 256 enum dcn_bw_defs bandwidth_support[number_of_states_plus_one + 1]; 257 float prefetch_bw[number_of_planes_minus_one + 1]; 258 float meta_pte_bytes_per_frame[number_of_planes_minus_one + 1]; 259 float meta_row_bytes[number_of_planes_minus_one + 1]; 260 float dpte_bytes_per_row[number_of_planes_minus_one + 1]; 261 float prefetch_lines_y[number_of_planes_minus_one + 1]; 262 float prefetch_lines_c[number_of_planes_minus_one + 1]; 263 float max_num_sw_y[number_of_planes_minus_one + 1]; 264 float max_num_sw_c[number_of_planes_minus_one + 1]; 265 float line_times_for_prefetch[number_of_planes_minus_one + 1]; 266 float lines_for_meta_pte_with_immediate_flip[number_of_planes_minus_one + 1]; 267 float lines_for_meta_pte_without_immediate_flip[number_of_planes_minus_one + 1]; 268 float lines_for_meta_and_dpte_row_with_immediate_flip[number_of_planes_minus_one + 1]; 269 float lines_for_meta_and_dpte_row_without_immediate_flip[number_of_planes_minus_one + 1]; 270 float min_dppclk_using_single_dpp[number_of_planes_minus_one + 1]; 271 float swath_width_ysingle_dpp[number_of_planes_minus_one + 1]; 272 float byte_per_pixel_in_dety[number_of_planes_minus_one + 1]; 273 float byte_per_pixel_in_detc[number_of_planes_minus_one + 1]; 274 float number_of_dpp_required_for_det_and_lb_size[number_of_planes_minus_one + 1]; 275 float required_phyclk[number_of_planes_minus_one + 1]; 276 float read256_block_height_y[number_of_planes_minus_one + 1]; 277 float read256_block_width_y[number_of_planes_minus_one + 1]; 278 float read256_block_height_c[number_of_planes_minus_one + 1]; 279 float read256_block_width_c[number_of_planes_minus_one + 1]; 280 float max_swath_height_y[number_of_planes_minus_one + 1]; 281 float max_swath_height_c[number_of_planes_minus_one + 1]; 282 float min_swath_height_y[number_of_planes_minus_one + 1]; 283 float min_swath_height_c[number_of_planes_minus_one + 1]; 284 float read_bandwidth[number_of_planes_minus_one + 1]; 285 float write_bandwidth[number_of_planes_minus_one + 1]; 286 float pscl_factor[number_of_planes_minus_one + 1]; 287 float pscl_factor_chroma[number_of_planes_minus_one + 1]; 288 enum dcn_bw_defs scale_ratio_support; 289 enum dcn_bw_defs source_format_pixel_and_scan_support; 290 float total_read_bandwidth_consumed_gbyte_per_second; 291 float total_write_bandwidth_consumed_gbyte_per_second; 292 float total_bandwidth_consumed_gbyte_per_second; 293 enum dcn_bw_defs dcc_enabled_in_any_plane; 294 float return_bw_todcn_per_state; 295 float critical_point; 296 enum dcn_bw_defs writeback_latency_support; 297 float required_output_bw; 298 float total_number_of_active_writeback; 299 enum dcn_bw_defs total_available_writeback_support; 300 float maximum_swath_width; 301 float number_of_dpp_required_for_det_size; 302 float number_of_dpp_required_for_lb_size; 303 float min_dispclk_using_single_dpp; 304 float min_dispclk_using_dual_dpp; 305 enum dcn_bw_defs viewport_size_support; 306 float swath_width_granularity_y; 307 float rounded_up_max_swath_size_bytes_y; 308 float swath_width_granularity_c; 309 float rounded_up_max_swath_size_bytes_c; 310 float lines_in_det_luma; 311 float lines_in_det_chroma; 312 float effective_lb_latency_hiding_source_lines_luma; 313 float effective_lb_latency_hiding_source_lines_chroma; 314 float effective_detlb_lines_luma; 315 float effective_detlb_lines_chroma; 316 float projected_dcfclk_deep_sleep; 317 float meta_req_height_y; 318 float meta_req_width_y; 319 float meta_surface_width_y; 320 float meta_surface_height_y; 321 float meta_pte_bytes_per_frame_y; 322 float meta_row_bytes_y; 323 float macro_tile_block_size_bytes_y; 324 float macro_tile_block_height_y; 325 float data_pte_req_height_y; 326 float data_pte_req_width_y; 327 float dpte_bytes_per_row_y; 328 float meta_req_height_c; 329 float meta_req_width_c; 330 float meta_surface_width_c; 331 float meta_surface_height_c; 332 float meta_pte_bytes_per_frame_c; 333 float meta_row_bytes_c; 334 float macro_tile_block_size_bytes_c; 335 float macro_tile_block_height_c; 336 float macro_tile_block_width_c; 337 float data_pte_req_height_c; 338 float data_pte_req_width_c; 339 float dpte_bytes_per_row_c; 340 float v_init_y; 341 float max_partial_sw_y; 342 float v_init_c; 343 float max_partial_sw_c; 344 float dst_x_after_scaler; 345 float dst_y_after_scaler; 346 float time_calc; 347 float v_update_offset[number_of_planes_minus_one + 1]; 348 float total_repeater_delay; 349 float v_update_width[number_of_planes_minus_one + 1]; 350 float v_ready_offset[number_of_planes_minus_one + 1]; 351 float time_setup; 352 float extra_latency; 353 float maximum_vstartup; 354 float bw_available_for_immediate_flip; 355 float total_immediate_flip_bytes[number_of_planes_minus_one + 1]; 356 float time_for_meta_pte_with_immediate_flip; 357 float time_for_meta_pte_without_immediate_flip; 358 float time_for_meta_and_dpte_row_with_immediate_flip; 359 float time_for_meta_and_dpte_row_without_immediate_flip; 360 float line_times_to_request_prefetch_pixel_data_with_immediate_flip; 361 float line_times_to_request_prefetch_pixel_data_without_immediate_flip; 362 float maximum_read_bandwidth_with_prefetch_with_immediate_flip; 363 float maximum_read_bandwidth_with_prefetch_without_immediate_flip; 364 float voltage_level_with_immediate_flip; 365 float voltage_level_without_immediate_flip; 366 float total_number_of_active_dpp_per_ratio[1 + 1]; 367 float byte_per_pix_dety; 368 float byte_per_pix_detc; 369 float read256_bytes_block_height_y; 370 float read256_bytes_block_width_y; 371 float read256_bytes_block_height_c; 372 float read256_bytes_block_width_c; 373 float maximum_swath_height_y; 374 float maximum_swath_height_c; 375 float minimum_swath_height_y; 376 float minimum_swath_height_c; 377 float swath_width; 378 float prefetch_bandwidth[number_of_planes_minus_one + 1]; 379 float v_init_pre_fill_y[number_of_planes_minus_one + 1]; 380 float v_init_pre_fill_c[number_of_planes_minus_one + 1]; 381 float max_num_swath_y[number_of_planes_minus_one + 1]; 382 float max_num_swath_c[number_of_planes_minus_one + 1]; 383 float prefill_y[number_of_planes_minus_one + 1]; 384 float prefill_c[number_of_planes_minus_one + 1]; 385 float v_startup[number_of_planes_minus_one + 1]; 386 enum dcn_bw_defs allow_dram_clock_change_during_vblank[number_of_planes_minus_one + 1]; 387 float allow_dram_self_refresh_during_vblank[number_of_planes_minus_one + 1]; 388 float v_ratio_prefetch_y[number_of_planes_minus_one + 1]; 389 float v_ratio_prefetch_c[number_of_planes_minus_one + 1]; 390 float destination_lines_for_prefetch[number_of_planes_minus_one + 1]; 391 float destination_lines_to_request_vm_inv_blank[number_of_planes_minus_one + 1]; 392 float destination_lines_to_request_row_in_vblank[number_of_planes_minus_one + 1]; 393 float min_ttuv_blank[number_of_planes_minus_one + 1]; 394 float byte_per_pixel_dety[number_of_planes_minus_one + 1]; 395 float byte_per_pixel_detc[number_of_planes_minus_one + 1]; 396 float swath_width_y[number_of_planes_minus_one + 1]; 397 float lines_in_dety[number_of_planes_minus_one + 1]; 398 float lines_in_dety_rounded_down_to_swath[number_of_planes_minus_one + 1]; 399 float lines_in_detc[number_of_planes_minus_one + 1]; 400 float lines_in_detc_rounded_down_to_swath[number_of_planes_minus_one + 1]; 401 float full_det_buffering_time_y[number_of_planes_minus_one + 1]; 402 float full_det_buffering_time_c[number_of_planes_minus_one + 1]; 403 float active_dram_clock_change_latency_margin[number_of_planes_minus_one + 1]; 404 float v_blank_dram_clock_change_latency_margin[number_of_planes_minus_one + 1]; 405 float dcfclk_deep_sleep_per_plane[number_of_planes_minus_one + 1]; 406 float read_bandwidth_plane_luma[number_of_planes_minus_one + 1]; 407 float read_bandwidth_plane_chroma[number_of_planes_minus_one + 1]; 408 float display_pipe_line_delivery_time_luma[number_of_planes_minus_one + 1]; 409 float display_pipe_line_delivery_time_chroma[number_of_planes_minus_one + 1]; 410 float display_pipe_line_delivery_time_luma_prefetch[number_of_planes_minus_one + 1]; 411 float display_pipe_line_delivery_time_chroma_prefetch[number_of_planes_minus_one + 1]; 412 float pixel_pte_bytes_per_row[number_of_planes_minus_one + 1]; 413 float meta_pte_bytes_frame[number_of_planes_minus_one + 1]; 414 float meta_row_byte[number_of_planes_minus_one + 1]; 415 float prefetch_source_lines_y[number_of_planes_minus_one + 1]; 416 float prefetch_source_lines_c[number_of_planes_minus_one + 1]; 417 float pscl_throughput[number_of_planes_minus_one + 1]; 418 float pscl_throughput_chroma[number_of_planes_minus_one + 1]; 419 float output_bpphdmi[number_of_planes_minus_one + 1]; 420 float output_bppdp4_lane_hbr[number_of_planes_minus_one + 1]; 421 float output_bppdp4_lane_hbr2[number_of_planes_minus_one + 1]; 422 float output_bppdp4_lane_hbr3[number_of_planes_minus_one + 1]; 423 float max_vstartup_lines[number_of_planes_minus_one + 1]; 424 float dispclk_with_ramping; 425 float dispclk_without_ramping; 426 float dppclk_using_single_dpp_luma; 427 float dppclk_using_single_dpp; 428 float dppclk_using_single_dpp_chroma; 429 enum dcn_bw_defs odm_capable; 430 float dispclk; 431 float dppclk; 432 float return_bandwidth_to_dcn; 433 enum dcn_bw_defs dcc_enabled_any_plane; 434 float return_bw; 435 float critical_compression; 436 float total_data_read_bandwidth; 437 float total_active_dpp; 438 float total_dcc_active_dpp; 439 float urgent_round_trip_and_out_of_order_latency; 440 float last_pixel_of_line_extra_watermark; 441 float data_fabric_line_delivery_time_luma; 442 float data_fabric_line_delivery_time_chroma; 443 float urgent_extra_latency; 444 float urgent_watermark; 445 float ptemeta_urgent_watermark; 446 float dram_clock_change_watermark; 447 float total_active_writeback; 448 float writeback_dram_clock_change_watermark; 449 float min_full_det_buffering_time; 450 float frame_time_for_min_full_det_buffering_time; 451 float average_read_bandwidth_gbyte_per_second; 452 float part_of_burst_that_fits_in_rob; 453 float stutter_burst_time; 454 float stutter_efficiency_not_including_vblank; 455 float smallest_vblank; 456 float v_blank_time; 457 float stutter_efficiency; 458 float dcf_clk_deep_sleep; 459 float stutter_exit_watermark; 460 float stutter_enter_plus_exit_watermark; 461 float effective_det_plus_lb_lines_luma; 462 float urgent_latency_support_us_luma; 463 float effective_det_plus_lb_lines_chroma; 464 float urgent_latency_support_us_chroma; 465 float min_urgent_latency_support_us; 466 float non_urgent_latency_tolerance; 467 float block_height256_bytes_y; 468 float block_height256_bytes_c; 469 float meta_request_width_y; 470 float meta_surf_width_y; 471 float meta_surf_height_y; 472 float meta_pte_bytes_frame_y; 473 float meta_row_byte_y; 474 float macro_tile_size_byte_y; 475 float macro_tile_height_y; 476 float pixel_pte_req_height_y; 477 float pixel_pte_req_width_y; 478 float pixel_pte_bytes_per_row_y; 479 float meta_request_width_c; 480 float meta_surf_width_c; 481 float meta_surf_height_c; 482 float meta_pte_bytes_frame_c; 483 float meta_row_byte_c; 484 float macro_tile_size_bytes_c; 485 float macro_tile_height_c; 486 float pixel_pte_req_height_c; 487 float pixel_pte_req_width_c; 488 float pixel_pte_bytes_per_row_c; 489 float max_partial_swath_y; 490 float max_partial_swath_c; 491 float t_calc; 492 float next_prefetch_mode; 493 float v_startup_lines; 494 enum dcn_bw_defs planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw; 495 enum dcn_bw_defs planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4; 496 enum dcn_bw_defs planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2; 497 enum dcn_bw_defs v_ratio_prefetch_more_than4; 498 enum dcn_bw_defs destination_line_times_for_prefetch_less_than2; 499 float prefetch_mode; 500 float dstx_after_scaler; 501 float dsty_after_scaler; 502 float v_update_offset_pix; 503 float total_repeater_delay_time; 504 float v_update_width_pix; 505 float v_ready_offset_pix; 506 float t_setup; 507 float t_wait; 508 float bandwidth_available_for_immediate_flip; 509 float tot_immediate_flip_bytes; 510 float max_rd_bandwidth; 511 float time_for_fetching_meta_pte; 512 float time_for_fetching_row_in_vblank; 513 float lines_to_request_prefetch_pixel_data; 514 float required_prefetch_pix_data_bw; 515 enum dcn_bw_defs prefetch_mode_supported; 516 float active_dp_ps; 517 float lb_latency_hiding_source_lines_y; 518 float lb_latency_hiding_source_lines_c; 519 float effective_lb_latency_hiding_y; 520 float effective_lb_latency_hiding_c; 521 float dpp_output_buffer_lines_y; 522 float dpp_output_buffer_lines_c; 523 float dppopp_buffering_y; 524 float max_det_buffering_time_y; 525 float active_dram_clock_change_latency_margin_y; 526 float dppopp_buffering_c; 527 float max_det_buffering_time_c; 528 float active_dram_clock_change_latency_margin_c; 529 float writeback_dram_clock_change_latency_margin; 530 float min_active_dram_clock_change_margin; 531 float v_blank_of_min_active_dram_clock_change_margin; 532 float second_min_active_dram_clock_change_margin; 533 float min_vblank_dram_clock_change_margin; 534 float dram_clock_change_margin; 535 float dram_clock_change_support; 536 float wr_bandwidth; 537 float max_used_bw; 538 }; 539 540 struct dcn_soc_bounding_box { 541 float sr_exit_time; /*us*/ 542 float sr_enter_plus_exit_time; /*us*/ 543 float urgent_latency; /*us*/ 544 float write_back_latency; /*us*/ 545 float percent_of_ideal_drambw_received_after_urg_latency; /*%*/ 546 int max_request_size; /*bytes*/ 547 float dcfclkv_max0p9; /*MHz*/ 548 float dcfclkv_nom0p8; /*MHz*/ 549 float dcfclkv_mid0p72; /*MHz*/ 550 float dcfclkv_min0p65; /*MHz*/ 551 float max_dispclk_vmax0p9; /*MHz*/ 552 float max_dispclk_vmid0p72; /*MHz*/ 553 float max_dispclk_vnom0p8; /*MHz*/ 554 float max_dispclk_vmin0p65; /*MHz*/ 555 float max_dppclk_vmax0p9; /*MHz*/ 556 float max_dppclk_vnom0p8; /*MHz*/ 557 float max_dppclk_vmid0p72; /*MHz*/ 558 float max_dppclk_vmin0p65; /*MHz*/ 559 float socclk; /*MHz*/ 560 float fabric_and_dram_bandwidth_vmax0p9; /*GB/s*/ 561 float fabric_and_dram_bandwidth_vnom0p8; /*GB/s*/ 562 float fabric_and_dram_bandwidth_vmid0p72; /*GB/s*/ 563 float fabric_and_dram_bandwidth_vmin0p65; /*GB/s*/ 564 float phyclkv_max0p9; /*MHz*/ 565 float phyclkv_nom0p8; /*MHz*/ 566 float phyclkv_mid0p72; /*MHz*/ 567 float phyclkv_min0p65; /*MHz*/ 568 float downspreading; /*%*/ 569 int round_trip_ping_latency_cycles; /*DCFCLK Cycles*/ 570 int urgent_out_of_order_return_per_channel; /*bytes*/ 571 int number_of_channels; 572 int vmm_page_size; /*bytes*/ 573 float dram_clock_change_latency; /*us*/ 574 int return_bus_width; /*bytes*/ 575 }; 576 extern const struct dcn_soc_bounding_box dcn10_soc_defaults; 577 578 struct dcn_ip_params { 579 float rob_buffer_size_in_kbyte; 580 float det_buffer_size_in_kbyte; 581 float dpp_output_buffer_pixels; 582 float opp_output_buffer_lines; 583 float pixel_chunk_size_in_kbyte; 584 enum dcn_bw_defs pte_enable; 585 int pte_chunk_size; /*kbytes*/ 586 int meta_chunk_size; /*kbytes*/ 587 int writeback_chunk_size; /*kbytes*/ 588 enum dcn_bw_defs odm_capability; 589 enum dcn_bw_defs dsc_capability; 590 int line_buffer_size; /*bit*/ 591 int max_line_buffer_lines; 592 enum dcn_bw_defs is_line_buffer_bpp_fixed; 593 int line_buffer_fixed_bpp; 594 int writeback_luma_buffer_size; /*kbytes*/ 595 int writeback_chroma_buffer_size; /*kbytes*/ 596 int max_num_dpp; 597 int max_num_writeback; 598 int max_dchub_topscl_throughput; /*pixels/dppclk*/ 599 int max_pscl_tolb_throughput; /*pixels/dppclk*/ 600 int max_lb_tovscl_throughput; /*pixels/dppclk*/ 601 int max_vscl_tohscl_throughput; /*pixels/dppclk*/ 602 float max_hscl_ratio; 603 float max_vscl_ratio; 604 int max_hscl_taps; 605 int max_vscl_taps; 606 int pte_buffer_size_in_requests; 607 float dispclk_ramping_margin; /*%*/ 608 float under_scan_factor; 609 int max_inter_dcn_tile_repeaters; 610 enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 611 enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed; 612 int dcfclk_cstate_latency; 613 }; 614 extern const struct dcn_ip_params dcn10_ip_defaults; 615 616 bool dcn_validate_bandwidth( 617 const struct core_dc *dc, 618 struct validate_context *context); 619 620 unsigned int dcn_find_dcfclk_suits_all( 621 const struct core_dc *dc, 622 struct clocks_value *clocks); 623 624 void dcn_bw_update_from_pplib(struct core_dc *dc); 625 void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc); 626 void dcn_bw_sync_calcs_and_dml(struct core_dc *dc); 627 628 #endif /* __DCN_CALCS_H__ */ 629 630