1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright 2012-15 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DC_CLOCK_SOURCE_H__ 28 #define __DC_CLOCK_SOURCE_H__ 29 30 #include "dc_types.h" 31 #include "include/grph_object_id.h" 32 #include "include/bios_parser_types.h" 33 34 struct clock_source; 35 36 struct spread_spectrum_data { 37 uint32_t percentage; /*> In unit of 0.01% or 0.001%*/ 38 uint32_t percentage_divider; /*> 100 or 1000 */ 39 uint32_t freq_range_khz; 40 uint32_t modulation_freq_hz; 41 42 struct spread_spectrum_flags flags; 43 }; 44 45 struct delta_sigma_data { 46 uint32_t feedback_amount; 47 uint32_t nfrac_amount; 48 uint32_t ds_frac_size; 49 uint32_t ds_frac_amount; 50 }; 51 52 /** 53 * Pixel Clock Parameters structure 54 * These parameters are required as input 55 * when calculating Pixel Clock Dividers for requested Pixel Clock 56 */ 57 struct pixel_clk_flags { 58 uint32_t ENABLE_SS:1; 59 uint32_t DISPLAY_BLANKED:1; 60 uint32_t PROGRAM_PIXEL_CLOCK:1; 61 uint32_t PROGRAM_ID_CLOCK:1; 62 uint32_t SUPPORT_YCBCR420:1; 63 }; 64 65 /** 66 * Display Port HW De spread of Reference Clock related Parameters structure 67 * Store it once at boot for later usage 68 */ 69 struct csdp_ref_clk_ds_params { 70 bool hw_dso_n_dp_ref_clk; 71 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/ 72 uint32_t avg_dp_ref_clk_khz; 73 /* Average DP Reference clock (in KHz)*/ 74 uint32_t ss_percentage_on_dp_ref_clk; 75 /* DP Reference clock SS percentage 76 * (not to be mixed with DP IDCLK SS from PLL Settings)*/ 77 uint32_t ss_percentage_divider; 78 /* DP Reference clock SS percentage divider */ 79 }; 80 81 struct pixel_clk_params { 82 uint32_t requested_pix_clk_100hz; 83 /*> Requested Pixel Clock 84 * (based on Video Timing standard used for requested mode)*/ 85 uint32_t requested_sym_clk; /* in KHz */ 86 /*> Requested Sym Clock (relevant only for display port)*/ 87 uint32_t dp_ref_clk; /* in KHz */ 88 /*> DP reference clock - calculated only for DP signal for specific cases*/ 89 struct graphics_object_id encoder_object_id; 90 /*> Encoder object Id - needed by VBIOS Exec table*/ 91 enum signal_type signal_type; 92 /*> signalType -> Encoder Mode - needed by VBIOS Exec table*/ 93 enum controller_id controller_id; 94 /*> ControllerId - which controller using this PLL*/ 95 enum dc_color_depth color_depth; 96 struct csdp_ref_clk_ds_params de_spread_params; 97 /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/ 98 enum dc_pixel_encoding pixel_encoding; 99 struct pixel_clk_flags flags; 100 uint32_t dio_se_pix_per_cycle; 101 }; 102 103 /** 104 * Pixel Clock Dividers structure with desired Pixel Clock 105 * (adjusted after VBIOS exec table), 106 * with actually calculated Clock and reference Crystal frequency 107 */ 108 struct pll_settings { 109 uint32_t actual_pix_clk_100hz; 110 uint32_t adjusted_pix_clk_100hz; 111 uint32_t calculated_pix_clk_100hz; 112 uint32_t vco_freq; 113 uint32_t reference_freq; 114 uint32_t reference_divider; 115 uint32_t feedback_divider; 116 uint32_t fract_feedback_divider; 117 uint32_t pix_clk_post_divider; 118 uint32_t ss_percentage; 119 bool use_external_clk; 120 }; 121 122 struct calc_pll_clock_source_init_data { 123 struct dc_bios *bp; 124 uint32_t min_pix_clk_pll_post_divider; 125 uint32_t max_pix_clk_pll_post_divider; 126 uint32_t min_pll_ref_divider; 127 uint32_t max_pll_ref_divider; 128 uint32_t min_override_input_pxl_clk_pll_freq_khz; 129 /* if not 0, override the firmware info */ 130 131 uint32_t max_override_input_pxl_clk_pll_freq_khz; 132 /* if not 0, override the firmware info */ 133 134 uint32_t num_fract_fb_divider_decimal_point; 135 /* number of decimal point for fractional feedback divider value */ 136 137 uint32_t num_fract_fb_divider_decimal_point_precision; 138 /* number of decimal point to round off for fractional feedback divider value*/ 139 struct dc_context *ctx; 140 141 }; 142 143 struct calc_pll_clock_source { 144 uint32_t ref_freq_khz; 145 uint32_t min_pix_clock_pll_post_divider; 146 uint32_t max_pix_clock_pll_post_divider; 147 uint32_t min_pll_ref_divider; 148 uint32_t max_pll_ref_divider; 149 150 uint32_t max_vco_khz; 151 uint32_t min_vco_khz; 152 uint32_t min_pll_input_freq_khz; 153 uint32_t max_pll_input_freq_khz; 154 155 uint32_t fract_fb_divider_decimal_points_num; 156 uint32_t fract_fb_divider_factor; 157 uint32_t fract_fb_divider_precision; 158 uint32_t fract_fb_divider_precision_factor; 159 struct dc_context *ctx; 160 }; 161 162 struct clock_source_funcs { 163 bool (*cs_power_down)( 164 struct clock_source *); 165 bool (*program_pix_clk)( 166 struct clock_source *, 167 struct pixel_clk_params *, 168 enum dp_link_encoding encoding, 169 struct pll_settings *); 170 uint32_t (*get_pix_clk_dividers)( 171 struct clock_source *, 172 struct pixel_clk_params *, 173 struct pll_settings *); 174 bool (*get_dp_dto_frequency_100hz)( 175 const struct clock_source *clock_source, 176 unsigned int inst, 177 unsigned int *pixel_clk_100hz); 178 bool (*override_dp_pix_clk)( 179 struct clock_source *clock_source, 180 unsigned int inst, 181 unsigned int pixel_clk, 182 unsigned int ref_clk); 183 }; 184 185 struct clock_source { 186 const struct clock_source_funcs *funcs; 187 struct dc_context *ctx; 188 enum clock_source_id id; 189 unsigned int inst; 190 bool dp_clk_src; 191 }; 192 193 #endif 194