1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 35 struct pipe_ctx; 36 struct dc_state; 37 struct dc_stream_status; 38 struct dc_writeback_info; 39 struct dchub_init_data; 40 struct dc_static_screen_params; 41 struct resource_pool; 42 struct dc_phy_addr_space_config; 43 struct dc_virtual_addr_space_config; 44 struct dpp; 45 struct dce_hwseq; 46 struct link_resource; 47 struct dc_dmub_cmd; 48 struct pg_block_update; 49 struct drr_params; 50 struct dc_underflow_debug_data; 51 52 struct subvp_pipe_control_lock_fast_params { 53 struct dc *dc; 54 bool lock; 55 bool subvp_immediate_flip; 56 }; 57 58 struct pipe_control_lock_params { 59 struct dc *dc; 60 struct pipe_ctx *pipe_ctx; 61 bool lock; 62 }; 63 64 struct set_flip_control_gsl_params { 65 struct pipe_ctx *pipe_ctx; 66 bool flip_immediate; 67 }; 68 69 struct program_triplebuffer_params { 70 const struct dc *dc; 71 struct pipe_ctx *pipe_ctx; 72 bool enableTripleBuffer; 73 }; 74 75 struct update_plane_addr_params { 76 struct dc *dc; 77 struct pipe_ctx *pipe_ctx; 78 }; 79 80 struct set_input_transfer_func_params { 81 struct dc *dc; 82 struct pipe_ctx *pipe_ctx; 83 struct dc_plane_state *plane_state; 84 }; 85 86 struct program_gamut_remap_params { 87 struct pipe_ctx *pipe_ctx; 88 }; 89 90 struct program_manual_trigger_params { 91 struct pipe_ctx *pipe_ctx; 92 }; 93 94 struct send_dmcub_cmd_params { 95 struct dc_context *ctx; 96 union dmub_rb_cmd *cmd; 97 enum dm_dmub_wait_type wait_type; 98 }; 99 100 struct setup_dpp_params { 101 struct pipe_ctx *pipe_ctx; 102 }; 103 104 struct program_bias_and_scale_params { 105 struct pipe_ctx *pipe_ctx; 106 }; 107 108 struct set_output_transfer_func_params { 109 struct dc *dc; 110 struct pipe_ctx *pipe_ctx; 111 const struct dc_stream_state *stream; 112 }; 113 114 struct update_visual_confirm_params { 115 struct dc *dc; 116 struct pipe_ctx *pipe_ctx; 117 int mpcc_id; 118 }; 119 120 struct power_on_mpc_mem_pwr_params { 121 struct mpc *mpc; 122 int mpcc_id; 123 bool power_on; 124 }; 125 126 struct set_output_csc_params { 127 struct mpc *mpc; 128 int opp_id; 129 const uint16_t *regval; 130 enum mpc_output_csc_mode ocsc_mode; 131 }; 132 133 struct set_ocsc_default_params { 134 struct mpc *mpc; 135 int opp_id; 136 enum dc_color_space color_space; 137 enum mpc_output_csc_mode ocsc_mode; 138 }; 139 140 struct subvp_save_surf_addr { 141 struct dc_dmub_srv *dc_dmub_srv; 142 const struct dc_plane_address *addr; 143 uint8_t subvp_index; 144 }; 145 146 struct wait_for_dcc_meta_propagation_params { 147 const struct dc *dc; 148 const struct pipe_ctx *top_pipe_to_program; 149 }; 150 151 struct fams2_global_control_lock_fast_params { 152 struct dc *dc; 153 bool is_required; 154 bool lock; 155 }; 156 157 union block_sequence_params { 158 struct update_plane_addr_params update_plane_addr_params; 159 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 160 struct pipe_control_lock_params pipe_control_lock_params; 161 struct set_flip_control_gsl_params set_flip_control_gsl_params; 162 struct program_triplebuffer_params program_triplebuffer_params; 163 struct set_input_transfer_func_params set_input_transfer_func_params; 164 struct program_gamut_remap_params program_gamut_remap_params; 165 struct program_manual_trigger_params program_manual_trigger_params; 166 struct send_dmcub_cmd_params send_dmcub_cmd_params; 167 struct setup_dpp_params setup_dpp_params; 168 struct program_bias_and_scale_params program_bias_and_scale_params; 169 struct set_output_transfer_func_params set_output_transfer_func_params; 170 struct update_visual_confirm_params update_visual_confirm_params; 171 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 172 struct set_output_csc_params set_output_csc_params; 173 struct set_ocsc_default_params set_ocsc_default_params; 174 struct subvp_save_surf_addr subvp_save_surf_addr; 175 struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; 176 struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params; 177 }; 178 179 enum block_sequence_func { 180 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 181 OPTC_PIPE_CONTROL_LOCK, 182 HUBP_SET_FLIP_CONTROL_GSL, 183 HUBP_PROGRAM_TRIPLEBUFFER, 184 HUBP_UPDATE_PLANE_ADDR, 185 DPP_SET_INPUT_TRANSFER_FUNC, 186 DPP_PROGRAM_GAMUT_REMAP, 187 OPTC_PROGRAM_MANUAL_TRIGGER, 188 DMUB_SEND_DMCUB_CMD, 189 DPP_SETUP_DPP, 190 DPP_PROGRAM_BIAS_AND_SCALE, 191 DPP_SET_OUTPUT_TRANSFER_FUNC, 192 MPC_UPDATE_VISUAL_CONFIRM, 193 MPC_POWER_ON_MPC_MEM_PWR, 194 MPC_SET_OUTPUT_CSC, 195 MPC_SET_OCSC_DEFAULT, 196 DMUB_SUBVP_SAVE_SURF_ADDR, 197 HUBP_WAIT_FOR_DCC_META_PROP, 198 DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST, 199 /* This must be the last value in this enum, add new ones above */ 200 HWSS_BLOCK_SEQUENCE_FUNC_COUNT 201 }; 202 203 struct block_sequence { 204 union block_sequence_params params; 205 enum block_sequence_func func; 206 }; 207 208 #define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES) 209 210 struct hw_sequencer_funcs { 211 void (*hardware_release)(struct dc *dc); 212 /* Embedded Display Related */ 213 void (*edp_power_control)(struct dc_link *link, bool enable); 214 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 215 void (*edp_wait_for_T12)(struct dc_link *link); 216 217 /* Pipe Programming Related */ 218 void (*init_hw)(struct dc *dc); 219 void (*power_down_on_boot)(struct dc *dc); 220 void (*enable_accelerated_mode)(struct dc *dc, 221 struct dc_state *context); 222 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 223 struct dc_state *context); 224 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 225 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 226 void (*apply_ctx_for_surface)(struct dc *dc, 227 const struct dc_stream_state *stream, 228 int num_planes, struct dc_state *context); 229 void (*program_front_end_for_ctx)(struct dc *dc, 230 struct dc_state *context); 231 void (*wait_for_pending_cleared)(struct dc *dc, 232 struct dc_state *context); 233 void (*post_unlock_program_front_end)(struct dc *dc, 234 struct dc_state *context); 235 void (*update_plane_addr)(const struct dc *dc, 236 struct pipe_ctx *pipe_ctx); 237 void (*update_dchub)(struct dce_hwseq *hws, 238 struct dchub_init_data *dh_data); 239 void (*wait_for_mpcc_disconnect)(struct dc *dc, 240 struct resource_pool *res_pool, 241 struct pipe_ctx *pipe_ctx); 242 void (*edp_backlight_control)( 243 struct dc_link *link, 244 bool enable); 245 void (*program_triplebuffer)(const struct dc *dc, 246 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 247 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 248 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 249 void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); 250 251 /* Pipe Lock Related */ 252 void (*pipe_control_lock)(struct dc *dc, 253 struct pipe_ctx *pipe, bool lock); 254 void (*interdependent_update_lock)(struct dc *dc, 255 struct dc_state *context, bool lock); 256 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 257 bool flip_immediate); 258 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 259 260 /* Timing Related */ 261 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 262 struct crtc_position *position); 263 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 264 void (*calc_vupdate_position)( 265 struct dc *dc, 266 struct pipe_ctx *pipe_ctx, 267 uint32_t *start_line, 268 uint32_t *end_line); 269 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 270 int group_size, struct pipe_ctx *grouped_pipes[]); 271 void (*enable_timing_synchronization)(struct dc *dc, 272 struct dc_state *state, 273 int group_index, int group_size, 274 struct pipe_ctx *grouped_pipes[]); 275 void (*enable_vblanks_synchronization)(struct dc *dc, 276 int group_index, int group_size, 277 struct pipe_ctx *grouped_pipes[]); 278 void (*setup_periodic_interrupt)(struct dc *dc, 279 struct pipe_ctx *pipe_ctx); 280 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 281 struct dc_crtc_timing_adjust adjust); 282 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 283 int num_pipes, 284 const struct dc_static_screen_params *events); 285 286 /* Stream Related */ 287 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 288 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 289 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 290 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 291 struct dc_link_settings *link_settings); 292 293 /* Bandwidth Related */ 294 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 295 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 296 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 297 298 /* Infopacket Related */ 299 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 300 void (*send_immediate_sdp_message)( 301 struct pipe_ctx *pipe_ctx, 302 const uint8_t *custom_sdp_message, 303 unsigned int sdp_message_size); 304 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 305 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 306 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 307 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 308 309 /* Cursor Related */ 310 void (*set_cursor_position)(struct pipe_ctx *pipe); 311 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 312 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 313 314 /* Colour Related */ 315 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 316 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 317 enum dc_color_space colorspace, 318 uint16_t *matrix, int opp_id); 319 void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 320 321 /* VM Related */ 322 int (*init_sys_ctx)(struct dce_hwseq *hws, 323 struct dc *dc, 324 struct dc_phy_addr_space_config *pa_config); 325 void (*init_vm_ctx)(struct dce_hwseq *hws, 326 struct dc *dc, 327 struct dc_virtual_addr_space_config *va_config, 328 int vmid); 329 330 /* Writeback Related */ 331 void (*update_writeback)(struct dc *dc, 332 struct dc_writeback_info *wb_info, 333 struct dc_state *context); 334 void (*enable_writeback)(struct dc *dc, 335 struct dc_writeback_info *wb_info, 336 struct dc_state *context); 337 void (*disable_writeback)(struct dc *dc, 338 unsigned int dwb_pipe_inst); 339 340 /* Clock Related */ 341 enum dc_status (*set_clock)(struct dc *dc, 342 enum dc_clock_type clock_type, 343 uint32_t clk_khz, uint32_t stepping); 344 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 345 struct dc_clock_config *clock_cfg); 346 void (*optimize_pwr_state)(const struct dc *dc, 347 struct dc_state *context); 348 void (*exit_optimized_pwr_state)(const struct dc *dc, 349 struct dc_state *context); 350 void (*calculate_pix_rate_divider)(struct dc *dc, 351 struct dc_state *context, 352 const struct dc_stream_state *stream); 353 354 /* Audio Related */ 355 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 356 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 357 358 /* Stereo 3D Related */ 359 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 360 361 /* HW State Logging Related */ 362 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 363 void (*log_color_state)(struct dc *dc, 364 struct dc_log_buffer_ctx *log_ctx); 365 void (*get_hw_state)(struct dc *dc, char *pBuf, 366 unsigned int bufSize, unsigned int mask); 367 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 368 369 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 370 struct set_backlight_level_params *params); 371 372 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 373 374 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 375 376 void (*enable_dp_link_output)(struct dc_link *link, 377 const struct link_resource *link_res, 378 enum signal_type signal, 379 enum clock_source_id clock_source, 380 const struct dc_link_settings *link_settings); 381 void (*enable_tmds_link_output)(struct dc_link *link, 382 const struct link_resource *link_res, 383 enum signal_type signal, 384 enum clock_source_id clock_source, 385 enum dc_color_depth color_depth, 386 uint32_t pixel_clock); 387 void (*enable_lvds_link_output)(struct dc_link *link, 388 const struct link_resource *link_res, 389 enum clock_source_id clock_source, 390 uint32_t pixel_clock); 391 void (*disable_link_output)(struct dc_link *link, 392 const struct link_resource *link_res, 393 enum signal_type signal); 394 395 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 396 397 /* Idle Optimization Related */ 398 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 399 400 bool (*does_plane_fit_in_mall)(struct dc *dc, 401 unsigned int pitch, 402 unsigned int height, 403 enum surface_pixel_format format, 404 struct dc_cursor_attributes *cursor_attr); 405 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 406 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 407 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 408 void (*subvp_pipe_control_lock)(struct dc *dc, 409 struct dc_state *context, 410 bool lock, 411 bool should_lock_all_pipes, 412 struct pipe_ctx *top_pipe_to_program, 413 bool subvp_prev_use); 414 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 415 416 void (*z10_restore)(const struct dc *dc); 417 void (*z10_save_init)(struct dc *dc); 418 bool (*is_abm_supported)(struct dc *dc, 419 struct dc_state *context, struct dc_stream_state *stream); 420 421 void (*set_disp_pattern_generator)(const struct dc *dc, 422 struct pipe_ctx *pipe_ctx, 423 enum controller_dp_test_pattern test_pattern, 424 enum controller_dp_color_space color_space, 425 enum dc_color_depth color_depth, 426 const struct tg_color *solid_color, 427 int width, int height, int offset); 428 void (*blank_phantom)(struct dc *dc, 429 struct timing_generator *tg, 430 int width, 431 int height); 432 void (*update_visual_confirm_color)(struct dc *dc, 433 struct pipe_ctx *pipe_ctx, 434 int mpcc_id); 435 void (*update_phantom_vp_position)(struct dc *dc, 436 struct dc_state *context, 437 struct pipe_ctx *phantom_pipe); 438 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 439 440 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 441 struct pg_block_update *update_state); 442 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 443 struct pg_block_update *update_state); 444 void (*hw_block_power_up)(struct dc *dc, 445 struct pg_block_update *update_state); 446 void (*hw_block_power_down)(struct dc *dc, 447 struct pg_block_update *update_state); 448 void (*root_clock_control)(struct dc *dc, 449 struct pg_block_update *update_state, bool power_on); 450 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 451 const struct dc_state *cur_ctx, 452 const struct dc_state *new_ctx); 453 void (*wait_for_dcc_meta_propagation)(const struct dc *dc, 454 const struct pipe_ctx *top_pipe_to_program); 455 void (*fams2_global_control_lock)(struct dc *dc, 456 struct dc_state *context, 457 bool lock); 458 void (*fams2_update_config)(struct dc *dc, 459 struct dc_state *context, 460 bool enable); 461 void (*fams2_global_control_lock_fast)(union block_sequence_params *params); 462 void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); 463 void (*program_outstanding_updates)(struct dc *dc, 464 struct dc_state *context); 465 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); 466 void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); 467 void (*detect_pipe_changes)(struct dc_state *old_state, 468 struct dc_state *new_state, 469 struct pipe_ctx *old_pipe, 470 struct pipe_ctx *new_pipe); 471 void (*enable_plane)(struct dc *dc, 472 struct pipe_ctx *pipe_ctx, 473 struct dc_state *context); 474 void (*update_dchubp_dpp)(struct dc *dc, 475 struct pipe_ctx *pipe_ctx, 476 struct dc_state *context); 477 void (*post_unlock_reset_opp)(struct dc *dc, 478 struct pipe_ctx *opp_head); 479 void (*get_underflow_debug_data)(const struct dc *dc, 480 struct timing_generator *tg, 481 struct dc_underflow_debug_data *out_data); 482 }; 483 484 void color_space_to_black_color( 485 const struct dc *dc, 486 enum dc_color_space colorspace, 487 struct tg_color *black_color); 488 489 bool hwss_wait_for_blank_complete( 490 struct timing_generator *tg); 491 492 const uint16_t *find_color_matrix( 493 enum dc_color_space color_space, 494 uint32_t *array_size); 495 496 void get_surface_tile_visual_confirm_color( 497 struct pipe_ctx *pipe_ctx, 498 struct tg_color *color); 499 void get_surface_visual_confirm_color( 500 const struct pipe_ctx *pipe_ctx, 501 struct tg_color *color); 502 503 void get_hdr_visual_confirm_color( 504 struct pipe_ctx *pipe_ctx, 505 struct tg_color *color); 506 void get_mpctree_visual_confirm_color( 507 struct pipe_ctx *pipe_ctx, 508 struct tg_color *color); 509 void get_smartmux_visual_confirm_color( 510 struct dc *dc, 511 struct tg_color *color); 512 void get_vabc_visual_confirm_color( 513 struct pipe_ctx *pipe_ctx, 514 struct tg_color *color); 515 void get_subvp_visual_confirm_color( 516 struct pipe_ctx *pipe_ctx, 517 struct tg_color *color); 518 void get_fams2_visual_confirm_color( 519 struct dc *dc, 520 struct dc_state *context, 521 struct pipe_ctx *pipe_ctx, 522 struct tg_color *color); 523 524 void get_mclk_switch_visual_confirm_color( 525 struct pipe_ctx *pipe_ctx, 526 struct tg_color *color); 527 528 void get_cursor_visual_confirm_color( 529 struct pipe_ctx *pipe_ctx, 530 struct tg_color *color); 531 532 void get_dcc_visual_confirm_color( 533 struct dc *dc, 534 struct pipe_ctx *pipe_ctx, 535 struct tg_color *color); 536 537 void set_p_state_switch_method( 538 struct dc *dc, 539 struct dc_state *context, 540 struct pipe_ctx *pipe_ctx); 541 542 void set_drr_and_clear_adjust_pending( 543 struct pipe_ctx *pipe_ctx, 544 struct dc_stream_state *stream, 545 struct drr_params *params); 546 547 void hwss_execute_sequence(struct dc *dc, 548 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 549 int num_steps); 550 551 void hwss_build_fast_sequence(struct dc *dc, 552 struct dc_dmub_cmd *dc_dmub_cmd, 553 unsigned int dmub_cmd_count, 554 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 555 unsigned int *num_steps, 556 struct pipe_ctx *pipe_ctx, 557 struct dc_stream_status *stream_status, 558 struct dc_state *context); 559 560 void hwss_wait_for_all_blank_complete(struct dc *dc, 561 struct dc_state *context); 562 563 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, 564 struct dc_state *context); 565 566 void hwss_wait_for_no_pipes_pending(struct dc *dc, 567 struct dc_state *context); 568 569 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, 570 struct dc_state *dc_context); 571 572 void hwss_process_outstanding_hw_updates(struct dc *dc, 573 struct dc_state *dc_context); 574 575 void hwss_send_dmcub_cmd(union block_sequence_params *params); 576 577 void hwss_program_manual_trigger(union block_sequence_params *params); 578 579 void hwss_setup_dpp(union block_sequence_params *params); 580 581 void hwss_program_bias_and_scale(union block_sequence_params *params); 582 583 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 584 585 void hwss_set_output_csc(union block_sequence_params *params); 586 587 void hwss_set_ocsc_default(union block_sequence_params *params); 588 589 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 590 591 #endif /* __DC_HW_SEQUENCER_H__ */ 592