1 /* 2 * Copyright 2015-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 #include "inc/hw/hw_shared.h" 35 #include "dsc/dsc.h" 36 #include "link_service_types.h" 37 38 struct pipe_ctx; 39 struct dc_state; 40 struct dc_stream_status; 41 struct dc_writeback_info; 42 struct dchub_init_data; 43 struct dc_static_screen_params; 44 struct resource_pool; 45 struct dc_phy_addr_space_config; 46 struct dc_virtual_addr_space_config; 47 struct dpp; 48 struct dce_hwseq; 49 struct link_resource; 50 struct dc_dmub_cmd; 51 struct pg_block_update; 52 struct drr_params; 53 struct dc_underflow_debug_data; 54 struct dsc_optc_config; 55 struct vm_system_aperture_param; 56 struct dc_measured_memory_qos; 57 struct stream_encoder; 58 struct hpo_dp_stream_encoder; 59 struct hpo_frl_stream_encoder; 60 struct link_training_settings; 61 struct dc_link; 62 struct dc_crtc_timing; 63 struct subvp_pipe_control_lock_fast_params { 64 struct dc *dc; 65 bool lock; 66 bool subvp_immediate_flip; 67 }; 68 69 struct pipe_control_lock_params { 70 struct dc *dc; 71 struct pipe_ctx *pipe_ctx; 72 bool lock; 73 }; 74 75 struct set_flip_control_gsl_params { 76 struct hubp *hubp; 77 bool flip_immediate; 78 }; 79 80 struct program_triplebuffer_params { 81 const struct dc *dc; 82 struct pipe_ctx *pipe_ctx; 83 bool enableTripleBuffer; 84 }; 85 86 struct update_plane_addr_params { 87 struct dc *dc; 88 struct pipe_ctx *pipe_ctx; 89 }; 90 91 struct set_input_transfer_func_params { 92 struct dc *dc; 93 struct pipe_ctx *pipe_ctx; 94 struct dc_plane_state *plane_state; 95 }; 96 97 struct program_gamut_remap_params { 98 struct pipe_ctx *pipe_ctx; 99 }; 100 101 struct hubp_enable_3dlut_fl_params { 102 struct hubp *hubp; 103 }; 104 105 struct tg_setup_vertical_interrupt0_params { 106 struct timing_generator *tg; 107 uint32_t start_line; 108 uint32_t end_line; 109 }; 110 111 struct update_info_frame_params { 112 struct dc *dc; 113 struct pipe_ctx *pipe_ctx; 114 }; 115 116 struct program_manual_trigger_params { 117 struct pipe_ctx *pipe_ctx; 118 }; 119 120 struct send_dmcub_cmd_params { 121 struct dc_context *ctx; 122 union dmub_rb_cmd *cmd; 123 enum dm_dmub_wait_type wait_type; 124 }; 125 126 struct setup_dpp_params { 127 struct pipe_ctx *pipe_ctx; 128 }; 129 130 struct program_bias_and_scale_params { 131 struct pipe_ctx *pipe_ctx; 132 }; 133 134 struct set_output_transfer_func_params { 135 struct dc *dc; 136 struct pipe_ctx *pipe_ctx; 137 const struct dc_stream_state *stream; 138 }; 139 140 struct update_visual_confirm_params { 141 struct dc *dc; 142 struct pipe_ctx *pipe_ctx; 143 int mpcc_id; 144 }; 145 146 struct power_on_mpc_mem_pwr_params { 147 struct mpc *mpc; 148 int mpcc_id; 149 bool power_on; 150 }; 151 152 struct set_output_csc_params { 153 struct mpc *mpc; 154 int opp_id; 155 const uint16_t *regval; 156 enum mpc_output_csc_mode ocsc_mode; 157 }; 158 159 struct set_ocsc_default_params { 160 struct mpc *mpc; 161 int opp_id; 162 enum dc_color_space color_space; 163 enum mpc_output_csc_mode ocsc_mode; 164 }; 165 166 struct subvp_save_surf_addr { 167 struct dc_dmub_srv *dc_dmub_srv; 168 const struct dc_plane_address *addr; 169 uint8_t subvp_index; 170 }; 171 172 struct wait_for_dcc_meta_propagation_params { 173 const struct dc *dc; 174 const struct pipe_ctx *top_pipe_to_program; 175 }; 176 177 struct dmub_hw_control_lock_fast_params { 178 struct dc *dc; 179 bool is_required; 180 bool lock; 181 }; 182 183 struct program_surface_config_params { 184 struct hubp *hubp; 185 enum surface_pixel_format format; 186 struct dc_tiling_info *tiling_info; 187 struct plane_size plane_size; 188 enum dc_rotation_angle rotation; 189 struct dc_plane_dcc_param *dcc; 190 bool horizontal_mirror; 191 int compat_level; 192 }; 193 194 struct program_mcache_id_and_split_coordinate { 195 struct hubp *hubp; 196 struct dml2_hubp_pipe_mcache_regs *mcache_regs; 197 }; 198 199 struct control_cm_hist_params { 200 struct dpp *dpp; 201 struct cm_hist_control cm_hist_control; 202 enum dc_color_space color_space; 203 }; 204 205 struct program_cursor_update_now_params { 206 struct dc *dc; 207 struct pipe_ctx *pipe_ctx; 208 }; 209 210 struct hubp_wait_pipe_read_start_params { 211 struct hubp *hubp; 212 }; 213 214 struct apply_update_flags_for_phantom_params { 215 struct pipe_ctx *pipe_ctx; 216 }; 217 218 struct update_phantom_vp_position_params { 219 struct dc *dc; 220 struct pipe_ctx *pipe_ctx; 221 struct dc_state *context; 222 }; 223 224 struct set_odm_combine_params { 225 struct timing_generator *tg; 226 int opp_inst[MAX_PIPES]; 227 int opp_head_count; 228 int odm_slice_width; 229 int last_odm_slice_width; 230 }; 231 232 struct set_odm_bypass_params { 233 struct timing_generator *tg; 234 const struct dc_crtc_timing *timing; 235 }; 236 237 struct opp_pipe_clock_control_params { 238 struct output_pixel_processor *opp; 239 bool enable; 240 }; 241 242 struct opp_program_left_edge_extra_pixel_params { 243 struct output_pixel_processor *opp; 244 enum dc_pixel_encoding pixel_encoding; 245 bool is_otg_master; 246 }; 247 248 struct dccg_set_dto_dscclk_params { 249 struct dccg *dccg; 250 int inst; 251 int num_slices_h; 252 }; 253 254 struct dsc_set_config_params { 255 struct display_stream_compressor *dsc; 256 struct dsc_config *dsc_cfg; 257 struct dsc_optc_config *dsc_optc_cfg; 258 }; 259 260 struct dsc_enable_params { 261 struct display_stream_compressor *dsc; 262 int opp_inst; 263 }; 264 265 struct tg_set_dsc_config_params { 266 struct timing_generator *tg; 267 struct dsc_optc_config *dsc_optc_cfg; 268 bool enable; 269 }; 270 271 struct dsc_disconnect_params { 272 struct display_stream_compressor *dsc; 273 }; 274 275 struct dsc_read_state_params { 276 struct display_stream_compressor *dsc; 277 struct dcn_dsc_state *dsc_state; 278 }; 279 280 struct dsc_calculate_and_set_config_params { 281 struct pipe_ctx *pipe_ctx; 282 struct dsc_optc_config dsc_optc_cfg; 283 bool enable; 284 int opp_cnt; 285 }; 286 287 struct dsc_enable_with_opp_params { 288 struct pipe_ctx *pipe_ctx; 289 }; 290 291 struct program_tg_params { 292 struct dc *dc; 293 struct pipe_ctx *pipe_ctx; 294 struct dc_state *context; 295 }; 296 297 struct tg_program_global_sync_params { 298 struct timing_generator *tg; 299 int vready_offset; 300 unsigned int vstartup_lines; 301 unsigned int vupdate_offset_pixels; 302 unsigned int vupdate_vupdate_width_pixels; 303 unsigned int pstate_keepout_start_lines; 304 }; 305 306 struct tg_wait_for_state_params { 307 struct timing_generator *tg; 308 enum crtc_state state; 309 }; 310 311 struct tg_set_vtg_params_params { 312 struct timing_generator *tg; 313 struct dc_crtc_timing *timing; 314 bool program_fp2; 315 }; 316 317 struct tg_set_gsl_params { 318 struct timing_generator *tg; 319 struct gsl_params gsl; 320 }; 321 322 struct tg_set_gsl_source_select_params { 323 struct timing_generator *tg; 324 int group_idx; 325 uint32_t gsl_ready_signal; 326 }; 327 328 struct setup_vupdate_interrupt_params { 329 struct dc *dc; 330 struct pipe_ctx *pipe_ctx; 331 }; 332 333 struct tg_setup_vertical_interrupt2_params { 334 struct timing_generator *tg; 335 int start_line; 336 }; 337 338 struct dpp_set_hdr_multiplier_params { 339 struct dpp *dpp; 340 uint32_t hw_mult; 341 }; 342 343 struct program_det_size_params { 344 struct hubbub *hubbub; 345 unsigned int hubp_inst; 346 unsigned int det_buffer_size_kb; 347 }; 348 349 struct program_det_segments_params { 350 struct hubbub *hubbub; 351 unsigned int hubp_inst; 352 unsigned int det_size; 353 }; 354 355 struct update_dchubp_dpp_params { 356 struct dc *dc; 357 struct pipe_ctx *pipe_ctx; 358 struct dc_state *context; 359 }; 360 361 struct opp_set_dyn_expansion_params { 362 struct output_pixel_processor *opp; 363 enum dc_color_space color_space; 364 enum dc_color_depth color_depth; 365 enum signal_type signal; 366 }; 367 368 struct opp_program_fmt_params { 369 struct output_pixel_processor *opp; 370 struct bit_depth_reduction_params *fmt_bit_depth; 371 struct clamping_and_pixel_encoding_params *clamping; 372 }; 373 374 struct opp_program_bit_depth_reduction_params { 375 struct output_pixel_processor *opp; 376 bool use_default_params; 377 struct pipe_ctx *pipe_ctx; 378 }; 379 380 struct opp_set_disp_pattern_generator_params { 381 struct output_pixel_processor *opp; 382 enum controller_dp_test_pattern test_pattern; 383 enum controller_dp_color_space color_space; 384 enum dc_color_depth color_depth; 385 struct tg_color solid_color; 386 bool use_solid_color; 387 int width; 388 int height; 389 int offset; 390 }; 391 392 struct set_abm_pipe_params { 393 struct dc *dc; 394 struct pipe_ctx *pipe_ctx; 395 }; 396 397 struct set_abm_level_params { 398 struct abm *abm; 399 unsigned int abm_level; 400 }; 401 402 struct set_abm_immediate_disable_params { 403 struct dc *dc; 404 struct pipe_ctx *pipe_ctx; 405 }; 406 407 struct set_disp_pattern_generator_params { 408 struct dc *dc; 409 struct pipe_ctx *pipe_ctx; 410 enum controller_dp_test_pattern test_pattern; 411 enum controller_dp_color_space color_space; 412 enum dc_color_depth color_depth; 413 const struct tg_color *solid_color; 414 int width; 415 int height; 416 int offset; 417 }; 418 419 struct mpc_update_blending_params { 420 struct mpc *mpc; 421 struct mpcc_blnd_cfg blnd_cfg; 422 int mpcc_id; 423 }; 424 425 struct mpc_assert_idle_mpcc_params { 426 struct mpc *mpc; 427 int mpcc_id; 428 }; 429 430 struct mpc_insert_plane_params { 431 struct mpc *mpc; 432 struct mpc_tree *mpc_tree_params; 433 struct mpcc_blnd_cfg blnd_cfg; 434 struct mpcc_sm_cfg *sm_cfg; 435 struct mpcc *insert_above_mpcc; 436 int dpp_id; 437 int mpcc_id; 438 }; 439 440 struct mpc_remove_mpcc_params { 441 struct mpc *mpc; 442 struct mpc_tree *mpc_tree_params; 443 struct mpcc *mpcc_to_remove; 444 }; 445 446 struct opp_set_mpcc_disconnect_pending_params { 447 struct output_pixel_processor *opp; 448 int mpcc_inst; 449 bool pending; 450 }; 451 452 struct dc_set_optimized_required_params { 453 struct dc *dc; 454 bool optimized_required; 455 }; 456 457 struct hubp_disconnect_params { 458 struct hubp *hubp; 459 }; 460 461 struct hubbub_force_pstate_change_control_params { 462 struct hubbub *hubbub; 463 bool enable; 464 bool wait; 465 }; 466 467 struct tg_enable_crtc_params { 468 struct timing_generator *tg; 469 }; 470 471 struct hubp_wait_flip_pending_params { 472 struct hubp *hubp; 473 unsigned int timeout_us; 474 unsigned int polling_interval_us; 475 }; 476 477 struct tg_wait_double_buffer_pending_params { 478 struct timing_generator *tg; 479 unsigned int timeout_us; 480 unsigned int polling_interval_us; 481 }; 482 483 struct update_force_pstate_params { 484 struct dc *dc; 485 struct dc_state *context; 486 }; 487 488 struct hubbub_apply_dedcn21_147_wa_params { 489 struct hubbub *hubbub; 490 }; 491 492 struct hubbub_allow_self_refresh_control_params { 493 struct hubbub *hubbub; 494 bool allow; 495 bool *disallow_self_refresh_applied; 496 }; 497 498 struct tg_get_frame_count_params { 499 struct timing_generator *tg; 500 unsigned int *frame_count; 501 }; 502 503 struct mpc_set_dwb_mux_params { 504 struct mpc *mpc; 505 int dwb_id; 506 int mpcc_id; 507 }; 508 509 struct mpc_disable_dwb_mux_params { 510 struct mpc *mpc; 511 unsigned int dwb_id; 512 }; 513 514 struct mcif_wb_config_buf_params { 515 struct mcif_wb *mcif_wb; 516 struct mcif_buf_params *mcif_buf_params; 517 unsigned int dest_height; 518 }; 519 520 struct mcif_wb_config_arb_params { 521 struct mcif_wb *mcif_wb; 522 struct mcif_arb_params *mcif_arb_params; 523 }; 524 525 struct mcif_wb_enable_params { 526 struct mcif_wb *mcif_wb; 527 }; 528 529 struct mcif_wb_disable_params { 530 struct mcif_wb *mcif_wb; 531 }; 532 533 struct dwbc_enable_params { 534 struct dwbc *dwb; 535 struct dc_dwb_params *dwb_params; 536 }; 537 538 struct dwbc_disable_params { 539 struct dwbc *dwb; 540 }; 541 542 struct dwbc_update_params { 543 struct dwbc *dwb; 544 struct dc_dwb_params *dwb_params; 545 }; 546 547 struct hubp_update_mall_sel_params { 548 struct hubp *hubp; 549 uint32_t mall_sel; 550 bool cache_cursor; 551 }; 552 553 struct hubp_prepare_subvp_buffering_params { 554 struct hubp *hubp; 555 bool enable; 556 }; 557 558 struct hubp_set_blank_en_params { 559 struct hubp *hubp; 560 bool enable; 561 }; 562 563 struct hubp_disable_control_params { 564 struct hubp *hubp; 565 bool disable; 566 }; 567 568 struct hubbub_soft_reset_params { 569 struct hubbub *hubbub; 570 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset); 571 bool reset; 572 }; 573 574 struct hubp_clk_cntl_params { 575 struct hubp *hubp; 576 bool enable; 577 }; 578 579 struct hubp_init_params { 580 struct hubp *hubp; 581 }; 582 583 struct hubp_set_vm_system_aperture_settings_params { 584 struct hubp *hubp; 585 //struct vm_system_aperture_param apt; 586 PHYSICAL_ADDRESS_LOC sys_default; 587 PHYSICAL_ADDRESS_LOC sys_low; 588 PHYSICAL_ADDRESS_LOC sys_high; 589 }; 590 591 struct hubp_set_flip_int_params { 592 struct hubp *hubp; 593 }; 594 595 struct dpp_dppclk_control_params { 596 struct dpp *dpp; 597 bool dppclk_div; 598 bool enable; 599 }; 600 601 struct disable_phantom_crtc_params { 602 struct timing_generator *tg; 603 }; 604 605 struct dpp_pg_control_params { 606 struct dce_hwseq *hws; 607 unsigned int dpp_inst; 608 bool power_on; 609 }; 610 611 struct hubp_pg_control_params { 612 struct dce_hwseq *hws; 613 unsigned int hubp_inst; 614 bool power_on; 615 }; 616 617 struct hubp_reset_params { 618 struct hubp *hubp; 619 }; 620 621 struct dpp_reset_params { 622 struct dpp *dpp; 623 }; 624 625 struct dpp_root_clock_control_params { 626 struct dce_hwseq *hws; 627 unsigned int dpp_inst; 628 bool clock_on; 629 }; 630 631 struct dc_ip_request_cntl_params { 632 struct dc *dc; 633 bool enable; 634 }; 635 636 struct dsc_pg_status_params { 637 struct dce_hwseq *hws; 638 int dsc_inst; 639 bool is_ungated; 640 }; 641 642 struct dsc_wait_disconnect_pending_clear_params { 643 struct display_stream_compressor *dsc; 644 bool *is_ungated; 645 }; 646 647 struct dsc_disable_params { 648 struct display_stream_compressor *dsc; 649 bool *is_ungated; 650 }; 651 652 struct dccg_set_ref_dscclk_params { 653 struct dccg *dccg; 654 int dsc_inst; 655 bool *is_ungated; 656 }; 657 658 struct dccg_update_dpp_dto_params { 659 struct dccg *dccg; 660 int dpp_inst; 661 int dppclk_khz; 662 }; 663 664 struct hubp_vtg_sel_params { 665 struct hubp *hubp; 666 uint32_t otg_inst; 667 }; 668 669 struct hubp_setup2_params { 670 struct hubp *hubp; 671 struct dml2_dchub_per_pipe_register_set *hubp_regs; 672 union dml2_global_sync_programming *global_sync; 673 struct dc_crtc_timing *timing; 674 }; 675 676 struct hubp_setup_params { 677 struct hubp *hubp; 678 struct _vcs_dpi_display_dlg_regs_st *dlg_regs; 679 struct _vcs_dpi_display_ttu_regs_st *ttu_regs; 680 struct _vcs_dpi_display_rq_regs_st *rq_regs; 681 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest; 682 }; 683 684 struct hubp_set_unbounded_requesting_params { 685 struct hubp *hubp; 686 bool unbounded_req; 687 }; 688 689 struct hubp_setup_interdependent2_params { 690 struct hubp *hubp; 691 struct dml2_dchub_per_pipe_register_set *hubp_regs; 692 }; 693 694 struct hubp_setup_interdependent_params { 695 struct hubp *hubp; 696 struct _vcs_dpi_display_dlg_regs_st *dlg_regs; 697 struct _vcs_dpi_display_ttu_regs_st *ttu_regs; 698 }; 699 700 struct dpp_set_cursor_matrix_params { 701 struct dpp *dpp; 702 enum dc_color_space color_space; 703 struct dc_csc_transform *cursor_csc_color_matrix; 704 }; 705 706 struct mpc_update_mpcc_params { 707 struct dc *dc; 708 struct pipe_ctx *pipe_ctx; 709 }; 710 711 struct dpp_set_scaler_params { 712 struct dpp *dpp; 713 const struct scaler_data *scl_data; 714 }; 715 716 struct hubp_mem_program_viewport_params { 717 struct hubp *hubp; 718 const struct rect *viewport; 719 const struct rect *viewport_c; 720 }; 721 722 struct hubp_program_mcache_id_and_split_coordinate_params { 723 struct hubp *hubp; 724 struct mcache_regs_struct *mcache_regs; 725 }; 726 727 struct abort_cursor_offload_update_params { 728 struct dc *dc; 729 struct pipe_ctx *pipe_ctx; 730 }; 731 732 struct cursor_lock_params { 733 struct dc *dc; 734 struct pipe_ctx *pipe_ctx; 735 bool lock; 736 }; 737 738 struct setup_periodic_interrupt_params { 739 struct dc *dc; 740 struct pipe_ctx *pipe_ctx; 741 }; 742 743 struct send_cursor_info_to_dmu_params { 744 struct pipe_ctx *pipe_ctx; 745 int pipe_idx; 746 }; 747 748 struct set_cursor_attribute_params { 749 struct dc *dc; 750 struct pipe_ctx *pipe_ctx; 751 }; 752 753 struct hubp_set_cursor_attributes_params { 754 struct hubp *hubp; 755 const struct dc_cursor_attributes *attributes; 756 }; 757 758 struct dpp_set_cursor_attributes_params { 759 struct dpp *dpp; 760 struct dc_cursor_attributes *attributes; 761 }; 762 763 struct set_cursor_position_params { 764 struct dc *dc; 765 struct pipe_ctx *pipe_ctx; 766 }; 767 768 struct set_cursor_sdr_white_level_params { 769 struct dc *dc; 770 struct pipe_ctx *pipe_ctx; 771 }; 772 773 struct program_output_csc_params { 774 struct dc *dc; 775 struct pipe_ctx *pipe_ctx; 776 enum dc_color_space colorspace; 777 uint16_t *matrix; 778 int opp_id; 779 }; 780 781 struct hubp_set_blank_params { 782 struct hubp *hubp; 783 bool blank; 784 }; 785 786 struct phantom_hubp_post_enable_params { 787 struct hubp *hubp; 788 }; 789 790 struct begin_cursor_offload_update_params { 791 struct dc *dc; 792 struct pipe_ctx *pipe_ctx; 793 }; 794 795 struct update_cursor_offload_pipe_params { 796 struct dc *dc; 797 struct pipe_ctx *pipe_ctx; 798 }; 799 800 struct commit_cursor_offload_update_params { 801 struct dc *dc; 802 struct pipe_ctx *pipe_ctx; 803 }; 804 805 struct stream_enc_update_hdmi_info_packets_params { 806 struct pipe_ctx *pipe_ctx; 807 }; 808 809 struct hpo_frl_stream_enc_update_hdmi_info_packets_params { 810 struct pipe_ctx *pipe_ctx; 811 }; 812 813 struct hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params { 814 struct pipe_ctx *pipe_ctx; 815 }; 816 817 struct hpo_dp_stream_enc_update_dp_info_packets_params { 818 struct pipe_ctx *pipe_ctx; 819 }; 820 821 struct stream_enc_update_dp_info_packets_sdp_line_num_params { 822 struct pipe_ctx *pipe_ctx; 823 }; 824 825 struct stream_enc_update_dp_info_packets_params { 826 struct pipe_ctx *pipe_ctx; 827 }; 828 829 struct dsc_set_config_simple_params { 830 struct display_stream_compressor *dsc; 831 struct dsc_config dsc_cfg; 832 struct dsc_optc_config dsc_optc_cfg; 833 }; 834 835 struct stream_enc_dp_set_dsc_config_params { 836 struct stream_encoder *stream_enc; 837 const struct dsc_optc_config *dsc_optc_cfg; 838 }; 839 840 struct hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params { 841 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 842 bool immediate_update; 843 uint8_t *dsc_packed_pps; 844 bool pps_sdp_stream; 845 }; 846 847 struct stream_enc_dp_set_dsc_pps_info_packet_params { 848 struct stream_encoder *stream_enc; 849 bool immediate_update; 850 uint8_t *dsc_packed_pps; 851 bool pps_sdp_stream; 852 }; 853 854 struct hpo_frl_stream_enc_set_dsc_config_params { 855 struct hpo_frl_stream_encoder *hpo_frl_stream_enc; 856 const struct dc_crtc_timing *timing; 857 uint8_t *dsc_packed_pps; 858 }; 859 860 struct dp_trace_source_sequence_params { 861 struct dc_link *link; 862 enum dpcd_source_sequence source; 863 }; 864 865 struct set_dmdata_attributes_params { 866 struct hubp *hubp; 867 struct dc_dmdata_attributes attr; 868 }; 869 870 struct link_increase_mst_payload_params { 871 struct pipe_ctx *pipe_ctx; 872 uint32_t mst_stream_bw; 873 }; 874 875 struct link_reduce_mst_payload_params { 876 struct pipe_ctx *pipe_ctx; 877 uint32_t mst_stream_bw; 878 }; 879 880 struct dp_set_test_pattern_params { 881 struct dc_link *link; 882 enum dp_test_pattern test_pattern; 883 enum dp_test_pattern_color_space test_pattern_color_space; 884 const struct link_training_settings *p_link_settings; 885 const unsigned char *p_custom_pattern; 886 unsigned int cust_pattern_size; 887 }; 888 889 struct link_set_dpms_off_params { 890 struct pipe_ctx *pipe_ctx; 891 }; 892 893 struct disable_audio_stream_params { 894 struct pipe_ctx *pipe_ctx; 895 }; 896 897 struct prepare_bandwidth_params { 898 struct dc *dc; 899 struct dc_state *context; 900 }; 901 902 struct link_set_dpms_on_params { 903 struct dc_state *state; 904 struct pipe_ctx *pipe_ctx; 905 }; 906 907 union block_sequence_params { 908 struct update_plane_addr_params update_plane_addr_params; 909 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 910 struct pipe_control_lock_params pipe_control_lock_params; 911 struct set_flip_control_gsl_params set_flip_control_gsl_params; 912 struct program_triplebuffer_params program_triplebuffer_params; 913 struct set_input_transfer_func_params set_input_transfer_func_params; 914 struct program_gamut_remap_params program_gamut_remap_params; 915 struct hubp_enable_3dlut_fl_params hubp_enable_3dlut_fl_params; 916 struct tg_setup_vertical_interrupt0_params tg_setup_vertical_interrupt0_params; 917 struct update_info_frame_params update_info_frame_params; 918 struct program_manual_trigger_params program_manual_trigger_params; 919 struct send_dmcub_cmd_params send_dmcub_cmd_params; 920 struct setup_dpp_params setup_dpp_params; 921 struct program_bias_and_scale_params program_bias_and_scale_params; 922 struct set_output_transfer_func_params set_output_transfer_func_params; 923 struct update_visual_confirm_params update_visual_confirm_params; 924 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 925 struct set_output_csc_params set_output_csc_params; 926 struct set_ocsc_default_params set_ocsc_default_params; 927 struct subvp_save_surf_addr subvp_save_surf_addr; 928 struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; 929 struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; 930 struct program_surface_config_params program_surface_config_params; 931 struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate; 932 struct control_cm_hist_params control_cm_hist_params; 933 struct program_cursor_update_now_params program_cursor_update_now_params; 934 struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params; 935 struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params; 936 struct update_phantom_vp_position_params update_phantom_vp_position_params; 937 struct set_odm_combine_params set_odm_combine_params; 938 struct set_odm_bypass_params set_odm_bypass_params; 939 struct opp_pipe_clock_control_params opp_pipe_clock_control_params; 940 struct opp_program_left_edge_extra_pixel_params opp_program_left_edge_extra_pixel_params; 941 struct dccg_set_dto_dscclk_params dccg_set_dto_dscclk_params; 942 struct dsc_set_config_params dsc_set_config_params; 943 struct dsc_enable_params dsc_enable_params; 944 struct tg_set_dsc_config_params tg_set_dsc_config_params; 945 struct dsc_disconnect_params dsc_disconnect_params; 946 struct dsc_read_state_params dsc_read_state_params; 947 struct dsc_calculate_and_set_config_params dsc_calculate_and_set_config_params; 948 struct dsc_enable_with_opp_params dsc_enable_with_opp_params; 949 struct program_tg_params program_tg_params; 950 struct tg_program_global_sync_params tg_program_global_sync_params; 951 struct tg_wait_for_state_params tg_wait_for_state_params; 952 struct tg_set_vtg_params_params tg_set_vtg_params_params; 953 struct tg_setup_vertical_interrupt2_params tg_setup_vertical_interrupt2_params; 954 struct dpp_set_hdr_multiplier_params dpp_set_hdr_multiplier_params; 955 struct tg_set_gsl_params tg_set_gsl_params; 956 struct tg_set_gsl_source_select_params tg_set_gsl_source_select_params; 957 struct setup_vupdate_interrupt_params setup_vupdate_interrupt_params; 958 struct program_det_size_params program_det_size_params; 959 struct program_det_segments_params program_det_segments_params; 960 struct update_dchubp_dpp_params update_dchubp_dpp_params; 961 struct opp_set_dyn_expansion_params opp_set_dyn_expansion_params; 962 struct opp_program_fmt_params opp_program_fmt_params; 963 struct opp_program_bit_depth_reduction_params opp_program_bit_depth_reduction_params; 964 struct opp_set_disp_pattern_generator_params opp_set_disp_pattern_generator_params; 965 struct set_abm_pipe_params set_abm_pipe_params; 966 struct set_abm_level_params set_abm_level_params; 967 struct set_abm_immediate_disable_params set_abm_immediate_disable_params; 968 struct set_disp_pattern_generator_params set_disp_pattern_generator_params; 969 struct mpc_remove_mpcc_params mpc_remove_mpcc_params; 970 struct opp_set_mpcc_disconnect_pending_params opp_set_mpcc_disconnect_pending_params; 971 struct dc_set_optimized_required_params dc_set_optimized_required_params; 972 struct hubp_disconnect_params hubp_disconnect_params; 973 struct hubbub_force_pstate_change_control_params hubbub_force_pstate_change_control_params; 974 struct tg_enable_crtc_params tg_enable_crtc_params; 975 struct hubp_wait_flip_pending_params hubp_wait_flip_pending_params; 976 struct tg_wait_double_buffer_pending_params tg_wait_double_buffer_pending_params; 977 struct update_force_pstate_params update_force_pstate_params; 978 struct hubbub_apply_dedcn21_147_wa_params hubbub_apply_dedcn21_147_wa_params; 979 struct hubbub_allow_self_refresh_control_params hubbub_allow_self_refresh_control_params; 980 struct tg_get_frame_count_params tg_get_frame_count_params; 981 struct mpc_set_dwb_mux_params mpc_set_dwb_mux_params; 982 struct mpc_disable_dwb_mux_params mpc_disable_dwb_mux_params; 983 struct mcif_wb_config_buf_params mcif_wb_config_buf_params; 984 struct mcif_wb_config_arb_params mcif_wb_config_arb_params; 985 struct mcif_wb_enable_params mcif_wb_enable_params; 986 struct mcif_wb_disable_params mcif_wb_disable_params; 987 struct dwbc_enable_params dwbc_enable_params; 988 struct dwbc_disable_params dwbc_disable_params; 989 struct dwbc_update_params dwbc_update_params; 990 struct hubp_update_mall_sel_params hubp_update_mall_sel_params; 991 struct hubp_prepare_subvp_buffering_params hubp_prepare_subvp_buffering_params; 992 struct hubp_set_blank_en_params hubp_set_blank_en_params; 993 struct hubp_disable_control_params hubp_disable_control_params; 994 struct hubbub_soft_reset_params hubbub_soft_reset_params; 995 struct hubp_clk_cntl_params hubp_clk_cntl_params; 996 struct hubp_init_params hubp_init_params; 997 struct hubp_set_vm_system_aperture_settings_params hubp_set_vm_system_aperture_settings_params; 998 struct hubp_set_flip_int_params hubp_set_flip_int_params; 999 struct dpp_dppclk_control_params dpp_dppclk_control_params; 1000 struct disable_phantom_crtc_params disable_phantom_crtc_params; 1001 struct dpp_pg_control_params dpp_pg_control_params; 1002 struct hubp_pg_control_params hubp_pg_control_params; 1003 struct hubp_reset_params hubp_reset_params; 1004 struct dpp_reset_params dpp_reset_params; 1005 struct dpp_root_clock_control_params dpp_root_clock_control_params; 1006 struct dc_ip_request_cntl_params dc_ip_request_cntl_params; 1007 struct dsc_pg_status_params dsc_pg_status_params; 1008 struct dsc_wait_disconnect_pending_clear_params dsc_wait_disconnect_pending_clear_params; 1009 struct dsc_disable_params dsc_disable_params; 1010 struct dccg_set_ref_dscclk_params dccg_set_ref_dscclk_params; 1011 struct dccg_update_dpp_dto_params dccg_update_dpp_dto_params; 1012 struct hubp_vtg_sel_params hubp_vtg_sel_params; 1013 struct hubp_setup2_params hubp_setup2_params; 1014 struct hubp_setup_params hubp_setup_params; 1015 struct hubp_set_unbounded_requesting_params hubp_set_unbounded_requesting_params; 1016 struct hubp_setup_interdependent2_params hubp_setup_interdependent2_params; 1017 struct hubp_setup_interdependent_params hubp_setup_interdependent_params; 1018 struct dpp_set_cursor_matrix_params dpp_set_cursor_matrix_params; 1019 struct mpc_update_mpcc_params mpc_update_mpcc_params; 1020 struct mpc_update_blending_params mpc_update_blending_params; 1021 struct mpc_assert_idle_mpcc_params mpc_assert_idle_mpcc_params; 1022 struct mpc_insert_plane_params mpc_insert_plane_params; 1023 struct dpp_set_scaler_params dpp_set_scaler_params; 1024 struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params; 1025 struct abort_cursor_offload_update_params abort_cursor_offload_update_params; 1026 struct cursor_lock_params cursor_lock_params; 1027 struct setup_periodic_interrupt_params setup_periodic_interrupt_params; 1028 struct send_cursor_info_to_dmu_params send_cursor_info_to_dmu_params; 1029 struct set_cursor_attribute_params set_cursor_attribute_params; 1030 struct hubp_set_cursor_attributes_params hubp_set_cursor_attributes_params; 1031 struct dpp_set_cursor_attributes_params dpp_set_cursor_attributes_params; 1032 struct set_cursor_position_params set_cursor_position_params; 1033 struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params; 1034 struct program_output_csc_params program_output_csc_params; 1035 struct hubp_set_blank_params hubp_set_blank_params; 1036 struct phantom_hubp_post_enable_params phantom_hubp_post_enable_params; 1037 struct begin_cursor_offload_update_params begin_cursor_offload_update_params; 1038 struct update_cursor_offload_pipe_params update_cursor_offload_pipe_params; 1039 struct commit_cursor_offload_update_params commit_cursor_offload_update_params; 1040 struct stream_enc_update_hdmi_info_packets_params stream_enc_update_hdmi_info_packets_params; 1041 struct hpo_frl_stream_enc_update_hdmi_info_packets_params hpo_frl_stream_enc_update_hdmi_info_packets_params; 1042 struct hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params; 1043 struct hpo_dp_stream_enc_update_dp_info_packets_params hpo_dp_stream_enc_update_dp_info_packets_params; 1044 struct stream_enc_update_dp_info_packets_sdp_line_num_params stream_enc_update_dp_info_packets_sdp_line_num_params; 1045 struct stream_enc_update_dp_info_packets_params stream_enc_update_dp_info_packets_params; 1046 struct dsc_set_config_simple_params dsc_set_config_simple_params; 1047 struct stream_enc_dp_set_dsc_config_params stream_enc_dp_set_dsc_config_params; 1048 struct hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params; 1049 struct stream_enc_dp_set_dsc_pps_info_packet_params stream_enc_dp_set_dsc_pps_info_packet_params; 1050 struct hpo_frl_stream_enc_set_dsc_config_params hpo_frl_stream_enc_set_dsc_config_params; 1051 struct dp_trace_source_sequence_params dp_trace_source_sequence_params; 1052 struct set_dmdata_attributes_params set_dmdata_attributes_params; 1053 struct link_increase_mst_payload_params link_increase_mst_payload_params; 1054 struct link_reduce_mst_payload_params link_reduce_mst_payload_params; 1055 struct dp_set_test_pattern_params dp_set_test_pattern_params; 1056 struct link_set_dpms_off_params link_set_dpms_off_params; 1057 struct disable_audio_stream_params disable_audio_stream_params; 1058 struct prepare_bandwidth_params prepare_bandwidth_params; 1059 struct link_set_dpms_on_params link_set_dpms_on_params; 1060 }; 1061 1062 enum block_sequence_func { 1063 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 1064 OPTC_PIPE_CONTROL_LOCK, 1065 HUBP_SET_FLIP_CONTROL_GSL, 1066 HUBP_PROGRAM_TRIPLEBUFFER, 1067 HUBP_UPDATE_PLANE_ADDR, 1068 DPP_SET_INPUT_TRANSFER_FUNC, 1069 DPP_PROGRAM_GAMUT_REMAP, 1070 HUBP_ENABLE_3DLUT_FL, 1071 OTG_SETUP_VERTICAL_INTERRUPT, 1072 HWSS_SETUP_PERIODIC_INTERRUPT, 1073 HWSS_UPDATE_INFO_FRAME, 1074 HUBP_SET_DMDATA_ATTRIBUTES, 1075 OPTC_PROGRAM_MANUAL_TRIGGER, 1076 DMUB_SEND_DMCUB_CMD, 1077 DPP_SETUP_DPP, 1078 DPP_PROGRAM_BIAS_AND_SCALE, 1079 DPP_SET_OUTPUT_TRANSFER_FUNC, 1080 DPP_SET_HDR_MULTIPLIER, 1081 MPC_UPDATE_VISUAL_CONFIRM, 1082 MPC_POWER_ON_MPC_MEM_PWR, 1083 MPC_SET_OUTPUT_CSC, 1084 MPC_SET_OCSC_DEFAULT, 1085 DMUB_SUBVP_SAVE_SURF_ADDR, 1086 HUBP_WAIT_FOR_DCC_META_PROP, 1087 DMUB_HW_CONTROL_LOCK_FAST, 1088 HUBP_PROGRAM_SURFACE_CONFIG, 1089 HUBP_PROGRAM_MCACHE_ID, 1090 DPP_PROGRAM_CM_HIST, 1091 PROGRAM_CURSOR_UPDATE_NOW, 1092 HUBP_WAIT_PIPE_READ_START, 1093 HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM, 1094 HWS_UPDATE_PHANTOM_VP_POSITION, 1095 OPTC_SET_ODM_COMBINE, 1096 OPTC_SET_ODM_BYPASS, 1097 OPP_PIPE_CLOCK_CONTROL, 1098 OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL, 1099 DCCG_SET_DTO_DSCCLK, 1100 DSC_SET_CONFIG, 1101 DSC_ENABLE, 1102 TG_SET_DSC_CONFIG, 1103 DSC_DISCONNECT, 1104 DSC_READ_STATE, 1105 DSC_CALCULATE_AND_SET_CONFIG, 1106 DSC_ENABLE_WITH_OPP, 1107 TG_PROGRAM_GLOBAL_SYNC, 1108 TG_WAIT_FOR_STATE, 1109 TG_SET_VTG_PARAMS, 1110 TG_SETUP_VERTICAL_INTERRUPT2, 1111 HUBP_PROGRAM_DET_SIZE, 1112 HUBP_PROGRAM_DET_SEGMENTS, 1113 OPP_SET_DYN_EXPANSION, 1114 OPP_PROGRAM_FMT, 1115 OPP_PROGRAM_BIT_DEPTH_REDUCTION, 1116 OPP_SET_DISP_PATTERN_GENERATOR, 1117 ABM_SET_PIPE, 1118 ABM_SET_LEVEL, 1119 ABM_SET_IMMEDIATE_DISABLE, 1120 MPC_REMOVE_MPCC, 1121 OPP_SET_MPCC_DISCONNECT_PENDING, 1122 DC_SET_OPTIMIZED_REQUIRED, 1123 HUBP_DISCONNECT, 1124 HUBBUB_FORCE_PSTATE_CHANGE_CONTROL, 1125 TG_ENABLE_CRTC, 1126 TG_SET_GSL, 1127 TG_SET_GSL_SOURCE_SELECT, 1128 HUBP_WAIT_FLIP_PENDING, 1129 TG_WAIT_DOUBLE_BUFFER_PENDING, 1130 UPDATE_FORCE_PSTATE, 1131 PROGRAM_MALL_PIPE_CONFIG, 1132 HUBBUB_APPLY_DEDCN21_147_WA, 1133 HUBBUB_ALLOW_SELF_REFRESH_CONTROL, 1134 TG_GET_FRAME_COUNT, 1135 MPC_SET_DWB_MUX, 1136 MPC_DISABLE_DWB_MUX, 1137 MCIF_WB_CONFIG_BUF, 1138 MCIF_WB_CONFIG_ARB, 1139 MCIF_WB_ENABLE, 1140 MCIF_WB_DISABLE, 1141 DWBC_ENABLE, 1142 DWBC_DISABLE, 1143 DWBC_UPDATE, 1144 HUBP_UPDATE_MALL_SEL, 1145 HUBP_PREPARE_SUBVP_BUFFERING, 1146 HUBP_SET_BLANK_EN, 1147 HUBP_DISABLE_CONTROL, 1148 HUBBUB_SOFT_RESET, 1149 HUBP_CLK_CNTL, 1150 HUBP_INIT, 1151 HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS, 1152 HUBP_SET_FLIP_INT, 1153 DPP_DPPCLK_CONTROL, 1154 DISABLE_PHANTOM_CRTC, 1155 DSC_PG_STATUS, 1156 DSC_WAIT_DISCONNECT_PENDING_CLEAR, 1157 DSC_DISABLE, 1158 DCCG_SET_REF_DSCCLK, 1159 DPP_PG_CONTROL, 1160 HUBP_PG_CONTROL, 1161 HUBP_RESET, 1162 DPP_RESET, 1163 DPP_ROOT_CLOCK_CONTROL, 1164 DC_IP_REQUEST_CNTL, 1165 DCCG_UPDATE_DPP_DTO, 1166 HUBP_VTG_SEL, 1167 HUBP_SETUP2, 1168 HUBP_SETUP, 1169 HUBP_SET_UNBOUNDED_REQUESTING, 1170 HUBP_SETUP_INTERDEPENDENT2, 1171 HUBP_SETUP_INTERDEPENDENT, 1172 DPP_SET_CURSOR_MATRIX, 1173 MPC_UPDATE_BLENDING, 1174 MPC_ASSERT_IDLE_MPCC, 1175 MPC_INSERT_PLANE, 1176 DPP_SET_SCALER, 1177 HUBP_MEM_PROGRAM_VIEWPORT, 1178 ABORT_CURSOR_OFFLOAD_UPDATE, 1179 HWSS_CURSOR_LOCK, 1180 HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE, 1181 HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE, 1182 HWSS_UPDATE_CURSOR_OFFLOAD_PIPE, 1183 DC_SEND_CURSOR_INFO_TO_DMU, 1184 SET_CURSOR_ATTRIBUTE, 1185 HUBP_SET_CURSOR_ATTRIBUTES, 1186 DPP_SET_CURSOR_ATTRIBUTES, 1187 SET_CURSOR_POSITION, 1188 SET_CURSOR_SDR_WHITE_LEVEL, 1189 PROGRAM_OUTPUT_CSC, 1190 HUBP_SET_LEGACY_TILING_COMPAT_LEVEL, 1191 HUBP_SET_BLANK, 1192 PHANTOM_HUBP_POST_ENABLE, 1193 STREAM_ENC_UPDATE_HDMI_INFO_PACKETS, 1194 HPO_FRL_STREAM_ENC_UPDATE_HDMI_INFO_PACKETS, 1195 HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM, 1196 HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS, 1197 STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM, 1198 STREAM_ENC_UPDATE_DP_INFO_PACKETS, 1199 DSC_SET_CONFIG_SIMPLE, 1200 STREAM_ENC_DP_SET_DSC_CONFIG, 1201 HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET, 1202 STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET, 1203 HPO_FRL_STREAM_ENC_SET_DSC_CONFIG, 1204 LINK_INCREASE_MST_PAYLOAD, 1205 LINK_REDUCE_MST_PAYLOAD, 1206 DP_TRACE_SOURCE_SEQUENCE, 1207 DP_SET_TEST_PATTERN, 1208 LINK_SET_DPMS_OFF, 1209 DISABLE_AUDIO_STREAM, 1210 PREPARE_BANDWIDTH, 1211 LINK_SET_DPMS_ON, 1212 /* This must be the last value in this enum, add new ones above */ 1213 HWSS_BLOCK_SEQUENCE_FUNC_COUNT 1214 }; 1215 1216 struct block_sequence { 1217 union block_sequence_params params; 1218 enum block_sequence_func func; 1219 }; 1220 1221 struct block_sequence_state { 1222 struct block_sequence *steps; 1223 unsigned int *num_steps; 1224 }; 1225 1226 #define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES) 1227 1228 struct hw_sequencer_funcs { 1229 void (*hardware_release)(struct dc *dc); 1230 /* Embedded Display Related */ 1231 void (*edp_power_control)(struct dc_link *link, bool enable); 1232 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 1233 void (*edp_wait_for_T12)(struct dc_link *link); 1234 1235 /* Pipe Programming Related */ 1236 void (*init_hw)(struct dc *dc); 1237 void (*power_down_on_boot)(struct dc *dc); 1238 void (*enable_accelerated_mode)(struct dc *dc, 1239 struct dc_state *context); 1240 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 1241 struct dc_state *context); 1242 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 1243 void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx, 1244 struct block_sequence_state *seq_state); 1245 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 1246 void (*apply_ctx_for_surface)(struct dc *dc, 1247 const struct dc_stream_state *stream, 1248 int num_planes, struct dc_state *context); 1249 void (*program_front_end_for_ctx)(struct dc *dc, 1250 struct dc_state *context); 1251 void (*wait_for_pending_cleared)(struct dc *dc, 1252 struct dc_state *context); 1253 void (*post_unlock_program_front_end)(struct dc *dc, 1254 struct dc_state *context); 1255 void (*update_plane_addr)(const struct dc *dc, 1256 struct pipe_ctx *pipe_ctx); 1257 void (*update_dchub)(struct dce_hwseq *hws, 1258 struct dchub_init_data *dh_data); 1259 void (*wait_for_mpcc_disconnect)(struct dc *dc, 1260 struct resource_pool *res_pool, 1261 struct pipe_ctx *pipe_ctx); 1262 void (*wait_for_mpcc_disconnect_sequence)(struct dc *dc, 1263 struct resource_pool *res_pool, 1264 struct pipe_ctx *pipe_ctx, 1265 struct block_sequence_state *seq_state); 1266 void (*edp_backlight_control)( 1267 struct dc_link *link, 1268 bool enable); 1269 void (*program_triplebuffer)(const struct dc *dc, 1270 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 1271 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 1272 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 1273 void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); 1274 1275 /* Pipe Lock Related */ 1276 void (*pipe_control_lock)(struct dc *dc, 1277 struct pipe_ctx *pipe, bool lock); 1278 void (*interdependent_update_lock)(struct dc *dc, 1279 struct dc_state *context, bool lock); 1280 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 1281 bool flip_immediate); 1282 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 1283 1284 /* Timing Related */ 1285 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 1286 struct crtc_position *position); 1287 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 1288 void (*calc_vupdate_position)( 1289 struct dc *dc, 1290 struct pipe_ctx *pipe_ctx, 1291 uint32_t *start_line, 1292 uint32_t *end_line); 1293 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 1294 int group_size, struct pipe_ctx *grouped_pipes[]); 1295 void (*enable_timing_synchronization)(struct dc *dc, 1296 struct dc_state *state, 1297 int group_index, int group_size, 1298 struct pipe_ctx *grouped_pipes[]); 1299 void (*enable_vblanks_synchronization)(struct dc *dc, 1300 int group_index, int group_size, 1301 struct pipe_ctx *grouped_pipes[]); 1302 void (*setup_periodic_interrupt)(struct dc *dc, 1303 struct pipe_ctx *pipe_ctx); 1304 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 1305 struct dc_crtc_timing_adjust adjust); 1306 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 1307 int num_pipes, 1308 const struct dc_static_screen_params *events); 1309 1310 /* Stream Related */ 1311 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 1312 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 1313 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 1314 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 1315 struct dc_link_settings *link_settings); 1316 1317 /* Bandwidth Related */ 1318 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 1319 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 1320 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 1321 1322 /* Infopacket Related */ 1323 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 1324 void (*send_immediate_sdp_message)( 1325 struct pipe_ctx *pipe_ctx, 1326 const uint8_t *custom_sdp_message, 1327 unsigned int sdp_message_size); 1328 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 1329 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 1330 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 1331 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 1332 1333 /* Cursor Related */ 1334 void (*set_cursor_position)(struct pipe_ctx *pipe); 1335 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 1336 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 1337 void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1338 void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1339 void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1340 void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe); 1341 void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context, 1342 const struct dc_stream_state *stream); 1343 void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe); 1344 1345 /* Colour Related */ 1346 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 1347 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 1348 enum dc_color_space colorspace, 1349 uint16_t *matrix, int opp_id); 1350 void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 1351 1352 /* VM Related */ 1353 int (*init_sys_ctx)(struct dce_hwseq *hws, 1354 struct dc *dc, 1355 struct dc_phy_addr_space_config *pa_config); 1356 void (*init_vm_ctx)(struct dce_hwseq *hws, 1357 struct dc *dc, 1358 struct dc_virtual_addr_space_config *va_config, 1359 int vmid); 1360 1361 /* Writeback Related */ 1362 void (*update_writeback)(struct dc *dc, 1363 struct dc_writeback_info *wb_info, 1364 struct dc_state *context); 1365 void (*enable_writeback)(struct dc *dc, 1366 struct dc_writeback_info *wb_info, 1367 struct dc_state *context); 1368 void (*disable_writeback)(struct dc *dc, 1369 unsigned int dwb_pipe_inst); 1370 1371 /* Clock Related */ 1372 enum dc_status (*set_clock)(struct dc *dc, 1373 enum dc_clock_type clock_type, 1374 uint32_t clk_khz, uint32_t stepping); 1375 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 1376 struct dc_clock_config *clock_cfg); 1377 void (*optimize_pwr_state)(const struct dc *dc, 1378 struct dc_state *context); 1379 void (*exit_optimized_pwr_state)(const struct dc *dc, 1380 struct dc_state *context); 1381 void (*calculate_pix_rate_divider)(struct dc *dc, 1382 struct dc_state *context, 1383 const struct dc_stream_state *stream); 1384 1385 /* Audio Related */ 1386 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 1387 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 1388 1389 /* Stereo 3D Related */ 1390 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 1391 1392 /* HW State Logging Related */ 1393 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 1394 void (*log_color_state)(struct dc *dc, 1395 struct dc_log_buffer_ctx *log_ctx); 1396 void (*get_hw_state)(struct dc *dc, char *pBuf, 1397 unsigned int bufSize, unsigned int mask); 1398 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 1399 1400 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 1401 struct set_backlight_level_params *params); 1402 1403 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 1404 1405 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 1406 1407 void (*enable_dp_link_output)(struct dc_link *link, 1408 const struct link_resource *link_res, 1409 enum signal_type signal, 1410 enum clock_source_id clock_source, 1411 const struct dc_link_settings *link_settings); 1412 void (*enable_tmds_link_output)(struct dc_link *link, 1413 const struct link_resource *link_res, 1414 enum signal_type signal, 1415 enum clock_source_id clock_source, 1416 enum dc_color_depth color_depth, 1417 uint32_t pixel_clock); 1418 void (*enable_lvds_link_output)(struct dc_link *link, 1419 const struct link_resource *link_res, 1420 enum clock_source_id clock_source, 1421 uint32_t pixel_clock); 1422 void (*enable_analog_link_output)(struct dc_link *link, 1423 uint32_t pixel_clock); 1424 void (*disable_link_output)(struct dc_link *link, 1425 const struct link_resource *link_res, 1426 enum signal_type signal); 1427 bool (*dac_load_detect)(struct dc_link *link); 1428 void (*prepare_ddc)(struct dc_link *link); 1429 1430 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 1431 1432 enum dc_status (*setup_hdmi_frl_link)( 1433 struct dc_link *link, 1434 int hpo_inst, 1435 enum clock_source_id frl_phy_clock_source_id); 1436 1437 unsigned int (*get_max_dispclk_mhz)(struct dc *dc, 1438 struct dc_state *context); 1439 1440 /* Idle Optimization Related */ 1441 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 1442 1443 bool (*does_plane_fit_in_mall)(struct dc *dc, 1444 unsigned int pitch, 1445 unsigned int height, 1446 enum surface_pixel_format format, 1447 struct dc_cursor_attributes *cursor_attr); 1448 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 1449 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 1450 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 1451 void (*subvp_pipe_control_lock)(struct dc *dc, 1452 struct dc_state *context, 1453 bool lock, 1454 bool should_lock_all_pipes, 1455 struct pipe_ctx *top_pipe_to_program, 1456 bool subvp_prev_use); 1457 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 1458 1459 void (*z10_restore)(const struct dc *dc); 1460 void (*z10_save_init)(struct dc *dc); 1461 bool (*is_abm_supported)(struct dc *dc, 1462 struct dc_state *context, struct dc_stream_state *stream); 1463 1464 void (*set_disp_pattern_generator)(const struct dc *dc, 1465 struct pipe_ctx *pipe_ctx, 1466 enum controller_dp_test_pattern test_pattern, 1467 enum controller_dp_color_space color_space, 1468 enum dc_color_depth color_depth, 1469 const struct tg_color *solid_color, 1470 int width, int height, int offset); 1471 void (*blank_phantom)(struct dc *dc, 1472 struct timing_generator *tg, 1473 int width, 1474 int height); 1475 void (*update_visual_confirm_color)(struct dc *dc, 1476 struct pipe_ctx *pipe_ctx, 1477 int mpcc_id); 1478 void (*update_phantom_vp_position)(struct dc *dc, 1479 struct dc_state *context, 1480 struct pipe_ctx *phantom_pipe); 1481 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 1482 1483 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 1484 struct pg_block_update *update_state); 1485 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 1486 struct pg_block_update *update_state); 1487 void (*hw_block_power_up)(struct dc *dc, 1488 struct pg_block_update *update_state); 1489 void (*hw_block_power_down)(struct dc *dc, 1490 struct pg_block_update *update_state); 1491 void (*root_clock_control)(struct dc *dc, 1492 struct pg_block_update *update_state, bool power_on); 1493 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 1494 const struct dc_state *cur_ctx, 1495 const struct dc_state *new_ctx); 1496 void (*wait_for_dcc_meta_propagation)(const struct dc *dc, 1497 const struct pipe_ctx *top_pipe_to_program); 1498 void (*dmub_hw_control_lock)(struct dc *dc, 1499 struct dc_state *context, 1500 bool lock); 1501 void (*fams2_update_config)(struct dc *dc, 1502 struct dc_state *context, 1503 bool enable); 1504 void (*dmub_hw_control_lock_fast)(union block_sequence_params *params); 1505 void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); 1506 void (*program_outstanding_updates)(struct dc *dc, 1507 struct dc_state *context); 1508 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); 1509 void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); 1510 void (*detect_pipe_changes)(struct dc_state *old_state, 1511 struct dc_state *new_state, 1512 struct pipe_ctx *old_pipe, 1513 struct pipe_ctx *new_pipe); 1514 void (*enable_plane)(struct dc *dc, 1515 struct pipe_ctx *pipe_ctx, 1516 struct dc_state *context); 1517 void (*enable_plane_sequence)(struct dc *dc, 1518 struct pipe_ctx *pipe_ctx, 1519 struct dc_state *context, 1520 struct block_sequence_state *seq_state); 1521 void (*update_dchubp_dpp)(struct dc *dc, 1522 struct pipe_ctx *pipe_ctx, 1523 struct dc_state *context); 1524 void (*update_dchubp_dpp_sequence)(struct dc *dc, 1525 struct pipe_ctx *pipe_ctx, 1526 struct dc_state *context, 1527 struct block_sequence_state *seq_state); 1528 void (*post_unlock_reset_opp)(struct dc *dc, 1529 struct pipe_ctx *opp_head); 1530 void (*post_unlock_reset_opp_sequence)( 1531 struct dc *dc, 1532 struct pipe_ctx *opp_head, 1533 struct block_sequence_state *seq_state); 1534 void (*get_underflow_debug_data)(const struct dc *dc, 1535 struct timing_generator *tg, 1536 struct dc_underflow_debug_data *out_data); 1537 1538 /** 1539 * measure_memory_qos - Measure memory QoS metrics 1540 * @dc: DC structure 1541 * @qos: Pointer to dc_measured_memory_qos struct to populate with measured values 1542 * 1543 * Populates the provided dc_measured_memory_qos struct with peak bandwidth, average bandwidth, 1544 * max latency, min latency, and average latency from hardware performance counters. 1545 */ 1546 void (*measure_memory_qos)(struct dc *dc, struct dc_measured_memory_qos *qos); 1547 1548 }; 1549 1550 void color_space_to_black_color( 1551 const struct dc *dc, 1552 enum dc_color_space colorspace, 1553 struct tg_color *black_color); 1554 1555 bool hwss_wait_for_blank_complete( 1556 struct timing_generator *tg); 1557 1558 const uint16_t *find_color_matrix( 1559 enum dc_color_space color_space, 1560 uint32_t *array_size); 1561 1562 void get_surface_tile_visual_confirm_color( 1563 struct pipe_ctx *pipe_ctx, 1564 struct tg_color *color); 1565 void get_surface_visual_confirm_color( 1566 const struct pipe_ctx *pipe_ctx, 1567 struct tg_color *color); 1568 1569 void get_hdr_visual_confirm_color( 1570 struct pipe_ctx *pipe_ctx, 1571 struct tg_color *color); 1572 void get_mpctree_visual_confirm_color( 1573 struct pipe_ctx *pipe_ctx, 1574 struct tg_color *color); 1575 void get_smartmux_visual_confirm_color( 1576 struct dc *dc, 1577 struct tg_color *color); 1578 void get_vabc_visual_confirm_color( 1579 struct pipe_ctx *pipe_ctx, 1580 struct tg_color *color); 1581 void get_subvp_visual_confirm_color( 1582 struct pipe_ctx *pipe_ctx, 1583 struct tg_color *color); 1584 void get_fams2_visual_confirm_color( 1585 struct dc *dc, 1586 struct dc_state *context, 1587 struct pipe_ctx *pipe_ctx, 1588 struct tg_color *color); 1589 1590 void get_mclk_switch_visual_confirm_color( 1591 struct pipe_ctx *pipe_ctx, 1592 struct tg_color *color); 1593 1594 void get_cursor_visual_confirm_color( 1595 struct pipe_ctx *pipe_ctx, 1596 struct tg_color *color); 1597 1598 void get_dcc_visual_confirm_color( 1599 struct dc *dc, 1600 struct pipe_ctx *pipe_ctx, 1601 struct tg_color *color); 1602 1603 void get_refresh_rate_confirm_color( 1604 struct pipe_ctx *pipe_ctx, 1605 struct tg_color *color); 1606 1607 void set_p_state_switch_method( 1608 struct dc *dc, 1609 struct dc_state *context, 1610 struct pipe_ctx *pipe_ctx); 1611 1612 void set_drr_and_clear_adjust_pending( 1613 struct pipe_ctx *pipe_ctx, 1614 struct dc_stream_state *stream, 1615 struct drr_params *params); 1616 1617 void hwss_execute_sequence(struct dc *dc, 1618 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 1619 int num_steps); 1620 1621 void hwss_build_fast_sequence(struct dc *dc, 1622 struct dc_dmub_cmd *dc_dmub_cmd, 1623 unsigned int dmub_cmd_count, 1624 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 1625 unsigned int *num_steps, 1626 struct pipe_ctx *pipe_ctx, 1627 struct dc_stream_status *stream_status, 1628 struct dc_state *context); 1629 1630 void hwss_wait_for_all_blank_complete(struct dc *dc, 1631 struct dc_state *context); 1632 1633 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, 1634 struct dc_state *context); 1635 1636 void hwss_wait_for_no_pipes_pending(struct dc *dc, 1637 struct dc_state *context); 1638 1639 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, 1640 struct dc_state *dc_context); 1641 1642 void hwss_process_outstanding_hw_updates(struct dc *dc, 1643 struct dc_state *dc_context); 1644 1645 void hwss_send_dmcub_cmd(union block_sequence_params *params); 1646 1647 void hwss_program_manual_trigger(union block_sequence_params *params); 1648 1649 void hwss_setup_dpp(union block_sequence_params *params); 1650 1651 void hwss_program_bias_and_scale(union block_sequence_params *params); 1652 1653 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 1654 1655 void hwss_set_output_csc(union block_sequence_params *params); 1656 1657 void hwss_set_ocsc_default(union block_sequence_params *params); 1658 1659 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 1660 1661 void hwss_program_surface_config(union block_sequence_params *params); 1662 1663 void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params); 1664 1665 void hwss_program_cm_hist(union block_sequence_params *params); 1666 1667 void hwss_set_odm_combine(union block_sequence_params *params); 1668 1669 void hwss_set_odm_bypass(union block_sequence_params *params); 1670 1671 void hwss_opp_pipe_clock_control(union block_sequence_params *params); 1672 1673 void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params); 1674 1675 void hwss_blank_pixel_data(union block_sequence_params *params); 1676 1677 void hwss_dccg_set_dto_dscclk(union block_sequence_params *params); 1678 1679 void hwss_dsc_set_config(union block_sequence_params *params); 1680 1681 void hwss_dsc_enable(union block_sequence_params *params); 1682 1683 void hwss_tg_set_dsc_config(union block_sequence_params *params); 1684 1685 void hwss_dsc_disconnect(union block_sequence_params *params); 1686 1687 void hwss_dsc_read_state(union block_sequence_params *params); 1688 1689 void hwss_dsc_calculate_and_set_config(union block_sequence_params *params); 1690 1691 void hwss_dsc_enable_with_opp(union block_sequence_params *params); 1692 1693 void hwss_dsc_set_config_simple(union block_sequence_params *params); 1694 1695 void hwss_stream_enc_update_hdmi_info_packets(union block_sequence_params *params); 1696 1697 void hwss_hpo_frl_stream_enc_update_hdmi_info_packets(union block_sequence_params *params); 1698 1699 void hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params); 1700 1701 void hwss_hpo_dp_stream_enc_update_dp_info_packets(union block_sequence_params *params); 1702 1703 void hwss_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params); 1704 1705 void hwss_stream_enc_update_dp_info_packets(union block_sequence_params *params); 1706 1707 void hwss_stream_enc_dp_set_dsc_config(union block_sequence_params *params); 1708 1709 void hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params); 1710 1711 void hwss_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params); 1712 1713 void hwss_hpo_frl_stream_enc_set_dsc_config(union block_sequence_params *params); 1714 1715 void hwss_set_dmdata_attributes(union block_sequence_params *params); 1716 1717 void hwss_dp_trace_source_sequence(union block_sequence_params *params); 1718 1719 void hwss_link_increase_mst_payload(union block_sequence_params *params); 1720 1721 void hwss_link_reduce_mst_payload(union block_sequence_params *params); 1722 1723 void hwss_dp_set_test_pattern(union block_sequence_params *params); 1724 1725 void hwss_link_set_dpms_off(union block_sequence_params *params); 1726 1727 void hwss_prepare_bandwidth(struct dc *dc, union block_sequence_params *params); 1728 1729 void hwss_link_set_dpms_on(union block_sequence_params *params); 1730 1731 void hwss_program_tg(union block_sequence_params *params); 1732 1733 void hwss_tg_program_global_sync(union block_sequence_params *params); 1734 1735 void hwss_tg_wait_for_state(union block_sequence_params *params); 1736 1737 void hwss_tg_set_vtg_params(union block_sequence_params *params); 1738 1739 void hwss_hubp_enable_3dlut_fl(union block_sequence_params *params); 1740 1741 void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params); 1742 1743 void hwss_tg_setup_vertical_interrupt0(union block_sequence_params *params); 1744 1745 void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params); 1746 1747 void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params); 1748 1749 void hwss_program_det_size(union block_sequence_params *params); 1750 1751 void hwss_program_det_segments(union block_sequence_params *params); 1752 1753 void hwss_opp_set_dyn_expansion(union block_sequence_params *params); 1754 1755 void hwss_opp_program_fmt(union block_sequence_params *params); 1756 1757 void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params); 1758 1759 void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params); 1760 1761 void hwss_set_abm_pipe(union block_sequence_params *params); 1762 1763 void hwss_set_abm_level(union block_sequence_params *params); 1764 1765 void hwss_set_abm_immediate_disable(union block_sequence_params *params); 1766 1767 void hwss_mpc_remove_mpcc(union block_sequence_params *params); 1768 1769 void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params); 1770 1771 void hwss_dc_set_optimized_required(union block_sequence_params *params); 1772 1773 void hwss_hubp_disconnect(union block_sequence_params *params); 1774 1775 void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params); 1776 1777 void hwss_tg_enable_crtc(union block_sequence_params *params); 1778 1779 void hwss_tg_set_gsl(union block_sequence_params *params); 1780 1781 void hwss_tg_set_gsl_source_select(union block_sequence_params *params); 1782 1783 void hwss_hubp_wait_flip_pending(union block_sequence_params *params); 1784 1785 void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params); 1786 1787 void hwss_update_force_pstate(union block_sequence_params *params); 1788 1789 void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params); 1790 1791 void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params); 1792 1793 void hwss_tg_get_frame_count(union block_sequence_params *params); 1794 1795 void hwss_mpc_set_dwb_mux(union block_sequence_params *params); 1796 1797 void hwss_mpc_disable_dwb_mux(union block_sequence_params *params); 1798 1799 void hwss_mcif_wb_config_buf(union block_sequence_params *params); 1800 1801 void hwss_mcif_wb_config_arb(union block_sequence_params *params); 1802 1803 void hwss_mcif_wb_enable(union block_sequence_params *params); 1804 1805 void hwss_mcif_wb_disable(union block_sequence_params *params); 1806 1807 void hwss_dwbc_enable(union block_sequence_params *params); 1808 1809 void hwss_dwbc_disable(union block_sequence_params *params); 1810 1811 void hwss_dwbc_update(union block_sequence_params *params); 1812 1813 void hwss_hubp_update_mall_sel(union block_sequence_params *params); 1814 1815 void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params); 1816 1817 void hwss_hubp_set_blank_en(union block_sequence_params *params); 1818 1819 void hwss_hubp_disable_control(union block_sequence_params *params); 1820 1821 void hwss_hubbub_soft_reset(union block_sequence_params *params); 1822 1823 void hwss_hubp_clk_cntl(union block_sequence_params *params); 1824 1825 void hwss_hubp_init(union block_sequence_params *params); 1826 1827 void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params); 1828 1829 void hwss_hubp_set_flip_int(union block_sequence_params *params); 1830 1831 void hwss_dpp_dppclk_control(union block_sequence_params *params); 1832 1833 void hwss_disable_phantom_crtc(union block_sequence_params *params); 1834 1835 void hwss_dsc_pg_status(union block_sequence_params *params); 1836 1837 void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params); 1838 1839 void hwss_dsc_disable(union block_sequence_params *params); 1840 1841 void hwss_dccg_set_ref_dscclk(union block_sequence_params *params); 1842 1843 void hwss_dpp_pg_control(union block_sequence_params *params); 1844 1845 void hwss_hubp_pg_control(union block_sequence_params *params); 1846 1847 void hwss_hubp_reset(union block_sequence_params *params); 1848 1849 void hwss_dpp_reset(union block_sequence_params *params); 1850 1851 void hwss_dpp_root_clock_control(union block_sequence_params *params); 1852 1853 void hwss_dc_ip_request_cntl(union block_sequence_params *params); 1854 1855 void hwss_dccg_update_dpp_dto(union block_sequence_params *params); 1856 1857 void hwss_hubp_vtg_sel(union block_sequence_params *params); 1858 1859 void hwss_hubp_setup2(union block_sequence_params *params); 1860 1861 void hwss_hubp_setup(union block_sequence_params *params); 1862 1863 void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params); 1864 1865 void hwss_hubp_setup_interdependent2(union block_sequence_params *params); 1866 1867 void hwss_hubp_setup_interdependent(union block_sequence_params *params); 1868 1869 void hwss_dpp_set_cursor_matrix(union block_sequence_params *params); 1870 1871 void hwss_mpc_update_mpcc(union block_sequence_params *params); 1872 1873 void hwss_mpc_update_blending(union block_sequence_params *params); 1874 1875 void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params); 1876 1877 void hwss_mpc_insert_plane(union block_sequence_params *params); 1878 1879 void hwss_dpp_set_scaler(union block_sequence_params *params); 1880 1881 void hwss_hubp_mem_program_viewport(union block_sequence_params *params); 1882 1883 void hwss_abort_cursor_offload_update(union block_sequence_params *params); 1884 1885 void hwss_send_cursor_info_to_dmu(union block_sequence_params *params); 1886 1887 void hwss_set_cursor_attribute(union block_sequence_params *params); 1888 1889 void hwss_hubp_set_cursor_attributes(union block_sequence_params *params); 1890 1891 void hwss_dpp_set_cursor_attributes(union block_sequence_params *params); 1892 1893 void hwss_set_cursor_position(union block_sequence_params *params); 1894 1895 void hwss_set_cursor_sdr_white_level(union block_sequence_params *params); 1896 1897 void hwss_program_gamut_remap(union block_sequence_params *params); 1898 1899 void hwss_program_output_csc(union block_sequence_params *params); 1900 1901 void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params); 1902 1903 void hwss_hubp_set_blank(union block_sequence_params *params); 1904 1905 void hwss_phantom_hubp_post_enable(union block_sequence_params *params); 1906 1907 void hwss_cursor_lock(union block_sequence_params *params); 1908 1909 void hwss_begin_cursor_offload_update(union block_sequence_params *params); 1910 1911 void hwss_commit_cursor_offload_update(union block_sequence_params *params); 1912 1913 void hwss_update_cursor_offload_pipe(union block_sequence_params *params); 1914 1915 void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params); 1916 1917 void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params); 1918 1919 void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, 1920 struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock); 1921 1922 void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, 1923 struct hubp *hubp, bool flip_immediate); 1924 1925 void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state, 1926 struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 1927 1928 void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, 1929 struct dc *dc, struct pipe_ctx *pipe_ctx); 1930 1931 void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state, 1932 struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state); 1933 1934 void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, 1935 struct pipe_ctx *pipe_ctx); 1936 1937 void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, 1938 struct pipe_ctx *pipe_ctx); 1939 1940 void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state, 1941 struct pipe_ctx *pipe_ctx); 1942 1943 void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state, 1944 struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream); 1945 1946 void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state, 1947 struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id); 1948 1949 void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state, 1950 struct mpc *mpc, int mpcc_id, bool power_on); 1951 1952 void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state, 1953 struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); 1954 1955 void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state, 1956 struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode); 1957 1958 void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, 1959 struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 1960 1961 void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, 1962 struct dc_dmub_srv *dc_dmub_srv, struct dc_plane_address *addr, uint8_t subvp_index); 1963 1964 void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, 1965 struct dc *dc, struct pipe_ctx *top_pipe_to_program); 1966 1967 void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, 1968 struct hubp *hubp); 1969 1970 void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state, 1971 struct pipe_ctx *pipe_ctx); 1972 1973 void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state, 1974 struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 1975 1976 void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state, 1977 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, 1978 int odm_slice_width, int last_odm_slice_width); 1979 1980 void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state, 1981 struct timing_generator *optc, struct dc_crtc_timing *timing); 1982 1983 void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state, 1984 struct timing_generator *tg, 1985 int vready_offset, 1986 unsigned int vstartup_lines, 1987 unsigned int vupdate_offset_pixels, 1988 unsigned int vupdate_vupdate_width_pixels, 1989 unsigned int pstate_keepout_start_lines); 1990 1991 void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, 1992 struct timing_generator *tg, enum crtc_state state); 1993 1994 void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, 1995 struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 1996 1997 void hwss_add_vertical_interrupt_setup(struct block_sequence_state *seq_state, 1998 struct timing_generator *tg, uint32_t start_line, uint32_t end_line); 1999 2000 void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, 2001 struct timing_generator *tg, int start_line); 2002 2003 void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state, 2004 struct dpp *dpp, uint32_t hw_mult); 2005 2006 void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state, 2007 struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_buffer_size_kb); 2008 2009 void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state, 2010 struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); 2011 2012 void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state, 2013 struct hubbub *hubbub, bool enable, bool wait); 2014 2015 void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state, 2016 struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_size); 2017 2018 void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state, 2019 struct output_pixel_processor *opp, enum dc_color_space color_sp, 2020 enum dc_color_depth color_dpth, enum signal_type signal); 2021 2022 void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state, 2023 struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, 2024 struct clamping_and_pixel_encoding_params *clamping); 2025 2026 void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state, 2027 struct dc *dc, struct pipe_ctx *pipe_ctx); 2028 2029 void hwss_add_abm_set_level(struct block_sequence_state *seq_state, 2030 struct abm *abm, uint32_t abm_level); 2031 2032 void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state, 2033 struct timing_generator *tg); 2034 2035 void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state, 2036 struct hubp *hubp, unsigned int timeout_us, unsigned int polling_interval_us); 2037 2038 void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state, 2039 struct timing_generator *tg, unsigned int timeout_us, unsigned int polling_interval_us); 2040 2041 void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, 2042 struct dccg *dccg, int inst, int num_slices_h); 2043 2044 void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state, 2045 struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt); 2046 2047 void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state, 2048 struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove); 2049 2050 void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state, 2051 struct output_pixel_processor *opp, int mpcc_inst, bool pending); 2052 2053 void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state, 2054 struct hubp *hubp); 2055 2056 void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state, 2057 struct pipe_ctx *pipe_ctx); 2058 2059 void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state, 2060 struct display_stream_compressor *dsc); 2061 2062 void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state, 2063 struct dc *dc, bool optimized_required); 2064 2065 void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state, 2066 struct dc *dc, struct pipe_ctx *pipe_ctx); 2067 2068 void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state, 2069 struct output_pixel_processor *opp, 2070 enum controller_dp_test_pattern test_pattern, 2071 enum controller_dp_color_space color_space, 2072 enum dc_color_depth color_depth, 2073 struct tg_color solid_color, 2074 bool use_solid_color, 2075 int width, 2076 int height, 2077 int offset); 2078 2079 void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state, 2080 struct output_pixel_processor *opp, 2081 bool use_default_params, 2082 struct pipe_ctx *pipe_ctx); 2083 2084 void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state, 2085 struct dpp *dpp, 2086 struct cm_hist_control cm_hist_control, 2087 enum dc_color_space color_space); 2088 2089 void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, 2090 struct dc *dc, 2091 bool enable); 2092 2093 void hwss_add_dwbc_update(struct block_sequence_state *seq_state, 2094 struct dwbc *dwb, 2095 struct dc_dwb_params *dwb_params); 2096 2097 void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state, 2098 struct mcif_wb *mcif_wb, 2099 struct mcif_buf_params *mcif_buf_params, 2100 unsigned int dest_height); 2101 2102 void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state, 2103 struct mcif_wb *mcif_wb, 2104 struct mcif_arb_params *mcif_arb_params); 2105 2106 void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state, 2107 struct mcif_wb *mcif_wb); 2108 2109 void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state, 2110 struct mcif_wb *mcif_wb); 2111 2112 void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state, 2113 struct mpc *mpc, 2114 int dwb_id, 2115 int mpcc_id); 2116 2117 void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state, 2118 struct mpc *mpc, 2119 unsigned int dwb_id); 2120 2121 void hwss_add_dwbc_enable(struct block_sequence_state *seq_state, 2122 struct dwbc *dwb, 2123 struct dc_dwb_params *dwb_params); 2124 2125 void hwss_add_dwbc_disable(struct block_sequence_state *seq_state, 2126 struct dwbc *dwb); 2127 2128 void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state, 2129 struct timing_generator *tg, 2130 struct gsl_params gsl); 2131 2132 void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state, 2133 struct timing_generator *tg, 2134 int group_idx, 2135 uint32_t gsl_ready_signal); 2136 2137 void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state, 2138 struct hubp *hubp, 2139 uint32_t mall_sel, 2140 bool cache_cursor); 2141 2142 void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state, 2143 struct hubp *hubp, 2144 bool enable); 2145 2146 void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state, 2147 struct hubp *hubp, 2148 bool enable); 2149 2150 void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state, 2151 struct hubp *hubp, 2152 bool disable); 2153 2154 void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state, 2155 struct hubbub *hubbub, 2156 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset), 2157 bool reset); 2158 2159 void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state, 2160 struct hubp *hubp, 2161 bool enable); 2162 2163 void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, 2164 struct dpp *dpp, 2165 bool dppclk_div, 2166 bool enable); 2167 2168 void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, 2169 struct timing_generator *tg); 2170 2171 void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, 2172 struct dce_hwseq *hws, 2173 int dsc_inst, 2174 bool is_ungated); 2175 2176 void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, 2177 struct display_stream_compressor *dsc, 2178 bool *is_ungated); 2179 2180 void hwss_add_dsc_disable(struct block_sequence_state *seq_state, 2181 struct display_stream_compressor *dsc, 2182 bool *is_ungated); 2183 2184 void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, 2185 struct dccg *dccg, 2186 int dsc_inst, 2187 bool *is_ungated); 2188 2189 void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state, 2190 struct dce_hwseq *hws, 2191 unsigned int dpp_inst, 2192 bool clock_on); 2193 2194 void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state, 2195 struct dce_hwseq *hws, 2196 unsigned int dpp_inst, 2197 bool power_on); 2198 2199 void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state, 2200 struct dce_hwseq *hws, 2201 unsigned int hubp_inst, 2202 bool power_on); 2203 2204 void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state, 2205 struct hubp *hubp, 2206 bool blank); 2207 2208 void hwss_add_hubp_init(struct block_sequence_state *seq_state, 2209 struct hubp *hubp); 2210 2211 void hwss_add_hubp_reset(struct block_sequence_state *seq_state, 2212 struct hubp *hubp); 2213 2214 void hwss_add_dpp_reset(struct block_sequence_state *seq_state, 2215 struct dpp *dpp); 2216 2217 void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state, 2218 struct output_pixel_processor *opp, 2219 bool enable); 2220 2221 void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state, 2222 struct hubp *hubp, 2223 uint64_t sys_default, 2224 uint64_t sys_low, 2225 uint64_t sys_high); 2226 2227 void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state, 2228 struct hubp *hubp); 2229 2230 void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state, 2231 struct dccg *dccg, 2232 int dpp_inst, 2233 int dppclk_khz); 2234 2235 void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state, 2236 struct hubp *hubp, 2237 uint32_t otg_inst); 2238 2239 void hwss_add_hubp_setup2(struct block_sequence_state *seq_state, 2240 struct hubp *hubp, 2241 struct dml2_dchub_per_pipe_register_set *hubp_regs, 2242 union dml2_global_sync_programming *global_sync, 2243 struct dc_crtc_timing *timing); 2244 2245 void hwss_add_hubp_setup(struct block_sequence_state *seq_state, 2246 struct hubp *hubp, 2247 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 2248 struct _vcs_dpi_display_ttu_regs_st *ttu_regs, 2249 struct _vcs_dpi_display_rq_regs_st *rq_regs, 2250 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); 2251 2252 void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state, 2253 struct hubp *hubp, 2254 bool unbounded_req); 2255 2256 void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state, 2257 struct hubp *hubp, 2258 struct dml2_dchub_per_pipe_register_set *hubp_regs); 2259 2260 void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state, 2261 struct hubp *hubp, 2262 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 2263 struct _vcs_dpi_display_ttu_regs_st *ttu_regs); 2264 void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state, 2265 struct hubp *hubp, 2266 enum surface_pixel_format format, 2267 struct dc_tiling_info *tiling_info, 2268 struct plane_size plane_size, 2269 enum dc_rotation_angle rotation, 2270 struct dc_plane_dcc_param *dcc, 2271 bool horizontal_mirror, 2272 int compat_level); 2273 2274 void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, 2275 struct pipe_ctx *pipe_ctx); 2276 2277 void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state, 2278 struct dpp *dpp, 2279 enum dc_color_space color_space, 2280 struct dc_csc_transform *cursor_csc_color_matrix); 2281 2282 void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state, 2283 struct mpc *mpc, 2284 struct mpcc_blnd_cfg blnd_cfg, 2285 int mpcc_id); 2286 2287 void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state, 2288 struct mpc *mpc, 2289 int mpcc_id); 2290 2291 void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state, 2292 struct mpc *mpc, 2293 struct mpc_tree *mpc_tree_params, 2294 struct mpcc_blnd_cfg blnd_cfg, 2295 struct mpcc_sm_cfg *sm_cfg, 2296 struct mpcc *insert_above_mpcc, 2297 int dpp_id, 2298 int mpcc_id); 2299 2300 void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state, 2301 struct dpp *dpp, 2302 const struct scaler_data *scl_data); 2303 2304 void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state, 2305 struct hubp *hubp, 2306 const struct rect *viewport, 2307 const struct rect *viewport_c); 2308 2309 void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state, 2310 struct dc *dc, 2311 struct pipe_ctx *pipe_ctx); 2312 2313 void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, 2314 struct dc *dc, 2315 struct pipe_ctx *pipe_ctx); 2316 2317 void hwss_add_hubp_set_cursor_attributes(struct block_sequence_state *seq_state, 2318 struct hubp *hubp, 2319 const struct dc_cursor_attributes *attributes); 2320 2321 void hwss_add_dpp_set_cursor_attributes(struct block_sequence_state *seq_state, 2322 struct dpp *dpp, 2323 struct dc_cursor_attributes *attributes); 2324 2325 void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, 2326 struct dc *dc, 2327 struct pipe_ctx *pipe_ctx); 2328 2329 void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, 2330 struct dc *dc, 2331 struct pipe_ctx *pipe_ctx); 2332 2333 void hwss_add_program_output_csc(struct block_sequence_state *seq_state, 2334 struct dc *dc, 2335 struct pipe_ctx *pipe_ctx, 2336 enum dc_color_space colorspace, 2337 uint16_t *matrix, 2338 int opp_id); 2339 2340 void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state, 2341 struct hubp *hubp); 2342 2343 void hwss_add_update_force_pstate(struct block_sequence_state *seq_state, 2344 struct dc *dc, 2345 struct dc_state *context); 2346 2347 void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state, 2348 struct hubbub *hubbub); 2349 2350 void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state, 2351 struct hubbub *hubbub, 2352 bool allow, 2353 bool *disallow_self_refresh_applied); 2354 2355 void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, 2356 struct timing_generator *tg, 2357 unsigned int *frame_count); 2358 2359 void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state, 2360 struct timing_generator *tg, 2361 struct dsc_optc_config *dsc_optc_cfg, 2362 bool enable); 2363 2364 void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state, 2365 struct output_pixel_processor *opp, 2366 enum dc_pixel_encoding pixel_encoding, 2367 bool is_otg_master); 2368 2369 void hwss_add_hubp_enable_3dlut_fl(struct block_sequence_state *seq_state, 2370 struct hubp *hubp); 2371 2372 void hwss_add_begin_cursor_offload_update(struct block_sequence_state *seq_state, 2373 struct dc *dc, 2374 struct pipe_ctx *pipe_ctx); 2375 2376 void hwss_add_cursor_lock(struct block_sequence_state *seq_state, 2377 struct dc *dc, 2378 struct pipe_ctx *pipe_ctx, 2379 bool lock); 2380 2381 void hwss_add_send_update_cursor_info_to_dmu(struct block_sequence_state *seq_state, 2382 struct pipe_ctx *pipe_ctx, 2383 int index); 2384 2385 void hwss_add_update_cursor_offload_pipe(struct block_sequence_state *seq_state, 2386 struct dc *dc, 2387 struct pipe_ctx *pipe_ctx); 2388 2389 void hwss_add_commit_cursor_offload_update(struct block_sequence_state *seq_state, 2390 struct dc *dc, 2391 struct pipe_ctx *pipe_ctx); 2392 2393 void hwss_add_stream_enc_update_hdmi_info_packets(struct block_sequence_state *seq_state, 2394 struct pipe_ctx *pipe_ctx); 2395 2396 void hwss_add_hpo_frl_stream_enc_update_hdmi_info_packets(struct block_sequence_state *seq_state, 2397 struct pipe_ctx *pipe_ctx); 2398 2399 void hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, 2400 struct pipe_ctx *pipe_ctx); 2401 2402 void hwss_add_hpo_dp_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, 2403 struct pipe_ctx *pipe_ctx); 2404 2405 void hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, 2406 struct pipe_ctx *pipe_ctx); 2407 2408 void hwss_add_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, 2409 struct pipe_ctx *pipe_ctx); 2410 2411 void hwss_add_dsc_set_config(struct block_sequence_state *seq_state, 2412 struct display_stream_compressor *dsc, 2413 const struct dsc_config *dsc_cfg, 2414 const struct dsc_optc_config *dsc_optc_cfg); 2415 2416 void hwss_add_stream_enc_dp_set_dsc_config(struct block_sequence_state *seq_state, 2417 struct stream_encoder *stream_enc, 2418 const struct dsc_optc_config *dsc_optc_cfg); 2419 2420 void hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, 2421 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, 2422 bool immediate_update, 2423 uint8_t *dsc_packed_pps, 2424 bool pps_sdp_stream); 2425 2426 void hwss_add_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, 2427 struct stream_encoder *stream_enc, 2428 bool immediate_update, 2429 uint8_t *dsc_packed_pps, 2430 bool pps_sdp_stream); 2431 2432 void hwss_add_hpo_frl_stream_enc_set_dsc_config(struct block_sequence_state *seq_state, 2433 struct hpo_frl_stream_encoder *hpo_frl_stream_enc, 2434 const struct dc_crtc_timing *timing, 2435 uint8_t *dsc_packed_pps); 2436 2437 void hwss_add_setup_periodic_interrupt(struct block_sequence_state *seq_state, 2438 struct dc *dc, 2439 struct pipe_ctx *pipe_ctx); 2440 2441 void hwss_add_dp_trace_source_sequence(struct block_sequence_state *seq_state, 2442 struct dc_link *link, 2443 enum dpcd_source_sequence source); 2444 2445 void hwss_add_set_dmdata_attributes(struct block_sequence_state *seq_state, 2446 struct pipe_ctx *pipe_ctx); 2447 2448 void hwss_add_link_increase_mst_payload(struct block_sequence_state *seq_state, 2449 struct pipe_ctx *pipe_ctx, 2450 uint32_t mst_stream_bw); 2451 2452 void hwss_add_link_reduce_mst_payload(struct block_sequence_state *seq_state, 2453 struct pipe_ctx *pipe_ctx, 2454 uint32_t mst_stream_bw); 2455 2456 void hwss_add_dp_set_test_pattern(struct block_sequence_state *seq_state, 2457 struct dc_link *link, 2458 enum dp_test_pattern test_pattern, 2459 enum dp_test_pattern_color_space test_pattern_color_space, 2460 const struct link_training_settings *p_link_settings, 2461 const unsigned char *p_custom_pattern, 2462 unsigned int cust_pattern_size); 2463 2464 void hwss_add_link_set_dpms_off(struct block_sequence_state *seq_state, 2465 struct pipe_ctx *pipe_ctx); 2466 2467 void hwss_add_disable_audio_stream(struct block_sequence_state *seq_state, 2468 struct pipe_ctx *pipe_ctx); 2469 2470 void hwss_add_prepare_bandwidth(struct block_sequence_state *seq_state, 2471 struct dc *dc, 2472 struct dc_state *context); 2473 2474 void hwss_add_link_set_dpms_on(struct block_sequence_state *seq_state, 2475 struct dc_state *state, 2476 struct pipe_ctx *pipe_ctx); 2477 2478 #endif /* __DC_HW_SEQUENCER_H__ */ 2479